From 8d8856f22ec44012a4f937d3a8968b7dc6dd7c18 Mon Sep 17 00:00:00 2001 From: Penguin Date: Wed, 20 May 2020 06:07:02 -0500 Subject: [PATCH] . --- README.md | 2 +- electrical/same54_dev_board/BRAIN.sch | 1124 +- electrical/same54_dev_board/BRAIN.sch-bak | 1124 +- electrical/same54_dev_board/NCP349MNAETBG.dcm | 6 +- electrical/same54_dev_board/NCP349MNAETBG.lib | 44 +- electrical/same54_dev_board/Power.sch | 802 +- electrical/same54_dev_board/Power.sch-bak | 802 +- electrical/same54_dev_board/SCREEN_INTF.sch | 1312 +- .../same54_dev_board/SCREEN_INTF.sch-bak | 1312 +- electrical/same54_dev_board/USB_INTF.sch | 564 +- electrical/same54_dev_board/USB_INTF.sch-bak | 564 +- electrical/same54_dev_board/fp-info-cache | 157530 +++++++-------- electrical/same54_dev_board/fp-lib-table | 6 +- .../libraries/Conn_02x20_LCD_INTF.bck | 18 +- .../libraries/Conn_02x20_LCD_INTF.dcm | 18 +- .../libraries/Conn_02x20_LCD_INTF.lib | 198 +- .../libraries/MAX7301AAX_.dcm | 6 +- .../libraries/MAX7301AAX_.lib | 120 +- .../libraries/TPS73733QDRBRQ1.dcm | 6 +- .../libraries/TPS73733QDRBRQ1.lib | 30 +- .../SOP80P1030X264-36N.kicad_mod | 114 +- .../same54_dev_board-cache.lib | 1342 +- .../same54_dev_board.kicad_pcb | 3182 +- .../same54_dev_board.kicad_pcb-bak | 3182 +- .../same54_dev_board/same54_dev_board.pro | 86 +- .../same54_dev_board/same54_dev_board.sch | 456 +- .../same54_dev_board/same54_dev_board.sch-bak | 456 +- electrical/same54_dev_board/sym-lib-table | 12 +- software/README.md | 34 +- software/conf/project_oractle_config.atstart | 2354 +- .../.atmelstart/AtmelStart.env_conf | 12 +- .../.atmelstart/AtmelStart.gpdsc | 430 +- .../.atmelstart/atmel_start_config.atstart | 2354 +- .../Config/hpl_cmcc_config.h | 108 +- .../Config/hpl_dmac_config.h | 14554 +- .../Config/hpl_eic_config.h | 1822 +- .../Config/hpl_gclk_config.h | 1840 +- .../Config/hpl_mclk_config.h | 208 +- .../Config/hpl_osc32kctrl_config.h | 330 +- .../Config/hpl_oscctrl_config.h | 1280 +- .../Config/hpl_port_config.h | 1044 +- .../Config/hpl_sercom_config.h | 826 +- .../Config/hpl_tc_config.h | 360 +- .../Config/peripheral_clk_config.h | 514 +- .../project_oracle_test_prj/atmel_start.c | 18 +- .../project_oracle_test_prj/atmel_start.h | 36 +- .../atmel_start_pins.h | 24 +- .../project_oracle_test_prj/driver_init.c | 268 +- .../project_oracle_test_prj/driver_init.h | 108 +- .../examples/driver_examples.c | 168 +- .../examples/driver_examples.h | 52 +- .../hal/documentation/ext_irq.rst | 78 +- .../hal/documentation/i2c_master_sync.rst | 174 +- .../hal/documentation/timer.rst | 104 +- .../hal/documentation/usart_async.rst | 144 +- .../hal/include/hal_atomic.h | 240 +- .../hal/include/hal_cache.h | 192 +- .../hal/include/hal_delay.h | 178 +- .../hal/include/hal_ext_irq.h | 236 +- .../hal/include/hal_gpio.h | 402 +- .../hal/include/hal_i2c_m_sync.h | 488 +- .../hal/include/hal_init.h | 144 +- .../hal/include/hal_io.h | 220 +- .../hal/include/hal_sleep.h | 148 +- .../hal/include/hal_timer.h | 412 +- .../hal/include/hal_usart_async.h | 678 +- .../hal/include/hpl_cmcc.h | 554 +- .../hal/include/hpl_core.h | 112 +- .../hal/include/hpl_delay.h | 194 +- .../hal/include/hpl_dma.h | 352 +- .../hal/include/hpl_ext_irq.h | 190 +- .../hal/include/hpl_gpio.h | 370 +- .../hal/include/hpl_i2c_m_async.h | 410 +- .../hal/include/hpl_i2c_m_sync.h | 370 +- .../hal/include/hpl_i2c_s_async.h | 368 +- .../hal/include/hpl_i2c_s_sync.h | 368 +- .../hal/include/hpl_init.h | 248 +- .../hal/include/hpl_irq.h | 232 +- .../hal/include/hpl_missing_features.h | 74 +- .../hal/include/hpl_pwm.h | 386 +- .../hal/include/hpl_ramecc.h | 200 +- .../hal/include/hpl_reset.h | 186 +- .../hal/include/hpl_sleep.h | 176 +- .../hal/include/hpl_spi.h | 326 +- .../hal/include/hpl_spi_async.h | 262 +- .../hal/include/hpl_spi_m_async.h | 486 +- .../hal/include/hpl_spi_m_dma.h | 364 +- .../hal/include/hpl_spi_m_sync.h | 332 +- .../hal/include/hpl_spi_s_async.h | 464 +- .../hal/include/hpl_spi_s_sync.h | 464 +- .../hal/include/hpl_spi_sync.h | 140 +- .../hal/include/hpl_timer.h | 320 +- .../hal/include/hpl_usart.h | 226 +- .../hal/include/hpl_usart_async.h | 540 +- .../hal/include/hpl_usart_sync.h | 508 +- .../hal/src/hal_atomic.c | 132 +- .../hal/src/hal_cache.c | 156 +- .../hal/src/hal_delay.c | 160 +- .../hal/src/hal_ext_irq.c | 376 +- .../hal/src/hal_gpio.c | 88 +- .../hal/src/hal_i2c_m_sync.c | 516 +- .../hal/src/hal_init.c | 94 +- .../project_oracle_test_prj/hal/src/hal_io.c | 126 +- .../hal/src/hal_sleep.c | 146 +- .../hal/src/hal_timer.c | 500 +- .../hal/src/hal_usart_async.c | 840 +- .../hal/utils/include/compiler.h | 128 +- .../hal/utils/include/err_codes.h | 146 +- .../hal/utils/include/events.h | 108 +- .../hal/utils/include/parts.h | 82 +- .../hal/utils/include/utils.h | 736 +- .../hal/utils/include/utils_assert.h | 186 +- .../hal/utils/include/utils_event.h | 230 +- .../hal/utils/include/utils_increment_macro.h | 616 +- .../hal/utils/include/utils_list.h | 328 +- .../hal/utils/include/utils_repeat_macro.h | 644 +- .../hal/utils/include/utils_ringbuffer.h | 232 +- .../hal/utils/src/utils_assert.c | 92 +- .../hal/utils/src/utils_event.c | 250 +- .../hal/utils/src/utils_list.c | 272 +- .../hal/utils/src/utils_ringbuffer.c | 236 +- .../hal/utils/src/utils_syscalls.c | 304 +- .../hpl/cmcc/hpl_cmcc.c | 708 +- .../hpl/core/hpl_core_m4.c | 482 +- .../hpl/core/hpl_core_port.h | 122 +- .../hpl/core/hpl_init.c | 156 +- .../hpl/dmac/hpl_dmac.c | 526 +- .../project_oracle_test_prj/hpl/eic/hpl_eic.c | 516 +- .../hpl/gclk/hpl_gclk.c | 624 +- .../hpl/gclk/hpl_gclk_base.h | 174 +- .../hpl/mclk/hpl_mclk.c | 88 +- .../hpl/osc32kctrl/hpl_osc32kctrl.c | 164 +- .../hpl/oscctrl/hpl_oscctrl.c | 460 +- .../project_oracle_test_prj/hpl/pm/hpl_pm.c | 136 +- .../hpl/pm/hpl_pm_base.h | 90 +- .../hpl/port/hpl_gpio_base.h | 344 +- .../hpl/ramecc/hpl_ramecc.c | 166 +- .../hpl/sercom/hpl_sercom.c | 6050 +- .../project_oracle_test_prj/hpl/tc/hpl_tc.c | 694 +- .../hpl/tc/hpl_tc_base.h | 154 +- .../project_oracle_test_prj/hri/hri_ac_e54.h | 3672 +- .../project_oracle_test_prj/hri/hri_adc_e54.h | 7326 +- .../project_oracle_test_prj/hri/hri_aes_e54.h | 2574 +- .../project_oracle_test_prj/hri/hri_can_e54.h | 33994 ++-- .../project_oracle_test_prj/hri/hri_ccl_e54.h | 1552 +- .../hri/hri_cmcc_e54.h | 722 +- .../project_oracle_test_prj/hri/hri_dac_e54.h | 3412 +- .../hri/hri_dmac_e54.h | 13600 +- .../project_oracle_test_prj/hri/hri_dsu_e54.h | 2512 +- .../project_oracle_test_prj/hri/hri_e54.h | 152 +- .../project_oracle_test_prj/hri/hri_eic_e54.h | 3676 +- .../hri/hri_evsys_e54.h | 3414 +- .../hri/hri_freqm_e54.h | 928 +- .../hri/hri_gclk_e54.h | 1610 +- .../hri/hri_gmac_e54.h | 7532 +- .../hri/hri_hmatrixb_e54.h | 474 +- .../project_oracle_test_prj/hri/hri_i2s_e54.h | 6064 +- .../project_oracle_test_prj/hri/hri_icm_e54.h | 1522 +- .../hri/hri_mclk_e54.h | 7112 +- .../hri/hri_nvmctrl_e54.h | 3236 +- .../hri/hri_osc32kctrl_e54.h | 2398 +- .../hri/hri_oscctrl_e54.h | 8882 +- .../project_oracle_test_prj/hri/hri_pac_e54.h | 3028 +- .../project_oracle_test_prj/hri/hri_pcc_e54.h | 596 +- .../hri/hri_pdec_e54.h | 5368 +- .../project_oracle_test_prj/hri/hri_pm_e54.h | 1640 +- .../hri/hri_port_e54.h | 5056 +- .../hri/hri_qspi_e54.h | 4116 +- .../hri/hri_ramecc_e54.h | 724 +- .../hri/hri_rstc_e54.h | 284 +- .../project_oracle_test_prj/hri/hri_rtc_e54.h | 20278 +- .../hri/hri_sdhc_e54.h | 14954 +- .../hri/hri_sercom_e54.h | 17784 +- .../hri/hri_supc_e54.h | 3538 +- .../project_oracle_test_prj/hri/hri_tc_e54.h | 6006 +- .../project_oracle_test_prj/hri/hri_tcc_e54.h | 19984 +- .../hri/hri_trng_e54.h | 760 +- .../project_oracle_test_prj/hri/hri_usb_e54.h | 18670 +- .../project_oracle_test_prj/hri/hri_wdt_e54.h | 1234 +- .../project_oracle_test_prj/main.c | 12 +- 180 files changed, 237998 insertions(+), 237998 deletions(-) diff --git a/README.md b/README.md index f7c6ee5..f6da4ce 100644 --- a/README.md +++ b/README.md @@ -1 +1 @@ -# Embedded-Graphics-Learning +# Embedded-Graphics-Learning diff --git a/electrical/same54_dev_board/BRAIN.sch b/electrical/same54_dev_board/BRAIN.sch index 0bb6d69..2f4bcef 100644 --- a/electrical/same54_dev_board/BRAIN.sch +++ b/electrical/same54_dev_board/BRAIN.sch @@ -1,562 +1,562 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 5 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 2 1 5E82C3BA -P 6800 1600 -F 0 "U1" H 6908 2665 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 6908 2574 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 5600 2850 50 0001 C CNN -F 3 "" H 5600 2850 50 0001 C CNN - 2 6800 1600 - 1 0 0 -1 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 3 1 5E82DE73 -P 8950 1650 -F 0 "U1" H 9058 2665 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 9058 2574 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 7750 2900 50 0001 C CNN -F 3 "" H 7750 2900 50 0001 C CNN - 3 8950 1650 - 1 0 0 -1 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 4 1 5E8352A8 -P 10250 1800 -F 0 "U1" H 10358 2865 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 10358 2774 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 9050 3050 50 0001 C CNN -F 3 "" H 9050 3050 50 0001 C CNN - 4 10250 1800 - 1 0 0 -1 -$EndComp -$Comp -L Connector:Conn_ARM_JTAG_SWD_10 J2 -U 1 1 5EA1E350 -P 4400 5700 -F 0 "J2" H 3957 5746 50 0000 R CNN -F 1 "Conn_ARM_JTAG_SWD_10" H 3957 5655 50 0000 R CNN -F 2 "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical" H 4400 5700 50 0001 C CNN -F 3 "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/DDI0314H_coresight_components_trm.pdf" V 4050 4450 50 0001 C CNN - 1 4400 5700 - 1 0 0 -1 -$EndComp -Wire Notes Line - 7200 4200 11150 4200 -Wire Notes Line - 11150 4200 11150 6450 -Wire Notes Line - 11150 6450 7200 6450 -Wire Notes Line - 7200 6450 7200 4200 -Text Notes 7250 5100 0 50 ~ 0 -Brain -- aka ATSAME54P20A_AU\n - 120Mhz Core Clock\n - 32khz External Clock (for startup)\n - 12(?)Mhz Alt Clock (probably unused, but adding it just in case)\n - 3 Sercoms\n - 1 I2C\n - 1 SPI\n - 1 U(S)ART\n - Interfaces with IO Extender for parallel bus control without sacrificing pins\n - The E54 has a shitty pin set for parallel control (not bc of no. of pins, but \nbecause of positions and default pin functions) -$Comp -L Device:Crystal Y1 -U 1 1 5E75D825 -P 5000 1300 -F 0 "Y1" V 5046 1169 50 0000 R CNN -F 1 "XOSC32" V 4955 1169 50 0000 R CNN -F 2 "Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm" H 5000 1300 50 0001 C CNN -F 3 "~" H 5000 1300 50 0001 C CNN - 1 5000 1300 - 0 -1 -1 0 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 1 1 5E82A2F6 -P 3650 2000 -F 0 "U1" H 3733 3165 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 3733 3074 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 2450 3250 50 0001 C CNN -F 3 "" H 2450 3250 50 0001 C CNN - 1 3650 2000 - 1 0 0 -1 -$EndComp -$Comp -L Device:C_Small C1 -U 1 1 5E7E5146 -P 5100 1050 -F 0 "C1" V 4871 1050 50 0000 C CNN -F 1 "6.8pF" V 4962 1050 50 0000 C CNN -F 2 "" H 5100 1050 50 0001 C CNN -F 3 "~" H 5100 1050 50 0001 C CNN - 1 5100 1050 - 0 1 1 0 -$EndComp -$Comp -L Device:C_Small C2 -U 1 1 5E7E6123 -P 5100 1550 -F 0 "C2" V 4871 1550 50 0000 C CNN -F 1 "6.8pF" V 4950 1500 50 0000 C CNN -F 2 "" H 5100 1550 50 0001 C CNN -F 3 "~" H 5100 1550 50 0001 C CNN - 1 5100 1550 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 4800 1350 4250 1350 -Wire Wire Line - 4800 1250 4250 1250 -Wire Wire Line - 5000 1050 5000 1150 -Wire Wire Line - 5000 1550 5000 1450 -Wire Wire Line - 4800 1550 5000 1550 -Wire Wire Line - 4800 1350 4800 1550 -Connection ~ 5000 1550 -Wire Wire Line - 4800 1050 5000 1050 -Wire Wire Line - 4800 1050 4800 1250 -Connection ~ 5000 1050 -Wire Wire Line - 5200 1050 5450 1050 -Wire Wire Line - 5450 1050 5450 1300 -Wire Wire Line - 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-I2C0_SCL -Text Notes 3200 2950 0 50 ~ 0 -SERCOM1 (I2C) -Wire Notes Line - 4050 2800 3200 2800 -Wire Notes Line - 3200 2800 3200 3000 -Wire Notes Line - 3200 3000 4050 3000 -Wire Notes Line - 4050 3000 4050 2800 -Wire Wire Line - 4900 5400 5000 5400 -Text HLabel 1000 1250 0 50 Input ~ 0 -~SYS_RST -Wire Notes Line - 550 1300 1700 1300 -Wire Notes Line - 1700 600 1700 1300 -Wire Notes Line - 550 600 550 1300 -Text Label 1250 1250 0 50 ~ 0 -~BRAIN_RST -Wire Wire Line - 1000 1250 1250 1250 -Wire Wire Line - 4900 5600 5000 5600 -Text Label 5000 5600 0 50 ~ 0 -SWCLK -Wire Wire Line - 4900 5700 5000 5700 -Text Label 5000 5700 0 50 ~ 0 -SWDIO -Text Label 5000 5800 0 50 ~ 0 -SWO -Wire Wire Line - 4900 5800 5000 5800 -Wire Wire Line - 4300 6300 4400 6300 -NoConn ~ 4900 5900 -Text Label 5000 5400 0 50 ~ 0 -~SWRST -Wire Wire Line - 4400 6300 4400 6350 -Connection ~ 4400 6300 -$Comp -L power:GND #PWR0119 -U 1 1 5EA9AF4B -P 4400 6350 -F 0 "#PWR0119" H 4400 6100 50 0001 C CNN -F 1 "GND" H 4405 6177 50 0000 C CNN -F 2 "" H 4400 6350 50 0001 C CNN -F 3 "" H 4400 6350 50 0001 C CNN - 1 4400 6350 - 1 0 0 -1 -$EndComp -Text Label 1550 3600 0 50 ~ 0 -~TFT_WR -Text Label 1900 5050 0 50 ~ 0 -I2C0_SCL -Text Label 1900 4600 0 50 ~ 0 -I2C0_SDA -Text HLabel 1300 5050 0 50 Input ~ 0 -MASTER_I2C_SCL -Text HLabel 1300 4600 0 50 Input ~ 0 -MASTER_I2C_SDA -$Comp -L Device:R_Small R4 -U 1 1 5EB11658 -P 1450 4450 -F 0 "R4" H 1509 4496 50 0000 L CNN -F 1 "4.7k" H 1509 4405 50 0000 L CNN -F 2 "" H 1450 4450 50 0001 C CNN -F 3 "~" H 1450 4450 50 0001 C CNN - 1 1450 4450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1450 4350 1450 4300 -Text Label 1450 4300 0 50 ~ 0 -3v3 -$Comp -L Device:R_Small R5 -U 1 1 5EB38D15 -P 1450 4900 -F 0 "R5" H 1509 4946 50 0000 L CNN -F 1 "4.7k" H 1509 4855 50 0000 L CNN -F 2 "" H 1450 4900 50 0001 C CNN -F 3 "~" H 1450 4900 50 0001 C CNN - 1 1450 4900 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1300 5050 1450 5050 -Wire Wire Line - 1300 4600 1450 4600 -Wire Wire Line - 1450 4600 1450 4550 -Connection ~ 1450 4600 -Wire Wire Line - 1450 4600 1900 4600 -Wire Wire Line - 1450 5050 1450 5000 -Connection ~ 1450 5050 -Wire Wire Line - 1450 4800 1450 4750 -Text Label 1450 4750 0 50 ~ 0 -3v3 -Wire Wire Line - 1450 5050 1900 5050 -Text Label 850 7150 2 50 ~ 0 -~SWRST -Wire Wire Line - 850 7150 1250 7150 -Text Label 1250 7150 0 50 ~ 0 -~BRAIN_RST -Text Notes 600 7000 0 50 ~ 0 -Locals -Text HLabel 1050 5200 0 50 Input ~ 0 -EXT_IRQ_0 -Text HLabel 1050 5300 0 50 Input ~ 0 -EXT_IRQ_1 -Text HLabel 1050 5400 0 50 Input ~ 0 -EXT_IRQ_2 -Text HLabel 1050 5500 0 50 Input ~ 0 -EXT_IRQ_3 -Text HLabel 1050 5600 0 50 Input ~ 0 -EXT_IRQ_4 -Text HLabel 1050 5700 0 50 Input ~ 0 -EXT_IRQ_5 -Wire Wire Line - 1050 5200 1300 5200 -Text Label 1300 5200 0 50 ~ 0 -EXT_IRQ_0 -Wire Wire Line - 1050 5300 1300 5300 -Text Label 1300 5300 0 50 ~ 0 -EXT_IRQ_1 -Wire Wire Line - 1050 5400 1300 5400 -Text Label 1300 5400 0 50 ~ 0 -EXT_IRQ_2 -Wire Wire Line - 1050 5500 1300 5500 -Text Label 1300 5500 0 50 ~ 0 -EXT_IRQ_3 -Wire Wire Line - 1050 5600 1300 5600 -Text Label 1300 5600 0 50 ~ 0 -EXT_IRQ_4 -Wire Wire Line - 1050 5700 1300 5700 -Text Label 1300 5700 0 50 ~ 0 -EXT_IRQ_5 -Text Label 7700 950 0 50 ~ 0 -EXT_IRQ_0 -Wire Wire Line - 7500 950 7700 950 -Text Label 7700 1050 0 50 ~ 0 -EXT_IRQ_1 -Wire Wire Line - 7500 1050 7700 1050 -Text Label 7700 1150 0 50 ~ 0 -EXT_IRQ_2 -Wire Wire Line - 7500 1150 7700 1150 -Wire Wire Line - 7500 1450 7700 1450 -Text Label 7700 1450 0 50 ~ 0 -EXT_IRQ_4 -Wire Wire Line - 7500 1350 7700 1350 -Text Label 7700 1350 0 50 ~ 0 -EXT_IRQ_3 -Wire Wire Line - 7500 1550 7700 1550 -Text Label 7700 1550 0 50 ~ 0 -EXT_IRQ_5 -Wire Notes Line - 2350 5750 550 5750 -Wire Notes Line - 550 1850 550 5750 -Wire Notes Line - 2350 1850 2350 5750 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 5 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 2 1 5E82C3BA +P 6800 1600 +F 0 "U1" H 6908 2665 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 6908 2574 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 5600 2850 50 0001 C CNN +F 3 "" H 5600 2850 50 0001 C CNN + 2 6800 1600 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 3 1 5E82DE73 +P 8950 1650 +F 0 "U1" H 9058 2665 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 9058 2574 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 7750 2900 50 0001 C CNN +F 3 "" H 7750 2900 50 0001 C CNN + 3 8950 1650 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 4 1 5E8352A8 +P 10250 1800 +F 0 "U1" H 10358 2865 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 10358 2774 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 9050 3050 50 0001 C CNN +F 3 "" H 9050 3050 50 0001 C CNN + 4 10250 1800 + 1 0 0 -1 +$EndComp +$Comp +L Connector:Conn_ARM_JTAG_SWD_10 J2 +U 1 1 5EA1E350 +P 4400 5700 +F 0 "J2" H 3957 5746 50 0000 R CNN +F 1 "Conn_ARM_JTAG_SWD_10" H 3957 5655 50 0000 R CNN +F 2 "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical" H 4400 5700 50 0001 C CNN +F 3 "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/DDI0314H_coresight_components_trm.pdf" V 4050 4450 50 0001 C CNN + 1 4400 5700 + 1 0 0 -1 +$EndComp +Wire Notes Line + 7200 4200 11150 4200 +Wire Notes Line + 11150 4200 11150 6450 +Wire Notes Line + 11150 6450 7200 6450 +Wire Notes Line + 7200 6450 7200 4200 +Text Notes 7250 5100 0 50 ~ 0 +Brain -- aka ATSAME54P20A_AU\n - 120Mhz Core Clock\n - 32khz External Clock (for startup)\n - 12(?)Mhz Alt Clock (probably unused, but adding it just in case)\n - 3 Sercoms\n - 1 I2C\n - 1 SPI\n - 1 U(S)ART\n - Interfaces with IO Extender for parallel bus control without sacrificing pins\n - The E54 has a shitty pin set for parallel control (not bc of no. of pins, but \nbecause of positions and default pin functions) +$Comp +L Device:Crystal Y1 +U 1 1 5E75D825 +P 5000 1300 +F 0 "Y1" V 5046 1169 50 0000 R CNN +F 1 "XOSC32" V 4955 1169 50 0000 R CNN +F 2 "Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm" H 5000 1300 50 0001 C CNN +F 3 "~" H 5000 1300 50 0001 C CNN + 1 5000 1300 + 0 -1 -1 0 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 1 1 5E82A2F6 +P 3650 2000 +F 0 "U1" H 3733 3165 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 3733 3074 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 2450 3250 50 0001 C CNN +F 3 "" H 2450 3250 50 0001 C CNN + 1 3650 2000 + 1 0 0 -1 +$EndComp +$Comp +L Device:C_Small C1 +U 1 1 5E7E5146 +P 5100 1050 +F 0 "C1" V 4871 1050 50 0000 C CNN +F 1 "6.8pF" V 4962 1050 50 0000 C CNN +F 2 "" H 5100 1050 50 0001 C CNN +F 3 "~" H 5100 1050 50 0001 C CNN + 1 5100 1050 + 0 1 1 0 +$EndComp +$Comp +L Device:C_Small C2 +U 1 1 5E7E6123 +P 5100 1550 +F 0 "C2" V 4871 1550 50 0000 C CNN +F 1 "6.8pF" V 4950 1500 50 0000 C CNN +F 2 "" H 5100 1550 50 0001 C CNN +F 3 "~" H 5100 1550 50 0001 C CNN + 1 5100 1550 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4800 1350 4250 1350 +Wire Wire Line + 4800 1250 4250 1250 +Wire Wire Line + 5000 1050 5000 1150 +Wire Wire Line + 5000 1550 5000 1450 +Wire Wire Line + 4800 1550 5000 1550 +Wire Wire Line + 4800 1350 4800 1550 +Connection ~ 5000 1550 +Wire Wire Line + 4800 1050 5000 1050 +Wire Wire Line + 4800 1050 4800 1250 +Connection ~ 5000 1050 +Wire Wire Line + 5200 1050 5450 1050 +Wire Wire Line + 5450 1050 5450 1300 +Wire Wire Line + 5450 1550 5200 1550 +Wire Wire Line + 5450 1300 5550 1300 +Connection ~ 5450 1300 +Wire Wire Line + 5450 1300 5450 1550 +$Comp +L power:GND #PWR0104 +U 1 1 5E825E8D +P 5550 1300 +F 0 "#PWR0104" H 5550 1050 50 0001 C CNN +F 1 "GND" H 5555 1127 50 0000 C CNN +F 2 "" H 5550 1300 50 0001 C CNN +F 3 "" H 5550 1300 50 0001 C CNN + 1 5550 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2700 5900 2850 +Connection ~ 5350 2700 +$Comp +L power:GND #PWR0108 +U 1 1 5E880A2C +P 5900 2850 +F 0 "#PWR0108" H 5900 2600 50 0001 C CNN +F 1 "GND" H 5905 2677 50 0000 C CNN +F 2 "" H 5900 2850 50 0001 C CNN +F 3 "" H 5900 2850 50 0001 C CNN + 1 5900 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 2550 5150 2500 +Wire Wire Line + 5150 2500 4900 2500 +Wire Wire Line + 4900 2500 4900 2650 +Wire Wire Line + 4900 2650 4250 2650 +Wire Wire Line + 5150 2850 5150 2900 +Wire Wire Line + 5150 2900 4900 2900 +Wire Wire Line + 4900 2900 4900 2750 +Wire Wire Line + 4900 2750 4250 2750 +$Comp +L Device:C_Small C5 +U 1 1 5E8AA0A3 +P 5250 3050 +F 0 "C5" V 5450 3050 50 0000 C CNN +F 1 "5pF" V 5350 3050 50 0000 C CNN +F 2 "" H 5250 3050 50 0001 C CNN +F 3 "~" H 5250 3050 50 0001 C CNN + 1 5250 3050 + 0 1 1 0 +$EndComp +Wire Wire Line + 5350 2700 4950 2700 +$Comp +L Device:Crystal_GND24 Y2 +U 1 1 5E843969 +P 5150 2700 +F 0 "Y2" V 5100 3050 50 0000 R CNN +F 1 "XOSC0" V 5000 3200 50 0000 R CNN +F 2 "" H 5150 2700 50 0001 C CNN +F 3 "~" H 5150 2700 50 0001 C CNN + 1 5150 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 5150 3050 5150 2900 +Connection ~ 5150 2900 +$Comp +L Device:C_Small C4 +U 1 1 5E8C2D5D +P 5250 2350 +F 0 "C4" V 5021 2350 50 0000 C CNN +F 1 "5pF" V 5112 2350 50 0000 C CNN +F 2 "" H 5250 2350 50 0001 C CNN +F 3 "~" H 5250 2350 50 0001 C CNN + 1 5250 2350 + 0 1 1 0 +$EndComp +Wire Wire Line + 5150 2500 5150 2350 +Connection ~ 5150 2500 +Wire Wire Line + 5350 2700 5900 2700 +Wire Wire Line + 5350 2350 5350 2700 +Wire Wire Line + 5350 3050 5350 2700 +Text GLabel 900 800 0 50 Input ~ 0 +g_3v3 +Text GLabel 850 950 0 50 Input ~ 0 +g_5v +Text Label 1500 800 0 50 ~ 0 +3v3 +Text Label 1500 950 0 50 ~ 0 +5v +Text HLabel 1100 2100 0 50 Input ~ 0 +DEBUG_TX +Text HLabel 1100 2250 0 50 Input ~ 0 +DEBUG_RX +Text Label 1550 2100 0 50 ~ 0 +UART0_TX +Text Label 1550 2250 0 50 ~ 0 +UART0_RX +Text HLabel 1350 2400 0 50 Input ~ 0 +MASTER_SPI_MOSI +Text HLabel 1350 2550 0 50 Input ~ 0 +MASTER_SPI_MISO +Text HLabel 1300 2700 0 50 Input ~ 0 +MASTER_SPI_CLK +Text HLabel 1100 2850 0 50 Input ~ 0 +~TFT_CS +Text HLabel 1250 3000 0 50 Input ~ 0 +~FLASH_MEM_CS +Wire Wire Line + 1350 2400 1550 2400 +Wire Wire Line + 1350 2550 1550 2550 +Wire Wire Line + 1300 2700 1550 2700 +Wire Wire Line + 1100 2850 1550 2850 +Wire Wire Line + 1250 3000 1550 3000 +Text HLabel 1350 3150 0 50 Input ~ 0 +~IO_EXPANDER_CS +Wire Wire Line + 1350 3150 1550 3150 +Wire Wire Line + 1100 2100 1550 2100 +Wire Wire Line + 1100 2250 1550 2250 +Wire Wire Line + 900 800 1500 800 +Wire Wire Line + 850 950 1500 950 +Text Notes 600 700 0 50 ~ 0 +Power Interface +Wire Notes Line + 550 600 1700 600 +Text Notes 650 1950 0 50 ~ 0 +Brain Interface +Wire Notes Line + 2350 1850 550 1850 +Text Label 1550 2400 0 50 ~ 0 +SPI0_MOSI +Text Label 1550 2550 0 50 ~ 0 +SPI0_MISO +Text Label 1550 2700 0 50 ~ 0 +SPI0_CLK +Text Label 1550 2850 0 50 ~ 0 +SPI0_CS0 +Text Label 1550 3000 0 50 ~ 0 +SPI0_CS1 +Text Label 1550 3150 0 50 ~ 0 +SPI0_CS2 +Text Label 7550 1250 0 50 ~ 0 +VBAT +Wire Wire Line + 800 1150 1500 1150 +Text Label 800 1150 2 50 ~ 0 +3v3 +Text Label 1500 1150 0 50 ~ 0 +VBAT +Wire Wire Line + 7500 1250 7550 1250 +Text HLabel 1100 3600 0 50 Input ~ 0 +~TFT_WR +Text HLabel 1100 3700 0 50 Input ~ 0 +~TFT_RD +Text HLabel 1100 3800 0 50 Input ~ 0 +TFT_RSDC +Wire Wire Line + 1100 3600 1550 3600 +Wire Wire Line + 1100 3700 1550 3700 +Wire Wire Line + 1100 3800 1550 3800 +Text Label 1550 3700 0 50 ~ 0 +~TFT_RD +Text Label 1550 3800 0 50 ~ 0 +TFT_RSDC +Text HLabel 1100 3900 0 50 Input ~ 0 +~TFT_RST +Wire Wire Line + 1100 3900 1550 3900 +Text Label 1550 3900 0 50 ~ 0 +~TFT_RST +Wire Wire Line + 4250 1850 4350 1850 +Wire Wire Line + 4250 1750 4350 1750 +Wire Wire Line + 4250 1650 4350 1650 +Text Label 4350 1750 0 50 ~ 0 +SPI0_CLK +Text Label 4350 1850 0 50 ~ 0 +SPI0_MISO +Text Label 4350 1650 0 50 ~ 0 +SPI0_MISO +Wire Wire Line + 7500 3350 7600 3350 +Wire Wire Line + 7500 3450 7600 3450 +Text Label 7600 3450 0 50 ~ 0 +UART0_TX +Text Label 7600 3350 0 50 ~ 0 +UART0_RX +Text Notes 6350 3450 0 50 ~ 0 +SERCOM2 (USART) +Wire Notes Line + 6300 3500 7300 3500 +Wire Notes Line + 7300 3500 7300 3300 +Wire Notes Line + 6300 3300 7300 3300 +Wire Notes Line + 6300 3300 6300 3500 +Wire Notes Line + 4050 1600 3200 1600 +Wire Notes Line + 3200 1600 3200 1900 +Wire Notes Line + 3200 1900 4050 1900 +Wire Notes Line + 4050 1900 4050 1600 +Text Notes 3200 1800 0 50 ~ 0 +SERCOM0 (SPI) +Wire Wire Line + 4250 2850 4350 2850 +Wire Wire Line + 4250 2950 4350 2950 +Text Label 4350 2850 0 50 ~ 0 +I2C0_SDA +Text Label 4350 2950 0 50 ~ 0 +I2C0_SCL +Text Notes 3200 2950 0 50 ~ 0 +SERCOM1 (I2C) +Wire Notes Line + 4050 2800 3200 2800 +Wire Notes Line + 3200 2800 3200 3000 +Wire Notes Line + 3200 3000 4050 3000 +Wire Notes Line + 4050 3000 4050 2800 +Wire Wire Line + 4900 5400 5000 5400 +Text HLabel 1000 1250 0 50 Input ~ 0 +~SYS_RST +Wire Notes Line + 550 1300 1700 1300 +Wire Notes Line + 1700 600 1700 1300 +Wire Notes Line + 550 600 550 1300 +Text Label 1250 1250 0 50 ~ 0 +~BRAIN_RST +Wire Wire Line + 1000 1250 1250 1250 +Wire Wire Line + 4900 5600 5000 5600 +Text Label 5000 5600 0 50 ~ 0 +SWCLK +Wire Wire Line + 4900 5700 5000 5700 +Text Label 5000 5700 0 50 ~ 0 +SWDIO +Text Label 5000 5800 0 50 ~ 0 +SWO +Wire Wire Line + 4900 5800 5000 5800 +Wire Wire Line + 4300 6300 4400 6300 +NoConn ~ 4900 5900 +Text Label 5000 5400 0 50 ~ 0 +~SWRST +Wire Wire Line + 4400 6300 4400 6350 +Connection ~ 4400 6300 +$Comp +L power:GND #PWR0119 +U 1 1 5EA9AF4B +P 4400 6350 +F 0 "#PWR0119" H 4400 6100 50 0001 C CNN +F 1 "GND" H 4405 6177 50 0000 C CNN +F 2 "" H 4400 6350 50 0001 C CNN +F 3 "" H 4400 6350 50 0001 C CNN + 1 4400 6350 + 1 0 0 -1 +$EndComp +Text Label 1550 3600 0 50 ~ 0 +~TFT_WR +Text Label 1900 5050 0 50 ~ 0 +I2C0_SCL +Text Label 1900 4600 0 50 ~ 0 +I2C0_SDA +Text HLabel 1300 5050 0 50 Input ~ 0 +MASTER_I2C_SCL +Text HLabel 1300 4600 0 50 Input ~ 0 +MASTER_I2C_SDA +$Comp +L Device:R_Small R4 +U 1 1 5EB11658 +P 1450 4450 +F 0 "R4" H 1509 4496 50 0000 L CNN +F 1 "4.7k" H 1509 4405 50 0000 L CNN +F 2 "" H 1450 4450 50 0001 C CNN +F 3 "~" H 1450 4450 50 0001 C CNN + 1 1450 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1450 4350 1450 4300 +Text Label 1450 4300 0 50 ~ 0 +3v3 +$Comp +L Device:R_Small R5 +U 1 1 5EB38D15 +P 1450 4900 +F 0 "R5" H 1509 4946 50 0000 L CNN +F 1 "4.7k" H 1509 4855 50 0000 L CNN +F 2 "" H 1450 4900 50 0001 C CNN +F 3 "~" H 1450 4900 50 0001 C CNN + 1 1450 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 5050 1450 5050 +Wire Wire Line + 1300 4600 1450 4600 +Wire Wire Line + 1450 4600 1450 4550 +Connection ~ 1450 4600 +Wire Wire Line + 1450 4600 1900 4600 +Wire Wire Line + 1450 5050 1450 5000 +Connection ~ 1450 5050 +Wire Wire Line + 1450 4800 1450 4750 +Text Label 1450 4750 0 50 ~ 0 +3v3 +Wire Wire Line + 1450 5050 1900 5050 +Text Label 850 7150 2 50 ~ 0 +~SWRST +Wire Wire Line + 850 7150 1250 7150 +Text Label 1250 7150 0 50 ~ 0 +~BRAIN_RST +Text Notes 600 7000 0 50 ~ 0 +Locals +Text HLabel 1050 5200 0 50 Input ~ 0 +EXT_IRQ_0 +Text HLabel 1050 5300 0 50 Input ~ 0 +EXT_IRQ_1 +Text HLabel 1050 5400 0 50 Input ~ 0 +EXT_IRQ_2 +Text HLabel 1050 5500 0 50 Input ~ 0 +EXT_IRQ_3 +Text HLabel 1050 5600 0 50 Input ~ 0 +EXT_IRQ_4 +Text HLabel 1050 5700 0 50 Input ~ 0 +EXT_IRQ_5 +Wire Wire Line + 1050 5200 1300 5200 +Text Label 1300 5200 0 50 ~ 0 +EXT_IRQ_0 +Wire Wire Line + 1050 5300 1300 5300 +Text Label 1300 5300 0 50 ~ 0 +EXT_IRQ_1 +Wire Wire Line + 1050 5400 1300 5400 +Text Label 1300 5400 0 50 ~ 0 +EXT_IRQ_2 +Wire Wire Line + 1050 5500 1300 5500 +Text Label 1300 5500 0 50 ~ 0 +EXT_IRQ_3 +Wire Wire Line + 1050 5600 1300 5600 +Text Label 1300 5600 0 50 ~ 0 +EXT_IRQ_4 +Wire Wire Line + 1050 5700 1300 5700 +Text Label 1300 5700 0 50 ~ 0 +EXT_IRQ_5 +Text Label 7700 950 0 50 ~ 0 +EXT_IRQ_0 +Wire Wire Line + 7500 950 7700 950 +Text Label 7700 1050 0 50 ~ 0 +EXT_IRQ_1 +Wire Wire Line + 7500 1050 7700 1050 +Text Label 7700 1150 0 50 ~ 0 +EXT_IRQ_2 +Wire Wire Line + 7500 1150 7700 1150 +Wire Wire Line + 7500 1450 7700 1450 +Text Label 7700 1450 0 50 ~ 0 +EXT_IRQ_4 +Wire Wire Line + 7500 1350 7700 1350 +Text Label 7700 1350 0 50 ~ 0 +EXT_IRQ_3 +Wire Wire Line + 7500 1550 7700 1550 +Text Label 7700 1550 0 50 ~ 0 +EXT_IRQ_5 +Wire Notes Line + 2350 5750 550 5750 +Wire Notes Line + 550 1850 550 5750 +Wire Notes Line + 2350 1850 2350 5750 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/BRAIN.sch-bak b/electrical/same54_dev_board/BRAIN.sch-bak index fa4ac14..f0fd3c9 100644 --- a/electrical/same54_dev_board/BRAIN.sch-bak +++ b/electrical/same54_dev_board/BRAIN.sch-bak @@ -1,562 +1,562 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 5 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 2 1 5E82C3BA -P 6800 1600 -F 0 "U1" H 6908 2665 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 6908 2574 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 5600 2850 50 0001 C CNN -F 3 "" H 5600 2850 50 0001 C CNN - 2 6800 1600 - 1 0 0 -1 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 3 1 5E82DE73 -P 8950 1650 -F 0 "U1" H 9058 2665 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 9058 2574 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 7750 2900 50 0001 C CNN -F 3 "" H 7750 2900 50 0001 C CNN - 3 8950 1650 - 1 0 0 -1 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 4 1 5E8352A8 -P 10250 1800 -F 0 "U1" H 10358 2865 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 10358 2774 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 9050 3050 50 0001 C CNN -F 3 "" H 9050 3050 50 0001 C CNN - 4 10250 1800 - 1 0 0 -1 -$EndComp -$Comp -L Connector:Conn_ARM_JTAG_SWD_10 J2 -U 1 1 5EA1E350 -P 4400 5700 -F 0 "J2" H 3957 5746 50 0000 R CNN -F 1 "Conn_ARM_JTAG_SWD_10" H 3957 5655 50 0000 R CNN -F 2 "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical" H 4400 5700 50 0001 C CNN -F 3 "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/DDI0314H_coresight_components_trm.pdf" V 4050 4450 50 0001 C CNN - 1 4400 5700 - 1 0 0 -1 -$EndComp -Wire Notes Line - 7200 4200 11150 4200 -Wire Notes Line - 11150 4200 11150 6450 -Wire Notes Line - 11150 6450 7200 6450 -Wire Notes Line - 7200 6450 7200 4200 -Text Notes 7250 5100 0 50 ~ 0 -Brain -- aka ATSAME54P20A_AU\n - 120Mhz Core Clock\n - 32khz External Clock (for startup)\n - 12(?)Mhz Alt Clock (probably unused, but adding it just in case)\n - 3 Sercoms\n - 1 I2C\n - 1 SPI\n - 1 U(S)ART\n - Interfaces with IO Extender for parallel bus control without sacrificing pins\n - The E54 has a shitty pin set for parallel control (not bc of no. of pins, but \nbecause of positions and default pin functions) -$Comp -L Device:Crystal Y1 -U 1 1 5E75D825 -P 5000 1300 -F 0 "Y1" V 5046 1169 50 0000 R CNN -F 1 "XOSC32" V 4955 1169 50 0000 R CNN -F 2 "Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm" H 5000 1300 50 0001 C CNN -F 3 "~" H 5000 1300 50 0001 C CNN - 1 5000 1300 - 0 -1 -1 0 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 1 1 5E82A2F6 -P 3650 2000 -F 0 "U1" H 3733 3165 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 3733 3074 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 2450 3250 50 0001 C CNN -F 3 "" H 2450 3250 50 0001 C CNN - 1 3650 2000 - 1 0 0 -1 -$EndComp -$Comp -L Device:C_Small C1 -U 1 1 5E7E5146 -P 5100 1050 -F 0 "C1" V 4871 1050 50 0000 C CNN -F 1 "6.8pF" V 4962 1050 50 0000 C CNN -F 2 "" H 5100 1050 50 0001 C CNN -F 3 "~" H 5100 1050 50 0001 C CNN - 1 5100 1050 - 0 1 1 0 -$EndComp -$Comp -L Device:C_Small C2 -U 1 1 5E7E6123 -P 5100 1550 -F 0 "C2" V 4871 1550 50 0000 C CNN -F 1 "6.8pF" V 4950 1500 50 0000 C CNN -F 2 "" H 5100 1550 50 0001 C CNN -F 3 "~" H 5100 1550 50 0001 C CNN - 1 5100 1550 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 4800 1350 4250 1350 -Wire Wire Line - 4800 1250 4250 1250 -Wire Wire Line - 5000 1050 5000 1150 -Wire Wire Line - 5000 1550 5000 1450 -Wire Wire Line - 4800 1550 5000 1550 -Wire Wire Line - 4800 1350 4800 1550 -Connection ~ 5000 1550 -Wire Wire Line - 4800 1050 5000 1050 -Wire Wire Line - 4800 1050 4800 1250 -Connection ~ 5000 1050 -Wire Wire Line - 5200 1050 5450 1050 -Wire Wire Line - 5450 1050 5450 1300 -Wire Wire Line - 5450 1550 5200 1550 -Wire Wire Line - 5450 1300 5550 1300 -Connection ~ 5450 1300 -Wire Wire Line - 5450 1300 5450 1550 -$Comp -L power:GND #PWR0104 -U 1 1 5E825E8D -P 5550 1300 -F 0 "#PWR0104" H 5550 1050 50 0001 C CNN -F 1 "GND" H 5555 1127 50 0000 C CNN -F 2 "" H 5550 1300 50 0001 C CNN -F 3 "" H 5550 1300 50 0001 C CNN - 1 5550 1300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5900 2700 5900 2850 -Connection ~ 5350 2700 -$Comp -L power:GND #PWR0108 -U 1 1 5E880A2C -P 5900 2850 -F 0 "#PWR0108" H 5900 2600 50 0001 C CNN -F 1 "GND" H 5905 2677 50 0000 C CNN -F 2 "" H 5900 2850 50 0001 C CNN -F 3 "" H 5900 2850 50 0001 C CNN - 1 5900 2850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5150 2550 5150 2500 -Wire Wire Line - 5150 2500 4900 2500 -Wire Wire Line - 4900 2500 4900 2650 -Wire Wire Line - 4900 2650 4250 2650 -Wire Wire Line - 5150 2850 5150 2900 -Wire Wire Line - 5150 2900 4900 2900 -Wire Wire Line - 4900 2900 4900 2750 -Wire Wire Line - 4900 2750 4250 2750 -$Comp -L Device:C_Small C5 -U 1 1 5E8AA0A3 -P 5250 3050 -F 0 "C5" V 5450 3050 50 0000 C CNN -F 1 "5pF" V 5350 3050 50 0000 C CNN -F 2 "" H 5250 3050 50 0001 C CNN -F 3 "~" H 5250 3050 50 0001 C CNN - 1 5250 3050 - 0 1 1 0 -$EndComp -Wire Wire Line - 5350 2700 4950 2700 -$Comp -L Device:Crystal_GND24 Y2 -U 1 1 5E843969 -P 5150 2700 -F 0 "Y2" V 5100 3050 50 0000 R CNN -F 1 "XOSC0" V 5000 3200 50 0000 R CNN -F 2 "" H 5150 2700 50 0001 C CNN -F 3 "~" H 5150 2700 50 0001 C CNN - 1 5150 2700 - 0 1 1 0 -$EndComp -Wire Wire Line - 5150 3050 5150 2900 -Connection ~ 5150 2900 -$Comp -L Device:C_Small C4 -U 1 1 5E8C2D5D -P 5250 2350 -F 0 "C4" V 5021 2350 50 0000 C CNN -F 1 "5pF" V 5112 2350 50 0000 C CNN -F 2 "" H 5250 2350 50 0001 C CNN -F 3 "~" H 5250 2350 50 0001 C CNN - 1 5250 2350 - 0 1 1 0 -$EndComp -Wire Wire Line - 5150 2500 5150 2350 -Connection ~ 5150 2500 -Wire Wire Line - 5350 2700 5900 2700 -Wire Wire Line - 5350 2350 5350 2700 -Wire Wire Line - 5350 3050 5350 2700 -Text GLabel 900 800 0 50 Input ~ 0 -g_3v3 -Text GLabel 850 950 0 50 Input ~ 0 -g_5v -Text Label 1500 800 0 50 ~ 0 -3v3 -Text Label 1500 950 0 50 ~ 0 -5v -Text HLabel 1100 2100 0 50 Input ~ 0 -DEBUG_TX -Text HLabel 1100 2250 0 50 Input ~ 0 -DEBUG_RX -Text Label 1550 2100 0 50 ~ 0 -UART0_TX -Text Label 1550 2250 0 50 ~ 0 -UART0_RX -Text HLabel 1350 2400 0 50 Input ~ 0 -MASTER_SPI_MOSI -Text HLabel 1350 2550 0 50 Input ~ 0 -MASTER_SPI_MISO -Text HLabel 1300 2700 0 50 Input ~ 0 -MASTER_SPI_CLK -Text HLabel 1100 2850 0 50 Input ~ 0 -~TFT_CS -Text HLabel 1250 3000 0 50 Input ~ 0 -~FLASH_MEM_CS -Wire Wire Line - 1350 2400 1550 2400 -Wire Wire Line - 1350 2550 1550 2550 -Wire Wire Line - 1300 2700 1550 2700 -Wire Wire Line - 1100 2850 1550 2850 -Wire Wire Line - 1250 3000 1550 3000 -Text HLabel 1350 3150 0 50 Input ~ 0 -~IO_EXPANDER_CS -Wire Wire Line - 1350 3150 1550 3150 -Wire Wire Line - 1100 2100 1550 2100 -Wire Wire Line - 1100 2250 1550 2250 -Wire Wire Line - 900 800 1500 800 -Wire Wire Line - 850 950 1500 950 -Text Notes 600 700 0 50 ~ 0 -Power Interface -Wire Notes Line - 550 600 1700 600 -Text Notes 650 1950 0 50 ~ 0 -Brain Interface -Wire Notes Line - 2350 1850 550 1850 -Text Label 1550 2400 0 50 ~ 0 -SPI0_MOSI -Text Label 1550 2550 0 50 ~ 0 -SPI0_MISO -Text Label 1550 2700 0 50 ~ 0 -SPI0_CLK -Text Label 1550 2850 0 50 ~ 0 -SPI0_CS0 -Text Label 1550 3000 0 50 ~ 0 -SPI0_CS1 -Text Label 1550 3150 0 50 ~ 0 -SPI0_CS2 -Text Label 7550 1250 0 50 ~ 0 -VBAT -Wire Wire Line - 800 1150 1500 1150 -Text Label 800 1150 2 50 ~ 0 -3v3 -Text Label 1500 1150 0 50 ~ 0 -VBAT -Wire Wire Line - 7500 1250 7550 1250 -Text HLabel 1100 3600 0 50 Input ~ 0 -~TFT_WR -Text HLabel 1100 3700 0 50 Input ~ 0 -~TFT_RD -Text HLabel 1100 3800 0 50 Input ~ 0 -TFT_RSDC -Wire Wire Line - 1100 3600 1550 3600 -Wire Wire Line - 1100 3700 1550 3700 -Wire Wire Line - 1100 3800 1550 3800 -Text Label 1550 3700 0 50 ~ 0 -~TFT_RD -Text Label 1550 3800 0 50 ~ 0 -TFT_RSDC -Text HLabel 1100 3900 0 50 Input ~ 0 -~TFT_RST -Wire Wire Line - 1100 3900 1550 3900 -Text Label 1550 3900 0 50 ~ 0 -~TFT_RST -Wire Wire Line - 4250 1850 4350 1850 -Wire Wire Line - 4250 1750 4350 1750 -Wire Wire Line - 4250 1650 4350 1650 -Text Label 4350 1750 0 50 ~ 0 -SPI0_CLK -Text Label 4350 1850 0 50 ~ 0 -SPI0_MISO -Text Label 4350 1650 0 50 ~ 0 -SPI0_MISO -Wire Wire Line - 7500 3350 7600 3350 -Wire Wire Line - 7500 3450 7600 3450 -Text Label 7600 3450 0 50 ~ 0 -UART0_TX -Text Label 7600 3350 0 50 ~ 0 -UART0_RX -Text Notes 6350 3450 0 50 ~ 0 -SERCOM2 (USART) -Wire Notes Line - 6300 3500 7300 3500 -Wire Notes Line - 7300 3500 7300 3300 -Wire Notes Line - 6300 3300 7300 3300 -Wire Notes Line - 6300 3300 6300 3500 -Wire Notes Line - 4050 1600 3200 1600 -Wire Notes Line - 3200 1600 3200 1900 -Wire Notes Line - 3200 1900 4050 1900 -Wire Notes Line - 4050 1900 4050 1600 -Text Notes 3200 1800 0 50 ~ 0 -SERCOM2 (SPI) -Wire Wire Line - 4250 2850 4350 2850 -Wire Wire Line - 4250 2950 4350 2950 -Text Label 4350 2850 0 50 ~ 0 -I2C0_SDA -Text Label 4350 2950 0 50 ~ 0 -I2C0_SCL -Text Notes 3200 2950 0 50 ~ 0 -SERCOM1 (I2C) -Wire Notes Line - 4050 2800 3200 2800 -Wire Notes Line - 3200 2800 3200 3000 -Wire Notes Line - 3200 3000 4050 3000 -Wire Notes Line - 4050 3000 4050 2800 -Wire Wire Line - 4900 5400 5000 5400 -Text HLabel 1000 1250 0 50 Input ~ 0 -~SYS_RST -Wire Notes Line - 550 1300 1700 1300 -Wire Notes Line - 1700 600 1700 1300 -Wire Notes Line - 550 600 550 1300 -Text Label 1250 1250 0 50 ~ 0 -~BRAIN_RST -Wire Wire Line - 1000 1250 1250 1250 -Wire Wire Line - 4900 5600 5000 5600 -Text Label 5000 5600 0 50 ~ 0 -SWCLK -Wire Wire Line - 4900 5700 5000 5700 -Text Label 5000 5700 0 50 ~ 0 -SWDIO -Text Label 5000 5800 0 50 ~ 0 -SWO -Wire Wire Line - 4900 5800 5000 5800 -Wire Wire Line - 4300 6300 4400 6300 -NoConn ~ 4900 5900 -Text Label 5000 5400 0 50 ~ 0 -~SWRST -Wire Wire Line - 4400 6300 4400 6350 -Connection ~ 4400 6300 -$Comp -L power:GND #PWR0119 -U 1 1 5EA9AF4B -P 4400 6350 -F 0 "#PWR0119" H 4400 6100 50 0001 C CNN -F 1 "GND" H 4405 6177 50 0000 C CNN -F 2 "" H 4400 6350 50 0001 C CNN -F 3 "" H 4400 6350 50 0001 C CNN - 1 4400 6350 - 1 0 0 -1 -$EndComp -Text Label 1550 3600 0 50 ~ 0 -~TFT_WR -Text Label 1900 5050 0 50 ~ 0 -I2C0_SCL -Text Label 1900 4600 0 50 ~ 0 -I2C0_SDA -Text HLabel 1300 5050 0 50 Input ~ 0 -MASTER_I2C_SCL -Text HLabel 1300 4600 0 50 Input ~ 0 -MASTER_I2C_SDA -$Comp -L Device:R_Small R4 -U 1 1 5EB11658 -P 1450 4450 -F 0 "R4" H 1509 4496 50 0000 L CNN -F 1 "4.7k" H 1509 4405 50 0000 L CNN -F 2 "" H 1450 4450 50 0001 C CNN -F 3 "~" H 1450 4450 50 0001 C CNN - 1 1450 4450 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1450 4350 1450 4300 -Text Label 1450 4300 0 50 ~ 0 -3v3 -$Comp -L Device:R_Small R5 -U 1 1 5EB38D15 -P 1450 4900 -F 0 "R5" H 1509 4946 50 0000 L CNN -F 1 "4.7k" H 1509 4855 50 0000 L CNN -F 2 "" H 1450 4900 50 0001 C CNN -F 3 "~" H 1450 4900 50 0001 C CNN - 1 1450 4900 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1300 5050 1450 5050 -Wire Wire Line - 1300 4600 1450 4600 -Wire Wire Line - 1450 4600 1450 4550 -Connection ~ 1450 4600 -Wire Wire Line - 1450 4600 1900 4600 -Wire Wire Line - 1450 5050 1450 5000 -Connection ~ 1450 5050 -Wire Wire Line - 1450 4800 1450 4750 -Text Label 1450 4750 0 50 ~ 0 -3v3 -Wire Wire Line - 1450 5050 1900 5050 -Text Label 850 7150 2 50 ~ 0 -~SWRST -Wire Wire Line - 850 7150 1250 7150 -Text Label 1250 7150 0 50 ~ 0 -~BRAIN_RST -Text Notes 600 7000 0 50 ~ 0 -Locals -Text HLabel 1050 5200 0 50 Input ~ 0 -EXT_IRQ_0 -Text HLabel 1050 5300 0 50 Input ~ 0 -EXT_IRQ_1 -Text HLabel 1050 5400 0 50 Input ~ 0 -EXT_IRQ_2 -Text HLabel 1050 5500 0 50 Input ~ 0 -EXT_IRQ_3 -Text HLabel 1050 5600 0 50 Input ~ 0 -EXT_IRQ_4 -Text HLabel 1050 5700 0 50 Input ~ 0 -EXT_IRQ_5 -Wire Wire Line - 1050 5200 1300 5200 -Text Label 1300 5200 0 50 ~ 0 -EXT_IRQ_0 -Wire Wire Line - 1050 5300 1300 5300 -Text Label 1300 5300 0 50 ~ 0 -EXT_IRQ_1 -Wire Wire Line - 1050 5400 1300 5400 -Text Label 1300 5400 0 50 ~ 0 -EXT_IRQ_2 -Wire Wire Line - 1050 5500 1300 5500 -Text Label 1300 5500 0 50 ~ 0 -EXT_IRQ_3 -Wire Wire Line - 1050 5600 1300 5600 -Text Label 1300 5600 0 50 ~ 0 -EXT_IRQ_4 -Wire Wire Line - 1050 5700 1300 5700 -Text Label 1300 5700 0 50 ~ 0 -EXT_IRQ_5 -Text Label 7700 950 0 50 ~ 0 -EXT_IRQ_0 -Wire Wire Line - 7500 950 7700 950 -Text Label 7700 1050 0 50 ~ 0 -EXT_IRQ_1 -Wire Wire Line - 7500 1050 7700 1050 -Text Label 7700 1150 0 50 ~ 0 -EXT_IRQ_2 -Wire Wire Line - 7500 1150 7700 1150 -Wire Wire Line - 7500 1450 7700 1450 -Text Label 7700 1450 0 50 ~ 0 -EXT_IRQ_4 -Wire Wire Line - 7500 1350 7700 1350 -Text Label 7700 1350 0 50 ~ 0 -EXT_IRQ_3 -Wire Wire Line - 7500 1550 7700 1550 -Text Label 7700 1550 0 50 ~ 0 -EXT_IRQ_5 -Wire Notes Line - 2350 5750 550 5750 -Wire Notes Line - 550 1850 550 5750 -Wire Notes Line - 2350 1850 2350 5750 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 5 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 2 1 5E82C3BA +P 6800 1600 +F 0 "U1" H 6908 2665 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 6908 2574 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 5600 2850 50 0001 C CNN +F 3 "" H 5600 2850 50 0001 C CNN + 2 6800 1600 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 3 1 5E82DE73 +P 8950 1650 +F 0 "U1" H 9058 2665 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 9058 2574 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 7750 2900 50 0001 C CNN +F 3 "" H 7750 2900 50 0001 C CNN + 3 8950 1650 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 4 1 5E8352A8 +P 10250 1800 +F 0 "U1" H 10358 2865 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 10358 2774 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 9050 3050 50 0001 C CNN +F 3 "" H 9050 3050 50 0001 C CNN + 4 10250 1800 + 1 0 0 -1 +$EndComp +$Comp +L Connector:Conn_ARM_JTAG_SWD_10 J2 +U 1 1 5EA1E350 +P 4400 5700 +F 0 "J2" H 3957 5746 50 0000 R CNN +F 1 "Conn_ARM_JTAG_SWD_10" H 3957 5655 50 0000 R CNN +F 2 "Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical" H 4400 5700 50 0001 C CNN +F 3 "http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/DDI0314H_coresight_components_trm.pdf" V 4050 4450 50 0001 C CNN + 1 4400 5700 + 1 0 0 -1 +$EndComp +Wire Notes Line + 7200 4200 11150 4200 +Wire Notes Line + 11150 4200 11150 6450 +Wire Notes Line + 11150 6450 7200 6450 +Wire Notes Line + 7200 6450 7200 4200 +Text Notes 7250 5100 0 50 ~ 0 +Brain -- aka ATSAME54P20A_AU\n - 120Mhz Core Clock\n - 32khz External Clock (for startup)\n - 12(?)Mhz Alt Clock (probably unused, but adding it just in case)\n - 3 Sercoms\n - 1 I2C\n - 1 SPI\n - 1 U(S)ART\n - Interfaces with IO Extender for parallel bus control without sacrificing pins\n - The E54 has a shitty pin set for parallel control (not bc of no. of pins, but \nbecause of positions and default pin functions) +$Comp +L Device:Crystal Y1 +U 1 1 5E75D825 +P 5000 1300 +F 0 "Y1" V 5046 1169 50 0000 R CNN +F 1 "XOSC32" V 4955 1169 50 0000 R CNN +F 2 "Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm" H 5000 1300 50 0001 C CNN +F 3 "~" H 5000 1300 50 0001 C CNN + 1 5000 1300 + 0 -1 -1 0 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 1 1 5E82A2F6 +P 3650 2000 +F 0 "U1" H 3733 3165 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 3733 3074 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 2450 3250 50 0001 C CNN +F 3 "" H 2450 3250 50 0001 C CNN + 1 3650 2000 + 1 0 0 -1 +$EndComp +$Comp +L Device:C_Small C1 +U 1 1 5E7E5146 +P 5100 1050 +F 0 "C1" V 4871 1050 50 0000 C CNN +F 1 "6.8pF" V 4962 1050 50 0000 C CNN +F 2 "" H 5100 1050 50 0001 C CNN +F 3 "~" H 5100 1050 50 0001 C CNN + 1 5100 1050 + 0 1 1 0 +$EndComp +$Comp +L Device:C_Small C2 +U 1 1 5E7E6123 +P 5100 1550 +F 0 "C2" V 4871 1550 50 0000 C CNN +F 1 "6.8pF" V 4950 1500 50 0000 C CNN +F 2 "" H 5100 1550 50 0001 C CNN +F 3 "~" H 5100 1550 50 0001 C CNN + 1 5100 1550 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4800 1350 4250 1350 +Wire Wire Line + 4800 1250 4250 1250 +Wire Wire Line + 5000 1050 5000 1150 +Wire Wire Line + 5000 1550 5000 1450 +Wire Wire Line + 4800 1550 5000 1550 +Wire Wire Line + 4800 1350 4800 1550 +Connection ~ 5000 1550 +Wire Wire Line + 4800 1050 5000 1050 +Wire Wire Line + 4800 1050 4800 1250 +Connection ~ 5000 1050 +Wire Wire Line + 5200 1050 5450 1050 +Wire Wire Line + 5450 1050 5450 1300 +Wire Wire Line + 5450 1550 5200 1550 +Wire Wire Line + 5450 1300 5550 1300 +Connection ~ 5450 1300 +Wire Wire Line + 5450 1300 5450 1550 +$Comp +L power:GND #PWR0104 +U 1 1 5E825E8D +P 5550 1300 +F 0 "#PWR0104" H 5550 1050 50 0001 C CNN +F 1 "GND" H 5555 1127 50 0000 C CNN +F 2 "" H 5550 1300 50 0001 C CNN +F 3 "" H 5550 1300 50 0001 C CNN + 1 5550 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2700 5900 2850 +Connection ~ 5350 2700 +$Comp +L power:GND #PWR0108 +U 1 1 5E880A2C +P 5900 2850 +F 0 "#PWR0108" H 5900 2600 50 0001 C CNN +F 1 "GND" H 5905 2677 50 0000 C CNN +F 2 "" H 5900 2850 50 0001 C CNN +F 3 "" H 5900 2850 50 0001 C CNN + 1 5900 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5150 2550 5150 2500 +Wire Wire Line + 5150 2500 4900 2500 +Wire Wire Line + 4900 2500 4900 2650 +Wire Wire Line + 4900 2650 4250 2650 +Wire Wire Line + 5150 2850 5150 2900 +Wire Wire Line + 5150 2900 4900 2900 +Wire Wire Line + 4900 2900 4900 2750 +Wire Wire Line + 4900 2750 4250 2750 +$Comp +L Device:C_Small C5 +U 1 1 5E8AA0A3 +P 5250 3050 +F 0 "C5" V 5450 3050 50 0000 C CNN +F 1 "5pF" V 5350 3050 50 0000 C CNN +F 2 "" H 5250 3050 50 0001 C CNN +F 3 "~" H 5250 3050 50 0001 C CNN + 1 5250 3050 + 0 1 1 0 +$EndComp +Wire Wire Line + 5350 2700 4950 2700 +$Comp +L Device:Crystal_GND24 Y2 +U 1 1 5E843969 +P 5150 2700 +F 0 "Y2" V 5100 3050 50 0000 R CNN +F 1 "XOSC0" V 5000 3200 50 0000 R CNN +F 2 "" H 5150 2700 50 0001 C CNN +F 3 "~" H 5150 2700 50 0001 C CNN + 1 5150 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 5150 3050 5150 2900 +Connection ~ 5150 2900 +$Comp +L Device:C_Small C4 +U 1 1 5E8C2D5D +P 5250 2350 +F 0 "C4" V 5021 2350 50 0000 C CNN +F 1 "5pF" V 5112 2350 50 0000 C CNN +F 2 "" H 5250 2350 50 0001 C CNN +F 3 "~" H 5250 2350 50 0001 C CNN + 1 5250 2350 + 0 1 1 0 +$EndComp +Wire Wire Line + 5150 2500 5150 2350 +Connection ~ 5150 2500 +Wire Wire Line + 5350 2700 5900 2700 +Wire Wire Line + 5350 2350 5350 2700 +Wire Wire Line + 5350 3050 5350 2700 +Text GLabel 900 800 0 50 Input ~ 0 +g_3v3 +Text GLabel 850 950 0 50 Input ~ 0 +g_5v +Text Label 1500 800 0 50 ~ 0 +3v3 +Text Label 1500 950 0 50 ~ 0 +5v +Text HLabel 1100 2100 0 50 Input ~ 0 +DEBUG_TX +Text HLabel 1100 2250 0 50 Input ~ 0 +DEBUG_RX +Text Label 1550 2100 0 50 ~ 0 +UART0_TX +Text Label 1550 2250 0 50 ~ 0 +UART0_RX +Text HLabel 1350 2400 0 50 Input ~ 0 +MASTER_SPI_MOSI +Text HLabel 1350 2550 0 50 Input ~ 0 +MASTER_SPI_MISO +Text HLabel 1300 2700 0 50 Input ~ 0 +MASTER_SPI_CLK +Text HLabel 1100 2850 0 50 Input ~ 0 +~TFT_CS +Text HLabel 1250 3000 0 50 Input ~ 0 +~FLASH_MEM_CS +Wire Wire Line + 1350 2400 1550 2400 +Wire Wire Line + 1350 2550 1550 2550 +Wire Wire Line + 1300 2700 1550 2700 +Wire Wire Line + 1100 2850 1550 2850 +Wire Wire Line + 1250 3000 1550 3000 +Text HLabel 1350 3150 0 50 Input ~ 0 +~IO_EXPANDER_CS +Wire Wire Line + 1350 3150 1550 3150 +Wire Wire Line + 1100 2100 1550 2100 +Wire Wire Line + 1100 2250 1550 2250 +Wire Wire Line + 900 800 1500 800 +Wire Wire Line + 850 950 1500 950 +Text Notes 600 700 0 50 ~ 0 +Power Interface +Wire Notes Line + 550 600 1700 600 +Text Notes 650 1950 0 50 ~ 0 +Brain Interface +Wire Notes Line + 2350 1850 550 1850 +Text Label 1550 2400 0 50 ~ 0 +SPI0_MOSI +Text Label 1550 2550 0 50 ~ 0 +SPI0_MISO +Text Label 1550 2700 0 50 ~ 0 +SPI0_CLK +Text Label 1550 2850 0 50 ~ 0 +SPI0_CS0 +Text Label 1550 3000 0 50 ~ 0 +SPI0_CS1 +Text Label 1550 3150 0 50 ~ 0 +SPI0_CS2 +Text Label 7550 1250 0 50 ~ 0 +VBAT +Wire Wire Line + 800 1150 1500 1150 +Text Label 800 1150 2 50 ~ 0 +3v3 +Text Label 1500 1150 0 50 ~ 0 +VBAT +Wire Wire Line + 7500 1250 7550 1250 +Text HLabel 1100 3600 0 50 Input ~ 0 +~TFT_WR +Text HLabel 1100 3700 0 50 Input ~ 0 +~TFT_RD +Text HLabel 1100 3800 0 50 Input ~ 0 +TFT_RSDC +Wire Wire Line + 1100 3600 1550 3600 +Wire Wire Line + 1100 3700 1550 3700 +Wire Wire Line + 1100 3800 1550 3800 +Text Label 1550 3700 0 50 ~ 0 +~TFT_RD +Text Label 1550 3800 0 50 ~ 0 +TFT_RSDC +Text HLabel 1100 3900 0 50 Input ~ 0 +~TFT_RST +Wire Wire Line + 1100 3900 1550 3900 +Text Label 1550 3900 0 50 ~ 0 +~TFT_RST +Wire Wire Line + 4250 1850 4350 1850 +Wire Wire Line + 4250 1750 4350 1750 +Wire Wire Line + 4250 1650 4350 1650 +Text Label 4350 1750 0 50 ~ 0 +SPI0_CLK +Text Label 4350 1850 0 50 ~ 0 +SPI0_MISO +Text Label 4350 1650 0 50 ~ 0 +SPI0_MISO +Wire Wire Line + 7500 3350 7600 3350 +Wire Wire Line + 7500 3450 7600 3450 +Text Label 7600 3450 0 50 ~ 0 +UART0_TX +Text Label 7600 3350 0 50 ~ 0 +UART0_RX +Text Notes 6350 3450 0 50 ~ 0 +SERCOM2 (USART) +Wire Notes Line + 6300 3500 7300 3500 +Wire Notes Line + 7300 3500 7300 3300 +Wire Notes Line + 6300 3300 7300 3300 +Wire Notes Line + 6300 3300 6300 3500 +Wire Notes Line + 4050 1600 3200 1600 +Wire Notes Line + 3200 1600 3200 1900 +Wire Notes Line + 3200 1900 4050 1900 +Wire Notes Line + 4050 1900 4050 1600 +Text Notes 3200 1800 0 50 ~ 0 +SERCOM2 (SPI) +Wire Wire Line + 4250 2850 4350 2850 +Wire Wire Line + 4250 2950 4350 2950 +Text Label 4350 2850 0 50 ~ 0 +I2C0_SDA +Text Label 4350 2950 0 50 ~ 0 +I2C0_SCL +Text Notes 3200 2950 0 50 ~ 0 +SERCOM1 (I2C) +Wire Notes Line + 4050 2800 3200 2800 +Wire Notes Line + 3200 2800 3200 3000 +Wire Notes Line + 3200 3000 4050 3000 +Wire Notes Line + 4050 3000 4050 2800 +Wire Wire Line + 4900 5400 5000 5400 +Text HLabel 1000 1250 0 50 Input ~ 0 +~SYS_RST +Wire Notes Line + 550 1300 1700 1300 +Wire Notes Line + 1700 600 1700 1300 +Wire Notes Line + 550 600 550 1300 +Text Label 1250 1250 0 50 ~ 0 +~BRAIN_RST +Wire Wire Line + 1000 1250 1250 1250 +Wire Wire Line + 4900 5600 5000 5600 +Text Label 5000 5600 0 50 ~ 0 +SWCLK +Wire Wire Line + 4900 5700 5000 5700 +Text Label 5000 5700 0 50 ~ 0 +SWDIO +Text Label 5000 5800 0 50 ~ 0 +SWO +Wire Wire Line + 4900 5800 5000 5800 +Wire Wire Line + 4300 6300 4400 6300 +NoConn ~ 4900 5900 +Text Label 5000 5400 0 50 ~ 0 +~SWRST +Wire Wire Line + 4400 6300 4400 6350 +Connection ~ 4400 6300 +$Comp +L power:GND #PWR0119 +U 1 1 5EA9AF4B +P 4400 6350 +F 0 "#PWR0119" H 4400 6100 50 0001 C CNN +F 1 "GND" H 4405 6177 50 0000 C CNN +F 2 "" H 4400 6350 50 0001 C CNN +F 3 "" H 4400 6350 50 0001 C CNN + 1 4400 6350 + 1 0 0 -1 +$EndComp +Text Label 1550 3600 0 50 ~ 0 +~TFT_WR +Text Label 1900 5050 0 50 ~ 0 +I2C0_SCL +Text Label 1900 4600 0 50 ~ 0 +I2C0_SDA +Text HLabel 1300 5050 0 50 Input ~ 0 +MASTER_I2C_SCL +Text HLabel 1300 4600 0 50 Input ~ 0 +MASTER_I2C_SDA +$Comp +L Device:R_Small R4 +U 1 1 5EB11658 +P 1450 4450 +F 0 "R4" H 1509 4496 50 0000 L CNN +F 1 "4.7k" H 1509 4405 50 0000 L CNN +F 2 "" H 1450 4450 50 0001 C CNN +F 3 "~" H 1450 4450 50 0001 C CNN + 1 1450 4450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1450 4350 1450 4300 +Text Label 1450 4300 0 50 ~ 0 +3v3 +$Comp +L Device:R_Small R5 +U 1 1 5EB38D15 +P 1450 4900 +F 0 "R5" H 1509 4946 50 0000 L CNN +F 1 "4.7k" H 1509 4855 50 0000 L CNN +F 2 "" H 1450 4900 50 0001 C CNN +F 3 "~" H 1450 4900 50 0001 C CNN + 1 1450 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1300 5050 1450 5050 +Wire Wire Line + 1300 4600 1450 4600 +Wire Wire Line + 1450 4600 1450 4550 +Connection ~ 1450 4600 +Wire Wire Line + 1450 4600 1900 4600 +Wire Wire Line + 1450 5050 1450 5000 +Connection ~ 1450 5050 +Wire Wire Line + 1450 4800 1450 4750 +Text Label 1450 4750 0 50 ~ 0 +3v3 +Wire Wire Line + 1450 5050 1900 5050 +Text Label 850 7150 2 50 ~ 0 +~SWRST +Wire Wire Line + 850 7150 1250 7150 +Text Label 1250 7150 0 50 ~ 0 +~BRAIN_RST +Text Notes 600 7000 0 50 ~ 0 +Locals +Text HLabel 1050 5200 0 50 Input ~ 0 +EXT_IRQ_0 +Text HLabel 1050 5300 0 50 Input ~ 0 +EXT_IRQ_1 +Text HLabel 1050 5400 0 50 Input ~ 0 +EXT_IRQ_2 +Text HLabel 1050 5500 0 50 Input ~ 0 +EXT_IRQ_3 +Text HLabel 1050 5600 0 50 Input ~ 0 +EXT_IRQ_4 +Text HLabel 1050 5700 0 50 Input ~ 0 +EXT_IRQ_5 +Wire Wire Line + 1050 5200 1300 5200 +Text Label 1300 5200 0 50 ~ 0 +EXT_IRQ_0 +Wire Wire Line + 1050 5300 1300 5300 +Text Label 1300 5300 0 50 ~ 0 +EXT_IRQ_1 +Wire Wire Line + 1050 5400 1300 5400 +Text Label 1300 5400 0 50 ~ 0 +EXT_IRQ_2 +Wire Wire Line + 1050 5500 1300 5500 +Text Label 1300 5500 0 50 ~ 0 +EXT_IRQ_3 +Wire Wire Line + 1050 5600 1300 5600 +Text Label 1300 5600 0 50 ~ 0 +EXT_IRQ_4 +Wire Wire Line + 1050 5700 1300 5700 +Text Label 1300 5700 0 50 ~ 0 +EXT_IRQ_5 +Text Label 7700 950 0 50 ~ 0 +EXT_IRQ_0 +Wire Wire Line + 7500 950 7700 950 +Text Label 7700 1050 0 50 ~ 0 +EXT_IRQ_1 +Wire Wire Line + 7500 1050 7700 1050 +Text Label 7700 1150 0 50 ~ 0 +EXT_IRQ_2 +Wire Wire Line + 7500 1150 7700 1150 +Wire Wire Line + 7500 1450 7700 1450 +Text Label 7700 1450 0 50 ~ 0 +EXT_IRQ_4 +Wire Wire Line + 7500 1350 7700 1350 +Text Label 7700 1350 0 50 ~ 0 +EXT_IRQ_3 +Wire Wire Line + 7500 1550 7700 1550 +Text Label 7700 1550 0 50 ~ 0 +EXT_IRQ_5 +Wire Notes Line + 2350 5750 550 5750 +Wire Notes Line + 550 1850 550 5750 +Wire Notes Line + 2350 1850 2350 5750 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/NCP349MNAETBG.dcm b/electrical/same54_dev_board/NCP349MNAETBG.dcm index 5f3ed79..5dd71cb 100644 --- a/electrical/same54_dev_board/NCP349MNAETBG.dcm +++ b/electrical/same54_dev_board/NCP349MNAETBG.dcm @@ -1,3 +1,3 @@ -EESchema-DOCLIB Version 2.0 -# -#End Doc Library +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/electrical/same54_dev_board/NCP349MNAETBG.lib b/electrical/same54_dev_board/NCP349MNAETBG.lib index 93fad29..0427376 100644 --- a/electrical/same54_dev_board/NCP349MNAETBG.lib +++ b/electrical/same54_dev_board/NCP349MNAETBG.lib @@ -1,22 +1,22 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# NCP349MNAETBG -# -DEF NCP349MNAETBG U 0 40 Y Y 1 F N -F0 "U" 0 -200 50 H V C CNN -F1 "NCP349MNAETBG" 0 350 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -S -300 250 300 -150 0 1 0 f -X VIN 1 -400 150 100 R 50 50 1 1 I -X GND 2 -400 50 100 R 50 50 1 1 I -X ~FLAG 3 400 150 100 L 50 50 1 1 I -X ~EN 4 -400 -50 100 R 50 50 1 1 I -X OUT 5 400 50 100 L 50 50 1 1 I -X OUT 6 400 -50 100 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -#End Library +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# NCP349MNAETBG +# +DEF NCP349MNAETBG U 0 40 Y Y 1 F N +F0 "U" 0 -200 50 H V C CNN +F1 "NCP349MNAETBG" 0 350 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -300 250 300 -150 0 1 0 f +X VIN 1 -400 150 100 R 50 50 1 1 I +X GND 2 -400 50 100 R 50 50 1 1 I +X ~FLAG 3 400 150 100 L 50 50 1 1 I +X ~EN 4 -400 -50 100 R 50 50 1 1 I +X OUT 5 400 50 100 L 50 50 1 1 I +X OUT 6 400 -50 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/electrical/same54_dev_board/Power.sch b/electrical/same54_dev_board/Power.sch index 956d777..c14db1d 100644 --- a/electrical/same54_dev_board/Power.sch +++ b/electrical/same54_dev_board/Power.sch @@ -1,401 +1,401 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 2 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5950 4350 5950 4450 -Connection ~ 5950 4450 -Wire Wire Line - 5950 4450 5950 4550 -Connection ~ 5950 4550 -Wire Wire Line - 5950 4550 5950 4650 -Connection ~ 5950 4650 -Wire Wire Line - 5950 4650 5950 4750 -Connection ~ 5950 4750 -Wire Wire Line - 5950 4750 5950 4850 -Connection ~ 5950 4850 -Wire Wire Line - 5950 4850 5950 4950 -Connection ~ 5950 4950 -Wire Wire Line - 5950 4950 5950 5050 -Connection ~ 5950 5050 -Wire Wire Line - 5950 5050 5950 5150 -Connection ~ 5950 5150 -Wire Wire Line - 5950 5150 5950 5250 -Wire Wire Line - 5950 5500 5950 5600 -Text HLabel 950 900 0 50 Input ~ 0 -USB_3v3 -Text HLabel 950 1050 0 50 Input ~ 0 -USB_5v -Text GLabel 950 600 0 50 Input ~ 0 -g_3v3 -Text GLabel 950 750 0 50 Input ~ 0 -g_5v -Wire Wire Line - 950 900 1350 900 -Text Label 1350 900 0 50 ~ 0 -USB_3v3 -Wire Wire Line - 950 1050 1350 1050 -Text Label 1350 1050 0 50 ~ 0 -USB_5v -Wire Wire Line - 950 600 1350 600 -Wire Wire Line - 950 750 1350 750 -Text Label 1350 600 0 50 ~ 0 -3v3Out -Text Label 1350 750 0 50 ~ 0 -5vOut -Wire Wire Line - 3950 5300 3950 5400 -Connection ~ 3950 5400 -Wire Wire Line - 3950 5400 3950 5500 -Connection ~ 3950 5500 -Wire Wire Line - 3950 5500 3950 5600 -Connection ~ 3950 5600 -Wire Wire Line - 3950 5600 3950 5700 -Connection ~ 3950 5700 -Wire Wire Line - 3950 5700 3950 5800 -Connection ~ 3950 5800 -Wire Wire Line - 3950 5800 3950 5900 -Connection ~ 3950 5900 -Wire Wire Line - 3950 5900 3950 6000 -$Comp -L Connector:Barrel_Jack_Switch J4 -U 1 1 5E88DD8C -P 950 1500 -F 0 "J4" H 1007 1817 50 0000 C CNN -F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN -F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN -F 3 "~" H 1000 1460 50 0001 C CNN - 1 950 1500 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1250 1400 1350 1400 -Text Label 1350 1400 0 50 ~ 0 -Wall_5V -NoConn ~ 1250 1500 -Wire Wire Line - 1250 1600 1350 1600 -$Comp -L power:GND #PWR0113 -U 1 1 5E8980B4 -P 1350 1600 -F 0 "#PWR0113" H 1350 1350 50 0001 C CNN -F 1 "GND" H 1355 1427 50 0000 C CNN -F 2 "" H 1350 1600 50 0001 C CNN -F 3 "" H 1350 1600 50 0001 C CNN - 1 1350 1600 - 1 0 0 -1 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 5 1 5E84F3B3 -P 4950 5000 -F 0 "U1" H 4950 5915 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN -F 3 "" H 3750 6250 50 0001 C CNN - 5 4950 5000 - 1 0 0 -1 -$EndComp -Text Notes 3300 2350 0 50 ~ 0 -These are dummy loads!!! -Wire Wire Line - 4500 1800 3950 1800 -$Comp -L Device:R_Small R2 -U 1 1 5E8D1249 -P 3950 1900 -F 0 "R2" H 4009 1946 50 0000 L CNN -F 1 "100k" H 4009 1855 50 0000 L CNN -F 2 "" H 3950 1900 50 0001 C CNN -F 3 "~" H 3950 1900 50 0001 C CNN - 1 3950 1900 - 1 0 0 -1 -$EndComp -$Comp -L Device:R_Small R3 -U 1 1 5E8D1C92 -P 3950 2600 -F 0 "R3" H 4009 2646 50 0000 L CNN -F 1 "100k" H 4009 2555 50 0000 L CNN -F 2 "" H 3950 2600 50 0001 C CNN -F 3 "~" H 3950 2600 50 0001 C CNN - 1 3950 2600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 2000 3950 2050 -$Comp -L power:GND #PWR0114 -U 1 1 5E8D3DAD -P 3950 2050 -F 0 "#PWR0114" H 3950 1800 50 0001 C CNN -F 1 "GND" H 3955 1877 50 0000 C CNN -F 2 "" H 3950 2050 50 0001 C CNN -F 3 "" H 3950 2050 50 0001 C CNN - 1 3950 2050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 2700 3950 2750 -$Comp -L power:GND #PWR0115 -U 1 1 5E8D4B47 -P 3950 2750 -F 0 "#PWR0115" H 3950 2500 50 0001 C CNN -F 1 "GND" H 3955 2577 50 0000 C CNN -F 2 "" H 3950 2750 50 0001 C CNN -F 3 "" H 3950 2750 50 0001 C CNN - 1 3950 2750 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 1800 3550 1800 -Connection ~ 3950 1800 -Text Label 3550 1800 2 50 ~ 0 -USB_5v -Wire Wire Line - 3950 2500 3550 2500 -Connection ~ 3950 2500 -Text Label 3550 2500 2 50 ~ 0 -USB_3v3 -Wire Wire Line - 4900 2500 5800 2500 -Wire Wire Line - 4500 2500 4350 2500 -Wire Wire Line - 4900 1800 5350 1800 -$Comp -L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4 -U 1 1 5E7F2428 -P 8100 2250 -AR Path="/5E7F2428" Ref="U4" Part="1" -AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1" -F 0 "U4" H 8100 2665 50 0000 C CNN -F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN -F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN -F 3 "" H 8100 2250 50 0001 C CNN - 1 8100 2250 - 1 0 0 -1 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1 -U 1 1 5E9B8E9E -P 4700 1800 -F 0 "Q1" V 4950 1800 60 0000 C CNN -F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer" -F 12 "Active" H 4900 3000 60 0001 L CNN "Status" - 1 4700 1800 - 0 1 -1 0 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3 -U 1 1 5E9CBFD6 -P 6000 1800 -F 0 "Q3" V 6250 1800 60 0000 C CNN -F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer" -F 12 "Active" H 6200 3000 60 0001 L CNN "Status" - 1 6000 1800 - 0 -1 -1 0 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2 -U 1 1 5E9D56A5 -P 4700 2500 -F 0 "Q2" V 4950 2500 60 0000 C CNN -F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer" -F 12 "Active" H 4900 3700 60 0001 L CNN "Status" - 1 4700 2500 - 0 1 -1 0 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4 -U 1 1 5E9DB598 -P 6000 2500 -F 0 "Q4" V 6250 2500 60 0000 C CNN -F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer" -F 12 "Active" H 6200 3700 60 0001 L CNN "Status" - 1 6000 2500 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 4600 2800 5350 2800 -Wire Wire Line - 4600 2100 6100 2100 -Wire Wire Line - 4600 2100 4350 2100 -Wire Wire Line - 4350 2100 4350 2500 -Connection ~ 4600 2100 -Connection ~ 4350 2500 -Wire Wire Line - 4350 2500 3950 2500 -Wire Wire Line - 5350 1800 5350 2800 -Connection ~ 5350 1800 -Wire Wire Line - 5350 1800 5800 1800 -Connection ~ 5350 2800 -Wire Wire Line - 5350 2800 6100 2800 -Wire Wire Line - 5350 2800 5350 2900 -$Comp -L Device:R_Small R6 -U 1 1 5E9E8F6F -P 5350 3000 -F 0 "R6" H 5409 3046 50 0000 L CNN -F 1 "R_Small" H 5409 2955 50 0000 L CNN -F 2 "" H 5350 3000 50 0001 C CNN -F 3 "~" H 5350 3000 50 0001 C CNN - 1 5350 3000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5350 3100 5350 3150 -$Comp -L power:GND #PWR0117 -U 1 1 5E9EA130 -P 5350 3150 -F 0 "#PWR0117" H 5350 2900 50 0001 C CNN -F 1 "GND" H 5355 2977 50 0000 C CNN -F 2 "" H 5350 3150 50 0001 C CNN -F 3 "" H 5350 3150 50 0001 C CNN - 1 5350 3150 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6200 1800 6550 1800 -Wire Wire Line - 6550 2500 6200 2500 -Wire Wire Line - 6550 1800 6550 2100 -Connection ~ 6550 2100 -Wire Wire Line - 6550 2100 6550 2500 -$Comp -L Device:C_Small C10 -U 1 1 5E9F5727 -P 7050 2200 -F 0 "C10" H 7250 2250 50 0000 R CNN -F 1 "100nF" H 7350 2150 50 0000 R CNN -F 2 "" H 7050 2200 50 0001 C CNN -F 3 "~" H 7050 2200 50 0001 C CNN - 1 7050 2200 - -1 0 0 -1 -$EndComp -Wire Wire Line - 6550 2100 7050 2100 -Wire Wire Line - 7050 2100 7200 2100 -Connection ~ 7050 2100 -$Comp -L Device:C_Small C11 -U 1 1 5E9F9ED9 -P 7200 2200 -F 0 "C11" H 7292 2246 50 0000 L CNN -F 1 "1uF" H 7292 2155 50 0000 L CNN -F 2 "" H 7200 2200 50 0001 C CNN -F 3 "~" H 7200 2200 50 0001 C CNN - 1 7200 2200 - 1 0 0 -1 -$EndComp -Connection ~ 7200 2100 -Wire Wire Line - 7200 2100 7700 2100 -Wire Wire Line - 7700 2200 7700 2300 -Wire Wire Line - 7700 2300 7700 2400 -Connection ~ 7700 2300 -$Comp -L power:GND #PWR0118 -U 1 1 5EA05C9E -P 7700 2400 -F 0 "#PWR0118" H 7700 2150 50 0001 C CNN -F 1 "GND" H 7705 2227 50 0000 C CNN -F 2 "" H 7700 2400 50 0001 C CNN -F 3 "" H 7700 2400 50 0001 C CNN - 1 7700 2400 - 1 0 0 -1 -$EndComp -NoConn ~ 8500 2100 -Wire Wire Line - 8500 2200 8500 2300 -Wire Wire Line - 8500 2200 8650 2200 -Connection ~ 8500 2200 -Wire Wire Line - 7050 2300 7200 2300 -Wire Wire Line - 7200 2300 7700 2300 -Connection ~ 7200 2300 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 2 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5950 4350 5950 4450 +Connection ~ 5950 4450 +Wire Wire Line + 5950 4450 5950 4550 +Connection ~ 5950 4550 +Wire Wire Line + 5950 4550 5950 4650 +Connection ~ 5950 4650 +Wire Wire Line + 5950 4650 5950 4750 +Connection ~ 5950 4750 +Wire Wire Line + 5950 4750 5950 4850 +Connection ~ 5950 4850 +Wire Wire Line + 5950 4850 5950 4950 +Connection ~ 5950 4950 +Wire Wire Line + 5950 4950 5950 5050 +Connection ~ 5950 5050 +Wire Wire Line + 5950 5050 5950 5150 +Connection ~ 5950 5150 +Wire Wire Line + 5950 5150 5950 5250 +Wire Wire Line + 5950 5500 5950 5600 +Text HLabel 950 900 0 50 Input ~ 0 +USB_3v3 +Text HLabel 950 1050 0 50 Input ~ 0 +USB_5v +Text GLabel 950 600 0 50 Input ~ 0 +g_3v3 +Text GLabel 950 750 0 50 Input ~ 0 +g_5v +Wire Wire Line + 950 900 1350 900 +Text Label 1350 900 0 50 ~ 0 +USB_3v3 +Wire Wire Line + 950 1050 1350 1050 +Text Label 1350 1050 0 50 ~ 0 +USB_5v +Wire Wire Line + 950 600 1350 600 +Wire Wire Line + 950 750 1350 750 +Text Label 1350 600 0 50 ~ 0 +3v3Out +Text Label 1350 750 0 50 ~ 0 +5vOut +Wire Wire Line + 3950 5300 3950 5400 +Connection ~ 3950 5400 +Wire Wire Line + 3950 5400 3950 5500 +Connection ~ 3950 5500 +Wire Wire Line + 3950 5500 3950 5600 +Connection ~ 3950 5600 +Wire Wire Line + 3950 5600 3950 5700 +Connection ~ 3950 5700 +Wire Wire Line + 3950 5700 3950 5800 +Connection ~ 3950 5800 +Wire Wire Line + 3950 5800 3950 5900 +Connection ~ 3950 5900 +Wire Wire Line + 3950 5900 3950 6000 +$Comp +L Connector:Barrel_Jack_Switch J4 +U 1 1 5E88DD8C +P 950 1500 +F 0 "J4" H 1007 1817 50 0000 C CNN +F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN +F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN +F 3 "~" H 1000 1460 50 0001 C CNN + 1 950 1500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 1400 1350 1400 +Text Label 1350 1400 0 50 ~ 0 +Wall_5V +NoConn ~ 1250 1500 +Wire Wire Line + 1250 1600 1350 1600 +$Comp +L power:GND #PWR0113 +U 1 1 5E8980B4 +P 1350 1600 +F 0 "#PWR0113" H 1350 1350 50 0001 C CNN +F 1 "GND" H 1355 1427 50 0000 C CNN +F 2 "" H 1350 1600 50 0001 C CNN +F 3 "" H 1350 1600 50 0001 C CNN + 1 1350 1600 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 +U 5 1 5E84F3B3 +P 4950 5000 +F 0 "U1" H 4950 5915 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN +F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN +F 3 "" H 3750 6250 50 0001 C CNN + 5 4950 5000 + 1 0 0 -1 +$EndComp +Text Notes 3300 2350 0 50 ~ 0 +These are dummy loads!!! +Wire Wire Line + 4500 1800 3950 1800 +$Comp +L Device:R_Small R2 +U 1 1 5E8D1249 +P 3950 1900 +F 0 "R2" H 4009 1946 50 0000 L CNN +F 1 "100k" H 4009 1855 50 0000 L CNN +F 2 "" H 3950 1900 50 0001 C CNN +F 3 "~" H 3950 1900 50 0001 C CNN + 1 3950 1900 + 1 0 0 -1 +$EndComp +$Comp +L Device:R_Small R3 +U 1 1 5E8D1C92 +P 3950 2600 +F 0 "R3" H 4009 2646 50 0000 L CNN +F 1 "100k" H 4009 2555 50 0000 L CNN +F 2 "" H 3950 2600 50 0001 C CNN +F 3 "~" H 3950 2600 50 0001 C CNN + 1 3950 2600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 2000 3950 2050 +$Comp +L power:GND #PWR0114 +U 1 1 5E8D3DAD +P 3950 2050 +F 0 "#PWR0114" H 3950 1800 50 0001 C CNN +F 1 "GND" H 3955 1877 50 0000 C CNN +F 2 "" H 3950 2050 50 0001 C CNN +F 3 "" H 3950 2050 50 0001 C CNN + 1 3950 2050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 2700 3950 2750 +$Comp +L power:GND #PWR0115 +U 1 1 5E8D4B47 +P 3950 2750 +F 0 "#PWR0115" H 3950 2500 50 0001 C CNN +F 1 "GND" H 3955 2577 50 0000 C CNN +F 2 "" H 3950 2750 50 0001 C CNN +F 3 "" H 3950 2750 50 0001 C CNN + 1 3950 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 1800 3550 1800 +Connection ~ 3950 1800 +Text Label 3550 1800 2 50 ~ 0 +USB_5v +Wire Wire Line + 3950 2500 3550 2500 +Connection ~ 3950 2500 +Text Label 3550 2500 2 50 ~ 0 +USB_3v3 +Wire Wire Line + 4900 2500 5800 2500 +Wire Wire Line + 4500 2500 4350 2500 +Wire Wire Line + 4900 1800 5350 1800 +$Comp +L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4 +U 1 1 5E7F2428 +P 8100 2250 +AR Path="/5E7F2428" Ref="U4" Part="1" +AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1" +F 0 "U4" H 8100 2665 50 0000 C CNN +F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN +F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN +F 3 "" H 8100 2250 50 0001 C CNN + 1 8100 2250 + 1 0 0 -1 +$EndComp +$Comp +L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1 +U 1 1 5E9B8E9E +P 4700 1800 +F 0 "Q1" V 4950 1800 60 0000 C CNN +F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN +F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN +F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN +F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer" +F 12 "Active" H 4900 3000 60 0001 L CNN "Status" + 1 4700 1800 + 0 1 -1 0 +$EndComp +$Comp +L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3 +U 1 1 5E9CBFD6 +P 6000 1800 +F 0 "Q3" V 6250 1800 60 0000 C CNN +F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN +F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN +F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN +F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer" +F 12 "Active" H 6200 3000 60 0001 L CNN "Status" + 1 6000 1800 + 0 -1 -1 0 +$EndComp +$Comp +L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2 +U 1 1 5E9D56A5 +P 4700 2500 +F 0 "Q2" V 4950 2500 60 0000 C CNN +F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN +F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN +F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN +F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer" +F 12 "Active" H 4900 3700 60 0001 L CNN "Status" + 1 4700 2500 + 0 1 -1 0 +$EndComp +$Comp +L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4 +U 1 1 5E9DB598 +P 6000 2500 +F 0 "Q4" V 6250 2500 60 0000 C CNN +F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN +F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN +F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN +F 4 "IRLML6402PBFCT-ND" H 6200 2900 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 6200 3000 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 6200 3100 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 6200 3200 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 3300 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 3400 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 3500 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 6200 3600 60 0001 L CNN "Manufacturer" +F 12 "Active" H 6200 3700 60 0001 L CNN "Status" + 1 6000 2500 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4600 2800 5350 2800 +Wire Wire Line + 4600 2100 6100 2100 +Wire Wire Line + 4600 2100 4350 2100 +Wire Wire Line + 4350 2100 4350 2500 +Connection ~ 4600 2100 +Connection ~ 4350 2500 +Wire Wire Line + 4350 2500 3950 2500 +Wire Wire Line + 5350 1800 5350 2800 +Connection ~ 5350 1800 +Wire Wire Line + 5350 1800 5800 1800 +Connection ~ 5350 2800 +Wire Wire Line + 5350 2800 6100 2800 +Wire Wire Line + 5350 2800 5350 2900 +$Comp +L Device:R_Small R6 +U 1 1 5E9E8F6F +P 5350 3000 +F 0 "R6" H 5409 3046 50 0000 L CNN +F 1 "R_Small" H 5409 2955 50 0000 L CNN +F 2 "" H 5350 3000 50 0001 C CNN +F 3 "~" H 5350 3000 50 0001 C CNN + 1 5350 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3100 5350 3150 +$Comp +L power:GND #PWR0117 +U 1 1 5E9EA130 +P 5350 3150 +F 0 "#PWR0117" H 5350 2900 50 0001 C CNN +F 1 "GND" H 5355 2977 50 0000 C CNN +F 2 "" H 5350 3150 50 0001 C CNN +F 3 "" H 5350 3150 50 0001 C CNN + 1 5350 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 1800 6550 1800 +Wire Wire Line + 6550 2500 6200 2500 +Wire Wire Line + 6550 1800 6550 2100 +Connection ~ 6550 2100 +Wire Wire Line + 6550 2100 6550 2500 +$Comp +L Device:C_Small C10 +U 1 1 5E9F5727 +P 7050 2200 +F 0 "C10" H 7250 2250 50 0000 R CNN +F 1 "100nF" H 7350 2150 50 0000 R CNN +F 2 "" H 7050 2200 50 0001 C CNN +F 3 "~" H 7050 2200 50 0001 C CNN + 1 7050 2200 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6550 2100 7050 2100 +Wire Wire Line + 7050 2100 7200 2100 +Connection ~ 7050 2100 +$Comp +L Device:C_Small C11 +U 1 1 5E9F9ED9 +P 7200 2200 +F 0 "C11" H 7292 2246 50 0000 L CNN +F 1 "1uF" H 7292 2155 50 0000 L CNN +F 2 "" H 7200 2200 50 0001 C CNN +F 3 "~" H 7200 2200 50 0001 C CNN + 1 7200 2200 + 1 0 0 -1 +$EndComp +Connection ~ 7200 2100 +Wire Wire Line + 7200 2100 7700 2100 +Wire Wire Line + 7700 2200 7700 2300 +Wire Wire Line + 7700 2300 7700 2400 +Connection ~ 7700 2300 +$Comp +L power:GND #PWR0118 +U 1 1 5EA05C9E +P 7700 2400 +F 0 "#PWR0118" H 7700 2150 50 0001 C CNN +F 1 "GND" H 7705 2227 50 0000 C CNN +F 2 "" H 7700 2400 50 0001 C CNN +F 3 "" H 7700 2400 50 0001 C CNN + 1 7700 2400 + 1 0 0 -1 +$EndComp +NoConn ~ 8500 2100 +Wire Wire Line + 8500 2200 8500 2300 +Wire Wire Line + 8500 2200 8650 2200 +Connection ~ 8500 2200 +Wire Wire Line + 7050 2300 7200 2300 +Wire Wire Line + 7200 2300 7700 2300 +Connection ~ 7200 2300 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/Power.sch-bak b/electrical/same54_dev_board/Power.sch-bak index 956d777..c14db1d 100644 --- a/electrical/same54_dev_board/Power.sch-bak +++ b/electrical/same54_dev_board/Power.sch-bak @@ -1,401 +1,401 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 2 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 5950 4350 5950 4450 -Connection ~ 5950 4450 -Wire Wire Line - 5950 4450 5950 4550 -Connection ~ 5950 4550 -Wire Wire Line - 5950 4550 5950 4650 -Connection ~ 5950 4650 -Wire Wire Line - 5950 4650 5950 4750 -Connection ~ 5950 4750 -Wire Wire Line - 5950 4750 5950 4850 -Connection ~ 5950 4850 -Wire Wire Line - 5950 4850 5950 4950 -Connection ~ 5950 4950 -Wire Wire Line - 5950 4950 5950 5050 -Connection ~ 5950 5050 -Wire Wire Line - 5950 5050 5950 5150 -Connection ~ 5950 5150 -Wire Wire Line - 5950 5150 5950 5250 -Wire Wire Line - 5950 5500 5950 5600 -Text HLabel 950 900 0 50 Input ~ 0 -USB_3v3 -Text HLabel 950 1050 0 50 Input ~ 0 -USB_5v -Text GLabel 950 600 0 50 Input ~ 0 -g_3v3 -Text GLabel 950 750 0 50 Input ~ 0 -g_5v -Wire Wire Line - 950 900 1350 900 -Text Label 1350 900 0 50 ~ 0 -USB_3v3 -Wire Wire Line - 950 1050 1350 1050 -Text Label 1350 1050 0 50 ~ 0 -USB_5v -Wire Wire Line - 950 600 1350 600 -Wire Wire Line - 950 750 1350 750 -Text Label 1350 600 0 50 ~ 0 -3v3Out -Text Label 1350 750 0 50 ~ 0 -5vOut -Wire Wire Line - 3950 5300 3950 5400 -Connection ~ 3950 5400 -Wire Wire Line - 3950 5400 3950 5500 -Connection ~ 3950 5500 -Wire Wire Line - 3950 5500 3950 5600 -Connection ~ 3950 5600 -Wire Wire Line - 3950 5600 3950 5700 -Connection ~ 3950 5700 -Wire Wire Line - 3950 5700 3950 5800 -Connection ~ 3950 5800 -Wire Wire Line - 3950 5800 3950 5900 -Connection ~ 3950 5900 -Wire Wire Line - 3950 5900 3950 6000 -$Comp -L Connector:Barrel_Jack_Switch J4 -U 1 1 5E88DD8C -P 950 1500 -F 0 "J4" H 1007 1817 50 0000 C CNN -F 1 "Barrel_Jack_Switch" H 1007 1726 50 0000 C CNN -F 2 "digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A" H 1000 1460 50 0001 C CNN -F 3 "~" H 1000 1460 50 0001 C CNN - 1 950 1500 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1250 1400 1350 1400 -Text Label 1350 1400 0 50 ~ 0 -Wall_5V -NoConn ~ 1250 1500 -Wire Wire Line - 1250 1600 1350 1600 -$Comp -L power:GND #PWR0113 -U 1 1 5E8980B4 -P 1350 1600 -F 0 "#PWR0113" H 1350 1350 50 0001 C CNN -F 1 "GND" H 1355 1427 50 0000 C CNN -F 2 "" H 1350 1600 50 0001 C CNN -F 3 "" H 1350 1600 50 0001 C CNN - 1 1350 1600 - 1 0 0 -1 -$EndComp -$Comp -L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U1 -U 5 1 5E84F3B3 -P 4950 5000 -F 0 "U1" H 4950 5915 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 4950 5824 50 0000 C CNN -F 2 "penguin:QFP40P1600X1600X120-128N_ATSAME54P20A" H 3750 6250 50 0001 C CNN -F 3 "" H 3750 6250 50 0001 C CNN - 5 4950 5000 - 1 0 0 -1 -$EndComp -Text Notes 3300 2350 0 50 ~ 0 -These are dummy loads!!! -Wire Wire Line - 4500 1800 3950 1800 -$Comp -L Device:R_Small R2 -U 1 1 5E8D1249 -P 3950 1900 -F 0 "R2" H 4009 1946 50 0000 L CNN -F 1 "100k" H 4009 1855 50 0000 L CNN -F 2 "" H 3950 1900 50 0001 C CNN -F 3 "~" H 3950 1900 50 0001 C CNN - 1 3950 1900 - 1 0 0 -1 -$EndComp -$Comp -L Device:R_Small R3 -U 1 1 5E8D1C92 -P 3950 2600 -F 0 "R3" H 4009 2646 50 0000 L CNN -F 1 "100k" H 4009 2555 50 0000 L CNN -F 2 "" H 3950 2600 50 0001 C CNN -F 3 "~" H 3950 2600 50 0001 C CNN - 1 3950 2600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 2000 3950 2050 -$Comp -L power:GND #PWR0114 -U 1 1 5E8D3DAD -P 3950 2050 -F 0 "#PWR0114" H 3950 1800 50 0001 C CNN -F 1 "GND" H 3955 1877 50 0000 C CNN -F 2 "" H 3950 2050 50 0001 C CNN -F 3 "" H 3950 2050 50 0001 C CNN - 1 3950 2050 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 2700 3950 2750 -$Comp -L power:GND #PWR0115 -U 1 1 5E8D4B47 -P 3950 2750 -F 0 "#PWR0115" H 3950 2500 50 0001 C CNN -F 1 "GND" H 3955 2577 50 0000 C CNN -F 2 "" H 3950 2750 50 0001 C CNN -F 3 "" H 3950 2750 50 0001 C CNN - 1 3950 2750 - 1 0 0 -1 -$EndComp -Wire Wire Line - 3950 1800 3550 1800 -Connection ~ 3950 1800 -Text Label 3550 1800 2 50 ~ 0 -USB_5v -Wire Wire Line - 3950 2500 3550 2500 -Connection ~ 3950 2500 -Text Label 3550 2500 2 50 ~ 0 -USB_3v3 -Wire Wire Line - 4900 2500 5800 2500 -Wire Wire Line - 4500 2500 4350 2500 -Wire Wire Line - 4900 1800 5350 1800 -$Comp -L same54_dev_board-rescue:NCP349MNAETBG-NCP349MNAETBG U4 -U 1 1 5E7F2428 -P 8100 2250 -AR Path="/5E7F2428" Ref="U4" Part="1" -AR Path="/5E7872D3/5E7F2428" Ref="U4" Part="1" -F 0 "U4" H 8100 2665 50 0000 C CNN -F 1 "NCP349MNAETBG" H 8100 2574 50 0000 C CNN -F 2 "Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm" H 8100 2250 50 0001 C CNN -F 3 "" H 8100 2250 50 0001 C CNN - 1 8100 2250 - 1 0 0 -1 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q1 -U 1 1 5E9B8E9E -P 4700 1800 -F 0 "Q1" V 4950 1800 60 0000 C CNN -F 1 "Default PFET_A" V 4850 1800 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 4900 2000 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2100 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer" -F 12 "Active" H 4900 3000 60 0001 L CNN "Status" - 1 4700 1800 - 0 1 -1 0 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3 -U 1 1 5E9CBFD6 -P 6000 1800 -F 0 "Q3" V 6250 1800 60 0000 C CNN -F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer" -F 12 "Active" H 6200 3000 60 0001 L CNN "Status" - 1 6000 1800 - 0 -1 -1 0 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2 -U 1 1 5E9D56A5 -P 4700 2500 -F 0 "Q2" V 4950 2500 60 0000 C CNN -F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN -F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN" -F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN" -F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category" -F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family" -F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page" -F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description" -F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer" -F 12 "Active" H 4900 3700 60 0001 L CNN "Status" - 1 4700 2500 - 0 1 -1 0 -$EndComp -$Comp -L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q4 -U 1 1 5E9DB598 -P 6000 2500 -F 0 "Q4" V 6250 2500 60 0000 C CNN -F 1 "Alt PFET_B" V 6150 2500 60 0000 C CNN -F 2 "digikey-footprints:SOT-23-3" H 6200 2700 60 0001 L CNN -F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2800 60 0001 L CNN -F 4 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4 "IRLML6402PBFCT-ND" H 4900 2200 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 4900 2300 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 4900 2400 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 4900 2500 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2600 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 2700 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 2800 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 4900 2900 60 0001 L CNN "Manufacturer" +F 12 "Active" H 4900 3000 60 0001 L CNN "Status" + 1 4700 1800 + 0 1 -1 0 +$EndComp +$Comp +L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q3 +U 1 1 5E9CBFD6 +P 6000 1800 +F 0 "Q3" V 6250 1800 60 0000 C CNN +F 1 "Default PFET_B" V 6150 1800 60 0000 C CNN +F 2 "digikey-footprints:SOT-23-3" H 6200 2000 60 0001 L CNN +F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2100 60 0001 L CNN +F 4 "IRLML6402PBFCT-ND" H 6200 2200 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 6200 2300 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 6200 2400 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 6200 2500 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 6200 2600 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 6200 2700 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 6200 2800 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 6200 2900 60 0001 L CNN "Manufacturer" +F 12 "Active" H 6200 3000 60 0001 L CNN "Status" + 1 6000 1800 + 0 -1 -1 0 +$EndComp +$Comp +L dk_Transistors-FETs-MOSFETs-Single:IRLML6402TRPBF Q2 +U 1 1 5E9D56A5 +P 4700 2500 +F 0 "Q2" V 4950 2500 60 0000 C CNN +F 1 "Alt PFET_A" V 4850 2500 60 0000 C CNN +F 2 "digikey-footprints:SOT-23-3" H 4900 2700 60 0001 L CNN +F 3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 2800 60 0001 L CNN +F 4 "IRLML6402PBFCT-ND" H 4900 2900 60 0001 L CNN "Digi-Key_PN" +F 5 "IRLML6402TRPBF" H 4900 3000 60 0001 L CNN "MPN" +F 6 "Discrete Semiconductor Products" H 4900 3100 60 0001 L CNN "Category" +F 7 "Transistors - FETs, MOSFETs - Single" H 4900 3200 60 0001 L CNN "Family" +F 8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" H 4900 3300 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" H 4900 3400 60 0001 L CNN "DK_Detail_Page" +F 10 "MOSFET P-CH 20V 3.7A SOT-23" H 4900 3500 60 0001 L CNN "Description" +F 11 "Infineon Technologies" H 4900 3600 60 0001 L CNN "Manufacturer" +F 12 "Active" H 4900 3700 60 0001 L CNN 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power:GND #PWR0105 -U 1 1 5E88D5B3 -P 6150 3850 -F 0 "#PWR0105" H 6150 3600 50 0001 C CNN -F 1 "GND" H 6155 3677 50 0000 C CNN -F 2 "" H 6150 3850 50 0001 C CNN -F 3 "" H 6150 3850 50 0001 C CNN - 1 6150 3850 - 1 0 0 -1 -$EndComp -Entry Wire Line - 6300 4050 6400 4150 -Wire Wire Line - 6400 4150 6500 4150 -Wire Wire Line - 7900 5650 7900 5750 -$Comp -L power:GND #PWR0106 -U 1 1 5E89C68E -P 7900 5800 -F 0 "#PWR0106" H 7900 5550 50 0001 C CNN -F 1 "GND" H 7905 5627 50 0000 C CNN -F 2 "" H 7900 5800 50 0001 C CNN -F 3 "" H 7900 5800 50 0001 C CNN - 1 7900 5800 - 1 0 0 -1 -$EndComp -Entry Wire Line - 6300 4150 6400 4250 -Entry Wire Line - 6300 4250 6400 4350 -Entry Wire Line - 6300 4350 6400 4450 -Entry Wire Line - 6300 4450 6400 4550 -Entry Wire Line - 6300 4550 6400 4650 -Entry Wire Line - 6300 4650 6400 4750 -Entry Wire Line - 6300 4750 6400 4850 -Entry Wire Line - 6300 4850 6400 4950 -Entry Wire Line - 6300 4950 6400 5050 -Entry Wire Line - 6300 5050 6400 5150 -Entry Wire Line - 6300 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50 ~ 0 -D0 -Text Label 6400 4250 0 50 ~ 0 -D1 -Text Label 6400 4350 0 50 ~ 0 -D2 -Text Label 6400 4450 0 50 ~ 0 -D3 -Text Label 6400 4550 0 50 ~ 0 -D4 -Text Label 6400 4650 0 50 ~ 0 -D5 -Text Label 6400 4750 0 50 ~ 0 -D6 -Text Label 6400 4850 0 50 ~ 0 -D7 -Text Label 6400 4950 0 50 ~ 0 -D8 -Text Label 6400 5050 0 50 ~ 0 -D9 -Text Label 6400 5150 0 50 ~ 0 -D10 -Text Label 6400 5250 0 50 ~ 0 -D11 -Text Label 6400 5350 0 50 ~ 0 -D12 -Text Label 6400 5450 0 50 ~ 0 -D13 -Text Label 7900 4150 0 50 ~ 0 -D14 -Text Label 7900 4250 0 50 ~ 0 -D15 -Text Label 7900 4350 0 50 ~ 0 -D16 -Text Label 7900 4450 0 50 ~ 0 -D17 -Text Label 7900 4550 0 50 ~ 0 -D18 -Text Label 7900 4650 0 50 ~ 0 -D19 -Text Label 7900 4750 0 50 ~ 0 -D20 -Text Label 7900 4850 0 50 ~ 0 -D21 -Text Label 7900 4950 0 50 ~ 0 -D22 -Text Label 7900 5050 0 50 ~ 0 -D23 -Text Notes 7150 1150 0 50 ~ 0 -LCD INTF -- LCD Interface Section\n - D[0-23] represent data pins on the 8080 (parallel) bus\n - The MAX7301 is an IO expander acting as the data bus middleman\n between the brain and the ssd1963\n - The lcd control pins will still be controlled directly from the brain to alleviate timing issues and \n because its just going to be easier to debug\n - The MAX7301 is going to be run at something around 20MHz so we should be ok with timing -Wire Notes Line - 7100 550 11150 550 -Wire Notes Line - 11150 550 11150 2000 -Wire Notes Line - 11150 2000 7100 2000 -Wire Notes Line - 7100 2000 7100 550 -Entry Wire Line - 9050 3650 9150 3750 -Entry Wire Line - 9050 3750 9150 3850 -Entry Wire Line - 9050 3850 9150 3950 -Entry Wire Line - 9050 3950 9150 4050 -Entry Wire Line - 9050 4050 9150 4150 -Entry Wire Line - 9050 4150 9150 4250 -Entry Wire Line - 9050 4250 9150 4350 -Entry Wire Line - 9050 4350 9150 4450 -Entry Wire Line - 9050 4450 9150 4550 -Entry Wire Line - 9050 4550 9150 4650 -Entry Wire Line - 9050 4650 9150 4750 -Entry Wire Line - 9050 4750 9150 4850 -Wire Wire Line - 9150 3750 9300 3750 -Wire Wire Line - 9150 3850 9300 3850 -Wire Wire Line - 9150 3950 9300 3950 -Wire Wire Line - 9150 4050 9300 4050 -Wire Wire Line - 9150 4150 9300 4150 -Wire Wire Line - 9150 4250 9300 4250 -Wire Wire Line - 9150 4350 9300 4350 -Wire Wire Line - 9150 4450 9300 4450 -Wire Wire Line - 9150 4550 9300 4550 -Wire Wire Line - 9150 4650 9300 4650 -Wire Wire Line - 9150 4750 9300 4750 -Wire Wire Line - 9150 4850 9300 4850 -Wire Wire Line - 7900 4150 8100 4150 -Wire Wire Line - 7900 4250 8100 4250 -Wire Wire Line - 7900 4350 8100 4350 -Wire Wire Line - 7900 4450 8100 4450 -Wire Wire Line - 7900 4550 8100 4550 -Wire Wire Line - 7900 4650 8100 4650 -Wire Wire Line - 7900 4750 8100 4750 -Wire Wire Line - 7900 4850 8100 4850 -Wire Wire Line - 7900 4950 8100 4950 -Wire Wire Line - 7900 5050 8100 5050 -Wire Bus Line - 6300 6200 8200 6200 -NoConn ~ 7900 5150 -NoConn ~ 7900 5250 -NoConn ~ 7900 5350 -NoConn ~ 7900 5450 -Text Notes 7500 2650 0 50 ~ 0 -this looks atrocious but idk how to make busses vertical ,,, -$Comp -L MAX7301AAX_:MAX7301AAX+ U3 -U 1 1 5E86D6D7 -P 7200 4650 -F 0 "U3" H 7200 6120 50 0000 C CNN -F 1 "MAX7301AAX+" H 7200 6029 50 0000 C CNN -F 2 "proj_modules:SOP80P1030X264-36N" H 7200 4650 50 0001 L BNN -F 3 "https://datasheets.maximintegrated.com/en/ds/MAX7301.pdf" H 7200 4650 50 0001 L BNN -F 4 "None" H 7200 4650 50 0001 L BNN "Field4" -F 5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" H 7200 4650 50 0001 L BNN "Field5" -F 6 "SSOP-36 Maxim" H 7200 4650 50 0001 L BNN "Field6" -F 7 "Unavailable" H 7200 4650 50 0001 L BNN "Field7" -F 8 "MAX7301AAX+" H 7200 4650 50 0001 L BNN "Field8" - 1 7200 4650 - 1 0 0 -1 -$EndComp -Connection ~ 7900 5750 -Wire Wire Line - 7900 5750 7900 5800 -$Comp -L Device:C_Small C3 -U 1 1 5E988E9B -P 8200 3000 -F 0 "C3" H 8292 3046 50 0000 L CNN -F 1 "C_Small" H 8292 2955 50 0000 L CNN -F 2 "" H 8200 3000 50 0001 C CNN -F 3 "~" H 8200 3000 50 0001 C CNN - 1 8200 3000 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8200 2750 8200 2900 -Wire Wire Line - 8200 2900 7950 2900 -Connection ~ 8200 2900 -Wire Wire Line - 8200 3100 8200 3200 -$Comp -L power:GND #PWR0107 -U 1 1 5E98EDCE -P 8200 3200 -F 0 "#PWR0107" H 8200 2950 50 0001 C CNN -F 1 "GND" H 8205 3027 50 0000 C CNN -F 2 "" H 8200 3200 50 0001 C CNN -F 3 "" H 8200 3200 50 0001 C CNN - 1 8200 3200 - 1 0 0 -1 -$EndComp -Entry Wire Line - 10800 3750 10900 3650 -Entry Wire Line - 10800 3850 10900 3750 -Entry Wire Line - 10800 3950 10900 3850 -Entry Wire Line - 10800 4050 10900 3950 -Entry Wire Line - 10800 4150 10900 4050 -Entry Wire Line - 10800 4250 10900 4150 -Entry Wire Line - 10800 4350 10900 4250 -Entry Wire Line - 10800 4450 10900 4350 -Entry Wire Line - 10800 4550 10900 4450 -Entry Wire Line - 10800 4650 10900 4550 -Entry Wire Line - 10800 4750 10900 4650 -Entry Wire Line - 10800 4850 10900 4750 -Wire Wire Line - 10500 3750 10800 3750 -Wire Wire Line - 10500 3850 10800 3850 -Wire Wire Line - 10500 3950 10800 3950 -Wire Wire Line - 10500 4050 10800 4050 -Wire Wire Line - 10500 4150 10800 4150 -Wire Wire Line - 10500 4250 10800 4250 -Wire Wire Line - 10500 4350 10800 4350 -Wire Wire Line - 10500 4450 10800 4450 -Wire Wire Line - 10500 4550 10800 4550 -Wire Wire Line - 10500 4650 10800 4650 -Wire Wire Line - 10500 4750 10800 4750 -Wire Wire Line - 10500 4850 10800 4850 -Text Label 9150 3750 0 50 ~ 0 -D0 -Text Label 9150 3850 0 50 ~ 0 -D2 -Text Label 9150 3950 0 50 ~ 0 -D4 -Text Label 9150 4050 0 50 ~ 0 -D6 -Text Label 9150 4150 0 50 ~ 0 -D8 -Text Label 9150 4250 0 50 ~ 0 -D10 -Text Label 9150 4350 0 50 ~ 0 -D12 -Text Label 9150 4450 0 50 ~ 0 -D14 -Text Label 9150 4550 0 50 ~ 0 -D16 -Text Label 9150 4650 0 50 ~ 0 -D18 -Text Label 9150 4750 0 50 ~ 0 -D20 -Text Label 9150 4850 0 50 ~ 0 -D22 -Text Label 10550 3750 0 50 ~ 0 -D1 -Text Label 10550 3850 0 50 ~ 0 -D3 -Text Label 10550 3950 0 50 ~ 0 -D5 -Text Label 10550 4050 0 50 ~ 0 -D7 -Text Label 10550 4150 0 50 ~ 0 -D9 -Text Label 10550 4250 0 50 ~ 0 -D11 -Text Label 10550 4350 0 50 ~ 0 -D13 -Text Label 10550 4450 0 50 ~ 0 -D15 -Text Label 10550 4550 0 50 ~ 0 -D17 -Text Label 10550 4650 0 50 ~ 0 -D19 -Text Label 10550 4750 0 50 ~ 0 -D21 -Text Label 10550 4850 0 50 ~ 0 -D23 -Text Notes 650 650 0 50 ~ 0 -Power Interface -Wire Wire Line - 9300 3150 9250 3150 -Text Label 9250 3150 2 50 ~ 0 -3v3 -Text HLabel 1350 1450 0 50 Input ~ 0 -MASTER_SPI_CLK -Text HLabel 1350 1550 0 50 Input ~ 0 -MASTER_SPI_MISO -Text HLabel 1350 1650 0 50 Input ~ 0 -MASTER_SPI_MOSI -Text HLabel 1350 1750 0 50 Input ~ 0 -~IO_EXPANDER_CS -Text HLabel 1350 1900 0 50 Input ~ 0 -~TFT_CS -Text HLabel 1350 2000 0 50 Input ~ 0 -~TFT_RD -Text HLabel 1350 2100 0 50 Input ~ 0 -~TFT_WR -Text HLabel 1350 2200 0 50 Input ~ 0 -TFT_RSDC -Text HLabel 1350 2300 0 50 Input ~ 0 -~TFT_RST -Text HLabel 1350 2400 0 50 Input ~ 0 -TFT_STB -Text HLabel 1350 2700 0 50 Input ~ 0 -TFT_TOUCH_SDA -Text HLabel 1350 2800 0 50 Input ~ 0 -TFT_TOUCH_SCL -Text HLabel 1350 2600 0 50 Input ~ 0 -TFT_TOUCH_INT -Entry Bus Bus - 8450 4050 8550 3950 -Wire Wire Line - 9300 3650 9250 3650 -Wire Wire Line - 1350 1450 1600 1450 -Text Label 1600 1450 0 50 ~ 0 -IO_EXP_CLK -Text Label 1600 1550 0 50 ~ 0 -IO_EXP_DOUT -Wire Wire Line - 1600 1550 1350 1550 -Wire Wire Line - 1350 1650 1600 1650 -Text Label 1600 1650 0 50 ~ 0 -IO_EXP_DIN -Wire Wire Line - 1350 1750 1600 1750 -Text Label 1600 1750 0 50 ~ 0 -~IO_EXP_CS -Wire Wire Line - 1350 1900 1600 1900 -Text Label 1600 1900 0 50 ~ 0 -~TFT_CS -Text Label 1600 2000 0 50 ~ 0 -~TFT_RD -Wire Wire Line - 1600 2000 1350 2000 -Wire Wire Line - 1350 2100 1600 2100 -Text Label 1600 2100 0 50 ~ 0 -~TFT_WR -Text Label 1600 2200 0 50 ~ 0 -TFT_RSDC -Wire Wire Line - 1600 2200 1350 2200 -Wire Wire Line - 1350 2300 1600 2300 -Text Label 1600 2300 0 50 ~ 0 -~TFT_RST -Text Label 1600 2400 0 50 ~ 0 -TFT_STB -Wire Wire Line - 1600 2400 1350 2400 -Text Label 1600 2800 0 50 ~ 0 -TFT_TOUCH_SCL -Text Label 1600 2600 0 50 ~ 0 -TFT_TOUCH_INT -Wire Wire Line - 1600 2600 1350 2600 -Wire Wire Line - 7900 3650 8000 3650 -Text Label 8000 3650 0 50 ~ 0 -~IO_EXP_CS -Wire Wire Line - 7950 2900 7950 3450 -Wire Wire Line - 7900 3750 8000 3750 -Text Label 8000 3750 0 50 ~ 0 -IO_EXP_CLK -Wire Wire Line - 7900 3850 8000 3850 -Text Label 8000 3850 0 50 ~ 0 -IO_EXP_DIN -Wire Wire Line - 7900 3950 8000 3950 -Text Label 8000 3950 0 50 ~ 0 -IO_EXP_DOUT -Wire Wire Line - 10500 3550 10600 3550 -Text Label 10600 3550 0 50 ~ 0 -~TFT_WR -Text HLabel 1350 2500 0 50 Input ~ 0 -TFT_TE -Wire Wire Line - 1350 2500 1600 2500 -Text Label 1600 2500 0 50 ~ 0 -TFT_TE -Wire Wire Line - 10500 3450 10600 3450 -NoConn ~ 10500 3350 -Wire Wire Line - 10500 3250 10600 3250 -Text Label 10600 3250 0 50 ~ 0 -TFT_TOUCH_SDA -Wire Wire Line - 10500 3150 10600 3150 -Wire Wire Line - 10600 3150 10600 2500 -Wire Wire Line - 10600 2500 10850 2500 -Wire Wire Line - 10850 2500 10850 2650 -$Comp -L power:GND #PWR0109 -U 1 1 5EC6B772 -P 10850 2650 -F 0 "#PWR0109" H 10850 2400 50 0001 C CNN -F 1 "GND" H 10855 2477 50 0000 C CNN -F 2 "" H 10850 2650 50 0001 C CNN -F 3 "" H 10850 2650 50 0001 C CNN - 1 10850 2650 - 1 0 0 -1 -$EndComp -Wire Wire Line - 9300 3250 9250 3250 -Text Label 9250 3250 2 50 ~ 0 -TFT_TOUCH_SCL -Text Label 9250 3350 2 50 ~ 0 -TFT_TOUCH_INT -Wire Wire Line - 9250 3350 9300 3350 -Text Label 9250 3450 2 50 ~ 0 -~TFT_RST -Wire Wire Line - 9300 3450 9250 3450 -Wire Wire Line - 9300 3550 9250 3550 -Text Label 9250 3550 2 50 ~ 0 -~TFT_CS -Text Label 10600 3450 0 50 ~ 0 -TFT_RSDC -Text Label 10600 3650 0 50 ~ 0 -TFT_TE -Wire Wire Line - 10500 3650 10600 3650 -Text Label 9250 3650 2 50 ~ 0 -~TFT_RD -Wire Wire Line - 9300 4950 9200 4950 -Text Label 9200 4950 2 50 ~ 0 -TFT_STB -Wire Bus Line - 8850 5600 8850 4850 -Wire Bus Line - 8850 5600 10900 5600 -Entry Bus Bus - 8850 4850 8950 4750 -Wire Bus Line - 8950 4750 9050 4750 -Wire Bus Line - 8550 3950 8600 3950 -Entry Bus Bus - 8600 3950 8700 3850 -Wire Bus Line - 8700 3850 8750 3850 -Entry Bus Bus - 8750 3850 8850 3750 -Wire Bus Line - 8850 3750 8900 3750 -Wire Bus Line - 9000 3650 9050 3650 -Wire Bus Line - 8200 4050 8450 4050 -Entry Bus Bus - 8900 3750 9000 3650 -Wire Notes Line - 550 550 1350 550 -Wire Notes Line - 1350 550 1350 1200 -Wire Notes Line - 1350 1200 550 1200 -Wire Notes Line - 550 1200 550 550 -Wire Notes Line - 550 1250 550 3000 -Wire Notes Line - 2200 3000 2200 1250 -Wire Notes Line - 2200 1250 550 1250 -Text Notes 650 1350 0 50 ~ 0 -LCD Interface -Text Label 1600 2700 0 50 ~ 0 -TFT_TOUCH_SDA -Wire Wire Line - 1350 2700 1600 2700 -Wire Wire Line - 1350 2800 1600 2800 -Wire Notes Line - 2200 3000 550 3000 -Wire Bus Line - 9050 3650 9050 4750 -Wire Bus Line - 8200 4050 8200 6200 -Wire Bus Line - 6300 4050 6300 6200 -Wire Bus Line - 10900 3650 10900 5600 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 3 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Conn_02x20_LCD_INTF:Conn_02x20_Odd_Even_LCD_INTF J3 +U 1 1 5E858ED6 +P 9900 4050 +F 0 "J3" H 9900 5175 50 0000 C CNN +F 1 "Conn_02x20_Odd_Even_LCD_INTF" H 9900 5084 50 0000 C CNN +F 2 "Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal" H 9500 4050 50 0001 C CNN +F 3 "file:///home/penguin/Downloads/SSD1963_v1.6.pdf" H 9500 4050 50 0001 C CNN + 1 9900 4050 + 1 0 0 -1 +$EndComp +Text GLabel 900 750 0 50 Input ~ 0 +g_3v3 +Text GLabel 850 900 0 50 Input ~ 0 +g_5v +Wire Wire Line + 900 750 1150 750 +Text Label 1150 750 0 50 ~ 0 +3v3 +Wire Wire Line + 850 900 1150 900 +Text Label 1150 900 0 50 ~ 0 +5v +Wire Wire Line + 7900 3450 7950 3450 +Text Label 8200 2750 0 50 ~ 0 +3v3 +$Comp +L Device:R_Small R1 +U 1 1 5E889CF7 +P 6250 3650 +F 0 "R1" V 6054 3650 50 0000 C CNN +F 1 "39k" V 6145 3650 50 0000 C CNN +F 2 "" H 6250 3650 50 0001 C CNN +F 3 "~" H 6250 3650 50 0001 C CNN + 1 6250 3650 + 0 1 1 0 +$EndComp +Wire Wire Line + 6500 3650 6350 3650 +Wire Wire Line + 6150 3650 6150 3850 +$Comp +L power:GND #PWR0105 +U 1 1 5E88D5B3 +P 6150 3850 +F 0 "#PWR0105" H 6150 3600 50 0001 C CNN +F 1 "GND" H 6155 3677 50 0000 C CNN +F 2 "" H 6150 3850 50 0001 C CNN +F 3 "" H 6150 3850 50 0001 C CNN + 1 6150 3850 + 1 0 0 -1 +$EndComp +Entry Wire Line + 6300 4050 6400 4150 +Wire Wire Line + 6400 4150 6500 4150 +Wire Wire Line + 7900 5650 7900 5750 +$Comp +L power:GND #PWR0106 +U 1 1 5E89C68E +P 7900 5800 +F 0 "#PWR0106" H 7900 5550 50 0001 C CNN +F 1 "GND" H 7905 5627 50 0000 C CNN +F 2 "" H 7900 5800 50 0001 C CNN +F 3 "" H 7900 5800 50 0001 C CNN + 1 7900 5800 + 1 0 0 -1 +$EndComp +Entry Wire Line + 6300 4150 6400 4250 +Entry Wire Line + 6300 4250 6400 4350 +Entry Wire Line + 6300 4350 6400 4450 +Entry Wire Line + 6300 4450 6400 4550 +Entry Wire Line + 6300 4550 6400 4650 +Entry Wire Line + 6300 4650 6400 4750 +Entry Wire Line + 6300 4750 6400 4850 +Entry Wire Line + 6300 4850 6400 4950 +Entry Wire Line + 6300 4950 6400 5050 +Entry Wire Line + 6300 5050 6400 5150 +Entry Wire Line + 6300 5150 6400 5250 +Entry Wire Line + 6300 5250 6400 5350 +Entry Wire Line + 6300 5350 6400 5450 +Entry Wire Line + 8200 4050 8100 4150 +Entry Wire Line + 8200 4150 8100 4250 +Entry Wire Line + 8200 4250 8100 4350 +Entry Wire Line + 8200 4350 8100 4450 +Entry Wire Line + 8200 4450 8100 4550 +Entry Wire Line + 8200 4550 8100 4650 +Entry Wire Line + 8200 4650 8100 4750 +Entry Wire Line + 8200 4750 8100 4850 +Entry Wire Line + 8200 4850 8100 4950 +Entry Wire Line + 8200 4950 8100 5050 +Wire Wire Line + 6400 4250 6500 4250 +Wire Wire Line + 6400 4350 6500 4350 +Wire Wire Line + 6400 4450 6500 4450 +Wire Wire Line + 6400 4550 6500 4550 +Wire Wire Line + 6400 4650 6500 4650 +Wire Wire Line + 6400 4750 6500 4750 +Wire Wire Line + 6400 4850 6500 4850 +Wire Wire Line + 6400 4950 6500 4950 +Wire Wire Line + 6400 5050 6500 5050 +Wire Wire Line + 6400 5150 6500 5150 +Wire Wire Line + 6400 5250 6500 5250 +Wire Wire Line + 6400 5350 6500 5350 +Wire Wire Line + 6400 5450 6500 5450 +Text Label 6400 4150 0 50 ~ 0 +D0 +Text Label 6400 4250 0 50 ~ 0 +D1 +Text Label 6400 4350 0 50 ~ 0 +D2 +Text Label 6400 4450 0 50 ~ 0 +D3 +Text Label 6400 4550 0 50 ~ 0 +D4 +Text Label 6400 4650 0 50 ~ 0 +D5 +Text Label 6400 4750 0 50 ~ 0 +D6 +Text Label 6400 4850 0 50 ~ 0 +D7 +Text Label 6400 4950 0 50 ~ 0 +D8 +Text Label 6400 5050 0 50 ~ 0 +D9 +Text Label 6400 5150 0 50 ~ 0 +D10 +Text Label 6400 5250 0 50 ~ 0 +D11 +Text Label 6400 5350 0 50 ~ 0 +D12 +Text Label 6400 5450 0 50 ~ 0 +D13 +Text Label 7900 4150 0 50 ~ 0 +D14 +Text Label 7900 4250 0 50 ~ 0 +D15 +Text Label 7900 4350 0 50 ~ 0 +D16 +Text Label 7900 4450 0 50 ~ 0 +D17 +Text Label 7900 4550 0 50 ~ 0 +D18 +Text Label 7900 4650 0 50 ~ 0 +D19 +Text Label 7900 4750 0 50 ~ 0 +D20 +Text Label 7900 4850 0 50 ~ 0 +D21 +Text Label 7900 4950 0 50 ~ 0 +D22 +Text Label 7900 5050 0 50 ~ 0 +D23 +Text Notes 7150 1150 0 50 ~ 0 +LCD INTF -- LCD Interface Section\n - D[0-23] represent data pins on the 8080 (parallel) bus\n - The MAX7301 is an IO expander acting as the data bus middleman\n between the brain and the ssd1963\n - The lcd control pins will still be controlled directly from the brain to alleviate timing issues and \n because its just going to be easier to debug\n - The MAX7301 is going to be run at something around 20MHz so we should be ok with timing +Wire Notes Line + 7100 550 11150 550 +Wire Notes Line + 11150 550 11150 2000 +Wire Notes Line + 11150 2000 7100 2000 +Wire Notes Line + 7100 2000 7100 550 +Entry Wire Line + 9050 3650 9150 3750 +Entry Wire Line + 9050 3750 9150 3850 +Entry Wire Line + 9050 3850 9150 3950 +Entry Wire Line + 9050 3950 9150 4050 +Entry Wire Line + 9050 4050 9150 4150 +Entry Wire Line + 9050 4150 9150 4250 +Entry Wire Line + 9050 4250 9150 4350 +Entry Wire Line + 9050 4350 9150 4450 +Entry Wire Line + 9050 4450 9150 4550 +Entry Wire Line + 9050 4550 9150 4650 +Entry Wire Line + 9050 4650 9150 4750 +Entry Wire Line + 9050 4750 9150 4850 +Wire Wire Line + 9150 3750 9300 3750 +Wire Wire Line + 9150 3850 9300 3850 +Wire Wire Line + 9150 3950 9300 3950 +Wire Wire Line + 9150 4050 9300 4050 +Wire Wire Line + 9150 4150 9300 4150 +Wire Wire Line + 9150 4250 9300 4250 +Wire Wire Line + 9150 4350 9300 4350 +Wire Wire Line + 9150 4450 9300 4450 +Wire Wire Line + 9150 4550 9300 4550 +Wire Wire Line + 9150 4650 9300 4650 +Wire Wire Line + 9150 4750 9300 4750 +Wire Wire Line + 9150 4850 9300 4850 +Wire Wire Line + 7900 4150 8100 4150 +Wire Wire Line + 7900 4250 8100 4250 +Wire Wire Line + 7900 4350 8100 4350 +Wire Wire Line + 7900 4450 8100 4450 +Wire Wire Line + 7900 4550 8100 4550 +Wire Wire Line + 7900 4650 8100 4650 +Wire Wire Line + 7900 4750 8100 4750 +Wire Wire Line + 7900 4850 8100 4850 +Wire Wire Line + 7900 4950 8100 4950 +Wire Wire Line + 7900 5050 8100 5050 +Wire Bus Line + 6300 6200 8200 6200 +NoConn ~ 7900 5150 +NoConn ~ 7900 5250 +NoConn ~ 7900 5350 +NoConn ~ 7900 5450 +Text Notes 7500 2650 0 50 ~ 0 +this looks atrocious but idk how to make busses vertical ,,, +$Comp +L MAX7301AAX_:MAX7301AAX+ U3 +U 1 1 5E86D6D7 +P 7200 4650 +F 0 "U3" H 7200 6120 50 0000 C CNN +F 1 "MAX7301AAX+" H 7200 6029 50 0000 C CNN +F 2 "proj_modules:SOP80P1030X264-36N" H 7200 4650 50 0001 L BNN +F 3 "https://datasheets.maximintegrated.com/en/ds/MAX7301.pdf" H 7200 4650 50 0001 L BNN +F 4 "None" H 7200 4650 50 0001 L BNN "Field4" +F 5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" H 7200 4650 50 0001 L BNN "Field5" +F 6 "SSOP-36 Maxim" H 7200 4650 50 0001 L BNN "Field6" +F 7 "Unavailable" H 7200 4650 50 0001 L BNN "Field7" +F 8 "MAX7301AAX+" H 7200 4650 50 0001 L BNN "Field8" + 1 7200 4650 + 1 0 0 -1 +$EndComp +Connection ~ 7900 5750 +Wire Wire Line + 7900 5750 7900 5800 +$Comp +L Device:C_Small C3 +U 1 1 5E988E9B +P 8200 3000 +F 0 "C3" H 8292 3046 50 0000 L CNN +F 1 "C_Small" H 8292 2955 50 0000 L CNN +F 2 "" H 8200 3000 50 0001 C CNN +F 3 "~" H 8200 3000 50 0001 C CNN + 1 8200 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 2750 8200 2900 +Wire Wire Line + 8200 2900 7950 2900 +Connection ~ 8200 2900 +Wire Wire Line + 8200 3100 8200 3200 +$Comp +L power:GND #PWR0107 +U 1 1 5E98EDCE +P 8200 3200 +F 0 "#PWR0107" H 8200 2950 50 0001 C CNN +F 1 "GND" H 8205 3027 50 0000 C CNN +F 2 "" H 8200 3200 50 0001 C CNN +F 3 "" H 8200 3200 50 0001 C CNN + 1 8200 3200 + 1 0 0 -1 +$EndComp +Entry Wire Line + 10800 3750 10900 3650 +Entry Wire Line + 10800 3850 10900 3750 +Entry Wire Line + 10800 3950 10900 3850 +Entry Wire Line + 10800 4050 10900 3950 +Entry Wire Line + 10800 4150 10900 4050 +Entry Wire Line + 10800 4250 10900 4150 +Entry Wire Line + 10800 4350 10900 4250 +Entry Wire Line + 10800 4450 10900 4350 +Entry Wire Line + 10800 4550 10900 4450 +Entry Wire Line + 10800 4650 10900 4550 +Entry Wire Line + 10800 4750 10900 4650 +Entry Wire Line + 10800 4850 10900 4750 +Wire Wire Line + 10500 3750 10800 3750 +Wire Wire Line + 10500 3850 10800 3850 +Wire Wire Line + 10500 3950 10800 3950 +Wire Wire Line + 10500 4050 10800 4050 +Wire Wire Line + 10500 4150 10800 4150 +Wire Wire Line + 10500 4250 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Bus + 8900 3750 9000 3650 +Wire Notes Line + 550 550 1350 550 +Wire Notes Line + 1350 550 1350 1200 +Wire Notes Line + 1350 1200 550 1200 +Wire Notes Line + 550 1200 550 550 +Wire Notes Line + 550 1250 550 3000 +Wire Notes Line + 2200 3000 2200 1250 +Wire Notes Line + 2200 1250 550 1250 +Text Notes 650 1350 0 50 ~ 0 +LCD Interface +Text Label 1600 2700 0 50 ~ 0 +TFT_TOUCH_SDA +Wire Wire Line + 1350 2700 1600 2700 +Wire Wire Line + 1350 2800 1600 2800 +Wire Notes Line + 2200 3000 550 3000 +Wire Bus Line + 9050 3650 9050 4750 +Wire Bus Line + 8200 4050 8200 6200 +Wire Bus Line + 6300 4050 6300 6200 +Wire Bus Line + 10900 3650 10900 5600 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/SCREEN_INTF.sch-bak b/electrical/same54_dev_board/SCREEN_INTF.sch-bak index 811fbf4..4602dc9 100644 --- a/electrical/same54_dev_board/SCREEN_INTF.sch-bak +++ b/electrical/same54_dev_board/SCREEN_INTF.sch-bak @@ -1,656 +1,656 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 3 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L Conn_02x20_LCD_INTF:Conn_02x20_Odd_Even_LCD_INTF J3 -U 1 1 5E858ED6 -P 9900 4050 -F 0 "J3" H 9900 5175 50 0000 C CNN -F 1 "Conn_02x20_Odd_Even_LCD_INTF" H 9900 5084 50 0000 C CNN -F 2 "Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal" H 9500 4050 50 0001 C CNN -F 3 "file:///home/penguin/Downloads/SSD1963_v1.6.pdf" H 9500 4050 50 0001 C CNN - 1 9900 4050 - 1 0 0 -1 -$EndComp -Text GLabel 900 750 0 50 Input ~ 0 -g_3v3 -Text GLabel 850 900 0 50 Input ~ 0 -g_5v -Wire Wire Line - 900 750 1150 750 -Text Label 1150 750 0 50 ~ 0 -3v3 -Wire Wire Line - 850 900 1150 900 -Text Label 1150 900 0 50 ~ 0 -5v -Wire Wire Line - 7900 3450 7950 3450 -Text Label 8200 2750 0 50 ~ 0 -3v3 -$Comp -L Device:R_Small R1 -U 1 1 5E889CF7 -P 6250 3650 -F 0 "R1" V 6054 3650 50 0000 C CNN -F 1 "39k" V 6145 3650 50 0000 C CNN -F 2 "" H 6250 3650 50 0001 C CNN -F 3 "~" H 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6500 5150 -Wire Wire Line - 6400 5250 6500 5250 -Wire Wire Line - 6400 5350 6500 5350 -Wire Wire Line - 6400 5450 6500 5450 -Text Label 6400 4150 0 50 ~ 0 -D0 -Text Label 6400 4250 0 50 ~ 0 -D1 -Text Label 6400 4350 0 50 ~ 0 -D2 -Text Label 6400 4450 0 50 ~ 0 -D3 -Text Label 6400 4550 0 50 ~ 0 -D4 -Text Label 6400 4650 0 50 ~ 0 -D5 -Text Label 6400 4750 0 50 ~ 0 -D6 -Text Label 6400 4850 0 50 ~ 0 -D7 -Text Label 6400 4950 0 50 ~ 0 -D8 -Text Label 6400 5050 0 50 ~ 0 -D9 -Text Label 6400 5150 0 50 ~ 0 -D10 -Text Label 6400 5250 0 50 ~ 0 -D11 -Text Label 6400 5350 0 50 ~ 0 -D12 -Text Label 6400 5450 0 50 ~ 0 -D13 -Text Label 7900 4150 0 50 ~ 0 -D14 -Text Label 7900 4250 0 50 ~ 0 -D15 -Text Label 7900 4350 0 50 ~ 0 -D16 -Text Label 7900 4450 0 50 ~ 0 -D17 -Text Label 7900 4550 0 50 ~ 0 -D18 -Text Label 7900 4650 0 50 ~ 0 -D19 -Text Label 7900 4750 0 50 ~ 0 -D20 -Text Label 7900 4850 0 50 ~ 0 -D21 -Text Label 7900 4950 0 50 ~ 0 -D22 -Text Label 7900 5050 0 50 ~ 0 -D23 -Text Notes 7150 1150 0 50 ~ 0 -LCD INTF -- LCD Interface Section\n - D[0-23] represent data pins on the 8080 (parallel) bus\n - The MAX7301 is an IO expander acting as the data bus middleman\n between the brain and the ssd1963\n - The lcd control pins will still be controlled directly from the brain to alleviate timing issues and \n because its just going to be easier to debug\n - The MAX7301 is going to be run at something around 20MHz so we should be ok with timing -Wire Notes Line - 7100 550 11150 550 -Wire Notes Line - 11150 550 11150 2000 -Wire Notes Line - 11150 2000 7100 2000 -Wire Notes Line - 7100 2000 7100 550 -Entry Wire Line - 9050 3650 9150 3750 -Entry Wire Line - 9050 3750 9150 3850 -Entry Wire Line - 9050 3850 9150 3950 -Entry Wire Line - 9050 3950 9150 4050 -Entry Wire Line - 9050 4050 9150 4150 -Entry Wire Line - 9050 4150 9150 4250 -Entry Wire Line - 9050 4250 9150 4350 -Entry Wire Line - 9050 4350 9150 4450 -Entry Wire Line - 9050 4450 9150 4550 -Entry Wire Line - 9050 4550 9150 4650 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7900 5350 -NoConn ~ 7900 5450 -Text Notes 7500 2650 0 50 ~ 0 -this looks atrocious but idk how to make busses vertical ,,, -$Comp -L MAX7301AAX_:MAX7301AAX+ U3 -U 1 1 5E86D6D7 -P 7200 4650 -F 0 "U3" H 7200 6120 50 0000 C CNN -F 1 "MAX7301AAX+" H 7200 6029 50 0000 C CNN -F 2 "proj_modules:SOP80P1030X264-36N" H 7200 4650 50 0001 L BNN -F 3 "https://datasheets.maximintegrated.com/en/ds/MAX7301.pdf" H 7200 4650 50 0001 L BNN -F 4 "None" H 7200 4650 50 0001 L BNN "Field4" -F 5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" H 7200 4650 50 0001 L BNN "Field5" -F 6 "SSOP-36 Maxim" H 7200 4650 50 0001 L BNN "Field6" -F 7 "Unavailable" H 7200 4650 50 0001 L BNN "Field7" -F 8 "MAX7301AAX+" H 7200 4650 50 0001 L BNN "Field8" - 1 7200 4650 - 1 0 0 -1 -$EndComp -Connection ~ 7900 5750 -Wire Wire Line - 7900 5750 7900 5800 -$Comp -L Device:C_Small C3 -U 1 1 5E988E9B -P 8200 3000 -F 0 "C3" H 8292 3046 50 0000 L CNN -F 1 "C_Small" H 8292 2955 50 0000 L CNN -F 2 "" H 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3950 8700 3850 -Wire Bus Line - 8700 3850 8750 3850 -Entry Bus Bus - 8750 3850 8850 3750 -Wire Bus Line - 8850 3750 8900 3750 -Wire Bus Line - 9000 3650 9050 3650 -Wire Bus Line - 8200 4050 8450 4050 -Entry Bus Bus - 8900 3750 9000 3650 -Wire Notes Line - 550 550 1350 550 -Wire Notes Line - 1350 550 1350 1200 -Wire Notes Line - 1350 1200 550 1200 -Wire Notes Line - 550 1200 550 550 -Wire Notes Line - 550 1250 550 3000 -Wire Notes Line - 2200 3000 2200 1250 -Wire Notes Line - 2200 1250 550 1250 -Text Notes 650 1350 0 50 ~ 0 -LCD Interface -Text Label 1600 2700 0 50 ~ 0 -TFT_TOUCH_SDA -Wire Wire Line - 1350 2700 1600 2700 -Wire Wire Line - 1350 2800 1600 2800 -Wire Notes Line - 2200 3000 550 3000 -Wire Bus Line - 9050 3650 9050 4750 -Wire Bus Line - 8200 4050 8200 6200 -Wire Bus Line - 6300 4050 6300 6200 -Wire Bus Line - 10900 3650 10900 5600 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 3 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Conn_02x20_LCD_INTF:Conn_02x20_Odd_Even_LCD_INTF J3 +U 1 1 5E858ED6 +P 9900 4050 +F 0 "J3" H 9900 5175 50 0000 C CNN +F 1 "Conn_02x20_Odd_Even_LCD_INTF" H 9900 5084 50 0000 C CNN +F 2 "Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal" H 9500 4050 50 0001 C CNN +F 3 "file:///home/penguin/Downloads/SSD1963_v1.6.pdf" H 9500 4050 50 0001 C CNN + 1 9900 4050 + 1 0 0 -1 +$EndComp +Text GLabel 900 750 0 50 Input ~ 0 +g_3v3 +Text GLabel 850 900 0 50 Input ~ 0 +g_5v +Wire Wire Line + 900 750 1150 750 +Text Label 1150 750 0 50 ~ 0 +3v3 +Wire Wire Line + 850 900 1150 900 +Text Label 1150 900 0 50 ~ 0 +5v +Wire Wire Line + 7900 3450 7950 3450 +Text Label 8200 2750 0 50 ~ 0 +3v3 +$Comp +L Device:R_Small R1 +U 1 1 5E889CF7 +P 6250 3650 +F 0 "R1" V 6054 3650 50 0000 C CNN +F 1 "39k" V 6145 3650 50 0000 C CNN +F 2 "" H 6250 3650 50 0001 C CNN +F 3 "~" H 6250 3650 50 0001 C CNN + 1 6250 3650 + 0 1 1 0 +$EndComp +Wire Wire Line + 6500 3650 6350 3650 +Wire Wire Line + 6150 3650 6150 3850 +$Comp +L power:GND #PWR0105 +U 1 1 5E88D5B3 +P 6150 3850 +F 0 "#PWR0105" H 6150 3600 50 0001 C CNN +F 1 "GND" H 6155 3677 50 0000 C CNN +F 2 "" H 6150 3850 50 0001 C CNN +F 3 "" H 6150 3850 50 0001 C CNN + 1 6150 3850 + 1 0 0 -1 +$EndComp +Entry Wire Line + 6300 4050 6400 4150 +Wire Wire Line + 6400 4150 6500 4150 +Wire Wire Line + 7900 5650 7900 5750 +$Comp +L power:GND #PWR0106 +U 1 1 5E89C68E +P 7900 5800 +F 0 "#PWR0106" H 7900 5550 50 0001 C CNN +F 1 "GND" H 7905 5627 50 0000 C CNN +F 2 "" H 7900 5800 50 0001 C CNN +F 3 "" H 7900 5800 50 0001 C CNN + 1 7900 5800 + 1 0 0 -1 +$EndComp +Entry Wire Line + 6300 4150 6400 4250 +Entry Wire Line + 6300 4250 6400 4350 +Entry Wire Line + 6300 4350 6400 4450 +Entry Wire Line + 6300 4450 6400 4550 +Entry Wire Line + 6300 4550 6400 4650 +Entry Wire Line + 6300 4650 6400 4750 +Entry Wire Line + 6300 4750 6400 4850 +Entry Wire Line + 6300 4850 6400 4950 +Entry Wire Line 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Line + 6400 5350 6500 5350 +Wire Wire Line + 6400 5450 6500 5450 +Text Label 6400 4150 0 50 ~ 0 +D0 +Text Label 6400 4250 0 50 ~ 0 +D1 +Text Label 6400 4350 0 50 ~ 0 +D2 +Text Label 6400 4450 0 50 ~ 0 +D3 +Text Label 6400 4550 0 50 ~ 0 +D4 +Text Label 6400 4650 0 50 ~ 0 +D5 +Text Label 6400 4750 0 50 ~ 0 +D6 +Text Label 6400 4850 0 50 ~ 0 +D7 +Text Label 6400 4950 0 50 ~ 0 +D8 +Text Label 6400 5050 0 50 ~ 0 +D9 +Text Label 6400 5150 0 50 ~ 0 +D10 +Text Label 6400 5250 0 50 ~ 0 +D11 +Text Label 6400 5350 0 50 ~ 0 +D12 +Text Label 6400 5450 0 50 ~ 0 +D13 +Text Label 7900 4150 0 50 ~ 0 +D14 +Text Label 7900 4250 0 50 ~ 0 +D15 +Text Label 7900 4350 0 50 ~ 0 +D16 +Text Label 7900 4450 0 50 ~ 0 +D17 +Text Label 7900 4550 0 50 ~ 0 +D18 +Text Label 7900 4650 0 50 ~ 0 +D19 +Text Label 7900 4750 0 50 ~ 0 +D20 +Text Label 7900 4850 0 50 ~ 0 +D21 +Text Label 7900 4950 0 50 ~ 0 +D22 +Text Label 7900 5050 0 50 ~ 0 +D23 +Text Notes 7150 1150 0 50 ~ 0 +LCD INTF -- LCD Interface Section\n - D[0-23] represent data pins on the 8080 (parallel) bus\n - The MAX7301 is an IO expander acting as the data bus middleman\n between the brain and the ssd1963\n - The lcd control pins will still be controlled directly from the brain to alleviate timing issues and \n because its just going to be easier to debug\n - The MAX7301 is going to be run at something around 20MHz so we should be ok with timing +Wire Notes Line + 7100 550 11150 550 +Wire Notes Line + 11150 550 11150 2000 +Wire Notes Line + 11150 2000 7100 2000 +Wire Notes Line + 7100 2000 7100 550 +Entry Wire Line + 9050 3650 9150 3750 +Entry Wire Line + 9050 3750 9150 3850 +Entry Wire Line + 9050 3850 9150 3950 +Entry Wire Line + 9050 3950 9150 4050 +Entry Wire Line + 9050 4050 9150 4150 +Entry Wire Line + 9050 4150 9150 4250 +Entry Wire Line + 9050 4250 9150 4350 +Entry Wire Line + 9050 4350 9150 4450 +Entry Wire Line + 9050 4450 9150 4550 +Entry Wire Line + 9050 4550 9150 4650 +Entry Wire Line + 9050 4650 9150 4750 +Entry Wire Line + 9050 4750 9150 4850 +Wire Wire Line + 9150 3750 9300 3750 +Wire Wire Line + 9150 3850 9300 3850 +Wire Wire Line + 9150 3950 9300 3950 +Wire Wire Line + 9150 4050 9300 4050 +Wire Wire Line + 9150 4150 9300 4150 +Wire Wire Line + 9150 4250 9300 4250 +Wire Wire Line + 9150 4350 9300 4350 +Wire Wire Line + 9150 4450 9300 4450 +Wire Wire Line + 9150 4550 9300 4550 +Wire Wire Line + 9150 4650 9300 4650 +Wire Wire Line + 9150 4750 9300 4750 +Wire Wire Line + 9150 4850 9300 4850 +Wire Wire Line + 7900 4150 8100 4150 +Wire Wire Line + 7900 4250 8100 4250 +Wire Wire Line + 7900 4350 8100 4350 +Wire Wire Line + 7900 4450 8100 4450 +Wire Wire Line + 7900 4550 8100 4550 +Wire Wire Line + 7900 4650 8100 4650 +Wire Wire Line + 7900 4750 8100 4750 +Wire Wire Line + 7900 4850 8100 4850 +Wire Wire Line + 7900 4950 8100 4950 +Wire Wire Line + 7900 5050 8100 5050 +Wire Bus Line + 6300 6200 8200 6200 +NoConn ~ 7900 5150 +NoConn ~ 7900 5250 +NoConn ~ 7900 5350 +NoConn ~ 7900 5450 +Text Notes 7500 2650 0 50 ~ 0 +this looks atrocious but idk how to make busses vertical ,,, +$Comp +L MAX7301AAX_:MAX7301AAX+ U3 +U 1 1 5E86D6D7 +P 7200 4650 +F 0 "U3" H 7200 6120 50 0000 C CNN +F 1 "MAX7301AAX+" H 7200 6029 50 0000 C CNN +F 2 "proj_modules:SOP80P1030X264-36N" H 7200 4650 50 0001 L BNN +F 3 "https://datasheets.maximintegrated.com/en/ds/MAX7301.pdf" H 7200 4650 50 0001 L BNN +F 4 "None" H 7200 4650 50 0001 L BNN "Field4" +F 5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" H 7200 4650 50 0001 L BNN "Field5" +F 6 "SSOP-36 Maxim" H 7200 4650 50 0001 L BNN "Field6" +F 7 "Unavailable" H 7200 4650 50 0001 L BNN "Field7" +F 8 "MAX7301AAX+" H 7200 4650 50 0001 L BNN "Field8" + 1 7200 4650 + 1 0 0 -1 +$EndComp +Connection ~ 7900 5750 +Wire Wire Line + 7900 5750 7900 5800 +$Comp +L Device:C_Small C3 +U 1 1 5E988E9B +P 8200 3000 +F 0 "C3" H 8292 3046 50 0000 L CNN +F 1 "C_Small" H 8292 2955 50 0000 L CNN +F 2 "" H 8200 3000 50 0001 C CNN +F 3 "~" H 8200 3000 50 0001 C CNN + 1 8200 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 2750 8200 2900 +Wire Wire Line + 8200 2900 7950 2900 +Connection ~ 8200 2900 +Wire Wire Line + 8200 3100 8200 3200 +$Comp +L power:GND #PWR0107 +U 1 1 5E98EDCE +P 8200 3200 +F 0 "#PWR0107" H 8200 2950 50 0001 C CNN +F 1 "GND" H 8205 3027 50 0000 C CNN +F 2 "" H 8200 3200 50 0001 C CNN +F 3 "" H 8200 3200 50 0001 C CNN + 1 8200 3200 + 1 0 0 -1 +$EndComp +Entry Wire Line + 10800 3750 10900 3650 +Entry Wire Line + 10800 3850 10900 3750 +Entry Wire Line + 10800 3950 10900 3850 +Entry Wire Line + 10800 4050 10900 3950 +Entry Wire Line + 10800 4150 10900 4050 +Entry Wire Line + 10800 4250 10900 4150 +Entry Wire Line + 10800 4350 10900 4250 +Entry Wire Line + 10800 4450 10900 4350 +Entry Wire Line + 10800 4550 10900 4450 +Entry Wire Line + 10800 4650 10900 4550 +Entry Wire Line + 10800 4750 10900 4650 +Entry Wire Line + 10800 4850 10900 4750 +Wire Wire Line + 10500 3750 10800 3750 +Wire Wire Line + 10500 3850 10800 3850 +Wire Wire Line + 10500 3950 10800 3950 +Wire Wire Line + 10500 4050 10800 4050 +Wire Wire Line + 10500 4150 10800 4150 +Wire Wire Line + 10500 4250 10800 4250 +Wire Wire Line + 10500 4350 10800 4350 +Wire Wire Line + 10500 4450 10800 4450 +Wire Wire Line + 10500 4550 10800 4550 +Wire Wire Line + 10500 4650 10800 4650 +Wire Wire Line + 10500 4750 10800 4750 +Wire Wire Line + 10500 4850 10800 4850 +Text Label 9150 3750 0 50 ~ 0 +D0 +Text Label 9150 3850 0 50 ~ 0 +D2 +Text Label 9150 3950 0 50 ~ 0 +D4 +Text Label 9150 4050 0 50 ~ 0 +D6 +Text Label 9150 4150 0 50 ~ 0 +D8 +Text Label 9150 4250 0 50 ~ 0 +D10 +Text Label 9150 4350 0 50 ~ 0 +D12 +Text Label 9150 4450 0 50 ~ 0 +D14 +Text Label 9150 4550 0 50 ~ 0 +D16 +Text Label 9150 4650 0 50 ~ 0 +D18 +Text Label 9150 4750 0 50 ~ 0 +D20 +Text Label 9150 4850 0 50 ~ 0 +D22 +Text Label 10550 3750 0 50 ~ 0 +D1 +Text Label 10550 3850 0 50 ~ 0 +D3 +Text Label 10550 3950 0 50 ~ 0 +D5 +Text Label 10550 4050 0 50 ~ 0 +D7 +Text Label 10550 4150 0 50 ~ 0 +D9 +Text Label 10550 4250 0 50 ~ 0 +D11 +Text Label 10550 4350 0 50 ~ 0 +D13 +Text Label 10550 4450 0 50 ~ 0 +D15 +Text Label 10550 4550 0 50 ~ 0 +D17 +Text Label 10550 4650 0 50 ~ 0 +D19 +Text Label 10550 4750 0 50 ~ 0 +D21 +Text Label 10550 4850 0 50 ~ 0 +D23 +Text Notes 650 650 0 50 ~ 0 +Power Interface +Wire Wire Line + 9300 3150 9250 3150 +Text Label 9250 3150 2 50 ~ 0 +3v3 +Text HLabel 1350 1450 0 50 Input ~ 0 +MASTER_SPI_CLK +Text HLabel 1350 1550 0 50 Input ~ 0 +MASTER_SPI_MISO +Text HLabel 1350 1650 0 50 Input ~ 0 +MASTER_SPI_MOSI +Text HLabel 1350 1750 0 50 Input ~ 0 +~IO_EXPANDER_CS +Text HLabel 1350 1900 0 50 Input ~ 0 +~TFT_CS +Text HLabel 1350 2000 0 50 Input ~ 0 +~TFT_RD +Text HLabel 1350 2100 0 50 Input ~ 0 +~TFT_WR +Text HLabel 1350 2200 0 50 Input ~ 0 +TFT_RSDC +Text HLabel 1350 2300 0 50 Input ~ 0 +~TFT_RST +Text HLabel 1350 2400 0 50 Input ~ 0 +TFT_STB +Text HLabel 1350 2700 0 50 Input ~ 0 +TFT_TOUCH_SDA +Text HLabel 1350 2800 0 50 Input ~ 0 +TFT_TOUCH_SCL +Text HLabel 1350 2600 0 50 Input ~ 0 +TFT_TOUCH_INT +Entry Bus Bus + 8450 4050 8550 3950 +Wire Wire Line + 9300 3650 9250 3650 +Wire Wire Line + 1350 1450 1600 1450 +Text Label 1600 1450 0 50 ~ 0 +IO_EXP_CLK +Text Label 1600 1550 0 50 ~ 0 +IO_EXP_DOUT +Wire Wire Line + 1600 1550 1350 1550 +Wire Wire Line + 1350 1650 1600 1650 +Text Label 1600 1650 0 50 ~ 0 +IO_EXP_DIN +Wire Wire Line + 1350 1750 1600 1750 +Text Label 1600 1750 0 50 ~ 0 +~IO_EXP_CS +Wire Wire Line + 1350 1900 1600 1900 +Text Label 1600 1900 0 50 ~ 0 +~TFT_CS +Text Label 1600 2000 0 50 ~ 0 +~TFT_RD +Wire Wire Line + 1600 2000 1350 2000 +Wire Wire Line + 1350 2100 1600 2100 +Text Label 1600 2100 0 50 ~ 0 +~TFT_WR +Text Label 1600 2200 0 50 ~ 0 +TFT_RSDC +Wire Wire Line + 1600 2200 1350 2200 +Wire Wire Line + 1350 2300 1600 2300 +Text Label 1600 2300 0 50 ~ 0 +~TFT_RST +Text Label 1600 2400 0 50 ~ 0 +TFT_STB +Wire Wire Line + 1600 2400 1350 2400 +Text Label 1600 2800 0 50 ~ 0 +TFT_TOUCH_SCL +Text Label 1600 2600 0 50 ~ 0 +TFT_TOUCH_INT +Wire Wire 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CNN +F 1 "GND" H 10855 2477 50 0000 C CNN +F 2 "" H 10850 2650 50 0001 C CNN +F 3 "" H 10850 2650 50 0001 C CNN + 1 10850 2650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9300 3250 9250 3250 +Text Label 9250 3250 2 50 ~ 0 +TFT_TOUCH_SCL +Text Label 9250 3350 2 50 ~ 0 +TFT_TOUCH_INT +Wire Wire Line + 9250 3350 9300 3350 +Text Label 9250 3450 2 50 ~ 0 +~TFT_RST +Wire Wire Line + 9300 3450 9250 3450 +Wire Wire Line + 9300 3550 9250 3550 +Text Label 9250 3550 2 50 ~ 0 +~TFT_CS +Text Label 10600 3450 0 50 ~ 0 +TFT_RSDC +Text Label 10600 3650 0 50 ~ 0 +TFT_TE +Wire Wire Line + 10500 3650 10600 3650 +Text Label 9250 3650 2 50 ~ 0 +~TFT_RD +Wire Wire Line + 9300 4950 9200 4950 +Text Label 9200 4950 2 50 ~ 0 +TFT_STB +Wire Bus Line + 8850 5600 8850 4850 +Wire Bus Line + 8850 5600 10900 5600 +Entry Bus Bus + 8850 4850 8950 4750 +Wire Bus Line + 8950 4750 9050 4750 +Wire Bus Line + 8550 3950 8600 3950 +Entry Bus Bus + 8600 3950 8700 3850 +Wire Bus Line + 8700 3850 8750 3850 +Entry Bus Bus + 8750 3850 8850 3750 +Wire Bus Line + 8850 3750 8900 3750 +Wire Bus Line + 9000 3650 9050 3650 +Wire Bus Line + 8200 4050 8450 4050 +Entry Bus Bus + 8900 3750 9000 3650 +Wire Notes Line + 550 550 1350 550 +Wire Notes Line + 1350 550 1350 1200 +Wire Notes Line + 1350 1200 550 1200 +Wire Notes Line + 550 1200 550 550 +Wire Notes Line + 550 1250 550 3000 +Wire Notes Line + 2200 3000 2200 1250 +Wire Notes Line + 2200 1250 550 1250 +Text Notes 650 1350 0 50 ~ 0 +LCD Interface +Text Label 1600 2700 0 50 ~ 0 +TFT_TOUCH_SDA +Wire Wire Line + 1350 2700 1600 2700 +Wire Wire Line + 1350 2800 1600 2800 +Wire Notes Line + 2200 3000 550 3000 +Wire Bus Line + 9050 3650 9050 4750 +Wire Bus Line + 8200 4050 8200 6200 +Wire Bus Line + 6300 4050 6300 6200 +Wire Bus Line + 10900 3650 10900 5600 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/USB_INTF.sch b/electrical/same54_dev_board/USB_INTF.sch index 540a437..f6ac022 100644 --- a/electrical/same54_dev_board/USB_INTF.sch +++ b/electrical/same54_dev_board/USB_INTF.sch @@ -1,282 +1,282 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 4 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L Connector:USB_B_Micro J1 -U 1 1 5E8480AD -P 6050 1300 -F 0 "J1" H 6107 1767 50 0000 C CNN -F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN -F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN -F 3 "~" H 6200 1250 50 0001 C CNN - 1 6050 1300 - 1 0 0 -1 -$EndComp -$Comp -L dk_Interface-Controllers:FT232RQ-REEL U2 -U 1 1 5E84744C -P 7700 2500 -F 0 "U2" H 8000 1100 60 0000 C CNN -F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN -F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN -F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN -F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN" -F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN" -F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category" -F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family" -F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page" -F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description" -F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer" -F 12 "Active" H 7900 3700 60 0001 L CNN "Status" - 1 7700 2500 - 1 0 0 -1 -$EndComp -Text Notes 650 700 0 50 ~ 0 -Power Interface -Wire Wire Line - 6350 1300 6400 1300 -Text Label 6400 1300 0 50 ~ 0 -USB_D+ -Wire Wire Line - 6350 1400 6400 1400 -Text Label 6400 1400 0 50 ~ 0 -USB_D- -Wire Wire Line - 7000 3400 6900 3400 -Wire Wire Line - 7000 3500 6900 3500 -Text Label 6900 3400 2 50 ~ 0 -USB_D+ -Text Label 6900 3500 2 50 ~ 0 -USB_D- -Wire Wire Line - 8000 3000 8100 3000 -Text Label 8100 3000 0 50 ~ 0 -FTDI_TX -Wire Wire Line - 7000 2600 6900 2600 -Text Label 6900 2600 2 50 ~ 0 -FTDI_RX -Wire Wire Line - 7400 4200 7500 4200 -Connection ~ 7500 4200 -Wire Wire Line - 7500 4200 7600 4200 -Wire Wire Line - 7500 4200 7500 4300 -$Comp -L power:GND #PWR0110 -U 1 1 5E7B73F2 -P 7500 4300 -F 0 "#PWR0110" H 7500 4050 50 0001 C CNN -F 1 "GND" H 7505 4127 50 0000 C CNN -F 2 "" H 7500 4300 50 0001 C CNN -F 3 "" H 7500 4300 50 0001 C CNN - 1 7500 4300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5950 1700 6050 1700 -Wire Wire Line - 6050 1700 6050 1800 -Connection ~ 6050 1700 -$Comp -L power:GND #PWR0111 -U 1 1 5E7BED3A -P 6050 1800 -F 0 "#PWR0111" H 6050 1550 50 0001 C CNN -F 1 "GND" H 6055 1627 50 0000 C CNN -F 2 "" H 6050 1800 50 0001 C CNN -F 3 "" H 6050 1800 50 0001 C CNN - 1 6050 1800 - 1 0 0 -1 -$EndComp -NoConn ~ 6350 1500 -Wire Notes Line - 600 600 2000 600 -Text Label 1350 1950 0 50 ~ 0 -FTDI_TX -Wire Wire Line - 1100 1950 1350 1950 -Text HLabel 1100 1950 0 50 Input ~ 0 -DEBUG_RX -Text Label 1350 1850 0 50 ~ 0 -FTDI_RX -Wire Wire Line - 1100 1850 1350 1850 -Text HLabel 1100 1850 0 50 Input ~ 0 -DEBUG_TX -Text Notes 700 1750 0 50 ~ 0 -USB Interface -Wire Notes Line - 2000 1650 600 1650 -Wire Notes Line - 600 600 600 1650 -Wire Wire Line - 7500 2300 7500 2400 -Wire Wire Line - 8000 2800 8500 2800 -$Comp -L Device:C_Small C6 -U 1 1 5E7E8395 -P 8500 2900 -F 0 "C6" H 8592 2946 50 0000 L CNN -F 1 "100nF" H 8592 2855 50 0000 L CNN -F 2 "" H 8500 2900 50 0001 C CNN -F 3 "~" H 8500 2900 50 0001 C CNN - 1 8500 2900 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8500 3000 8500 3100 -$Comp -L power:GND #PWR0112 -U 1 1 5E7E91F3 -P 8500 3100 -F 0 "#PWR0112" H 8500 2850 50 0001 C CNN -F 1 "GND" H 8505 2927 50 0000 C CNN -F 2 "" H 8500 3100 50 0001 C CNN -F 3 "" H 8500 3100 50 0001 C CNN - 1 8500 3100 - 1 0 0 -1 -$EndComp -NoConn ~ 8000 3100 -NoConn ~ 8000 3200 -Wire Wire Line - 8500 2800 8850 2800 -Connection ~ 8500 2800 -Text Label 8850 2800 0 50 ~ 0 -FTDI_3v3 -Text Label 7500 2300 2 50 ~ 0 -FTDI_3v3 -Wire Wire Line - 7000 3100 6900 3100 -Text Label 6900 3100 2 50 ~ 0 -FTDI_3v3 -Wire Wire Line - 7600 4200 7700 4200 -Connection ~ 7600 4200 -Wire Wire Line - 7000 3900 6900 3900 -Wire Wire Line - 6900 3900 6900 4200 -Wire Wire Line - 6900 4200 7400 4200 -Connection ~ 7400 4200 -Wire Wire Line - 7700 4200 7800 4200 -Connection ~ 7700 4200 -$Comp -L Device:C_Small C7 -U 1 1 5E7F85B7 -P 6800 1200 -F 0 "C7" H 6892 1246 50 0000 L CNN -F 1 "10nF" H 6892 1155 50 0000 L CNN -F 2 "" H 6800 1200 50 0001 C CNN -F 3 "~" H 6800 1200 50 0001 C CNN - 1 6800 1200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6350 1100 6800 1100 -Wire Wire Line - 6800 1300 6800 1700 -Wire Wire Line - 6800 1700 6050 1700 -Wire Wire Line - 6800 1100 7050 1100 -Connection ~ 6800 1100 -$Comp -L Device:Ferrite_Bead_Small FB1 -U 1 1 5E7FB1E4 -P 7150 1100 -F 0 "FB1" V 6913 1100 50 0000 C CNN -F 1 "40_Ohm" V 7004 1100 50 0000 C CNN -F 2 "" V 7080 1100 50 0001 C CNN -F 3 "~" H 7150 1100 50 0001 C CNN - 1 7150 1100 - 0 1 1 0 -$EndComp -Wire Wire Line - 7600 1100 7600 2400 -Wire Wire Line - 7250 1100 7600 1100 -Wire Wire Line - 7600 1100 8050 1100 -Connection ~ 7600 1100 -$Comp -L Device:C_Small C8 -U 1 1 5E8424CD -P 8050 1200 -F 0 "C8" H 8142 1246 50 0000 L CNN -F 1 "4.7uF" H 8142 1155 50 0000 L CNN -F 2 "" H 8050 1200 50 0001 C CNN -F 3 "~" H 8050 1200 50 0001 C CNN - 1 8050 1200 - 1 0 0 -1 -$EndComp -$Comp -L Device:C_Small C9 -U 1 1 5E844B56 -P 8550 1200 -F 0 "C9" H 8642 1246 50 0000 L CNN -F 1 "100nF" H 8642 1155 50 0000 L CNN -F 2 "" H 8550 1200 50 0001 C CNN -F 3 "~" H 8550 1200 50 0001 C CNN - 1 8550 1200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8050 1100 8550 1100 -Connection ~ 8050 1100 -Wire Wire Line - 8050 1300 8300 1300 -Wire Wire Line - 8300 1300 8300 1400 -Connection ~ 8300 1300 -Wire Wire Line - 8300 1300 8550 1300 -$Comp -L power:GND #PWR0116 -U 1 1 5E849ABD -P 8300 1400 -F 0 "#PWR0116" H 8300 1150 50 0001 C CNN -F 1 "GND" H 8305 1227 50 0000 C CNN -F 2 "" H 8300 1400 50 0001 C CNN -F 3 "" H 8300 1400 50 0001 C CNN - 1 8300 1400 - 1 0 0 -1 -$EndComp -Text Label 8950 1100 0 50 ~ 0 -FTDI_5V -Wire Wire Line - 8550 1100 8950 1100 -Connection ~ 8550 1100 -Wire Wire Line - 1050 800 1550 800 -Text Label 1550 800 0 50 ~ 0 -FTDI_5V -Text HLabel 1050 800 0 50 Input ~ 0 -FTDI_5V -Text Label 1550 950 0 50 ~ 0 -FTDI_3v3 -Wire Wire Line - 1050 950 1550 950 -Wire Notes Line - 2000 600 2000 1650 -Text HLabel 1050 950 0 50 Input ~ 0 -FTDI_3V3 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 4 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Connector:USB_B_Micro J1 +U 1 1 5E8480AD +P 6050 1300 +F 0 "J1" H 6107 1767 50 0000 C CNN +F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN +F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN +F 3 "~" H 6200 1250 50 0001 C CNN + 1 6050 1300 + 1 0 0 -1 +$EndComp +$Comp +L dk_Interface-Controllers:FT232RQ-REEL U2 +U 1 1 5E84744C +P 7700 2500 +F 0 "U2" H 8000 1100 60 0000 C CNN +F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN +F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN +F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN +F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN" +F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN" +F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category" +F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family" +F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page" +F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description" +F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer" +F 12 "Active" H 7900 3700 60 0001 L CNN "Status" + 1 7700 2500 + 1 0 0 -1 +$EndComp +Text Notes 650 700 0 50 ~ 0 +Power Interface +Wire Wire Line + 6350 1300 6400 1300 +Text Label 6400 1300 0 50 ~ 0 +USB_D+ +Wire Wire Line + 6350 1400 6400 1400 +Text Label 6400 1400 0 50 ~ 0 +USB_D- +Wire Wire Line + 7000 3400 6900 3400 +Wire Wire Line + 7000 3500 6900 3500 +Text Label 6900 3400 2 50 ~ 0 +USB_D+ +Text Label 6900 3500 2 50 ~ 0 +USB_D- +Wire Wire Line + 8000 3000 8100 3000 +Text Label 8100 3000 0 50 ~ 0 +FTDI_TX +Wire Wire Line + 7000 2600 6900 2600 +Text Label 6900 2600 2 50 ~ 0 +FTDI_RX +Wire Wire Line + 7400 4200 7500 4200 +Connection ~ 7500 4200 +Wire Wire Line + 7500 4200 7600 4200 +Wire Wire Line + 7500 4200 7500 4300 +$Comp +L power:GND #PWR0110 +U 1 1 5E7B73F2 +P 7500 4300 +F 0 "#PWR0110" H 7500 4050 50 0001 C CNN +F 1 "GND" H 7505 4127 50 0000 C CNN +F 2 "" H 7500 4300 50 0001 C CNN +F 3 "" H 7500 4300 50 0001 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 1700 6050 1700 +Wire Wire Line + 6050 1700 6050 1800 +Connection ~ 6050 1700 +$Comp +L power:GND #PWR0111 +U 1 1 5E7BED3A +P 6050 1800 +F 0 "#PWR0111" H 6050 1550 50 0001 C CNN +F 1 "GND" H 6055 1627 50 0000 C CNN +F 2 "" H 6050 1800 50 0001 C CNN +F 3 "" H 6050 1800 50 0001 C CNN + 1 6050 1800 + 1 0 0 -1 +$EndComp +NoConn ~ 6350 1500 +Wire Notes Line + 600 600 2000 600 +Text Label 1350 1950 0 50 ~ 0 +FTDI_TX +Wire Wire Line + 1100 1950 1350 1950 +Text HLabel 1100 1950 0 50 Input ~ 0 +DEBUG_RX +Text Label 1350 1850 0 50 ~ 0 +FTDI_RX +Wire Wire Line + 1100 1850 1350 1850 +Text HLabel 1100 1850 0 50 Input ~ 0 +DEBUG_TX +Text Notes 700 1750 0 50 ~ 0 +USB Interface +Wire Notes Line + 2000 1650 600 1650 +Wire Notes Line + 600 600 600 1650 +Wire Wire Line + 7500 2300 7500 2400 +Wire Wire Line + 8000 2800 8500 2800 +$Comp +L Device:C_Small C6 +U 1 1 5E7E8395 +P 8500 2900 +F 0 "C6" H 8592 2946 50 0000 L CNN +F 1 "100nF" H 8592 2855 50 0000 L CNN +F 2 "" H 8500 2900 50 0001 C CNN +F 3 "~" H 8500 2900 50 0001 C CNN + 1 8500 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 3000 8500 3100 +$Comp +L power:GND #PWR0112 +U 1 1 5E7E91F3 +P 8500 3100 +F 0 "#PWR0112" H 8500 2850 50 0001 C CNN +F 1 "GND" H 8505 2927 50 0000 C CNN +F 2 "" H 8500 3100 50 0001 C CNN +F 3 "" H 8500 3100 50 0001 C CNN + 1 8500 3100 + 1 0 0 -1 +$EndComp +NoConn ~ 8000 3100 +NoConn ~ 8000 3200 +Wire Wire Line + 8500 2800 8850 2800 +Connection ~ 8500 2800 +Text Label 8850 2800 0 50 ~ 0 +FTDI_3v3 +Text Label 7500 2300 2 50 ~ 0 +FTDI_3v3 +Wire Wire Line + 7000 3100 6900 3100 +Text Label 6900 3100 2 50 ~ 0 +FTDI_3v3 +Wire Wire Line + 7600 4200 7700 4200 +Connection ~ 7600 4200 +Wire Wire Line + 7000 3900 6900 3900 +Wire Wire Line + 6900 3900 6900 4200 +Wire Wire Line + 6900 4200 7400 4200 +Connection ~ 7400 4200 +Wire Wire Line + 7700 4200 7800 4200 +Connection ~ 7700 4200 +$Comp +L Device:C_Small C7 +U 1 1 5E7F85B7 +P 6800 1200 +F 0 "C7" H 6892 1246 50 0000 L CNN +F 1 "10nF" H 6892 1155 50 0000 L CNN +F 2 "" H 6800 1200 50 0001 C CNN +F 3 "~" H 6800 1200 50 0001 C CNN + 1 6800 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6350 1100 6800 1100 +Wire Wire Line + 6800 1300 6800 1700 +Wire Wire Line + 6800 1700 6050 1700 +Wire Wire Line + 6800 1100 7050 1100 +Connection ~ 6800 1100 +$Comp +L Device:Ferrite_Bead_Small FB1 +U 1 1 5E7FB1E4 +P 7150 1100 +F 0 "FB1" V 6913 1100 50 0000 C CNN +F 1 "40_Ohm" V 7004 1100 50 0000 C CNN +F 2 "" V 7080 1100 50 0001 C CNN +F 3 "~" H 7150 1100 50 0001 C CNN + 1 7150 1100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7600 1100 7600 2400 +Wire Wire Line + 7250 1100 7600 1100 +Wire Wire Line + 7600 1100 8050 1100 +Connection ~ 7600 1100 +$Comp +L Device:C_Small C8 +U 1 1 5E8424CD +P 8050 1200 +F 0 "C8" H 8142 1246 50 0000 L CNN +F 1 "4.7uF" H 8142 1155 50 0000 L CNN +F 2 "" H 8050 1200 50 0001 C CNN +F 3 "~" H 8050 1200 50 0001 C CNN + 1 8050 1200 + 1 0 0 -1 +$EndComp +$Comp +L Device:C_Small C9 +U 1 1 5E844B56 +P 8550 1200 +F 0 "C9" H 8642 1246 50 0000 L CNN +F 1 "100nF" H 8642 1155 50 0000 L CNN +F 2 "" H 8550 1200 50 0001 C CNN +F 3 "~" H 8550 1200 50 0001 C CNN + 1 8550 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8050 1100 8550 1100 +Connection ~ 8050 1100 +Wire Wire Line + 8050 1300 8300 1300 +Wire Wire Line + 8300 1300 8300 1400 +Connection ~ 8300 1300 +Wire Wire Line + 8300 1300 8550 1300 +$Comp +L power:GND #PWR0116 +U 1 1 5E849ABD +P 8300 1400 +F 0 "#PWR0116" H 8300 1150 50 0001 C CNN +F 1 "GND" H 8305 1227 50 0000 C CNN +F 2 "" H 8300 1400 50 0001 C CNN +F 3 "" H 8300 1400 50 0001 C CNN + 1 8300 1400 + 1 0 0 -1 +$EndComp +Text Label 8950 1100 0 50 ~ 0 +FTDI_5V +Wire Wire Line + 8550 1100 8950 1100 +Connection ~ 8550 1100 +Wire Wire Line + 1050 800 1550 800 +Text Label 1550 800 0 50 ~ 0 +FTDI_5V +Text HLabel 1050 800 0 50 Input ~ 0 +FTDI_5V +Text Label 1550 950 0 50 ~ 0 +FTDI_3v3 +Wire Wire Line + 1050 950 1550 950 +Wire Notes Line + 2000 600 2000 1650 +Text HLabel 1050 950 0 50 Input ~ 0 +FTDI_3V3 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/USB_INTF.sch-bak b/electrical/same54_dev_board/USB_INTF.sch-bak index 540a437..f6ac022 100644 --- a/electrical/same54_dev_board/USB_INTF.sch-bak +++ b/electrical/same54_dev_board/USB_INTF.sch-bak @@ -1,282 +1,282 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 4 5 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L Connector:USB_B_Micro J1 -U 1 1 5E8480AD -P 6050 1300 -F 0 "J1" H 6107 1767 50 0000 C CNN -F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN -F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN -F 3 "~" H 6200 1250 50 0001 C CNN - 1 6050 1300 - 1 0 0 -1 -$EndComp -$Comp -L dk_Interface-Controllers:FT232RQ-REEL U2 -U 1 1 5E84744C -P 7700 2500 -F 0 "U2" H 8000 1100 60 0000 C CNN -F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN -F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN -F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN -F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN" -F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN" -F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category" -F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family" -F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link" -F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page" -F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description" -F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer" -F 12 "Active" H 7900 3700 60 0001 L CNN "Status" - 1 7700 2500 - 1 0 0 -1 -$EndComp -Text Notes 650 700 0 50 ~ 0 -Power Interface -Wire Wire Line - 6350 1300 6400 1300 -Text Label 6400 1300 0 50 ~ 0 -USB_D+ -Wire Wire Line - 6350 1400 6400 1400 -Text Label 6400 1400 0 50 ~ 0 -USB_D- -Wire Wire Line - 7000 3400 6900 3400 -Wire Wire Line - 7000 3500 6900 3500 -Text Label 6900 3400 2 50 ~ 0 -USB_D+ -Text Label 6900 3500 2 50 ~ 0 -USB_D- -Wire Wire Line - 8000 3000 8100 3000 -Text Label 8100 3000 0 50 ~ 0 -FTDI_TX -Wire Wire Line - 7000 2600 6900 2600 -Text Label 6900 2600 2 50 ~ 0 -FTDI_RX -Wire Wire Line - 7400 4200 7500 4200 -Connection ~ 7500 4200 -Wire Wire Line - 7500 4200 7600 4200 -Wire Wire Line - 7500 4200 7500 4300 -$Comp -L power:GND #PWR0110 -U 1 1 5E7B73F2 -P 7500 4300 -F 0 "#PWR0110" H 7500 4050 50 0001 C CNN -F 1 "GND" H 7505 4127 50 0000 C CNN -F 2 "" H 7500 4300 50 0001 C CNN -F 3 "" H 7500 4300 50 0001 C CNN - 1 7500 4300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5950 1700 6050 1700 -Wire Wire Line - 6050 1700 6050 1800 -Connection ~ 6050 1700 -$Comp -L power:GND #PWR0111 -U 1 1 5E7BED3A -P 6050 1800 -F 0 "#PWR0111" H 6050 1550 50 0001 C CNN -F 1 "GND" H 6055 1627 50 0000 C CNN -F 2 "" H 6050 1800 50 0001 C CNN -F 3 "" H 6050 1800 50 0001 C CNN - 1 6050 1800 - 1 0 0 -1 -$EndComp -NoConn ~ 6350 1500 -Wire Notes Line - 600 600 2000 600 -Text Label 1350 1950 0 50 ~ 0 -FTDI_TX -Wire Wire Line - 1100 1950 1350 1950 -Text HLabel 1100 1950 0 50 Input ~ 0 -DEBUG_RX -Text Label 1350 1850 0 50 ~ 0 -FTDI_RX -Wire Wire Line - 1100 1850 1350 1850 -Text HLabel 1100 1850 0 50 Input ~ 0 -DEBUG_TX -Text Notes 700 1750 0 50 ~ 0 -USB Interface -Wire Notes Line - 2000 1650 600 1650 -Wire Notes Line - 600 600 600 1650 -Wire Wire Line - 7500 2300 7500 2400 -Wire Wire Line - 8000 2800 8500 2800 -$Comp -L Device:C_Small C6 -U 1 1 5E7E8395 -P 8500 2900 -F 0 "C6" H 8592 2946 50 0000 L CNN -F 1 "100nF" H 8592 2855 50 0000 L CNN -F 2 "" H 8500 2900 50 0001 C CNN -F 3 "~" H 8500 2900 50 0001 C CNN - 1 8500 2900 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8500 3000 8500 3100 -$Comp -L power:GND #PWR0112 -U 1 1 5E7E91F3 -P 8500 3100 -F 0 "#PWR0112" H 8500 2850 50 0001 C CNN -F 1 "GND" H 8505 2927 50 0000 C CNN -F 2 "" H 8500 3100 50 0001 C CNN -F 3 "" H 8500 3100 50 0001 C CNN - 1 8500 3100 - 1 0 0 -1 -$EndComp -NoConn ~ 8000 3100 -NoConn ~ 8000 3200 -Wire Wire Line - 8500 2800 8850 2800 -Connection ~ 8500 2800 -Text Label 8850 2800 0 50 ~ 0 -FTDI_3v3 -Text Label 7500 2300 2 50 ~ 0 -FTDI_3v3 -Wire Wire Line - 7000 3100 6900 3100 -Text Label 6900 3100 2 50 ~ 0 -FTDI_3v3 -Wire Wire Line - 7600 4200 7700 4200 -Connection ~ 7600 4200 -Wire Wire Line - 7000 3900 6900 3900 -Wire Wire Line - 6900 3900 6900 4200 -Wire Wire Line - 6900 4200 7400 4200 -Connection ~ 7400 4200 -Wire Wire Line - 7700 4200 7800 4200 -Connection ~ 7700 4200 -$Comp -L Device:C_Small C7 -U 1 1 5E7F85B7 -P 6800 1200 -F 0 "C7" H 6892 1246 50 0000 L CNN -F 1 "10nF" H 6892 1155 50 0000 L CNN -F 2 "" H 6800 1200 50 0001 C CNN -F 3 "~" H 6800 1200 50 0001 C CNN - 1 6800 1200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 6350 1100 6800 1100 -Wire Wire Line - 6800 1300 6800 1700 -Wire Wire Line - 6800 1700 6050 1700 -Wire Wire Line - 6800 1100 7050 1100 -Connection ~ 6800 1100 -$Comp -L Device:Ferrite_Bead_Small FB1 -U 1 1 5E7FB1E4 -P 7150 1100 -F 0 "FB1" V 6913 1100 50 0000 C CNN -F 1 "40_Ohm" V 7004 1100 50 0000 C CNN -F 2 "" V 7080 1100 50 0001 C CNN -F 3 "~" H 7150 1100 50 0001 C CNN - 1 7150 1100 - 0 1 1 0 -$EndComp -Wire Wire Line - 7600 1100 7600 2400 -Wire Wire Line - 7250 1100 7600 1100 -Wire Wire Line - 7600 1100 8050 1100 -Connection ~ 7600 1100 -$Comp -L Device:C_Small C8 -U 1 1 5E8424CD -P 8050 1200 -F 0 "C8" H 8142 1246 50 0000 L CNN -F 1 "4.7uF" H 8142 1155 50 0000 L CNN -F 2 "" H 8050 1200 50 0001 C CNN -F 3 "~" H 8050 1200 50 0001 C CNN - 1 8050 1200 - 1 0 0 -1 -$EndComp -$Comp -L Device:C_Small C9 -U 1 1 5E844B56 -P 8550 1200 -F 0 "C9" H 8642 1246 50 0000 L CNN -F 1 "100nF" H 8642 1155 50 0000 L CNN -F 2 "" H 8550 1200 50 0001 C CNN -F 3 "~" H 8550 1200 50 0001 C CNN - 1 8550 1200 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8050 1100 8550 1100 -Connection ~ 8050 1100 -Wire Wire Line - 8050 1300 8300 1300 -Wire Wire Line - 8300 1300 8300 1400 -Connection ~ 8300 1300 -Wire Wire Line - 8300 1300 8550 1300 -$Comp -L power:GND #PWR0116 -U 1 1 5E849ABD -P 8300 1400 -F 0 "#PWR0116" H 8300 1150 50 0001 C CNN -F 1 "GND" H 8305 1227 50 0000 C CNN -F 2 "" H 8300 1400 50 0001 C CNN -F 3 "" H 8300 1400 50 0001 C CNN - 1 8300 1400 - 1 0 0 -1 -$EndComp -Text Label 8950 1100 0 50 ~ 0 -FTDI_5V -Wire Wire Line - 8550 1100 8950 1100 -Connection ~ 8550 1100 -Wire Wire Line - 1050 800 1550 800 -Text Label 1550 800 0 50 ~ 0 -FTDI_5V -Text HLabel 1050 800 0 50 Input ~ 0 -FTDI_5V -Text Label 1550 950 0 50 ~ 0 -FTDI_3v3 -Wire Wire Line - 1050 950 1550 950 -Wire Notes Line - 2000 600 2000 1650 -Text HLabel 1050 950 0 50 Input ~ 0 -FTDI_3V3 -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 4 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Connector:USB_B_Micro J1 +U 1 1 5E8480AD +P 6050 1300 +F 0 "J1" H 6107 1767 50 0000 C CNN +F 1 "USB_B_Micro" H 6107 1676 50 0000 C CNN +F 2 "Connector_USB:USB_Micro-B_Wuerth_629105150521" H 6200 1250 50 0001 C CNN +F 3 "~" H 6200 1250 50 0001 C CNN + 1 6050 1300 + 1 0 0 -1 +$EndComp +$Comp +L dk_Interface-Controllers:FT232RQ-REEL U2 +U 1 1 5E84744C +P 7700 2500 +F 0 "U2" H 8000 1100 60 0000 C CNN +F 1 "FT232RQ-REEL" H 8300 1200 60 0000 C CNN +F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 7900 2700 60 0001 L CNN +F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 2800 60 0001 L CNN +F 4 "768-1008-1-ND" H 7900 2900 60 0001 L CNN "Digi-Key_PN" +F 5 "FT232RQ-REEL" H 7900 3000 60 0001 L CNN "MPN" +F 6 "Integrated Circuits (ICs)" H 7900 3100 60 0001 L CNN "Category" +F 7 "Interface - Controllers" H 7900 3200 60 0001 L CNN "Family" +F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 7900 3300 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 7900 3400 60 0001 L CNN "DK_Detail_Page" +F 10 "IC USB FS SERIAL UART 32-QFN" H 7900 3500 60 0001 L CNN "Description" +F 11 "FTDI, Future Technology Devices International Ltd" H 7900 3600 60 0001 L CNN "Manufacturer" +F 12 "Active" H 7900 3700 60 0001 L CNN "Status" + 1 7700 2500 + 1 0 0 -1 +$EndComp +Text Notes 650 700 0 50 ~ 0 +Power Interface +Wire Wire Line + 6350 1300 6400 1300 +Text Label 6400 1300 0 50 ~ 0 +USB_D+ +Wire Wire Line + 6350 1400 6400 1400 +Text Label 6400 1400 0 50 ~ 0 +USB_D- +Wire Wire Line + 7000 3400 6900 3400 +Wire Wire Line + 7000 3500 6900 3500 +Text Label 6900 3400 2 50 ~ 0 +USB_D+ +Text Label 6900 3500 2 50 ~ 0 +USB_D- +Wire Wire Line + 8000 3000 8100 3000 +Text Label 8100 3000 0 50 ~ 0 +FTDI_TX +Wire Wire Line + 7000 2600 6900 2600 +Text Label 6900 2600 2 50 ~ 0 +FTDI_RX +Wire Wire Line + 7400 4200 7500 4200 +Connection ~ 7500 4200 +Wire Wire Line + 7500 4200 7600 4200 +Wire Wire Line + 7500 4200 7500 4300 +$Comp +L power:GND #PWR0110 +U 1 1 5E7B73F2 +P 7500 4300 +F 0 "#PWR0110" H 7500 4050 50 0001 C CNN +F 1 "GND" H 7505 4127 50 0000 C CNN +F 2 "" H 7500 4300 50 0001 C CNN +F 3 "" H 7500 4300 50 0001 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 1700 6050 1700 +Wire Wire Line + 6050 1700 6050 1800 +Connection ~ 6050 1700 +$Comp +L power:GND #PWR0111 +U 1 1 5E7BED3A +P 6050 1800 +F 0 "#PWR0111" H 6050 1550 50 0001 C CNN +F 1 "GND" H 6055 1627 50 0000 C CNN +F 2 "" H 6050 1800 50 0001 C CNN +F 3 "" H 6050 1800 50 0001 C CNN + 1 6050 1800 + 1 0 0 -1 +$EndComp +NoConn ~ 6350 1500 +Wire Notes Line + 600 600 2000 600 +Text Label 1350 1950 0 50 ~ 0 +FTDI_TX +Wire Wire Line + 1100 1950 1350 1950 +Text HLabel 1100 1950 0 50 Input ~ 0 +DEBUG_RX +Text Label 1350 1850 0 50 ~ 0 +FTDI_RX +Wire Wire Line + 1100 1850 1350 1850 +Text HLabel 1100 1850 0 50 Input ~ 0 +DEBUG_TX +Text Notes 700 1750 0 50 ~ 0 +USB Interface +Wire Notes Line + 2000 1650 600 1650 +Wire Notes Line + 600 600 600 1650 +Wire Wire Line + 7500 2300 7500 2400 +Wire Wire Line + 8000 2800 8500 2800 +$Comp +L Device:C_Small C6 +U 1 1 5E7E8395 +P 8500 2900 +F 0 "C6" H 8592 2946 50 0000 L CNN +F 1 "100nF" H 8592 2855 50 0000 L CNN +F 2 "" H 8500 2900 50 0001 C CNN +F 3 "~" H 8500 2900 50 0001 C CNN + 1 8500 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8500 3000 8500 3100 +$Comp +L power:GND #PWR0112 +U 1 1 5E7E91F3 +P 8500 3100 +F 0 "#PWR0112" H 8500 2850 50 0001 C CNN +F 1 "GND" H 8505 2927 50 0000 C CNN +F 2 "" H 8500 3100 50 0001 C CNN +F 3 "" H 8500 3100 50 0001 C CNN + 1 8500 3100 + 1 0 0 -1 +$EndComp +NoConn ~ 8000 3100 +NoConn ~ 8000 3200 +Wire Wire Line + 8500 2800 8850 2800 +Connection ~ 8500 2800 +Text Label 8850 2800 0 50 ~ 0 +FTDI_3v3 +Text Label 7500 2300 2 50 ~ 0 +FTDI_3v3 +Wire Wire Line + 7000 3100 6900 3100 +Text Label 6900 3100 2 50 ~ 0 +FTDI_3v3 +Wire Wire Line + 7600 4200 7700 4200 +Connection ~ 7600 4200 +Wire Wire Line + 7000 3900 6900 3900 +Wire Wire Line + 6900 3900 6900 4200 +Wire Wire Line + 6900 4200 7400 4200 +Connection ~ 7400 4200 +Wire Wire Line + 7700 4200 7800 4200 +Connection ~ 7700 4200 +$Comp +L Device:C_Small C7 +U 1 1 5E7F85B7 +P 6800 1200 +F 0 "C7" H 6892 1246 50 0000 L CNN +F 1 "10nF" H 6892 1155 50 0000 L CNN +F 2 "" H 6800 1200 50 0001 C CNN +F 3 "~" H 6800 1200 50 0001 C CNN + 1 6800 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6350 1100 6800 1100 +Wire Wire Line + 6800 1300 6800 1700 +Wire Wire Line + 6800 1700 6050 1700 +Wire Wire Line + 6800 1100 7050 1100 +Connection ~ 6800 1100 +$Comp +L Device:Ferrite_Bead_Small FB1 +U 1 1 5E7FB1E4 +P 7150 1100 +F 0 "FB1" V 6913 1100 50 0000 C CNN +F 1 "40_Ohm" V 7004 1100 50 0000 C CNN +F 2 "" V 7080 1100 50 0001 C CNN +F 3 "~" H 7150 1100 50 0001 C CNN + 1 7150 1100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7600 1100 7600 2400 +Wire Wire Line + 7250 1100 7600 1100 +Wire Wire Line + 7600 1100 8050 1100 +Connection ~ 7600 1100 +$Comp +L Device:C_Small C8 +U 1 1 5E8424CD +P 8050 1200 +F 0 "C8" H 8142 1246 50 0000 L CNN +F 1 "4.7uF" H 8142 1155 50 0000 L CNN +F 2 "" H 8050 1200 50 0001 C CNN +F 3 "~" H 8050 1200 50 0001 C CNN + 1 8050 1200 + 1 0 0 -1 +$EndComp +$Comp +L Device:C_Small C9 +U 1 1 5E844B56 +P 8550 1200 +F 0 "C9" H 8642 1246 50 0000 L CNN +F 1 "100nF" H 8642 1155 50 0000 L CNN +F 2 "" H 8550 1200 50 0001 C CNN +F 3 "~" H 8550 1200 50 0001 C CNN + 1 8550 1200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8050 1100 8550 1100 +Connection ~ 8050 1100 +Wire Wire Line + 8050 1300 8300 1300 +Wire Wire Line + 8300 1300 8300 1400 +Connection ~ 8300 1300 +Wire Wire Line + 8300 1300 8550 1300 +$Comp +L power:GND #PWR0116 +U 1 1 5E849ABD +P 8300 1400 +F 0 "#PWR0116" H 8300 1150 50 0001 C CNN +F 1 "GND" H 8305 1227 50 0000 C CNN +F 2 "" H 8300 1400 50 0001 C CNN +F 3 "" H 8300 1400 50 0001 C CNN + 1 8300 1400 + 1 0 0 -1 +$EndComp +Text Label 8950 1100 0 50 ~ 0 +FTDI_5V +Wire Wire Line + 8550 1100 8950 1100 +Connection ~ 8550 1100 +Wire Wire Line + 1050 800 1550 800 +Text Label 1550 800 0 50 ~ 0 +FTDI_5V +Text HLabel 1050 800 0 50 Input ~ 0 +FTDI_5V +Text Label 1550 950 0 50 ~ 0 +FTDI_3v3 +Wire Wire Line + 1050 950 1550 950 +Wire Notes Line + 2000 600 2000 1650 +Text HLabel 1050 950 0 50 Input ~ 0 +FTDI_3V3 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/fp-info-cache b/electrical/same54_dev_board/fp-info-cache index f2b3535..8bce34c 100644 --- a/electrical/same54_dev_board/fp-info-cache +++ b/electrical/same54_dev_board/fp-info-cache @@ -1,78765 +1,78765 @@ -17824947138230346 -Battery -BatteryHolder_Bulgin_BX0036_1xC -Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf) -Bulgin BX0036 -0 -2 -2 -Battery -BatteryHolder_ComfortableElectronic_CH273-2450_1x2450 -Comfortable Electronic CR2450 battery holder, http://www.comf.com.tw/ProductDetail.asp?no=148 -Comfortable Electronic CR2450 -0 -2 -2 -Battery -BatteryHolder_Eagle_12BH611-GR -https://eu.mouser.com/datasheet/2/209/EPD-200766-1274481.pdf -9V Battery Holder -0 -2 -2 -Battery -BatteryHolder_Keystone_103_1x20mm -http://www.keyelco.com/product-pdf.cfm?p=719 -Keystone type 103 battery holder -0 -2 -2 -Battery -BatteryHolder_Keystone_104_1x23mm -http://www.keyelco.com/product-pdf.cfm?p=744 -Keystone type 104 battery holder -0 -2 -2 -Battery -BatteryHolder_Keystone_105_1x2430 -http://www.keyelco.com/product-pdf.cfm?p=745 -Keystone type 105 battery holder -0 -2 -2 -Battery -BatteryHolder_Keystone_106_1x20mm -http://www.keyelco.com/product-pdf.cfm?p=720 -Keystone type 106 battery holder -0 -2 -2 -Battery -BatteryHolder_Keystone_107_1x23mm -http://www.keyelco.com/product-pdf.cfm?p=746 -Keystone type 107 battery holder -0 -2 -2 -Battery -BatteryHolder_Keystone_500 -Keystone #500, CR1220 battery holder, http://www.keyelco.com/product-pdf.cfm?p=710 -CR1220 battery holder -0 -2 -2 -Battery -BatteryHolder_Keystone_1042_1x18650 -Battery holder for 18650 cylindrical cells http://www.keyelco.com/product.cfm/product_id/918 -18650 Keystone 1042 Li-ion -0 -2 -2 -Battery -BatteryHolder_Keystone_1058_1x2032 -http://www.keyelco.com/product-pdf.cfm?p=14028 -Keystone type 1058 coin cell retainer -0 -2 -2 -Battery -BatteryHolder_Keystone_1060_1x2032 -http://www.keyelco.com/product-pdf.cfm?p=726 -CR2032 BR2032 BatteryHolder Battery -0 -2 -2 -Battery -BatteryHolder_Keystone_2460_1xAA -https://www.keyelco.com/product-pdf.cfm?p=1025 -AA battery cell holder -0 -2 -2 -Battery -BatteryHolder_Keystone_2462_2xAA -2xAA cell battery holder, Keystone P/N 2462, https://www.keyelco.com/product-pdf.cfm?p=1027 -AA battery cell holder -0 -2 -2 -Battery -BatteryHolder_Keystone_2466_1xAAA -1xAAA Battery Holder, Keystone, Plastic Case, http://www.keyelco.com/product-pdf.cfm?p=1031 -AAA battery holder Keystone -0 -2 -2 -Battery -BatteryHolder_Keystone_2468_2xAAA -2xAAA cell battery holder, Keystone P/N 2468, http://www.keyelco.com/product-pdf.cfm?p=1033 -AAA battery cell holder -0 -2 -2 -Battery -BatteryHolder_Keystone_2479_3xAAA -3xAAA cell battery holder, Keystone P/N 2479, http://www.keyelco.com/product-pdf.cfm?p=1041 -AAA battery cell holder -0 -2 -2 -Battery -BatteryHolder_Keystone_2993 -http://www.keyelco.com/product-pdf.cfm?p=776 -Keystone type 2993 negative battery contact -0 -1 -1 -Battery -BatteryHolder_Keystone_3000_1x12mm -http://www.keyelco.com/product-pdf.cfm?p=777 -Keystone type 3000 coin cell retainer -0 -3 -2 -Battery -BatteryHolder_Keystone_3001_1x12mm -http://www.keyelco.com/product-pdf.cfm?p=778 -Keystone type 3001 coin cell retainer -0 -3 -2 -Battery -BatteryHolder_Keystone_3002_1x2032 -https://www.tme.eu/it/Document/a823211ec201a9e209042d155fe22d2b/KEYS2996.pdf -BR2016 CR2016 DL2016 BR2020 CL2020 BR2025 CR2025 DL2025 DR2032 CR2032 DL2032 -0 -3 -2 -Battery -BatteryHolder_Keystone_3008_1x2450 -http://www.keyelco.com/product-pdf.cfm?p=786 -Keystone type 3008 coin cell retainer -0 -3 -2 -Battery -BatteryHolder_Keystone_3009_1x2450 -http://www.keyelco.com/product-pdf.cfm?p=787 -Keystone type 3009 coin cell retainer -0 -3 -2 -Battery -BatteryHolder_Keystone_3034_1x20mm -Keystone 3034 SMD battery holder for 2020, 2025 and 2032 coincell batteries. http://www.keyelco.com/product-pdf.cfm?p=798 -Keystone type 3034 coin cell retainer -0 -3 -2 -Battery -BatteryHolder_LINX_BAT-HLD-012-SMT -SMT battery holder for CR1216/1220/1225, https://linxtechnologies.com/wp/wp-content/uploads/bat-hld-012-smt.pdf -battery holder coin cell cr1216 cr1220 cr1225 -0 -3 -2 -Battery -BatteryHolder_MPD_BC2AAPC_2xAA -2xAA cell battery holder, Memory Protection Devices P/N BC2AAPC, http://www.memoryprotectiondevices.com/datasheets/BC2AAPC-datasheet.pdf -AA battery cell holder -0 -2 -2 -Battery -BatteryHolder_MPD_BC12AAPC_2xAA -2xAA cell battery holder, Memory Protection Devices P/N BC12AAPC, http://www.memoryprotectiondevices.com/datasheets/BC12AAPC-datasheet.pdf -AA battery cell holder -0 -2 -2 -Battery -BatteryHolder_MPD_BC2003_1x2032 -http://www.memoryprotectiondevices.com/datasheets/BC-2003-datasheet.pdf -BC2003 CR2032 2032 Battery Holder -0 -3 -2 -Battery -BatteryHolder_MPD_BH-18650-PC2 -18650 Battery Holder (http://www.memoryprotectiondevices.com/datasheets/BK-18650-PC2-datasheet.pdf) -18650 Battery Holder -0 -2 -2 -Battery -BatteryHolder_Seiko_MS621F -Seiko MS621F, https://www.sii.co.jp/en/me/files/2014/02/file_EXTENDED_PRDCT_SPEC_75_FILE_11.jpg -Seiko MS621F -0 -2 -2 -Battery -BatteryHolder_TruPower_BH-331P_3xAA -Keystone Battery Holder BH-331P Battery Type 3xAA (Script generated with StandardBox.py) (Keystone Battery Holder BH-331P Battery Type 3xAA) -Battery Holder BH-331P Battery Type 3xAA -0 -2 -2 -Battery -Battery_CR1225 -CR1225 battery -battery CR1225 coin cell -0 -0 -0 -Battery -Battery_Panasonic_CR1025-VSK_Vertical_CircularHoles -Panasonic CR-1025/VSK battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-1025 coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR1220-VCN_Vertical_CircularHoles -Panasonic CR-1220/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-1220 coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR1632-V1AN_Vertical_CircularHoles -Panasonic CR-1632-V1AN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-1632 coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR2025-V1AK_Vertical_CircularHoles -Panasonic CR-2025/V1AK battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-2025 coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR2032-VS1N_Vertical_CircularHoles -Panasonic CR-2032/VS1N battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-2032 coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR2354-VCN_Vertical_CircularHoles -Panasonic CR-2354/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-2354/VCN coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR2450-VAN_Vertical_CircularHoles -Panasonic CR-2450/VAN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-2450 coin cell -0 -2 -2 -Battery -Battery_Panasonic_CR2477-VCN_Vertical_CircularHoles -Panasonic CR-2477/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-2477 coin cell vertical -0 -2 -2 -Battery -Battery_Panasonic_CR3032-VCN_Vertical_CircularHoles -Panasonic CR-3032/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf -battery CR-3032 coin cell vertical -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.00u_PCB -Cherry MX keyswitch, 1.00u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.00u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.00u_Plate -Cherry MX keyswitch, 1.00u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.00u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.25u_PCB -Cherry MX keyswitch, 1.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.25u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.25u_Plate -Cherry MX keyswitch, 1.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.25u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.50u_PCB -Cherry MX keyswitch, 1.50u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.50u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.50u_Plate -Cherry MX keyswitch, 1.50u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.50u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.75u_PCB -Cherry MX keyswitch, 1.75u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.75u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_1.75u_Plate -Cherry MX keyswitch, 1.75u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 1.75u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.00u_PCB -Cherry MX keyswitch, 2.00u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.00u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.00u_Plate -Cherry MX keyswitch, 2.00u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.00u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.00u_Vertical_PCB -Cherry MX keyswitch, 2.00u, vertical, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.00u vertical PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.00u_Vertical_Plate -Cherry MX keyswitch, 2.00u, vertical, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.00u vertical plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.25u_PCB -Cherry MX keyswitch, 2.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.25u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.25u_Plate -Cherry MX keyswitch, 2.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.25u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.75u_PCB -Cherry MX keyswitch, 2.75u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.75u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_2.75u_Plate -Cherry MX keyswitch, 2.75u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 2.75u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_6.25u_PCB -Cherry MX keyswitch, 6.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 6.25u PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_6.25u_Plate -Cherry MX keyswitch, 6.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch 6.25u plate -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_ISOEnter_PCB -Cherry MX keyswitch, ISO Enter, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch ISO enter PCB -0 -2 -2 -Button_Switch_Keyboard -SW_Cherry_MX_ISOEnter_Plate -Cherry MX keyswitch, ISO Enter, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf -Cherry MX keyswitch ISO enter plate -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_1.00u -Matias/ALPS keyswitch, 1.00u, http://matias.ca/switches/ -Matias ALPS keyswitch 1.00u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_1.25u -Matias/ALPS keyswitch, 1.25u, http://matias.ca/switches/ -Matias ALPS keyswitch 1.25u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_1.50u -Matias/ALPS keyswitch, 1.50u, http://matias.ca/switches/ -Matias ALPS keyswitch 1.50u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_1.75u -Matias/ALPS keyswitch, 1.75u, http://matias.ca/switches/ -Matias ALPS keyswitch 1.75u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_2.00u -Matias/ALPS keyswitch, 2.00u, http://matias.ca/switches/ -Matias ALPS keyswitch 2.00u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_2.25u -Matias/ALPS keyswitch, 2.25u, http://matias.ca/switches/ -Matias ALPS keyswitch 2.25u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_2.75u -Matias/ALPS keyswitch, 2.75u, http://matias.ca/switches/ -Matias ALPS keyswitch 2.75u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_6.25u -Matias/ALPS keyswitch, 6.25u, http://matias.ca/switches/ -Matias ALPS keyswitch 6.25u -0 -2 -2 -Button_Switch_Keyboard -SW_Matias_ISOEnter -Matias/ALPS keyswitch, ISO Enter, http://matias.ca/switches/ -Matias ALPS keyswitch ISO enter -0 -2 -2 -Button_Switch_SMD -Nidec_Copal_SH-7010A -4-bit rotary coded switch, J-hook, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf -rotary switch bcd -0 -6 -5 -Button_Switch_SMD -Nidec_Copal_SH-7010B -4-bit rotary coded switch, gull wing, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf -rotary switch bcd -0 -6 -5 -Button_Switch_SMD -Nidec_Copal_SH-7040B -4-bit rotary coded switch, gull wing, Gray code, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf -rotary switch bcd -0 -5 -5 -Button_Switch_SMD -Panasonic_EVQPUJ_EVQPUA -http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf -SMD SMT SPST EVQPUJ EVQPUA -0 -4 -2 -Button_Switch_SMD -Panasonic_EVQPUK_EVQPUB -http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf -SMD SMT SPST EVQPUK EVQPUB -0 -4 -2 -Button_Switch_SMD -Panasonic_EVQPUL_EVQPUC -http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf -SMD SMT SPST EVQPUL EVQPUC -0 -4 -2 -Button_Switch_SMD -Panasonic_EVQPUM_EVQPUD -http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf -SMD SMT SPST EVQPUM EVQPUD -0 -4 -2 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_6.7x4.1mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 1x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -2 -2 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_6.7x4.1mm_W8.61mm_P2.54mm_LowProfile -SMD 1x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -2 -2 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_9.78x4.72mm_W8.61mm_P2.54mm -SMD 1x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x4.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -2 -2 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_Copal_CHS-01A_W5.08mm_P1.27mm_JPin -SMD 1x-dip-switch SPST Copal_CHS-01A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin -SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin -0 -2 -2 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_Copal_CHS-01B_W7.62mm_P1.27mm -SMD 1x-dip-switch SPST Copal_CHS-01B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD -SMD DIP Switch SPST Slide 7.62mm 300mil SMD -0 -2 -2 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_Copal_CVS-01xB_W5.9mm_P1mm -SMD 1x-dip-switch SPST Copal_CVS-01xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) -SMD DIP Switch SPST Slide 5.9mm 232mil -0 -6 -3 -Button_Switch_SMD -SW_DIP_SPSTx01_Slide_Omron_A6S-110x_W8.9mm_P2.54mm -SMD 1x-dip-switch SPST Omron_A6S-110x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -2 -2 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_6.7x6.64mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 2x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_6.7x6.64mm_W8.61mm_P2.54mm_LowProfile -SMD 2x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_9.78x7.26mm_W8.61mm_P2.54mm -SMD 2x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x7.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_Copal_CHS-02A_W5.08mm_P1.27mm_JPin -SMD 2x-dip-switch SPST Copal_CHS-02A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin -SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_Copal_CHS-02B_W7.62mm_P1.27mm -SMD 2x-dip-switch SPST Copal_CHS-02B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD -SMD DIP Switch SPST Slide 7.62mm 300mil SMD -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_Copal_CVS-02xB_W5.9mm_P1mm -SMD 2x-dip-switch SPST Copal_CVS-02xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) -SMD DIP Switch SPST Slide 5.9mm 232mil -0 -8 -5 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_KingTek_DSHP02TJ_W5.25mm_P1.27mm_JPin -SMD 2x-dip-switch SPST KingTek_DSHP02TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_KingTek_DSHP02TS_W7.62mm_P1.27mm -SMD 2x-dip-switch SPST KingTek_DSHP02TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_Omron_A6H-2101_W6.15mm_P1.27mm -SMD 2x-dip-switch SPST Omron_A6H-2101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) -SMD DIP Switch SPST Slide 6.15mm 242mil -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx02_Slide_Omron_A6S-210x_W8.9mm_P2.54mm -SMD 2x-dip-switch SPST Omron_A6S-210x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -4 -4 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_6.7x9.18mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 3x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -6 -6 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_6.7x9.18mm_W8.61mm_P2.54mm_LowProfile -SMD 3x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -6 -6 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_9.78x9.8mm_W8.61mm_P2.54mm -SMD 3x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x9.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -6 -6 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_Copal_CVS-03xB_W5.9mm_P1mm -SMD 3x-dip-switch SPST Copal_CVS-03xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) -SMD DIP Switch SPST Slide 5.9mm 232mil -0 -10 -7 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_KingTek_DSHP03TJ_W5.25mm_P1.27mm_JPin -SMD 3x-dip-switch SPST KingTek_DSHP03TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -6 -6 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_KingTek_DSHP03TS_W7.62mm_P1.27mm -SMD 3x-dip-switch SPST KingTek_DSHP03TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -6 -6 -Button_Switch_SMD -SW_DIP_SPSTx03_Slide_Omron_A6S-310x_W8.9mm_P2.54mm -SMD 3x-dip-switch SPST Omron_A6S-310x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -6 -6 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_6.7x11.72mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 4x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_6.7x11.72mm_W8.61mm_P2.54mm_LowProfile -SMD 4x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_9.78x12.34mm_W8.61mm_P2.54mm -SMD 4x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x12.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_Copal_CHS-04A_W5.08mm_P1.27mm_JPin -SMD 4x-dip-switch SPST Copal_CHS-04A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin -SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_Copal_CHS-04B_W7.62mm_P1.27mm -SMD 4x-dip-switch SPST Copal_CHS-04B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD -SMD DIP Switch SPST Slide 7.62mm 300mil SMD -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_Copal_CVS-04xB_W5.9mm_P1mm -SMD 4x-dip-switch SPST Copal_CVS-04xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) -SMD DIP Switch SPST Slide 5.9mm 232mil -0 -12 -9 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_KingTek_DSHP04TJ_W5.25mm_P1.27mm_JPin -SMD 4x-dip-switch SPST KingTek_DSHP04TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_KingTek_DSHP04TS_W7.62mm_P1.27mm -SMD 4x-dip-switch SPST KingTek_DSHP04TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_Omron_A6H-4101_W6.15mm_P1.27mm -SMD 4x-dip-switch SPST Omron_A6H-4101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) -SMD DIP Switch SPST Slide 6.15mm 242mil -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx04_Slide_Omron_A6S-410x_W8.9mm_P2.54mm -SMD 4x-dip-switch SPST Omron_A6S-410x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -8 -8 -Button_Switch_SMD -SW_DIP_SPSTx05_Slide_6.7x14.26mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 5x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -10 -10 -Button_Switch_SMD -SW_DIP_SPSTx05_Slide_6.7x14.26mm_W8.61mm_P2.54mm_LowProfile -SMD 5x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -10 -10 -Button_Switch_SMD -SW_DIP_SPSTx05_Slide_9.78x14.88mm_W8.61mm_P2.54mm -SMD 5x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x14.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -10 -10 -Button_Switch_SMD -SW_DIP_SPSTx05_Slide_KingTek_DSHP05TJ_W5.25mm_P1.27mm_JPin -SMD 5x-dip-switch SPST KingTek_DSHP05TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -10 -10 -Button_Switch_SMD -SW_DIP_SPSTx05_Slide_KingTek_DSHP05TS_W7.62mm_P1.27mm -SMD 5x-dip-switch SPST KingTek_DSHP05TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -10 -10 -Button_Switch_SMD -SW_DIP_SPSTx05_Slide_Omron_A6S-510x_W8.9mm_P2.54mm -SMD 5x-dip-switch SPST Omron_A6S-510x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -10 -10 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_6.7x16.8mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 6x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_6.7x16.8mm_W8.61mm_P2.54mm_LowProfile -SMD 6x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_9.78x17.42mm_W8.61mm_P2.54mm -SMD 6x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_Copal_CHS-06A_W5.08mm_P1.27mm_JPin -SMD 6x-dip-switch SPST Copal_CHS-06A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin -SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_Copal_CHS-06B_W7.62mm_P1.27mm -SMD 6x-dip-switch SPST Copal_CHS-06B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD -SMD DIP Switch SPST Slide 7.62mm 300mil SMD -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_KingTek_DSHP06TJ_W5.25mm_P1.27mm_JPin -SMD 6x-dip-switch SPST KingTek_DSHP06TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_KingTek_DSHP06TS_W7.62mm_P1.27mm -SMD 6x-dip-switch SPST KingTek_DSHP06TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_Omron_A6H-6101_W6.15mm_P1.27mm -SMD 6x-dip-switch SPST Omron_A6H-6101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) -SMD DIP Switch SPST Slide 6.15mm 242mil -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx06_Slide_Omron_A6S-610x_W8.9mm_P2.54mm -SMD 6x-dip-switch SPST Omron_A6S-610x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -12 -12 -Button_Switch_SMD -SW_DIP_SPSTx07_Slide_6.7x19.34mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 7x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -14 -14 -Button_Switch_SMD -SW_DIP_SPSTx07_Slide_6.7x19.34mm_W8.61mm_P2.54mm_LowProfile -SMD 7x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -14 -14 -Button_Switch_SMD -SW_DIP_SPSTx07_Slide_9.78x19.96mm_W8.61mm_P2.54mm -SMD 7x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x19.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -14 -14 -Button_Switch_SMD -SW_DIP_SPSTx07_Slide_KingTek_DSHP07TJ_W5.25mm_P1.27mm_JPin -SMD 7x-dip-switch SPST KingTek_DSHP07TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -14 -14 -Button_Switch_SMD -SW_DIP_SPSTx07_Slide_KingTek_DSHP07TS_W7.62mm_P1.27mm -SMD 7x-dip-switch SPST KingTek_DSHP07TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -14 -14 -Button_Switch_SMD -SW_DIP_SPSTx07_Slide_Omron_A6S-710x_W8.9mm_P2.54mm -SMD 7x-dip-switch SPST Omron_A6S-710x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -14 -14 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_6.7x21.88mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 8x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_6.7x21.88mm_W8.61mm_P2.54mm_LowProfile -SMD 8x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_9.78x22.5mm_W8.61mm_P2.54mm -SMD 8x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_Copal_CHS-08A_W5.08mm_P1.27mm_JPin -SMD 8x-dip-switch SPST Copal_CHS-08A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin -SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_Copal_CHS-08B_W7.62mm_P1.27mm -SMD 8x-dip-switch SPST Copal_CHS-08B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD -SMD DIP Switch SPST Slide 7.62mm 300mil SMD -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_Copal_CVS-08xB_W5.9mm_P1mm -SMD 8x-dip-switch SPST Copal_CVS-08xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) -SMD DIP Switch SPST Slide 5.9mm 232mil -0 -20 -17 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_KingTek_DSHP08TJ_W5.25mm_P1.27mm_JPin -SMD 8x-dip-switch SPST KingTek_DSHP08TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_KingTek_DSHP08TS_W7.62mm_P1.27mm -SMD 8x-dip-switch SPST KingTek_DSHP08TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_Omron_A6H-8101_W6.15mm_P1.27mm -SMD 8x-dip-switch SPST Omron_A6H-8101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) -SMD DIP Switch SPST Slide 6.15mm 242mil -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx08_Slide_Omron_A6S-810x_W8.9mm_P2.54mm -SMD 8x-dip-switch SPST Omron_A6S-810x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -16 -16 -Button_Switch_SMD -SW_DIP_SPSTx09_Slide_6.7x24.42mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 9x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -18 -18 -Button_Switch_SMD -SW_DIP_SPSTx09_Slide_6.7x24.42mm_W8.61mm_P2.54mm_LowProfile -SMD 9x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -18 -18 -Button_Switch_SMD -SW_DIP_SPSTx09_Slide_9.78x25.04mm_W8.61mm_P2.54mm -SMD 9x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x25.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -18 -18 -Button_Switch_SMD -SW_DIP_SPSTx09_Slide_KingTek_DSHP09TJ_W5.25mm_P1.27mm_JPin -SMD 9x-dip-switch SPST KingTek_DSHP09TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -18 -18 -Button_Switch_SMD -SW_DIP_SPSTx09_Slide_KingTek_DSHP09TS_W7.62mm_P1.27mm -SMD 9x-dip-switch SPST KingTek_DSHP09TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -18 -18 -Button_Switch_SMD -SW_DIP_SPSTx09_Slide_Omron_A6S-910x_W8.9mm_P2.54mm -SMD 9x-dip-switch SPST Omron_A6S-910x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -18 -18 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_6.7x26.96mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 10x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_6.7x26.96mm_W8.61mm_P2.54mm_LowProfile -SMD 10x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_9.78x27.58mm_W8.61mm_P2.54mm -SMD 10x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x27.58mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_Copal_CHS-10A_W5.08mm_P1.27mm_JPin -SMD 10x-dip-switch SPST Copal_CHS-10A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin -SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_Copal_CHS-10B_W7.62mm_P1.27mm -SMD 10x-dip-switch SPST Copal_CHS-10B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD -SMD DIP Switch SPST Slide 7.62mm 300mil SMD -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_KingTek_DSHP10TJ_W5.25mm_P1.27mm_JPin -SMD 10x-dip-switch SPST KingTek_DSHP10TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin -SMD DIP Switch SPST Slide 5.25mm 206mil JPin -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_KingTek_DSHP10TS_W7.62mm_P1.27mm -SMD 10x-dip-switch SPST KingTek_DSHP10TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) -SMD DIP Switch SPST Slide 7.62mm 300mil -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_Omron_A6H-10101_W6.15mm_P1.27mm -SMD 10x-dip-switch SPST Omron_A6H-10101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) -SMD DIP Switch SPST Slide 6.15mm 242mil -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx10_Slide_Omron_A6S-1010x_W8.9mm_P2.54mm -SMD 10x-dip-switch SPST Omron_A6S-1010x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) -SMD DIP Switch SPST Slide 8.9mm 350mil -0 -20 -20 -Button_Switch_SMD -SW_DIP_SPSTx11_Slide_6.7x29.5mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 11x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -22 -22 -Button_Switch_SMD -SW_DIP_SPSTx11_Slide_6.7x29.5mm_W8.61mm_P2.54mm_LowProfile -SMD 11x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -22 -22 -Button_Switch_SMD -SW_DIP_SPSTx11_Slide_9.78x30.12mm_W8.61mm_P2.54mm -SMD 11x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x30.12mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -22 -22 -Button_Switch_SMD -SW_DIP_SPSTx12_Slide_6.7x32.04mm_W6.73mm_P2.54mm_LowProfile_JPin -SMD 12x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin -SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin -0 -24 -24 -Button_Switch_SMD -SW_DIP_SPSTx12_Slide_6.7x32.04mm_W8.61mm_P2.54mm_LowProfile -SMD 12x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile -SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile -0 -24 -24 -Button_Switch_SMD -SW_DIP_SPSTx12_Slide_9.78x32.66mm_W8.61mm_P2.54mm -SMD 12x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x32.66mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD -SMD DIP Switch SPST Slide 8.61mm 338mil SMD -0 -24 -24 -Button_Switch_SMD -SW_MEC_5GSH9 -MEC 5G single pole normally-open tactile switch -switch normally-open pushbutton push-button -0 -4 -4 -Button_Switch_SMD -SW_Push_1P1T-SH_NO_CK_KMR2xxG -CK components KMR2 tactile switch with ground pin http://www.ckswitches.com/media/1479/kmr2.pdf -tactile switch kmr2 -0 -5 -3 -Button_Switch_SMD -SW_Push_1P1T_NO_6x6mm_H9.5mm -tactile push button, 6x6mm e.g. PTS645xx series, height=9.5mm -tact sw push 6mm smd -0 -4 -2 -Button_Switch_SMD -SW_Push_1P1T_NO_CK_KMR2 -CK components KMR2 tactile switch http://www.ckswitches.com/media/1479/kmr2.pdf -tactile switch kmr2 -0 -4 -2 -Button_Switch_SMD -SW_Push_1P1T_NO_CK_KSC6xxJ -CK components KSC6 tactile switch https://www.ckswitches.com/media/1972/ksc6.pdf -tactile switch ksc6 -0 -4 -2 -Button_Switch_SMD -SW_Push_1P1T_NO_CK_KSC7xxJ -CK components KSC7 tactile switch https://www.ckswitches.com/media/1973/ksc7.pdf -tactile switch ksc7 -0 -4 -2 -Button_Switch_SMD -SW_Push_1P1T_NO_CK_PTS125Sx43PSMTR -C&K Switches 1P1T SMD PTS125 Series 12mm Tact Switch with Pegs, https://www.ckswitches.com/media/1462/pts125.pdf -Button Tactile Switch SPST 1P1T -0 -4 -2 -Button_Switch_SMD -SW_Push_1P1T_NO_Vertical_Wuerth_434133025816 -https://katalog.we-online.com/em/datasheet/434133025816.pdf -tactile switch Wurth Wuerth -0 -4 -2 -Button_Switch_SMD -SW_Push_SPST_NO_Alps_SKRK -http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKRK/SKRKAHE020.html -SMD SMT button -0 -2 -2 -Button_Switch_SMD -SW_SP3T_PCM13 -Ultraminiature Surface Mount Slide Switch, right-angle, https://www.ckswitches.com/media/1424/pcm.pdf - -0 -8 -4 -Button_Switch_SMD -SW_SPDT_CK-JS102011SAQN -Sub-miniature slide switch, right-angle, http://www.ckswitches.com/media/1422/js.pdf -switch spdt -0 -3 -3 -Button_Switch_SMD -SW_SPDT_PCM12 -Ultraminiature Surface Mount Slide Switch, right-angle, https://www.ckswitches.com/media/1424/pcm.pdf - -0 -7 -3 -Button_Switch_SMD -SW_SPST_B3S-1000 -Surface Mount Tactile Switch for High-Density Packaging -Tactile Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_B3S-1100 -Surface Mount Tactile Switch for High-Density Packaging with Ground Terminal -Tactile Switch -0 -5 -3 -Button_Switch_SMD -SW_SPST_B3SL-1002P -Middle Stroke Tactile Switch, B3SL -Middle Stroke Tactile Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_B3SL-1022P -Middle Stroke Tactile Switch, B3SL -Middle Stroke Tactile Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_B3U-1000P -Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, without Ground Terminal, without Boss -Tactile Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_B3U-1000P-B -Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, without Ground Terminal, with Boss -Tactile Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_B3U-1100P -Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, with Ground Terminal, without Boss -Tactile Switch -0 -3 -3 -Button_Switch_SMD -SW_SPST_B3U-1100P-B -Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, with Ground Terminal, with Boss -Tactile Switch -0 -3 -3 -Button_Switch_SMD -SW_SPST_B3U-3000P -Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, without Ground Terminal, without Boss -Tactile Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_B3U-3000P-B -Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, without Ground Terminal, with Boss -Tactile Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_B3U-3100P -Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, with Ground Terminal, without Boss -Tactile Switch -0 -3 -3 -Button_Switch_SMD -SW_SPST_B3U-3100P-B -Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, with Ground Terminal, with Boss -Tactile Switch -0 -3 -3 -Button_Switch_SMD -SW_SPST_CK_KXT3 -https://www.ckswitches.com/media/1465/kxt3.pdf -Switch SPST KXT3 -0 -2 -2 -Button_Switch_SMD -SW_SPST_CK_RS282G05A3 -https://www.mouser.com/ds/2/60/RS-282G05A-SM_RT-1159762.pdf -SPST button tactile switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_EVPBF -Light Touch Switch - -0 -4 -2 -Button_Switch_SMD -SW_SPST_EVQP0 -Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE28.pdf - -0 -4 -2 -Button_Switch_SMD -SW_SPST_EVQP2 -Light Touch Switch - -0 -4 -2 -Button_Switch_SMD -SW_SPST_EVQP7A -Light Touch Switch,https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE20.pdf - -0 -4 -2 -Button_Switch_SMD -SW_SPST_EVQP7C -Light Touch Switch - -0 -4 -2 -Button_Switch_SMD -SW_SPST_EVQPE1 -Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE7.pdf - -0 -2 -2 -Button_Switch_SMD -SW_SPST_EVQQ2 -Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE28.pdf - -0 -4 -2 -Button_Switch_SMD -SW_SPST_FSMSM -http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=1437566-3&DocType=Customer+Drawing&DocLang=English -SPST button tactile switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_PTS645 -C&K Components SPST SMD PTS645 Series 6mm Tact Switch -SPST Button Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_PTS810 -C&K Components, PTS 810 Series, Microminiature SMT Top Actuated, http://www.ckswitches.com/media/1476/pts810.pdf -SPST Button Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_Panasonic_EVQPL_3PL_5PL_PT_A08 -Light Touch Switch, http://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE3.pdf -SMD SMT SPST EVQPL EVQPT -0 -6 -3 -Button_Switch_SMD -SW_SPST_Panasonic_EVQPL_3PL_5PL_PT_A15 -Light Touch Switch, http://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE3.pdf -SMD SMT SPST EVQPL EVQPT -0 -6 -3 -Button_Switch_SMD -SW_SPST_REED_CT05-XXXX-G1 -Coto Technologies SPST Reed Switch CT05-XXXX-G1 -Coto Reed SPST Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_REED_CT05-XXXX-J1 -Coto Technologies SPST Reed Switch CT05-XXXX-J1 -Coto Reed SPST Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_REED_CT10-XXXX-G1 -Coto Technologies SPST Reed Switch CT10-XXXX-G1 -Coto Reed SPST Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_REED_CT10-XXXX-G2 -Coto Technologies SPST Reed Switch CT10-XXXX-G2 -Coto Reed SPST Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_REED_CT10-XXXX-G4 -Coto Technologies SPST Reed Switch CT10-XXXX-G4 -Coto Reed SPST Switch -0 -2 -2 -Button_Switch_SMD -SW_SPST_SKQG_WithStem -ALPS 5.2mm Square Low-profile Type (Surface Mount) SKQG Series, With stem, http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKQG/SKQGAFE010.html -SPST Button Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_SKQG_WithoutStem -ALPS 5.2mm Square Low-profile Type (Surface Mount) SKQG Series, Without stem, http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKQG/SKQGAEE010.html -SPST Button Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_TL3305A -https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf -TL3305 Series Tact Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_TL3305B -https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf -TL3305 Series Tact Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_TL3305C -https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf -TL3305 Series Tact Switch -0 -4 -2 -Button_Switch_SMD -SW_SPST_TL3342 -Low-profile SMD Tactile Switch, https://www.e-switch.com/system/asset/product_line/data_sheet/165/TL3342.pdf -SPST Tactile Switch -0 -4 -2 -Button_Switch_THT -KSA_Tactile_SPST -KSA http://www.ckswitches.com/media/1457/ksa_ksl.pdf -SWITCH SMD KSA SW -0 -5 -5 -Button_Switch_THT -Nidec_Copal_SH-7010C -4-bit rotary coded switch, through-hole, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf -rotary switch bcd -0 -6 -5 -Button_Switch_THT -Push_E-Switch_KS01Q01 -E-Switch KS01Q01 http://spec_sheets.e-switch.com/specs/29-KS01Q01.pdf -Push Button -0 -4 -4 -Button_Switch_THT -SW_CW_GPTS203211B -SPST Off-On Pushbutton, 1A, 30V, CW Industries P/N GPTS203211B, http://switches-connectors-custom.cwind.com/Asset/GPTS203211BR2.pdf -SPST button switch Off-On -0 -2 -2 -Button_Switch_THT -SW_CuK_JS202011AQN_DPDT_Angled -CuK sub miniature slide switch, JS series, DPDT, right angle, http://www.ckswitches.com/media/1422/js.pdf -switch DPDT -0 -6 -6 -Button_Switch_THT -SW_CuK_JS202011CQN_DPDT_Straight -CuK sub miniature slide switch, JS series, DPDT, right angle, http://www.ckswitches.com/media/1422/js.pdf -switch DPDT -0 -6 -6 -Button_Switch_THT -SW_CuK_OS102011MA1QN1_SPDT_Angled -CuK miniature slide switch, OS series, SPDT, right angle, http://www.ckswitches.com/media/1428/os.pdf -switch SPDT -0 -5 -3 -Button_Switch_THT -SW_DIP_SPSTx01_Piano_10.8x4.1mm_W7.62mm_P2.54mm -1x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x4.1mm -DIP Switch SPST Piano 7.62mm 300mil -0 -2 -2 -Button_Switch_THT -SW_DIP_SPSTx01_Slide_6.7x4.1mm_W7.62mm_P2.54mm_LowProfile -1x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -2 -2 -Button_Switch_THT -SW_DIP_SPSTx01_Slide_9.78x4.72mm_W7.62mm_P2.54mm -1x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x4.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -2 -2 -Button_Switch_THT -SW_DIP_SPSTx02_Piano_10.8x6.64mm_W7.62mm_P2.54mm -2x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x6.64mm -DIP Switch SPST Piano 7.62mm 300mil -0 -4 -4 -Button_Switch_THT -SW_DIP_SPSTx02_Piano_CTS_Series194-2MSTN_W7.62mm_P2.54mm -2x-dip-switch SPST CTS_Series194-2MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -4 -4 -Button_Switch_THT -SW_DIP_SPSTx02_Slide_6.7x6.64mm_W7.62mm_P2.54mm_LowProfile -2x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -4 -4 -Button_Switch_THT -SW_DIP_SPSTx02_Slide_9.78x7.26mm_W7.62mm_P2.54mm -2x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x7.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -4 -4 -Button_Switch_THT -SW_DIP_SPSTx03_Piano_10.8x9.18mm_W7.62mm_P2.54mm -3x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x9.18mm -DIP Switch SPST Piano 7.62mm 300mil -0 -6 -6 -Button_Switch_THT -SW_DIP_SPSTx03_Piano_CTS_Series194-3MSTN_W7.62mm_P2.54mm -3x-dip-switch SPST CTS_Series194-3MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -6 -6 -Button_Switch_THT -SW_DIP_SPSTx03_Slide_6.7x9.18mm_W7.62mm_P2.54mm_LowProfile -3x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -6 -6 -Button_Switch_THT -SW_DIP_SPSTx03_Slide_9.78x9.8mm_W7.62mm_P2.54mm -3x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x9.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -6 -6 -Button_Switch_THT -SW_DIP_SPSTx04_Piano_10.8x11.72mm_W7.62mm_P2.54mm -4x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x11.72mm -DIP Switch SPST Piano 7.62mm 300mil -0 -8 -8 -Button_Switch_THT -SW_DIP_SPSTx04_Piano_CTS_Series194-4MSTN_W7.62mm_P2.54mm -4x-dip-switch SPST CTS_Series194-4MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -8 -8 -Button_Switch_THT -SW_DIP_SPSTx04_Slide_6.7x11.72mm_W7.62mm_P2.54mm_LowProfile -4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -8 -8 -Button_Switch_THT -SW_DIP_SPSTx04_Slide_9.78x12.34mm_W7.62mm_P2.54mm -4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x12.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -8 -8 -Button_Switch_THT -SW_DIP_SPSTx05_Piano_10.8x14.26mm_W7.62mm_P2.54mm -5x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x14.26mm -DIP Switch SPST Piano 7.62mm 300mil -0 -10 -10 -Button_Switch_THT -SW_DIP_SPSTx05_Piano_CTS_Series194-5MSTN_W7.62mm_P2.54mm -5x-dip-switch SPST CTS_Series194-5MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -10 -10 -Button_Switch_THT -SW_DIP_SPSTx05_Slide_6.7x14.26mm_W7.62mm_P2.54mm_LowProfile -5x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -10 -10 -Button_Switch_THT -SW_DIP_SPSTx05_Slide_9.78x14.88mm_W7.62mm_P2.54mm -5x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x14.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -10 -10 -Button_Switch_THT -SW_DIP_SPSTx06_Piano_10.8x16.8mm_W7.62mm_P2.54mm -6x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x16.8mm -DIP Switch SPST Piano 7.62mm 300mil -0 -12 -12 -Button_Switch_THT -SW_DIP_SPSTx06_Piano_CTS_Series194-6MSTN_W7.62mm_P2.54mm -6x-dip-switch SPST CTS_Series194-6MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -12 -12 -Button_Switch_THT -SW_DIP_SPSTx06_Slide_6.7x16.8mm_W7.62mm_P2.54mm_LowProfile -6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -12 -12 -Button_Switch_THT -SW_DIP_SPSTx06_Slide_9.78x17.42mm_W7.62mm_P2.54mm -6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -12 -12 -Button_Switch_THT -SW_DIP_SPSTx07_Piano_10.8x19.34mm_W7.62mm_P2.54mm -7x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x19.34mm -DIP Switch SPST Piano 7.62mm 300mil -0 -14 -14 -Button_Switch_THT -SW_DIP_SPSTx07_Piano_CTS_Series194-7MSTN_W7.62mm_P2.54mm -7x-dip-switch SPST CTS_Series194-7MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -14 -14 -Button_Switch_THT -SW_DIP_SPSTx07_Slide_6.7x19.34mm_W7.62mm_P2.54mm_LowProfile -7x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -14 -14 -Button_Switch_THT -SW_DIP_SPSTx07_Slide_9.78x19.96mm_W7.62mm_P2.54mm -7x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x19.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -14 -14 -Button_Switch_THT -SW_DIP_SPSTx08_Piano_10.8x21.88mm_W7.62mm_P2.54mm -8x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x21.88mm -DIP Switch SPST Piano 7.62mm 300mil -0 -16 -16 -Button_Switch_THT -SW_DIP_SPSTx08_Piano_CTS_Series194-8MSTN_W7.62mm_P2.54mm -8x-dip-switch SPST CTS_Series194-8MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -16 -16 -Button_Switch_THT -SW_DIP_SPSTx08_Slide_6.7x21.88mm_W7.62mm_P2.54mm_LowProfile -8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -16 -16 -Button_Switch_THT -SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm -8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -16 -16 -Button_Switch_THT -SW_DIP_SPSTx09_Piano_10.8x24.42mm_W7.62mm_P2.54mm -9x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x24.42mm -DIP Switch SPST Piano 7.62mm 300mil -0 -18 -18 -Button_Switch_THT -SW_DIP_SPSTx09_Piano_CTS_Series194-9MSTN_W7.62mm_P2.54mm -9x-dip-switch SPST CTS_Series194-9MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -18 -18 -Button_Switch_THT -SW_DIP_SPSTx09_Slide_6.7x24.42mm_W7.62mm_P2.54mm_LowProfile -9x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -18 -18 -Button_Switch_THT -SW_DIP_SPSTx09_Slide_9.78x25.04mm_W7.62mm_P2.54mm -9x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x25.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -18 -18 -Button_Switch_THT -SW_DIP_SPSTx10_Piano_10.8x26.96mm_W7.62mm_P2.54mm -10x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x26.96mm -DIP Switch SPST Piano 7.62mm 300mil -0 -20 -20 -Button_Switch_THT -SW_DIP_SPSTx10_Piano_CTS_Series194-10MSTN_W7.62mm_P2.54mm -10x-dip-switch SPST CTS_Series194-10MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -20 -20 -Button_Switch_THT -SW_DIP_SPSTx10_Slide_6.7x26.96mm_W7.62mm_P2.54mm_LowProfile -10x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -20 -20 -Button_Switch_THT -SW_DIP_SPSTx10_Slide_9.78x27.58mm_W7.62mm_P2.54mm -10x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x27.58mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -20 -20 -Button_Switch_THT -SW_DIP_SPSTx11_Piano_10.8x29.5mm_W7.62mm_P2.54mm -11x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x29.5mm -DIP Switch SPST Piano 7.62mm 300mil -0 -22 -22 -Button_Switch_THT -SW_DIP_SPSTx11_Piano_CTS_Series194-11MSTN_W7.62mm_P2.54mm -11x-dip-switch SPST CTS_Series194-11MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -22 -22 -Button_Switch_THT -SW_DIP_SPSTx11_Slide_6.7x29.5mm_W7.62mm_P2.54mm_LowProfile -11x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -22 -22 -Button_Switch_THT -SW_DIP_SPSTx11_Slide_9.78x30.12mm_W7.62mm_P2.54mm -11x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x30.12mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -22 -22 -Button_Switch_THT -SW_DIP_SPSTx12_Piano_10.8x32.04mm_W7.62mm_P2.54mm -12x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x32.04mm -DIP Switch SPST Piano 7.62mm 300mil -0 -24 -24 -Button_Switch_THT -SW_DIP_SPSTx12_Piano_CTS_Series194-12MSTN_W7.62mm_P2.54mm -12x-dip-switch SPST CTS_Series194-12MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) -DIP Switch SPST Piano 7.62mm 300mil -0 -24 -24 -Button_Switch_THT -SW_DIP_SPSTx12_Slide_6.7x32.04mm_W7.62mm_P2.54mm_LowProfile -12x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile -DIP Switch SPST Slide 7.62mm 300mil LowProfile -0 -24 -24 -Button_Switch_THT -SW_DIP_SPSTx12_Slide_9.78x32.66mm_W7.62mm_P2.54mm -12x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x32.66mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) -DIP Switch SPST Slide 7.62mm 300mil -0 -24 -24 -Button_Switch_THT -SW_E-Switch_EG1224_SPDT_Angled -E-Switch slide switch, EG series, SPDT, right angle, http://spec_sheets.e-switch.com/specs/P040042.pdf -switch SPDT -0 -7 -3 -Button_Switch_THT -SW_E-Switch_EG1271_DPDT -E-Switch sub miniature slide switch, EG series, DPDT, http://spec_sheets.e-switch.com/specs/P040047.pdf -switch DPDT -0 -6 -6 -Button_Switch_THT -SW_E-Switch_EG2219_DPDT_Angled -E-Switch slide switch, EG series, DPDT, right angle, http://spec_sheets.e-switch.com/specs/P040170.pdf -switch DPDT -0 -10 -6 -Button_Switch_THT -SW_Lever_1P2T_NKK_GW12LxH -Switch, single pole double throw, right angle, http://www.nkkswitches.com/pdf/GW.pdf -switch single-pole double-throw spdt ON-ON horizontal -0 -5 -3 -Button_Switch_THT -SW_MEC_5GTH9 -MEC 5G single pole normally-open tactile switch https://cdn.sos.sk/productdata/80/f6/aabf7be6/5gth9358222.pdf -switch normally-open pushbutton push-button -0 -4 -2 -Button_Switch_THT -SW_NKK_BB15AH -https://www.nkkswitches.com/pdf/Bpushbuttons-1.pdf -Pushbutton Right-angle -0 -5 -3 -Button_Switch_THT -SW_NKK_G1xJP -Switch NKK G1xJP http://www.nkkswitches.com/pdf/gwillum.pdf -SWITCH TOGGLE ILLUM SPDT NKK -0 -6 -6 -Button_Switch_THT -SW_NKK_GW12LJP -Switch, single pole double throw, illuminated paddle, http://www.nkkswitches.com/pdf/gwillum.pdf -switch single-pole double-throw spdt ON-ON illuminated LED -0 -6 -6 -Button_Switch_THT -SW_PUSH-12mm -SW PUSH 12mm https://www.e-switch.com/system/asset/product_line/data_sheet/143/TL1100.pdf -tact sw push 12mm -0 -4 -2 -Button_Switch_THT -SW_PUSH-12mm_Wuerth-430476085716 -SW PUSH 12mm http://katalog.we-online.de/em/datasheet/430476085716.pdf -tact sw push 12mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm -https://www.omron.com/ecb/products/pdf/en-b3f.pdf -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H4.3mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=4.3mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H5mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=5mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H7.3mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=7.3mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H8.5mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=8.5mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H8mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=8mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H9.5mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=9.5mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_6mm_H13mm -tactile push button, 6x6mm e.g. PHAP33xx series, height=13mm -tact sw push 6mm -0 -4 -2 -Button_Switch_THT -SW_PUSH_E-Switch_FS5700DP_DPDT -FS5700 series pushbutton footswitch, DPDT, https://www.e-switch.com/system/asset/product_line/data_sheet/226/FS5700.pdf -switch DPDT footswitch -0 -6 -6 -Button_Switch_THT -SW_PUSH_LCD_E3_SAxxxx -Switch with LCD screen E3 SAxxxx -switch normally-open pushbutton push-button LCD -0 -6 -6 -Button_Switch_THT -SW_PUSH_LCD_E3_SAxxxx_SocketPins -Switch with LCD screen E3 SAxxxx -switch normally-open pushbutton push-button LCD -0 -6 -6 -Button_Switch_THT -SW_Push_1P1T_NO_LED_E-Switch_TL1250 -illuminated right angle tact switch https://www.e-switch.com/system/asset/product_line/data_sheet/148/TL1250.pdf -led push switch right angle -0 -6 -4 -Button_Switch_THT -SW_Push_1P2T_Vertical_E-Switch_800UDP8P1A1M6 - right angle SPDT push button https://www.e-switch.com/system/asset/product_line/data_sheet/210/800U.pdf -IP67 ultra-miniture horizontal -0 -5 -3 -Button_Switch_THT -SW_Push_2P2T_Vertical_E-Switch_800UDP8P1A1M6 - right angle DPDT push button https://www.e-switch.com/system/asset/product_line/data_sheet/210/800U.pdf -IP67 ultra-miniture horizontal -0 -8 -6 -Button_Switch_THT -SW_Slide_1P2T_CK_OS102011MS2Q -CuK miniature slide switch, OS series, SPDT, https://www.ckswitches.com/media/1428/os.pdf -switch SPDT -0 -5 -3 -Button_Switch_THT -SW_TH_Tactile_Omron_B3F-10xx -SW_TH_Tactile_Omron_B3F-10xx_https://www.omron.com/ecb/products/pdf/en-b3f.pdf -Omron B3F-10xx -0 -4 -4 -Button_Switch_THT -SW_Tactile_SKHH_Angled -tactile switch 6mm ALPS SKHH right angle http://www.alps.com/prod/info/E/HTML/Tact/SnapIn/SKHH/SKHHLUA010.html -tactile switch 6mm ALPS SKHH right angle -0 -4 -2 -Button_Switch_THT -SW_Tactile_SPST_Angled_PTS645Vx31-2LFS -tactile switch SPST right angle, PTS645VL31-2 LFS -tactile switch SPST angled PTS645VL31-2 LFS C&K Button -0 -4 -2 -Button_Switch_THT -SW_Tactile_SPST_Angled_PTS645Vx39-2LFS -tactile switch SPST right angle, PTS645VL39-2 LFS -tactile switch SPST angled PTS645VL39-2 LFS C&K Button -0 -4 -2 -Button_Switch_THT -SW_Tactile_SPST_Angled_PTS645Vx58-2LFS -tactile switch SPST right angle, PTS645VL58-2 LFS -tactile switch SPST angled PTS645VL58-2 LFS C&K Button -0 -4 -2 -Button_Switch_THT -SW_Tactile_SPST_Angled_PTS645Vx83-2LFS -tactile switch SPST right angle, PTS645VL83-2 LFS -tactile switch SPST angled PTS645VL83-2 LFS C&K Button -0 -4 -2 -Button_Switch_THT -SW_Tactile_Straight_KSA0Axx1LFTR -SW PUSH SMALL http://www.ckswitches.com/media/1457/ksa_ksl.pdf -SW PUSH SMALL Tactile C&K -0 -4 -2 -Button_Switch_THT -SW_Tactile_Straight_KSL0Axx1LFTR -SW PUSH SMALL http://www.ckswitches.com/media/1457/ksa_ksl.pdf -SW PUSH SMALL Tactile C&K -0 -4 -2 -Buzzer_Beeper -Buzzer_12x9.5RM7.6 -Generic Buzzer, D12mm height 9.5mm with RM7.6mm -buzzer -0 -2 -2 -Buzzer_Beeper -Buzzer_15x7.5RM7.6 -Generic Buzzer, D15mm height 7.5mm with RM7.6mm -buzzer -0 -2 -2 -Buzzer_Beeper -Buzzer_CUI_CPT-9019S-SMT -https://www.cui.com/product/resource/cpt-9019s-smt.pdf -buzzer piezo -0 -2 -2 -Buzzer_Beeper -Buzzer_D14mm_H7mm_P10mm -Generic Buzzer, D14mm height 7mm with pitch 10mm -buzzer -0 -2 -2 -Buzzer_Beeper -Buzzer_Mallory_AST1109MLTRQ -Mallory low-profile piezo buzzer, https://www.mspindy.com/specifications/AST1109MLTRQ.pdf -buzzer piezo -0 -2 -2 -Buzzer_Beeper -Buzzer_Murata_PKMCS0909E4000-R1 -Murata Buzzer http://www.murata.com/en-us/api/pdfdownloadapi?cate=&partno=PKMCS0909E4000-R1 -Murata Buzzer Beeper -0 -2 -2 -Buzzer_Beeper -Buzzer_TDK_PS1240P02BT_D12.2mm_H6.5mm -Buzzer, D12.2mm height 6.5mm, https://product.tdk.com/info/en/catalog/datasheets/piezoelectronic_buzzer_ps_en.pdf -buzzer -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_CUI_CST-931RP-A -CST-931RP-A, http://www.cui.com/product/resource/cst-931rp-a.pdf -CST-931RP-A -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_Kingstate_KCG0601 -Buzzer, Elektromagnetic Beeper, Summer, -Kingstate KCG0601 -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_Kobitone_254-EMB84Q-RO -MagneticBuzzer Kobitone 254-EMB84Q-RO https://www.mouser.es/datasheet/2/209/KT-400385-1171904.pdf -MagneticBuzzer Kobitone 254-EMB84Q-RO -0 -3 -3 -Buzzer_Beeper -MagneticBuzzer_PUI_AT-0927-TT-6-R -Buzzer Magnetic 9mm AT-0927-TT-6-R, http://www.puiaudio.com/pdf/AT-0927-TT-6-R.pdf -Buzzer Magnetic 9mm AT-0927-TT-6-R -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_ProSignal_ABI-009-RC -Buzzer, Elektromagnetic Beeper, Summer, 6V-DC, -Pro Signal ABI-009-RC -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_ProSignal_ABI-010-RC -Buzzer, Elektromagnetic Beeper, Summer, 12V-DC, -Pro Signal ABI-010-RC -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_ProSignal_ABT-410-RC -Buzzer, Elektromagnetic Beeper, Summer, 1,5V-DC, -Pro Signal ABT-410-RC -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_ProjectsUnlimited_AI-4228-TWT-R -Buzzer, Elektromagnetic Beeper, Summer, 3-28V-DC, https://www.kynix.com/uploadfiles/pdf/AI-4228-TWT-R.pdf -Projects Unlimited AI-4228-TWT-R -0 -2 -2 -Buzzer_Beeper -MagneticBuzzer_StarMicronics_HMB-06_HMB-12 -Buzzer, Elektromagnetic Beeper, Summer, -Star Micronics HMB-06 HMB-12 -0 -2 -2 -Buzzer_Beeper -PUIAudio_SMT_0825_S_4_R -SMD 8540, http://www.puiaudio.com/product-detail.aspx?partnumber=SMT-0825-S-4-R -SMD 8540 -0 -4 -4 -Calibration_Scale -Gauge_10mm_Type1_CopperTop -Gauge, Massstab, 10mm, CopperTop, Type 1, -Gauge Massstab 10mm CopperTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type1_SilkScreenTop -Gauge, Massstab, 10mm, SilkScreenTop, Type 1, -Gauge Massstab 10mm SilkScreenTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type2_CopperTop -Gauge, Massstab, 10mm, CopperTop, Type 2, -Gauge Massstab 10mm CopperTop Type 2 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type2_SilkScreenTop -Gauge, Massstab, 10mm, SilkScreenTop, Type 2, -Gauge Massstab 10mm SilkScreenTop Type 2 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type3_CopperTop -Gauge, Massstab, 10mm, CopperTop, Type 3, -Gauge Massstab 10mm CopperTop Type 3 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type3_SilkScreenTop -Gauge, Massstab, 10mm, SilkScreenTop, Type 3, -Gauge Massstab 10mm SilkScreenTop Type 3 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type4_CopperTop -Gauge, Massstab, 10mm, CopperTop, Type 4, -Gauge Massstab 10mm CopperTop Type 4 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type4_SilkScreenTop -Gauge, Massstab, 10mm, SilkScreenTop, Type 4, -Gauge Massstab 10mm SilkScreenTop Type 4 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type5_CopperTop -Gauge, Massstab, 10mm, CopperTop, Type 5, -Gauge Massstab 10mm CopperTop Type 5 -0 -0 -0 -Calibration_Scale -Gauge_10mm_Type5_SilkScreenTop -Gauge, Massstab, 10mm, SilkScreenTop, Type 5, -Gauge Massstab 10mm SilkScreenTop Type 5 -0 -0 -0 -Calibration_Scale -Gauge_50mm_Type1_CopperTop -Gauge, Massstab, 50mm, CopperTop, Type 1, -Gauge Massstab 50mm CopperTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_50mm_Type1_SilkScreenTop -Gauge, Massstab, 50mm, SilkScreenTop, Type 1, -Gauge Massstab 50mm SilkScreenTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_50mm_Type2_CopperTop -Gauge, Massstab, 50mm, CopperTop, Type 2, -Gauge Massstab 50mm CopperTop Type 2 -0 -0 -0 -Calibration_Scale -Gauge_50mm_Type2_SilkScreenTop -Gauge, Massstab, 50mm, SilkScreenTop, Type 2, -Gauge Massstab 50mm SilkScreenTop Type 2 -0 -0 -0 -Calibration_Scale -Gauge_100mm_Grid_Type1_CopperTop -Gauge, Massstab, 100mm, Gitter, Grid, CopperTop, Type 1, -Gauge Massstab 100mm Gitter Grid CopperTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_100mm_Type1_CopperTop -Gauge, Massstab, 100mm, CopperTop, Type 1, -Gauge Massstab 100mm CopperTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_100mm_Type1_SilkScreenTop -Gauge, Massstab, 100mm, SilkScreenTop, Type 1, -Gauge Massstab 100mm SilkScreenTop Type 1 -0 -0 -0 -Calibration_Scale -Gauge_100mm_Type2_CopperTop -Gauge, Massstab, 100mm, CopperTop, Type 2, -Gauge Massstab 100mm CopperTop Type 2 -0 -0 -0 -Calibration_Scale -Gauge_100mm_Type2_SilkScreenTop -Gauge, Massstab, 100mm, SilkScreenTop, Type 2, -Gauge Massstab 100mm SilkScreenTop Type 2 -0 -0 -0 -Capacitor_SMD -CP_Elec_3x5.3 -SMT capacitor, aluminium electrolytic, 3x5.3, Cornell Dubilier Electronics -Capacitor Electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_3x5.4 -SMD capacitor, aluminum electrolytic, Nichicon, 3.0x5.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x3 -SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x3.9 -SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x4.5 -SMD capacitor, aluminum electrolytic, Nichicon, 4.0x4.5mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x5.3 -SMD capacitor, aluminum electrolytic, Vishay, 4.0x5.3mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x5.4 -SMD capacitor, aluminum electrolytic, Panasonic A5 / Nichicon, 4.0x5.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x5.7 -SMD capacitor, aluminum electrolytic, United Chemi-Con, 4.0x5.7mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_4x5.8 -SMD capacitor, aluminum electrolytic, Panasonic, 4.0x5.8mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x3 -SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.0mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x3.9 -SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x4.4 -SMD capacitor, aluminum electrolytic, Panasonic B45, 5.0x4.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x4.5 -SMD capacitor, aluminum electrolytic, Nichicon, 5.0x4.5mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x5.3 -SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.3mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x5.4 -SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x5.7 -SMD capacitor, aluminum electrolytic, United Chemi-Con, 5.0x5.7mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x5.8 -SMD capacitor, aluminum electrolytic, Panasonic, 5.0x5.8mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_5x5.9 -SMD capacitor, aluminum electrolytic, Panasonic B6, 5.0x5.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x3 -SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.0mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x3.9 -SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x4.5 -SMD capacitor, aluminum electrolytic, Nichicon, 6.3x4.5mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x4.9 -SMD capacitor, aluminum electrolytic, Panasonic C5, 6.3x4.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.2 -SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.2mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.3 -SMD capacitor, aluminum electrolytic, Cornell Dubilier, 6.3x5.3mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.4 -SMD capacitor, aluminum electrolytic, Panasonic C55, 6.3x5.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.4_Nichicon -SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.7 -SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.7mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.8 -SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.8mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x5.9 -SMD capacitor, aluminum electrolytic, Panasonic C6, 6.3x5.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x7.7 -SMD capacitor, aluminum electrolytic, Nichicon, 6.3x7.7mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_6.3x9.9 -SMD capacitor, aluminum electrolytic, Panasonic C10, 6.3x9.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x5.4 -SMD capacitor, aluminum electrolytic, Nichicon, 8.0x5.4mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x6.2 -SMD capacitor, aluminum electrolytic, Nichicon, 8.0x6.2mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x6.5 -SMD capacitor, aluminum electrolytic, Rubycon, 8.0x6.5mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x6.7 -SMD capacitor, aluminum electrolytic, United Chemi-Con, 8.0x6.7mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x6.9 -SMD capacitor, aluminum electrolytic, Panasonic E7, 8.0x6.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x10 -SMD capacitor, aluminum electrolytic, Nichicon, 8.0x10mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x10.5 -SMD capacitor, aluminum electrolytic, Vishay 0810, 8.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_8x11.9 -SMD capacitor, aluminum electrolytic, Panasonic E12, 8.0x11.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x7.7 -SMD capacitor, aluminum electrolytic, Nichicon, 10.0x7.7mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x7.9 -SMD capacitor, aluminum electrolytic, Panasonic F8, 10.0x7.9mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x10 -SMD capacitor, aluminum electrolytic, Nichicon, 10.0x10.0mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x10.5 -SMD capacitor, aluminum electrolytic, Vishay 1010, 10.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x12.5 -SMD capacitor, aluminum electrolytic, Vishay 1012, 10.0x12.5mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x12.6 -SMD capacitor, aluminum electrolytic, Panasonic F12, 10.0x12.6mm -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_10x14.3 -SMD capacitor, aluminum electrolytic, Vishay 1014, 10.0x14.3mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_16x17.5 -SMD capacitor, aluminum electrolytic, Vishay 1616, 16.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_16x22 -SMD capacitor, aluminum electrolytic, Vishay 1621, 16.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_18x17.5 -SMD capacitor, aluminum electrolytic, Vishay 1816, 18.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -CP_Elec_18x22 -SMD capacitor, aluminum electrolytic, Vishay 1821, 18.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf -capacitor electrolytic -0 -2 -2 -Capacitor_SMD -C_0201_0603Metric -Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator -capacitor -0 -4 -2 -Capacitor_SMD -C_0402_1005Metric -Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_0603_1608Metric -Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_0603_1608Metric_Pad1.05x0.95mm_HandSolder -Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_0805_2012Metric -Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_0805_2012Metric_Pad1.15x1.40mm_HandSolder -Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_01005_0402Metric -Capacitor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator -capacitor -0 -4 -2 -Capacitor_SMD -C_1206_3216Metric -Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_1206_3216Metric_Pad1.42x1.75mm_HandSolder -Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_1210_3225Metric -Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_1210_3225Metric_Pad1.42x2.65mm_HandSolder -Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_1806_4516Metric -Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_1806_4516Metric_Pad1.57x1.80mm_HandSolder -Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_1812_4532Metric -Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_1812_4532Metric_Pad1.30x3.40mm_HandSolder -Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_1825_4564Metric -Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_1825_4564Metric_Pad1.88x6.70mm_HandSolder -Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_2010_5025Metric -Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_2010_5025Metric_Pad1.52x2.65mm_HandSolder -Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_2220_5650Metric -Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_2220_5650Metric_Pad1.97x5.40mm_HandSolder -Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_2225_5664Metric -Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_2225_5664Metric_Pad1.80x6.60mm_HandSolder -Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_2512_6332Metric -Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_2512_6332Metric_Pad1.52x3.35mm_HandSolder -Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_2816_7142Metric -Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_2816_7142Metric_Pad3.20x4.45mm_HandSolder -Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_3640_9110Metric -Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor -0 -2 -2 -Capacitor_SMD -C_3640_9110Metric_Pad2.10x10.45mm_HandSolder -Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator -capacitor handsolder -0 -2 -2 -Capacitor_SMD -C_Elec_3x5.4 -SMD capacitor, aluminum electrolytic nonpolar, 3.0x5.4mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_4x5.4 -SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.4mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_4x5.8 -SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.8mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_5x5.4 -SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.4mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_5x5.8 -SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.8mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_6.3x5.4 -SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.4mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_6.3x5.8 -SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.8mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_6.3x7.7 -SMD capacitor, aluminum electrolytic nonpolar, 6.3x7.7mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_8x5.4 -SMD capacitor, aluminum electrolytic nonpolar, 8.0x5.4mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_8x6.2 -SMD capacitor, aluminum electrolytic nonpolar, 8.0x6.2mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_8x10.2 -SMD capacitor, aluminum electrolytic nonpolar, 8.0x10.2mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Elec_10x10.2 -SMD capacitor, aluminum electrolytic nonpolar, 10.0x10.2mm -capacitor electrolyic nonpolar -0 -2 -2 -Capacitor_SMD -C_Trimmer_Murata_TZB4-A -trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb - Murata TZB4 TZB4-A -0 -2 -2 -Capacitor_SMD -C_Trimmer_Murata_TZB4-B -trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb - Murata TZB4 TZB4-A -0 -2 -2 -Capacitor_SMD -C_Trimmer_Murata_TZC3 -trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb - Murata TZC3 -0 -2 -2 -Capacitor_SMD -C_Trimmer_Murata_TZR1 -trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb - Murata TZR1 -0 -2 -2 -Capacitor_SMD -C_Trimmer_Murata_TZW4 -trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb - Murata TZW4 -0 -2 -2 -Capacitor_SMD -C_Trimmer_Murata_TZY2 -trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb - Murata TZY2 -0 -2 -2 -Capacitor_SMD -C_Trimmer_Sprague-Goodman_SGC3 -trimmer capacitor SMD horizontal, http://media.wix.com/ugd/d86717_38d9821e12823a7aa9cef38c6c2a73cc.pdf - Sprague Goodman SGC3 -0 -2 -2 -Capacitor_SMD -C_Trimmer_Voltronics_JN -trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf - Voltronics JN -0 -2 -2 -Capacitor_SMD -C_Trimmer_Voltronics_JQ -trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf - Voltronics JQ -0 -2 -2 -Capacitor_SMD -C_Trimmer_Voltronics_JR -trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf - Voltronics JR -0 -2 -2 -Capacitor_SMD -C_Trimmer_Voltronics_JV -trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf - Voltronics JV -0 -2 -2 -Capacitor_SMD -C_Trimmer_Voltronics_JZ -trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf - Voltronics JR -0 -2 -2 -Capacitor_THT -CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*4.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 15mm length 10mm diameter 4.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L10.0mm_D6.0mm_P15.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*6mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 15mm length 10mm diameter 6mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L11.0mm_D5.0mm_P18.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*5mm^2, Electrolytic Capacitor -CP Axial series Axial Horizontal pin pitch 18mm length 11mm diameter 5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*6mm^2, Electrolytic Capacitor -CP Axial series Axial Horizontal pin pitch 18mm length 11mm diameter 6mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L11.0mm_D8.0mm_P15.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=11*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 15mm length 11mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*6.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 6.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L18.0mm_D10.0mm_P25.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L20.0mm_D10.0mm_P26.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 26mm length 20mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L20.0mm_D13.0mm_P26.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 26mm length 20mm diameter 13mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L21.0mm_D8.0mm_P28.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=28mm, , length*diameter=21*8mm^2, Electrolytic Capacitor -CP Axial series Axial Horizontal pin pitch 28mm length 21mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L25.0mm_D10.0mm_P30.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=30mm, , length*diameter=25*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 30mm length 25mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L26.5mm_D20.0mm_P33.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=33mm, , length*diameter=26.5*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 33mm length 26.5mm diameter 20mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L29.0mm_D10.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L29.0mm_D13.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 13mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L29.0mm_D16.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*16mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 16mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L29.0mm_D20.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 20mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L30.0mm_D10.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L30.0mm_D12.5mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*12.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 12.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L30.0mm_D15.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*15mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 15mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L30.0mm_D18.0mm_P35.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*18mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 18mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L34.5mm_D20.0mm_P41.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=41mm, , length*diameter=34.5*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 41mm length 34.5mm diameter 20mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L37.0mm_D13.0mm_P43.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 43mm length 37mm diameter 13mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L37.0mm_D16.0mm_P43.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*16mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 43mm length 37mm diameter 16mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L37.0mm_D20.0mm_P43.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf -CP Axial series Axial Horizontal pin pitch 43mm length 37mm diameter 20mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L38.0mm_D18.0mm_P44.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=44mm, , length*diameter=38*18mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 44mm length 38mm diameter 18mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L38.0mm_D21.0mm_P44.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=44mm, , length*diameter=38*21mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf -CP Axial series Axial Horizontal pin pitch 44mm length 38mm diameter 21mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L40.0mm_D16.0mm_P48.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=48mm, , length*diameter=40*16mm^2, Electrolytic Capacitor -CP Axial series Axial Horizontal pin pitch 48mm length 40mm diameter 16mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L42.0mm_D23.0mm_P45.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 23.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L42.0mm_D26.0mm_P45.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 26mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L42.0mm_D29.0mm_P45.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 29.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L42.0mm_D32.0mm_P45.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 32.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L42.0mm_D35.0mm_P45.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 35.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L42.5mm_D20.0mm_P49.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=49mm, , length*diameter=42.5*20mm^2, Electrolytic Capacitor -CP Axial series Axial Horizontal pin pitch 49mm length 42.5mm diameter 20mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L46.0mm_D20.0mm_P52.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=52mm, , length*diameter=46*20mm^2, Electrolytic Capacitor -CP Axial series Axial Horizontal pin pitch 52mm length 46mm diameter 20mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L55.0mm_D23.0mm_P60.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 23.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L55.0mm_D26.0mm_P60.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 26mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L55.0mm_D29.0mm_P60.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 29.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L55.0mm_D32.0mm_P60.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 32.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L55.0mm_D35.0mm_P60.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 35.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L67.0mm_D23.0mm_P75.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 23.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L67.0mm_D26.0mm_P75.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 26mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L67.0mm_D29.0mm_P75.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 29.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L67.0mm_D32.0mm_P75.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 32.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L67.0mm_D35.0mm_P75.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 35.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L80.0mm_D23.0mm_P85.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 23.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L80.0mm_D26.0mm_P85.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 26mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L80.0mm_D29.0mm_P85.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 29.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L80.0mm_D32.0mm_P85.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 32.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L80.0mm_D35.0mm_P85.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 35.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L93.0mm_D23.0mm_P100.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 23.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L93.0mm_D26.0mm_P100.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 26mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L93.0mm_D29.0mm_P100.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 29.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L93.0mm_D32.0mm_P100.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 32.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Axial_L93.0mm_D35.0mm_P100.00mm_Horizontal -CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf -CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 35.0mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D4.0mm_P1.50mm -CP, Radial series, Radial, pin pitch=1.50mm, , diameter=4mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 1.50mm diameter 4mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D4.0mm_P2.00mm -CP, Radial series, Radial, pin pitch=2.00mm, , diameter=4mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.00mm diameter 4mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D5.0mm_P2.00mm -CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D5.0mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=5mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D6.3mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D7.5mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=7.5mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 7.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D8.0mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=8mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D8.0mm_P3.50mm -CP, Radial series, Radial, pin pitch=3.50mm, , diameter=8mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 3.50mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D8.0mm_P3.80mm -CP, Radial series, Radial, pin pitch=3.80mm, , diameter=8mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 3.80mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D8.0mm_P5.00mm -CP, Radial series, Radial, pin pitch=5.00mm, , diameter=8mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 5.00mm diameter 8mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D10.0mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D10.0mm_P2.50mm_P5.00mm -CP, Radial series, Radial, pin pitch=2.50mm 5.00mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm 5.00mm diameter 10mm Electrolytic Capacitor -0 -4 -2 -Capacitor_THT -CP_Radial_D10.0mm_P3.50mm -CP, Radial series, Radial, pin pitch=3.50mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 3.50mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D10.0mm_P3.80mm -CP, Radial series, Radial, pin pitch=3.80mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 3.80mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D10.0mm_P5.00mm -CP, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 5.00mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D10.0mm_P5.00mm_P7.50mm -CP, Radial series, Radial, pin pitch=5.00mm 7.50mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 5.00mm 7.50mm diameter 10mm Electrolytic Capacitor -0 -4 -2 -Capacitor_THT -CP_Radial_D10.0mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=10mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 10mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D12.5mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=12.5mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 12.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D12.5mm_P5.00mm -CP, Radial series, Radial, pin pitch=5.00mm, , diameter=12.5mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 5.00mm diameter 12.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D12.5mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=12.5mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 12.5mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D13.0mm_P2.50mm -CP, Radial series, Radial, pin pitch=2.50mm, , diameter=13mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 2.50mm diameter 13mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D13.0mm_P5.00mm -CP, Radial series, Radial, pin pitch=5.00mm, , diameter=13mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 5.00mm diameter 13mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D13.0mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=13mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 13mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D14.0mm_P5.00mm -CP, Radial series, Radial, pin pitch=5.00mm, , diameter=14mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 5.00mm diameter 14mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D14.0mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=14mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 14mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D16.0mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=16mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 16mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D17.0mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=17mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 17mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D18.0mm_P7.50mm -CP, Radial series, Radial, pin pitch=7.50mm, , diameter=18mm, Electrolytic Capacitor -CP Radial series Radial pin pitch 7.50mm diameter 18mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D22.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 22mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D22.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 22mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D24.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=24mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 24mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D24.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=24mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 24mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D25.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=25mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 25mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D25.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=25mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 25mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D26.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=26mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 26mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D26.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=26mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 26mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D30.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=30mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 30mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D30.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=30mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 30mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D35.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=35mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 35mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D35.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=35mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 35mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_D40.0mm_P10.00mm_3pin_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=40mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 40mm Electrolytic Capacitor -0 -3 -2 -Capacitor_THT -CP_Radial_D40.0mm_P10.00mm_SnapIn -CP, Radial series, Radial, pin pitch=10.00mm, , diameter=40mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf -CP Radial series Radial pin pitch 10.00mm diameter 40mm Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D4.5mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=4.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 4.5mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D4.5mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=4.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 4.5mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D5.0mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=5.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 5.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D5.0mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=5.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 5.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D5.5mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=5.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 5.5mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D5.5mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=5.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 5.5mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D6.0mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=6.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 6.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D6.0mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=6.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 6.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D7.0mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=7.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 7.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D7.0mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=7.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 7.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D8.0mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=8.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 8.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D8.0mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=8.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 8.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D9.0mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=9.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 9.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D9.0mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=9.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 9.0mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D10.5mm_P2.50mm -CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=10.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 2.50mm diameter 10.5mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -CP_Radial_Tantal_D10.5mm_P5.00mm -CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=10.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf -CP Radial_Tantal series Radial pin pitch 5.00mm diameter 10.5mm Tantal Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Axial_L3.8mm_D2.6mm_P7.50mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=7.5mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 7.5mm length 3.8mm diameter 2.6mm -0 -2 -2 -Capacitor_THT -C_Axial_L3.8mm_D2.6mm_P10.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=10mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 10mm length 3.8mm diameter 2.6mm -0 -2 -2 -Capacitor_THT -C_Axial_L3.8mm_D2.6mm_P12.50mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=12.5mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 12.5mm length 3.8mm diameter 2.6mm -0 -2 -2 -Capacitor_THT -C_Axial_L3.8mm_D2.6mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 15mm length 3.8mm diameter 2.6mm -0 -2 -2 -Capacitor_THT -C_Axial_L5.1mm_D3.1mm_P7.50mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=7.5mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 7.5mm length 5.1mm diameter 3.1mm -0 -2 -2 -Capacitor_THT -C_Axial_L5.1mm_D3.1mm_P10.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=10mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 10mm length 5.1mm diameter 3.1mm -0 -2 -2 -Capacitor_THT -C_Axial_L5.1mm_D3.1mm_P12.50mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=12.5mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 12.5mm length 5.1mm diameter 3.1mm -0 -2 -2 -Capacitor_THT -C_Axial_L5.1mm_D3.1mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf -C Axial series Axial Horizontal pin pitch 15mm length 5.1mm diameter 3.1mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D6.5mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 6.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D6.5mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 6.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D7.5mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 7.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D7.5mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 7.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D8.5mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*8.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 8.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D8.5mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*8.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 8.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D9.5mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 9.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D9.5mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 9.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D10.5mm_P15.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 10.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L12.0mm_D10.5mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 10.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L17.0mm_D6.5mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=17*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 17mm diameter 6.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L17.0mm_D6.5mm_P25.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=17*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 25mm length 17mm diameter 6.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L17.0mm_D7.0mm_P20.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=17*7.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 20mm length 17mm diameter 7.0mm -0 -2 -2 -Capacitor_THT -C_Axial_L17.0mm_D7.0mm_P25.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=17*7.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 25mm length 17mm diameter 7.0mm -0 -2 -2 -Capacitor_THT -C_Axial_L19.0mm_D7.5mm_P25.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 7.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L19.0mm_D8.0mm_P25.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*8.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 8.0mm -0 -2 -2 -Capacitor_THT -C_Axial_L19.0mm_D9.0mm_P25.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*9mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 9mm -0 -2 -2 -Capacitor_THT -C_Axial_L19.0mm_D9.5mm_P25.00mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 9.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L22.0mm_D9.5mm_P27.50mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=27.5mm, , length*diameter=22*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 27.5mm length 22mm diameter 9.5mm -0 -2 -2 -Capacitor_THT -C_Axial_L22.0mm_D10.5mm_P27.50mm_Horizontal -C, Axial series, Axial, Horizontal, pin pitch=27.5mm, , length*diameter=22*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf -C Axial series Axial Horizontal pin pitch 27.5mm length 22mm diameter 10.5mm -0 -2 -2 -Capacitor_THT -C_Disc_D3.0mm_W1.6mm_P2.50mm -C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf -C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D3.0mm_W2.0mm_P2.50mm -C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor -C Disc series Radial pin pitch 2.50mm diameter 3mm width 2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D3.4mm_W2.1mm_P2.50mm -C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.4*2.1mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf -C Disc series Radial pin pitch 2.50mm diameter 3.4mm width 2.1mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D3.8mm_W2.6mm_P2.50mm -C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf -C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D4.3mm_W1.9mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.3*1.9mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf -C Disc series Radial pin pitch 5.00mm diameter 4.3mm width 1.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D4.7mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf -C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D5.0mm_W2.5mm_P2.50mm -C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 2.50mm diameter 5mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D5.0mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D5.1mm_W3.2mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf -C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D6.0mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=6*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 5.00mm diameter 6mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D6.0mm_W4.4mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=6*4.4mm^2, Capacitor -C Disc series Radial pin pitch 5.00mm diameter 6mm width 4.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D7.0mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 5.00mm diameter 7mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D7.5mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*2.5mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 5.00mm diameter 7.5mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D7.5mm_W4.4mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*4.4mm^2, Capacitor -C Disc series Radial pin pitch 5.00mm diameter 7.5mm width 4.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D7.5mm_W5.0mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 5.00mm diameter 7.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D7.5mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 7.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D7.5mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 7.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D8.0mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=8*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 5.00mm diameter 8mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D8.0mm_W5.0mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 5.00mm diameter 8mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D8.0mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 8mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D8.0mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 8mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D9.0mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=9*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 5.00mm diameter 9mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D9.0mm_W5.0mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 5.00mm diameter 9mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D9.0mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 9mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D9.0mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 9mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D10.0mm_W2.5mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=10*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf -C Disc series Radial pin pitch 5.00mm diameter 10mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D10.5mm_W5.0mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 5.00mm diameter 10.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D10.5mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 10.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D10.5mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 10.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D11.0mm_W5.0mm_P5.00mm -C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 5.00mm diameter 11mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D11.0mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 11mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D11.0mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 11mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D12.0mm_W4.4mm_P7.75mm -C, Disc series, Radial, pin pitch=7.75mm, , diameter*width=12*4.4mm^2, Capacitor -C Disc series Radial pin pitch 7.75mm diameter 12mm width 4.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D12.5mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=12.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 12.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D12.5mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=12.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 12.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D14.5mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=14.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 14.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D14.5mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=14.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 14.5mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D16.0mm_W5.0mm_P7.50mm -C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=16.0*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 7.50mm diameter 16.0mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Disc_D16.0mm_W5.0mm_P10.00mm -C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=16.0*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf -C Disc series Radial pin pitch 10.00mm diameter 16.0mm width 5.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D4.0mm_H5.0mm_P1.50mm -C, Radial series, Radial, pin pitch=1.50mm, diameter=4mm, height=5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 1.50mm diameter 4mm height 5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D4.0mm_H7.0mm_P1.50mm -C, Radial series, Radial, pin pitch=1.50mm, diameter=4mm, height=7mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 1.50mm diameter 4mm height 7mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D5.0mm_H5.0mm_P2.00mm -C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 2.00mm diameter 5mm height 5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D5.0mm_H7.0mm_P2.00mm -C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=7mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 2.00mm diameter 5mm height 7mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D5.0mm_H11.0mm_P2.00mm -C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=11mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 2.00mm diameter 5mm height 11mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D6.3mm_H5.0mm_P2.50mm -C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D6.3mm_H7.0mm_P2.50mm -C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=7mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 7mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D6.3mm_H11.0mm_P2.50mm -C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=11mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 11mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D8.0mm_H7.0mm_P3.50mm -C, Radial series, Radial, pin pitch=3.50mm, diameter=8mm, height=7mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 3.50mm diameter 8mm height 7mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D8.0mm_H11.5mm_P3.50mm -C, Radial series, Radial, pin pitch=3.50mm, diameter=8mm, height=11.5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 3.50mm diameter 8mm height 11.5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D10.0mm_H12.5mm_P5.00mm -C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=12.5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 5.00mm diameter 10mm height 12.5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D10.0mm_H16.0mm_P5.00mm -C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=16mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 5.00mm diameter 10mm height 16mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D10.0mm_H20.0mm_P5.00mm -C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=20mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 5.00mm diameter 10mm height 20mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D12.5mm_H20.0mm_P5.00mm -C, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=20mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 5.00mm diameter 12.5mm height 20mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D12.5mm_H25.0mm_P5.00mm -C, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=25mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 5.00mm diameter 12.5mm height 25mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D16.0mm_H25.0mm_P7.50mm -C, Radial series, Radial, pin pitch=7.50mm, diameter=16mm, height=25mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 7.50mm diameter 16mm height 25mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D16.0mm_H31.5mm_P7.50mm -C, Radial series, Radial, pin pitch=7.50mm, diameter=16mm, height=31.5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 7.50mm diameter 16mm height 31.5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Radial_D18.0mm_H35.5mm_P7.50mm -C, Radial series, Radial, pin pitch=7.50mm, diameter=18mm, height=35.5mm, Non-Polar Electrolytic Capacitor -C Radial series Radial pin pitch 7.50mm diameter 18mm height 35.5mm Non-Polar Electrolytic Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L4.0mm_W2.5mm_P2.50mm -C, Rect series, Radial, pin pitch=2.50mm, , length*width=4*2.5mm^2, Capacitor -C Rect series Radial pin pitch 2.50mm length 4mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L4.6mm_W2.0mm_P2.50mm_MKS02_FKP02 -C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*2mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf -C Rect series Radial pin pitch 2.50mm length 4.6mm width 2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L4.6mm_W3.0mm_P2.50mm_MKS02_FKP02 -C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*3.0mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf -C Rect series Radial pin pitch 2.50mm length 4.6mm width 3.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L4.6mm_W3.8mm_P2.50mm_MKS02_FKP02 -C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*3.8mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf -C Rect series Radial pin pitch 2.50mm length 4.6mm width 3.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L4.6mm_W4.6mm_P2.50mm_MKS02_FKP02 -C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*4.6mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf -C Rect series Radial pin pitch 2.50mm length 4.6mm width 4.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L4.6mm_W5.5mm_P2.50mm_MKS02_FKP02 -C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*5.5mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf -C Rect series Radial pin pitch 2.50mm length 4.6mm width 5.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.0mm_W2.0mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*2mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7mm width 2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.0mm_W2.5mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*2.5mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.0mm_W3.5mm_P2.50mm_P5.00mm -C, Rect series, Radial, pin pitch=2.50mm 5.00mm, , length*width=7*3.5mm^2, Capacitor -C Rect series Radial pin pitch 2.50mm 5.00mm length 7mm width 3.5mm Capacitor -0 -4 -2 -Capacitor_THT -C_Rect_L7.0mm_W3.5mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*3.5mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7mm width 3.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.0mm_W4.5mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*4.5mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7mm width 4.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.0mm_W6.0mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*6mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7mm width 6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.0mm_W6.5mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*6.5mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7mm width 6.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*2.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W3.0mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*3.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 3.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W3.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*3.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 3.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W4.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*4.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 4.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W5.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*5.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 5.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W7.2mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*7.2mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 7.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W8.5mm_P5.00mm_FKP2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*8.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 8.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.2mm_W11.0mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf -C Rect series Radial pin pitch 5.00mm length 7.2mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L7.5mm_W6.5mm_P5.00mm -C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.5*6.5mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm length 7.5mm width 6.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W2.5mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W2.6mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 2.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 2.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W3.2mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 3.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W3.3mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 3.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W3.4mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 3.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W3.6mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 3.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W3.8mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 3.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W3.9mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 3.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W4.0mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 4.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W4.2mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 4.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W4.9mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 4.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W5.1mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 5.1mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W5.7mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*5.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 5.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W6.4mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 6.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W6.7mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*6.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 6.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W7.7mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*7.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 7.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W8.5mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*8.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 8.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W9.5mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*9.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 9.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L9.0mm_W9.8mm_P7.50mm_MKT -C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*9.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 7.50mm length 9mm width 9.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.0mm_W2.5mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*2.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10mm width 2.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.0mm_W3.0mm_P7.50mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*3mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 7.50mm length 10mm width 3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.0mm_W3.0mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*3.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10mm width 3.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.0mm_W4.0mm_P7.50mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 7.50mm length 10mm width 4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.0mm_W4.0mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*4.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10mm width 4.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.0mm_W5.0mm_P5.00mm_P7.50mm -C, Rect series, Radial, pin pitch=5.00mm 7.50mm, , length*width=10*5mm^2, Capacitor -C Rect series Radial pin pitch 5.00mm 7.50mm length 10mm width 5mm Capacitor -0 -4 -2 -Capacitor_THT -C_Rect_L10.3mm_W4.5mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*4.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10.3mm width 4.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.3mm_W5.0mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10.3mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.3mm_W5.7mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*5.7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10.3mm width 5.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L10.3mm_W7.2mm_P7.50mm_MKS4 -C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*7.2mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 7.50mm length 10.3mm width 7.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W2.8mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*2.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 2.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W3.4mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*3.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 3.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W3.5mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*3.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 3.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W4.2mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*4.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 4.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W4.3mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*4.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 4.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W5.1mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 5.1mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W5.3mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*5.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 5.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W6.3mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*6.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 6.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W6.4mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 6.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W7.3mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 7.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.0mm_W8.8mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*8.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.0mm width 8.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W2.0mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W2.6mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 2.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W2.8mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 2.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W3.2mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 3.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W3.5mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 3.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W3.6mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 3.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W4.0mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 4.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W4.3mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 4.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W4.5mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 4.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W5.0mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W5.1mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 5.1mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W5.2mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 5.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W5.6mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 5.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W6.4mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 6.4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W6.6mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 6.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W6.9mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 6.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W7.3mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 7.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W7.5mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 7.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W7.8mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 7.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W8.0mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*8.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 8.0mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W8.8mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*8.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 8.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W9.5mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*9.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 9.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L11.5mm_W9.8mm_P10.00mm_MKT -C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*9.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 10.00mm length 11.5mm width 9.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.0mm_W3.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*3mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13mm width 3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.0mm_W4.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13mm width 4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.0mm_W5.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.0mm_W6.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13mm width 6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.0mm_W6.5mm_P7.50mm_P10.00mm -C, Rect series, Radial, pin pitch=7.50mm 10.00mm, , length*width=13*6.5mm^2, Capacitor -C Rect series Radial pin pitch 7.50mm 10.00mm length 13mm width 6.5mm Capacitor -0 -4 -2 -Capacitor_THT -C_Rect_L13.0mm_W8.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13mm width 8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.5mm_W4.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13.5*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13.5mm width 4mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L13.5mm_W5.0mm_P10.00mm_FKS3_FKP3_MKS4 -C, Rect series, Radial, pin pitch=10.00mm, , length*width=13.5*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 10.00mm length 13.5mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W4.7mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*4.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 4.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W4.9mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*4.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 4.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W5.0mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W6.0mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W7.0mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W7.3mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 7.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W8.7mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*8.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 8.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W8.9mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*8.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 8.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W9.0mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W9.2mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*9.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 9.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W10.7mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*10.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 10.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W10.9mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*10.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 10.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W11.2mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*11.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 11.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W11.8mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*11.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 11.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W13.5mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 13.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W13.7mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 13.7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L16.5mm_W13.9mm_P15.00mm_MKT -C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 15.00mm length 16.5mm width 13.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L18.0mm_W5.0mm_P15.00mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 15.00mm length 18mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L18.0mm_W6.0mm_P15.00mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 15.00mm length 18mm width 6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 15.00mm length 18mm width 7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L18.0mm_W8.0mm_P15.00mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 15.00mm length 18mm width 8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L18.0mm_W9.0mm_P15.00mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 15.00mm length 18mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L18.0mm_W11.0mm_P15.00mm_FKS3_FKP3 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf -C Rect series Radial pin pitch 15.00mm length 18mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L19.0mm_W5.0mm_P15.00mm_MKS4 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 15.00mm length 19mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L19.0mm_W6.0mm_P15.00mm_MKS4 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 15.00mm length 19mm width 6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L19.0mm_W7.0mm_P15.00mm_MKS4 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 15.00mm length 19mm width 7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L19.0mm_W8.0mm_P15.00mm_MKS4 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 15.00mm length 19mm width 8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L19.0mm_W9.0mm_P15.00mm_MKS4 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 15.00mm length 19mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L19.0mm_W11.0mm_P15.00mm_MKS4 -C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 15.00mm length 19mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W7.0mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W8.3mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*8.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 8.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W8.6mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*8.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 8.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W10.1mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 10.1mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W10.3mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 10.3mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W10.9mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 10.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W12.2mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 12.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W12.6mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 12.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L24.0mm_W12.8mm_P22.50mm_MKT -C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 22.50mm length 24mm width 12.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L26.5mm_W5.0mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 26.5mm width 5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L26.5mm_W6.0mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 26.5mm width 6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L26.5mm_W7.0mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 26.5mm width 7mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L26.5mm_W8.5mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*8.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 26.5mm width 8.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L26.5mm_W10.5mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*10.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 26.5mm width 10.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L26.5mm_W11.5mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*11.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 26.5mm width 11.5mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L27.0mm_W9.0mm_P22.00mm -C, Rect series, Radial, pin pitch=22.00mm, , length*width=27*9mm^2, Capacitor -C Rect series Radial pin pitch 22.00mm length 27mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L27.0mm_W9.0mm_P23.00mm -C, Rect series, Radial, pin pitch=23.00mm, , length*width=27*9mm^2, Capacitor -C Rect series Radial pin pitch 23.00mm length 27mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L27.0mm_W11.0mm_P22.00mm -C, Rect series, Radial, pin pitch=22.00mm, , length*width=27*11mm^2, Capacitor -C Rect series Radial pin pitch 22.00mm length 27mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L28.0mm_W8.0mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 28mm width 8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L28.0mm_W10.0mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*10mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 28mm width 10mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L28.0mm_W12.0mm_P22.50mm_MKS4 -C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*12mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 22.50mm length 28mm width 12mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W7.6mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 7.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W7.8mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 7.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W7.9mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 7.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W9.1mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*9.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 9.1mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W9.6mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*9.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 9.6mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W11.0mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*11mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W11.9mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*11.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 11.9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W12.2mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*12.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 12.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W13.0mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*13mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 13mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W13.8mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*13.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 13.8mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W14.2mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*14.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 14.2mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L29.0mm_W16.0mm_P27.50mm_MKT -C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*16mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf -C Rect series Radial pin pitch 27.50mm length 29mm width 16mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L31.5mm_W9.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 31.5mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L31.5mm_W11.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 31.5mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L31.5mm_W13.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 31.5mm width 13mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 31.5mm width 15mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L31.5mm_W17.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*17mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 31.5mm width 17mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L31.5mm_W20.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 31.5mm width 20mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L32.0mm_W15.0mm_P27.00mm -C, Rect series, Radial, pin pitch=27.00mm, , length*width=32*15mm^2, Capacitor -C Rect series Radial pin pitch 27.00mm length 32mm width 15mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L33.0mm_W13.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 33mm width 13mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L33.0mm_W15.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 33mm width 15mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L33.0mm_W20.0mm_P27.50mm_MKS4 -C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 27.50mm length 33mm width 20mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W9.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 9mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W11.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 11mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W13.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 13mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W15.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 15mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W17.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*17mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 17mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W19.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*19mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 19mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W20.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 20mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W24.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*24mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 24mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W31.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*31mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 31mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W35.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*35mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 35mm Capacitor -0 -2 -2 -Capacitor_THT -C_Rect_L41.5mm_W40.0mm_P37.50mm_MKS4 -C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*40mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf -C Rect series Radial pin pitch 37.50mm length 41.5mm width 40mm Capacitor -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-1608-08_AVX-J -Tantalum Capacitor SMD AVX-J (1608-08 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-1608-08_AVX-J_Pad1.25x1.05mm_HandSolder -Tantalum Capacitor SMD AVX-J (1608-08 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-1608-10_AVX-L -Tantalum Capacitor SMD AVX-L (1608-10 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-1608-10_AVX-L_Pad1.25x1.05mm_HandSolder -Tantalum Capacitor SMD AVX-L (1608-10 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-2012-12_Kemet-R -Tantalum Capacitor SMD Kemet-R (2012-12 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-2012-12_Kemet-R_Pad1.30x1.05mm_HandSolder -Tantalum Capacitor SMD Kemet-R (2012-12 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-2012-15_AVX-P -Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-2012-15_AVX-P_Pad1.30x1.05mm_HandSolder -Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3216-10_Kemet-I -Tantalum Capacitor SMD Kemet-I (3216-10 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3216-10_Kemet-I_Pad1.58x1.35mm_HandSolder -Tantalum Capacitor SMD Kemet-I (3216-10 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3216-12_Kemet-S -Tantalum Capacitor SMD Kemet-S (3216-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3216-12_Kemet-S_Pad1.58x1.35mm_HandSolder -Tantalum Capacitor SMD Kemet-S (3216-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3216-18_Kemet-A -Tantalum Capacitor SMD Kemet-A (3216-18 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder -Tantalum Capacitor SMD Kemet-A (3216-18 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3528-12_Kemet-T -Tantalum Capacitor SMD Kemet-T (3528-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3528-12_Kemet-T_Pad1.50x2.35mm_HandSolder -Tantalum Capacitor SMD Kemet-T (3528-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3528-15_AVX-H -Tantalum Capacitor SMD AVX-H (3528-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3528-15_AVX-H_Pad1.50x2.35mm_HandSolder -Tantalum Capacitor SMD AVX-H (3528-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3528-21_Kemet-B -Tantalum Capacitor SMD Kemet-B (3528-21 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-3528-21_Kemet-B_Pad1.50x2.35mm_HandSolder -Tantalum Capacitor SMD Kemet-B (3528-21 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-6032-15_Kemet-U -Tantalum Capacitor SMD Kemet-U (6032-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-6032-15_Kemet-U_Pad2.25x2.35mm_HandSolder -Tantalum Capacitor SMD Kemet-U (6032-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-6032-20_AVX-F -Tantalum Capacitor SMD AVX-F (6032-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-6032-20_AVX-F_Pad2.25x2.35mm_HandSolder -Tantalum Capacitor SMD AVX-F (6032-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-6032-28_Kemet-C -Tantalum Capacitor SMD Kemet-C (6032-28 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-6032-28_Kemet-C_Pad2.25x2.35mm_HandSolder -Tantalum Capacitor SMD Kemet-C (6032-28 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7132-20_AVX-U -Tantalum Capacitor SMD AVX-U (7132-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7132-20_AVX-U_Pad2.72x3.50mm_HandSolder -Tantalum Capacitor SMD AVX-U (7132-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7132-28_AVX-C -Tantalum Capacitor SMD AVX-C (7132-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7132-28_AVX-C_Pad2.72x3.50mm_HandSolder -Tantalum Capacitor SMD AVX-C (7132-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-15_AVX-R -Tantalum Capacitor SMD AVX-R (7260-15 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-15_AVX-R_Pad2.68x6.30mm_HandSolder -Tantalum Capacitor SMD AVX-R (7260-15 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-20_AVX-M -Tantalum Capacitor SMD AVX-M (7260-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-20_AVX-M_Pad2.68x6.30mm_HandSolder -Tantalum Capacitor SMD AVX-M (7260-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-28_AVX-M -Tantalum Capacitor SMD AVX-M (7260-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-28_AVX-M_Pad2.68x6.30mm_HandSolder -Tantalum Capacitor SMD AVX-M (7260-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-38_AVX-R -Tantalum Capacitor SMD AVX-R (7260-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7260-38_AVX-R_Pad2.68x6.30mm_HandSolder -Tantalum Capacitor SMD AVX-R (7260-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-15_Kemet-W -Tantalum Capacitor SMD Kemet-W (7343-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-15_Kemet-W_Pad2.25x2.55mm_HandSolder -Tantalum Capacitor SMD Kemet-W (7343-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-20_Kemet-V -Tantalum Capacitor SMD Kemet-V (7343-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-20_Kemet-V_Pad2.25x2.55mm_HandSolder -Tantalum Capacitor SMD Kemet-V (7343-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-30_AVX-N -Tantalum Capacitor SMD AVX-N (7343-30 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-30_AVX-N_Pad2.25x2.55mm_HandSolder -Tantalum Capacitor SMD AVX-N (7343-30 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-31_Kemet-D -Tantalum Capacitor SMD Kemet-D (7343-31 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-31_Kemet-D_Pad2.25x2.55mm_HandSolder -Tantalum Capacitor SMD Kemet-D (7343-31 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-40_Kemet-Y -Tantalum Capacitor SMD Kemet-Y (7343-40 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-40_Kemet-Y_Pad2.25x2.55mm_HandSolder -Tantalum Capacitor SMD Kemet-Y (7343-40 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-43_Kemet-X -Tantalum Capacitor SMD Kemet-X (7343-43 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7343-43_Kemet-X_Pad2.25x2.55mm_HandSolder -Tantalum Capacitor SMD Kemet-X (7343-43 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7360-38_Kemet-E -Tantalum Capacitor SMD Kemet-E (7360-38 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7360-38_Kemet-E_Pad2.25x4.25mm_HandSolder -Tantalum Capacitor SMD Kemet-E (7360-38 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7361-38_AVX-V -Tantalum Capacitor SMD AVX-V (7361-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7361-38_AVX-V_Pad2.18x3.30mm_HandSolder -Tantalum Capacitor SMD AVX-V (7361-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7361-438_AVX-U -Tantalum Capacitor SMD AVX-U (7361-438 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Capacitor_Tantalum_SMD -CP_EIA-7361-438_AVX-U_Pad2.18x3.30mm_HandSolder -Tantalum Capacitor SMD AVX-U (7361-438 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator -capacitor tantalum -0 -2 -2 -Connector -Banana_Jack_1Pin -Single banana socket, footprint - 6mm drill -banana socket -0 -1 -1 -Connector -Banana_Jack_2Pin -Dual banana socket, footprint - 2 x 6mm drills -banana socket -0 -2 -2 -Connector -Banana_Jack_3Pin -Triple banana socket, footprint - 3 x 6mm drills -banana socket -0 -3 -3 -Connector -CUI_PD-30 -3 pin connector, PD-30, http://www.cui.com/product/resource/pd-30.pdf -connector 3-pin PD-30 power DIN -0 -4 -4 -Connector -CalTest_CT3151 -Right-angle standard banana jack, http://www.caltestelectronics.com/images/attachments/P315100rH_drawing.pdf -banana jack horizontal -0 -4 -1 -Connector -Connector_SFP_and_Cage -https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2227302&DocType=Customer+Drawing&DocLang=English -SFP+ SFP -0 -40 -21 -Connector -DTF13-12Px -http://www.te.com/usa-en/product-DTF13-12PA-G003.html -DEUTSCH DT header 12 pin -0 -12 -12 -Connector -FanPinHeader_1x03_P2.54mm_Vertical -3-pin CPU fan Through hole pin header, see http://www.formfactors.org/developer%5Cspecs%5Crev1_2_public.pdf -pin header 3-pin CPU fan -0 -3 -3 -Connector -FanPinHeader_1x04_P2.54mm_Vertical -4-pin CPU fan Through hole pin header, e.g. for Wieson part number 2366C888-007 Molex 47053-1000, Foxconn HF27040-M1, Tyco 1470947-1 or equivalent, see http://www.formfactors.org/developer%5Cspecs%5Crev1_2_public.pdf -pin header 4-pin CPU fan -0 -4 -4 -Connector -GB042-34S-H10 -http://www.lsmtron.com/pdf/Connector&Antenna_catalog.PDF -34pin SMD connector -0 -34 -34 -Connector -IHI_B6A-PCB-45_Vertical -https://lugsdirect.com/PDF_Webprint/B6A-PCB-45-XX(-X).pdf -connector IHI B6A-PCB-45 -0 -49 -1 -Connector -JWT_A3963_1x02_P3.96mm_Vertical -JWT A3963, 3.96mm pitch Pin head connector (http://www.jwt.com.tw/pro_pdf/A3963.pdf) -connector JWT A3963 pinhead -0 -2 -2 -Connector -NS-Tech_Grove_1x04_P2mm_Vertical -https://statics3.seeedstudio.com/images/opl/datasheet/3470130P1.pdf -Grove-1x04 -0 -4 -4 -Connector -Tag-Connect_TC2030-IDC-FP_2x03_P1.27mm_Vertical -Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC.pdf -tag connect programming header pogo pins -0 -6 -6 -Connector -Tag-Connect_TC2030-IDC-NL_2x03_P1.27mm_Vertical -Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC-NL.pdf -tag connect programming header pogo pins -0 -6 -6 -Connector -Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical -Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-430%20Datasheet.pdf -tag connect programming header pogo pins -0 -10 -10 -Connector -Tag-Connect_TC2050-IDC-NL_2x05_P1.27mm_Vertical -Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-NL%20Datasheet.pdf -tag connect programming header pogo pins -0 -10 -10 -Connector -Tag-Connect_TC2070-IDC-FP_2x07_P1.27mm_Vertical -Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2070-IDC%20Datasheet.pdf -tag connect programming header pogo pins -0 -14 -14 -Connector_AMASS -AMASS_MR30PW-FB_1x03_P3.50mm_Horizontal -Connector XT30 Horizontal PCB Female, https://www.tme.eu/en/Document/5e47640ba39fa492dbd4c0f4c8ae7b93/MR30PW%20SPEC.pdf -RC Connector XT30 -0 -5 -3 -Connector_AMASS -AMASS_MR30PW-M_1x03_P3.50mm_Horizontal -Connector XT30 Horizontal PCB Male, https://www.tme.eu/en/Document/5e47640ba39fa492dbd4c0f4c8ae7b93/MR30PW%20SPEC.pdf -RC Connector XT30 -0 -5 -3 -Connector_AMASS -AMASS_XT30PW-F_1x02_P2.50mm_Horizontal -Connector XT30 Horizontal PCB Female, https://www.tme.eu/en/Document/ce4077e36b79046da520ca73227e15de/XT30PW%20SPEC.pdf -RC Connector XT30 -0 -4 -2 -Connector_AMASS -AMASS_XT30PW-M_1x02_P2.50mm_Horizontal -Connector XT30 Horizontal PCB Male, https://www.tme.eu/en/Document/ce4077e36b79046da520ca73227e15de/XT30PW%20SPEC.pdf -RC Connector XT30 -0 -4 -2 -Connector_AMASS -AMASS_XT30U-F_1x02_P5.0mm_Vertical -Connector XT30 Vertical Cable Female, https://www.tme.eu/en/Document/3cbfa5cfa544d79584972dd5234a409e/XT30U%20SPEC.pdf -RC Connector XT30 -0 -2 -2 -Connector_AMASS -AMASS_XT30U-M_1x02_P5.0mm_Vertical -Connector XT30 Vertical Cable Male, https://www.tme.eu/en/Document/3cbfa5cfa544d79584972dd5234a409e/XT30U%20SPEC.pdf -RC Connector XT30 -0 -2 -2 -Connector_AMASS -AMASS_XT30UPB-F_1x02_P5.0mm_Vertical -Connector XT30 Vertical PCB Female, https://www.tme.eu/en/Document/4acc913878197f8c2e30d4b8cdc47230/XT30UPB%20SPEC.pdf -RC Connector XT30 -0 -2 -2 -Connector_AMASS -AMASS_XT30UPB-M_1x02_P5.0mm_Vertical -Connector XT30 Vertical PCB Male, https://www.tme.eu/en/Document/4acc913878197f8c2e30d4b8cdc47230/XT30UPB%20SPEC.pdf -RC Connector XT30 -0 -2 -2 -Connector_AMASS -AMASS_XT60-F_1x02_P7.20mm_Vertical -AMASS female XT60, through hole, vertical, https://www.tme.eu/Document/2d152ced3b7a446066e6c419d84bb460/XT60%20SPEC.pdf -XT60 female vertical -0 -2 -2 -Connector_AMASS -AMASS_XT60-M_1x02_P7.20mm_Vertical -AMASS female XT60, through hole, vertical, https://www.tme.eu/Document/2d152ced3b7a446066e6c419d84bb460/XT60%20SPEC.pdf -XT60 female vertical -0 -2 -2 -Connector_Audio -Jack_3.5mm_CUI_SJ-3523-SMT_Horizontal -3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf) -3.5mm audio cui horizontal jack stereo -0 -3 -3 -Connector_Audio -Jack_3.5mm_CUI_SJ-3524-SMT_Horizontal -3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf) -3.5mm audio cui horizontal jack stereo -0 -4 -4 -Connector_Audio -Jack_3.5mm_CUI_SJ1-3533NG_Horizontal -TRS 3.5mm, horizontal, through-hole, https://www.cui.com/product/resource/sj1-353xng.pdf -TRS audio jack stereo horizontal -0 -3 -3 -Connector_Audio -Jack_3.5mm_CUI_SJ1-3533NG_Horizontal_CircularHoles -TRS 3.5mm, horizontal, through-hole, , circular holeshttps://www.cui.com/product/resource/sj1-353xng.pdf -TRS audio jack stereo horizontal circular -0 -3 -3 -Connector_Audio -Jack_3.5mm_CUI_SJ1-3535NG_Horizontal -TRS 3.5mm, horizontal, through-hole, with switch, https://www.cui.com/product/resource/sj1-353xng.pdf -TRS audio jack stereo horizontal -0 -5 -5 -Connector_Audio -Jack_3.5mm_CUI_SJ1-3535NG_Horizontal_CircularHoles -TRS 3.5mm, horizontal, through-hole, with switch, circular holes, https://www.cui.com/product/resource/sj1-353xng.pdf -TRS audio jack stereo horizontal circular -0 -5 -5 -Connector_Audio -Jack_3.5mm_Ledino_KB3SPRS_Horizontal -https://www.reichelt.de/index.html?ACTION=7&LA=3&OPEN=0&INDEX=0&FILENAME=C160%252FKB3SPRS.pdf -jack stereo TRS -0 -5 -5 -Connector_Audio -Jack_3.5mm_Neutrik_NMJ6HCD2_Horizontal -NMJ6HCD2, TRS 1/4in (http://www.neutrik.com/en/audio/plugs-and-jacks/m-series/nmj6hcd2) -NMJ6HCD2 TRS stereo jack connector -0 -6 -6 -Connector_Audio -Jack_3.5mm_PJ311_Horizontal -PJ311 6pin SMD 3.5mm stereo headphones jack. -headphones jack plug stereo 3.5mm PJ311 -0 -6 -6 -Connector_Audio -Jack_3.5mm_PJ320D_Horizontal -Headphones with microphone connector, 3.5mm, 4 pins (http://www.qingpu-electronics.com/en/products/WQP-PJ320D-72.html) -3.5mm jack mic microphone phones headphones 4pins audio plug -0 -4 -4 -Connector_Audio -Jack_3.5mm_PJ320E_Horizontal -Headphones with microphone connector, 3.5mm, 4 pins (http://www.qingpu-electronics.com/en/products/WQP-PJ320E-177.html) -3.5mm jack mic microphone phones headphones 4pins audio plug -0 -5 -4 -Connector_Audio -Jack_3.5mm_PJ31060-I_Horizontal -PJ31060-I 6pin SMD 3.5mm headphones jack (http://www.china-bsun.com/Product48/1577.html) -headphones jack plug stereo 3.5mm PJ31060-I PJ31060 -0 -6 -6 -Connector_Audio -Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles -TRS 3.5mm, vertical, Thonkiconn, PCB mount, (http://www.qingpu-electronics.com/en/products/WQP-PJ398SM-362.html) -WQP-PJ398SM WQP-PJ301M-12 TRS 3.5mm mono vertical jack thonkiconn qingpu -0 -3 -3 -Connector_Audio -Jack_3.5mm_Switronic_ST-005-G_horizontal -3.5mm horizontal headphones jack, http://akizukidenshi.com/download/ds/switronic/ST-005-G.pdf -Connector Audio Switronic ST-005-G -0 -4 -3 -Connector_Audio -MiniXLR-5_Switchcraft_TRAPC_Horizontal -http://www.switchcraft.com/ProductSummary.aspx?Parent=620 http://www.switchcraft.com/Drawings/TRAPC_X-TRASM_X_SERIES_CD.PDF -THT Mini XLR 5Pin right angle -0 -5 -5 -Connector_BarrelJack -BarrelJack_CUI_PJ-036AH-SMT_Horizontal -Surface-mount DC Barrel Jack, http://www.cui.com/product/resource/pj-036ah-smt.pdf -Power Jack SMT -0 -3 -3 -Connector_BarrelJack -BarrelJack_CUI_PJ-063AH_Horizontal -Barrel Jack, 2.0mm ID, 5.5mm OD, 24V, 8A, no switch, https://www.cui.com/product/resource/pj-063ah.pdf -barrel jack cui dc power -0 -4 -3 -Connector_BarrelJack -BarrelJack_CUI_PJ-063AH_Horizontal_CircularHoles -Barrel Jack, 2.0mm ID, 5.5mm OD, 24V, 8A, no switch, https://www.cui.com/product/resource/pj-063ah.pdf -barrel jack cui dc power -0 -4 -3 -Connector_BarrelJack -BarrelJack_CUI_PJ-102AH_Horizontal -Thin-pin DC Barrel Jack, https://cdn-shop.adafruit.com/datasheets/21mmdcjackDatasheet.pdf -Power Jack -0 -3 -3 -Connector_BarrelJack -BarrelJack_Horizontal -DC Barrel Jack -Power Jack -0 -3 -3 -Connector_BarrelJack -BarrelJack_Wuerth_6941xx301002 -Wuerth electronics barrel jack connector (5.5mm outher diameter, inner diameter 2.05mm or 2.55mm depending on exact order number), See: http://katalog.we-online.de/em/datasheet/6941xx301002.pdf -connector barrel jack -0 -3 -3 -Connector_Card -CF-Card_3M_N7E50-7516PK-20-WF -Compact Flash Card connector (https://multimedia.3m.com/mws/media/22365O/3mtm-cf-card-header-compactflashtm-type-i-sm-ts0662.pdf) -connector cf -0 -54 -50 -Connector_Card -SD_Kyocera_145638009211859+ -SD Card Connector, Normal Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) -sd card smt -0 -13 -12 -Connector_Card -SD_Kyocera_145638009511859+ -SD Card Connector, Normal Type, Outer Tail, Spring Eject Type (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) -sd card smt -0 -13 -12 -Connector_Card -SD_Kyocera_145638109211859+ -SD Card Connector, Reverse Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) -sd card smt -0 -13 -12 -Connector_Card -SD_Kyocera_145638109511859+ -SD Card Connector, Reverse Type, Outer Tail, Spring Eject Type (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) -sd card smt -0 -13 -12 -Connector_Card -SD_TE_2041021 -SD card connector, top mount, SMT (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F2041021%7FB%7Fpdf%7FEnglish%7FENG_CD_2041021_B_C_2041021_B.pdf%7F2041021-4) -sd card -0 -15 -12 -Connector_Card -microSD_HC_Hirose_DM3AT-SF-PEJM5 -Micro SD, SMD, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3AT-SF-PEJM5/category/Drawing%20(2D)/doc_file_id/44099/?file_category_id=6&item_id=06090031000&is_series=) -Micro SD -0 -14 -11 -Connector_Card -microSD_HC_Hirose_DM3BT-DSF-PEJS -Micro SD, SMD, reverse on-board, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3BT-DSF-PEJS/category/Drawing%20(2D)/doc_file_id/44097/?file_category_id=6&item_id=06090029900&is_series=) -Micro SD -0 -16 -11 -Connector_Card -microSD_HC_Hirose_DM3D-SF -Micro SD, SMD, right-angle, push-pull (https://media.digikey.com/PDF/Data%20Sheets/Hirose%20PDFs/DM3D-SF.pdf) -Micro SD -0 -14 -11 -Connector_Card -microSD_HC_Molex_104031-0811 -1.10mm Pitch microSD Memory Card Connector, Surface Mount, Push-Pull Type, 1.42mm Height, with Detect Switch (https://www.molex.com/pdm_docs/sd/1040310811_sd.pdf) -microSD SD molex -0 -14 -11 -Connector_Card -microSD_HC_Wuerth_693072010801 -http://katalog.we-online.de/em/datasheet/693072010801.pdf -Micro SD Wuerth Wurth Würth -0 -12 -9 -Connector_Card -microSIM_JAE_SF53S006VCBR2000 -https://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ115712.pdf -microSIM GSM Card -0 -14 -7 -Connector_Coaxial -BNC_Amphenol_031-6575_Horizontal -dual independently isolated BNC plug (https://www.amphenolrf.com/downloads/dl/file/id/2980/product/644/031_6575_customer_drawing.pdf) -Dual BNC Amphenol Horizontal -0 -6 -4 -Connector_Coaxial -BNC_Amphenol_B6252HB-NPP3G-50_Horizontal -http://www.farnell.com/datasheets/612848.pdf -BNC Amphenol Horizontal -0 -4 -2 -Connector_Coaxial -BNC_PanelMountable_Vertical -Panel-mountable BNC connector mounted through PCB, vertical -BNC connector -0 -2 -2 -Connector_Coaxial -BNC_TEConnectivity_1478204_Vertical -BNC female PCB mount 4 pin straight chassis connector http://www.te.com/usa-en/product-1-1478204-0.html -BNC female PCB mount 4 pin straight chassis connector -0 -5 -2 -Connector_Coaxial -BNC_Win_364A2x95_Horizontal -Dual front isolated BNC plug (https://www.winconn.com/wp-content/uploads/364A2595.pdf) -Dual BNC Horizontal Isolated -0 -6 -3 -Connector_Coaxial -MMCX_Molex_73415-0961_Horizontal_0.8mm-PCB -Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf -Molex MMCX Horizontal Coaxial -0 -3 -2 -Connector_Coaxial -MMCX_Molex_73415-0961_Horizontal_1.0mm-PCB -Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf -Molex MMCX Horizontal Coaxial -0 -3 -2 -Connector_Coaxial -MMCX_Molex_73415-0961_Horizontal_1.6mm-PCB -Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf -Molex MMCX Horizontal Coaxial -0 -3 -2 -Connector_Coaxial -MMCX_Molex_73415-1471_Vertical -http://www.molex.com/pdm_docs/sd/734151471_sd.pdf -Molex MMCX Coaxial Connector 50 ohms Female Jack Vertical THT -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_901-144_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/7023/product/3103/901_144_customer_drawing.pdf -SMA THT Female Jack Vertical -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132134-10_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/4007/product/2974/132134_10_customer_drawing.pdf -SMA SMD Female Jack Vertical -0 -3 -2 -Connector_Coaxial -SMA_Amphenol_132134-11_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/3406/product/2975/132134_11_customer_drawing.pdf -SMA THT Female Jack Vertical ExtendedLegs -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132134-14_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/1793/product/2976/132134_14_customer_drawing.pdf -SMA THT Female Jack Vertical ExtendedLegs -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132134-16_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/1141/product/2978/132134_16_customer_drawing.pdf -SMA THT Female Jack Vertical ExtendedLegs -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132134_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/2187/product/2843/132134_customer_drawing.pdf -SMA THT Female Jack Vertical ExtendedLegs -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132203-12_Horizontal -https://www.amphenolrf.com/media/downloads/1769/132203-12.pdf -SMA THT Female Jack Horizontal -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132289_EdgeMount -http://www.amphenolrf.com/132289.html -SMA -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132291-12_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/1688/product/3020/132291_12_customer_drawing.pdf -SMA THT Female Jack Vertical Bulkhead -0 -5 -2 -Connector_Coaxial -SMA_Amphenol_132291_Vertical -https://www.amphenolrf.com/downloads/dl/file/id/3222/product/2918/132291_customer_drawing.pdf -SMA THT Female Jack Vertical Bulkhead -0 -5 -2 -Connector_Coaxial -SMA_Molex_73251-1153_EdgeMount_Horizontal -Molex SMA RF Connectors, Edge Mount, (http://www.molex.com/pdm_docs/sd/732511150_sd.pdf) -sma edge -0 -11 -2 -Connector_Coaxial -SMA_Molex_73251-2200_Horizontal -https://www.molex.com/webdocs/datasheets/pdf/en-us/0732512200_RF_COAX_CONNECTORS.pdf -SMA THT Female Jack Horizontal -0 -5 -2 -Connector_Coaxial -SMA_Samtec_SMA-J-P-X-ST-EM1_EdgeMount -Connector SMA, 0Hz to 20GHz, 50Ohm, Edge Mount (http://suddendocs.samtec.com/prints/sma-j-p-x-st-em1-mkt.pdf) -SMA Straight Samtec Edge Mount -0 -5 -2 -Connector_Coaxial -SMB_Jack_Vertical -SMB pcb mounting jack -SMB Jack Striaght -0 -5 -2 -Connector_Coaxial -U.FL_Hirose_U.FL-R-SMT-1_Vertical -Hirose U.FL Coaxial https://www.hirose.com/product/en/products/U.FL/U.FL-R-SMT-1%2810%29/ -Hirose U.FL Coaxial -0 -3 -2 -Connector_Coaxial -U.FL_Molex_MCRF_73412-0110_Vertical -Molex Microcoaxial RF Connectors (MCRF), mates Hirose U.FL, (http://www.molex.com/pdm_docs/sd/734120110_sd.pdf) -mcrf hirose ufl u.fl microcoaxial -0 -4 -2 -Connector_DIN -DIN41612_B2_2x8_Horizontal -DIN 41612 connector, type B/2, horizontal, 16 pins wide, 2 rows, even columns -DIN 41512 IEC 60603 B/2 -0 -16 -16 -Connector_DIN -DIN41612_B2_2x8_Vertical -DIN 41612 connector, type B/2, vertical, 16 pins wide, 2 rows, even columns -DIN 41512 IEC 60603 B/2 -0 -16 -16 -Connector_DIN -DIN41612_B2_2x16_Horizontal -DIN 41612 connector, type B/2, horizontal, 16 pins wide, 2 rows, full configuration -DIN 41512 IEC 60603 B/2 -0 -32 -32 -Connector_DIN -DIN41612_B2_2x16_Vertical -DIN 41612 connector, type B/2, vertical, 16 pins wide, 2 rows, full configuration -DIN 41512 IEC 60603 B/2 -0 -32 -32 -Connector_DIN -DIN41612_B3_2x5_Horizontal -DIN 41612 connector, type B/3, horizontal, 10 pins wide, 2 rows, even columns -DIN 41512 IEC 60603 B/3 -0 -10 -10 -Connector_DIN -DIN41612_B3_2x5_Vertical -DIN 41612 connector, type B/3, vertical, 10 pins wide, 2 rows, even columns -DIN 41512 IEC 60603 B/3 -0 -10 -10 -Connector_DIN -DIN41612_B3_2x10_Horizontal -DIN 41612 connector, type B/3, horizontal, 10 pins wide, 2 rows, full configuration -DIN 41512 IEC 60603 B/3 -0 -20 -20 -Connector_DIN -DIN41612_B3_2x10_Vertical -DIN 41612 connector, type B/3, vertical, 10 pins wide, 2 rows, full configuration -DIN 41512 IEC 60603 B/3 -0 -20 -20 -Connector_DIN -DIN41612_B_2x16_Horizontal -DIN 41612 connector, type B, horizontal, 32 pins wide, 2 rows, even columns -DIN 41512 IEC 60603 B -0 -32 -32 -Connector_DIN -DIN41612_B_2x16_Vertical -DIN 41612 connector, type B, vertical, 32 pins wide, 2 rows, even columns -DIN 41512 IEC 60603 B -0 -32 -32 -Connector_DIN -DIN41612_B_2x32_Horizontal -DIN 41612 connector, type B, horizontal, 32 pins wide, 2 rows, full configuration -DIN 41512 IEC 60603 B -0 -64 -64 -Connector_DIN -DIN41612_B_2x32_Vertical -DIN 41612 connector, type B, vertical, 32 pins wide, 2 rows, full configuration -DIN 41512 IEC 60603 B -0 -64 -64 -Connector_Dsub -DSUB-9_Female_EdgeMount_P2.77mm -9-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 25mm -0 -9 -9 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -9 -9 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -9 -9 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Female_Vertical_P2.77x2.84mm -9-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 25mm -0 -9 -9 -Connector_Dsub -DSUB-9_Female_Vertical_P2.77x2.84mm_MountingHoles -9-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Male_EdgeMount_P2.77mm -9-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 25mm -0 -9 -9 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -9 -9 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -9 -9 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -11 -10 -Connector_Dsub -DSUB-9_Male_Vertical_P2.77x2.84mm -9-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 25mm -0 -9 -9 -Connector_Dsub -DSUB-9_Male_Vertical_P2.77x2.84mm_MountingHoles -9-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -9-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 25mm -0 -11 -10 -Connector_Dsub -DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -17 -16 -Connector_Dsub -DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -17 -16 -Connector_Dsub -DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15-HD_Female_Vertical_P2.29x1.98mm_MountingHoles -15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 25mm -0 -17 -16 -Connector_Dsub -DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -17 -16 -Connector_Dsub -DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 25mm mounting-hole-offset 25mm -0 -17 -16 -Connector_Dsub -DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15-HD_Male_Vertical_P2.29x1.98mm_MountingHoles -15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 25mm -0 -17 -16 -Connector_Dsub -DSUB-15_Female_EdgeMount_P2.77mm -15-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 33.3mm -0 -15 -15 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Female_Vertical_P2.77x2.84mm -15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 33.3mm -0 -15 -15 -Connector_Dsub -DSUB-15_Female_Vertical_P2.77x2.84mm_MountingHoles -15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Male_EdgeMount_P2.77mm -15-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 33.3mm -0 -15 -15 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -15 -15 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-15_Male_Vertical_P2.77x2.84mm -15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 33.3mm -0 -15 -15 -Connector_Dsub -DSUB-15_Male_Vertical_P2.77x2.84mm_MountingHoles -15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -15-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 33.3mm -0 -17 -16 -Connector_Dsub -DSUB-25_Female_EdgeMount_P2.77mm -25-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 47.1mm -0 -25 -25 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -25 -25 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -25 -25 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Female_Vertical_P2.77x2.84mm -25-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 47.1mm -0 -25 -25 -Connector_Dsub -DSUB-25_Female_Vertical_P2.77x2.84mm_MountingHoles -25-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Male_EdgeMount_P2.77mm -25-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 47.1mm -0 -25 -25 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -25 -25 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -25 -25 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-25_Male_Vertical_P2.77x2.84mm -25-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 47.1mm -0 -25 -25 -Connector_Dsub -DSUB-25_Male_Vertical_P2.77x2.84mm_MountingHoles -25-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -25-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 47.1mm -0 -27 -26 -Connector_Dsub -DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -28 -27 -Connector_Dsub -DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -28 -27 -Connector_Dsub -DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm -0 -26 -26 -Connector_Dsub -DSUB-26-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm -0 -26 -26 -Connector_Dsub -DSUB-26-HD_Female_Vertical_P2.29x1.98mm_MountingHoles -26-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -26-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 33.3mm -0 -28 -27 -Connector_Dsub -DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -28 -27 -Connector_Dsub -DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm -0 -28 -27 -Connector_Dsub -DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm -0 -26 -26 -Connector_Dsub -DSUB-26-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm -26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm -0 -26 -26 -Connector_Dsub -DSUB-26-HD_Male_Vertical_P2.29x1.98mm_MountingHoles -26-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -26-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 33.3mm -0 -28 -27 -Connector_Dsub -DSUB-37_Female_EdgeMount_P2.77mm -37-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 63.5mm -0 -37 -37 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -37 -37 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -37 -37 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Female_Vertical_P2.77x2.84mm -37-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 63.5mm -0 -37 -37 -Connector_Dsub -DSUB-37_Female_Vertical_P2.77x2.84mm_MountingHoles -37-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Male_EdgeMount_P2.77mm -37-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 63.5mm -0 -37 -37 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm -0 -37 -37 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm -0 -37 -37 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm -37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-37_Male_Vertical_P2.77x2.84mm -37-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 63.5mm -0 -37 -37 -Connector_Dsub -DSUB-37_Male_Vertical_P2.77x2.84mm_MountingHoles -37-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -37-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 63.5mm -0 -39 -38 -Connector_Dsub -DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -46 -45 -Connector_Dsub -DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -46 -45 -Connector_Dsub -DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm -0 -44 -44 -Connector_Dsub -DSUB-44-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm -0 -44 -44 -Connector_Dsub -DSUB-44-HD_Female_Vertical_P2.29x1.98mm_MountingHoles -44-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -44-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 47.1mm -0 -46 -45 -Connector_Dsub -DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -46 -45 -Connector_Dsub -DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm -0 -46 -45 -Connector_Dsub -DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm -0 -44 -44 -Connector_Dsub -DSUB-44-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm -44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm -0 -44 -44 -Connector_Dsub -DSUB-44-HD_Male_Vertical_P2.29x1.98mm_MountingHoles -44-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -44-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 47.1mm -0 -46 -45 -Connector_Dsub -DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -64 -63 -Connector_Dsub -DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -64 -63 -Connector_Dsub -DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset9.40mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 9.4mm -0 -62 -62 -Connector_Dsub -DSUB-62-HD_Female_Horizontal_P2.41x2.54mm_EdgePinOffset9.40mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x2.54mm pin-PCB-offset 9.4mm -0 -62 -62 -Connector_Dsub -DSUB-62-HD_Female_Vertical_P2.41x1.98mm_MountingHoles -62-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.41x1.98mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -62-pin D-Sub connector straight vertical THT female pitch 2.41x1.98mm mounting holes distance 63.5mm -0 -64 -63 -Connector_Dsub -DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -64 -63 -Connector_Dsub -DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm -0 -64 -63 -Connector_Dsub -DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset9.40mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 9.4mm -0 -62 -62 -Connector_Dsub -DSUB-62-HD_Male_Horizontal_P2.41x2.54mm_EdgePinOffset9.40mm -62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf -62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x2.54mm pin-PCB-offset 9.4mm -0 -62 -62 -Connector_Dsub -DSUB-62-HD_Male_Vertical_P2.41x1.98mm_MountingHoles -62-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.41x1.98mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf -62-pin D-Sub connector straight vertical THT male pitch 2.41x1.98mm mounting holes distance 63.5mm -0 -64 -63 -Connector_FFC-FPC -Hirose_FH12-6S-0.5SH_1x06-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-6S-0.5SH, 6 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -8 -7 -Connector_FFC-FPC -Hirose_FH12-8S-0.5SH_1x08-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-8S-0.5SH, 8 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -10 -9 -Connector_FFC-FPC -Hirose_FH12-10S-0.5SH_1x10-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-10S-0.5SH, 10 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -12 -11 -Connector_FFC-FPC -Hirose_FH12-11S-0.5SH_1x11-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-11S-0.5SH, 11 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -13 -12 -Connector_FFC-FPC -Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-12S-0.5SH, 12 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -14 -13 -Connector_FFC-FPC -Hirose_FH12-13S-0.5SH_1x13-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-13S-0.5SH, 13 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -15 -14 -Connector_FFC-FPC -Hirose_FH12-14S-0.5SH_1x14-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-14S-0.5SH, 14 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -16 -15 -Connector_FFC-FPC -Hirose_FH12-15S-0.5SH_1x15-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-15S-0.5SH, 15 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -17 -16 -Connector_FFC-FPC -Hirose_FH12-16S-0.5SH_1x16-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-16S-0.5SH, 16 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -18 -17 -Connector_FFC-FPC -Hirose_FH12-17S-0.5SH_1x17-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-17S-0.5SH, 17 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -19 -18 -Connector_FFC-FPC -Hirose_FH12-18S-0.5SH_1x18-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-18S-0.5SH, 18 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -20 -19 -Connector_FFC-FPC -Hirose_FH12-19S-0.5SH_1x19-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-19S-0.5SH, 19 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -21 -20 -Connector_FFC-FPC -Hirose_FH12-20S-0.5SH_1x20-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-20S-0.5SH, 20 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -22 -21 -Connector_FFC-FPC -Hirose_FH12-22S-0.5SH_1x22-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-22S-0.5SH, 22 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -24 -23 -Connector_FFC-FPC -Hirose_FH12-24S-0.5SH_1x24-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-24S-0.5SH, 24 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -26 -25 -Connector_FFC-FPC -Hirose_FH12-25S-0.5SH_1x25-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-25S-0.5SH, 25 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -27 -26 -Connector_FFC-FPC -Hirose_FH12-26S-0.5SH_1x26-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-26S-0.5SH, 26 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -28 -27 -Connector_FFC-FPC -Hirose_FH12-28S-0.5SH_1x28-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-28S-0.5SH, 28 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -30 -29 -Connector_FFC-FPC -Hirose_FH12-30S-0.5SH_1x30-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-30S-0.5SH, 30 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -32 -31 -Connector_FFC-FPC -Hirose_FH12-32S-0.5SH_1x32-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-32S-0.5SH, 32 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -34 -33 -Connector_FFC-FPC -Hirose_FH12-33S-0.5SH_1x33-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-33S-0.5SH, 33 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -35 -34 -Connector_FFC-FPC -Hirose_FH12-34S-0.5SH_1x34-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-34S-0.5SH, 34 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -36 -35 -Connector_FFC-FPC -Hirose_FH12-35S-0.5SH_1x35-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-35S-0.5SH, 35 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -37 -36 -Connector_FFC-FPC -Hirose_FH12-36S-0.5SH_1x36-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-36S-0.5SH, 36 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -38 -37 -Connector_FFC-FPC -Hirose_FH12-40S-0.5SH_1x40-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-40S-0.5SH, 40 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -42 -41 -Connector_FFC-FPC -Hirose_FH12-45S-0.5SH_1x45-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-45S-0.5SH, 45 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -47 -46 -Connector_FFC-FPC -Hirose_FH12-50S-0.5SH_1x50-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-50S-0.5SH, 50 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -52 -51 -Connector_FFC-FPC -Hirose_FH12-53S-0.5SH_1x53-1MP_P0.50mm_Horizontal -Hirose FH12, FFC/FPC connector, FH12-53S-0.5SH, 53 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator -connector Hirose FH12 horizontal -0 -55 -54 -Connector_FFC-FPC -JAE_FF0825SA1_2Rows-25Pins_P0.40mm_Horizontal -Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0825SA1, 25 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -25 -25 -Connector_FFC-FPC -JAE_FF0829SA1_2Rows-29Pins_P0.40mm_Horizontal -Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0829SA1, 29 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -29 -29 -Connector_FFC-FPC -JAE_FF0841SA1_2Rows-41Pins_P0.40mm_Horizontal -Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0841SA1, 41 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -41 -41 -Connector_FFC-FPC -JAE_FF0851SA1_2Rows-51Pins_P0.40mm_Horizontal -Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0851SA1, 51 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -51 -51 -Connector_FFC-FPC -JAE_FF0871SA1_2Rows-71Pins_P0.40mm_Horizontal -Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0871SA1, 71 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -71 -71 -Connector_FFC-FPC -JAE_FF0881SA1_2Rows-81Pins_P0.40mm_Horizontal -Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0881SA1, 81 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -81 -81 -Connector_FFC-FPC -Molex_54132-5033_1x50-1MP_P0.5mm_Horizontal -Molex FFC/FPC connector, 50 bottom-side contacts, 0.5mm pitch, 2.0mm height, https://www.molex.com/pdm_docs/sd/541325033_sd.pdf -FFC FPC -0 -54 -51 -Connector_FFC-FPC -Molex_200528-0040_1x04-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0040, 4 Circuits (https://www.molex.com/pdm_docs/sd/2005280040_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -6 -5 -Connector_FFC-FPC -Molex_200528-0050_1x05-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0050, 5 Circuits (https://www.molex.com/pdm_docs/sd/2005280050_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -7 -6 -Connector_FFC-FPC -Molex_200528-0060_1x06-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0060, 6 Circuits (https://www.molex.com/pdm_docs/sd/2005280060_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -8 -7 -Connector_FFC-FPC -Molex_200528-0070_1x07-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0070, 7 Circuits (https://www.molex.com/pdm_docs/sd/2005280070_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -9 -8 -Connector_FFC-FPC -Molex_200528-0080_1x08-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0080, 8 Circuits (https://www.molex.com/pdm_docs/sd/2005280080_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -10 -9 -Connector_FFC-FPC -Molex_200528-0090_1x09-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0090, 9 Circuits (https://www.molex.com/pdm_docs/sd/2005280090_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -11 -10 -Connector_FFC-FPC -Molex_200528-0100_1x10-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0100, 10 Circuits (https://www.molex.com/pdm_docs/sd/2005280100_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -12 -11 -Connector_FFC-FPC -Molex_200528-0110_1x11-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0110, 11 Circuits (https://www.molex.com/pdm_docs/sd/2005280110_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -13 -12 -Connector_FFC-FPC -Molex_200528-0120_1x12-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0120, 12 Circuits (https://www.molex.com/pdm_docs/sd/2005280120_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -14 -13 -Connector_FFC-FPC -Molex_200528-0130_1x13-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0130, 13 Circuits (https://www.molex.com/pdm_docs/sd/2005280130_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -15 -14 -Connector_FFC-FPC -Molex_200528-0140_1x14-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0140, 14 Circuits (https://www.molex.com/pdm_docs/sd/2005280140_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -16 -15 -Connector_FFC-FPC -Molex_200528-0150_1x15-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0150, 15 Circuits (https://www.molex.com/pdm_docs/sd/2005280150_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -17 -16 -Connector_FFC-FPC -Molex_200528-0160_1x16-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0160, 16 Circuits (https://www.molex.com/pdm_docs/sd/2005280160_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -18 -17 -Connector_FFC-FPC -Molex_200528-0170_1x17-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0170, 17 Circuits (https://www.molex.com/pdm_docs/sd/2005280170_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -19 -18 -Connector_FFC-FPC -Molex_200528-0180_1x18-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0180, 18 Circuits (https://www.molex.com/pdm_docs/sd/2005280180_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -20 -19 -Connector_FFC-FPC -Molex_200528-0190_1x19-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0190, 19 Circuits (https://www.molex.com/pdm_docs/sd/2005280190_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -21 -20 -Connector_FFC-FPC -Molex_200528-0200_1x20-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0200, 20 Circuits (https://www.molex.com/pdm_docs/sd/2005280200_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -22 -21 -Connector_FFC-FPC -Molex_200528-0210_1x21-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0210, 21 Circuits (https://www.molex.com/pdm_docs/sd/2005280210_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -23 -22 -Connector_FFC-FPC -Molex_200528-0220_1x22-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0220, 22 Circuits (https://www.molex.com/pdm_docs/sd/2005280220_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -24 -23 -Connector_FFC-FPC -Molex_200528-0230_1x23-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0230, 23 Circuits (https://www.molex.com/pdm_docs/sd/2005280230_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -25 -24 -Connector_FFC-FPC -Molex_200528-0240_1x24-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0240, 24 Circuits (https://www.molex.com/pdm_docs/sd/2005280240_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -26 -25 -Connector_FFC-FPC -Molex_200528-0250_1x25-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0250, 25 Circuits (https://www.molex.com/pdm_docs/sd/2005280250_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -27 -26 -Connector_FFC-FPC -Molex_200528-0260_1x26-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0260, 26 Circuits (https://www.molex.com/pdm_docs/sd/2005280260_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -28 -27 -Connector_FFC-FPC -Molex_200528-0270_1x27-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0270, 27 Circuits (https://www.molex.com/pdm_docs/sd/2005280270_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -29 -28 -Connector_FFC-FPC -Molex_200528-0280_1x28-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0280, 28 Circuits (https://www.molex.com/pdm_docs/sd/2005280280_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -30 -29 -Connector_FFC-FPC -Molex_200528-0290_1x29-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0290, 29 Circuits (https://www.molex.com/pdm_docs/sd/2005280290_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -31 -30 -Connector_FFC-FPC -Molex_200528-0300_1x30-1MP_P1.00mm_Horizontal -Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0300, 30 Circuits (https://www.molex.com/pdm_docs/sd/2005280300_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -32 -31 -Connector_FFC-FPC -Molex_502231-1500_1x15-1SH_P0.5mm_Vertical -Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 15 Circuits (https://www.molex.com/pdm_docs/sd/5022311500_sd.pdf) -molex FFC/FPC connector Pitch 0.5mm vertical -0 -17 -16 -Connector_FFC-FPC -Molex_502231-2400_1x24-1SH_P0.5mm_Vertical -Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 24 Circuits (https://www.molex.com/pdm_docs/sd/5022312400_sd.pdf) -molex FFC/FPC connector Pitch 0.5mm vertical -0 -26 -25 -Connector_FFC-FPC -Molex_502231-3300_1x33-1SH_P0.5mm_Vertical -Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 33 Circuits (https://www.molex.com/pdm_docs/sd/5022313300_sd.pdf) -molex FFC/FPC connector Pitch 0.5mm vertical -0 -36 -34 -Connector_FFC-FPC -Molex_502244-1530_1x15-1MP_P0.5mm_Horizontal -Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 15 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf) -molex FFC/FPC connector Pitch 0.5mm right angle -0 -19 -16 -Connector_FFC-FPC -Molex_502244-2430_1x24-1MP_P0.5mm_Horizontal -Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 24 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf) -molex FFC/FPC connector Pitch 0.5mm right angle -0 -28 -25 -Connector_FFC-FPC -Molex_502244-3330_1x33-1MP_P0.5mm_Horizontal -Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 33 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf) -molex FFC/FPC connector Pitch 0.5mm right angle -0 -39 -34 -Connector_FFC-FPC -Molex_502250-1791_2Rows-17Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-1791, 17 Circuits (http://www.molex.com/pdm_docs/sd/5022501791_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -19 -18 -Connector_FFC-FPC -Molex_502250-2191_2Rows-21Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2191, 21 Circuits (http://www.molex.com/pdm_docs/sd/5022502191_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -23 -22 -Connector_FFC-FPC -Molex_502250-2391_2Rows-23Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2391, 23 Circuits (http://www.molex.com/pdm_docs/sd/5022502391_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -25 -24 -Connector_FFC-FPC -Molex_502250-2791_2Rows-27Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2791, 27 Circuits (http://www.molex.com/pdm_docs/sd/5022502791_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -29 -28 -Connector_FFC-FPC -Molex_502250-3391_2Rows-33Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3391, 33 Circuits (http://www.molex.com/pdm_docs/sd/5022503391_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -35 -34 -Connector_FFC-FPC -Molex_502250-3591_2Rows-35Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3591, 35 Circuits (http://www.molex.com/pdm_docs/sd/5022503591_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -37 -36 -Connector_FFC-FPC -Molex_502250-3991_2Rows-39Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3991, 39 Circuits (http://www.molex.com/pdm_docs/sd/5022503991_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -41 -40 -Connector_FFC-FPC -Molex_502250-4191_2Rows-41Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-4191, 41 Circuits (http://www.molex.com/pdm_docs/sd/5022504191_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -43 -42 -Connector_FFC-FPC -Molex_502250-5191_2Rows-51Pins-1MP_P0.60mm_Horizontal -Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-5191, 51 Circuits (http://www.molex.com/pdm_docs/sd/5022505191_sd.pdf), generated with kicad-footprint-generator -connector Molex top entry -0 -53 -52 -Connector_FFC-FPC -TE_0-1734839-5_1x05-1MP_P0.5mm_Horizontal -TE FPC connector, 05 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -7 -6 -Connector_FFC-FPC -TE_0-1734839-6_1x06-1MP_P0.5mm_Horizontal -TE FPC connector, 06 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -8 -7 -Connector_FFC-FPC -TE_0-1734839-7_1x07-1MP_P0.5mm_Horizontal -TE FPC connector, 07 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -9 -8 -Connector_FFC-FPC -TE_0-1734839-8_1x08-1MP_P0.5mm_Horizontal -TE FPC connector, 08 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -10 -9 -Connector_FFC-FPC -TE_0-1734839-9_1x09-1MP_P0.5mm_Horizontal -TE FPC connector, 09 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -11 -10 -Connector_FFC-FPC -TE_1-84952-0_1x10-1MP_P1.0mm_Horizontal -TE FPC connector, 10 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -12 -11 -Connector_FFC-FPC -TE_1-84952-1_1x11-1MP_P1.0mm_Horizontal -TE FPC connector, 11 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -13 -12 -Connector_FFC-FPC -TE_1-84952-2_1x12-1MP_P1.0mm_Horizontal -TE FPC connector, 12 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -14 -13 -Connector_FFC-FPC -TE_1-84952-3_1x13-1MP_P1.0mm_Horizontal -TE FPC connector, 13 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -15 -14 -Connector_FFC-FPC -TE_1-84952-4_1x14-1MP_P1.0mm_Horizontal -TE FPC connector, 14 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -16 -15 -Connector_FFC-FPC -TE_1-84952-5_1x15-1MP_P1.0mm_Horizontal -TE FPC connector, 15 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -17 -16 -Connector_FFC-FPC -TE_1-84952-6_1x16-1MP_P1.0mm_Horizontal -TE FPC connector, 16 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -18 -17 -Connector_FFC-FPC -TE_1-84952-7_1x17-1MP_P1.0mm_Horizontal -TE FPC connector, 17 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -19 -18 -Connector_FFC-FPC -TE_1-84952-8_1x18-1MP_P1.0mm_Horizontal -TE FPC connector, 18 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -20 -19 -Connector_FFC-FPC -TE_1-84952-9_1x19-1MP_P1.0mm_Horizontal -TE FPC connector, 19 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -21 -20 -Connector_FFC-FPC -TE_1-84953-0_1x10-1MP_P1.0mm_Horizontal -TE FPC connector, 10 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -12 -11 -Connector_FFC-FPC -TE_1-84953-1_1x11-1MP_P1.0mm_Horizontal -TE FPC connector, 11 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -13 -12 -Connector_FFC-FPC -TE_1-84953-2_1x12-1MP_P1.0mm_Horizontal -TE FPC connector, 12 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -14 -13 -Connector_FFC-FPC -TE_1-84953-3_1x13-1MP_P1.0mm_Horizontal -TE FPC connector, 13 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -15 -14 -Connector_FFC-FPC -TE_1-84953-4_1x14-1MP_P1.0mm_Horizontal -TE FPC connector, 14 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -16 -15 -Connector_FFC-FPC -TE_1-84953-5_1x15-1MP_P1.0mm_Horizontal -TE FPC connector, 15 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -17 -16 -Connector_FFC-FPC -TE_1-84953-6_1x16-1MP_P1.0mm_Horizontal -TE FPC connector, 16 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -18 -17 -Connector_FFC-FPC -TE_1-84953-7_1x17-1MP_P1.0mm_Horizontal -TE FPC connector, 17 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -19 -18 -Connector_FFC-FPC -TE_1-84953-8_1x18-1MP_P1.0mm_Horizontal -TE FPC connector, 18 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -20 -19 -Connector_FFC-FPC -TE_1-84953-9_1x19-1MP_P1.0mm_Horizontal -TE FPC connector, 19 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -21 -20 -Connector_FFC-FPC -TE_1-1734839-0_1x10-1MP_P0.5mm_Horizontal -TE FPC connector, 10 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -12 -11 -Connector_FFC-FPC -TE_1-1734839-1_1x11-1MP_P0.5mm_Horizontal -TE FPC connector, 11 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -13 -12 -Connector_FFC-FPC -TE_1-1734839-2_1x12-1MP_P0.5mm_Horizontal -TE FPC connector, 12 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -14 -13 -Connector_FFC-FPC -TE_1-1734839-3_1x13-1MP_P0.5mm_Horizontal -TE FPC connector, 13 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -15 -14 -Connector_FFC-FPC -TE_1-1734839-4_1x14-1MP_P0.5mm_Horizontal -TE FPC connector, 14 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -16 -15 -Connector_FFC-FPC -TE_1-1734839-5_1x15-1MP_P0.5mm_Horizontal -TE FPC connector, 15 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -17 -16 -Connector_FFC-FPC -TE_1-1734839-6_1x16-1MP_P0.5mm_Horizontal -TE FPC connector, 16 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -18 -17 -Connector_FFC-FPC -TE_1-1734839-7_1x17-1MP_P0.5mm_Horizontal -TE FPC connector, 17 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -19 -18 -Connector_FFC-FPC -TE_1-1734839-8_1x18-1MP_P0.5mm_Horizontal -TE FPC connector, 18 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -20 -19 -Connector_FFC-FPC -TE_1-1734839-9_1x19-1MP_P0.5mm_Horizontal -TE FPC connector, 19 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -21 -20 -Connector_FFC-FPC -TE_2-84952-0_1x20-1MP_P1.0mm_Horizontal -TE FPC connector, 20 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -22 -21 -Connector_FFC-FPC -TE_2-84952-1_1x21-1MP_P1.0mm_Horizontal -TE FPC connector, 21 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -23 -22 -Connector_FFC-FPC -TE_2-84952-2_1x22-1MP_P1.0mm_Horizontal -TE FPC connector, 22 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -24 -23 -Connector_FFC-FPC -TE_2-84952-3_1x23-1MP_P1.0mm_Horizontal -TE FPC connector, 23 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -25 -24 -Connector_FFC-FPC -TE_2-84952-4_1x24-1MP_P1.0mm_Horizontal -TE FPC connector, 24 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -26 -25 -Connector_FFC-FPC -TE_2-84952-5_1x25-1MP_P1.0mm_Horizontal -TE FPC connector, 25 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -27 -26 -Connector_FFC-FPC -TE_2-84952-6_1x26-1MP_P1.0mm_Horizontal -TE FPC connector, 26 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -28 -27 -Connector_FFC-FPC -TE_2-84952-7_1x27-1MP_P1.0mm_Horizontal -TE FPC connector, 27 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -29 -28 -Connector_FFC-FPC -TE_2-84952-8_1x28-1MP_P1.0mm_Horizontal -TE FPC connector, 28 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -30 -29 -Connector_FFC-FPC -TE_2-84952-9_1x29-1MP_P1.0mm_Horizontal -TE FPC connector, 29 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -31 -30 -Connector_FFC-FPC -TE_2-84953-0_1x20-1MP_P1.0mm_Horizontal -TE FPC connector, 20 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -22 -21 -Connector_FFC-FPC -TE_2-84953-1_1x21-1MP_P1.0mm_Horizontal -TE FPC connector, 21 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -23 -22 -Connector_FFC-FPC -TE_2-84953-2_1x22-1MP_P1.0mm_Horizontal -TE FPC connector, 22 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -24 -23 -Connector_FFC-FPC -TE_2-84953-3_1x23-1MP_P1.0mm_Horizontal -TE FPC connector, 23 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -25 -24 -Connector_FFC-FPC -TE_2-84953-4_1x24-1MP_P1.0mm_Horizontal -TE FPC connector, 24 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -26 -25 -Connector_FFC-FPC -TE_2-84953-5_1x25-1MP_P1.0mm_Horizontal -TE FPC connector, 25 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -27 -26 -Connector_FFC-FPC -TE_2-84953-6_1x26-1MP_P1.0mm_Horizontal -TE FPC connector, 26 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -28 -27 -Connector_FFC-FPC -TE_2-84953-7_1x27-1MP_P1.0mm_Horizontal -TE FPC connector, 27 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -29 -28 -Connector_FFC-FPC -TE_2-84953-8_1x28-1MP_P1.0mm_Horizontal -TE FPC connector, 28 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -30 -29 -Connector_FFC-FPC -TE_2-84953-9_1x29-1MP_P1.0mm_Horizontal -TE FPC connector, 29 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -31 -30 -Connector_FFC-FPC -TE_2-1734839-0_1x20-1MP_P0.5mm_Horizontal -TE FPC connector, 20 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -22 -21 -Connector_FFC-FPC -TE_2-1734839-1_1x21-1MP_P0.5mm_Horizontal -TE FPC connector, 21 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -23 -22 -Connector_FFC-FPC -TE_2-1734839-2_1x22-1MP_P0.5mm_Horizontal -TE FPC connector, 22 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -24 -23 -Connector_FFC-FPC -TE_2-1734839-3_1x23-1MP_P0.5mm_Horizontal -TE FPC connector, 23 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -25 -24 -Connector_FFC-FPC -TE_2-1734839-4_1x24-1MP_P0.5mm_Horizontal -TE FPC connector, 24 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -26 -25 -Connector_FFC-FPC -TE_2-1734839-5_1x25-1MP_P0.5mm_Horizontal -TE FPC connector, 25 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -27 -26 -Connector_FFC-FPC -TE_2-1734839-6_1x26-1MP_P0.5mm_Horizontal -TE FPC connector, 26 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -28 -27 -Connector_FFC-FPC -TE_2-1734839-7_1x27-1MP_P0.5mm_Horizontal -TE FPC connector, 27 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -29 -28 -Connector_FFC-FPC -TE_2-1734839-8_1x28-1MP_P0.5mm_Horizontal -TE FPC connector, 28 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -30 -29 -Connector_FFC-FPC -TE_2-1734839-9_1x29-1MP_P0.5mm_Horizontal -TE FPC connector, 29 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -31 -30 -Connector_FFC-FPC -TE_3-84952-0_1x30-1MP_P1.0mm_Horizontal -TE FPC connector, 30 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -32 -31 -Connector_FFC-FPC -TE_3-84953-0_1x30-1MP_P1.0mm_Horizontal -TE FPC connector, 30 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -32 -31 -Connector_FFC-FPC -TE_3-1734839-0_1x30-1MP_P0.5mm_Horizontal -TE FPC connector, 30 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -32 -31 -Connector_FFC-FPC -TE_3-1734839-1_1x31-1MP_P0.5mm_Horizontal -TE FPC connector, 31 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -33 -32 -Connector_FFC-FPC -TE_3-1734839-2_1x32-1MP_P0.5mm_Horizontal -TE FPC connector, 32 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -34 -33 -Connector_FFC-FPC -TE_3-1734839-3_1x33-1MP_P0.5mm_Horizontal -TE FPC connector, 33 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -35 -34 -Connector_FFC-FPC -TE_3-1734839-4_1x34-1MP_P0.5mm_Horizontal -TE FPC connector, 34 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -36 -35 -Connector_FFC-FPC -TE_3-1734839-5_1x35-1MP_P0.5mm_Horizontal -TE FPC connector, 35 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -37 -36 -Connector_FFC-FPC -TE_3-1734839-6_1x36-1MP_P0.5mm_Horizontal -TE FPC connector, 36 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -38 -37 -Connector_FFC-FPC -TE_3-1734839-7_1x37-1MP_P0.5mm_Horizontal -TE FPC connector, 37 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -39 -38 -Connector_FFC-FPC -TE_3-1734839-8_1x38-1MP_P0.5mm_Horizontal -TE FPC connector, 38 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -40 -39 -Connector_FFC-FPC -TE_3-1734839-9_1x39-1MP_P0.5mm_Horizontal -TE FPC connector, 39 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -41 -40 -Connector_FFC-FPC -TE_4-1734839-0_1x40-1MP_P0.5mm_Horizontal -TE FPC connector, 40 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -42 -41 -Connector_FFC-FPC -TE_4-1734839-1_1x41-1MP_P0.5mm_Horizontal -TE FPC connector, 41 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -43 -42 -Connector_FFC-FPC -TE_4-1734839-2_1x42-1MP_P0.5mm_Horizontal -TE FPC connector, 42 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -44 -43 -Connector_FFC-FPC -TE_4-1734839-3_1x43-1MP_P0.5mm_Horizontal -TE FPC connector, 43 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -45 -44 -Connector_FFC-FPC -TE_4-1734839-4_1x44-1MP_P0.5mm_Horizontal -TE FPC connector, 44 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -46 -45 -Connector_FFC-FPC -TE_4-1734839-5_1x45-1MP_P0.5mm_Horizontal -TE FPC connector, 45 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -47 -46 -Connector_FFC-FPC -TE_4-1734839-6_1x46-1MP_P0.5mm_Horizontal -TE FPC connector, 46 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -48 -47 -Connector_FFC-FPC -TE_4-1734839-7_1x47-1MP_P0.5mm_Horizontal -TE FPC connector, 47 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -49 -48 -Connector_FFC-FPC -TE_4-1734839-8_1x48-1MP_P0.5mm_Horizontal -TE FPC connector, 48 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -50 -49 -Connector_FFC-FPC -TE_4-1734839-9_1x49-1MP_P0.5mm_Horizontal -TE FPC connector, 49 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -51 -50 -Connector_FFC-FPC -TE_5-1734839-0_1x50-1MP_P0.5mm_Horizontal -TE FPC connector, 50 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 -te fpc 1734839 -0 -52 -51 -Connector_FFC-FPC -TE_84952-4_1x04-1MP_P1.0mm_Horizontal -TE FPC connector, 04 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -6 -5 -Connector_FFC-FPC -TE_84952-5_1x05-1MP_P1.0mm_Horizontal -TE FPC connector, 05 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -7 -6 -Connector_FFC-FPC -TE_84952-6_1x06-1MP_P1.0mm_Horizontal -TE FPC connector, 06 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -8 -7 -Connector_FFC-FPC -TE_84952-7_1x07-1MP_P1.0mm_Horizontal -TE FPC connector, 07 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -9 -8 -Connector_FFC-FPC -TE_84952-8_1x08-1MP_P1.0mm_Horizontal -TE FPC connector, 08 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -10 -9 -Connector_FFC-FPC -TE_84952-9_1x09-1MP_P1.0mm_Horizontal -TE FPC connector, 09 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 -te fpc 84952 -0 -11 -10 -Connector_FFC-FPC -TE_84953-4_1x04-1MP_P1.0mm_Horizontal -TE FPC connector, 04 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -6 -5 -Connector_FFC-FPC -TE_84953-5_1x05-1MP_P1.0mm_Horizontal -TE FPC connector, 05 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -7 -6 -Connector_FFC-FPC -TE_84953-6_1x06-1MP_P1.0mm_Horizontal -TE FPC connector, 06 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -8 -7 -Connector_FFC-FPC -TE_84953-7_1x07-1MP_P1.0mm_Horizontal -TE FPC connector, 07 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -9 -8 -Connector_FFC-FPC -TE_84953-8_1x08-1MP_P1.0mm_Horizontal -TE FPC connector, 08 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -10 -9 -Connector_FFC-FPC -TE_84953-9_1x09-1MP_P1.0mm_Horizontal -TE FPC connector, 09 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 -te fpc 84953 -0 -11 -10 -Connector_FFC-FPC -Wuerth_68611214422_1x12-1MP_P1.0mm_Horizontal -http://katalog.we-online.de/em/datasheet/68611214422.pdf -Wuerth FPC 68611214422 connector 12 bottom-side contacts 1.0mm pitch 1.0mm height SMT -0 -14 -13 -Connector_HDMI -HDMI_A_Contact_Technology_HDMI-19APL2_Horizontal -HDMI Contact Technology Type A http://www.contactswitch.com/en/download.aspx?id=1449 -HDMI Contact Technology Type A -0 -23 -20 -Connector_HDMI -HDMI_A_Kycon_KDMIX-SL1-NS-WS-B15_VerticalRightAngle -HDMI, Type A, Kycon KDMIX-SL1-NS-WS-B15, Vertical Right Angle, http://www.kycon.com/Pub_Eng_Draw/KDMIX-SL1-NS-WS-B15.pdf -hdmi type a -0 -23 -20 -Connector_HDMI -HDMI_Micro-D_Molex_46765-0x01 -HDMI, Micro, Type D, SMD, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf) -hdmi micro type d right angle smd -0 -23 -20 -Connector_HDMI -HDMI_Micro-D_Molex_46765-1x01 -HDMI, Micro, Type D, THT, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf) -hdmi micro type d right angle tht -0 -23 -20 -Connector_HDMI -HDMI_Micro-D_Molex_46765-2x0x -HDMI, Micro, Type D, THT/SMD hybrid, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf) -hdmi micro type d right angle tht smd hybrid -0 -23 -20 -Connector_Harwin -Harwin_Gecko-G125-FVX0605L0X_2x03_P1.25mm_Vertical -Harwin Gecko Connector, 6 pins, dual row female, vertical entry, PN:G125-FVX0605L0X -connector harwin gecko -0 -6 -6 -Connector_Harwin -Harwin_Gecko-G125-FVX1005L0X_2x05_P1.25mm_Vertical -Harwin Gecko Connector, 10 pins, dual row female, vertical entry, PN:G125-FVX1005L0X -connector harwin gecko -0 -10 -10 -Connector_Harwin -Harwin_Gecko-G125-FVX1205L0X_2x06_P1.25mm_Vertical -Harwin Gecko Connector, 12 pins, dual row female, vertical entry, PN:G125-FVX1205L0X -connector harwin gecko -0 -12 -12 -Connector_Harwin -Harwin_Gecko-G125-FVX1605L0X_2x08_P1.25mm_Vertical -Harwin Gecko Connector, 16 pins, dual row female, vertical entry, PN:G125-FVX1605L0X -connector harwin gecko -0 -16 -16 -Connector_Harwin -Harwin_Gecko-G125-FVX2005L0X_2x10_P1.25mm_Vertical -Harwin Gecko Connector, 20 pins, dual row female, vertical entry, PN:G125-FVX2005L0X -connector harwin gecko -0 -20 -20 -Connector_Harwin -Harwin_Gecko-G125-FVX2605L0X_2x13_P1.25mm_Vertical -Harwin Gecko Connector, 26 pins, dual row female, vertical entry, PN:G125-FVX2605L0X -connector harwin gecko -0 -26 -26 -Connector_Harwin -Harwin_Gecko-G125-FVX3405L0X_2x17_P1.25mm_Vertical -Harwin Gecko Connector, 34 pins, dual row female, vertical entry, PN:G125-FVX3405L0X -connector harwin gecko -0 -34 -34 -Connector_Harwin -Harwin_Gecko-G125-FVX5005L0X_2x25_P1.25mm_Vertical -Harwin Gecko Connector, 50 pins, dual row female, vertical entry, PN:G125-FVX5005L0X -connector harwin gecko -0 -50 -50 -Connector_Harwin -Harwin_Gecko-G125-MVX0605L0X_2x03_P1.25mm_Vertical -Harwin Gecko Connector, 6 pins, dual row male, vertical entry, no latches, PN:G125-MVX0605L0X -connector harwin gecko -0 -6 -6 -Connector_Harwin -Harwin_Gecko-G125-MVX0605L1X_2x03_P1.25mm_Vertical -Harwin Gecko Connector, 6 pins, dual row male, vertical entry, with latches, PN:G125-MVX0605L1X -connector harwin gecko -0 -6 -6 -Connector_Harwin -Harwin_Gecko-G125-MVX1005L0X_2x05_P1.25mm_Vertical -Harwin Gecko Connector, 10 pins, dual row male, vertical entry, no latches, PN:G125-MVX1005L0X -connector harwin gecko -0 -10 -10 -Connector_Harwin -Harwin_Gecko-G125-MVX1005L1X_2x05_P1.25mm_Vertical -Harwin Gecko Connector, 10 pins, dual row male, vertical entry, with latches, PN:G125-MVX1005L1X -connector harwin gecko -0 -10 -10 -Connector_Harwin -Harwin_Gecko-G125-MVX1205L0X_2x06_P1.25mm_Vertical -Harwin Gecko Connector, 12 pins, dual row male, vertical entry, no latches, PN:G125-MVX1205L0X -connector harwin gecko -0 -12 -12 -Connector_Harwin -Harwin_Gecko-G125-MVX1205L1X_2x06_P1.25mm_Vertical -Harwin Gecko Connector, 12 pins, dual row male, vertical entry, with latches, PN:G125-MVX1205L1X -connector harwin gecko -0 -12 -12 -Connector_Harwin -Harwin_Gecko-G125-MVX1605L0X_2x08_P1.25mm_Vertical -Harwin Gecko Connector, 16 pins, dual row male, vertical entry, no latches, PN:G125-MVX1605L0X -connector harwin gecko -0 -16 -16 -Connector_Harwin -Harwin_Gecko-G125-MVX1605L1X_2x08_P1.25mm_Vertical -Harwin Gecko Connector, 16 pins, dual row male, vertical entry, with latches, PN:G125-MVX1605L1X -connector harwin gecko -0 -16 -16 -Connector_Harwin -Harwin_Gecko-G125-MVX2005L0X_2x10_P1.25mm_Vertical -Harwin Gecko Connector, 20 pins, dual row male, vertical entry, no latches, PN:G125-MVX2005L0X -connector harwin gecko -0 -20 -20 -Connector_Harwin -Harwin_Gecko-G125-MVX2005L1X_2x10_P1.25mm_Vertical -Harwin Gecko Connector, 20 pins, dual row male, vertical entry, with latches, PN:G125-MVX2005L1X -connector harwin gecko -0 -20 -20 -Connector_Harwin -Harwin_Gecko-G125-MVX2605L0X_2x13_P1.25mm_Vertical -Harwin Gecko Connector, 26 pins, dual row male, vertical entry, no latches, PN:G125-MVX2605L0X -connector harwin gecko -0 -26 -26 -Connector_Harwin -Harwin_Gecko-G125-MVX2605L1X_2x13_P1.25mm_Vertical -Harwin Gecko Connector, 26 pins, dual row male, vertical entry, with latches, PN:G125-MVX2605L1X -connector harwin gecko -0 -26 -26 -Connector_Harwin -Harwin_Gecko-G125-MVX3405L0X_2x17_P1.25mm_Vertical -Harwin Gecko Connector, 34 pins, dual row male, vertical entry, no latches, PN:G125-MVX3405L0X -connector harwin gecko -0 -34 -34 -Connector_Harwin -Harwin_Gecko-G125-MVX3405L1X_2x17_P1.25mm_Vertical -Harwin Gecko Connector, 34 pins, dual row male, vertical entry, with latches, PN:G125-MVX3405L1X -connector harwin gecko -0 -34 -34 -Connector_Harwin -Harwin_Gecko-G125-MVX5005L0X_2x25_P1.25mm_Vertical -Harwin Gecko Connector, 50 pins, dual row male, vertical entry, no latches, PN:G125-MVX5005L0X -connector harwin gecko -0 -50 -50 -Connector_Harwin -Harwin_Gecko-G125-MVX5005L1X_2x25_P1.25mm_Vertical -Harwin Gecko Connector, 50 pins, dual row male, vertical entry, with latches, PN:G125-MVX5005L1X -connector harwin gecko -0 -50 -50 -Connector_Harwin -Harwin_LTek-Male_02_P2.00mm_Vertical -Harwin LTek Connector, 2 pins, single row male, vertical entry -connector harwin ltek M80 -0 -2 -2 -Connector_Harwin -Harwin_LTek-Male_02_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 2 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -6 -2 -Connector_Harwin -Harwin_LTek-Male_2x02_P2.00mm_Vertical -Harwin LTek Connector, 4 pins, single row male, vertical entry -connector harwin ltek M80 -0 -4 -4 -Connector_Harwin -Harwin_LTek-Male_2x02_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 4 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -8 -4 -Connector_Harwin -Harwin_LTek-Male_2x03_P2.00mm_Vertical -Harwin LTek Connector, 6 pins, single row male, vertical entry -connector harwin ltek M80 -0 -6 -6 -Connector_Harwin -Harwin_LTek-Male_2x03_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 6 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -10 -6 -Connector_Harwin -Harwin_LTek-Male_2x04_P2.00mm_Vertical -Harwin LTek Connector, 8 pins, single row male, vertical entry -connector harwin ltek M80 -0 -8 -8 -Connector_Harwin -Harwin_LTek-Male_2x04_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 8 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -12 -8 -Connector_Harwin -Harwin_LTek-Male_2x05_P2.00mm_Vertical -Harwin LTek Connector, 10 pins, single row male, vertical entry -connector harwin ltek M80 -0 -10 -10 -Connector_Harwin -Harwin_LTek-Male_2x05_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 10 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -14 -10 -Connector_Harwin -Harwin_LTek-Male_2x06_P2.00mm_Vertical -Harwin LTek Connector, 12 pins, single row male, vertical entry -connector harwin ltek M80 -0 -12 -12 -Connector_Harwin -Harwin_LTek-Male_2x06_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 12 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -16 -12 -Connector_Harwin -Harwin_LTek-Male_2x07_P2.00mm_Vertical -Harwin LTek Connector, 14 pins, single row male, vertical entry -connector harwin ltek M80 -0 -14 -14 -Connector_Harwin -Harwin_LTek-Male_2x07_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 14 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -18 -14 -Connector_Harwin -Harwin_LTek-Male_2x08_P2.00mm_Vertical -Harwin LTek Connector, 16 pins, single row male, vertical entry -connector harwin ltek M80 -0 -16 -16 -Connector_Harwin -Harwin_LTek-Male_2x08_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 16 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -20 -16 -Connector_Harwin -Harwin_LTek-Male_2x09_P2.00mm_Vertical -Harwin LTek Connector, 18 pins, single row male, vertical entry -connector harwin ltek M80 -0 -18 -18 -Connector_Harwin -Harwin_LTek-Male_2x09_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 18 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -22 -18 -Connector_Harwin -Harwin_LTek-Male_2x10_P2.00mm_Vertical -Harwin LTek Connector, 20 pins, single row male, vertical entry -connector harwin ltek M80 -0 -20 -20 -Connector_Harwin -Harwin_LTek-Male_2x10_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 20 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -24 -20 -Connector_Harwin -Harwin_LTek-Male_2x13_P2.00mm_Vertical -Harwin LTek Connector, 26 pins, single row male, vertical entry -connector harwin ltek M80 -0 -26 -26 -Connector_Harwin -Harwin_LTek-Male_2x13_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 26 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -30 -26 -Connector_Harwin -Harwin_LTek-Male_2x17_P2.00mm_Vertical -Harwin LTek Connector, 34 pins, single row male, vertical entry -connector harwin ltek M80 -0 -34 -34 -Connector_Harwin -Harwin_LTek-Male_2x17_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 34 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -38 -34 -Connector_Harwin -Harwin_LTek-Male_2x22_P2.00mm_Vertical -Harwin LTek Connector, 44 pins, single row male, vertical entry -connector harwin ltek M80 -0 -44 -44 -Connector_Harwin -Harwin_LTek-Male_2x22_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 44 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -48 -44 -Connector_Harwin -Harwin_LTek-Male_03_P2.00mm_Vertical -Harwin LTek Connector, 3 pins, single row male, vertical entry -connector harwin ltek M80 -0 -3 -3 -Connector_Harwin -Harwin_LTek-Male_03_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 3 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -7 -3 -Connector_Harwin -Harwin_LTek-Male_04_P2.00mm_Vertical -Harwin LTek Connector, 4 pins, single row male, vertical entry -connector harwin ltek M80 -0 -4 -4 -Connector_Harwin -Harwin_LTek-Male_04_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 4 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -8 -4 -Connector_Harwin -Harwin_LTek-Male_05_P2.00mm_Vertical -Harwin LTek Connector, 5 pins, single row male, vertical entry -connector harwin ltek M80 -0 -5 -5 -Connector_Harwin -Harwin_LTek-Male_05_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 5 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -9 -5 -Connector_Harwin -Harwin_LTek-Male_06_P2.00mm_Vertical -Harwin LTek Connector, 6 pins, single row male, vertical entry -connector harwin ltek M80 -0 -6 -6 -Connector_Harwin -Harwin_LTek-Male_06_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 6 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -10 -6 -Connector_Harwin -Harwin_LTek-Male_07_P2.00mm_Vertical -Harwin LTek Connector, 7 pins, single row male, vertical entry -connector harwin ltek M80 -0 -7 -7 -Connector_Harwin -Harwin_LTek-Male_07_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 7 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -11 -7 -Connector_Harwin -Harwin_LTek-Male_17_P2.00mm_Vertical -Harwin LTek Connector, 17 pins, single row male, vertical entry -connector harwin ltek M80 -0 -17 -17 -Connector_Harwin -Harwin_LTek-Male_17_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 17 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -21 -17 -Connector_Harwin -Harwin_LTek-Male_22_P2.00mm_Vertical -Harwin LTek Connector, 22 pins, single row male, vertical entry -connector harwin ltek M80 -0 -22 -22 -Connector_Harwin -Harwin_LTek-Male_22_P2.00mm_Vertical_StrainRelief -Harwin LTek Connector, 22 pins, single row male, vertical entry, strain relief clip -connector harwin ltek M80 -0 -26 -22 -Connector_Harwin -Harwin_M20-89003xx_1x03_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89003xx, 3 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -4 -3 -Connector_Harwin -Harwin_M20-89004xx_1x04_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89004xx, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -5 -4 -Connector_Harwin -Harwin_M20-89005xx_1x05_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89005xx, 5 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -6 -5 -Connector_Harwin -Harwin_M20-89006xx_1x06_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89006xx, 6 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -7 -6 -Connector_Harwin -Harwin_M20-89007xx_1x07_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89007xx, 7 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -8 -7 -Connector_Harwin -Harwin_M20-89008xx_1x08_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89008xx, 8 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -9 -8 -Connector_Harwin -Harwin_M20-89009xx_1x09_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89009xx, 9 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -10 -9 -Connector_Harwin -Harwin_M20-89010xx_1x10_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89010xx, 10 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -11 -10 -Connector_Harwin -Harwin_M20-89011xx_1x11_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89011xx, 11 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -12 -11 -Connector_Harwin -Harwin_M20-89012xx_1x12_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89012xx, 12 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -13 -12 -Connector_Harwin -Harwin_M20-89013xx_1x13_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89013xx, 13 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -14 -13 -Connector_Harwin -Harwin_M20-89014xx_1x14_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89014xx, 14 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -15 -14 -Connector_Harwin -Harwin_M20-89015xx_1x15_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89015xx, 15 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -16 -15 -Connector_Harwin -Harwin_M20-89016xx_1x16_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89016xx, 16 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -17 -16 -Connector_Harwin -Harwin_M20-89017xx_1x17_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89017xx, 17 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -18 -17 -Connector_Harwin -Harwin_M20-89018xx_1x18_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89018xx, 18 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -19 -18 -Connector_Harwin -Harwin_M20-89019xx_1x19_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89019xx, 19 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -20 -19 -Connector_Harwin -Harwin_M20-89020xx_1x20_P2.54mm_Horizontal -Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89020xx, 20 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator -connector Harwin M20-890 horizontal -0 -21 -20 -Connector_Harwin -Harwin_M20-7810245_2x02_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810245, 2 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -4 -4 -Connector_Harwin -Harwin_M20-7810345_2x03_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810345, 3 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -6 -6 -Connector_Harwin -Harwin_M20-7810445_2x04_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810445, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -8 -8 -Connector_Harwin -Harwin_M20-7810545_2x05_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810545, 5 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -10 -10 -Connector_Harwin -Harwin_M20-7810645_2x06_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810645, 6 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -12 -12 -Connector_Harwin -Harwin_M20-7810745_2x07_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810745, 7 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -14 -14 -Connector_Harwin -Harwin_M20-7810845_2x08_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810845, 8 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -16 -16 -Connector_Harwin -Harwin_M20-7810945_2x09_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810945, 9 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -18 -18 -Connector_Harwin -Harwin_M20-7811045_2x10_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811045, 10 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -20 -20 -Connector_Harwin -Harwin_M20-7811245_2x12_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811245, 12 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -24 -24 -Connector_Harwin -Harwin_M20-7811545_2x15_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811545, 15 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -30 -30 -Connector_Harwin -Harwin_M20-7812045_2x20_P2.54mm_Vertical -Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7812045, 20 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator -connector Harwin M20 side entry -0 -40 -40 -Connector_Hirose -Hirose_BM24_BM24-40DP-2-0.35V_2x20_P0.35mm_PowerPin2_Vertical -Hirose BM24 series connector, BM24-40DP/2-0.35V (https://www.hirose.com/product/en/download_file/key_name/BM24/category/Catalog/doc_file_id/47680/?file_category_id=4&item_id=50&is_series=1) -connector Hirose BM24 40pin header -0 -44 -42 -Connector_Hirose -Hirose_BM24_BM24-40DS-2-0.35V_2x20_P0.35mm_PowerPin2_Vertical -Hirose BM24 series connector, BM24-40DS/2-0.35V (https://www.hirose.com/product/en/download_file/key_name/BM24/category/Catalog/doc_file_id/47680/?file_category_id=4&item_id=50&is_series=1) -connector Hirose 40pin receptacle vertical -0 -42 -42 -Connector_Hirose -Hirose_DF3EA-02P-2H_1x02-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-02P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -4 -3 -Connector_Hirose -Hirose_DF3EA-03P-2H_1x03-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-03P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -5 -4 -Connector_Hirose -Hirose_DF3EA-04P-2H_1x04-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-04P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -6 -5 -Connector_Hirose -Hirose_DF3EA-05P-2H_1x05-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-05P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -7 -6 -Connector_Hirose -Hirose_DF3EA-06P-2H_1x06-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-06P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -8 -7 -Connector_Hirose -Hirose_DF3EA-07P-2H_1x07-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-07P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -9 -8 -Connector_Hirose -Hirose_DF3EA-08P-2H_1x08-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-08P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -10 -9 -Connector_Hirose -Hirose_DF3EA-09P-2H_1x09-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-09P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -11 -10 -Connector_Hirose -Hirose_DF3EA-10P-2H_1x10-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-10P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -12 -11 -Connector_Hirose -Hirose_DF3EA-11P-2H_1x11-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-11P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -13 -12 -Connector_Hirose -Hirose_DF3EA-12P-2H_1x12-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-12P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -14 -13 -Connector_Hirose -Hirose_DF3EA-13P-2H_1x13-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-13P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -15 -14 -Connector_Hirose -Hirose_DF3EA-14P-2H_1x14-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-14P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -16 -15 -Connector_Hirose -Hirose_DF3EA-15P-2H_1x15-1MP_P2.00mm_Horizontal -Hirose series connector, DF3EA-15P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator -connector Hirose top entry -0 -17 -16 -Connector_Hirose -Hirose_DF11-4DP-2DSA_2x02_P2.00mm_Vertical -Hirose DF11 through hole, DF11-4DP-2DSA, 2 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -4 -4 -Connector_Hirose -Hirose_DF11-6DP-2DSA_2x03_P2.00mm_Vertical -Hirose DF11 through hole, DF11-6DP-2DSA, 3 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -6 -6 -Connector_Hirose -Hirose_DF11-8DP-2DSA_2x04_P2.00mm_Vertical -Hirose DF11 through hole, DF11-8DP-2DSA, 4 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -8 -8 -Connector_Hirose -Hirose_DF11-10DP-2DSA_2x05_P2.00mm_Vertical -Hirose DF11 through hole, DF11-10DP-2DSA, 5 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -10 -10 -Connector_Hirose -Hirose_DF11-12DP-2DSA_2x06_P2.00mm_Vertical -Hirose DF11 through hole, DF11-12DP-2DSA, 6 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -12 -12 -Connector_Hirose -Hirose_DF11-14DP-2DSA_2x07_P2.00mm_Vertical -Hirose DF11 through hole, DF11-14DP-2DSA, 7 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -14 -14 -Connector_Hirose -Hirose_DF11-16DP-2DSA_2x08_P2.00mm_Vertical -Hirose DF11 through hole, DF11-16DP-2DSA, 8 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -16 -16 -Connector_Hirose -Hirose_DF11-18DP-2DSA_2x09_P2.00mm_Vertical -Hirose DF11 through hole, DF11-18DP-2DSA, 9 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -18 -18 -Connector_Hirose -Hirose_DF11-20DP-2DSA_2x10_P2.00mm_Vertical -Hirose DF11 through hole, DF11-20DP-2DSA, 10 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -20 -20 -Connector_Hirose -Hirose_DF11-22DP-2DSA_2x11_P2.00mm_Vertical -Hirose DF11 through hole, DF11-22DP-2DSA, 11 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -22 -22 -Connector_Hirose -Hirose_DF11-24DP-2DSA_2x12_P2.00mm_Vertical -Hirose DF11 through hole, DF11-24DP-2DSA, 12 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -24 -24 -Connector_Hirose -Hirose_DF11-26DP-2DSA_2x13_P2.00mm_Vertical -Hirose DF11 through hole, DF11-26DP-2DSA, 13 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -26 -26 -Connector_Hirose -Hirose_DF11-28DP-2DSA_2x14_P2.00mm_Vertical -Hirose DF11 through hole, DF11-28DP-2DSA, 14 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -28 -28 -Connector_Hirose -Hirose_DF11-30DP-2DSA_2x15_P2.00mm_Vertical -Hirose DF11 through hole, DF11-30DP-2DSA, 15 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -30 -30 -Connector_Hirose -Hirose_DF11-32DP-2DSA_2x16_P2.00mm_Vertical -Hirose DF11 through hole, DF11-32DP-2DSA, 16 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator -connector Hirose DF11 vertical -0 -32 -32 -Connector_Hirose -Hirose_DF12_DF12C3.0-10DS-0.5V_2x05_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-10DS-0.5V, 10 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -20 -10 -Connector_Hirose -Hirose_DF12_DF12C3.0-14DS-0.5V_2x07_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-14DS-0.5V, 14 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -28 -14 -Connector_Hirose -Hirose_DF12_DF12C3.0-20DS-0.5V_2x10_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-20DS-0.5V, 20 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -40 -20 -Connector_Hirose -Hirose_DF12_DF12C3.0-30DS-0.5V_2x15_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-30DS-0.5V, 30 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -60 -30 -Connector_Hirose -Hirose_DF12_DF12C3.0-32DS-0.5V_2x16_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-32DS-0.5V, 32 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -64 -32 -Connector_Hirose -Hirose_DF12_DF12C3.0-36DS-0.5V_2x18_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-36DS-0.5V, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -72 -36 -Connector_Hirose -Hirose_DF12_DF12C3.0-40DS-0.5V_2x20_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-40DS-0.5V, 40 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -80 -40 -Connector_Hirose -Hirose_DF12_DF12C3.0-50DS-0.5V_2x25_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-50DS-0.5V, 50 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -100 -50 -Connector_Hirose -Hirose_DF12_DF12C3.0-60DS-0.5V_2x30_P0.50mm_Vertical -Hirose DF12C SMD, DF12C3.0-60DS-0.5V, 60 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -120 -60 -Connector_Hirose -Hirose_DF12_DF12E3.0-10DP-0.5V_2x05_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-10DP-0.5V, 10 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -20 -10 -Connector_Hirose -Hirose_DF12_DF12E3.0-14DP-0.5V_2x07_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-14DP-0.5V, 14 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -28 -14 -Connector_Hirose -Hirose_DF12_DF12E3.0-20DP-0.5V_2x10_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-20DP-0.5V, 20 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -40 -20 -Connector_Hirose -Hirose_DF12_DF12E3.0-30DP-0.5V_2x15_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-30DP-0.5V, 30 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -60 -30 -Connector_Hirose -Hirose_DF12_DF12E3.0-32DP-0.5V_2x16_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-32DP-0.5V, 32 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -64 -32 -Connector_Hirose -Hirose_DF12_DF12E3.0-36DP-0.5V_2x18_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-36DP-0.5V, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -72 -36 -Connector_Hirose -Hirose_DF12_DF12E3.0-40DP-0.5V_2x20_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-40DP-0.5V, 40 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -80 -40 -Connector_Hirose -Hirose_DF12_DF12E3.0-50DP-0.5V_2x25_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-50DP-0.5V, 50 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -100 -50 -Connector_Hirose -Hirose_DF12_DF12E3.0-60DP-0.5V_2x30_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-60DP-0.5V, 60 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -120 -60 -Connector_Hirose -Hirose_DF12_DF12E3.0-80DP-0.5V_2x40_P0.50mm_Vertical -Hirose DF12E SMD, DF12E3.0-80DP-0.5V, 80 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator -connector Hirose DF12 vertical -0 -160 -80 -Connector_Hirose -Hirose_DF13-02P-1.25DSA_1x02_P1.25mm_Vertical -Hirose DF13 through hole, DF13-02P-1.25DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -2 -2 -Connector_Hirose -Hirose_DF13-02P-1.25DS_1x02_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-02P-1.25DS, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -2 -2 -Connector_Hirose -Hirose_DF13-03P-1.25DSA_1x03_P1.25mm_Vertical -Hirose DF13 through hole, DF13-03P-1.25DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -3 -3 -Connector_Hirose -Hirose_DF13-03P-1.25DS_1x03_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-03P-1.25DS, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -3 -3 -Connector_Hirose -Hirose_DF13-04P-1.25DSA_1x04_P1.25mm_Vertical -Hirose DF13 through hole, DF13-04P-1.25DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -4 -4 -Connector_Hirose -Hirose_DF13-04P-1.25DS_1x04_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-04P-1.25DS, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -4 -4 -Connector_Hirose -Hirose_DF13-05P-1.25DSA_1x05_P1.25mm_Vertical -Hirose DF13 through hole, DF13-05P-1.25DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -5 -5 -Connector_Hirose -Hirose_DF13-05P-1.25DS_1x05_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-05P-1.25DS, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -5 -5 -Connector_Hirose -Hirose_DF13-06P-1.25DSA_1x06_P1.25mm_Vertical -Hirose DF13 through hole, DF13-06P-1.25DSA, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -6 -6 -Connector_Hirose -Hirose_DF13-06P-1.25DS_1x06_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-06P-1.25DS, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -6 -6 -Connector_Hirose -Hirose_DF13-07P-1.25DSA_1x07_P1.25mm_Vertical -Hirose DF13 through hole, DF13-07P-1.25DSA, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -7 -7 -Connector_Hirose -Hirose_DF13-07P-1.25DS_1x07_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-07P-1.25DS, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -7 -7 -Connector_Hirose -Hirose_DF13-08P-1.25DSA_1x08_P1.25mm_Vertical -Hirose DF13 through hole, DF13-08P-1.25DSA, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -8 -8 -Connector_Hirose -Hirose_DF13-08P-1.25DS_1x08_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-08P-1.25DS, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -8 -8 -Connector_Hirose -Hirose_DF13-09P-1.25DSA_1x09_P1.25mm_Vertical -Hirose DF13 through hole, DF13-09P-1.25DSA, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -9 -9 -Connector_Hirose -Hirose_DF13-09P-1.25DS_1x09_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-09P-1.25DS, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -9 -9 -Connector_Hirose -Hirose_DF13-10P-1.25DSA_1x10_P1.25mm_Vertical -Hirose DF13 through hole, DF13-10P-1.25DSA, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -10 -10 -Connector_Hirose -Hirose_DF13-10P-1.25DS_1x10_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-10P-1.25DS, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -10 -10 -Connector_Hirose -Hirose_DF13-11P-1.25DSA_1x11_P1.25mm_Vertical -Hirose DF13 through hole, DF13-11P-1.25DSA, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -11 -11 -Connector_Hirose -Hirose_DF13-11P-1.25DS_1x11_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-11P-1.25DS, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -11 -11 -Connector_Hirose -Hirose_DF13-12P-1.25DSA_1x12_P1.25mm_Vertical -Hirose DF13 through hole, DF13-12P-1.25DSA, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -12 -12 -Connector_Hirose -Hirose_DF13-12P-1.25DS_1x12_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-12P-1.25DS, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -12 -12 -Connector_Hirose -Hirose_DF13-13P-1.25DSA_1x13_P1.25mm_Vertical -Hirose DF13 through hole, DF13-13P-1.25DSA, 13 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -13 -13 -Connector_Hirose -Hirose_DF13-14P-1.25DSA_1x14_P1.25mm_Vertical -Hirose DF13 through hole, DF13-14P-1.25DSA, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -14 -14 -Connector_Hirose -Hirose_DF13-14P-1.25DS_1x14_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-14P-1.25DS, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -14 -14 -Connector_Hirose -Hirose_DF13-15P-1.25DSA_1x15_P1.25mm_Vertical -Hirose DF13 through hole, DF13-15P-1.25DSA, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator -connector Hirose DF13 vertical -0 -15 -15 -Connector_Hirose -Hirose_DF13-15P-1.25DS_1x15_P1.25mm_Horizontal -Hirose DF13 through hole, DF13-15P-1.25DS, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator -connector Hirose DF13 horizontal -0 -15 -15 -Connector_Hirose -Hirose_DF13C_CL535-0402-2-51_1x02-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0402-2-51, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -4 -3 -Connector_Hirose -Hirose_DF13C_CL535-0403-5-51_1x03-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0403-5-51, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -5 -4 -Connector_Hirose -Hirose_DF13C_CL535-0404-8-51_1x04-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0404-8-51, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -6 -5 -Connector_Hirose -Hirose_DF13C_CL535-0405-0-51_1x05-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0405-0-51, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -7 -6 -Connector_Hirose -Hirose_DF13C_CL535-0406-3-51_1x06-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0406-3-51, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -8 -7 -Connector_Hirose -Hirose_DF13C_CL535-0407-6-51_1x07-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0407-6-51, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -9 -8 -Connector_Hirose -Hirose_DF13C_CL535-0408-9-51_1x08-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0408-9-51, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -10 -9 -Connector_Hirose -Hirose_DF13C_CL535-0409-1-51_1x09-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0409-1-51, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -11 -10 -Connector_Hirose -Hirose_DF13C_CL535-0410-4-51_1x10-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0410-4-51, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -12 -11 -Connector_Hirose -Hirose_DF13C_CL535-0411-3-51_1x11-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0411-3-51, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -13 -12 -Connector_Hirose -Hirose_DF13C_CL535-0412-6-51_1x12-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0412-6-51, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -14 -13 -Connector_Hirose -Hirose_DF13C_CL535-0414-1-51_1x14-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0414-1-51, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -16 -15 -Connector_Hirose -Hirose_DF13C_CL535-0415-4-51_1x15-1MP_P1.25mm_Vertical -Hirose DF13C SMD, CL535-0415-4-51, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator -connector Hirose DF13C vertical -0 -17 -16 -Connector_Hirose -Hirose_DF52-2S-0.8H_1x02-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-2S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -4 -3 -Connector_Hirose -Hirose_DF52-3S-0.8H_1x03-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-3S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -5 -4 -Connector_Hirose -Hirose_DF52-4S-0.8H_1x04-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-4S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -6 -5 -Connector_Hirose -Hirose_DF52-5S-0.8H_1x05-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-5S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -7 -6 -Connector_Hirose -Hirose_DF52-6S-0.8H_1x06-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-6S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -8 -7 -Connector_Hirose -Hirose_DF52-7S-0.8H_1x07-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-7S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -9 -8 -Connector_Hirose -Hirose_DF52-8S-0.8H_1x08-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-8S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -10 -9 -Connector_Hirose -Hirose_DF52-9S-0.8H_1x09-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-9S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -11 -10 -Connector_Hirose -Hirose_DF52-10S-0.8H_1x10-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-10S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -12 -11 -Connector_Hirose -Hirose_DF52-11S-0.8H_1x11-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-11S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -13 -12 -Connector_Hirose -Hirose_DF52-12S-0.8H_1x12-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-12S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -14 -13 -Connector_Hirose -Hirose_DF52-14S-0.8H_1x14-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-14S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -16 -15 -Connector_Hirose -Hirose_DF52-15S-0.8H_1x15-1MP_P0.80mm_Horizontal -Hirose series connector, DF52-15S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator -connector Hirose top entry -0 -17 -16 -Connector_Hirose -Hirose_DF63-5P-3.96DSA_1x05_P3.96mm_Vertical -Hirose DF63 through hole, DF63-5P-3.96DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -5 -5 -Connector_Hirose -Hirose_DF63-6P-3.96DSA_1x06_P3.96mm_Vertical -Hirose DF63 through hole, DF63-6P-3.96DSA, 6 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -6 -6 -Connector_Hirose -Hirose_DF63M-1P-3.96DSA_1x01_P3.96mm_Vertical -Hirose DF63 through hole, DF63M-1P-3.96DSA, 1 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -1 -1 -Connector_Hirose -Hirose_DF63M-2P-3.96DSA_1x02_P3.96mm_Vertical -Hirose DF63 through hole, DF63M-2P-3.96DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -2 -2 -Connector_Hirose -Hirose_DF63M-3P-3.96DSA_1x03_P3.96mm_Vertical -Hirose DF63 through hole, DF63M-3P-3.96DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -3 -3 -Connector_Hirose -Hirose_DF63M-4P-3.96DSA_1x04_P3.96mm_Vertical -Hirose DF63 through hole, DF63M-4P-3.96DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -4 -4 -Connector_Hirose -Hirose_DF63R-1P-3.96DSA_1x01_P3.96mm_Vertical -Hirose DF63 through hole, DF63R-1P-3.96DSA, 1 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -1 -1 -Connector_Hirose -Hirose_DF63R-2P-3.96DSA_1x02_P3.96mm_Vertical -Hirose DF63 through hole, DF63R-2P-3.96DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -2 -2 -Connector_Hirose -Hirose_DF63R-3P-3.96DSA_1x03_P3.96mm_Vertical -Hirose DF63 through hole, DF63R-3P-3.96DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -3 -3 -Connector_Hirose -Hirose_DF63R-4P-3.96DSA_1x04_P3.96mm_Vertical -Hirose DF63 through hole, DF63R-4P-3.96DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -4 -4 -Connector_Hirose -Hirose_DF63R-5P-3.96DSA_1x05_P3.96mm_Vertical -Hirose DF63 through hole, DF63R-5P-3.96DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator -connector Hirose DF63 vertical -0 -5 -5 -Connector_IDC -IDC-Header_2x03_P2.54mm_Horizontal -Through hole angled IDC box header, 2x03, 2.54mm pitch, double rows -Through hole IDC box header THT 2x03 2.54mm double row -0 -6 -6 -Connector_IDC -IDC-Header_2x03_P2.54mm_Vertical -Through hole straight IDC box header, 2x03, 2.54mm pitch, double rows -Through hole IDC box header THT 2x03 2.54mm double row -0 -6 -6 -Connector_IDC -IDC-Header_2x04_P2.54mm_Horizontal -Through hole angled IDC box header, 2x04, 2.54mm pitch, double rows -Through hole IDC box header THT 2x04 2.54mm double row -0 -8 -8 -Connector_IDC -IDC-Header_2x04_P2.54mm_Vertical -Through hole straight IDC box header, 2x04, 2.54mm pitch, double rows -Through hole IDC box header THT 2x04 2.54mm double row -0 -8 -8 -Connector_IDC -IDC-Header_2x05_P2.54mm_Horizontal -Through hole angled IDC box header, 2x05, 2.54mm pitch, double rows -Through hole IDC box header THT 2x05 2.54mm double row -0 -10 -10 -Connector_IDC -IDC-Header_2x05_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -12 -10 -Connector_IDC -IDC-Header_2x05_P2.54mm_Vertical -Through hole straight IDC box header, 2x05, 2.54mm pitch, double rows -Through hole IDC box header THT 2x05 2.54mm double row -0 -10 -10 -Connector_IDC -IDC-Header_2x05_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -12 -10 -Connector_IDC -IDC-Header_2x06_P2.54mm_Horizontal -Through hole angled IDC box header, 2x06, 2.54mm pitch, double rows -Through hole IDC box header THT 2x06 2.54mm double row -0 -12 -12 -Connector_IDC -IDC-Header_2x06_P2.54mm_Vertical -Through hole straight IDC box header, 2x06, 2.54mm pitch, double rows -Through hole IDC box header THT 2x06 2.54mm double row -0 -12 -12 -Connector_IDC -IDC-Header_2x07_P2.54mm_Horizontal -Through hole angled IDC box header, 2x07, 2.54mm pitch, double rows -Through hole IDC box header THT 2x07 2.54mm double row -0 -14 -14 -Connector_IDC -IDC-Header_2x07_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -16 -14 -Connector_IDC -IDC-Header_2x07_P2.54mm_Vertical -Through hole straight IDC box header, 2x07, 2.54mm pitch, double rows -Through hole IDC box header THT 2x07 2.54mm double row -0 -14 -14 -Connector_IDC -IDC-Header_2x07_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -16 -14 -Connector_IDC -IDC-Header_2x08_P2.54mm_Horizontal -Through hole angled IDC box header, 2x08, 2.54mm pitch, double rows -Through hole IDC box header THT 2x08 2.54mm double row -0 -16 -16 -Connector_IDC -IDC-Header_2x08_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -18 -16 -Connector_IDC -IDC-Header_2x08_P2.54mm_Vertical -Through hole straight IDC box header, 2x08, 2.54mm pitch, double rows -Through hole IDC box header THT 2x08 2.54mm double row -0 -16 -16 -Connector_IDC -IDC-Header_2x08_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -18 -16 -Connector_IDC -IDC-Header_2x10_P2.54mm_Horizontal -Through hole angled IDC box header, 2x10, 2.54mm pitch, double rows -Through hole IDC box header THT 2x10 2.54mm double row -0 -20 -20 -Connector_IDC -IDC-Header_2x10_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -22 -20 -Connector_IDC -IDC-Header_2x10_P2.54mm_Vertical -Through hole straight IDC box header, 2x10, 2.54mm pitch, double rows -Through hole IDC box header THT 2x10 2.54mm double row -0 -20 -20 -Connector_IDC -IDC-Header_2x10_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -22 -20 -Connector_IDC -IDC-Header_2x13_P2.54mm_Horizontal -Through hole angled IDC box header, 2x13, 2.54mm pitch, double rows -Through hole IDC box header THT 2x13 2.54mm double row -0 -26 -26 -Connector_IDC -IDC-Header_2x13_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -28 -26 -Connector_IDC -IDC-Header_2x13_P2.54mm_Vertical -Through hole straight IDC box header, 2x13, 2.54mm pitch, double rows -Through hole IDC box header THT 2x13 2.54mm double row -0 -26 -26 -Connector_IDC -IDC-Header_2x13_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -28 -26 -Connector_IDC -IDC-Header_2x15_P2.54mm_Horizontal -Through hole angled IDC box header, 2x15, 2.54mm pitch, double rows -Through hole IDC box header THT 2x15 2.54mm double row -0 -30 -30 -Connector_IDC -IDC-Header_2x15_P2.54mm_Vertical -Through hole straight IDC box header, 2x15, 2.54mm pitch, double rows -Through hole IDC box header THT 2x15 2.54mm double row -0 -30 -30 -Connector_IDC -IDC-Header_2x17_P2.54mm_Horizontal -Through hole angled IDC box header, 2x17, 2.54mm pitch, double rows -Through hole IDC box header THT 2x17 2.54mm double row -0 -34 -34 -Connector_IDC -IDC-Header_2x17_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -36 -34 -Connector_IDC -IDC-Header_2x17_P2.54mm_Vertical -Through hole straight IDC box header, 2x17, 2.54mm pitch, double rows -Through hole IDC box header THT 2x17 2.54mm double row -0 -34 -34 -Connector_IDC -IDC-Header_2x17_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -36 -34 -Connector_IDC -IDC-Header_2x20_P2.54mm_Horizontal -Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows -Through hole IDC box header THT 2x20 2.54mm double row -0 -40 -40 -Connector_IDC -IDC-Header_2x20_P2.54mm_Horizontal_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -42 -41 -Connector_IDC -IDC-Header_2x20_P2.54mm_Vertical -Through hole straight IDC box header, 2x20, 2.54mm pitch, double rows -Through hole IDC box header THT 2x20 2.54mm double row -0 -40 -40 -Connector_IDC -IDC-Header_2x20_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -42 -40 -Connector_IDC -IDC-Header_2x25_P2.54mm_Horizontal -Through hole angled IDC box header, 2x25, 2.54mm pitch, double rows -Through hole IDC box header THT 2x25 2.54mm double row -0 -50 -50 -Connector_IDC -IDC-Header_2x25_P2.54mm_Vertical -Through hole straight IDC box header, 2x25, 2.54mm pitch, double rows -Through hole IDC box header THT 2x25 2.54mm double row -0 -50 -50 -Connector_IDC -IDC-Header_2x25_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -52 -50 -Connector_IDC -IDC-Header_2x30_P2.54mm_Horizontal -Through hole angled IDC box header, 2x30, 2.54mm pitch, double rows -Through hole IDC box header THT 2x30 2.54mm double row -0 -60 -60 -Connector_IDC -IDC-Header_2x30_P2.54mm_Vertical -Through hole straight IDC box header, 2x30, 2.54mm pitch, double rows -Through hole IDC box header THT 2x30 2.54mm double row -0 -60 -60 -Connector_IDC -IDC-Header_2x30_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -62 -60 -Connector_IDC -IDC-Header_2x32_P2.54mm_Horizontal -Through hole angled IDC box header, 2x32, 2.54mm pitch, double rows -Through hole IDC box header THT 2x32 2.54mm double row -0 -64 -64 -Connector_IDC -IDC-Header_2x32_P2.54mm_Vertical -Through hole straight IDC box header, 2x32, 2.54mm pitch, double rows -Through hole IDC box header THT 2x32 2.54mm double row -0 -64 -64 -Connector_IDC -IDC-Header_2x32_P2.54mm_Vertical_Lock -Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) -connector idc locked -0 -66 -64 -Connector_JAE -JAE_LY20-4P-DLT1_2x02_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-4P-DLT1, 2 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -4 -4 -Connector_JAE -JAE_LY20-4P-DT1_2x02_P2.00mm_Vertical -Molex LY 20 series connector, LY20-4P-DT1, 2 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -4 -4 -Connector_JAE -JAE_LY20-6P-DLT1_2x03_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-6P-DLT1, 3 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -6 -6 -Connector_JAE -JAE_LY20-6P-DT1_2x03_P2.00mm_Vertical -Molex LY 20 series connector, LY20-6P-DT1, 3 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -6 -6 -Connector_JAE -JAE_LY20-8P-DLT1_2x04_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-8P-DLT1, 4 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -8 -8 -Connector_JAE -JAE_LY20-8P-DT1_2x04_P2.00mm_Vertical -Molex LY 20 series connector, LY20-8P-DT1, 4 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -8 -8 -Connector_JAE -JAE_LY20-10P-DLT1_2x05_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-10P-DLT1, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -10 -10 -Connector_JAE -JAE_LY20-10P-DT1_2x05_P2.00mm_Vertical -Molex LY 20 series connector, LY20-10P-DT1, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -10 -10 -Connector_JAE -JAE_LY20-12P-DLT1_2x06_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-12P-DLT1, 6 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -12 -12 -Connector_JAE -JAE_LY20-12P-DT1_2x06_P2.00mm_Vertical -Molex LY 20 series connector, LY20-12P-DT1, 6 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -12 -12 -Connector_JAE -JAE_LY20-14P-DLT1_2x07_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-14P-DLT1, 7 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -14 -14 -Connector_JAE -JAE_LY20-14P-DT1_2x07_P2.00mm_Vertical -Molex LY 20 series connector, LY20-14P-DT1, 7 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -14 -14 -Connector_JAE -JAE_LY20-16P-DLT1_2x08_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-16P-DLT1, 8 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -16 -16 -Connector_JAE -JAE_LY20-16P-DT1_2x08_P2.00mm_Vertical -Molex LY 20 series connector, LY20-16P-DT1, 8 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -16 -16 -Connector_JAE -JAE_LY20-18P-DLT1_2x09_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-18P-DLT1, 9 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -18 -18 -Connector_JAE -JAE_LY20-18P-DT1_2x09_P2.00mm_Vertical -Molex LY 20 series connector, LY20-18P-DT1, 9 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -18 -18 -Connector_JAE -JAE_LY20-20P-DLT1_2x10_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-20P-DLT1, 10 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -20 -20 -Connector_JAE -JAE_LY20-20P-DT1_2x10_P2.00mm_Vertical -Molex LY 20 series connector, LY20-20P-DT1, 10 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -20 -20 -Connector_JAE -JAE_LY20-22P-DLT1_2x11_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-22P-DLT1, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -22 -22 -Connector_JAE -JAE_LY20-22P-DT1_2x11_P2.00mm_Vertical -Molex LY 20 series connector, LY20-22P-DT1, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -22 -22 -Connector_JAE -JAE_LY20-24P-DLT1_2x12_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-24P-DLT1, 12 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -24 -24 -Connector_JAE -JAE_LY20-24P-DT1_2x12_P2.00mm_Vertical -Molex LY 20 series connector, LY20-24P-DT1, 12 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -24 -24 -Connector_JAE -JAE_LY20-26P-DLT1_2x13_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-26P-DLT1, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -26 -26 -Connector_JAE -JAE_LY20-26P-DT1_2x13_P2.00mm_Vertical -Molex LY 20 series connector, LY20-26P-DT1, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -26 -26 -Connector_JAE -JAE_LY20-28P-DLT1_2x14_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-28P-DLT1, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -28 -28 -Connector_JAE -JAE_LY20-28P-DT1_2x14_P2.00mm_Vertical -Molex LY 20 series connector, LY20-28P-DT1, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -28 -28 -Connector_JAE -JAE_LY20-30P-DLT1_2x15_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-30P-DLT1, 15 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -30 -30 -Connector_JAE -JAE_LY20-30P-DT1_2x15_P2.00mm_Vertical -Molex LY 20 series connector, LY20-30P-DT1, 15 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -30 -30 -Connector_JAE -JAE_LY20-32P-DLT1_2x16_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-32P-DLT1, 16 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -32 -32 -Connector_JAE -JAE_LY20-32P-DT1_2x16_P2.00mm_Vertical -Molex LY 20 series connector, LY20-32P-DT1, 16 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -32 -32 -Connector_JAE -JAE_LY20-34P-DLT1_2x17_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-34P-DLT1, 17 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -34 -34 -Connector_JAE -JAE_LY20-34P-DT1_2x17_P2.00mm_Vertical -Molex LY 20 series connector, LY20-34P-DT1, 17 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -34 -34 -Connector_JAE -JAE_LY20-36P-DLT1_2x18_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-36P-DLT1, 18 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -36 -36 -Connector_JAE -JAE_LY20-36P-DT1_2x18_P2.00mm_Vertical -Molex LY 20 series connector, LY20-36P-DT1, 18 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -36 -36 -Connector_JAE -JAE_LY20-38P-DLT1_2x19_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-38P-DLT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -38 -38 -Connector_JAE -JAE_LY20-38P-DT1_2x19_P2.00mm_Vertical -Molex LY 20 series connector, LY20-38P-DT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -38 -38 -Connector_JAE -JAE_LY20-40P-DLT1_2x20_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-40P-DLT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -40 -40 -Connector_JAE -JAE_LY20-40P-DT1_2x20_P2.00mm_Vertical -Molex LY 20 series connector, LY20-40P-DT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -40 -40 -Connector_JAE -JAE_LY20-42P-DLT1_2x21_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-42P-DLT1, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -42 -42 -Connector_JAE -JAE_LY20-42P-DT1_2x21_P2.00mm_Vertical -Molex LY 20 series connector, LY20-42P-DT1, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -42 -42 -Connector_JAE -JAE_LY20-44P-DLT1_2x22_P2.00mm_Horizontal -Molex LY 20 series connector, LY20-44P-DLT1, 22 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator -connector JAE top entry -0 -44 -44 -Connector_JAE -JAE_LY20-44P-DT1_2x22_P2.00mm_Vertical -Molex LY 20 series connector, LY20-44P-DT1, 22 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator -connector JAE side entry -0 -44 -44 -Connector_JAE -JAE_MM70-314-310B1 -http://www.heilind.com/marketing/documents/jae/JAE_MM70.pdf -connector JAE MXM -0 -280 -279 -Connector_JST -JST_ACH_BM01B-ACHSS-A-GAN-ETF_1x01-1MP_P1.20mm_Vertical -JST ACH series connector, BM01B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator -connector JST ACH vertical -0 -3 -2 -Connector_JST -JST_ACH_BM02B-ACHSS-GAN-ETF_1x02-1MP_P1.20mm_Vertical -JST ACH series connector, BM02B-ACHSS-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator -connector JST ACH vertical -0 -4 -3 -Connector_JST -JST_ACH_BM03B-ACHSS-GAN-ETF_1x03-1MP_P1.20mm_Vertical -JST ACH series connector, BM03B-ACHSS-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator -connector JST ACH vertical -0 -5 -4 -Connector_JST -JST_ACH_BM04B-ACHSS-A-GAN-ETF_1x04-1MP_P1.20mm_Vertical -JST ACH series connector, BM04B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator -connector JST ACH vertical -0 -6 -5 -Connector_JST -JST_ACH_BM05B-ACHSS-A-GAN-ETF_1x05-1MP_P1.20mm_Vertical -JST ACH series connector, BM05B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator -connector JST ACH vertical -0 -7 -6 -Connector_JST -JST_AUH_BM03B-AUHKS-GA-TB_1x03-1MP_P1.50mm_Vertical -JST AUH series connector, BM03B-AUHKS-GA-TB (http://www.jst-mfg.com/product/pdf/eng/eAUH.pdf), generated with kicad-footprint-generator -connector JST AUH side entry -0 -5 -4 -Connector_JST -JST_AUH_BM05B-AUHKS-GA-TB_1x05-1MP_P1.50mm_Vertical -JST AUH series connector, BM05B-AUHKS-GA-TB (http://www.jst-mfg.com/product/pdf/eng/eAUH.pdf), generated with kicad-footprint-generator -connector JST AUH side entry -0 -7 -6 -Connector_JST -JST_EH_B2B-EH-A_1x02_P2.50mm_Vertical -JST EH series connector, B2B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -2 -2 -Connector_JST -JST_EH_B3B-EH-A_1x03_P2.50mm_Vertical -JST EH series connector, B3B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -3 -3 -Connector_JST -JST_EH_B4B-EH-A_1x04_P2.50mm_Vertical -JST EH series connector, B4B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -4 -4 -Connector_JST -JST_EH_B5B-EH-A_1x05_P2.50mm_Vertical -JST EH series connector, B5B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -5 -5 -Connector_JST -JST_EH_B6B-EH-A_1x06_P2.50mm_Vertical -JST EH series connector, B6B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -6 -6 -Connector_JST -JST_EH_B7B-EH-A_1x07_P2.50mm_Vertical -JST EH series connector, B7B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -7 -7 -Connector_JST -JST_EH_B8B-EH-A_1x08_P2.50mm_Vertical -JST EH series connector, B8B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -8 -8 -Connector_JST -JST_EH_B9B-EH-A_1x09_P2.50mm_Vertical -JST EH series connector, B9B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH vertical -0 -9 -9 -Connector_JST -JST_EH_B10B-EH-A_1x10_P2.50mm_Vertical -JST EH series connector, B10B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH side entry -0 -10 -10 -Connector_JST -JST_EH_B11B-EH-A_1x11_P2.50mm_Vertical -JST EH series connector, B11B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH side entry -0 -11 -11 -Connector_JST -JST_EH_B12B-EH-A_1x12_P2.50mm_Vertical -JST EH series connector, B12B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH side entry -0 -12 -12 -Connector_JST -JST_EH_B13B-EH-A_1x13_P2.50mm_Vertical -JST EH series connector, B13B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH side entry -0 -13 -13 -Connector_JST -JST_EH_B14B-EH-A_1x14_P2.50mm_Vertical -JST EH series connector, B14B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH side entry -0 -14 -14 -Connector_JST -JST_EH_B15B-EH-A_1x15_P2.50mm_Vertical -JST EH series connector, B15B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH side entry -0 -15 -15 -Connector_JST -JST_EH_S2B-EH_1x02_P2.50mm_Horizontal -JST EH series connector, S2B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -2 -2 -Connector_JST -JST_EH_S3B-EH_1x03_P2.50mm_Horizontal -JST EH series connector, S3B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -3 -3 -Connector_JST -JST_EH_S4B-EH_1x04_P2.50mm_Horizontal -JST EH series connector, S4B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -4 -4 -Connector_JST -JST_EH_S5B-EH_1x05_P2.50mm_Horizontal -JST EH series connector, S5B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -5 -5 -Connector_JST -JST_EH_S6B-EH_1x06_P2.50mm_Horizontal -JST EH series connector, S6B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -6 -6 -Connector_JST -JST_EH_S7B-EH_1x07_P2.50mm_Horizontal -JST EH series connector, S7B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -7 -7 -Connector_JST -JST_EH_S8B-EH_1x08_P2.50mm_Horizontal -JST EH series connector, S8B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -8 -8 -Connector_JST -JST_EH_S9B-EH_1x09_P2.50mm_Horizontal -JST EH series connector, S9B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH horizontal -0 -9 -9 -Connector_JST -JST_EH_S10B-EH_1x10_P2.50mm_Horizontal -JST EH series connector, S10B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH top entry -0 -10 -10 -Connector_JST -JST_EH_S11B-EH_1x11_P2.50mm_Horizontal -JST EH series connector, S11B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH top entry -0 -11 -11 -Connector_JST -JST_EH_S12B-EH_1x12_P2.50mm_Horizontal -JST EH series connector, S12B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH top entry -0 -12 -12 -Connector_JST -JST_EH_S13B-EH_1x13_P2.50mm_Horizontal -JST EH series connector, S13B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH top entry -0 -13 -13 -Connector_JST -JST_EH_S14B-EH_1x14_P2.50mm_Horizontal -JST EH series connector, S14B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH top entry -0 -14 -14 -Connector_JST -JST_EH_S15B-EH_1x15_P2.50mm_Horizontal -JST EH series connector, S15B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator -connector JST EH top entry -0 -15 -15 -Connector_JST -JST_GH_BM02B-GHS-TBT_1x02-1MP_P1.25mm_Vertical -JST GH series connector, BM02B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -4 -3 -Connector_JST -JST_GH_BM03B-GHS-TBT_1x03-1MP_P1.25mm_Vertical -JST GH series connector, BM03B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -5 -4 -Connector_JST -JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical -JST GH series connector, BM04B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -6 -5 -Connector_JST -JST_GH_BM05B-GHS-TBT_1x05-1MP_P1.25mm_Vertical -JST GH series connector, BM05B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -7 -6 -Connector_JST -JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical -JST GH series connector, BM06B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -8 -7 -Connector_JST -JST_GH_BM07B-GHS-TBT_1x07-1MP_P1.25mm_Vertical -JST GH series connector, BM07B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -9 -8 -Connector_JST -JST_GH_BM08B-GHS-TBT_1x08-1MP_P1.25mm_Vertical -JST GH series connector, BM08B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -10 -9 -Connector_JST -JST_GH_BM09B-GHS-TBT_1x09-1MP_P1.25mm_Vertical -JST GH series connector, BM09B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -11 -10 -Connector_JST -JST_GH_BM10B-GHS-TBT_1x10-1MP_P1.25mm_Vertical -JST GH series connector, BM10B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -12 -11 -Connector_JST -JST_GH_BM11B-GHS-TBT_1x11-1MP_P1.25mm_Vertical -JST GH series connector, BM11B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -13 -12 -Connector_JST -JST_GH_BM12B-GHS-TBT_1x12-1MP_P1.25mm_Vertical -JST GH series connector, BM12B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -14 -13 -Connector_JST -JST_GH_BM13B-GHS-TBT_1x13-1MP_P1.25mm_Vertical -JST GH series connector, BM13B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -15 -14 -Connector_JST -JST_GH_BM14B-GHS-TBT_1x14-1MP_P1.25mm_Vertical -JST GH series connector, BM14B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -16 -15 -Connector_JST -JST_GH_BM15B-GHS-TBT_1x15-1MP_P1.25mm_Vertical -JST GH series connector, BM15B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH side entry -0 -17 -16 -Connector_JST -JST_GH_SM02B-GHS-TB_1x02-1MP_P1.25mm_Horizontal -JST GH series connector, SM02B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -4 -3 -Connector_JST -JST_GH_SM03B-GHS-TB_1x03-1MP_P1.25mm_Horizontal -JST GH series connector, SM03B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -5 -4 -Connector_JST -JST_GH_SM04B-GHS-TB_1x04-1MP_P1.25mm_Horizontal -JST GH series connector, SM04B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -6 -5 -Connector_JST -JST_GH_SM05B-GHS-TB_1x05-1MP_P1.25mm_Horizontal -JST GH series connector, SM05B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -7 -6 -Connector_JST -JST_GH_SM06B-GHS-TB_1x06-1MP_P1.25mm_Horizontal -JST GH series connector, SM06B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -8 -7 -Connector_JST -JST_GH_SM07B-GHS-TB_1x07-1MP_P1.25mm_Horizontal -JST GH series connector, SM07B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -9 -8 -Connector_JST -JST_GH_SM08B-GHS-TB_1x08-1MP_P1.25mm_Horizontal -JST GH series connector, SM08B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -10 -9 -Connector_JST -JST_GH_SM09B-GHS-TB_1x09-1MP_P1.25mm_Horizontal -JST GH series connector, SM09B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -11 -10 -Connector_JST -JST_GH_SM10B-GHS-TB_1x10-1MP_P1.25mm_Horizontal -JST GH series connector, SM10B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -12 -11 -Connector_JST -JST_GH_SM11B-GHS-TB_1x11-1MP_P1.25mm_Horizontal -JST GH series connector, SM11B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -13 -12 -Connector_JST -JST_GH_SM12B-GHS-TB_1x12-1MP_P1.25mm_Horizontal -JST GH series connector, SM12B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -14 -13 -Connector_JST -JST_GH_SM13B-GHS-TB_1x13-1MP_P1.25mm_Horizontal -JST GH series connector, SM13B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -15 -14 -Connector_JST -JST_GH_SM14B-GHS-TB_1x14-1MP_P1.25mm_Horizontal -JST GH series connector, SM14B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -16 -15 -Connector_JST -JST_GH_SM15B-GHS-TB_1x15-1MP_P1.25mm_Horizontal -JST GH series connector, SM15B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator -connector JST GH top entry -0 -17 -16 -Connector_JST -JST_J2100_B06B-J21DK-GGXR_2x03_P2.50x4.00mm_Vertical -JST J2100 series connector, B06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 vertical -0 -8 -6 -Connector_JST -JST_J2100_B08B-J21DK-GGXR_2x04_P2.50x4.00mm_Vertical -JST J2100 series connector, B08B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 vertical -0 -10 -8 -Connector_JST -JST_J2100_B10B-J21DK-GGXR_2x05_P2.50x4.00mm_Vertical -JST J2100 series connector, B10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 vertical -0 -12 -10 -Connector_JST -JST_J2100_B12B-J21DK-GGXR_2x06_P2.50x4.00mm_Vertical -JST J2100 series connector, B12B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 vertical -0 -14 -12 -Connector_JST -JST_J2100_B16B-J21DK-GGXR_2x08_P2.50x4.00mm_Vertical -JST J2100 series connector, B16B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 vertical -0 -18 -16 -Connector_JST -JST_J2100_B20B-J21DK-GGXR_2x10_P2.50x4.00mm_Vertical -JST J2100 series connector, B20B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 vertical -0 -22 -20 -Connector_JST -JST_J2100_S06B-J21DK-GGXR_2x03_P2.50mm_Horizontal -JST J2100 series connector, S06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 horizontal -0 -7 -6 -Connector_JST -JST_J2100_S08B-J21DK-GGXR_2x04_P2.50mm_Horizontal -JST J2100 series connector, S08B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 horizontal -0 -10 -8 -Connector_JST -JST_J2100_S10B-J21DK-GGXR_2x05_P2.50mm_Horizontal -JST J2100 series connector, S10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 horizontal -0 -12 -10 -Connector_JST -JST_J2100_S12B-J21DK-GGXR_2x06_P2.50mm_Horizontal -JST J2100 series connector, S12B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 horizontal -0 -14 -12 -Connector_JST -JST_J2100_S16B-J21DK-GGXR_2x08_P2.50mm_Horizontal -JST J2100 series connector, S16B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 horizontal -0 -18 -16 -Connector_JST -JST_J2100_S20B-J21DK-GGXR_2x10_P2.50mm_Horizontal -JST J2100 series connector, S20B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator -connector JST J2100 horizontal -0 -22 -20 -Connector_JST -JST_JWPF_B02B-JWPF-SK-R_1x02_P2.00mm_Vertical -JST JWPF series connector, B02B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator -connector JST JWPF side entry -0 -2 -2 -Connector_JST -JST_JWPF_B03B-JWPF-SK-R_1x03_P2.00mm_Vertical -JST JWPF series connector, B03B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator -connector JST JWPF side entry -0 -3 -3 -Connector_JST -JST_JWPF_B04B-JWPF-SK-R_1x04_P2.00mm_Vertical -JST JWPF series connector, B04B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator -connector JST JWPF side entry -0 -4 -4 -Connector_JST -JST_JWPF_B06B-JWPF-SK-R_2x03_P2.00mm_Vertical -JST JWPF series connector, B06B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator -connector JST JWPF side entry -0 -6 -6 -Connector_JST -JST_JWPF_B08B-JWPF-SK-R_2x04_P2.00mm_Vertical -JST JWPF series connector, B08B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator -connector JST JWPF side entry -0 -8 -8 -Connector_JST -JST_LEA_SM02B-LEASS-TF_1x02-1MP_P4.20mm_Horizontal -JST LEA series connector, SM02B-LEASS-TF (http://www.jst-mfg.com/product/pdf/eng/eLEA.pdf), generated with kicad-footprint-generator -connector JST LEA top entry -0 -4 -3 -Connector_JST -JST_NV_B02P-NV_1x02_P5.00mm_Vertical -JST NV series connector, B02P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator -connector JST NV side entry -0 -2 -2 -Connector_JST -JST_NV_B03P-NV_1x03_P5.00mm_Vertical -JST NV series connector, B03P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator -connector JST NV side entry -0 -3 -3 -Connector_JST -JST_NV_B04P-NV_1x04_P5.00mm_Vertical -JST NV series connector, B04P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator -connector JST NV side entry -0 -4 -4 -Connector_JST -JST_PHD_B8B-PHDSS_2x04_P2.00mm_Vertical -JST PHD series connector, B8B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -8 -8 -Connector_JST -JST_PHD_B10B-PHDSS_2x05_P2.00mm_Vertical -JST PHD series connector, B10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -10 -10 -Connector_JST -JST_PHD_B12B-PHDSS_2x06_P2.00mm_Vertical -JST PHD series connector, B12B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -12 -12 -Connector_JST -JST_PHD_B14B-PHDSS_2x07_P2.00mm_Vertical -JST PHD series connector, B14B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -14 -14 -Connector_JST -JST_PHD_B16B-PHDSS_2x08_P2.00mm_Vertical -JST PHD series connector, B16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -16 -16 -Connector_JST -JST_PHD_B18B-PHDSS_2x09_P2.00mm_Vertical -JST PHD series connector, B18B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -18 -18 -Connector_JST -JST_PHD_B20B-PHDSS_2x10_P2.00mm_Vertical -JST PHD series connector, B20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -20 -20 -Connector_JST -JST_PHD_B22B-PHDSS_2x11_P2.00mm_Vertical -JST PHD series connector, B22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -22 -22 -Connector_JST -JST_PHD_B24B-PHDSS_2x12_P2.00mm_Vertical -JST PHD series connector, B24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -24 -24 -Connector_JST -JST_PHD_B26B-PHDSS_2x13_P2.00mm_Vertical -JST PHD series connector, B26B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -26 -26 -Connector_JST -JST_PHD_B28B-PHDSS_2x14_P2.00mm_Vertical -JST PHD series connector, B28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -28 -28 -Connector_JST -JST_PHD_B30B-PHDSS_2x15_P2.00mm_Vertical -JST PHD series connector, B30B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -30 -30 -Connector_JST -JST_PHD_B32B-PHDSS_2x16_P2.00mm_Vertical -JST PHD series connector, B32B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -32 -32 -Connector_JST -JST_PHD_B34B-PHDSS_2x17_P2.00mm_Vertical -JST PHD series connector, B34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD vertical -0 -34 -34 -Connector_JST -JST_PHD_S8B-PHDSS_2x04_P2.00mm_Horizontal -JST PHD series connector, S8B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -8 -8 -Connector_JST -JST_PHD_S10B-PHDSS_2x05_P2.00mm_Horizontal -JST PHD series connector, S10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -10 -10 -Connector_JST -JST_PHD_S12B-PHDSS_2x06_P2.00mm_Horizontal -JST PHD series connector, S12B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -12 -12 -Connector_JST -JST_PHD_S14B-PHDSS_2x07_P2.00mm_Horizontal -JST PHD series connector, S14B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -14 -14 -Connector_JST -JST_PHD_S16B-PHDSS_2x08_P2.00mm_Horizontal -JST PHD series connector, S16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -16 -16 -Connector_JST -JST_PHD_S18B-PHDSS_2x09_P2.00mm_Horizontal -JST PHD series connector, S18B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -18 -18 -Connector_JST -JST_PHD_S20B-PHDSS_2x10_P2.00mm_Horizontal -JST PHD series connector, S20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -20 -20 -Connector_JST -JST_PHD_S22B-PHDSS_2x11_P2.00mm_Horizontal -JST PHD series connector, S22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -22 -22 -Connector_JST -JST_PHD_S24B-PHDSS_2x12_P2.00mm_Horizontal -JST PHD series connector, S24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -24 -24 -Connector_JST -JST_PHD_S26B-PHDSS_2x13_P2.00mm_Horizontal -JST PHD series connector, S26B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -26 -26 -Connector_JST -JST_PHD_S28B-PHDSS_2x14_P2.00mm_Horizontal -JST PHD series connector, S28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -28 -28 -Connector_JST -JST_PHD_S30B-PHDSS_2x15_P2.00mm_Horizontal -JST PHD series connector, S30B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -30 -30 -Connector_JST -JST_PHD_S32B-PHDSS_2x16_P2.00mm_Horizontal -JST PHD series connector, S32B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -32 -32 -Connector_JST -JST_PHD_S34B-PHDSS_2x17_P2.00mm_Horizontal -JST PHD series connector, S34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator -connector JST PHD horizontal -0 -34 -34 -Connector_JST -JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical -JST PH series connector, B2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -2 -2 -Connector_JST -JST_PH_B2B-PH-SM4-TB_1x02-1MP_P2.00mm_Vertical -JST PH series connector, B2B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -4 -3 -Connector_JST -JST_PH_B3B-PH-K_1x03_P2.00mm_Vertical -JST PH series connector, B3B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -3 -3 -Connector_JST -JST_PH_B3B-PH-SM4-TB_1x03-1MP_P2.00mm_Vertical -JST PH series connector, B3B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -5 -4 -Connector_JST -JST_PH_B4B-PH-K_1x04_P2.00mm_Vertical -JST PH series connector, B4B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -4 -4 -Connector_JST -JST_PH_B4B-PH-SM4-TB_1x04-1MP_P2.00mm_Vertical -JST PH series connector, B4B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -6 -5 -Connector_JST -JST_PH_B5B-PH-K_1x05_P2.00mm_Vertical -JST PH series connector, B5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -5 -5 -Connector_JST -JST_PH_B5B-PH-SM4-TB_1x05-1MP_P2.00mm_Vertical -JST PH series connector, B5B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -7 -6 -Connector_JST -JST_PH_B6B-PH-K_1x06_P2.00mm_Vertical -JST PH series connector, B6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -6 -6 -Connector_JST -JST_PH_B6B-PH-SM4-TB_1x06-1MP_P2.00mm_Vertical -JST PH series connector, B6B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -8 -7 -Connector_JST -JST_PH_B7B-PH-K_1x07_P2.00mm_Vertical -JST PH series connector, B7B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -7 -7 -Connector_JST -JST_PH_B7B-PH-SM4-TB_1x07-1MP_P2.00mm_Vertical -JST PH series connector, B7B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -9 -8 -Connector_JST -JST_PH_B8B-PH-K_1x08_P2.00mm_Vertical -JST PH series connector, B8B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -8 -8 -Connector_JST -JST_PH_B8B-PH-SM4-TB_1x08-1MP_P2.00mm_Vertical -JST PH series connector, B8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -10 -9 -Connector_JST -JST_PH_B9B-PH-K_1x09_P2.00mm_Vertical -JST PH series connector, B9B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -9 -9 -Connector_JST -JST_PH_B9B-PH-SM4-TB_1x09-1MP_P2.00mm_Vertical -JST PH series connector, B9B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -11 -10 -Connector_JST -JST_PH_B10B-PH-K_1x10_P2.00mm_Vertical -JST PH series connector, B10B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -10 -10 -Connector_JST -JST_PH_B10B-PH-SM4-TB_1x10-1MP_P2.00mm_Vertical -JST PH series connector, B10B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -12 -11 -Connector_JST -JST_PH_B11B-PH-K_1x11_P2.00mm_Vertical -JST PH series connector, B11B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -11 -11 -Connector_JST -JST_PH_B11B-PH-SM4-TB_1x11-1MP_P2.00mm_Vertical -JST PH series connector, B11B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -13 -12 -Connector_JST -JST_PH_B12B-PH-K_1x12_P2.00mm_Vertical -JST PH series connector, B12B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -12 -12 -Connector_JST -JST_PH_B12B-PH-SM4-TB_1x12-1MP_P2.00mm_Vertical -JST PH series connector, B12B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -14 -13 -Connector_JST -JST_PH_B13B-PH-K_1x13_P2.00mm_Vertical -JST PH series connector, B13B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -13 -13 -Connector_JST -JST_PH_B13B-PH-SM4-TB_1x13-1MP_P2.00mm_Vertical -JST PH series connector, B13B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -15 -14 -Connector_JST -JST_PH_B14B-PH-K_1x14_P2.00mm_Vertical -JST PH series connector, B14B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -14 -14 -Connector_JST -JST_PH_B14B-PH-SM4-TB_1x14-1MP_P2.00mm_Vertical -JST PH series connector, B14B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -16 -15 -Connector_JST -JST_PH_B15B-PH-K_1x15_P2.00mm_Vertical -JST PH series connector, B15B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -15 -15 -Connector_JST -JST_PH_B15B-PH-SM4-TB_1x15-1MP_P2.00mm_Vertical -JST PH series connector, B15B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -17 -16 -Connector_JST -JST_PH_B16B-PH-K_1x16_P2.00mm_Vertical -JST PH series connector, B16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -16 -16 -Connector_JST -JST_PH_B16B-PH-SM4-TB_1x16-1MP_P2.00mm_Vertical -JST PH series connector, B16B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH side entry -0 -18 -17 -Connector_JST -JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal -JST PH series connector, S2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -2 -2 -Connector_JST -JST_PH_S2B-PH-SM4-TB_1x02-1MP_P2.00mm_Horizontal -JST PH series connector, S2B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -4 -3 -Connector_JST -JST_PH_S3B-PH-K_1x03_P2.00mm_Horizontal -JST PH series connector, S3B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -3 -3 -Connector_JST -JST_PH_S3B-PH-SM4-TB_1x03-1MP_P2.00mm_Horizontal -JST PH series connector, S3B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -5 -4 -Connector_JST -JST_PH_S4B-PH-K_1x04_P2.00mm_Horizontal -JST PH series connector, S4B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -4 -4 -Connector_JST -JST_PH_S4B-PH-SM4-TB_1x04-1MP_P2.00mm_Horizontal -JST PH series connector, S4B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -6 -5 -Connector_JST -JST_PH_S5B-PH-K_1x05_P2.00mm_Horizontal -JST PH series connector, S5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -5 -5 -Connector_JST -JST_PH_S5B-PH-SM4-TB_1x05-1MP_P2.00mm_Horizontal -JST PH series connector, S5B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -7 -6 -Connector_JST -JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal -JST PH series connector, S6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -6 -6 -Connector_JST -JST_PH_S6B-PH-SM4-TB_1x06-1MP_P2.00mm_Horizontal -JST PH series connector, S6B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -8 -7 -Connector_JST -JST_PH_S7B-PH-K_1x07_P2.00mm_Horizontal -JST PH series connector, S7B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -7 -7 -Connector_JST -JST_PH_S7B-PH-SM4-TB_1x07-1MP_P2.00mm_Horizontal -JST PH series connector, S7B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -9 -8 -Connector_JST -JST_PH_S8B-PH-K_1x08_P2.00mm_Horizontal -JST PH series connector, S8B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -8 -8 -Connector_JST -JST_PH_S8B-PH-SM4-TB_1x08-1MP_P2.00mm_Horizontal -JST PH series connector, S8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -10 -9 -Connector_JST -JST_PH_S9B-PH-K_1x09_P2.00mm_Horizontal -JST PH series connector, S9B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -9 -9 -Connector_JST -JST_PH_S9B-PH-SM4-TB_1x09-1MP_P2.00mm_Horizontal -JST PH series connector, S9B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -11 -10 -Connector_JST -JST_PH_S10B-PH-K_1x10_P2.00mm_Horizontal -JST PH series connector, S10B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -10 -10 -Connector_JST -JST_PH_S10B-PH-SM4-TB_1x10-1MP_P2.00mm_Horizontal -JST PH series connector, S10B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -12 -11 -Connector_JST -JST_PH_S11B-PH-K_1x11_P2.00mm_Horizontal -JST PH series connector, S11B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -11 -11 -Connector_JST -JST_PH_S11B-PH-SM4-TB_1x11-1MP_P2.00mm_Horizontal -JST PH series connector, S11B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -13 -12 -Connector_JST -JST_PH_S12B-PH-K_1x12_P2.00mm_Horizontal -JST PH series connector, S12B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -12 -12 -Connector_JST -JST_PH_S12B-PH-SM4-TB_1x12-1MP_P2.00mm_Horizontal -JST PH series connector, S12B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -14 -13 -Connector_JST -JST_PH_S13B-PH-K_1x13_P2.00mm_Horizontal -JST PH series connector, S13B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -13 -13 -Connector_JST -JST_PH_S13B-PH-SM4-TB_1x13-1MP_P2.00mm_Horizontal -JST PH series connector, S13B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -15 -14 -Connector_JST -JST_PH_S14B-PH-K_1x14_P2.00mm_Horizontal -JST PH series connector, S14B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -14 -14 -Connector_JST -JST_PH_S14B-PH-SM4-TB_1x14-1MP_P2.00mm_Horizontal -JST PH series connector, S14B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -16 -15 -Connector_JST -JST_PH_S15B-PH-K_1x15_P2.00mm_Horizontal -JST PH series connector, S15B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -15 -15 -Connector_JST -JST_PH_S15B-PH-SM4-TB_1x15-1MP_P2.00mm_Horizontal -JST PH series connector, S15B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -17 -16 -Connector_JST -JST_PH_S16B-PH-K_1x16_P2.00mm_Horizontal -JST PH series connector, S16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator -connector JST PH top entry -0 -16 -16 -Connector_JST -JST_PUD_B08B-PUDSS_2x04_P2.00mm_Vertical -JST PUD series connector, B08B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -8 -8 -Connector_JST -JST_PUD_B10B-PUDSS_2x05_P2.00mm_Vertical -JST PUD series connector, B10B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -10 -10 -Connector_JST -JST_PUD_B12B-PUDSS_2x06_P2.00mm_Vertical -JST PUD series connector, B12B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -12 -12 -Connector_JST -JST_PUD_B14B-PUDSS_2x07_P2.00mm_Vertical -JST PUD series connector, B14B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -14 -14 -Connector_JST -JST_PUD_B16B-PUDSS_2x08_P2.00mm_Vertical -JST PUD series connector, B16B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -16 -16 -Connector_JST -JST_PUD_B18B-PUDSS_2x09_P2.00mm_Vertical -JST PUD series connector, B18B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -18 -18 -Connector_JST -JST_PUD_B20B-PUDSS_2x10_P2.00mm_Vertical -JST PUD series connector, B20B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -20 -20 -Connector_JST -JST_PUD_B22B-PUDSS_2x11_P2.00mm_Vertical -JST PUD series connector, B22B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -22 -22 -Connector_JST -JST_PUD_B24B-PUDSS_2x12_P2.00mm_Vertical -JST PUD series connector, B24B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -24 -24 -Connector_JST -JST_PUD_B26B-PUDSS_2x13_P2.00mm_Vertical -JST PUD series connector, B26B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -26 -26 -Connector_JST -JST_PUD_B28B-PUDSS_2x14_P2.00mm_Vertical -JST PUD series connector, B28B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -28 -28 -Connector_JST -JST_PUD_B30B-PUDSS_2x15_P2.00mm_Vertical -JST PUD series connector, B30B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -30 -30 -Connector_JST -JST_PUD_B32B-PUDSS_2x16_P2.00mm_Vertical -JST PUD series connector, B32B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -32 -32 -Connector_JST -JST_PUD_B34B-PUDSS_2x17_P2.00mm_Vertical -JST PUD series connector, B34B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -34 -34 -Connector_JST -JST_PUD_B36B-PUDSS_2x18_P2.00mm_Vertical -JST PUD series connector, B36B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -36 -36 -Connector_JST -JST_PUD_B38B-PUDSS_2x19_P2.00mm_Vertical -JST PUD series connector, B38B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -38 -38 -Connector_JST -JST_PUD_B40B-PUDSS_2x20_P2.00mm_Vertical -JST PUD series connector, B40B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD side entry -0 -40 -40 -Connector_JST -JST_PUD_S08B-PUDSS-1_2x04_P2.00mm_Horizontal -JST PUD series connector, S08B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -8 -8 -Connector_JST -JST_PUD_S10B-PUDSS-1_2x05_P2.00mm_Horizontal -JST PUD series connector, S10B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -10 -10 -Connector_JST -JST_PUD_S12B-PUDSS-1_2x06_P2.00mm_Horizontal -JST PUD series connector, S12B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -12 -12 -Connector_JST -JST_PUD_S14B-PUDSS-1_2x07_P2.00mm_Horizontal -JST PUD series connector, S14B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -14 -14 -Connector_JST -JST_PUD_S16B-PUDSS-1_2x08_P2.00mm_Horizontal -JST PUD series connector, S16B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -16 -16 -Connector_JST -JST_PUD_S18B-PUDSS-1_2x09_P2.00mm_Horizontal -JST PUD series connector, S18B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -18 -18 -Connector_JST -JST_PUD_S20B-PUDSS-1_2x10_P2.00mm_Horizontal -JST PUD series connector, S20B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -20 -20 -Connector_JST -JST_PUD_S22B-PUDSS-1_2x11_P2.00mm_Horizontal -JST PUD series connector, S22B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -22 -22 -Connector_JST -JST_PUD_S24B-PUDSS-1_2x12_P2.00mm_Horizontal -JST PUD series connector, S24B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -24 -24 -Connector_JST -JST_PUD_S26B-PUDSS-1_2x13_P2.00mm_Horizontal -JST PUD series connector, S26B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -26 -26 -Connector_JST -JST_PUD_S28B-PUDSS-1_2x14_P2.00mm_Horizontal -JST PUD series connector, S28B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -28 -28 -Connector_JST -JST_PUD_S30B-PUDSS-1_2x15_P2.00mm_Horizontal -JST PUD series connector, S30B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -30 -30 -Connector_JST -JST_PUD_S32B-PUDSS-1_2x16_P2.00mm_Horizontal -JST PUD series connector, S32B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -32 -32 -Connector_JST -JST_PUD_S34B-PUDSS-1_2x17_P2.00mm_Horizontal -JST PUD series connector, S34B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -34 -34 -Connector_JST -JST_PUD_S36B-PUDSS-1_2x18_P2.00mm_Horizontal -JST PUD series connector, S36B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -36 -36 -Connector_JST -JST_PUD_S38B-PUDSS-1_2x19_P2.00mm_Horizontal -JST PUD series connector, S38B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -38 -38 -Connector_JST -JST_PUD_S40B-PUDSS-1_2x20_P2.00mm_Horizontal -JST PUD series connector, S40B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator -connector JST PUD top entry -0 -40 -40 -Connector_JST -JST_SFH_SM02B-SFHRS-TF_1x02-1MP_P4.20mm_Horizontal -JST SFH series connector, SM02B-SFHRS-TF (http://www.jst-mfg.com/product/pdf/eng/eSFH.pdf), generated with kicad-footprint-generator -connector JST SFH horizontal -0 -4 -3 -Connector_JST -JST_SHL_SM02B-SHLS-TF_1x02-1MP_P1.00mm_Horizontal -JST SHL series connector, SM02B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -4 -3 -Connector_JST -JST_SHL_SM05B-SHLS-TF_1x05-1MP_P1.00mm_Horizontal -JST SHL series connector, SM05B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -7 -6 -Connector_JST -JST_SHL_SM06B-SHLS-TF_1x06-1MP_P1.00mm_Horizontal -JST SHL series connector, SM06B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -8 -7 -Connector_JST -JST_SHL_SM07B-SHLS-TF_1x07-1MP_P1.00mm_Horizontal -JST SHL series connector, SM07B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -9 -8 -Connector_JST -JST_SHL_SM08B-SHLS-TF_1x08-1MP_P1.00mm_Horizontal -JST SHL series connector, SM08B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -10 -9 -Connector_JST -JST_SHL_SM10B-SHLS-TF_1x10-1MP_P1.00mm_Horizontal -JST SHL series connector, SM10B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -12 -11 -Connector_JST -JST_SHL_SM11B-SHLS-TF_1x11-1MP_P1.00mm_Horizontal -JST SHL series connector, SM11B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -13 -12 -Connector_JST -JST_SHL_SM12B-SHLS-TF_1x12-1MP_P1.00mm_Horizontal -JST SHL series connector, SM12B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -14 -13 -Connector_JST -JST_SHL_SM14B-SHLS-TF_1x14-1MP_P1.00mm_Horizontal -JST SHL series connector, SM14B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -16 -15 -Connector_JST -JST_SHL_SM16B-SHLS-TF_1x16-1MP_P1.00mm_Horizontal -JST SHL series connector, SM16B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -18 -17 -Connector_JST -JST_SHL_SM20B-SHLS-TF_1x20-1MP_P1.00mm_Horizontal -JST SHL series connector, SM20B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -22 -21 -Connector_JST -JST_SHL_SM22B-SHLS-TF_1x22-1MP_P1.00mm_Horizontal -JST SHL series connector, SM22B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -24 -23 -Connector_JST -JST_SHL_SM26B-SHLS-TF_1x26-1MP_P1.00mm_Horizontal -JST SHL series connector, SM26B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -28 -27 -Connector_JST -JST_SHL_SM30B-SHLS-TF_1x30-1MP_P1.00mm_Horizontal -JST SHL series connector, SM30B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator -connector JST SHL top entry -0 -32 -31 -Connector_JST -JST_SH_BM02B-SRSS-TB_1x02-1MP_P1.00mm_Vertical -JST SH series connector, BM02B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -4 -3 -Connector_JST -JST_SH_BM03B-SRSS-TB_1x03-1MP_P1.00mm_Vertical -JST SH series connector, BM03B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -5 -4 -Connector_JST -JST_SH_BM04B-SRSS-TB_1x04-1MP_P1.00mm_Vertical -JST SH series connector, BM04B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -6 -5 -Connector_JST -JST_SH_BM05B-SRSS-TB_1x05-1MP_P1.00mm_Vertical -JST SH series connector, BM05B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -7 -6 -Connector_JST -JST_SH_BM06B-SRSS-TB_1x06-1MP_P1.00mm_Vertical -JST SH series connector, BM06B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -8 -7 -Connector_JST -JST_SH_BM07B-SRSS-TB_1x07-1MP_P1.00mm_Vertical -JST SH series connector, BM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -9 -8 -Connector_JST -JST_SH_BM08B-SRSS-TB_1x08-1MP_P1.00mm_Vertical -JST SH series connector, BM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -10 -9 -Connector_JST -JST_SH_BM09B-SRSS-TB_1x09-1MP_P1.00mm_Vertical -JST SH series connector, BM09B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -11 -10 -Connector_JST -JST_SH_BM10B-SRSS-TB_1x10-1MP_P1.00mm_Vertical -JST SH series connector, BM10B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -12 -11 -Connector_JST -JST_SH_BM11B-SRSS-TB_1x11-1MP_P1.00mm_Vertical -JST SH series connector, BM11B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -13 -12 -Connector_JST -JST_SH_BM12B-SRSS-TB_1x12-1MP_P1.00mm_Vertical -JST SH series connector, BM12B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -14 -13 -Connector_JST -JST_SH_BM13B-SRSS-TB_1x13-1MP_P1.00mm_Vertical -JST SH series connector, BM13B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -15 -14 -Connector_JST -JST_SH_BM14B-SRSS-TB_1x14-1MP_P1.00mm_Vertical -JST SH series connector, BM14B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -16 -15 -Connector_JST -JST_SH_BM15B-SRSS-TB_1x15-1MP_P1.00mm_Vertical -JST SH series connector, BM15B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH side entry -0 -17 -16 -Connector_JST -JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal -JST SH series connector, SM02B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -4 -3 -Connector_JST -JST_SH_SM03B-SRSS-TB_1x03-1MP_P1.00mm_Horizontal -JST SH series connector, SM03B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -5 -4 -Connector_JST -JST_SH_SM04B-SRSS-TB_1x04-1MP_P1.00mm_Horizontal -JST SH series connector, SM04B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -6 -5 -Connector_JST -JST_SH_SM05B-SRSS-TB_1x05-1MP_P1.00mm_Horizontal -JST SH series connector, SM05B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -7 -6 -Connector_JST -JST_SH_SM06B-SRSS-TB_1x06-1MP_P1.00mm_Horizontal -JST SH series connector, SM06B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -8 -7 -Connector_JST -JST_SH_SM07B-SRSS-TB_1x07-1MP_P1.00mm_Horizontal -JST SH series connector, SM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -9 -8 -Connector_JST -JST_SH_SM08B-SRSS-TB_1x08-1MP_P1.00mm_Horizontal -JST SH series connector, SM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -10 -9 -Connector_JST -JST_SH_SM09B-SRSS-TB_1x09-1MP_P1.00mm_Horizontal -JST SH series connector, SM09B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -11 -10 -Connector_JST -JST_SH_SM10B-SRSS-TB_1x10-1MP_P1.00mm_Horizontal -JST SH series connector, SM10B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -12 -11 -Connector_JST -JST_SH_SM11B-SRSS-TB_1x11-1MP_P1.00mm_Horizontal -JST SH series connector, SM11B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -13 -12 -Connector_JST -JST_SH_SM12B-SRSS-TB_1x12-1MP_P1.00mm_Horizontal -JST SH series connector, SM12B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -14 -13 -Connector_JST -JST_SH_SM13B-SRSS-TB_1x13-1MP_P1.00mm_Horizontal -JST SH series connector, SM13B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -15 -14 -Connector_JST -JST_SH_SM14B-SRSS-TB_1x14-1MP_P1.00mm_Horizontal -JST SH series connector, SM14B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -16 -15 -Connector_JST -JST_SH_SM15B-SRSS-TB_1x15-1MP_P1.00mm_Horizontal -JST SH series connector, SM15B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -17 -16 -Connector_JST -JST_SH_SM20B-SRSS-TB_1x20-1MP_P1.00mm_Horizontal -JST SH series connector, SM20B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator -connector JST SH top entry -0 -22 -21 -Connector_JST -JST_SUR_BM02B-SURS-TF_1x02-1MP_P0.80mm_Vertical -JST SUR series connector, BM02B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -4 -3 -Connector_JST -JST_SUR_BM03B-SURS-TF_1x03-1MP_P0.80mm_Vertical -JST SUR series connector, BM03B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -5 -4 -Connector_JST -JST_SUR_BM04B-SURS-TF_1x04-1MP_P0.80mm_Vertical -JST SUR series connector, BM04B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -6 -5 -Connector_JST -JST_SUR_BM05B-SURS-TF_1x05-1MP_P0.80mm_Vertical -JST SUR series connector, BM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -7 -6 -Connector_JST -JST_SUR_BM06B-SURS-TF_1x06-1MP_P0.80mm_Vertical -JST SUR series connector, BM06B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -8 -7 -Connector_JST -JST_SUR_BM08B-SURS-TF_1x08-1MP_P0.80mm_Vertical -JST SUR series connector, BM08B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -10 -9 -Connector_JST -JST_SUR_BM10B-SURS-TF_1x10-1MP_P0.80mm_Vertical -JST SUR series connector, BM10B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -12 -11 -Connector_JST -JST_SUR_BM12B-SURS-TF_1x12-1MP_P0.80mm_Vertical -JST SUR series connector, BM12B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -14 -13 -Connector_JST -JST_SUR_BM14B-SURS-TF_1x14-1MP_P0.80mm_Vertical -JST SUR series connector, BM14B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -16 -15 -Connector_JST -JST_SUR_BM15B-SURS-TF_1x15-1MP_P0.80mm_Vertical -JST SUR series connector, BM15B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -17 -16 -Connector_JST -JST_SUR_BM16B-SURS-TF_1x16-1MP_P0.80mm_Vertical -JST SUR series connector, BM16B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -18 -17 -Connector_JST -JST_SUR_BM17B-SURS-TF_1x17-1MP_P0.80mm_Vertical -JST SUR series connector, BM17B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -19 -18 -Connector_JST -JST_SUR_BM20B-SURS-TF_1x20-1MP_P0.80mm_Vertical -JST SUR series connector, BM20B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR side entry -0 -22 -21 -Connector_JST -JST_SUR_SM02B-SURS-TF_1x02-1MP_P0.80mm_Horizontal -JST SUR series connector, SM02B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -4 -3 -Connector_JST -JST_SUR_SM03B-SURS-TF_1x03-1MP_P0.80mm_Horizontal -JST SUR series connector, SM03B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -5 -4 -Connector_JST -JST_SUR_SM04B-SURS-TF_1x04-1MP_P0.80mm_Horizontal -JST SUR series connector, SM04B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -6 -5 -Connector_JST -JST_SUR_SM05B-SURS-TF_1x05-1MP_P0.80mm_Horizontal -JST SUR series connector, SM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -7 -6 -Connector_JST -JST_SUR_SM06B-SURS-TF_1x06-1MP_P0.80mm_Horizontal -JST SUR series connector, SM06B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -8 -7 -Connector_JST -JST_SUR_SM08B-SURS-TF_1x08-1MP_P0.80mm_Horizontal -JST SUR series connector, SM08B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -10 -9 -Connector_JST -JST_SUR_SM10B-SURS-TF_1x10-1MP_P0.80mm_Horizontal -JST SUR series connector, SM10B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -12 -11 -Connector_JST -JST_SUR_SM12B-SURS-TF_1x12-1MP_P0.80mm_Horizontal -JST SUR series connector, SM12B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -14 -13 -Connector_JST -JST_SUR_SM14B-SURS-TF_1x14-1MP_P0.80mm_Horizontal -JST SUR series connector, SM14B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -16 -15 -Connector_JST -JST_SUR_SM15B-SURS-TF_1x15-1MP_P0.80mm_Horizontal -JST SUR series connector, SM15B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -17 -16 -Connector_JST -JST_SUR_SM16B-SURS-TF_1x16-1MP_P0.80mm_Horizontal -JST SUR series connector, SM16B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -18 -17 -Connector_JST -JST_SUR_SM17B-SURS-TF_1x17-1MP_P0.80mm_Horizontal -JST SUR series connector, SM17B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -19 -18 -Connector_JST -JST_SUR_SM20B-SURS-TF_1x20-1MP_P0.80mm_Horizontal -JST SUR series connector, SM20B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -22 -21 -Connector_JST -JST_SUR_SM22B-SURS-TF_1x22-1MP_P0.80mm_Horizontal -JST SUR series connector, SM22B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator -connector JST SUR top entry -0 -24 -23 -Connector_JST -JST_VH_B2P-VH-B_1x02_P3.96mm_Vertical -JST VH PBT series connector, B2P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -2 -2 -Connector_JST -JST_VH_B2P-VH-FB-B_1x02_P3.96mm_Vertical -JST VH series connector, B2P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -2 -2 -Connector_JST -JST_VH_B2P-VH_1x02_P3.96mm_Vertical -JST VH series connector, B2P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -2 -2 -Connector_JST -JST_VH_B2P3-VH_1x02_P7.92mm_Vertical -JST VH series connector, B2P3-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -2 -2 -Connector_JST -JST_VH_B2PS-VH_1x02_P3.96mm_Horizontal -JST VH series connector, B2PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -2 -2 -Connector_JST -JST_VH_B3P-VH-B_1x03_P3.96mm_Vertical -JST VH PBT series connector, B3P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -3 -3 -Connector_JST -JST_VH_B3P-VH-FB-B_1x03_P3.96mm_Vertical -JST VH series connector, B3P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -3 -3 -Connector_JST -JST_VH_B3P-VH_1x03_P3.96mm_Vertical -JST VH series connector, B3P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -3 -3 -Connector_JST -JST_VH_B3PS-VH_1x03_P3.96mm_Horizontal -JST VH series connector, B3PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -3 -3 -Connector_JST -JST_VH_B4P-VH-B_1x04_P3.96mm_Vertical -JST VH PBT series connector, B4P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -4 -4 -Connector_JST -JST_VH_B4P-VH-FB-B_1x04_P3.96mm_Vertical -JST VH series connector, B4P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -4 -4 -Connector_JST -JST_VH_B4P-VH_1x04_P3.96mm_Vertical -JST VH series connector, B4P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -4 -4 -Connector_JST -JST_VH_B4PS-VH_1x04_P3.96mm_Horizontal -JST VH series connector, B4PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -4 -4 -Connector_JST -JST_VH_B5P-VH-B_1x05_P3.96mm_Vertical -JST VH PBT series connector, B5P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -5 -5 -Connector_JST -JST_VH_B5P-VH-FB-B_1x05_P3.96mm_Vertical -JST VH series connector, B5P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -5 -5 -Connector_JST -JST_VH_B5P-VH_1x05_P3.96mm_Vertical -JST VH series connector, B5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -5 -5 -Connector_JST -JST_VH_B5PS-VH_1x05_P3.96mm_Horizontal -JST VH series connector, B5PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -5 -5 -Connector_JST -JST_VH_B6P-VH-B_1x06_P3.96mm_Vertical -JST VH PBT series connector, B6P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -6 -6 -Connector_JST -JST_VH_B6P-VH-FB-B_1x06_P3.96mm_Vertical -JST VH series connector, B6P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -6 -6 -Connector_JST -JST_VH_B6P-VH_1x06_P3.96mm_Vertical -JST VH series connector, B6P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -6 -6 -Connector_JST -JST_VH_B6PS-VH_1x06_P3.96mm_Horizontal -JST VH series connector, B6PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -6 -6 -Connector_JST -JST_VH_B7P-VH-B_1x07_P3.96mm_Vertical -JST VH PBT series connector, B7P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -7 -7 -Connector_JST -JST_VH_B7P-VH-FB-B_1x07_P3.96mm_Vertical -JST VH series connector, B7P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -7 -7 -Connector_JST -JST_VH_B7P-VH_1x07_P3.96mm_Vertical -JST VH series connector, B7P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -7 -7 -Connector_JST -JST_VH_B7PS-VH_1x07_P3.96mm_Horizontal -JST VH series connector, B7PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -7 -7 -Connector_JST -JST_VH_B8P-VH-B_1x08_P3.96mm_Vertical -JST VH PBT series connector, B8P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -8 -8 -Connector_JST -JST_VH_B8P-VH-FB-B_1x08_P3.96mm_Vertical -JST VH series connector, B8P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -8 -8 -Connector_JST -JST_VH_B8P-VH_1x08_P3.96mm_Vertical -JST VH series connector, B8P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -8 -8 -Connector_JST -JST_VH_B8PS-VH_1x08_P3.96mm_Horizontal -JST VH series connector, B8PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -8 -8 -Connector_JST -JST_VH_B9P-VH-B_1x09_P3.96mm_Vertical -JST VH PBT series connector, B9P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -9 -9 -Connector_JST -JST_VH_B9P-VH-FB-B_1x09_P3.96mm_Vertical -JST VH series connector, B9P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -9 -9 -Connector_JST -JST_VH_B9P-VH_1x09_P3.96mm_Vertical -JST VH series connector, B9P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -9 -9 -Connector_JST -JST_VH_B9PS-VH_1x09_P3.96mm_Horizontal -JST VH series connector, B9PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -9 -9 -Connector_JST -JST_VH_B10P-VH-B_1x10_P3.96mm_Vertical -JST VH PBT series connector, B10P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -10 -10 -Connector_JST -JST_VH_B10P-VH-FB-B_1x10_P3.96mm_Vertical -JST VH series connector, B10P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH side entry -0 -10 -10 -Connector_JST -JST_VH_B10P-VH_1x10_P3.96mm_Vertical -JST VH series connector, B10P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -10 -10 -Connector_JST -JST_VH_B10PS-VH_1x10_P3.96mm_Horizontal -JST VH series connector, B10PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -10 -10 -Connector_JST -JST_VH_B11P-VH-B_1x11_P3.96mm_Vertical -JST VH PBT series connector, B11P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH vertical -0 -11 -11 -Connector_JST -JST_VH_S2P-VH_1x02_P3.96mm_Horizontal -JST VH series connector, S2P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -2 -2 -Connector_JST -JST_VH_S3P-VH_1x03_P3.96mm_Horizontal -JST VH series connector, S3P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -3 -3 -Connector_JST -JST_VH_S4P-VH_1x04_P3.96mm_Horizontal -JST VH series connector, S4P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -4 -4 -Connector_JST -JST_VH_S5P-VH_1x05_P3.96mm_Horizontal -JST VH series connector, S5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -5 -5 -Connector_JST -JST_VH_S6P-VH_1x06_P3.96mm_Horizontal -JST VH series connector, S6P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -6 -6 -Connector_JST -JST_VH_S7P-VH_1x07_P3.96mm_Horizontal -JST VH series connector, S7P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator -connector JST VH top entry -0 -7 -7 -Connector_JST -JST_XAG_SM05B-XAGKS-BN-TB_1x05-1MP_P2.50mm_Horizontal -JST XAG series connector, SM05B-XAGKS-BN-TB (http://www.jst-mfg.com/product/pdf/eng/eXAG.pdf), generated with kicad-footprint-generator -connector JST XAG top entry -0 -7 -6 -Connector_JST -JST_XH_B1B-XH-AM_1x01_P2.50mm_Vertical -JST XH series connector, B1B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -1 -1 -Connector_JST -JST_XH_B2B-XH-AM_1x02_P2.50mm_Vertical -JST XH series connector, B2B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -2 -2 -Connector_JST -JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical -JST XH series connector, B2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -2 -2 -Connector_JST -JST_XH_B3B-XH-AM_1x03_P2.50mm_Vertical -JST XH series connector, B3B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -3 -3 -Connector_JST -JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical -JST XH series connector, B3B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -3 -3 -Connector_JST -JST_XH_B4B-XH-AM_1x04_P2.50mm_Vertical -JST XH series connector, B4B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -4 -4 -Connector_JST -JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical -JST XH series connector, B4B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -4 -4 -Connector_JST -JST_XH_B5B-XH-AM_1x05_P2.50mm_Vertical -JST XH series connector, B5B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -5 -5 -Connector_JST -JST_XH_B5B-XH-A_1x05_P2.50mm_Vertical -JST XH series connector, B5B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -5 -5 -Connector_JST -JST_XH_B6B-XH-AM_1x06_P2.50mm_Vertical -JST XH series connector, B6B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -6 -6 -Connector_JST -JST_XH_B6B-XH-A_1x06_P2.50mm_Vertical -JST XH series connector, B6B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -6 -6 -Connector_JST -JST_XH_B7B-XH-AM_1x07_P2.50mm_Vertical -JST XH series connector, B7B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -7 -7 -Connector_JST -JST_XH_B7B-XH-A_1x07_P2.50mm_Vertical -JST XH series connector, B7B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -7 -7 -Connector_JST -JST_XH_B8B-XH-AM_1x08_P2.50mm_Vertical -JST XH series connector, B8B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -8 -8 -Connector_JST -JST_XH_B8B-XH-A_1x08_P2.50mm_Vertical -JST XH series connector, B8B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -8 -8 -Connector_JST -JST_XH_B9B-XH-AM_1x09_P2.50mm_Vertical -JST XH series connector, B9B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical boss -0 -9 -9 -Connector_JST -JST_XH_B9B-XH-A_1x09_P2.50mm_Vertical -JST XH series connector, B9B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH vertical -0 -9 -9 -Connector_JST -JST_XH_B10B-XH-AM_1x10_P2.50mm_Vertical -JST XH series connector, B10B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry boss -0 -10 -10 -Connector_JST -JST_XH_B10B-XH-A_1x10_P2.50mm_Vertical -JST XH series connector, B10B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -10 -10 -Connector_JST -JST_XH_B11B-XH-A_1x11_P2.50mm_Vertical -JST XH series connector, B11B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -11 -11 -Connector_JST -JST_XH_B12B-XH-AM_1x12_P2.50mm_Vertical -JST XH series connector, B12B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry boss -0 -12 -12 -Connector_JST -JST_XH_B12B-XH-A_1x12_P2.50mm_Vertical -JST XH series connector, B12B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -12 -12 -Connector_JST -JST_XH_B13B-XH-A_1x13_P2.50mm_Vertical -JST XH series connector, B13B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -13 -13 -Connector_JST -JST_XH_B14B-XH-A_1x14_P2.50mm_Vertical -JST XH series connector, B14B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -14 -14 -Connector_JST -JST_XH_B15B-XH-A_1x15_P2.50mm_Vertical -JST XH series connector, B15B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -15 -15 -Connector_JST -JST_XH_B16B-XH-A_1x16_P2.50mm_Vertical -JST XH series connector, B16B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -16 -16 -Connector_JST -JST_XH_B20B-XH-A_1x20_P2.50mm_Vertical -JST XH series connector, B20B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH side entry -0 -20 -20 -Connector_JST -JST_XH_S2B-XH-A-1_1x02_P2.50mm_Horizontal -JST XH series connector, S2B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -2 -2 -Connector_JST -JST_XH_S2B-XH-A_1x02_P2.50mm_Horizontal -JST XH series connector, S2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -2 -2 -Connector_JST -JST_XH_S3B-XH-A-1_1x03_P2.50mm_Horizontal -JST XH series connector, S3B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -3 -3 -Connector_JST -JST_XH_S3B-XH-A_1x03_P2.50mm_Horizontal -JST XH series connector, S3B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -3 -3 -Connector_JST -JST_XH_S4B-XH-A-1_1x04_P2.50mm_Horizontal -JST XH series connector, S4B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -4 -4 -Connector_JST -JST_XH_S4B-XH-A_1x04_P2.50mm_Horizontal -JST XH series connector, S4B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -4 -4 -Connector_JST -JST_XH_S5B-XH-A-1_1x05_P2.50mm_Horizontal -JST XH series connector, S5B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -5 -5 -Connector_JST -JST_XH_S5B-XH-A_1x05_P2.50mm_Horizontal -JST XH series connector, S5B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -5 -5 -Connector_JST -JST_XH_S6B-XH-A-1_1x06_P2.50mm_Horizontal -JST XH series connector, S6B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -6 -6 -Connector_JST -JST_XH_S6B-XH-A_1x06_P2.50mm_Horizontal -JST XH series connector, S6B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -6 -6 -Connector_JST -JST_XH_S7B-XH-A-1_1x07_P2.50mm_Horizontal -JST XH series connector, S7B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -7 -7 -Connector_JST -JST_XH_S7B-XH-A_1x07_P2.50mm_Horizontal -JST XH series connector, S7B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -7 -7 -Connector_JST -JST_XH_S8B-XH-A-1_1x08_P2.50mm_Horizontal -JST XH series connector, S8B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -8 -8 -Connector_JST -JST_XH_S8B-XH-A_1x08_P2.50mm_Horizontal -JST XH series connector, S8B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -8 -8 -Connector_JST -JST_XH_S9B-XH-A-1_1x09_P2.50mm_Horizontal -JST XH series connector, S9B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -9 -9 -Connector_JST -JST_XH_S9B-XH-A_1x09_P2.50mm_Horizontal -JST XH series connector, S9B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH horizontal -0 -9 -9 -Connector_JST -JST_XH_S10B-XH-A-1_1x10_P2.50mm_Horizontal -JST XH series connector, S10B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -10 -10 -Connector_JST -JST_XH_S10B-XH-A_1x10_P2.50mm_Horizontal -JST XH series connector, S10B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -10 -10 -Connector_JST -JST_XH_S11B-XH-A-1_1x11_P2.50mm_Horizontal -JST XH series connector, S11B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -11 -11 -Connector_JST -JST_XH_S11B-XH-A_1x11_P2.50mm_Horizontal -JST XH series connector, S11B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -11 -11 -Connector_JST -JST_XH_S12B-XH-A-1_1x12_P2.50mm_Horizontal -JST XH series connector, S12B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -12 -12 -Connector_JST -JST_XH_S12B-XH-A_1x12_P2.50mm_Horizontal -JST XH series connector, S12B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -12 -12 -Connector_JST -JST_XH_S13B-XH-A-1_1x13_P2.50mm_Horizontal -JST XH series connector, S13B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -13 -13 -Connector_JST -JST_XH_S13B-XH-A_1x13_P2.50mm_Horizontal -JST XH series connector, S13B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -13 -13 -Connector_JST -JST_XH_S14B-XH-A-1_1x14_P2.50mm_Horizontal -JST XH series connector, S14B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -14 -14 -Connector_JST -JST_XH_S14B-XH-A_1x14_P2.50mm_Horizontal -JST XH series connector, S14B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -14 -14 -Connector_JST -JST_XH_S15B-XH-A-1_1x15_P2.50mm_Horizontal -JST XH series connector, S15B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -15 -15 -Connector_JST -JST_XH_S15B-XH-A_1x15_P2.50mm_Horizontal -JST XH series connector, S15B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -15 -15 -Connector_JST -JST_XH_S16B-XH-A_1x16_P2.50mm_Horizontal -JST XH series connector, S16B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator -connector JST XH top entry -0 -16 -16 -Connector_JST -JST_ZE_B02B-ZESK-1D_1x02_P1.50mm_Vertical -JST ZE series connector, B02B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -2 -2 -Connector_JST -JST_ZE_B03B-ZESK-1D_1x03_P1.50mm_Vertical -JST ZE series connector, B03B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -3 -3 -Connector_JST -JST_ZE_B03B-ZESK-D_1x03_P1.50mm_Vertical -JST ZE series connector, B03B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -3 -3 -Connector_JST -JST_ZE_B04B-ZESK-1D_1x04_P1.50mm_Vertical -JST ZE series connector, B04B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -4 -4 -Connector_JST -JST_ZE_B04B-ZESK-D_1x04_P1.50mm_Vertical -JST ZE series connector, B04B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -4 -4 -Connector_JST -JST_ZE_B05B-ZESK-1D_1x05_P1.50mm_Vertical -JST ZE series connector, B05B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -5 -5 -Connector_JST -JST_ZE_B05B-ZESK-D_1x05_P1.50mm_Vertical -JST ZE series connector, B05B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -5 -5 -Connector_JST -JST_ZE_B06B-ZESK-1D_1x06_P1.50mm_Vertical -JST ZE series connector, B06B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -6 -6 -Connector_JST -JST_ZE_B06B-ZESK-D_1x06_P1.50mm_Vertical -JST ZE series connector, B06B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -6 -6 -Connector_JST -JST_ZE_B07B-ZESK-1D_1x07_P1.50mm_Vertical -JST ZE series connector, B07B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -7 -7 -Connector_JST -JST_ZE_B07B-ZESK-D_1x07_P1.50mm_Vertical -JST ZE series connector, B07B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -7 -7 -Connector_JST -JST_ZE_B08B-ZESK-1D_1x08_P1.50mm_Vertical -JST ZE series connector, B08B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -8 -8 -Connector_JST -JST_ZE_B08B-ZESK-D_1x08_P1.50mm_Vertical -JST ZE series connector, B08B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -8 -8 -Connector_JST -JST_ZE_B09B-ZESK-1D_1x09_P1.50mm_Vertical -JST ZE series connector, B09B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -9 -9 -Connector_JST -JST_ZE_B09B-ZESK-D_1x09_P1.50mm_Vertical -JST ZE series connector, B09B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -9 -9 -Connector_JST -JST_ZE_B10B-ZESK-1D_1x10_P1.50mm_Vertical -JST ZE series connector, B10B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -10 -10 -Connector_JST -JST_ZE_B10B-ZESK-D_1x10_P1.50mm_Vertical -JST ZE series connector, B10B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -10 -10 -Connector_JST -JST_ZE_B11B-ZESK-1D_1x11_P1.50mm_Vertical -JST ZE series connector, B11B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -11 -11 -Connector_JST -JST_ZE_B11B-ZESK-D_1x11_P1.50mm_Vertical -JST ZE series connector, B11B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -11 -11 -Connector_JST -JST_ZE_B12B-ZESK-1D_1x12_P1.50mm_Vertical -JST ZE series connector, B12B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -12 -12 -Connector_JST -JST_ZE_B12B-ZESK-D_1x12_P1.50mm_Vertical -JST ZE series connector, B12B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -12 -12 -Connector_JST -JST_ZE_B13B-ZESK-1D_1x13_P1.50mm_Vertical -JST ZE series connector, B13B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -13 -13 -Connector_JST -JST_ZE_B13B-ZESK-D_1x13_P1.50mm_Vertical -JST ZE series connector, B13B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -13 -13 -Connector_JST -JST_ZE_B14B-ZESK-1D_1x14_P1.50mm_Vertical -JST ZE series connector, B14B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -14 -14 -Connector_JST -JST_ZE_B14B-ZESK-D_1x14_P1.50mm_Vertical -JST ZE series connector, B14B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -14 -14 -Connector_JST -JST_ZE_B15B-ZESK-1D_1x15_P1.50mm_Vertical -JST ZE series connector, B15B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -15 -15 -Connector_JST -JST_ZE_B15B-ZESK-D_1x15_P1.50mm_Vertical -JST ZE series connector, B15B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -15 -15 -Connector_JST -JST_ZE_B16B-ZESK-1D_1x16_P1.50mm_Vertical -JST ZE series connector, B16B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry boss -0 -16 -16 -Connector_JST -JST_ZE_B16B-ZESK-D_1x16_P1.50mm_Vertical -JST ZE series connector, B16B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE side entry -0 -16 -16 -Connector_JST -JST_ZE_BM02B-ZESS-TBT_1x02-1MP_P1.50mm_Vertical -JST ZE series connector, BM02B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -4 -3 -Connector_JST -JST_ZE_BM03B-ZESS-TBT_1x03-1MP_P1.50mm_Vertical -JST ZE series connector, BM03B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -5 -4 -Connector_JST -JST_ZE_BM04B-ZESS-TBT_1x04-1MP_P1.50mm_Vertical -JST ZE series connector, BM04B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -6 -5 -Connector_JST -JST_ZE_BM05B-ZESS-TBT_1x05-1MP_P1.50mm_Vertical -JST ZE series connector, BM05B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -7 -6 -Connector_JST -JST_ZE_BM06B-ZESS-TBT_1x06-1MP_P1.50mm_Vertical -JST ZE series connector, BM06B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -8 -7 -Connector_JST -JST_ZE_BM07B-ZESS-TBT_1x07-1MP_P1.50mm_Vertical -JST ZE series connector, BM07B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -9 -8 -Connector_JST -JST_ZE_BM08B-ZESS-TBT_1x08-1MP_P1.50mm_Vertical -JST ZE series connector, BM08B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -10 -9 -Connector_JST -JST_ZE_BM09B-ZESS-TBT_1x09-1MP_P1.50mm_Vertical -JST ZE series connector, BM09B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -11 -10 -Connector_JST -JST_ZE_BM10B-ZESS-TBT_1x10-1MP_P1.50mm_Vertical -JST ZE series connector, BM10B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -12 -11 -Connector_JST -JST_ZE_BM11B-ZESS-TBT_1x11-1MP_P1.50mm_Vertical -JST ZE series connector, BM11B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -13 -12 -Connector_JST -JST_ZE_BM12B-ZESS-TBT_1x12-1MP_P1.50mm_Vertical -JST ZE series connector, BM12B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -14 -13 -Connector_JST -JST_ZE_BM13B-ZESS-TBT_1x13-1MP_P1.50mm_Vertical -JST ZE series connector, BM13B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -15 -14 -Connector_JST -JST_ZE_BM14B-ZESS-TBT_1x14-1MP_P1.50mm_Vertical -JST ZE series connector, BM14B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -16 -15 -Connector_JST -JST_ZE_BM15B-ZESS-TBT_1x15-1MP_P1.50mm_Vertical -JST ZE series connector, BM15B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -17 -16 -Connector_JST -JST_ZE_BM16B-ZESS-TBT_1x16-1MP_P1.50mm_Vertical -JST ZE series connector, BM16B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE vertical -0 -18 -17 -Connector_JST -JST_ZE_S02B-ZESK-2D_1x02_P1.50mm_Horizontal -JST ZE series connector, S02B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -2 -2 -Connector_JST -JST_ZE_S03B-ZESK-2D_1x03_P1.50mm_Horizontal -JST ZE series connector, S03B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -3 -3 -Connector_JST -JST_ZE_S04B-ZESK-2D_1x04_P1.50mm_Horizontal -JST ZE series connector, S04B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -4 -4 -Connector_JST -JST_ZE_S05B-ZESK-2D_1x05_P1.50mm_Horizontal -JST ZE series connector, S05B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -5 -5 -Connector_JST -JST_ZE_S06B-ZESK-2D_1x06_P1.50mm_Horizontal -JST ZE series connector, S06B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -6 -6 -Connector_JST -JST_ZE_S07B-ZESK-2D_1x07_P1.50mm_Horizontal -JST ZE series connector, S07B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -7 -7 -Connector_JST -JST_ZE_S08B-ZESK-2D_1x08_P1.50mm_Horizontal -JST ZE series connector, S08B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -8 -8 -Connector_JST -JST_ZE_S09B-ZESK-2D_1x09_P1.50mm_Horizontal -JST ZE series connector, S09B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -9 -9 -Connector_JST -JST_ZE_S10B-ZESK-2D_1x10_P1.50mm_Horizontal -JST ZE series connector, S10B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -10 -10 -Connector_JST -JST_ZE_S11B-ZESK-2D_1x11_P1.50mm_Horizontal -JST ZE series connector, S11B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -11 -11 -Connector_JST -JST_ZE_S12B-ZESK-2D_1x12_P1.50mm_Horizontal -JST ZE series connector, S12B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -12 -12 -Connector_JST -JST_ZE_S13B-ZESK-2D_1x13_P1.50mm_Horizontal -JST ZE series connector, S13B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -13 -13 -Connector_JST -JST_ZE_S14B-ZESK-2D_1x14_P1.50mm_Horizontal -JST ZE series connector, S14B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -14 -14 -Connector_JST -JST_ZE_S15B-ZESK-2D_1x15_P1.50mm_Horizontal -JST ZE series connector, S15B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -15 -15 -Connector_JST -JST_ZE_S16B-ZESK-2D_1x16_P1.50mm_Horizontal -JST ZE series connector, S16B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE top entry -0 -16 -16 -Connector_JST -JST_ZE_SM02B-ZESS-TB_1x02-1MP_P1.50mm_Horizontal -JST ZE series connector, SM02B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -4 -3 -Connector_JST -JST_ZE_SM03B-ZESS-TB_1x03-1MP_P1.50mm_Horizontal -JST ZE series connector, SM03B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -5 -4 -Connector_JST -JST_ZE_SM04B-ZESS-TB_1x04-1MP_P1.50mm_Horizontal -JST ZE series connector, SM04B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -6 -5 -Connector_JST -JST_ZE_SM05B-ZESS-TB_1x05-1MP_P1.50mm_Horizontal -JST ZE series connector, SM05B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -7 -6 -Connector_JST -JST_ZE_SM06B-ZESS-TB_1x06-1MP_P1.50mm_Horizontal -JST ZE series connector, SM06B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -8 -7 -Connector_JST -JST_ZE_SM07B-ZESS-TB_1x07-1MP_P1.50mm_Horizontal -JST ZE series connector, SM07B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -9 -8 -Connector_JST -JST_ZE_SM08B-ZESS-TB_1x08-1MP_P1.50mm_Horizontal -JST ZE series connector, SM08B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -10 -9 -Connector_JST -JST_ZE_SM09B-ZESS-TB_1x09-1MP_P1.50mm_Horizontal -JST ZE series connector, SM09B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -11 -10 -Connector_JST -JST_ZE_SM10B-ZESS-TB_1x10-1MP_P1.50mm_Horizontal -JST ZE series connector, SM10B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -12 -11 -Connector_JST -JST_ZE_SM11B-ZESS-TB_1x11-1MP_P1.50mm_Horizontal -JST ZE series connector, SM11B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -13 -12 -Connector_JST -JST_ZE_SM12B-ZESS-TB_1x12-1MP_P1.50mm_Horizontal -JST ZE series connector, SM12B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -14 -13 -Connector_JST -JST_ZE_SM13B-ZESS-TB_1x13-1MP_P1.50mm_Horizontal -JST ZE series connector, SM13B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -15 -14 -Connector_JST -JST_ZE_SM14B-ZESS-TB_1x14-1MP_P1.50mm_Horizontal -JST ZE series connector, SM14B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -16 -15 -Connector_JST -JST_ZE_SM15B-ZESS-TB_1x15-1MP_P1.50mm_Horizontal -JST ZE series connector, SM15B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -17 -16 -Connector_JST -JST_ZE_SM16B-ZESS-TB_1x16-1MP_P1.50mm_Horizontal -JST ZE series connector, SM16B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator -connector JST ZE horizontal -0 -18 -17 -Connector_Molex -Molex_CLIK-Mate_502382-0270_1x02-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0270 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -4 -3 -Connector_Molex -Molex_CLIK-Mate_502382-0370_1x03-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0370 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -5 -4 -Connector_Molex -Molex_CLIK-Mate_502382-0470_1x04-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0470 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -6 -5 -Connector_Molex -Molex_CLIK-Mate_502382-0570_1x05-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0570 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -7 -6 -Connector_Molex -Molex_CLIK-Mate_502382-0670_1x06-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0670 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -8 -7 -Connector_Molex -Molex_CLIK-Mate_502382-0770_1x07-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0770 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -9 -8 -Connector_Molex -Molex_CLIK-Mate_502382-0870_1x08-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0870 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -10 -9 -Connector_Molex -Molex_CLIK-Mate_502382-0970_1x09-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-0970 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -11 -10 -Connector_Molex -Molex_CLIK-Mate_502382-1070_1x10-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-1070 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -12 -11 -Connector_Molex -Molex_CLIK-Mate_502382-1170_1x11-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-1170 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -13 -12 -Connector_Molex -Molex_CLIK-Mate_502382-1270_1x12-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-1270 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -14 -13 -Connector_Molex -Molex_CLIK-Mate_502382-1370_1x13-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-1370 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -15 -14 -Connector_Molex -Molex_CLIK-Mate_502382-1470_1x14-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-1470 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -16 -15 -Connector_Molex -Molex_CLIK-Mate_502382-1570_1x15-1MP_P1.25mm_Vertical -Molex CLIK-Mate series connector, 502382-1570 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -17 -16 -Connector_Molex -Molex_CLIK-Mate_502386-0270_1x02-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0270 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -4 -3 -Connector_Molex -Molex_CLIK-Mate_502386-0370_1x03-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -5 -4 -Connector_Molex -Molex_CLIK-Mate_502386-0470_1x04-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0470 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -6 -5 -Connector_Molex -Molex_CLIK-Mate_502386-0570_1x05-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0570 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -7 -6 -Connector_Molex -Molex_CLIK-Mate_502386-0670_1x06-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0670 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -8 -7 -Connector_Molex -Molex_CLIK-Mate_502386-0770_1x07-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0770 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -9 -8 -Connector_Molex -Molex_CLIK-Mate_502386-0870_1x08-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0870 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -10 -9 -Connector_Molex -Molex_CLIK-Mate_502386-0970_1x09-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-0970 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -11 -10 -Connector_Molex -Molex_CLIK-Mate_502386-1070_1x10-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-1070 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -12 -11 -Connector_Molex -Molex_CLIK-Mate_502386-1170_1x11-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-1170 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -13 -12 -Connector_Molex -Molex_CLIK-Mate_502386-1270_1x12-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-1270 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -14 -13 -Connector_Molex -Molex_CLIK-Mate_502386-1370_1x13-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-1370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -15 -14 -Connector_Molex -Molex_CLIK-Mate_502386-1470_1x14-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-1470 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -16 -15 -Connector_Molex -Molex_CLIK-Mate_502386-1570_1x15-1MP_P1.25mm_Horizontal -Molex CLIK-Mate series connector, 502386-1570 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -17 -16 -Connector_Molex -Molex_CLIK-Mate_502443-0270_1x02-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0270 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -4 -3 -Connector_Molex -Molex_CLIK-Mate_502443-0370_1x03-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0370 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -5 -4 -Connector_Molex -Molex_CLIK-Mate_502443-0470_1x04-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0470 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -6 -5 -Connector_Molex -Molex_CLIK-Mate_502443-0570_1x05-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0570 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -7 -6 -Connector_Molex -Molex_CLIK-Mate_502443-0670_1x06-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0670 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -8 -7 -Connector_Molex -Molex_CLIK-Mate_502443-0770_1x07-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0770 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -9 -8 -Connector_Molex -Molex_CLIK-Mate_502443-0870_1x08-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0870 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -10 -9 -Connector_Molex -Molex_CLIK-Mate_502443-0970_1x09-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-0970 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -11 -10 -Connector_Molex -Molex_CLIK-Mate_502443-1270_1x12-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-1270 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -14 -13 -Connector_Molex -Molex_CLIK-Mate_502443-1370_1x13-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-1370 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -15 -14 -Connector_Molex -Molex_CLIK-Mate_502443-1470_1x14-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-1470 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -16 -15 -Connector_Molex -Molex_CLIK-Mate_502443-1570_1x15-1MP_P2.00mm_Vertical -Molex CLIK-Mate series connector, 502443-1570 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -17 -16 -Connector_Molex -Molex_CLIK-Mate_502494-0270_1x02-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-0270 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -4 -3 -Connector_Molex -Molex_CLIK-Mate_502494-0370_1x03-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-0370 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -5 -4 -Connector_Molex -Molex_CLIK-Mate_502494-0470_1x04-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-0470 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -6 -5 -Connector_Molex -Molex_CLIK-Mate_502494-0670_1x06-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-0670 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -8 -7 -Connector_Molex -Molex_CLIK-Mate_502494-0870_1x08-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-0870 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -10 -9 -Connector_Molex -Molex_CLIK-Mate_502494-1070_1x10-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-1070 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -12 -11 -Connector_Molex -Molex_CLIK-Mate_502494-1270_1x12-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-1270 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -14 -13 -Connector_Molex -Molex_CLIK-Mate_502494-1370_1x13-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-1370 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -15 -14 -Connector_Molex -Molex_CLIK-Mate_502494-1470_1x14-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-1470 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -16 -15 -Connector_Molex -Molex_CLIK-Mate_502494-1570_1x15-1MP_P2.00mm_Horizontal -Molex CLIK-Mate series connector, 502494-1570 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -17 -16 -Connector_Molex -Molex_CLIK-Mate_502585-0270_1x02-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0270 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -4 -3 -Connector_Molex -Molex_CLIK-Mate_502585-0370_1x03-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0370 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -5 -4 -Connector_Molex -Molex_CLIK-Mate_502585-0470_1x04-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0470 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -6 -5 -Connector_Molex -Molex_CLIK-Mate_502585-0570_1x05-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0570 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -7 -6 -Connector_Molex -Molex_CLIK-Mate_502585-0670_1x06-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0670 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -8 -7 -Connector_Molex -Molex_CLIK-Mate_502585-0770_1x07-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0770 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -9 -8 -Connector_Molex -Molex_CLIK-Mate_502585-0870_1x08-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0870 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -10 -9 -Connector_Molex -Molex_CLIK-Mate_502585-0970_1x09-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-0970 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -11 -10 -Connector_Molex -Molex_CLIK-Mate_502585-1070_1x10-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-1070 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -12 -11 -Connector_Molex -Molex_CLIK-Mate_502585-1170_1x11-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-1170 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -13 -12 -Connector_Molex -Molex_CLIK-Mate_502585-1270_1x12-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-1270 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -14 -13 -Connector_Molex -Molex_CLIK-Mate_502585-1370_1x13-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-1370 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -15 -14 -Connector_Molex -Molex_CLIK-Mate_502585-1470_1x14-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-1470 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -16 -15 -Connector_Molex -Molex_CLIK-Mate_502585-1570_1x15-1MP_P1.50mm_Horizontal -Molex CLIK-Mate series connector, 502585-1570 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate top entry -0 -17 -16 -Connector_Molex -Molex_CLIK-Mate_505405-0270_1x02-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0270 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -4 -3 -Connector_Molex -Molex_CLIK-Mate_505405-0370_1x03-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0370 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -5 -4 -Connector_Molex -Molex_CLIK-Mate_505405-0470_1x04-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0470 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -6 -5 -Connector_Molex -Molex_CLIK-Mate_505405-0570_1x05-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0570 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -7 -6 -Connector_Molex -Molex_CLIK-Mate_505405-0670_1x06-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0670 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -8 -7 -Connector_Molex -Molex_CLIK-Mate_505405-0770_1x07-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0770 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -9 -8 -Connector_Molex -Molex_CLIK-Mate_505405-0870_1x08-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0870 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -10 -9 -Connector_Molex -Molex_CLIK-Mate_505405-0970_1x09-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-0970 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -11 -10 -Connector_Molex -Molex_CLIK-Mate_505405-1070_1x10-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-1070 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -12 -11 -Connector_Molex -Molex_CLIK-Mate_505405-1170_1x11-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-1170 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -13 -12 -Connector_Molex -Molex_CLIK-Mate_505405-1270_1x12-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-1270 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -14 -13 -Connector_Molex -Molex_CLIK-Mate_505405-1370_1x13-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-1370 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -15 -14 -Connector_Molex -Molex_CLIK-Mate_505405-1470_1x14-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-1470 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -16 -15 -Connector_Molex -Molex_CLIK-Mate_505405-1570_1x15-1MP_P1.50mm_Vertical -Molex CLIK-Mate series connector, 505405-1570 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator -connector Molex CLIK-Mate side entry -0 -17 -16 -Connector_Molex -Molex_KK-254_AE-6410-02A_1x02_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-02A example for new part number: 22-27-2021, 2 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -2 -2 -Connector_Molex -Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-03A example for new part number: 22-27-2031, 3 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -3 -3 -Connector_Molex -Molex_KK-254_AE-6410-04A_1x04_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-04A example for new part number: 22-27-2041, 4 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -4 -4 -Connector_Molex -Molex_KK-254_AE-6410-05A_1x05_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-05A example for new part number: 22-27-2051, 5 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -5 -5 -Connector_Molex -Molex_KK-254_AE-6410-06A_1x06_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-06A example for new part number: 22-27-2061, 6 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -6 -6 -Connector_Molex -Molex_KK-254_AE-6410-07A_1x07_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-07A example for new part number: 22-27-2071, 7 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -7 -7 -Connector_Molex -Molex_KK-254_AE-6410-08A_1x08_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-08A example for new part number: 22-27-2081, 8 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -8 -8 -Connector_Molex -Molex_KK-254_AE-6410-09A_1x09_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-09A example for new part number: 22-27-2091, 9 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -9 -9 -Connector_Molex -Molex_KK-254_AE-6410-10A_1x10_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-10A example for new part number: 22-27-2101, 10 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -10 -10 -Connector_Molex -Molex_KK-254_AE-6410-11A_1x11_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-11A example for new part number: 22-27-2111, 11 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -11 -11 -Connector_Molex -Molex_KK-254_AE-6410-12A_1x12_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-12A example for new part number: 22-27-2121, 12 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -12 -12 -Connector_Molex -Molex_KK-254_AE-6410-13A_1x13_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-13A example for new part number: 22-27-2131, 13 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -13 -13 -Connector_Molex -Molex_KK-254_AE-6410-14A_1x14_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-14A example for new part number: 22-27-2141, 14 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -14 -14 -Connector_Molex -Molex_KK-254_AE-6410-15A_1x15_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-15A example for new part number: 22-27-2151, 15 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -15 -15 -Connector_Molex -Molex_KK-254_AE-6410-16A_1x16_P2.54mm_Vertical -Molex KK-254 Interconnect System, old/engineering part number: AE-6410-16A example for new part number: 22-27-2161, 16 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-254 side entry -0 -16 -16 -Connector_Molex -Molex_KK-396_A-41791-0002_1x02_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0002 example for new part number: 26-60-4020, 2 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -2 -2 -Connector_Molex -Molex_KK-396_A-41791-0003_1x03_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0003 example for new part number: 26-60-4030, 3 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -3 -3 -Connector_Molex -Molex_KK-396_A-41791-0004_1x04_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0004 example for new part number: 26-60-4040, 4 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -4 -4 -Connector_Molex -Molex_KK-396_A-41791-0005_1x05_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0005 example for new part number: 26-60-4050, 5 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -5 -5 -Connector_Molex -Molex_KK-396_A-41791-0006_1x06_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0006 example for new part number: 26-60-4060, 6 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -6 -6 -Connector_Molex -Molex_KK-396_A-41791-0007_1x07_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0007 example for new part number: 26-60-4070, 7 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -7 -7 -Connector_Molex -Molex_KK-396_A-41791-0008_1x08_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0008 example for new part number: 26-60-4080, 8 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -8 -8 -Connector_Molex -Molex_KK-396_A-41791-0009_1x09_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0009 example for new part number: 26-60-4090, 9 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -9 -9 -Connector_Molex -Molex_KK-396_A-41791-0010_1x10_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0010 example for new part number: 26-60-4100, 10 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -10 -10 -Connector_Molex -Molex_KK-396_A-41791-0011_1x11_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0011 example for new part number: 26-60-4110, 11 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -11 -11 -Connector_Molex -Molex_KK-396_A-41791-0012_1x12_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0012 example for new part number: 26-60-4120, 12 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -12 -12 -Connector_Molex -Molex_KK-396_A-41791-0013_1x13_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0013 example for new part number: 26-60-4130, 13 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -13 -13 -Connector_Molex -Molex_KK-396_A-41791-0014_1x14_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0014 example for new part number: 26-60-4140, 14 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -14 -14 -Connector_Molex -Molex_KK-396_A-41791-0015_1x15_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0015 example for new part number: 26-60-4150, 15 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -15 -15 -Connector_Molex -Molex_KK-396_A-41791-0016_1x16_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0016 example for new part number: 26-60-4160, 16 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -16 -16 -Connector_Molex -Molex_KK-396_A-41791-0017_1x17_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0017 example for new part number: 26-60-4170, 17 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -17 -17 -Connector_Molex -Molex_KK-396_A-41791-0018_1x18_P3.96mm_Vertical -Molex KK 396 Interconnect System, old/engineering part number: A-41791-0018 example for new part number: 26-60-4180, 18 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator -connector Molex KK-396 vertical -0 -18 -18 -Connector_Molex -Molex_Mega-Fit_76825-0002_2x01_P5.70mm_Horizontal -Molex Mega-Fit Power Connectors, 76825-0002 (compatible alternatives: 172064-0002, 172064-1002), 1 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit top entry -0 -2 -2 -Connector_Molex -Molex_Mega-Fit_76825-0004_2x02_P5.70mm_Horizontal -Molex Mega-Fit Power Connectors, 76825-0004 (compatible alternatives: 172064-0004, 172064-1004), 2 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit top entry -0 -4 -4 -Connector_Molex -Molex_Mega-Fit_76825-0006_2x03_P5.70mm_Horizontal -Molex Mega-Fit Power Connectors, 76825-0006 (compatible alternatives: 172064-0006, 172064-1006), 3 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit top entry -0 -6 -6 -Connector_Molex -Molex_Mega-Fit_76825-0008_2x04_P5.70mm_Horizontal -Molex Mega-Fit Power Connectors, 76825-0008 (compatible alternatives: 172064-0008, 172064-1008), 4 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit top entry -0 -8 -8 -Connector_Molex -Molex_Mega-Fit_76825-0010_2x05_P5.70mm_Horizontal -Molex Mega-Fit Power Connectors, 76825-0010 (compatible alternatives: 172064-0010, 172064-1010), 5 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit top entry -0 -10 -10 -Connector_Molex -Molex_Mega-Fit_76825-0012_2x06_P5.70mm_Horizontal -Molex Mega-Fit Power Connectors, 76825-0012 (compatible alternatives: 172064-0012, 172064-1012), 6 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit top entry -0 -12 -12 -Connector_Molex -Molex_Mega-Fit_76829-0002_2x01_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0002 (compatible alternatives: 172065-0002, 172065-1002), 1 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -2 -2 -Connector_Molex -Molex_Mega-Fit_76829-0004_2x02_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0004 (compatible alternatives: 172065-0004, 172065-1004), 2 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -4 -4 -Connector_Molex -Molex_Mega-Fit_76829-0006_2x03_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0006 (compatible alternatives: 172065-0006, 172065-1006), 3 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -6 -6 -Connector_Molex -Molex_Mega-Fit_76829-0008_2x04_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0008 (compatible alternatives: 172065-0008, 172065-1008), 4 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -8 -8 -Connector_Molex -Molex_Mega-Fit_76829-0010_2x05_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0010 (compatible alternatives: 172065-0010, 172065-1010), 5 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -10 -10 -Connector_Molex -Molex_Mega-Fit_76829-0012_2x06_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0012 (compatible alternatives: 172065-0012, 172065-1012), 6 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -12 -12 -Connector_Molex -Molex_Mega-Fit_76829-0102_2x01_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0102 (compatible alternatives: 172065-0202, 172065-0302), 1 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -2 -2 -Connector_Molex -Molex_Mega-Fit_76829-0104_2x02_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0104 (compatible alternatives: 172065-0204, 172065-0304), 2 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -4 -4 -Connector_Molex -Molex_Mega-Fit_76829-0106_2x03_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0106 (compatible alternatives: 172065-0206, 172065-0306), 3 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -6 -6 -Connector_Molex -Molex_Mega-Fit_76829-0108_2x04_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0108 (compatible alternatives: 172065-0208, 172065-0308), 4 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -8 -8 -Connector_Molex -Molex_Mega-Fit_76829-0110_2x05_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0110 (compatible alternatives: 172065-0210, 172065-0310), 5 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -10 -10 -Connector_Molex -Molex_Mega-Fit_76829-0112_2x06_P5.70mm_Vertical -Molex Mega-Fit Power Connectors, 76829-0112 (compatible alternatives: 172065-0212, 172065-0312), 6 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator -connector Molex Mega-Fit side entry -0 -12 -12 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0200_2x01_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0200 (alternative finishes: 43045-020x), 1 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -2 -2 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0210_2x01-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0210 (compatible alternatives: 43045-0211, 43045-0209), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -4 -3 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0212_2x01_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0212 (compatible alternatives: 43045-0213, 43045-0224), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -2 -2 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0215_2x01_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0215 (compatible alternatives: 43045-0216, 43045-0217), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -2 -2 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0218_2x01-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0218 (compatible alternatives: 43045-0219, 43045-0220), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -4 -3 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0221_2x01-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0221 (alternative finishes: 43045-022x), 1 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -4 -3 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0400_2x02_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0400 (alternative finishes: 43045-040x), 2 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -4 -4 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0410_2x02-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0410 (compatible alternatives: 43045-0411, 43045-0409), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -6 -5 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0412_2x02_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0412 (compatible alternatives: 43045-0413, 43045-0424), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -4 -4 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0415_2x02_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0415 (compatible alternatives: 43045-0416, 43045-0417), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -4 -4 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0418_2x02-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0418 (compatible alternatives: 43045-0419, 43045-0420), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -6 -5 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0421_2x02-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0421 (alternative finishes: 43045-042x), 2 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -6 -5 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0600_2x03_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0600 (alternative finishes: 43045-060x), 3 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -6 -6 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0610_2x03-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0610 (compatible alternatives: 43045-0611, 43045-0609), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -8 -7 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0612_2x03_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0612 (compatible alternatives: 43045-0613, 43045-0624), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -6 -6 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0615_2x03_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0615 (compatible alternatives: 43045-0616, 43045-0617), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -6 -6 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0618_2x03-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0618 (compatible alternatives: 43045-0619, 43045-0620), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -8 -7 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0621_2x03-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0621 (alternative finishes: 43045-062x), 3 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -8 -7 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0800_2x04_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0800 (alternative finishes: 43045-080x), 4 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -8 -8 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0810_2x04-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0810 (compatible alternatives: 43045-0811, 43045-0809), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -10 -9 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0812_2x04_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0812 (compatible alternatives: 43045-0813, 43045-0824), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -8 -8 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0815_2x04_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0815 (compatible alternatives: 43045-0816, 43045-0817), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -8 -8 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0818_2x04-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-0818 (compatible alternatives: 43045-0819, 43045-0820), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -10 -9 -Connector_Molex -Molex_Micro-Fit_3.0_43045-0821_2x04-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-0821 (alternative finishes: 43045-082x), 4 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -10 -9 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1000_2x05_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1000 (alternative finishes: 43045-100x), 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -10 -10 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1010_2x05-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1010 (compatible alternatives: 43045-1011, 43045-1009), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -12 -11 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1012_2x05_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1012 (compatible alternatives: 43045-1013, 43045-1024), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -10 -10 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1015_2x05_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1015 (compatible alternatives: 43045-1016, 43045-1017), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -10 -10 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1018_2x05-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1018 (compatible alternatives: 43045-1019, 43045-1020), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -12 -11 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1021_2x05-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1021 (alternative finishes: 43045-102x), 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -12 -11 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1200_2x06_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1200 (alternative finishes: 43045-120x), 6 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -12 -12 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1210_2x06-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1210 (compatible alternatives: 43045-1211, 43045-1209), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -14 -13 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1212_2x06_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1212 (compatible alternatives: 43045-1213, 43045-1224), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -12 -12 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1215_2x06_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1215 (compatible alternatives: 43045-1216, 43045-1217), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -12 -12 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1218_2x06-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1218 (compatible alternatives: 43045-1219, 43045-1220), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -14 -13 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1221_2x06-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1221 (alternative finishes: 43045-122x), 6 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -14 -13 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1400_2x07_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1400 (alternative finishes: 43045-140x), 7 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -14 -14 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1410_2x07-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1410 (compatible alternatives: 43045-1411, 43045-1409), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -16 -15 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1412_2x07_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1412 (compatible alternatives: 43045-1413, 43045-1424), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -14 -14 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1415_2x07_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1415 (compatible alternatives: 43045-1416, 43045-1417), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -14 -14 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1418_2x07-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1418 (compatible alternatives: 43045-1419, 43045-1420), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -16 -15 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1421_2x07-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1421 (alternative finishes: 43045-142x), 7 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -16 -15 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1600_2x08_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1600 (alternative finishes: 43045-160x), 8 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -16 -16 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1610_2x08-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1610 (compatible alternatives: 43045-1611, 43045-1609), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -18 -17 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1612_2x08_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1612 (compatible alternatives: 43045-1613, 43045-1624), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -16 -16 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1615_2x08_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1615 (compatible alternatives: 43045-1616, 43045-1617), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -16 -16 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1618_2x08-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1618 (compatible alternatives: 43045-1619, 43045-1620), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -18 -17 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1621_2x08-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1621 (alternative finishes: 43045-162x), 8 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -18 -17 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1800_2x09_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1800 (alternative finishes: 43045-180x), 9 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -18 -18 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1810_2x09-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1810 (compatible alternatives: 43045-1811, 43045-1809), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -20 -19 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1812_2x09_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1812 (compatible alternatives: 43045-1813, 43045-1824), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -18 -18 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1815_2x09_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1815 (compatible alternatives: 43045-1816, 43045-1817), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -18 -18 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1818_2x09-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-1818 (compatible alternatives: 43045-1819, 43045-1820), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -20 -19 -Connector_Molex -Molex_Micro-Fit_3.0_43045-1821_2x09-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-1821 (alternative finishes: 43045-182x), 9 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -20 -19 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2000_2x10_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2000 (alternative finishes: 43045-200x), 10 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -20 -20 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2010_2x10-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2010 (compatible alternatives: 43045-2011, 43045-2009), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -22 -21 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2012_2x10_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2012 (compatible alternatives: 43045-2013, 43045-2024), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -20 -20 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2015_2x10_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2015 (compatible alternatives: 43045-2016, 43045-2017), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -20 -20 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2018_2x10-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2018 (compatible alternatives: 43045-2019, 43045-2020), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -22 -21 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2021_2x10-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2021 (alternative finishes: 43045-202x), 10 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -22 -21 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2200_2x11_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2200 (alternative finishes: 43045-220x), 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -22 -22 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2210_2x11-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2210 (compatible alternatives: 43045-2211, 43045-2209), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -24 -23 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2212_2x11_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2212 (compatible alternatives: 43045-2213, 43045-2224), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -22 -22 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2215_2x11_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2215 (compatible alternatives: 43045-2216, 43045-2217), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -22 -22 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2218_2x11-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2218 (compatible alternatives: 43045-2219, 43045-2220), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -24 -23 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2221_2x11-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2221 (alternative finishes: 43045-222x), 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -24 -23 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2400_2x12_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2400 (alternative finishes: 43045-240x), 12 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -24 -24 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2410_2x12-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2410 (compatible alternatives: 43045-2411, 43045-2409), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -26 -25 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2412_2x12_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2412 (compatible alternatives: 43045-2413, 43045-2424), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -24 -24 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2415_2x12_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2415 (compatible alternatives: 43045-2416, 43045-2417), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -24 -24 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2418_2x12-1MP_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43045-2418 (compatible alternatives: 43045-2419, 43045-2420), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 side entry -0 -26 -25 -Connector_Molex -Molex_Micro-Fit_3.0_43045-2421_2x12-1MP_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43045-2421 (alternative finishes: 43045-242x), 12 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 horizontal -0 -26 -25 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0200_1x02_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0200 (compatible alternatives: 43650-0201, 43650-0202), 2 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -2 -2 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0215_1x02_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0215 (compatible alternatives: 43650-0216, 43650-0217), 2 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -2 -2 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0300_1x03_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0300 (compatible alternatives: 43650-0301, 43650-0302), 3 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -3 -3 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0315_1x03_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0315 (compatible alternatives: 43650-0316, 43650-0317), 3 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -3 -3 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0400_1x04_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0400 (compatible alternatives: 43650-0401, 43650-0402), 4 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -4 -4 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0415_1x04_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0415 (compatible alternatives: 43650-0416, 43650-0417), 4 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -4 -4 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0500_1x05_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0500 (compatible alternatives: 43650-0501, 43650-0502), 5 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -5 -5 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0515_1x05_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0515 (compatible alternatives: 43650-0516, 43650-0517), 5 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -5 -5 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0600_1x06_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0600 (compatible alternatives: 43650-0601, 43650-0602), 6 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -6 -6 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0615_1x06_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0615 (compatible alternatives: 43650-0616, 43650-0617), 6 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -6 -6 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0700_1x07_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0700 (compatible alternatives: 43650-0701, 43650-0702), 7 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -7 -7 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0715_1x07_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0715 (compatible alternatives: 43650-0716, 43650-0717), 7 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -7 -7 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0800_1x08_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0800 (compatible alternatives: 43650-0801, 43650-0802), 8 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -8 -8 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0815_1x08_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0815 (compatible alternatives: 43650-0816, 43650-0817), 8 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -8 -8 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0900_1x09_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-0900 (compatible alternatives: 43650-0901, 43650-0902), 9 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -9 -9 -Connector_Molex -Molex_Micro-Fit_3.0_43650-0915_1x09_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-0915 (compatible alternatives: 43650-0916, 43650-0917), 9 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -9 -9 -Connector_Molex -Molex_Micro-Fit_3.0_43650-1000_1x10_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-1000 (compatible alternatives: 43650-1001, 43650-1002), 10 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -10 -10 -Connector_Molex -Molex_Micro-Fit_3.0_43650-1015_1x10_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-1015 (compatible alternatives: 43650-1016, 43650-1017), 10 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -10 -10 -Connector_Molex -Molex_Micro-Fit_3.0_43650-1100_1x11_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-1100 (compatible alternatives: 43650-1101, 43650-1102), 11 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -11 -11 -Connector_Molex -Molex_Micro-Fit_3.0_43650-1115_1x11_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-1115 (compatible alternatives: 43650-1116, 43650-1117), 11 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -11 -11 -Connector_Molex -Molex_Micro-Fit_3.0_43650-1200_1x12_P3.00mm_Horizontal -Molex Micro-Fit 3.0 Connector System, 43650-1200 (compatible alternatives: 43650-1201, 43650-1202), 12 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 top entry -0 -12 -12 -Connector_Molex -Molex_Micro-Fit_3.0_43650-1215_1x12_P3.00mm_Vertical -Molex Micro-Fit 3.0 Connector System, 43650-1215 (compatible alternatives: 43650-1216, 43650-1217), 12 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Fit_3.0 vertical -0 -12 -12 -Connector_Molex -Molex_Micro-Latch_53253-0270_1x02_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0270 (compatible alternatives: 53253-0250), 2 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -2 -2 -Connector_Molex -Molex_Micro-Latch_53253-0370_1x03_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0370 (compatible alternatives: 53253-0350), 3 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -3 -3 -Connector_Molex -Molex_Micro-Latch_53253-0470_1x04_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0470 (compatible alternatives: 53253-0450), 4 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -4 -4 -Connector_Molex -Molex_Micro-Latch_53253-0570_1x05_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0570 (compatible alternatives: 53253-0550), 5 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -5 -5 -Connector_Molex -Molex_Micro-Latch_53253-0670_1x06_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0670 (compatible alternatives: 53253-0650), 6 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -6 -6 -Connector_Molex -Molex_Micro-Latch_53253-0770_1x07_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0770 (compatible alternatives: 53253-0750), 7 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -7 -7 -Connector_Molex -Molex_Micro-Latch_53253-0870_1x08_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0870 (compatible alternatives: 53253-0850), 8 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -8 -8 -Connector_Molex -Molex_Micro-Latch_53253-0970_1x09_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-0970 (compatible alternatives: 53253-0950), 9 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -9 -9 -Connector_Molex -Molex_Micro-Latch_53253-1070_1x10_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-1070 (compatible alternatives: 53253-1050), 10 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -10 -10 -Connector_Molex -Molex_Micro-Latch_53253-1170_1x11_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-1170 (compatible alternatives: 53253-1150), 11 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -11 -11 -Connector_Molex -Molex_Micro-Latch_53253-1270_1x12_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-1270 (compatible alternatives: 53253-1250), 12 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -12 -12 -Connector_Molex -Molex_Micro-Latch_53253-1370_1x13_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-1370 (compatible alternatives: 53253-1350), 13 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -13 -13 -Connector_Molex -Molex_Micro-Latch_53253-1470_1x14_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-1470 (compatible alternatives: 53253-1450), 14 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -14 -14 -Connector_Molex -Molex_Micro-Latch_53253-1570_1x15_P2.00mm_Vertical -Molex Micro-Latch Wire-to-Board Connector System, 53253-1570 (compatible alternatives: 53253-1550), 15 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch side entry -0 -15 -15 -Connector_Molex -Molex_Micro-Latch_53254-0270_1x02_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0270 (compatible alternatives: 53254-0250), 2 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -2 -2 -Connector_Molex -Molex_Micro-Latch_53254-0370_1x03_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0370 (compatible alternatives: 53254-0350), 3 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -3 -3 -Connector_Molex -Molex_Micro-Latch_53254-0470_1x04_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0470 (compatible alternatives: 53254-0450), 4 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -4 -4 -Connector_Molex -Molex_Micro-Latch_53254-0570_1x05_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0570 (compatible alternatives: 53254-0550), 5 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -5 -5 -Connector_Molex -Molex_Micro-Latch_53254-0670_1x06_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0670 (compatible alternatives: 53254-0650), 6 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -6 -6 -Connector_Molex -Molex_Micro-Latch_53254-0770_1x07_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0770 (compatible alternatives: 53254-0750), 7 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -7 -7 -Connector_Molex -Molex_Micro-Latch_53254-0870_1x08_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0870 (compatible alternatives: 53254-0850), 8 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -8 -8 -Connector_Molex -Molex_Micro-Latch_53254-0970_1x09_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-0970 (compatible alternatives: 53254-0950), 9 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -9 -9 -Connector_Molex -Molex_Micro-Latch_53254-1070_1x10_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-1070 (compatible alternatives: 53254-1050), 10 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -10 -10 -Connector_Molex -Molex_Micro-Latch_53254-1170_1x11_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-1170 (compatible alternatives: 53254-1150), 11 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -11 -11 -Connector_Molex -Molex_Micro-Latch_53254-1270_1x12_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-1270 (compatible alternatives: 53254-1250), 12 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -12 -12 -Connector_Molex -Molex_Micro-Latch_53254-1370_1x13_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-1370 (compatible alternatives: 53254-1350), 13 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -13 -13 -Connector_Molex -Molex_Micro-Latch_53254-1470_1x14_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-1470 (compatible alternatives: 53254-1450), 14 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -14 -14 -Connector_Molex -Molex_Micro-Latch_53254-1570_1x15_P2.00mm_Horizontal -Molex Micro-Latch Wire-to-Board Connector System, 53254-1570 (compatible alternatives: 53254-1550), 15 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator -connector Molex Micro-Latch top entry -0 -15 -15 -Connector_Molex -Molex_MicroClasp_55932-0210_1x02_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0210, with PCB locator, 2 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -2 -2 -Connector_Molex -Molex_MicroClasp_55932-0230_1x02_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0230, 2 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -2 -2 -Connector_Molex -Molex_MicroClasp_55932-0310_1x03_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0310, with PCB locator, 3 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -3 -3 -Connector_Molex -Molex_MicroClasp_55932-0330_1x03_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0330, 3 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -3 -3 -Connector_Molex -Molex_MicroClasp_55932-0410_1x04_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0410, with PCB locator, 4 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -4 -4 -Connector_Molex -Molex_MicroClasp_55932-0430_1x04_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0430, 4 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -4 -4 -Connector_Molex -Molex_MicroClasp_55932-0510_1x05_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0510, with PCB locator, 5 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -5 -5 -Connector_Molex -Molex_MicroClasp_55932-0530_1x05_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0530, 5 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -5 -5 -Connector_Molex -Molex_MicroClasp_55932-0610_1x06_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0610, with PCB locator, 6 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -6 -6 -Connector_Molex -Molex_MicroClasp_55932-0630_1x06_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0630, 6 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -6 -6 -Connector_Molex -Molex_MicroClasp_55932-0710_1x07_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0710, with PCB locator, 7 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -7 -7 -Connector_Molex -Molex_MicroClasp_55932-0730_1x07_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0730, 7 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -7 -7 -Connector_Molex -Molex_MicroClasp_55932-0810_1x08_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0810, with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -8 -8 -Connector_Molex -Molex_MicroClasp_55932-0830_1x08_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0830, 8 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -8 -8 -Connector_Molex -Molex_MicroClasp_55932-0910_1x09_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0910, with PCB locator, 9 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -9 -9 -Connector_Molex -Molex_MicroClasp_55932-0930_1x09_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-0930, 9 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -9 -9 -Connector_Molex -Molex_MicroClasp_55932-1010_1x10_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1010, with PCB locator, 10 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -10 -10 -Connector_Molex -Molex_MicroClasp_55932-1030_1x10_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1030, 10 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -10 -10 -Connector_Molex -Molex_MicroClasp_55932-1110_1x11_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1110, with PCB locator, 11 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -11 -11 -Connector_Molex -Molex_MicroClasp_55932-1130_1x11_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1130, 11 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -11 -11 -Connector_Molex -Molex_MicroClasp_55932-1210_1x12_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1210, with PCB locator, 12 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -12 -12 -Connector_Molex -Molex_MicroClasp_55932-1230_1x12_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1230, 12 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -12 -12 -Connector_Molex -Molex_MicroClasp_55932-1310_1x13_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1310, with PCB locator, 13 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -13 -13 -Connector_Molex -Molex_MicroClasp_55932-1330_1x13_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1330, 13 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -13 -13 -Connector_Molex -Molex_MicroClasp_55932-1410_1x14_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1410, with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -14 -14 -Connector_Molex -Molex_MicroClasp_55932-1430_1x14_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1430, 14 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -14 -14 -Connector_Molex -Molex_MicroClasp_55932-1510_1x15_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1510, with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -15 -15 -Connector_Molex -Molex_MicroClasp_55932-1530_1x15_P2.00mm_Vertical -Molex MicroClasp Wire-to-Board System, 55932-1530, 15 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp side entry -0 -15 -15 -Connector_Molex -Molex_MicroClasp_55935-0210_1x02_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0210, with PCB locator, 2 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -2 -2 -Connector_Molex -Molex_MicroClasp_55935-0230_1x02_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0230, 2 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -2 -2 -Connector_Molex -Molex_MicroClasp_55935-0310_1x03_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0310, with PCB locator, 3 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -3 -3 -Connector_Molex -Molex_MicroClasp_55935-0330_1x03_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0330, 3 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -3 -3 -Connector_Molex -Molex_MicroClasp_55935-0410_1x04_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0410, with PCB locator, 4 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -4 -4 -Connector_Molex -Molex_MicroClasp_55935-0430_1x04_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0430, 4 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -4 -4 -Connector_Molex -Molex_MicroClasp_55935-0510_1x05_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0510, with PCB locator, 5 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -5 -5 -Connector_Molex -Molex_MicroClasp_55935-0530_1x05_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0530, 5 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -5 -5 -Connector_Molex -Molex_MicroClasp_55935-0610_1x06_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0610, with PCB locator, 6 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -6 -6 -Connector_Molex -Molex_MicroClasp_55935-0630_1x06_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0630, 6 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -6 -6 -Connector_Molex -Molex_MicroClasp_55935-0710_1x07_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0710, with PCB locator, 7 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -7 -7 -Connector_Molex -Molex_MicroClasp_55935-0730_1x07_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0730, 7 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -7 -7 -Connector_Molex -Molex_MicroClasp_55935-0810_1x08_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0810, with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -8 -8 -Connector_Molex -Molex_MicroClasp_55935-0830_1x08_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0830, 8 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -8 -8 -Connector_Molex -Molex_MicroClasp_55935-0910_1x09_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0910, with PCB locator, 9 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -9 -9 -Connector_Molex -Molex_MicroClasp_55935-0930_1x09_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-0930, 9 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -9 -9 -Connector_Molex -Molex_MicroClasp_55935-1010_1x10_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1010, with PCB locator, 10 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -10 -10 -Connector_Molex -Molex_MicroClasp_55935-1030_1x10_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1030, 10 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -10 -10 -Connector_Molex -Molex_MicroClasp_55935-1110_1x11_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1110, with PCB locator, 11 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -11 -11 -Connector_Molex -Molex_MicroClasp_55935-1130_1x11_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1130, 11 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -11 -11 -Connector_Molex -Molex_MicroClasp_55935-1210_1x12_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1210, with PCB locator, 12 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -12 -12 -Connector_Molex -Molex_MicroClasp_55935-1230_1x12_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1230, 12 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -12 -12 -Connector_Molex -Molex_MicroClasp_55935-1310_1x13_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1310, with PCB locator, 13 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -13 -13 -Connector_Molex -Molex_MicroClasp_55935-1330_1x13_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1330, 13 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -13 -13 -Connector_Molex -Molex_MicroClasp_55935-1410_1x14_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1410, with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -14 -14 -Connector_Molex -Molex_MicroClasp_55935-1430_1x14_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1430, 14 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -14 -14 -Connector_Molex -Molex_MicroClasp_55935-1510_1x15_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1510, with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -15 -15 -Connector_Molex -Molex_MicroClasp_55935-1530_1x15_P2.00mm_Horizontal -Molex MicroClasp Wire-to-Board System, 55935-1530, 15 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator -connector Molex MicroClasp horizontal -0 -15 -15 -Connector_Molex -Molex_Mini-Fit_Jr_5566-02A2_2x01_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-02A2, example for new mpn: 39-28-902x, 1 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -2 -2 -Connector_Molex -Molex_Mini-Fit_Jr_5566-02A_2x01_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-02A, example for new mpn: 39-28-x02x, 1 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -2 -2 -Connector_Molex -Molex_Mini-Fit_Jr_5566-04A2_2x02_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-04A2, example for new mpn: 39-28-904x, 2 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -4 -4 -Connector_Molex -Molex_Mini-Fit_Jr_5566-04A_2x02_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-04A, example for new mpn: 39-28-x04x, 2 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -4 -4 -Connector_Molex -Molex_Mini-Fit_Jr_5566-06A2_2x03_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-06A2, example for new mpn: 39-28-906x, 3 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -6 -6 -Connector_Molex -Molex_Mini-Fit_Jr_5566-06A_2x03_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-06A, example for new mpn: 39-28-x06x, 3 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -6 -6 -Connector_Molex -Molex_Mini-Fit_Jr_5566-08A2_2x04_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-08A2, example for new mpn: 39-28-908x, 4 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -8 -8 -Connector_Molex -Molex_Mini-Fit_Jr_5566-08A_2x04_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-08A, example for new mpn: 39-28-x08x, 4 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -8 -8 -Connector_Molex -Molex_Mini-Fit_Jr_5566-10A2_2x05_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-10A2, example for new mpn: 39-28-910x, 5 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -10 -10 -Connector_Molex -Molex_Mini-Fit_Jr_5566-10A_2x05_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-10A, example for new mpn: 39-28-x10x, 5 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -10 -10 -Connector_Molex -Molex_Mini-Fit_Jr_5566-12A2_2x06_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-12A2, example for new mpn: 39-28-912x, 6 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -12 -12 -Connector_Molex -Molex_Mini-Fit_Jr_5566-12A_2x06_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-12A, example for new mpn: 39-28-x12x, 6 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -12 -12 -Connector_Molex -Molex_Mini-Fit_Jr_5566-14A2_2x07_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-14A2, example for new mpn: 39-28-914x, 7 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -14 -14 -Connector_Molex -Molex_Mini-Fit_Jr_5566-14A_2x07_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-14A, example for new mpn: 39-28-x14x, 7 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -14 -14 -Connector_Molex -Molex_Mini-Fit_Jr_5566-16A2_2x08_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-16A2, example for new mpn: 39-28-916x, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -16 -16 -Connector_Molex -Molex_Mini-Fit_Jr_5566-16A_2x08_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-16A, example for new mpn: 39-28-x16x, 8 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -16 -16 -Connector_Molex -Molex_Mini-Fit_Jr_5566-18A2_2x09_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-18A2, example for new mpn: 39-28-918x, 9 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -18 -18 -Connector_Molex -Molex_Mini-Fit_Jr_5566-18A_2x09_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-18A, example for new mpn: 39-28-x18x, 9 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -18 -18 -Connector_Molex -Molex_Mini-Fit_Jr_5566-20A2_2x10_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-20A2, example for new mpn: 39-28-920x, 10 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -20 -20 -Connector_Molex -Molex_Mini-Fit_Jr_5566-20A_2x10_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-20A, example for new mpn: 39-28-x20x, 10 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -20 -20 -Connector_Molex -Molex_Mini-Fit_Jr_5566-22A2_2x11_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-22A2, example for new mpn: 39-28-922x, 11 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -22 -22 -Connector_Molex -Molex_Mini-Fit_Jr_5566-22A_2x11_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-22A, example for new mpn: 39-28-x22x, 11 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -22 -22 -Connector_Molex -Molex_Mini-Fit_Jr_5566-24A2_2x12_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-24A2, example for new mpn: 39-28-924x, 12 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entryplastic_peg -0 -24 -24 -Connector_Molex -Molex_Mini-Fit_Jr_5566-24A_2x12_P4.20mm_Vertical -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-24A, example for new mpn: 39-28-x24x, 12 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr side entry -0 -24 -24 -Connector_Molex -Molex_Mini-Fit_Jr_5569-02A1_2x01_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-02A1, example for new mpn: 39-29-4029, 1 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -2 -2 -Connector_Molex -Molex_Mini-Fit_Jr_5569-02A2_2x01_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-02A2, example for new mpn: 39-30-0020, 1 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -2 -2 -Connector_Molex -Molex_Mini-Fit_Jr_5569-04A1_2x02_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-04A1, example for new mpn: 39-29-4049, 2 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -4 -4 -Connector_Molex -Molex_Mini-Fit_Jr_5569-04A2_2x02_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-04A2, example for new mpn: 39-30-0040, 2 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -4 -4 -Connector_Molex -Molex_Mini-Fit_Jr_5569-06A1_2x03_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-06A1, example for new mpn: 39-29-4069, 3 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -6 -6 -Connector_Molex -Molex_Mini-Fit_Jr_5569-06A2_2x03_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-06A2, example for new mpn: 39-30-0060, 3 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -6 -6 -Connector_Molex -Molex_Mini-Fit_Jr_5569-08A1_2x04_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-08A1, example for new mpn: 39-29-4089, 4 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -8 -8 -Connector_Molex -Molex_Mini-Fit_Jr_5569-08A2_2x04_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-08A2, example for new mpn: 39-30-0080, 4 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -8 -8 -Connector_Molex -Molex_Mini-Fit_Jr_5569-10A1_2x05_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-10A1, example for new mpn: 39-29-4109, 5 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -10 -10 -Connector_Molex -Molex_Mini-Fit_Jr_5569-10A2_2x05_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-10A2, example for new mpn: 39-30-0100, 5 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -10 -10 -Connector_Molex -Molex_Mini-Fit_Jr_5569-12A1_2x06_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-12A1, example for new mpn: 39-29-4129, 6 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -12 -12 -Connector_Molex -Molex_Mini-Fit_Jr_5569-12A2_2x06_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-12A2, example for new mpn: 39-30-0120, 6 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -12 -12 -Connector_Molex -Molex_Mini-Fit_Jr_5569-14A1_2x07_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A1, example for new mpn: 39-29-4149, 7 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -14 -14 -Connector_Molex -Molex_Mini-Fit_Jr_5569-14A2_2x07_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A2, example for new mpn: 39-30-0140, 7 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -14 -14 -Connector_Molex -Molex_Mini-Fit_Jr_5569-16A1_2x08_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-16A1, example for new mpn: 39-29-4169, 8 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -16 -16 -Connector_Molex -Molex_Mini-Fit_Jr_5569-16A2_2x08_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-16A2, example for new mpn: 39-30-0160, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -16 -16 -Connector_Molex -Molex_Mini-Fit_Jr_5569-18A1_2x09_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-18A1, example for new mpn: 39-29-4189, 9 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -18 -18 -Connector_Molex -Molex_Mini-Fit_Jr_5569-18A2_2x09_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-18A2, example for new mpn: 39-30-0180, 9 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -18 -18 -Connector_Molex -Molex_Mini-Fit_Jr_5569-20A1_2x10_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-20A1, example for new mpn: 39-29-4209, 10 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -20 -20 -Connector_Molex -Molex_Mini-Fit_Jr_5569-20A2_2x10_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-20A2, example for new mpn: 39-30-0200, 10 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -20 -20 -Connector_Molex -Molex_Mini-Fit_Jr_5569-22A1_2x11_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-22A1, example for new mpn: 39-29-4229, 11 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -22 -22 -Connector_Molex -Molex_Mini-Fit_Jr_5569-22A2_2x11_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-22A2, example for new mpn: 39-30-0220, 11 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -22 -22 -Connector_Molex -Molex_Mini-Fit_Jr_5569-24A1_2x12_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-24A1, example for new mpn: 39-29-4249, 12 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryscrew_flange -0 -24 -24 -Connector_Molex -Molex_Mini-Fit_Jr_5569-24A2_2x12_P4.20mm_Horizontal -Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-24A2, example for new mpn: 39-30-0240, 12 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Jr top entryplastic_peg -0 -24 -24 -Connector_Molex -Molex_Mini-Fit_Sr_42819-22XX_1x02_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 42819-22XX, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -6 -2 -Connector_Molex -Molex_Mini-Fit_Sr_42819-22XX_1x02_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42819-22XX, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -32 -2 -Connector_Molex -Molex_Mini-Fit_Sr_42819-32XX_1x03_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 42819-32XX, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -8 -3 -Connector_Molex -Molex_Mini-Fit_Sr_42819-32XX_1x03_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42819-32XX, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -47 -3 -Connector_Molex -Molex_Mini-Fit_Sr_42819-42XX_1x04_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 42819-42XX, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -10 -4 -Connector_Molex -Molex_Mini-Fit_Sr_42819-42XX_1x04_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42819-42XX, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -62 -4 -Connector_Molex -Molex_Mini-Fit_Sr_42819-52XX_1x05_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 42819-52XX, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -12 -5 -Connector_Molex -Molex_Mini-Fit_Sr_42819-52XX_1x05_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42819-52XX, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -77 -5 -Connector_Molex -Molex_Mini-Fit_Sr_42819-62XX_1x06_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 42819-62XX, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -14 -6 -Connector_Molex -Molex_Mini-Fit_Sr_42819-62XX_1x06_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42819-62XX, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -92 -6 -Connector_Molex -Molex_Mini-Fit_Sr_42820-22XX_1x02_P10.00mm_Horizontal -Molex Mini-Fit Sr. Power Connectors, 42820-22XX, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -6 -2 -Connector_Molex -Molex_Mini-Fit_Sr_42820-22XX_1x02_P10.00mm_Horizontal_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42820-22XX, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -32 -2 -Connector_Molex -Molex_Mini-Fit_Sr_42820-32XX_1x03_P10.00mm_Horizontal -Molex Mini-Fit Sr. Power Connectors, 42820-32XX, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -8 -3 -Connector_Molex -Molex_Mini-Fit_Sr_42820-32XX_1x03_P10.00mm_Horizontal_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42820-32XX, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -47 -3 -Connector_Molex -Molex_Mini-Fit_Sr_42820-42XX_1x04_P10.00mm_Horizontal -Molex Mini-Fit Sr. Power Connectors, 42820-42XX, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -10 -4 -Connector_Molex -Molex_Mini-Fit_Sr_42820-42XX_1x04_P10.00mm_Horizontal_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42820-42XX, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -62 -4 -Connector_Molex -Molex_Mini-Fit_Sr_42820-52XX_1x05_P10.00mm_Horizontal -Molex Mini-Fit Sr. Power Connectors, 42820-52XX, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -12 -5 -Connector_Molex -Molex_Mini-Fit_Sr_42820-52XX_1x05_P10.00mm_Horizontal_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42820-52XX, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -77 -5 -Connector_Molex -Molex_Mini-Fit_Sr_42820-62XX_1x06_P10.00mm_Horizontal -Molex Mini-Fit Sr. Power Connectors, 42820-62XX, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -14 -6 -Connector_Molex -Molex_Mini-Fit_Sr_42820-62XX_1x06_P10.00mm_Horizontal_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 42820-62XX, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr top entry -0 -92 -6 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx06_2x03_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 43915-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -14 -6 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx06_2x03_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 43915-xx06, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -92 -6 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx08_2x04_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 43915-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -18 -8 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx08_2x04_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 43915-xx08, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -122 -8 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx10_2x05_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 43915-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -22 -10 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx10_2x05_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 43915-xx10, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -152 -10 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx12_2x06_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 43915-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -26 -12 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx12_2x06_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 43915-xx12, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -182 -12 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx14_2x07_P10.00mm_Vertical -Molex Mini-Fit Sr. Power Connectors, 43915-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -30 -14 -Connector_Molex -Molex_Mini-Fit_Sr_43915-xx14_2x07_P10.00mm_Vertical_ThermalVias -Molex Mini-Fit Sr. Power Connectors, 43915-xx14, With thermal vias in pads, 7 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator -connector Molex Mini-Fit_Sr side entry -0 -212 -14 -Connector_Molex -Molex_Nano-Fit_105309-xx02_1x02_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx02, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -2 -2 -Connector_Molex -Molex_Nano-Fit_105309-xx03_1x03_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx03, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -3 -3 -Connector_Molex -Molex_Nano-Fit_105309-xx04_1x04_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx04, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -4 -4 -Connector_Molex -Molex_Nano-Fit_105309-xx05_1x05_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx05, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -5 -5 -Connector_Molex -Molex_Nano-Fit_105309-xx06_1x06_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx06, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -6 -6 -Connector_Molex -Molex_Nano-Fit_105309-xx07_1x07_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx07, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -7 -7 -Connector_Molex -Molex_Nano-Fit_105309-xx08_1x08_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105309-xx08, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -8 -8 -Connector_Molex -Molex_Nano-Fit_105310-xx04_2x02_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx04, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -4 -4 -Connector_Molex -Molex_Nano-Fit_105310-xx06_2x03_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -6 -6 -Connector_Molex -Molex_Nano-Fit_105310-xx08_2x04_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -8 -8 -Connector_Molex -Molex_Nano-Fit_105310-xx10_2x05_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -10 -10 -Connector_Molex -Molex_Nano-Fit_105310-xx12_2x06_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -12 -12 -Connector_Molex -Molex_Nano-Fit_105310-xx14_2x07_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -14 -14 -Connector_Molex -Molex_Nano-Fit_105310-xx16_2x08_P2.50mm_Vertical -Molex Nano-Fit Power Connectors, 105310-xx16, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit side entry -0 -16 -16 -Connector_Molex -Molex_Nano-Fit_105313-xx02_1x02_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx02, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -2 -2 -Connector_Molex -Molex_Nano-Fit_105313-xx03_1x03_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx03, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -3 -3 -Connector_Molex -Molex_Nano-Fit_105313-xx04_1x04_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx04, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -4 -4 -Connector_Molex -Molex_Nano-Fit_105313-xx05_1x05_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx05, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -5 -5 -Connector_Molex -Molex_Nano-Fit_105313-xx06_1x06_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx06, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -6 -6 -Connector_Molex -Molex_Nano-Fit_105313-xx07_1x07_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx07, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -7 -7 -Connector_Molex -Molex_Nano-Fit_105313-xx08_1x08_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105313-xx08, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -8 -8 -Connector_Molex -Molex_Nano-Fit_105314-xx04_2x02_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx04, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -4 -4 -Connector_Molex -Molex_Nano-Fit_105314-xx06_2x03_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -6 -6 -Connector_Molex -Molex_Nano-Fit_105314-xx08_2x04_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -8 -8 -Connector_Molex -Molex_Nano-Fit_105314-xx10_2x05_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -10 -10 -Connector_Molex -Molex_Nano-Fit_105314-xx12_2x06_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -12 -12 -Connector_Molex -Molex_Nano-Fit_105314-xx14_2x07_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -14 -14 -Connector_Molex -Molex_Nano-Fit_105314-xx16_2x08_P2.50mm_Horizontal -Molex Nano-Fit Power Connectors, 105314-xx16, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator -connector Molex Nano-Fit top entry -0 -16 -16 -Connector_Molex -Molex_Panelmate_53780-0270_1x02-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0270 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -4 -3 -Connector_Molex -Molex_Panelmate_53780-0370_1x03-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0370 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -5 -4 -Connector_Molex -Molex_Panelmate_53780-0470_1x04-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0470 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -6 -5 -Connector_Molex -Molex_Panelmate_53780-0570_1x05-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0570 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -7 -6 -Connector_Molex -Molex_Panelmate_53780-0670_1x06-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0670 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -8 -7 -Connector_Molex -Molex_Panelmate_53780-0770_1x07-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0770 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -9 -8 -Connector_Molex -Molex_Panelmate_53780-0870_1x08-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0870 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -10 -9 -Connector_Molex -Molex_Panelmate_53780-0970_1x09-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-0970 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -11 -10 -Connector_Molex -Molex_Panelmate_53780-1070_1x10-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-1070 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -12 -11 -Connector_Molex -Molex_Panelmate_53780-1270_1x12-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-1270 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -14 -13 -Connector_Molex -Molex_Panelmate_53780-1470_1x14-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-1470 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -16 -15 -Connector_Molex -Molex_Panelmate_53780-1570_1x15-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-1570 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -17 -16 -Connector_Molex -Molex_Panelmate_53780-1870_1x18-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-1870 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -20 -19 -Connector_Molex -Molex_Panelmate_53780-3070_1x30-1MP_P1.25mm_Horizontal -Molex Panelmate series connector, 53780-3070 (), generated with kicad-footprint-generator -connector Molex Panelmate top entry -0 -32 -31 -Connector_Molex -Molex_Pico-Clasp_202396-0207_1x02-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0207 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -4 -3 -Connector_Molex -Molex_Pico-Clasp_202396-0307_1x03-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0307 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -5 -4 -Connector_Molex -Molex_Pico-Clasp_202396-0407_1x04-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0407 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -6 -5 -Connector_Molex -Molex_Pico-Clasp_202396-0507_1x05-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0507 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -7 -6 -Connector_Molex -Molex_Pico-Clasp_202396-0607_1x06-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0607 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -8 -7 -Connector_Molex -Molex_Pico-Clasp_202396-0707_1x07-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0707 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -9 -8 -Connector_Molex -Molex_Pico-Clasp_202396-0807_1x08-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0807 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -10 -9 -Connector_Molex -Molex_Pico-Clasp_202396-0907_1x09-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-0907 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -11 -10 -Connector_Molex -Molex_Pico-Clasp_202396-1007_1x10-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-1007 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -12 -11 -Connector_Molex -Molex_Pico-Clasp_202396-1107_1x11-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-1107 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -13 -12 -Connector_Molex -Molex_Pico-Clasp_202396-1207_1x12-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-1207 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -14 -13 -Connector_Molex -Molex_Pico-Clasp_202396-1307_1x13-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-1307 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -15 -14 -Connector_Molex -Molex_Pico-Clasp_202396-1407_1x14-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-1407 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -16 -15 -Connector_Molex -Molex_Pico-Clasp_202396-1507_1x15-1MP_P1.00mm_Horizontal -Molex Pico-Clasp series connector, 202396-1507 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp top entry -0 -17 -16 -Connector_Molex -Molex_Pico-Clasp_501331-0207_1x02-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0207 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -4 -3 -Connector_Molex -Molex_Pico-Clasp_501331-0307_1x03-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0307 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -5 -4 -Connector_Molex -Molex_Pico-Clasp_501331-0407_1x04-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0407 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -6 -5 -Connector_Molex -Molex_Pico-Clasp_501331-0507_1x05-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0507 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -7 -6 -Connector_Molex -Molex_Pico-Clasp_501331-0607_1x06-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0607 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -8 -7 -Connector_Molex -Molex_Pico-Clasp_501331-0707_1x07-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0707 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -9 -8 -Connector_Molex -Molex_Pico-Clasp_501331-0807_1x08-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0807 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -10 -9 -Connector_Molex -Molex_Pico-Clasp_501331-0907_1x09-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-0907 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -11 -10 -Connector_Molex -Molex_Pico-Clasp_501331-1007_1x10-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-1007 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -12 -11 -Connector_Molex -Molex_Pico-Clasp_501331-1107_1x11-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-1107 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -13 -12 -Connector_Molex -Molex_Pico-Clasp_501331-1207_1x12-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-1207 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -14 -13 -Connector_Molex -Molex_Pico-Clasp_501331-1307_1x13-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-1307 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -15 -14 -Connector_Molex -Molex_Pico-Clasp_501331-1407_1x14-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-1407 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -16 -15 -Connector_Molex -Molex_Pico-Clasp_501331-1507_1x15-1MP_P1.00mm_Vertical -Molex Pico-Clasp series connector, 501331-1507 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Clasp side entry -0 -17 -16 -Connector_Molex -Molex_Pico-EZmate_78171-0002_1x02-1MP_P1.20mm_Vertical -Molex Pico-EZmate series connector, 78171-0002 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-EZmate side entry -0 -4 -3 -Connector_Molex -Molex_Pico-EZmate_78171-0003_1x03-1MP_P1.20mm_Vertical -Molex Pico-EZmate series connector, 78171-0003 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-EZmate side entry -0 -5 -4 -Connector_Molex -Molex_Pico-EZmate_78171-0004_1x04-1MP_P1.20mm_Vertical -Molex Pico-EZmate series connector, 78171-0004 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-EZmate side entry -0 -6 -5 -Connector_Molex -Molex_Pico-EZmate_78171-0005_1x05-1MP_P1.20mm_Vertical -Molex Pico-EZmate series connector, 78171-0005 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-EZmate side entry -0 -7 -6 -Connector_Molex -Molex_Pico-EZmate_Slim_202656-0021_1x02-1MP_P1.20mm_Vertical -Molex Pico-EZmate_Slim series connector, 202656-0021 (http://www.molex.com/pdm_docs/sd/2026560021_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-EZmate_Slim side entry -0 -4 -3 -Connector_Molex -Molex_Pico-Lock_504050-0491_1x04-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-0491 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -6 -5 -Connector_Molex -Molex_Pico-Lock_504050-0591_1x05-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-0591 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -7 -6 -Connector_Molex -Molex_Pico-Lock_504050-0691_1x06-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-0691 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -8 -7 -Connector_Molex -Molex_Pico-Lock_504050-0791_1x07-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-0791 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -9 -8 -Connector_Molex -Molex_Pico-Lock_504050-0891_1x08-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-0891 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -10 -9 -Connector_Molex -Molex_Pico-Lock_504050-1091_1x10-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-1091 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -12 -11 -Connector_Molex -Molex_Pico-Lock_504050-1291_1x12-1MP_P1.50mm_Horizontal -Molex Pico-Lock series connector, 504050-1291 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator -connector Molex Pico-Lock top entry -0 -14 -13 -Connector_Molex -Molex_PicoBlade_53047-0210_1x02_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0210, 2 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -2 -2 -Connector_Molex -Molex_PicoBlade_53047-0310_1x03_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0310, 3 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -3 -3 -Connector_Molex -Molex_PicoBlade_53047-0410_1x04_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0410, 4 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -4 -4 -Connector_Molex -Molex_PicoBlade_53047-0510_1x05_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -5 -5 -Connector_Molex -Molex_PicoBlade_53047-0610_1x06_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0610, 6 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -6 -6 -Connector_Molex -Molex_PicoBlade_53047-0710_1x07_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0710, 7 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -7 -7 -Connector_Molex -Molex_PicoBlade_53047-0810_1x08_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0810, 8 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -8 -8 -Connector_Molex -Molex_PicoBlade_53047-0910_1x09_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-0910, 9 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -9 -9 -Connector_Molex -Molex_PicoBlade_53047-1010_1x10_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-1010, 10 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -10 -10 -Connector_Molex -Molex_PicoBlade_53047-1110_1x11_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-1110, 11 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -11 -11 -Connector_Molex -Molex_PicoBlade_53047-1210_1x12_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-1210, 12 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -12 -12 -Connector_Molex -Molex_PicoBlade_53047-1310_1x13_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-1310, 13 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -13 -13 -Connector_Molex -Molex_PicoBlade_53047-1410_1x14_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-1410, 14 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -14 -14 -Connector_Molex -Molex_PicoBlade_53047-1510_1x15_P1.25mm_Vertical -Molex PicoBlade Connector System, 53047-1510, 15 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -15 -15 -Connector_Molex -Molex_PicoBlade_53048-0210_1x02_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0210, 2 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -2 -2 -Connector_Molex -Molex_PicoBlade_53048-0310_1x03_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0310, 3 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -3 -3 -Connector_Molex -Molex_PicoBlade_53048-0410_1x04_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0410, 4 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -4 -4 -Connector_Molex -Molex_PicoBlade_53048-0510_1x05_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -5 -5 -Connector_Molex -Molex_PicoBlade_53048-0610_1x06_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0610, 6 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -6 -6 -Connector_Molex -Molex_PicoBlade_53048-0710_1x07_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0710, 7 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -7 -7 -Connector_Molex -Molex_PicoBlade_53048-0810_1x08_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0810, 8 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -8 -8 -Connector_Molex -Molex_PicoBlade_53048-0910_1x09_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-0910, 9 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -9 -9 -Connector_Molex -Molex_PicoBlade_53048-1010_1x10_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-1010, 10 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -10 -10 -Connector_Molex -Molex_PicoBlade_53048-1110_1x11_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-1110, 11 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -11 -11 -Connector_Molex -Molex_PicoBlade_53048-1210_1x12_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-1210, 12 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -12 -12 -Connector_Molex -Molex_PicoBlade_53048-1310_1x13_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-1310, 13 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -13 -13 -Connector_Molex -Molex_PicoBlade_53048-1410_1x14_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-1410, 14 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -14 -14 -Connector_Molex -Molex_PicoBlade_53048-1510_1x15_P1.25mm_Horizontal -Molex PicoBlade Connector System, 53048-1510, 15 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -15 -15 -Connector_Molex -Molex_PicoBlade_53261-0271_1x02-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -4 -3 -Connector_Molex -Molex_PicoBlade_53261-0371_1x03-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0371 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -5 -4 -Connector_Molex -Molex_PicoBlade_53261-0471_1x04-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0471 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -6 -5 -Connector_Molex -Molex_PicoBlade_53261-0571_1x05-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0571 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -7 -6 -Connector_Molex -Molex_PicoBlade_53261-0671_1x06-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0671 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -8 -7 -Connector_Molex -Molex_PicoBlade_53261-0771_1x07-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -9 -8 -Connector_Molex -Molex_PicoBlade_53261-0871_1x08-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0871 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -10 -9 -Connector_Molex -Molex_PicoBlade_53261-0971_1x09-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-0971 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -11 -10 -Connector_Molex -Molex_PicoBlade_53261-1071_1x10-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1071 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -12 -11 -Connector_Molex -Molex_PicoBlade_53261-1171_1x11-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1171 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -13 -12 -Connector_Molex -Molex_PicoBlade_53261-1271_1x12-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -14 -13 -Connector_Molex -Molex_PicoBlade_53261-1371_1x13-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1371 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -15 -14 -Connector_Molex -Molex_PicoBlade_53261-1471_1x14-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1471 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -16 -15 -Connector_Molex -Molex_PicoBlade_53261-1571_1x15-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1571 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -17 -16 -Connector_Molex -Molex_PicoBlade_53261-1771_1x17-1MP_P1.25mm_Horizontal -Molex PicoBlade series connector, 53261-1771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade top entry -0 -19 -18 -Connector_Molex -Molex_PicoBlade_53398-0271_1x02-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0271 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -4 -3 -Connector_Molex -Molex_PicoBlade_53398-0371_1x03-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0371 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -5 -4 -Connector_Molex -Molex_PicoBlade_53398-0471_1x04-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0471 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -6 -5 -Connector_Molex -Molex_PicoBlade_53398-0571_1x05-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -7 -6 -Connector_Molex -Molex_PicoBlade_53398-0671_1x06-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0671 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -8 -7 -Connector_Molex -Molex_PicoBlade_53398-0771_1x07-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0771 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -9 -8 -Connector_Molex -Molex_PicoBlade_53398-0871_1x08-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0871 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -10 -9 -Connector_Molex -Molex_PicoBlade_53398-0971_1x09-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-0971 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -11 -10 -Connector_Molex -Molex_PicoBlade_53398-1071_1x10-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-1071 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -12 -11 -Connector_Molex -Molex_PicoBlade_53398-1171_1x11-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-1171 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -13 -12 -Connector_Molex -Molex_PicoBlade_53398-1271_1x12-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-1271 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -14 -13 -Connector_Molex -Molex_PicoBlade_53398-1371_1x13-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-1371 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -15 -14 -Connector_Molex -Molex_PicoBlade_53398-1471_1x14-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-1471 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -16 -15 -Connector_Molex -Molex_PicoBlade_53398-1571_1x15-1MP_P1.25mm_Vertical -Molex PicoBlade series connector, 53398-1571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator -connector Molex PicoBlade side entry -0 -17 -16 -Connector_Molex -Molex_Picoflex_90325-0004_2x02_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0004, 4 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -4 -4 -Connector_Molex -Molex_Picoflex_90325-0006_2x03_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0006, 6 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -6 -6 -Connector_Molex -Molex_Picoflex_90325-0008_2x04_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0008, 8 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -8 -8 -Connector_Molex -Molex_Picoflex_90325-0010_2x05_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0010, 10 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -10 -10 -Connector_Molex -Molex_Picoflex_90325-0012_2x06_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0012, 12 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -12 -12 -Connector_Molex -Molex_Picoflex_90325-0014_2x07_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -14 -14 -Connector_Molex -Molex_Picoflex_90325-0016_2x08_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0016, 16 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -16 -16 -Connector_Molex -Molex_Picoflex_90325-0018_2x09_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0018, 18 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -18 -18 -Connector_Molex -Molex_Picoflex_90325-0020_2x10_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0020, 20 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -20 -20 -Connector_Molex -Molex_Picoflex_90325-0022_2x11_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0022, 22 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -22 -22 -Connector_Molex -Molex_Picoflex_90325-0024_2x12_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0024, 24 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -24 -24 -Connector_Molex -Molex_Picoflex_90325-0026_2x13_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90325-0026, 26 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -26 -26 -Connector_Molex -Molex_Picoflex_90814-0004_2x02_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0004, 4 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -4 -4 -Connector_Molex -Molex_Picoflex_90814-0006_2x03_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0006, 6 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -6 -6 -Connector_Molex -Molex_Picoflex_90814-0008_2x04_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0008, 8 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -8 -8 -Connector_Molex -Molex_Picoflex_90814-0010_2x05_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0010, 10 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -10 -10 -Connector_Molex -Molex_Picoflex_90814-0012_2x06_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0012, 12 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -12 -12 -Connector_Molex -Molex_Picoflex_90814-0014_2x07_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -14 -14 -Connector_Molex -Molex_Picoflex_90814-0016_2x08_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0016, 16 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -16 -16 -Connector_Molex -Molex_Picoflex_90814-0018_2x09_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0018, 18 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -18 -18 -Connector_Molex -Molex_Picoflex_90814-0020_2x10_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0020, 20 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -20 -20 -Connector_Molex -Molex_Picoflex_90814-0022_2x11_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0022, 22 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -22 -22 -Connector_Molex -Molex_Picoflex_90814-0024_2x12_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0024, 24 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -24 -24 -Connector_Molex -Molex_Picoflex_90814-0026_2x13_P1.27mm_Vertical -Molex Picoflex Ribbon-Cable Connectors, 90814-0026, 26 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator -connector Molex Picoflex side entry -0 -26 -26 -Connector_Molex -Molex_SL_171971-0002_1x02_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0002 (compatible alternatives: 171971-0102, 171971-0202), 2 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -2 -2 -Connector_Molex -Molex_SL_171971-0003_1x03_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0003 (compatible alternatives: 171971-0103, 171971-0203), 3 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -3 -3 -Connector_Molex -Molex_SL_171971-0004_1x04_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0004 (compatible alternatives: 171971-0104, 171971-0204), 4 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -4 -4 -Connector_Molex -Molex_SL_171971-0005_1x05_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0005 (compatible alternatives: 171971-0105, 171971-0205), 5 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -5 -5 -Connector_Molex -Molex_SL_171971-0006_1x06_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0006 (compatible alternatives: 171971-0106, 171971-0206), 6 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -6 -6 -Connector_Molex -Molex_SL_171971-0007_1x07_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0007 (compatible alternatives: 171971-0107, 171971-0207), 7 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -7 -7 -Connector_Molex -Molex_SL_171971-0008_1x08_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0008 (compatible alternatives: 171971-0108, 171971-0208), 8 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -8 -8 -Connector_Molex -Molex_SL_171971-0009_1x09_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0009 (compatible alternatives: 171971-0109, 171971-0209), 9 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -9 -9 -Connector_Molex -Molex_SL_171971-0010_1x10_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0010 (compatible alternatives: 171971-0110, 171971-0210), 10 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -10 -10 -Connector_Molex -Molex_SL_171971-0011_1x11_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0011 (compatible alternatives: 171971-0111, 171971-0211), 11 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -11 -11 -Connector_Molex -Molex_SL_171971-0012_1x12_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0012 (compatible alternatives: 171971-0112, 171971-0212), 12 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -12 -12 -Connector_Molex -Molex_SL_171971-0013_1x13_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0013 (compatible alternatives: 171971-0113, 171971-0213), 13 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -13 -13 -Connector_Molex -Molex_SL_171971-0014_1x14_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0014 (compatible alternatives: 171971-0114, 171971-0214), 14 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -14 -14 -Connector_Molex -Molex_SL_171971-0015_1x15_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0015 (compatible alternatives: 171971-0115, 171971-0215), 15 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -15 -15 -Connector_Molex -Molex_SL_171971-0016_1x16_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0016 (compatible alternatives: 171971-0116, 171971-0216), 16 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -16 -16 -Connector_Molex -Molex_SL_171971-0017_1x17_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0017 (compatible alternatives: 171971-0117, 171971-0217), 17 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -17 -17 -Connector_Molex -Molex_SL_171971-0018_1x18_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0018 (compatible alternatives: 171971-0118, 171971-0218), 18 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -18 -18 -Connector_Molex -Molex_SL_171971-0019_1x19_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0019 (compatible alternatives: 171971-0119, 171971-0219), 19 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -19 -19 -Connector_Molex -Molex_SL_171971-0020_1x20_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0020 (compatible alternatives: 171971-0120, 171971-0220), 20 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -20 -20 -Connector_Molex -Molex_SL_171971-0021_1x21_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0021 (compatible alternatives: 171971-0121, 171971-0221), 21 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -21 -21 -Connector_Molex -Molex_SL_171971-0022_1x22_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0022 (compatible alternatives: 171971-0122, 171971-0222), 22 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -22 -22 -Connector_Molex -Molex_SL_171971-0023_1x23_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0023 (compatible alternatives: 171971-0123, 171971-0223), 23 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -23 -23 -Connector_Molex -Molex_SL_171971-0024_1x24_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0024 (compatible alternatives: 171971-0124, 171971-0224), 24 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -24 -24 -Connector_Molex -Molex_SL_171971-0025_1x25_P2.54mm_Vertical -Molex Stackable Linear Connector, 171971-0025 (compatible alternatives: 171971-0125, 171971-0225), 25 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator -connector Molex SL vertical -0 -25 -25 -Connector_Molex -Molex_SPOX_5267-02A_1x02_P2.50mm_Vertical -Molex SPOX Connector System, 5267-02A, 2 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -2 -2 -Connector_Molex -Molex_SPOX_5267-03A_1x03_P2.50mm_Vertical -Molex SPOX Connector System, 5267-03A, 3 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -3 -3 -Connector_Molex -Molex_SPOX_5267-04A_1x04_P2.50mm_Vertical -Molex SPOX Connector System, 5267-04A, 4 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -4 -4 -Connector_Molex -Molex_SPOX_5267-05A_1x05_P2.50mm_Vertical -Molex SPOX Connector System, 5267-05A, 5 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -5 -5 -Connector_Molex -Molex_SPOX_5267-06A_1x06_P2.50mm_Vertical -Molex SPOX Connector System, 5267-06A, 6 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -6 -6 -Connector_Molex -Molex_SPOX_5267-07A_1x07_P2.50mm_Vertical -Molex SPOX Connector System, 5267-07A, 7 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -7 -7 -Connector_Molex -Molex_SPOX_5267-08A_1x08_P2.50mm_Vertical -Molex SPOX Connector System, 5267-08A, 8 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -8 -8 -Connector_Molex -Molex_SPOX_5267-09A_1x09_P2.50mm_Vertical -Molex SPOX Connector System, 5267-09A, 9 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -9 -9 -Connector_Molex -Molex_SPOX_5267-10A_1x10_P2.50mm_Vertical -Molex SPOX Connector System, 5267-10A, 10 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -10 -10 -Connector_Molex -Molex_SPOX_5267-11A_1x11_P2.50mm_Vertical -Molex SPOX Connector System, 5267-11A, 11 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -11 -11 -Connector_Molex -Molex_SPOX_5267-12A_1x12_P2.50mm_Vertical -Molex SPOX Connector System, 5267-12A, 12 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -12 -12 -Connector_Molex -Molex_SPOX_5267-13A_1x13_P2.50mm_Vertical -Molex SPOX Connector System, 5267-13A, 13 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -13 -13 -Connector_Molex -Molex_SPOX_5267-14A_1x14_P2.50mm_Vertical -Molex SPOX Connector System, 5267-14A, 14 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -14 -14 -Connector_Molex -Molex_SPOX_5267-15A_1x15_P2.50mm_Vertical -Molex SPOX Connector System, 5267-15A, 15 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX side entry -0 -15 -15 -Connector_Molex -Molex_SPOX_5268-02A_1x02_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-02A, 2 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -2 -2 -Connector_Molex -Molex_SPOX_5268-03A_1x03_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-03A, 3 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -3 -3 -Connector_Molex -Molex_SPOX_5268-04A_1x04_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-04A, 4 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -4 -4 -Connector_Molex -Molex_SPOX_5268-05A_1x05_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-05A, 5 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -5 -5 -Connector_Molex -Molex_SPOX_5268-06A_1x06_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-06A, 6 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -6 -6 -Connector_Molex -Molex_SPOX_5268-07A_1x07_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-07A, 7 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -7 -7 -Connector_Molex -Molex_SPOX_5268-08A_1x08_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-08A, 8 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -8 -8 -Connector_Molex -Molex_SPOX_5268-09A_1x09_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-09A, 9 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -9 -9 -Connector_Molex -Molex_SPOX_5268-10A_1x10_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-10A, 10 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -10 -10 -Connector_Molex -Molex_SPOX_5268-11A_1x11_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-11A, 11 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -11 -11 -Connector_Molex -Molex_SPOX_5268-12A_1x12_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-12A, 12 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -12 -12 -Connector_Molex -Molex_SPOX_5268-13A_1x13_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-13A, 13 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -13 -13 -Connector_Molex -Molex_SPOX_5268-14A_1x14_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-14A, 14 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -14 -14 -Connector_Molex -Molex_SPOX_5268-15A_1x15_P2.50mm_Horizontal -Molex SPOX Connector System, 5268-15A, 15 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator -connector Molex SPOX horizontal -0 -15 -15 -Connector_Molex -Molex_Sabre_43160-0102_1x02_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-0102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -4 -2 -Connector_Molex -Molex_Sabre_43160-0102_1x02_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-0102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -30 -2 -Connector_Molex -Molex_Sabre_43160-0103_1x03_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-0103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -6 -3 -Connector_Molex -Molex_Sabre_43160-0103_1x03_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-0103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -45 -3 -Connector_Molex -Molex_Sabre_43160-0104_1x04_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-0104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -8 -4 -Connector_Molex -Molex_Sabre_43160-0104_1x04_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-0104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -60 -4 -Connector_Molex -Molex_Sabre_43160-0105_1x05_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-0105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -10 -5 -Connector_Molex -Molex_Sabre_43160-0105_1x05_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-0105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -75 -5 -Connector_Molex -Molex_Sabre_43160-0106_1x06_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-0106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -12 -6 -Connector_Molex -Molex_Sabre_43160-0106_1x06_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-0106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -90 -6 -Connector_Molex -Molex_Sabre_43160-1102_1x02_P7.49mm_Horizontal -Molex Sabre Power Connector, 43160-1102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -6 -2 -Connector_Molex -Molex_Sabre_43160-1102_1x02_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 43160-1102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -32 -2 -Connector_Molex -Molex_Sabre_43160-1103_1x03_P7.49mm_Horizontal -Molex Sabre Power Connector, 43160-1103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -8 -3 -Connector_Molex -Molex_Sabre_43160-1103_1x03_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 43160-1103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -47 -3 -Connector_Molex -Molex_Sabre_43160-1104_1x04_P7.49mm_Horizontal -Molex Sabre Power Connector, 43160-1104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -10 -4 -Connector_Molex -Molex_Sabre_43160-1104_1x04_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 43160-1104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -62 -4 -Connector_Molex -Molex_Sabre_43160-1105_1x05_P7.49mm_Horizontal -Molex Sabre Power Connector, 43160-1105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -12 -5 -Connector_Molex -Molex_Sabre_43160-1105_1x05_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 43160-1105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -77 -5 -Connector_Molex -Molex_Sabre_43160-1106_1x06_P7.49mm_Horizontal -Molex Sabre Power Connector, 43160-1106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -14 -6 -Connector_Molex -Molex_Sabre_43160-1106_1x06_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 43160-1106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -92 -6 -Connector_Molex -Molex_Sabre_43160-2102_1x02_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-2102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -6 -2 -Connector_Molex -Molex_Sabre_43160-2102_1x02_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-2102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -32 -2 -Connector_Molex -Molex_Sabre_43160-2103_1x03_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-2103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -8 -3 -Connector_Molex -Molex_Sabre_43160-2103_1x03_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-2103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -47 -3 -Connector_Molex -Molex_Sabre_43160-2104_1x04_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-2104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -10 -4 -Connector_Molex -Molex_Sabre_43160-2104_1x04_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-2104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -62 -4 -Connector_Molex -Molex_Sabre_43160-2105_1x05_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-2105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -12 -5 -Connector_Molex -Molex_Sabre_43160-2105_1x05_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-2105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -77 -5 -Connector_Molex -Molex_Sabre_43160-2106_1x06_P7.49mm_Vertical -Molex Sabre Power Connector, 43160-2106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -14 -6 -Connector_Molex -Molex_Sabre_43160-2106_1x06_P7.49mm_Vertical_ThermalVias -Molex Sabre Power Connector, 43160-2106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre side entry -0 -92 -6 -Connector_Molex -Molex_Sabre_46007-1102_1x02_P7.49mm_Horizontal -Molex Sabre Power Connector, 46007-1102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -4 -2 -Connector_Molex -Molex_Sabre_46007-1102_1x02_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 46007-1102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -30 -2 -Connector_Molex -Molex_Sabre_46007-1103_1x03_P7.49mm_Horizontal -Molex Sabre Power Connector, 46007-1103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -6 -3 -Connector_Molex -Molex_Sabre_46007-1103_1x03_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 46007-1103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -45 -3 -Connector_Molex -Molex_Sabre_46007-1104_1x04_P7.49mm_Horizontal -Molex Sabre Power Connector, 46007-1104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -8 -4 -Connector_Molex -Molex_Sabre_46007-1104_1x04_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 46007-1104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -60 -4 -Connector_Molex -Molex_Sabre_46007-1105_1x05_P7.49mm_Horizontal -Molex Sabre Power Connector, 46007-1105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -10 -5 -Connector_Molex -Molex_Sabre_46007-1105_1x05_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 46007-1105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -75 -5 -Connector_Molex -Molex_Sabre_46007-1106_1x06_P7.49mm_Horizontal -Molex Sabre Power Connector, 46007-1106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -12 -6 -Connector_Molex -Molex_Sabre_46007-1106_1x06_P7.49mm_Horizontal_ThermalVias -Molex Sabre Power Connector, 46007-1106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator -connector Molex Sabre top entry -0 -90 -6 -Connector_Molex -Molex_SlimStack_52991-0208_2x10_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0208, 20 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -20 -20 -Connector_Molex -Molex_SlimStack_52991-0308_2x15_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0308, 30 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -30 -30 -Connector_Molex -Molex_SlimStack_52991-0408_2x20_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0408, 40 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -40 -40 -Connector_Molex -Molex_SlimStack_52991-0508_2x25_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0508, 50 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -50 -50 -Connector_Molex -Molex_SlimStack_52991-0608_2x30_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0608, 60 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -60 -60 -Connector_Molex -Molex_SlimStack_52991-0708_2x35_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0708, 70 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -70 -70 -Connector_Molex -Molex_SlimStack_52991-0808_2x40_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0808, 80 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack vertical -0 -80 -80 -Connector_Molex -Molex_SlimStack_54722-0164_2x08_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0164, 16 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -16 -16 -Connector_Molex -Molex_SlimStack_54722-0204_2x10_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0204, 20 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -20 -20 -Connector_Molex -Molex_SlimStack_54722-0224_2x11_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0224, 22 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -22 -22 -Connector_Molex -Molex_SlimStack_54722-0244_2x12_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0244, 24 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -24 -24 -Connector_Molex -Molex_SlimStack_54722-0304_2x15_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0304, 30 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -30 -30 -Connector_Molex -Molex_SlimStack_54722-0344_2x17_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0344, 34 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -34 -34 -Connector_Molex -Molex_SlimStack_54722-0404_2x20_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0404, 40 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -40 -40 -Connector_Molex -Molex_SlimStack_54722-0504_2x25_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0504, 50 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -50 -50 -Connector_Molex -Molex_SlimStack_54722-0604_2x30_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0604, 60 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -60 -60 -Connector_Molex -Molex_SlimStack_54722-0804_2x40_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0804, 80 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -80 -80 -Connector_Molex -Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0161, 16 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -16 -16 -Connector_Molex -Molex_SlimStack_55560-0201_2x10_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0201, 20 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -20 -20 -Connector_Molex -Molex_SlimStack_55560-0221_2x11_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0221, 22 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -22 -22 -Connector_Molex -Molex_SlimStack_55560-0241_2x12_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0241, 24 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -24 -24 -Connector_Molex -Molex_SlimStack_55560-0301_2x15_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0301, 30 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -30 -30 -Connector_Molex -Molex_SlimStack_55560-0341_2x17_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0341, 34 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -34 -34 -Connector_Molex -Molex_SlimStack_55560-0401_2x20_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0401, 40 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -40 -40 -Connector_Molex -Molex_SlimStack_55560-0501_2x25_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0501, 50 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -50 -50 -Connector_Molex -Molex_SlimStack_55560-0601_2x30_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0601, 60 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -60 -60 -Connector_Molex -Molex_SlimStack_55560-0801_2x40_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0801, 80 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -80 -80 -Connector_Molex -Molex_SlimStack_501920-3001_2x15_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-3001, 30 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -30 -30 -Connector_Molex -Molex_SlimStack_501920-4001_2x20_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-4001, 40 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -40 -40 -Connector_Molex -Molex_SlimStack_501920-5001_2x25_P0.50mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-5001, 50 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -50 -50 -Connector_Molex -Molex_SlimStack_502426-0810_2x04_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-0810, 8 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -8 -8 -Connector_Molex -Molex_SlimStack_502426-1410_2x07_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-1410, 14 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -14 -14 -Connector_Molex -Molex_SlimStack_502426-2010_2x10_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2010, 20 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -20 -20 -Connector_Molex -Molex_SlimStack_502426-2210_2x11_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2210, 22 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -22 -22 -Connector_Molex -Molex_SlimStack_502426-2410_2x12_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2410, 24 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -24 -24 -Connector_Molex -Molex_SlimStack_502426-2610_2x13_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2610, 26 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -26 -26 -Connector_Molex -Molex_SlimStack_502426-3010_2x15_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3010, 30 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -30 -30 -Connector_Molex -Molex_SlimStack_502426-3210_2x16_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3210, 32 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -32 -32 -Connector_Molex -Molex_SlimStack_502426-3410_2x17_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3410, 34 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -34 -34 -Connector_Molex -Molex_SlimStack_502426-4010_2x20_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-4010, 40 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -40 -40 -Connector_Molex -Molex_SlimStack_502426-4410_2x22_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-4410, 44 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -44 -44 -Connector_Molex -Molex_SlimStack_502426-5010_2x25_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-5010, 50 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -50 -50 -Connector_Molex -Molex_SlimStack_502426-6010_2x30_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-6010, 60 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -60 -60 -Connector_Molex -Molex_SlimStack_502426-6410_2x32_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-6410, 64 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -64 -64 -Connector_Molex -Molex_SlimStack_502426-8010_2x40_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-8010, 80 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -80 -80 -Connector_Molex -Molex_SlimStack_502430-0820_2x04_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-0820, 8 Pins (http://www.molex.com/pdm_docs/sd/5024300820_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -8 -8 -Connector_Molex -Molex_SlimStack_502430-1410_2x07_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-1410, 14 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -14 -14 -Connector_Molex -Molex_SlimStack_502430-2010_2x10_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2010, 20 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -20 -20 -Connector_Molex -Molex_SlimStack_502430-2210_2x11_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2210, 22 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -22 -22 -Connector_Molex -Molex_SlimStack_502430-2410_2x12_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2410, 24 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -24 -24 -Connector_Molex -Molex_SlimStack_502430-2610_2x13_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2610, 26 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -26 -26 -Connector_Molex -Molex_SlimStack_502430-3010_2x15_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3010, 30 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -30 -30 -Connector_Molex -Molex_SlimStack_502430-3210_2x16_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3210, 32 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -32 -32 -Connector_Molex -Molex_SlimStack_502430-3410_2x17_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3410, 34 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -34 -34 -Connector_Molex -Molex_SlimStack_502430-4010_2x20_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-4010, 40 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -40 -40 -Connector_Molex -Molex_SlimStack_502430-4410_2x22_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-4410, 44 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -44 -44 -Connector_Molex -Molex_SlimStack_502430-5010_2x25_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-5010, 50 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -50 -50 -Connector_Molex -Molex_SlimStack_502430-6010_2x30_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-6010, 60 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -60 -60 -Connector_Molex -Molex_SlimStack_502430-6410_2x32_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-6410, 64 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -64 -64 -Connector_Molex -Molex_SlimStack_502430-8010_2x40_P0.40mm_Vertical -Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-8010, 80 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator -connector Molex SlimStack side entry -0 -80 -80 -Connector_Multicomp -Multicomp_MC9A12-1034_2x05_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -10 -10 -Connector_Multicomp -Multicomp_MC9A12-1434_2x07_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -14 -14 -Connector_Multicomp -Multicomp_MC9A12-1634_2x08_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -16 -16 -Connector_Multicomp -Multicomp_MC9A12-2034_2x10_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -20 -20 -Connector_Multicomp -Multicomp_MC9A12-2634_2x13_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -26 -26 -Connector_Multicomp -Multicomp_MC9A12-3434_2x17_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -34 -34 -Connector_Multicomp -Multicomp_MC9A12-4034_2x20_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -40 -40 -Connector_Multicomp -Multicomp_MC9A12-5034_2x25_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -50 -50 -Connector_Multicomp -Multicomp_MC9A12-6034_2x30_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -60 -60 -Connector_Multicomp -Multicomp_MC9A12-6434_2x32_P2.54mm_Vertical -http://www.farnell.com/datasheets/1520732.pdf -connector multicomp MC9A MC9A12 -0 -64 -64 -Connector_Multicomp -Multicomp_MC9A22-1034_2x05_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -10 -10 -Connector_Multicomp -Multicomp_MC9A22-1434_2x07_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -14 -14 -Connector_Multicomp -Multicomp_MC9A22-1634_2x08_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -16 -16 -Connector_Multicomp -Multicomp_MC9A22-2034_2x10_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -20 -20 -Connector_Multicomp -Multicomp_MC9A22-2634_2x13_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -26 -26 -Connector_Multicomp -Multicomp_MC9A22-3434_2x17_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -34 -34 -Connector_Multicomp -Multicomp_MC9A22-4034_2x20_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -40 -40 -Connector_Multicomp -Multicomp_MC9A22-5034_2x25_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -50 -50 -Connector_Multicomp -Multicomp_MC9A22-6034_2x30_P2.54mm_Horizontal -http://www.farnell.com/cad/360651.pdf -connector multicomp MC9A MC9A22 -0 -60 -60 -Connector_PCBEdge -4UCON_10156_2x40_P1.27mm_Socket_Horizontal -4UCON 10156 Card edge socket with 80 contacts (40 each side), through-hole, http://www.4uconnector.com/online/object/4udrawing/10156.pdf -4UCON 10156 Card edge socket with 80 contacts -0 -80 -80 -Connector_PCBEdge -BUS_AT -AT ISA 16 bits Bus Edge Connector -BUS ISA AT Edge connector -0 -98 -98 -Connector_PCBEdge -BUS_PCI -PCI bus Edge Connector -PCI bus Edge Connector -0 -240 -120 -Connector_PCBEdge -BUS_PCIexpress_x1 -PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 -PCIe -0 -36 -36 -Connector_PCBEdge -BUS_PCIexpress_x4 -PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 -PCIe -0 -64 -64 -Connector_PCBEdge -BUS_PCIexpress_x8 -PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 -PCIe -0 -98 -98 -Connector_PCBEdge -BUS_PCIexpress_x16 -PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 -PCIe -0 -164 -164 -Connector_PCBEdge -Samtec_MECF-05-0_-L-DV_2x05_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 05 contacts (polarized) -conn samtec card-edge high-speed -0 -8 -8 -Connector_PCBEdge -Samtec_MECF-05-0_-NP-L-DV_2x05_P1.27mm_Edge -Highspeed card edge connector for PCB's with 05 contacts (not polarized) -conn samtec card-edge high-speed -0 -10 -10 -Connector_PCBEdge -Samtec_MECF-05-01-L-DV-WT_2x05_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 05 contacts (polarized) -conn samtec card-edge high-speed -0 -10 -8 -Connector_PCBEdge -Samtec_MECF-05-01-L-DV_2x05_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 05 contacts (polarized) -conn samtec card-edge high-speed -0 -8 -8 -Connector_PCBEdge -Samtec_MECF-05-01-NP-L-DV-WT_2x05_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 05 contacts (not polarized) -conn samtec card-edge high-speed -0 -12 -10 -Connector_PCBEdge -Samtec_MECF-05-01-NP-L-DV_2x05_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 05 contacts (not polarized) -conn samtec card-edge high-speed -0 -10 -10 -Connector_PCBEdge -Samtec_MECF-05-02-L-DV-WT_2x05_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized) -conn samtec card-edge high-speed -0 -10 -8 -Connector_PCBEdge -Samtec_MECF-05-02-L-DV_2x05_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized) -conn samtec card-edge high-speed -0 -8 -8 -Connector_PCBEdge -Samtec_MECF-05-02-NP-L-DV-WT_2x05_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 05 contacts (not polarized) -conn samtec card-edge high-speed -0 -12 -10 -Connector_PCBEdge -Samtec_MECF-05-02-NP-L-DV_2x05_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 05 contacts (not polarized) -conn samtec card-edge high-speed -0 -10 -10 -Connector_PCBEdge -Samtec_MECF-08-0_-L-DV_2x08_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 08 contacts (polarized) -conn samtec card-edge high-speed -0 -14 -14 -Connector_PCBEdge -Samtec_MECF-08-0_-NP-L-DV_2x08_P1.27mm_Edge -Highspeed card edge connector for PCB's with 08 contacts (not polarized) -conn samtec card-edge high-speed -0 -16 -16 -Connector_PCBEdge -Samtec_MECF-08-01-L-DV-WT_2x08_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 08 contacts (polarized) -conn samtec card-edge high-speed -0 -16 -14 -Connector_PCBEdge -Samtec_MECF-08-01-L-DV_2x08_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 08 contacts (polarized) -conn samtec card-edge high-speed -0 -14 -14 -Connector_PCBEdge -Samtec_MECF-08-01-NP-L-DV-WT_2x08_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 08 contacts (not polarized) -conn samtec card-edge high-speed -0 -18 -16 -Connector_PCBEdge -Samtec_MECF-08-01-NP-L-DV_2x08_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 08 contacts (not polarized) -conn samtec card-edge high-speed -0 -16 -16 -Connector_PCBEdge -Samtec_MECF-08-02-L-DV-WT_2x08_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 08 contacts (polarized) -conn samtec card-edge high-speed -0 -16 -14 -Connector_PCBEdge -Samtec_MECF-08-02-L-DV_2x08_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 08 contacts (polarized) -conn samtec card-edge high-speed -0 -14 -14 -Connector_PCBEdge -Samtec_MECF-08-02-NP-L-DV-WT_2x08_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized) -conn samtec card-edge high-speed -0 -18 -16 -Connector_PCBEdge -Samtec_MECF-08-02-NP-L-DV_2x08_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized) -conn samtec card-edge high-speed -0 -16 -16 -Connector_PCBEdge -Samtec_MECF-20-0_-L-DV_2x20_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 20 contacts (polarized) -conn samtec card-edge high-speed -0 -38 -38 -Connector_PCBEdge -Samtec_MECF-20-0_-NP-L-DV_2x20_P1.27mm_Edge -Highspeed card edge connector for PCB's with 20 contacts (not polarized) -conn samtec card-edge high-speed -0 -40 -40 -Connector_PCBEdge -Samtec_MECF-20-01-L-DV-WT_2x20_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 20 contacts (polarized) -conn samtec card-edge high-speed -0 -40 -38 -Connector_PCBEdge -Samtec_MECF-20-01-L-DV_2x20_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 20 contacts (polarized) -conn samtec card-edge high-speed -0 -38 -38 -Connector_PCBEdge -Samtec_MECF-20-01-NP-L-DV-WT_2x20_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 20 contacts (not polarized) -conn samtec card-edge high-speed -0 -42 -40 -Connector_PCBEdge -Samtec_MECF-20-01-NP-L-DV_2x20_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 20 contacts (not polarized) -conn samtec card-edge high-speed -0 -40 -40 -Connector_PCBEdge -Samtec_MECF-20-02-L-DV-WT_2x20_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 20 contacts (polarized) -conn samtec card-edge high-speed -0 -40 -38 -Connector_PCBEdge -Samtec_MECF-20-02-L-DV_2x20_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 20 contacts (polarized) -conn samtec card-edge high-speed -0 -38 -38 -Connector_PCBEdge -Samtec_MECF-20-02-NP-L-DV-WT_2x20_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 20 contacts (not polarized) -conn samtec card-edge high-speed -0 -42 -40 -Connector_PCBEdge -Samtec_MECF-20-02-NP-L-DV_2x20_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 20 contacts (not polarized) -conn samtec card-edge high-speed -0 -40 -40 -Connector_PCBEdge -Samtec_MECF-30-0_-L-DV_2x30_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 30 contacts (polarized) -conn samtec card-edge high-speed -0 -58 -58 -Connector_PCBEdge -Samtec_MECF-30-0_-NP-L-DV_2x30_P1.27mm_Edge -Highspeed card edge connector for PCB's with 30 contacts (not polarized) -conn samtec card-edge high-speed -0 -60 -60 -Connector_PCBEdge -Samtec_MECF-30-01-L-DV-WT_2x30_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized) -conn samtec card-edge high-speed -0 -60 -58 -Connector_PCBEdge -Samtec_MECF-30-01-L-DV_2x30_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized) -conn samtec card-edge high-speed -0 -58 -58 -Connector_PCBEdge -Samtec_MECF-30-01-NP-L-DV-WT_2x30_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized) -conn samtec card-edge high-speed -0 -62 -60 -Connector_PCBEdge -Samtec_MECF-30-01-NP-L-DV_2x30_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized) -conn samtec card-edge high-speed -0 -60 -60 -Connector_PCBEdge -Samtec_MECF-30-02-L-DV-WT_2x30_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 30 contacts (polarized) -conn samtec card-edge high-speed -0 -60 -58 -Connector_PCBEdge -Samtec_MECF-30-02-L-DV_2x30_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 30 contacts (polarized) -conn samtec card-edge high-speed -0 -58 -58 -Connector_PCBEdge -Samtec_MECF-30-02-NP-L-DV-WT_2x30_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized) -conn samtec card-edge high-speed -0 -62 -60 -Connector_PCBEdge -Samtec_MECF-30-02-NP-L-DV_2x30_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized) -conn samtec card-edge high-speed -0 -60 -60 -Connector_PCBEdge -Samtec_MECF-40-0_-L-DV_2x40_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 40 contacts (polarized) -conn samtec card-edge high-speed -0 -78 -78 -Connector_PCBEdge -Samtec_MECF-40-0_-NP-L-DV_2x40_P1.27mm_Edge -Highspeed card edge connector for PCB's with 40 contacts (not polarized) -conn samtec card-edge high-speed -0 -80 -80 -Connector_PCBEdge -Samtec_MECF-40-01-L-DV-WT_2x40_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 40 contacts (polarized) -conn samtec card-edge high-speed -0 -80 -78 -Connector_PCBEdge -Samtec_MECF-40-01-L-DV_2x40_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 40 contacts (polarized) -conn samtec card-edge high-speed -0 -78 -78 -Connector_PCBEdge -Samtec_MECF-40-01-NP-L-DV-WT_2x40_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 40 contacts (not polarized) -conn samtec card-edge high-speed -0 -82 -80 -Connector_PCBEdge -Samtec_MECF-40-01-NP-L-DV_2x40_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 40 contacts (not polarized) -conn samtec card-edge high-speed -0 -80 -80 -Connector_PCBEdge -Samtec_MECF-40-02-L-DV-WT_2x40_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 40 contacts (polarized) -conn samtec card-edge high-speed -0 -80 -78 -Connector_PCBEdge -Samtec_MECF-40-02-L-DV_2x40_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 40 contacts (polarized) -conn samtec card-edge high-speed -0 -78 -78 -Connector_PCBEdge -Samtec_MECF-40-02-NP-L-DV-WT_2x40_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized) -conn samtec card-edge high-speed -0 -82 -80 -Connector_PCBEdge -Samtec_MECF-40-02-NP-L-DV_2x40_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized) -conn samtec card-edge high-speed -0 -80 -80 -Connector_PCBEdge -Samtec_MECF-50-0_-L-DV_2x50_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 50 contacts (polarized) -conn samtec card-edge high-speed -0 -98 -98 -Connector_PCBEdge -Samtec_MECF-50-0_-NP-L-DV_2x50_P1.27mm_Edge -Highspeed card edge connector for PCB's with 50 contacts (not polarized) -conn samtec card-edge high-speed -0 -100 -100 -Connector_PCBEdge -Samtec_MECF-50-01-L-DV-WT_2x50_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized) -conn samtec card-edge high-speed -0 -100 -98 -Connector_PCBEdge -Samtec_MECF-50-01-L-DV_2x50_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized) -conn samtec card-edge high-speed -0 -98 -98 -Connector_PCBEdge -Samtec_MECF-50-01-NP-L-DV-WT_2x50_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 50 contacts (not polarized) -conn samtec card-edge high-speed -0 -102 -100 -Connector_PCBEdge -Samtec_MECF-50-01-NP-L-DV_2x50_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 50 contacts (not polarized) -conn samtec card-edge high-speed -0 -100 -100 -Connector_PCBEdge -Samtec_MECF-50-02-L-DV-WT_2x50_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 50 contacts (polarized) -conn samtec card-edge high-speed -0 -100 -98 -Connector_PCBEdge -Samtec_MECF-50-02-L-DV_2x50_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 50 contacts (polarized) -conn samtec card-edge high-speed -0 -98 -98 -Connector_PCBEdge -Samtec_MECF-50-02-NP-L-DV-WT_2x50_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 50 contacts (not polarized) -conn samtec card-edge high-speed -0 -102 -100 -Connector_PCBEdge -Samtec_MECF-50-02-NP-L-DV_2x50_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 50 contacts (not polarized) -conn samtec card-edge high-speed -0 -100 -100 -Connector_PCBEdge -Samtec_MECF-60-0_-L-DV_2x60_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 60 contacts (polarized) -conn samtec card-edge high-speed -0 -116 -116 -Connector_PCBEdge -Samtec_MECF-60-0_-NP-L-DV_2x60_P1.27mm_Edge -Highspeed card edge connector for PCB's with 60 contacts (not polarized) -conn samtec card-edge high-speed -0 -120 -120 -Connector_PCBEdge -Samtec_MECF-60-01-L-DV-WT_2x60_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 60 contacts (polarized) -conn samtec card-edge high-speed -0 -118 -116 -Connector_PCBEdge -Samtec_MECF-60-01-L-DV_2x60_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 60 contacts (polarized) -conn samtec card-edge high-speed -0 -116 -116 -Connector_PCBEdge -Samtec_MECF-60-01-NP-L-DV-WT_2x60_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 60 contacts (not polarized) -conn samtec card-edge high-speed -0 -122 -120 -Connector_PCBEdge -Samtec_MECF-60-01-NP-L-DV_2x60_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 60 contacts (not polarized) -conn samtec card-edge high-speed -0 -120 -120 -Connector_PCBEdge -Samtec_MECF-60-02-L-DV-WT_2x60_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 60 contacts (polarized) -conn samtec card-edge high-speed -0 -118 -116 -Connector_PCBEdge -Samtec_MECF-60-02-L-DV_2x60_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 60 contacts (polarized) -conn samtec card-edge high-speed -0 -116 -116 -Connector_PCBEdge -Samtec_MECF-60-02-NP-L-DV-WT_2x60_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 60 contacts (not polarized) -conn samtec card-edge high-speed -0 -122 -120 -Connector_PCBEdge -Samtec_MECF-60-02-NP-L-DV_2x60_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 60 contacts (not polarized) -conn samtec card-edge high-speed -0 -120 -120 -Connector_PCBEdge -Samtec_MECF-70-0_-L-DV_2x70_P1.27mm_Polarized_Edge -Highspeed card edge connector for PCB's with 70 contacts (polarized) -conn samtec card-edge high-speed -0 -136 -136 -Connector_PCBEdge -Samtec_MECF-70-0_-NP-L-DV_2x70_P1.27mm_Edge -Highspeed card edge connector for PCB's with 70 contacts (not polarized) -conn samtec card-edge high-speed -0 -140 -140 -Connector_PCBEdge -Samtec_MECF-70-01-L-DV-WT_2x70_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 70 contacts (polarized) -conn samtec card-edge high-speed -0 -138 -136 -Connector_PCBEdge -Samtec_MECF-70-01-L-DV_2x70_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 70 contacts (polarized) -conn samtec card-edge high-speed -0 -136 -136 -Connector_PCBEdge -Samtec_MECF-70-01-NP-L-DV-WT_2x70_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 70 contacts (not polarized) -conn samtec card-edge high-speed -0 -142 -140 -Connector_PCBEdge -Samtec_MECF-70-01-NP-L-DV_2x70_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 1.6mm PCB's with 70 contacts (not polarized) -conn samtec card-edge high-speed -0 -140 -140 -Connector_PCBEdge -Samtec_MECF-70-02-L-DV-WT_2x70_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 70 contacts (polarized) -conn samtec card-edge high-speed -0 -138 -136 -Connector_PCBEdge -Samtec_MECF-70-02-L-DV_2x70_P1.27mm_Polarized_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 70 contacts (polarized) -conn samtec card-edge high-speed -0 -136 -136 -Connector_PCBEdge -Samtec_MECF-70-02-NP-L-DV-WT_2x70_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 70 contacts (not polarized) -conn samtec card-edge high-speed -0 -142 -140 -Connector_PCBEdge -Samtec_MECF-70-02-NP-L-DV_2x70_P1.27mm_Socket_Horizontal -Highspeed card edge connector for 2.4mm PCB's with 70 contacts (not polarized) -conn samtec card-edge high-speed -0 -140 -140 -Connector_PCBEdge -molex_EDGELOCK_2-CKT -https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf -Connector PCBEdge molex EDGELOCK -0 -2 -2 -Connector_PCBEdge -molex_EDGELOCK_4-CKT -https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf -Connector PCBEdge molex EDGELOCK -0 -4 -4 -Connector_PCBEdge -molex_EDGELOCK_6-CKT -https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf -Connector PCBEdge molex EDGELOCK -0 -6 -6 -Connector_PCBEdge -molex_EDGELOCK_8-CKT -https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf -Connector PCBEdge molex EDGELOCK -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_2-G-7,62_1x02_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/2-G-7,62; number of pins: 02; pin pitch: 7.62mm; Angled || order number: 1766233 12A 630V -phoenix_contact connector GMSTBA_01x02_G_7.62mm -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_2-G_1x02_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/2-G; number of pins: 02; pin pitch: 7.50mm; Angled || order number: 1766343 12A 630V -phoenix_contact connector GMSTBA_01x02_G_7.50mm -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_3-G-7,62_1x03_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/3-G-7,62; number of pins: 03; pin pitch: 7.62mm; Angled || order number: 1766246 12A 630V -phoenix_contact connector GMSTBA_01x03_G_7.62mm -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_3-G_1x03_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/3-G; number of pins: 03; pin pitch: 7.50mm; Angled || order number: 1766356 12A 630V -phoenix_contact connector GMSTBA_01x03_G_7.50mm -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_4-G-7,62_1x04_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/4-G-7,62; number of pins: 04; pin pitch: 7.62mm; Angled || order number: 1766259 12A 630V -phoenix_contact connector GMSTBA_01x04_G_7.62mm -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_4-G_1x04_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/4-G; number of pins: 04; pin pitch: 7.50mm; Angled || order number: 1766369 12A 630V -phoenix_contact connector GMSTBA_01x04_G_7.50mm -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_5-G-7,62_1x05_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/5-G-7,62; number of pins: 05; pin pitch: 7.62mm; Angled || order number: 1766262 12A 630V -phoenix_contact connector GMSTBA_01x05_G_7.62mm -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_5-G_1x05_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/5-G; number of pins: 05; pin pitch: 7.50mm; Angled || order number: 1766372 12A 630V -phoenix_contact connector GMSTBA_01x05_G_7.50mm -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_6-G-7,62_1x06_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/6-G-7,62; number of pins: 06; pin pitch: 7.62mm; Angled || order number: 1766275 12A 630V -phoenix_contact connector GMSTBA_01x06_G_7.62mm -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_6-G_1x06_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/6-G; number of pins: 06; pin pitch: 7.50mm; Angled || order number: 1766385 12A 630V -phoenix_contact connector GMSTBA_01x06_G_7.50mm -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_7-G-7,62_1x07_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/7-G-7,62; number of pins: 07; pin pitch: 7.62mm; Angled || order number: 1766288 12A 630V -phoenix_contact connector GMSTBA_01x07_G_7.62mm -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_7-G_1x07_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/7-G; number of pins: 07; pin pitch: 7.50mm; Angled || order number: 1766398 12A 630V -phoenix_contact connector GMSTBA_01x07_G_7.50mm -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_8-G-7,62_1x08_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/8-G-7,62; number of pins: 08; pin pitch: 7.62mm; Angled || order number: 1766291 12A 630V -phoenix_contact connector GMSTBA_01x08_G_7.62mm -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_8-G_1x08_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/8-G; number of pins: 08; pin pitch: 7.50mm; Angled || order number: 1766408 12A 630V -phoenix_contact connector GMSTBA_01x08_G_7.50mm -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_9-G-7,62_1x09_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/9-G-7,62; number of pins: 09; pin pitch: 7.62mm; Angled || order number: 1766301 12A 630V -phoenix_contact connector GMSTBA_01x09_G_7.62mm -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_9-G_1x09_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/9-G; number of pins: 09; pin pitch: 7.50mm; Angled || order number: 1766411 12A 630V -phoenix_contact connector GMSTBA_01x09_G_7.50mm -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_10-G-7,62_1x10_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/10-G-7,62; number of pins: 10; pin pitch: 7.62mm; Angled || order number: 1766314 12A 630V -phoenix_contact connector GMSTBA_01x10_G_7.62mm -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_10-G_1x10_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/10-G; number of pins: 10; pin pitch: 7.50mm; Angled || order number: 1766424 12A 630V -phoenix_contact connector GMSTBA_01x10_G_7.50mm -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_11-G-7,62_1x11_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/11-G-7,62; number of pins: 11; pin pitch: 7.62mm; Angled || order number: 1766327 12A 630V -phoenix_contact connector GMSTBA_01x11_G_7.62mm -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_11-G_1x11_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/11-G; number of pins: 11; pin pitch: 7.50mm; Angled || order number: 1766437 12A 630V -phoenix_contact connector GMSTBA_01x11_G_7.50mm -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_12-G-7,62_1x12_P7.62mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/12-G-7,62; number of pins: 12; pin pitch: 7.62mm; Angled || order number: 1766330 12A 630V -phoenix_contact connector GMSTBA_01x12_G_7.62mm -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBA_2,5_12-G_1x12_P7.50mm_Horizontal -Generic Phoenix Contact connector footprint for: GMSTBA_2,5/12-G; number of pins: 12; pin pitch: 7.50mm; Angled || order number: 1766440 12A 630V -phoenix_contact connector GMSTBA_01x12_G_7.50mm -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_2-G-7,62_1x02_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/2-G-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical || order number: 1766770 12A 630V -phoenix_contact connector GMSTBVA_01x02_G_7.62mm -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_2-G_1x02_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/2-G; number of pins: 02; pin pitch: 7.50mm; Vertical || order number: 1766660 12A 630V -phoenix_contact connector GMSTBVA_01x02_G_7.50mm -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_3-G-7,62_1x03_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/3-G-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical || order number: 1766783 12A 630V -phoenix_contact connector GMSTBVA_01x03_G_7.62mm -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_3-G_1x03_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/3-G; number of pins: 03; pin pitch: 7.50mm; Vertical || order number: 1766673 12A 630V -phoenix_contact connector GMSTBVA_01x03_G_7.50mm -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_4-G-7,62_1x04_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/4-G-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical || order number: 1766796 12A 630V -phoenix_contact connector GMSTBVA_01x04_G_7.62mm -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_4-G_1x04_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/4-G; number of pins: 04; pin pitch: 7.50mm; Vertical || order number: 1766686 12A 630V -phoenix_contact connector GMSTBVA_01x04_G_7.50mm -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_5-G-7,62_1x05_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/5-G-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical || order number: 1766806 12A 630V -phoenix_contact connector GMSTBVA_01x05_G_7.62mm -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_5-G_1x05_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/5-G; number of pins: 05; pin pitch: 7.50mm; Vertical || order number: 1766699 12A 630V -phoenix_contact connector GMSTBVA_01x05_G_7.50mm -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_6-G-7,62_1x06_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/6-G-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical || order number: 1766819 12A 630V -phoenix_contact connector GMSTBVA_01x06_G_7.62mm -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_6-G_1x06_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/6-G; number of pins: 06; pin pitch: 7.50mm; Vertical || order number: 1766709 12A 630V -phoenix_contact connector GMSTBVA_01x06_G_7.50mm -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_7-G-7,62_1x07_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/7-G-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical || order number: 1766822 12A 630V -phoenix_contact connector GMSTBVA_01x07_G_7.62mm -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_7-G_1x07_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/7-G; number of pins: 07; pin pitch: 7.50mm; Vertical || order number: 1766712 12A 630V -phoenix_contact connector GMSTBVA_01x07_G_7.50mm -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_8-G-7,62_1x08_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/8-G-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical || order number: 1766835 12A 630V -phoenix_contact connector GMSTBVA_01x08_G_7.62mm -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_8-G_1x08_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/8-G; number of pins: 08; pin pitch: 7.50mm; Vertical || order number: 1766725 12A 630V -phoenix_contact connector GMSTBVA_01x08_G_7.50mm -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_9-G-7,62_1x09_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/9-G-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical || order number: 1766848 12A 630V -phoenix_contact connector GMSTBVA_01x09_G_7.62mm -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_9-G_1x09_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/9-G; number of pins: 09; pin pitch: 7.50mm; Vertical || order number: 1766738 12A 630V -phoenix_contact connector GMSTBVA_01x09_G_7.50mm -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_10-G-7,62_1x10_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/10-G-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical || order number: 1766851 12A 630V -phoenix_contact connector GMSTBVA_01x10_G_7.62mm -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_10-G_1x10_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/10-G; number of pins: 10; pin pitch: 7.50mm; Vertical || order number: 1766741 12A 630V -phoenix_contact connector GMSTBVA_01x10_G_7.50mm -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_11-G-7,62_1x11_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/11-G-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical || order number: 1766864 12A 630V -phoenix_contact connector GMSTBVA_01x11_G_7.62mm -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_11-G_1x11_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/11-G; number of pins: 11; pin pitch: 7.50mm; Vertical || order number: 1766754 12A 630V -phoenix_contact connector GMSTBVA_01x11_G_7.50mm -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_12-G-7,62_1x12_P7.62mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/12-G-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical || order number: 1766877 12A 630V -phoenix_contact connector GMSTBVA_01x12_G_7.62mm -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBVA_2,5_12-G_1x12_P7.50mm_Vertical -Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/12-G; number of pins: 12; pin pitch: 7.50mm; Vertical || order number: 1766767 12A 630V -phoenix_contact connector GMSTBVA_01x12_G_7.50mm -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_2-GF-7,62_1x02_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829154 12A 630V -phoenix_contact connector GMSTBV_01x02_GF_7.62mm -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_2-GF-7,62_1x02_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829154 12A 630V -phoenix_contact connector GMSTBV_01x02_GF_7.62mm_MH -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_3-GF-7,62_1x03_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829167 12A 630V -phoenix_contact connector GMSTBV_01x03_GF_7.62mm -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_3-GF-7,62_1x03_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829167 12A 630V -phoenix_contact connector GMSTBV_01x03_GF_7.62mm_MH -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_4-GF-7,62_1x04_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829170 12A 630V -phoenix_contact connector GMSTBV_01x04_GF_7.62mm -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_4-GF-7,62_1x04_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829170 12A 630V -phoenix_contact connector GMSTBV_01x04_GF_7.62mm_MH -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_5-GF-7,62_1x05_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829183 12A 630V -phoenix_contact connector GMSTBV_01x05_GF_7.62mm -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_5-GF-7,62_1x05_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829183 12A 630V -phoenix_contact connector GMSTBV_01x05_GF_7.62mm_MH -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_6-GF-7,62_1x06_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829196 12A 630V -phoenix_contact connector GMSTBV_01x06_GF_7.62mm -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_6-GF-7,62_1x06_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829196 12A 630V -phoenix_contact connector GMSTBV_01x06_GF_7.62mm_MH -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_7-GF-7,62_1x07_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829206 12A 630V -phoenix_contact connector GMSTBV_01x07_GF_7.62mm -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_7-GF-7,62_1x07_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829206 12A 630V -phoenix_contact connector GMSTBV_01x07_GF_7.62mm_MH -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_8-GF-7,62_1x08_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829219 12A 630V -phoenix_contact connector GMSTBV_01x08_GF_7.62mm -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_8-GF-7,62_1x08_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829219 12A 630V -phoenix_contact connector GMSTBV_01x08_GF_7.62mm_MH -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_9-GF-7,62_1x09_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829222 12A 630V -phoenix_contact connector GMSTBV_01x09_GF_7.62mm -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_9-GF-7,62_1x09_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829222 12A 630V -phoenix_contact connector GMSTBV_01x09_GF_7.62mm_MH -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_10-GF-7,62_1x10_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829235 12A 630V -phoenix_contact connector GMSTBV_01x10_GF_7.62mm -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_10-GF-7,62_1x10_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829235 12A 630V -phoenix_contact connector GMSTBV_01x10_GF_7.62mm_MH -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_11-GF-7,62_1x11_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829248 12A 630V -phoenix_contact connector GMSTBV_01x11_GF_7.62mm -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_11-GF-7,62_1x11_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829248 12A 630V -phoenix_contact connector GMSTBV_01x11_GF_7.62mm_MH -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_12-GF-7,62_1x12_P7.62mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829251 12A 630V -phoenix_contact connector GMSTBV_01x12_GF_7.62mm -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTBV_2,5_12-GF-7,62_1x12_P7.62mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTBV_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829251 12A 630V -phoenix_contact connector GMSTBV_01x12_GF_7.62mm_MH -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_2-GF-7,62_1x02_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806229 12A 630V -phoenix_contact connector GMSTB_01x02_GF_7.62mm -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_2-GF-7,62_1x02_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806229 12A 630V -phoenix_contact connector GMSTB_01x02_GF_7.62mm_MH -0 -2 -2 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_3-GF-7,62_1x03_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806232 12A 630V -phoenix_contact connector GMSTB_01x03_GF_7.62mm -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_3-GF-7,62_1x03_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806232 12A 630V -phoenix_contact connector GMSTB_01x03_GF_7.62mm_MH -0 -3 -3 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_4-GF-7,62_1x04_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806245 12A 630V -phoenix_contact connector GMSTB_01x04_GF_7.62mm -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_4-GF-7,62_1x04_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806245 12A 630V -phoenix_contact connector GMSTB_01x04_GF_7.62mm_MH -0 -4 -4 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_5-GF-7,62_1x05_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806258 12A 630V -phoenix_contact connector GMSTB_01x05_GF_7.62mm -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_5-GF-7,62_1x05_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806258 12A 630V -phoenix_contact connector GMSTB_01x05_GF_7.62mm_MH -0 -5 -5 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_6-GF-7,62_1x06_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806261 12A 630V -phoenix_contact connector GMSTB_01x06_GF_7.62mm -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_6-GF-7,62_1x06_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806261 12A 630V -phoenix_contact connector GMSTB_01x06_GF_7.62mm_MH -0 -6 -6 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_7-GF-7,62_1x07_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806274 12A 630V -phoenix_contact connector GMSTB_01x07_GF_7.62mm -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_7-GF-7,62_1x07_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806274 12A 630V -phoenix_contact connector GMSTB_01x07_GF_7.62mm_MH -0 -7 -7 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_8-GF-7,62_1x08_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806287 12A 630V -phoenix_contact connector GMSTB_01x08_GF_7.62mm -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_8-GF-7,62_1x08_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806287 12A 630V -phoenix_contact connector GMSTB_01x08_GF_7.62mm_MH -0 -8 -8 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_9-GF-7,62_1x09_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806290 12A 630V -phoenix_contact connector GMSTB_01x09_GF_7.62mm -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_9-GF-7,62_1x09_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806290 12A 630V -phoenix_contact connector GMSTB_01x09_GF_7.62mm_MH -0 -9 -9 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_10-GF-7,62_1x10_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806300 12A 630V -phoenix_contact connector GMSTB_01x10_GF_7.62mm -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_10-GF-7,62_1x10_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806300 12A 630V -phoenix_contact connector GMSTB_01x10_GF_7.62mm_MH -0 -10 -10 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_11-GF-7,62_1x11_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806313 12A 630V -phoenix_contact connector GMSTB_01x11_GF_7.62mm -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_11-GF-7,62_1x11_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806313 12A 630V -phoenix_contact connector GMSTB_01x11_GF_7.62mm_MH -0 -11 -11 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_12-GF-7,62_1x12_P7.62mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: GMSTB_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806326 12A 630V -phoenix_contact connector GMSTB_01x12_GF_7.62mm -0 -12 -12 -Connector_Phoenix_GMSTB -PhoenixContact_GMSTB_2,5_12-GF-7,62_1x12_P7.62mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: GMSTB_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806326 12A 630V -phoenix_contact connector GMSTB_01x12_GF_7.62mm_MH -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_2-G-3.5_1x02_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical || order number: 1843606 8A 160V -phoenix_contact connector MCV_01x02_G_3.5mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_2-G-3.81_1x02_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical || order number: 1803426 8A 160V -phoenix_contact connector MCV_01x02_G_3.81mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_2-GF-3.5_1x02_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843224 8A 160V -phoenix_contact connector MCV_01x02_GF_3.5mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_2-GF-3.5_1x02_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843224 8A 160V -phoenix_contact connector MCV_01x02_GF_3.5mm_MH -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_2-GF-3.81_1x02_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830596 8A 160V -phoenix_contact connector MCV_01x02_GF_3.81mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_2-GF-3.81_1x02_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830596 8A 160V -phoenix_contact connector MCV_01x02_GF_3.81mm_MH -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_3-G-3.5_1x03_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical || order number: 1843619 8A 160V -phoenix_contact connector MCV_01x03_G_3.5mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_3-G-3.81_1x03_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical || order number: 1803439 8A 160V -phoenix_contact connector MCV_01x03_G_3.81mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_3-GF-3.5_1x03_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843237 8A 160V -phoenix_contact connector MCV_01x03_GF_3.5mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_3-GF-3.5_1x03_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843237 8A 160V -phoenix_contact connector MCV_01x03_GF_3.5mm_MH -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_3-GF-3.81_1x03_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830606 8A 160V -phoenix_contact connector MCV_01x03_GF_3.81mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_3-GF-3.81_1x03_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830606 8A 160V -phoenix_contact connector MCV_01x03_GF_3.81mm_MH -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_4-G-3.5_1x04_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical || order number: 1843622 8A 160V -phoenix_contact connector MCV_01x04_G_3.5mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_4-G-3.81_1x04_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical || order number: 1803442 8A 160V -phoenix_contact connector MCV_01x04_G_3.81mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_4-GF-3.5_1x04_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843240 8A 160V -phoenix_contact connector MCV_01x04_GF_3.5mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_4-GF-3.5_1x04_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843240 8A 160V -phoenix_contact connector MCV_01x04_GF_3.5mm_MH -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_4-GF-3.81_1x04_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830619 8A 160V -phoenix_contact connector MCV_01x04_GF_3.81mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_4-GF-3.81_1x04_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830619 8A 160V -phoenix_contact connector MCV_01x04_GF_3.81mm_MH -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_5-G-3.5_1x05_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical || order number: 1843635 8A 160V -phoenix_contact connector MCV_01x05_G_3.5mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_5-G-3.81_1x05_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical || order number: 1803455 8A 160V -phoenix_contact connector MCV_01x05_G_3.81mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_5-GF-3.5_1x05_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843253 8A 160V -phoenix_contact connector MCV_01x05_GF_3.5mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_5-GF-3.5_1x05_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843253 8A 160V -phoenix_contact connector MCV_01x05_GF_3.5mm_MH -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_5-GF-3.81_1x05_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830622 8A 160V -phoenix_contact connector MCV_01x05_GF_3.81mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_5-GF-3.81_1x05_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830622 8A 160V -phoenix_contact connector MCV_01x05_GF_3.81mm_MH -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_6-G-3.5_1x06_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical || order number: 1843648 8A 160V -phoenix_contact connector MCV_01x06_G_3.5mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_6-G-3.81_1x06_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical || order number: 1803468 8A 160V -phoenix_contact connector MCV_01x06_G_3.81mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_6-GF-3.5_1x06_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843266 8A 160V -phoenix_contact connector MCV_01x06_GF_3.5mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_6-GF-3.5_1x06_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843266 8A 160V -phoenix_contact connector MCV_01x06_GF_3.5mm_MH -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_6-GF-3.81_1x06_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830635 8A 160V -phoenix_contact connector MCV_01x06_GF_3.81mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_6-GF-3.81_1x06_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830635 8A 160V -phoenix_contact connector MCV_01x06_GF_3.81mm_MH -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_7-G-3.5_1x07_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical || order number: 1843651 8A 160V -phoenix_contact connector MCV_01x07_G_3.5mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_7-G-3.81_1x07_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical || order number: 1803471 8A 160V -phoenix_contact connector MCV_01x07_G_3.81mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_7-GF-3.5_1x07_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843279 8A 160V -phoenix_contact connector MCV_01x07_GF_3.5mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_7-GF-3.5_1x07_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843279 8A 160V -phoenix_contact connector MCV_01x07_GF_3.5mm_MH -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_7-GF-3.81_1x07_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830648 8A 160V -phoenix_contact connector MCV_01x07_GF_3.81mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_7-GF-3.81_1x07_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830648 8A 160V -phoenix_contact connector MCV_01x07_GF_3.81mm_MH -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_8-G-3.5_1x08_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical || order number: 1843664 8A 160V -phoenix_contact connector MCV_01x08_G_3.5mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_8-G-3.81_1x08_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical || order number: 1803484 8A 160V -phoenix_contact connector MCV_01x08_G_3.81mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_8-GF-3.5_1x08_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843282 8A 160V -phoenix_contact connector MCV_01x08_GF_3.5mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_8-GF-3.5_1x08_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843282 8A 160V -phoenix_contact connector MCV_01x08_GF_3.5mm_MH -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_8-GF-3.81_1x08_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830651 8A 160V -phoenix_contact connector MCV_01x08_GF_3.81mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_8-GF-3.81_1x08_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830651 8A 160V -phoenix_contact connector MCV_01x08_GF_3.81mm_MH -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_9-G-3.5_1x09_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical || order number: 1843677 8A 160V -phoenix_contact connector MCV_01x09_G_3.5mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_9-G-3.81_1x09_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical || order number: 1803497 8A 160V -phoenix_contact connector MCV_01x09_G_3.81mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_9-GF-3.5_1x09_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843295 8A 160V -phoenix_contact connector MCV_01x09_GF_3.5mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_9-GF-3.5_1x09_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843295 8A 160V -phoenix_contact connector MCV_01x09_GF_3.5mm_MH -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_9-GF-3.81_1x09_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830664 8A 160V -phoenix_contact connector MCV_01x09_GF_3.81mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_9-GF-3.81_1x09_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830664 8A 160V -phoenix_contact connector MCV_01x09_GF_3.81mm_MH -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_10-G-3.5_1x10_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical || order number: 1843680 8A 160V -phoenix_contact connector MCV_01x10_G_3.5mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_10-G-3.81_1x10_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical || order number: 1803507 8A 160V -phoenix_contact connector MCV_01x10_G_3.81mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_10-GF-3.5_1x10_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843305 8A 160V -phoenix_contact connector MCV_01x10_GF_3.5mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_10-GF-3.5_1x10_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843305 8A 160V -phoenix_contact connector MCV_01x10_GF_3.5mm_MH -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_10-GF-3.81_1x10_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830677 8A 160V -phoenix_contact connector MCV_01x10_GF_3.81mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_10-GF-3.81_1x10_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830677 8A 160V -phoenix_contact connector MCV_01x10_GF_3.81mm_MH -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_11-G-3.5_1x11_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical || order number: 1843693 8A 160V -phoenix_contact connector MCV_01x11_G_3.5mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_11-G-3.81_1x11_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical || order number: 1803510 8A 160V -phoenix_contact connector MCV_01x11_G_3.81mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_11-GF-3.5_1x11_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843318 8A 160V -phoenix_contact connector MCV_01x11_GF_3.5mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_11-GF-3.5_1x11_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843318 8A 160V -phoenix_contact connector MCV_01x11_GF_3.5mm_MH -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_11-GF-3.81_1x11_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830680 8A 160V -phoenix_contact connector MCV_01x11_GF_3.81mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_11-GF-3.81_1x11_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830680 8A 160V -phoenix_contact connector MCV_01x11_GF_3.81mm_MH -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_12-G-3.5_1x12_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical || order number: 1843703 8A 160V -phoenix_contact connector MCV_01x12_G_3.5mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_12-G-3.81_1x12_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical || order number: 1803523 8A 160V -phoenix_contact connector MCV_01x12_G_3.81mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_12-GF-3.5_1x12_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843321 8A 160V -phoenix_contact connector MCV_01x12_GF_3.5mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_12-GF-3.5_1x12_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843321 8A 160V -phoenix_contact connector MCV_01x12_GF_3.5mm_MH -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_12-GF-3.81_1x12_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830693 8A 160V -phoenix_contact connector MCV_01x12_GF_3.81mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_12-GF-3.81_1x12_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830693 8A 160V -phoenix_contact connector MCV_01x12_GF_3.81mm_MH -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_13-G-3.5_1x13_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/13-G-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical || order number: 1843716 8A 160V -phoenix_contact connector MCV_01x13_G_3.5mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_13-G-3.81_1x13_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/13-G-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical || order number: 1803536 8A 160V -phoenix_contact connector MCV_01x13_G_3.81mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_13-GF-3.5_1x13_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843334 8A 160V -phoenix_contact connector MCV_01x13_GF_3.5mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_13-GF-3.5_1x13_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843334 8A 160V -phoenix_contact connector MCV_01x13_GF_3.5mm_MH -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_13-GF-3.81_1x13_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830703 8A 160V -phoenix_contact connector MCV_01x13_GF_3.81mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_13-GF-3.81_1x13_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830703 8A 160V -phoenix_contact connector MCV_01x13_GF_3.81mm_MH -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_14-G-3.5_1x14_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/14-G-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical || order number: 1843729 8A 160V -phoenix_contact connector MCV_01x14_G_3.5mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_14-G-3.81_1x14_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/14-G-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical || order number: 1803549 8A 160V -phoenix_contact connector MCV_01x14_G_3.81mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_14-GF-3.5_1x14_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843347 8A 160V -phoenix_contact connector MCV_01x14_GF_3.5mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_14-GF-3.5_1x14_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843347 8A 160V -phoenix_contact connector MCV_01x14_GF_3.5mm_MH -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_14-GF-3.81_1x14_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830716 8A 160V -phoenix_contact connector MCV_01x14_GF_3.81mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_14-GF-3.81_1x14_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830716 8A 160V -phoenix_contact connector MCV_01x14_GF_3.81mm_MH -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_15-G-3.5_1x15_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/15-G-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical || order number: 1843732 8A 160V -phoenix_contact connector MCV_01x15_G_3.5mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_15-G-3.81_1x15_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/15-G-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical || order number: 1803552 8A 160V -phoenix_contact connector MCV_01x15_G_3.81mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_15-GF-3.5_1x15_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843350 8A 160V -phoenix_contact connector MCV_01x15_GF_3.5mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_15-GF-3.5_1x15_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843350 8A 160V -phoenix_contact connector MCV_01x15_GF_3.5mm_MH -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_15-GF-3.81_1x15_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830729 8A 160V -phoenix_contact connector MCV_01x15_GF_3.81mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_15-GF-3.81_1x15_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830729 8A 160V -phoenix_contact connector MCV_01x15_GF_3.81mm_MH -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_16-G-3.5_1x16_P3.50mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/16-G-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical || order number: 1843745 8A 160V -phoenix_contact connector MCV_01x16_G_3.5mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_16-G-3.81_1x16_P3.81mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/16-G-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical || order number: 1803565 8A 160V -phoenix_contact connector MCV_01x16_G_3.81mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_16-GF-3.5_1x16_P3.50mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843363 8A 160V -phoenix_contact connector MCV_01x16_GF_3.5mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_16-GF-3.5_1x16_P3.50mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843363 8A 160V -phoenix_contact connector MCV_01x16_GF_3.5mm_MH -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_16-GF-3.81_1x16_P3.81mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830732 8A 160V -phoenix_contact connector MCV_01x16_GF_3.81mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MCV_1,5_16-GF-3.81_1x16_P3.81mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830732 8A 160V -phoenix_contact connector MCV_01x16_GF_3.81mm_MH -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_2-G-3.5_1x02_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/2-G-3.5; number of pins: 02; pin pitch: 3.50mm; Angled || order number: 1844210 8A 160V -phoenix_contact connector MC_01x02_G_3.5mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_2-G-3.81_1x02_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/2-G-3.81; number of pins: 02; pin pitch: 3.81mm; Angled || order number: 1803277 8A 160V -phoenix_contact connector MC_01x02_G_3.81mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_2-GF-3.5_1x02_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843790 8A 160V -phoenix_contact connector MC_01x02_GF_3.5mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_2-GF-3.5_1x02_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843790 8A 160V -phoenix_contact connector MC_01x02_GF_3.5mm_MH -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_2-GF-3.81_1x02_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827868 8A 160V -phoenix_contact connector MC_01x02_GF_3.81mm -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_2-GF-3.81_1x02_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827868 8A 160V -phoenix_contact connector MC_01x02_GF_3.81mm_MH -0 -2 -2 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/3-G-3.5; number of pins: 03; pin pitch: 3.50mm; Angled || order number: 1844223 8A 160V -phoenix_contact connector MC_01x03_G_3.5mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_3-G-3.81_1x03_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/3-G-3.81; number of pins: 03; pin pitch: 3.81mm; Angled || order number: 1803280 8A 160V -phoenix_contact connector MC_01x03_G_3.81mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_3-GF-3.5_1x03_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843800 8A 160V -phoenix_contact connector MC_01x03_GF_3.5mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_3-GF-3.5_1x03_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843800 8A 160V -phoenix_contact connector MC_01x03_GF_3.5mm_MH -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_3-GF-3.81_1x03_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827871 8A 160V -phoenix_contact connector MC_01x03_GF_3.81mm -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_3-GF-3.81_1x03_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827871 8A 160V -phoenix_contact connector MC_01x03_GF_3.81mm_MH -0 -3 -3 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_4-G-3.5_1x04_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/4-G-3.5; number of pins: 04; pin pitch: 3.50mm; Angled || order number: 1844236 8A 160V -phoenix_contact connector MC_01x04_G_3.5mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_4-G-3.81_1x04_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/4-G-3.81; number of pins: 04; pin pitch: 3.81mm; Angled || order number: 1803293 8A 160V -phoenix_contact connector MC_01x04_G_3.81mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_4-GF-3.5_1x04_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843813 8A 160V -phoenix_contact connector MC_01x04_GF_3.5mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_4-GF-3.5_1x04_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843813 8A 160V -phoenix_contact connector MC_01x04_GF_3.5mm_MH -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_4-GF-3.81_1x04_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827884 8A 160V -phoenix_contact connector MC_01x04_GF_3.81mm -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_4-GF-3.81_1x04_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827884 8A 160V -phoenix_contact connector MC_01x04_GF_3.81mm_MH -0 -4 -4 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_5-G-3.5_1x05_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/5-G-3.5; number of pins: 05; pin pitch: 3.50mm; Angled || order number: 1844249 8A 160V -phoenix_contact connector MC_01x05_G_3.5mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_5-G-3.81_1x05_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/5-G-3.81; number of pins: 05; pin pitch: 3.81mm; Angled || order number: 1803303 8A 160V -phoenix_contact connector MC_01x05_G_3.81mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_5-GF-3.5_1x05_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843826 8A 160V -phoenix_contact connector MC_01x05_GF_3.5mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_5-GF-3.5_1x05_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843826 8A 160V -phoenix_contact connector MC_01x05_GF_3.5mm_MH -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_5-GF-3.81_1x05_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827897 8A 160V -phoenix_contact connector MC_01x05_GF_3.81mm -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_5-GF-3.81_1x05_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827897 8A 160V -phoenix_contact connector MC_01x05_GF_3.81mm_MH -0 -5 -5 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_6-G-3.5_1x06_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/6-G-3.5; number of pins: 06; pin pitch: 3.50mm; Angled || order number: 1844252 8A 160V -phoenix_contact connector MC_01x06_G_3.5mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_6-G-3.81_1x06_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/6-G-3.81; number of pins: 06; pin pitch: 3.81mm; Angled || order number: 1803316 8A 160V -phoenix_contact connector MC_01x06_G_3.81mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_6-GF-3.5_1x06_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843839 8A 160V -phoenix_contact connector MC_01x06_GF_3.5mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_6-GF-3.5_1x06_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843839 8A 160V -phoenix_contact connector MC_01x06_GF_3.5mm_MH -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_6-GF-3.81_1x06_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827907 8A 160V -phoenix_contact connector MC_01x06_GF_3.81mm -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_6-GF-3.81_1x06_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827907 8A 160V -phoenix_contact connector MC_01x06_GF_3.81mm_MH -0 -6 -6 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_7-G-3.5_1x07_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/7-G-3.5; number of pins: 07; pin pitch: 3.50mm; Angled || order number: 1844265 8A 160V -phoenix_contact connector MC_01x07_G_3.5mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_7-G-3.81_1x07_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/7-G-3.81; number of pins: 07; pin pitch: 3.81mm; Angled || order number: 1803329 8A 160V -phoenix_contact connector MC_01x07_G_3.81mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_7-GF-3.5_1x07_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843842 8A 160V -phoenix_contact connector MC_01x07_GF_3.5mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_7-GF-3.5_1x07_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843842 8A 160V -phoenix_contact connector MC_01x07_GF_3.5mm_MH -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_7-GF-3.81_1x07_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827910 8A 160V -phoenix_contact connector MC_01x07_GF_3.81mm -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_7-GF-3.81_1x07_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827910 8A 160V -phoenix_contact connector MC_01x07_GF_3.81mm_MH -0 -7 -7 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_8-G-3.5_1x08_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/8-G-3.5; number of pins: 08; pin pitch: 3.50mm; Angled || order number: 1844278 8A 160V -phoenix_contact connector MC_01x08_G_3.5mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_8-G-3.81_1x08_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/8-G-3.81; number of pins: 08; pin pitch: 3.81mm; Angled || order number: 1803332 8A 160V -phoenix_contact connector MC_01x08_G_3.81mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_8-GF-3.5_1x08_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843855 8A 160V -phoenix_contact connector MC_01x08_GF_3.5mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_8-GF-3.5_1x08_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843855 8A 160V -phoenix_contact connector MC_01x08_GF_3.5mm_MH -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_8-GF-3.81_1x08_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827923 8A 160V -phoenix_contact connector MC_01x08_GF_3.81mm -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_8-GF-3.81_1x08_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827923 8A 160V -phoenix_contact connector MC_01x08_GF_3.81mm_MH -0 -8 -8 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_9-G-3.5_1x09_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/9-G-3.5; number of pins: 09; pin pitch: 3.50mm; Angled || order number: 1844281 8A 160V -phoenix_contact connector MC_01x09_G_3.5mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_9-G-3.81_1x09_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/9-G-3.81; number of pins: 09; pin pitch: 3.81mm; Angled || order number: 1803345 8A 160V -phoenix_contact connector MC_01x09_G_3.81mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_9-GF-3.5_1x09_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843868 8A 160V -phoenix_contact connector MC_01x09_GF_3.5mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_9-GF-3.5_1x09_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843868 8A 160V -phoenix_contact connector MC_01x09_GF_3.5mm_MH -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_9-GF-3.81_1x09_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827936 8A 160V -phoenix_contact connector MC_01x09_GF_3.81mm -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_9-GF-3.81_1x09_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827936 8A 160V -phoenix_contact connector MC_01x09_GF_3.81mm_MH -0 -9 -9 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_10-G-3.5_1x10_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/10-G-3.5; number of pins: 10; pin pitch: 3.50mm; Angled || order number: 1844294 8A 160V -phoenix_contact connector MC_01x10_G_3.5mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_10-G-3.81_1x10_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/10-G-3.81; number of pins: 10; pin pitch: 3.81mm; Angled || order number: 1803358 8A 160V -phoenix_contact connector MC_01x10_G_3.81mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_10-GF-3.5_1x10_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843871 8A 160V -phoenix_contact connector MC_01x10_GF_3.5mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_10-GF-3.5_1x10_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843871 8A 160V -phoenix_contact connector MC_01x10_GF_3.5mm_MH -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_10-GF-3.81_1x10_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827949 8A 160V -phoenix_contact connector MC_01x10_GF_3.81mm -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_10-GF-3.81_1x10_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827949 8A 160V -phoenix_contact connector MC_01x10_GF_3.81mm_MH -0 -10 -10 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_11-G-3.5_1x11_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/11-G-3.5; number of pins: 11; pin pitch: 3.50mm; Angled || order number: 1844304 8A 160V -phoenix_contact connector MC_01x11_G_3.5mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_11-G-3.81_1x11_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/11-G-3.81; number of pins: 11; pin pitch: 3.81mm; Angled || order number: 1803361 8A 160V -phoenix_contact connector MC_01x11_G_3.81mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_11-GF-3.5_1x11_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843884 8A 160V -phoenix_contact connector MC_01x11_GF_3.5mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_11-GF-3.5_1x11_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843884 8A 160V -phoenix_contact connector MC_01x11_GF_3.5mm_MH -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_11-GF-3.81_1x11_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827952 8A 160V -phoenix_contact connector MC_01x11_GF_3.81mm -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_11-GF-3.81_1x11_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827952 8A 160V -phoenix_contact connector MC_01x11_GF_3.81mm_MH -0 -11 -11 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_12-G-3.5_1x12_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/12-G-3.5; number of pins: 12; pin pitch: 3.50mm; Angled || order number: 1844317 8A 160V -phoenix_contact connector MC_01x12_G_3.5mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_12-G-3.81_1x12_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/12-G-3.81; number of pins: 12; pin pitch: 3.81mm; Angled || order number: 1803374 8A 160V -phoenix_contact connector MC_01x12_G_3.81mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_12-GF-3.5_1x12_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843897 8A 160V -phoenix_contact connector MC_01x12_GF_3.5mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_12-GF-3.5_1x12_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843897 8A 160V -phoenix_contact connector MC_01x12_GF_3.5mm_MH -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_12-GF-3.81_1x12_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827965 8A 160V -phoenix_contact connector MC_01x12_GF_3.81mm -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_12-GF-3.81_1x12_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827965 8A 160V -phoenix_contact connector MC_01x12_GF_3.81mm_MH -0 -12 -12 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_13-G-3.5_1x13_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/13-G-3.5; number of pins: 13; pin pitch: 3.50mm; Angled || order number: 1844320 8A 160V -phoenix_contact connector MC_01x13_G_3.5mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_13-G-3.81_1x13_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/13-G-3.81; number of pins: 13; pin pitch: 3.81mm; Angled || order number: 1803387 8A 160V -phoenix_contact connector MC_01x13_G_3.81mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_13-GF-3.5_1x13_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843907 8A 160V -phoenix_contact connector MC_01x13_GF_3.5mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_13-GF-3.5_1x13_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843907 8A 160V -phoenix_contact connector MC_01x13_GF_3.5mm_MH -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_13-GF-3.81_1x13_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827978 8A 160V -phoenix_contact connector MC_01x13_GF_3.81mm -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_13-GF-3.81_1x13_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827978 8A 160V -phoenix_contact connector MC_01x13_GF_3.81mm_MH -0 -13 -13 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_14-G-3.5_1x14_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/14-G-3.5; number of pins: 14; pin pitch: 3.50mm; Angled || order number: 1844333 8A 160V -phoenix_contact connector MC_01x14_G_3.5mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_14-G-3.81_1x14_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/14-G-3.81; number of pins: 14; pin pitch: 3.81mm; Angled || order number: 1803390 8A 160V -phoenix_contact connector MC_01x14_G_3.81mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_14-GF-3.5_1x14_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843910 8A 160V -phoenix_contact connector MC_01x14_GF_3.5mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_14-GF-3.5_1x14_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843910 8A 160V -phoenix_contact connector MC_01x14_GF_3.5mm_MH -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_14-GF-3.81_1x14_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827981 8A 160V -phoenix_contact connector MC_01x14_GF_3.81mm -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_14-GF-3.81_1x14_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827981 8A 160V -phoenix_contact connector MC_01x14_GF_3.81mm_MH -0 -14 -14 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_15-G-3.5_1x15_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/15-G-3.5; number of pins: 15; pin pitch: 3.50mm; Angled || order number: 1844346 8A 160V -phoenix_contact connector MC_01x15_G_3.5mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_15-G-3.81_1x15_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/15-G-3.81; number of pins: 15; pin pitch: 3.81mm; Angled || order number: 1803400 8A 160V -phoenix_contact connector MC_01x15_G_3.81mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_15-GF-3.5_1x15_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843923 8A 160V -phoenix_contact connector MC_01x15_GF_3.5mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_15-GF-3.5_1x15_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843923 8A 160V -phoenix_contact connector MC_01x15_GF_3.5mm_MH -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_15-GF-3.81_1x15_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827994 8A 160V -phoenix_contact connector MC_01x15_GF_3.81mm -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_15-GF-3.81_1x15_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827994 8A 160V -phoenix_contact connector MC_01x15_GF_3.81mm_MH -0 -15 -15 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_16-G-3.5_1x16_P3.50mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/16-G-3.5; number of pins: 16; pin pitch: 3.50mm; Angled || order number: 1844359 8A 160V -phoenix_contact connector MC_01x16_G_3.5mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_16-G-3.81_1x16_P3.81mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/16-G-3.81; number of pins: 16; pin pitch: 3.81mm; Angled || order number: 1803413 8A 160V -phoenix_contact connector MC_01x16_G_3.81mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_16-GF-3.5_1x16_P3.50mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843936 8A 160V -phoenix_contact connector MC_01x16_GF_3.5mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_16-GF-3.5_1x16_P3.50mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843936 8A 160V -phoenix_contact connector MC_01x16_GF_3.5mm_MH -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_16-GF-3.81_1x16_P3.81mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Angled; threaded flange || order number: 1828003 8A 160V -phoenix_contact connector MC_01x16_GF_3.81mm -0 -16 -16 -Connector_Phoenix_MC -PhoenixContact_MC_1,5_16-GF-3.81_1x16_P3.81mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1828003 8A 160V -phoenix_contact connector MC_01x16_GF_3.81mm_MH -0 -16 -16 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_2-G-5.08_1x02_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical || order number: 1836299 8A 320V -phoenix_contact connector MCV_01x02_G_5.08mm -0 -2 -2 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_2-GF-5.08_1x02_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847615 8A 320V -phoenix_contact connector MCV_01x02_GF_5.08mm -0 -2 -2 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_2-GF-5.08_1x02_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847615 8A 320V -phoenix_contact connector MCV_01x02_GF_5.08mm_MH -0 -2 -2 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_3-G-5.08_1x03_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical || order number: 1836309 8A 320V -phoenix_contact connector MCV_01x03_G_5.08mm -0 -3 -3 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_3-GF-5.08_1x03_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847628 8A 320V -phoenix_contact connector MCV_01x03_GF_5.08mm -0 -3 -3 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_3-GF-5.08_1x03_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847628 8A 320V -phoenix_contact connector MCV_01x03_GF_5.08mm_MH -0 -3 -3 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_4-G-5.08_1x04_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical || order number: 1836312 8A 320V -phoenix_contact connector MCV_01x04_G_5.08mm -0 -4 -4 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_4-GF-5.08_1x04_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847631 8A 320V -phoenix_contact connector MCV_01x04_GF_5.08mm -0 -4 -4 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_4-GF-5.08_1x04_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847631 8A 320V -phoenix_contact connector MCV_01x04_GF_5.08mm_MH -0 -4 -4 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_5-G-5.08_1x05_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical || order number: 1836325 8A 320V -phoenix_contact connector MCV_01x05_G_5.08mm -0 -5 -5 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_5-GF-5.08_1x05_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847644 8A 320V -phoenix_contact connector MCV_01x05_GF_5.08mm -0 -5 -5 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_5-GF-5.08_1x05_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847644 8A 320V -phoenix_contact connector MCV_01x05_GF_5.08mm_MH -0 -5 -5 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_6-G-5.08_1x06_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical || order number: 1836338 8A 320V -phoenix_contact connector MCV_01x06_G_5.08mm -0 -6 -6 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_6-GF-5.08_1x06_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847657 8A 320V -phoenix_contact connector MCV_01x06_GF_5.08mm -0 -6 -6 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_6-GF-5.08_1x06_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847657 8A 320V -phoenix_contact connector MCV_01x06_GF_5.08mm_MH -0 -6 -6 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_7-G-5.08_1x07_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical || order number: 1836341 8A 320V -phoenix_contact connector MCV_01x07_G_5.08mm -0 -7 -7 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_7-GF-5.08_1x07_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847660 8A 320V -phoenix_contact connector MCV_01x07_GF_5.08mm -0 -7 -7 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_7-GF-5.08_1x07_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847660 8A 320V -phoenix_contact connector MCV_01x07_GF_5.08mm_MH -0 -7 -7 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_8-G-5.08_1x08_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical || order number: 1836354 8A 320V -phoenix_contact connector MCV_01x08_G_5.08mm -0 -8 -8 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_8-GF-5.08_1x08_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847673 8A 320V -phoenix_contact connector MCV_01x08_GF_5.08mm -0 -8 -8 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_8-GF-5.08_1x08_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847673 8A 320V -phoenix_contact connector MCV_01x08_GF_5.08mm_MH -0 -8 -8 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_9-G-5.08_1x09_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical || order number: 1836367 8A 320V -phoenix_contact connector MCV_01x09_G_5.08mm -0 -9 -9 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_9-GF-5.08_1x09_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847686 8A 320V -phoenix_contact connector MCV_01x09_GF_5.08mm -0 -9 -9 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_9-GF-5.08_1x09_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847686 8A 320V -phoenix_contact connector MCV_01x09_GF_5.08mm_MH -0 -9 -9 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_10-G-5.08_1x10_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical || order number: 1836370 8A 320V -phoenix_contact connector MCV_01x10_G_5.08mm -0 -10 -10 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_10-GF-5.08_1x10_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847699 8A 320V -phoenix_contact connector MCV_01x10_GF_5.08mm -0 -10 -10 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_10-GF-5.08_1x10_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847699 8A 320V -phoenix_contact connector MCV_01x10_GF_5.08mm_MH -0 -10 -10 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_11-G-5.08_1x11_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical || order number: 1836383 8A 320V -phoenix_contact connector MCV_01x11_G_5.08mm -0 -11 -11 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_11-GF-5.08_1x11_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847709 8A 320V -phoenix_contact connector MCV_01x11_GF_5.08mm -0 -11 -11 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_11-GF-5.08_1x11_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847709 8A 320V -phoenix_contact connector MCV_01x11_GF_5.08mm_MH -0 -11 -11 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_12-G-5.08_1x12_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical || order number: 1836396 8A 320V -phoenix_contact connector MCV_01x12_G_5.08mm -0 -12 -12 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_12-GF-5.08_1x12_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847712 8A 320V -phoenix_contact connector MCV_01x12_GF_5.08mm -0 -12 -12 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MCV_1,5_12-GF-5.08_1x12_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847712 8A 320V -phoenix_contact connector MCV_01x12_GF_5.08mm_MH -0 -12 -12 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_2-G-5.08_1x02_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/2-G-5.08; number of pins: 02; pin pitch: 5.08mm; Angled || order number: 1836189 8A 320V -phoenix_contact connector MC_01x02_G_5.08mm -0 -2 -2 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_2-GF-5.08_1x02_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847466 8A 320V -phoenix_contact connector MC_01x02_GF_5.08mm -0 -2 -2 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_2-GF-5.08_1x02_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847466 8A 320V -phoenix_contact connector MC_01x02_GF_5.08mm_MH -0 -2 -2 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_3-G-5.08_1x03_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/3-G-5.08; number of pins: 03; pin pitch: 5.08mm; Angled || order number: 1836192 8A 320V -phoenix_contact connector MC_01x03_G_5.08mm -0 -3 -3 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_3-GF-5.08_1x03_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847479 8A 320V -phoenix_contact connector MC_01x03_GF_5.08mm -0 -3 -3 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_3-GF-5.08_1x03_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847479 8A 320V -phoenix_contact connector MC_01x03_GF_5.08mm_MH -0 -3 -3 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_4-G-5.08_1x04_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/4-G-5.08; number of pins: 04; pin pitch: 5.08mm; Angled || order number: 1836202 8A 320V -phoenix_contact connector MC_01x04_G_5.08mm -0 -4 -4 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_4-GF-5.08_1x04_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847482 8A 320V -phoenix_contact connector MC_01x04_GF_5.08mm -0 -4 -4 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_4-GF-5.08_1x04_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847482 8A 320V -phoenix_contact connector MC_01x04_GF_5.08mm_MH -0 -4 -4 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_5-G-5.08_1x05_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/5-G-5.08; number of pins: 05; pin pitch: 5.08mm; Angled || order number: 1836215 8A 320V -phoenix_contact connector MC_01x05_G_5.08mm -0 -5 -5 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_5-GF-5.08_1x05_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847495 8A 320V -phoenix_contact connector MC_01x05_GF_5.08mm -0 -5 -5 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_5-GF-5.08_1x05_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847495 8A 320V -phoenix_contact connector MC_01x05_GF_5.08mm_MH -0 -5 -5 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_6-G-5.08_1x06_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/6-G-5.08; number of pins: 06; pin pitch: 5.08mm; Angled || order number: 1836228 8A 320V -phoenix_contact connector MC_01x06_G_5.08mm -0 -6 -6 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_6-GF-5.08_1x06_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847505 8A 320V -phoenix_contact connector MC_01x06_GF_5.08mm -0 -6 -6 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_6-GF-5.08_1x06_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847505 8A 320V -phoenix_contact connector MC_01x06_GF_5.08mm_MH -0 -6 -6 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_7-G-5.08_1x07_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/7-G-5.08; number of pins: 07; pin pitch: 5.08mm; Angled || order number: 1836231 8A 320V -phoenix_contact connector MC_01x07_G_5.08mm -0 -7 -7 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_7-GF-5.08_1x07_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847518 8A 320V -phoenix_contact connector MC_01x07_GF_5.08mm -0 -7 -7 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_7-GF-5.08_1x07_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847518 8A 320V -phoenix_contact connector MC_01x07_GF_5.08mm_MH -0 -7 -7 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_8-G-5.08_1x08_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/8-G-5.08; number of pins: 08; pin pitch: 5.08mm; Angled || order number: 1836244 8A 320V -phoenix_contact connector MC_01x08_G_5.08mm -0 -8 -8 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_8-GF-5.08_1x08_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847521 8A 320V -phoenix_contact connector MC_01x08_GF_5.08mm -0 -8 -8 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_8-GF-5.08_1x08_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847521 8A 320V -phoenix_contact connector MC_01x08_GF_5.08mm_MH -0 -8 -8 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_9-G-5.08_1x09_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/9-G-5.08; number of pins: 09; pin pitch: 5.08mm; Angled || order number: 1836257 8A 320V -phoenix_contact connector MC_01x09_G_5.08mm -0 -9 -9 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_9-GF-5.08_1x09_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847534 8A 320V -phoenix_contact connector MC_01x09_GF_5.08mm -0 -9 -9 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_9-GF-5.08_1x09_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847534 8A 320V -phoenix_contact connector MC_01x09_GF_5.08mm_MH -0 -9 -9 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_10-G-5.08_1x10_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/10-G-5.08; number of pins: 10; pin pitch: 5.08mm; Angled || order number: 1836260 8A 320V -phoenix_contact connector MC_01x10_G_5.08mm -0 -10 -10 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_10-GF-5.08_1x10_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847547 8A 320V -phoenix_contact connector MC_01x10_GF_5.08mm -0 -10 -10 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_10-GF-5.08_1x10_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847547 8A 320V -phoenix_contact connector MC_01x10_GF_5.08mm_MH -0 -10 -10 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_11-G-5.08_1x11_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/11-G-5.08; number of pins: 11; pin pitch: 5.08mm; Angled || order number: 1836273 8A 320V -phoenix_contact connector MC_01x11_G_5.08mm -0 -11 -11 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_11-GF-5.08_1x11_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847550 8A 320V -phoenix_contact connector MC_01x11_GF_5.08mm -0 -11 -11 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_11-GF-5.08_1x11_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847550 8A 320V -phoenix_contact connector MC_01x11_GF_5.08mm_MH -0 -11 -11 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_12-G-5.08_1x12_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MC_1,5/12-G-5.08; number of pins: 12; pin pitch: 5.08mm; Angled || order number: 1836286 8A 320V -phoenix_contact connector MC_01x12_G_5.08mm -0 -12 -12 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_12-GF-5.08_1x12_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847563 8A 320V -phoenix_contact connector MC_01x12_GF_5.08mm -0 -12 -12 -Connector_Phoenix_MC_HighVoltage -PhoenixContact_MC_1,5_12-GF-5.08_1x12_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847563 8A 320V -phoenix_contact connector MC_01x12_GF_5.08mm_MH -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_2-G-5,08_1x02_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/2-G-5,08; number of pins: 02; pin pitch: 5.08mm; Angled || order number: 1757242 12A || order number: 1923869 16A (HC) -phoenix_contact connector MSTBA_01x02_G_5.08mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_2-G_1x02_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Angled || order number: 1757475 12A || order number: 1923759 16A (HC) -phoenix_contact connector MSTBA_01x02_G_5.00mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_3-G-5,08_1x03_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/3-G-5,08; number of pins: 03; pin pitch: 5.08mm; Angled || order number: 1757255 12A || order number: 1923872 16A (HC) -phoenix_contact connector MSTBA_01x03_G_5.08mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_3-G_1x03_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/3-G; number of pins: 03; pin pitch: 5.00mm; Angled || order number: 1757488 12A || order number: 1923762 16A (HC) -phoenix_contact connector MSTBA_01x03_G_5.00mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_4-G-5,08_1x04_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/4-G-5,08; number of pins: 04; pin pitch: 5.08mm; Angled || order number: 1757268 12A || order number: 1923885 16A (HC) -phoenix_contact connector MSTBA_01x04_G_5.08mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_4-G_1x04_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Angled || order number: 1757491 12A || order number: 1923775 16A (HC) -phoenix_contact connector MSTBA_01x04_G_5.00mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_5-G-5,08_1x05_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/5-G-5,08; number of pins: 05; pin pitch: 5.08mm; Angled || order number: 1757271 12A || order number: 1923898 16A (HC) -phoenix_contact connector MSTBA_01x05_G_5.08mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_5-G_1x05_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/5-G; number of pins: 05; pin pitch: 5.00mm; Angled || order number: 1757501 12A || order number: 1923788 16A (HC) -phoenix_contact connector MSTBA_01x05_G_5.00mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_6-G-5,08_1x06_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/6-G-5,08; number of pins: 06; pin pitch: 5.08mm; Angled || order number: 1757284 12A || order number: 1923908 16A (HC) -phoenix_contact connector MSTBA_01x06_G_5.08mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_6-G_1x06_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/6-G; number of pins: 06; pin pitch: 5.00mm; Angled || order number: 1757514 12A || order number: 1923791 16A (HC) -phoenix_contact connector MSTBA_01x06_G_5.00mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_7-G-5,08_1x07_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/7-G-5,08; number of pins: 07; pin pitch: 5.08mm; Angled || order number: 1757297 12A || order number: 1923911 16A (HC) -phoenix_contact connector MSTBA_01x07_G_5.08mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_7-G_1x07_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/7-G; number of pins: 07; pin pitch: 5.00mm; Angled || order number: 1757493 12A || order number: 1923801 16A (HC) -phoenix_contact connector MSTBA_01x07_G_5.00mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_8-G-5,08_1x08_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/8-G-5,08; number of pins: 08; pin pitch: 5.08mm; Angled || order number: 1757307 12A || order number: 1923924 16A (HC) -phoenix_contact connector MSTBA_01x08_G_5.08mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_8-G_1x08_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/8-G; number of pins: 08; pin pitch: 5.00mm; Angled || order number: 1757527 12A || order number: 1923814 16A (HC) -phoenix_contact connector MSTBA_01x08_G_5.00mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_9-G-5,08_1x09_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/9-G-5,08; number of pins: 09; pin pitch: 5.08mm; Angled || order number: 1757310 12A || order number: 1923937 16A (HC) -phoenix_contact connector MSTBA_01x09_G_5.08mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_9-G_1x09_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/9-G; number of pins: 09; pin pitch: 5.00mm; Angled || order number: 1757530 12A || order number: 1923827 16A (HC) -phoenix_contact connector MSTBA_01x09_G_5.00mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_10-G-5,08_1x10_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/10-G-5,08; number of pins: 10; pin pitch: 5.08mm; Angled || order number: 1757323 12A || order number: 1923940 16A (HC) -phoenix_contact connector MSTBA_01x10_G_5.08mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_10-G_1x10_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/10-G; number of pins: 10; pin pitch: 5.00mm; Angled || order number: 1757543 12A || order number: 1923830 16A (HC) -phoenix_contact connector MSTBA_01x10_G_5.00mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_11-G-5,08_1x11_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/11-G-5,08; number of pins: 11; pin pitch: 5.08mm; Angled || order number: 1757336 12A || order number: 1923953 16A (HC) -phoenix_contact connector MSTBA_01x11_G_5.08mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_11-G_1x11_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/11-G; number of pins: 11; pin pitch: 5.00mm; Angled || order number: 1757556 12A || order number: 1923843 16A (HC) -phoenix_contact connector MSTBA_01x11_G_5.00mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_12-G-5,08_1x12_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/12-G-5,08; number of pins: 12; pin pitch: 5.08mm; Angled || order number: 1757349 12A || order number: 1923966 16A (HC) -phoenix_contact connector MSTBA_01x12_G_5.08mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_12-G_1x12_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/12-G; number of pins: 12; pin pitch: 5.00mm; Angled || order number: 1757569 12A || order number: 1923856 16A (HC) -phoenix_contact connector MSTBA_01x12_G_5.00mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_13-G-5,08_1x13_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/13-G-5,08; number of pins: 13; pin pitch: 5.08mm; Angled || order number: 1757352 12A -phoenix_contact connector MSTBA_01x13_G_5.08mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_13-G_1x13_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/13-G; number of pins: 13; pin pitch: 5.00mm; Angled || order number: 1757572 12A -phoenix_contact connector MSTBA_01x13_G_5.00mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_14-G-5,08_1x14_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/14-G-5,08; number of pins: 14; pin pitch: 5.08mm; Angled || order number: 1757365 12A -phoenix_contact connector MSTBA_01x14_G_5.08mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_14-G_1x14_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/14-G; number of pins: 14; pin pitch: 5.00mm; Angled || order number: 1757585 12A -phoenix_contact connector MSTBA_01x14_G_5.00mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_15-G-5,08_1x15_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/15-G-5,08; number of pins: 15; pin pitch: 5.08mm; Angled || order number: 1757378 12A -phoenix_contact connector MSTBA_01x15_G_5.08mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_15-G_1x15_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/15-G; number of pins: 15; pin pitch: 5.00mm; Angled || order number: 1757598 12A -phoenix_contact connector MSTBA_01x15_G_5.00mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_16-G-5,08_1x16_P5.08mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/16-G-5,08; number of pins: 16; pin pitch: 5.08mm; Angled || order number: 1757381 12A -phoenix_contact connector MSTBA_01x16_G_5.08mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBA_2,5_16-G_1x16_P5.00mm_Horizontal -Generic Phoenix Contact connector footprint for: MSTBA_2,5/16-G; number of pins: 16; pin pitch: 5.00mm; Angled || order number: 1757608 12A -phoenix_contact connector MSTBA_01x16_G_5.00mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_2-G-5,08_1x02_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical || order number: 1755736 12A || order number: 1924305 16A (HC) -phoenix_contact connector MSTBVA_01x02_G_5.08mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_2-G_1x02_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Vertical || order number: 1755516 12A || order number: 1924198 16A (HC) -phoenix_contact connector MSTBVA_01x02_G_5.00mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_3-G-5,08_1x03_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/3-G-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical || order number: 1755749 12A || order number: 1924318 16A (HC) -phoenix_contact connector MSTBVA_01x03_G_5.08mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_3-G_1x03_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/3-G; number of pins: 03; pin pitch: 5.00mm; Vertical || order number: 1755529 12A || order number: 1924208 16A (HC) -phoenix_contact connector MSTBVA_01x03_G_5.00mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_4-G-5,08_1x04_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical || order number: 1755752 12A || order number: 1924321 16A (HC) -phoenix_contact connector MSTBVA_01x04_G_5.08mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_4-G_1x04_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Vertical || order number: 1755532 12A || order number: 1924211 16A (HC) -phoenix_contact connector MSTBVA_01x04_G_5.00mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_5-G-5,08_1x05_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/5-G-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical || order number: 1755765 12A || order number: 1924334 16A (HC) -phoenix_contact connector MSTBVA_01x05_G_5.08mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_5-G_1x05_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/5-G; number of pins: 05; pin pitch: 5.00mm; Vertical || order number: 1755545 12A || order number: 1924224 16A (HC) -phoenix_contact connector MSTBVA_01x05_G_5.00mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_6-G-5,08_1x06_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/6-G-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical || order number: 1755778 12A || order number: 1924347 16A (HC) -phoenix_contact connector MSTBVA_01x06_G_5.08mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_6-G_1x06_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/6-G; number of pins: 06; pin pitch: 5.00mm; Vertical || order number: 1755558 12A || order number: 1924237 16A (HC) -phoenix_contact connector MSTBVA_01x06_G_5.00mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_7-G-5,08_1x07_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/7-G-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical || order number: 1755781 12A || order number: 1924350 16A (HC) -phoenix_contact connector MSTBVA_01x07_G_5.08mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_7-G_1x07_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/7-G; number of pins: 07; pin pitch: 5.00mm; Vertical || order number: 1755561 12A || order number: 1924240 16A (HC) -phoenix_contact connector MSTBVA_01x07_G_5.00mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_8-G-5,08_1x08_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/8-G-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical || order number: 1755794 12A || order number: 1924363 16A (HC) -phoenix_contact connector MSTBVA_01x08_G_5.08mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_8-G_1x08_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/8-G; number of pins: 08; pin pitch: 5.00mm; Vertical || order number: 1755574 12A || order number: 1924253 16A (HC) -phoenix_contact connector MSTBVA_01x08_G_5.00mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_9-G-5,08_1x09_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/9-G-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical || order number: 1755804 12A || order number: 1924376 16A (HC) -phoenix_contact connector MSTBVA_01x09_G_5.08mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_9-G_1x09_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/9-G; number of pins: 09; pin pitch: 5.00mm; Vertical || order number: 1755587 12A || order number: 1924266 16A (HC) -phoenix_contact connector MSTBVA_01x09_G_5.00mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_10-G-5,08_1x10_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/10-G-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical || order number: 1755817 12A || order number: 1924389 16A (HC) -phoenix_contact connector MSTBVA_01x10_G_5.08mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_10-G_1x10_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/10-G; number of pins: 10; pin pitch: 5.00mm; Vertical || order number: 1755503 12A || order number: 1924279 16A (HC) -phoenix_contact connector MSTBVA_01x10_G_5.00mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_11-G-5,08_1x11_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/11-G-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical || order number: 1755820 12A || order number: 1924392 16A (HC) -phoenix_contact connector MSTBVA_01x11_G_5.08mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_11-G_1x11_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/11-G; number of pins: 11; pin pitch: 5.00mm; Vertical || order number: 1755590 12A || order number: 1924282 16A (HC) -phoenix_contact connector MSTBVA_01x11_G_5.00mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_12-G-5,08_1x12_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/12-G-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical || order number: 1755833 12A || order number: 1924402 16A (HC) -phoenix_contact connector MSTBVA_01x12_G_5.08mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_12-G_1x12_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/12-G; number of pins: 12; pin pitch: 5.00mm; Vertical || order number: 1755600 12A || order number: 1924295 16A (HC) -phoenix_contact connector MSTBVA_01x12_G_5.00mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_13-G-5,08_1x13_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/13-G-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical || order number: 1755846 12A -phoenix_contact connector MSTBVA_01x13_G_5.08mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_13-G_1x13_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/13-G; number of pins: 13; pin pitch: 5.00mm; Vertical || order number: 1755613 12A -phoenix_contact connector MSTBVA_01x13_G_5.00mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_14-G-5,08_1x14_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/14-G-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical || order number: 1755859 12A -phoenix_contact connector MSTBVA_01x14_G_5.08mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_14-G_1x14_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/14-G; number of pins: 14; pin pitch: 5.00mm; Vertical || order number: 1755626 12A -phoenix_contact connector MSTBVA_01x14_G_5.00mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_15-G-5,08_1x15_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/15-G-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical || order number: 1755862 12A -phoenix_contact connector MSTBVA_01x15_G_5.08mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_15-G_1x15_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/15-G; number of pins: 15; pin pitch: 5.00mm; Vertical || order number: 1755639 12A -phoenix_contact connector MSTBVA_01x15_G_5.00mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_16-G-5,08_1x16_P5.08mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/16-G-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical || order number: 1755875 12A -phoenix_contact connector MSTBVA_01x16_G_5.08mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBVA_2,5_16-G_1x16_P5.00mm_Vertical -Generic Phoenix Contact connector footprint for: MSTBVA_2,5/16-G; number of pins: 16; pin pitch: 5.00mm; Vertical || order number: 1755642 12A -phoenix_contact connector MSTBVA_01x16_G_5.00mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_2-GF-5,08_1x02_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777073 12A || order number: 1924525 16A (HC) -phoenix_contact connector MSTBV_01x02_GF_5.08mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_2-GF-5,08_1x02_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777073 12A || order number: 1924525 16A (HC) -phoenix_contact connector MSTBV_01x02_GF_5.08mm_MH -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_2-GF_1x02_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776883 12A || order number: 1924415 16A (HC) -phoenix_contact connector MSTBV_01x02_GF_5.00mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_2-GF_1x02_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776883 12A || order number: 1924415 16A (HC) -phoenix_contact connector MSTBV_01x02_GF_5.00mm_MH -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_3-GF-5,08_1x03_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777086 12A || order number: 1924538 16A (HC) -phoenix_contact connector MSTBV_01x03_GF_5.08mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_3-GF-5,08_1x03_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777086 12A || order number: 1924538 16A (HC) -phoenix_contact connector MSTBV_01x03_GF_5.08mm_MH -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_3-GF_1x03_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776896 12A || order number: 1924428 16A (HC) -phoenix_contact connector MSTBV_01x03_GF_5.00mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_3-GF_1x03_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776896 12A || order number: 1924428 16A (HC) -phoenix_contact connector MSTBV_01x03_GF_5.00mm_MH -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_4-GF-5,08_1x04_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777099 12A || order number: 1924541 16A (HC) -phoenix_contact connector MSTBV_01x04_GF_5.08mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_4-GF-5,08_1x04_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777099 12A || order number: 1924541 16A (HC) -phoenix_contact connector MSTBV_01x04_GF_5.08mm_MH -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_4-GF_1x04_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776906 12A || order number: 1924431 16A (HC) -phoenix_contact connector MSTBV_01x04_GF_5.00mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_4-GF_1x04_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776906 12A || order number: 1924431 16A (HC) -phoenix_contact connector MSTBV_01x04_GF_5.00mm_MH -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_5-GF-5,08_1x05_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777109 12A || order number: 1924554 16A (HC) -phoenix_contact connector MSTBV_01x05_GF_5.08mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_5-GF-5,08_1x05_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777109 12A || order number: 1924554 16A (HC) -phoenix_contact connector MSTBV_01x05_GF_5.08mm_MH -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_5-GF_1x05_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776919 12A || order number: 1924444 16A (HC) -phoenix_contact connector MSTBV_01x05_GF_5.00mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_5-GF_1x05_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776919 12A || order number: 1924444 16A (HC) -phoenix_contact connector MSTBV_01x05_GF_5.00mm_MH -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_6-GF-5,08_1x06_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777112 12A || order number: 1924567 16A (HC) -phoenix_contact connector MSTBV_01x06_GF_5.08mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_6-GF-5,08_1x06_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777112 12A || order number: 1924567 16A (HC) -phoenix_contact connector MSTBV_01x06_GF_5.08mm_MH -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_6-GF_1x06_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776922 12A || order number: 1924457 16A (HC) -phoenix_contact connector MSTBV_01x06_GF_5.00mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_6-GF_1x06_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776922 12A || order number: 1924457 16A (HC) -phoenix_contact connector MSTBV_01x06_GF_5.00mm_MH -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_7-GF-5,08_1x07_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777125 12A || order number: 1924570 16A (HC) -phoenix_contact connector MSTBV_01x07_GF_5.08mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_7-GF-5,08_1x07_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777125 12A || order number: 1924570 16A (HC) -phoenix_contact connector MSTBV_01x07_GF_5.08mm_MH -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_7-GF_1x07_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776935 12A || order number: 1924460 16A (HC) -phoenix_contact connector MSTBV_01x07_GF_5.00mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_7-GF_1x07_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776935 12A || order number: 1924460 16A (HC) -phoenix_contact connector MSTBV_01x07_GF_5.00mm_MH -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_8-GF-5,08_1x08_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777138 12A || order number: 1924583 16A (HC) -phoenix_contact connector MSTBV_01x08_GF_5.08mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_8-GF-5,08_1x08_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777138 12A || order number: 1924583 16A (HC) -phoenix_contact connector MSTBV_01x08_GF_5.08mm_MH -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_8-GF_1x08_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776948 12A || order number: 1924473 16A (HC) -phoenix_contact connector MSTBV_01x08_GF_5.00mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_8-GF_1x08_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776948 12A || order number: 1924473 16A (HC) -phoenix_contact connector MSTBV_01x08_GF_5.00mm_MH -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_9-GF-5,08_1x09_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777141 12A || order number: 1924596 16A (HC) -phoenix_contact connector MSTBV_01x09_GF_5.08mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_9-GF-5,08_1x09_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777141 12A || order number: 1924596 16A (HC) -phoenix_contact connector MSTBV_01x09_GF_5.08mm_MH -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_9-GF_1x09_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776951 12A || order number: 1924486 16A (HC) -phoenix_contact connector MSTBV_01x09_GF_5.00mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_9-GF_1x09_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776951 12A || order number: 1924486 16A (HC) -phoenix_contact connector MSTBV_01x09_GF_5.00mm_MH -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_10-GF-5,08_1x10_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777154 12A || order number: 1924606 16A (HC) -phoenix_contact connector MSTBV_01x10_GF_5.08mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_10-GF-5,08_1x10_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777154 12A || order number: 1924606 16A (HC) -phoenix_contact connector MSTBV_01x10_GF_5.08mm_MH -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_10-GF_1x10_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776964 12A || order number: 1924499 16A (HC) -phoenix_contact connector MSTBV_01x10_GF_5.00mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_10-GF_1x10_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776964 12A || order number: 1924499 16A (HC) -phoenix_contact connector MSTBV_01x10_GF_5.00mm_MH -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_11-GF-5,08_1x11_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777167 12A || order number: 1924619 16A (HC) -phoenix_contact connector MSTBV_01x11_GF_5.08mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_11-GF-5,08_1x11_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777167 12A || order number: 1924619 16A (HC) -phoenix_contact connector MSTBV_01x11_GF_5.08mm_MH -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_11-GF_1x11_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776977 12A || order number: 1924509 16A (HC) -phoenix_contact connector MSTBV_01x11_GF_5.00mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_11-GF_1x11_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776977 12A || order number: 1924509 16A (HC) -phoenix_contact connector MSTBV_01x11_GF_5.00mm_MH -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_12-GF-5,08_1x12_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777170 12A || order number: 1924622 16A (HC) -phoenix_contact connector MSTBV_01x12_GF_5.08mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_12-GF-5,08_1x12_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777170 12A || order number: 1924622 16A (HC) -phoenix_contact connector MSTBV_01x12_GF_5.08mm_MH -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_12-GF_1x12_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776980 12A || order number: 1924512 16A (HC) -phoenix_contact connector MSTBV_01x12_GF_5.00mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_12-GF_1x12_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776980 12A || order number: 1924512 16A (HC) -phoenix_contact connector MSTBV_01x12_GF_5.00mm_MH -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_13-GF-5,08_1x13_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777183 12A -phoenix_contact connector MSTBV_01x13_GF_5.08mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_13-GF-5,08_1x13_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777183 12A -phoenix_contact connector MSTBV_01x13_GF_5.08mm_MH -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_13-GF_1x13_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776993 12A -phoenix_contact connector MSTBV_01x13_GF_5.00mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_13-GF_1x13_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776993 12A -phoenix_contact connector MSTBV_01x13_GF_5.00mm_MH -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_14-GF-5,08_1x14_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777196 12A -phoenix_contact connector MSTBV_01x14_GF_5.08mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_14-GF-5,08_1x14_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777196 12A -phoenix_contact connector MSTBV_01x14_GF_5.08mm_MH -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_14-GF_1x14_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776002 12A -phoenix_contact connector MSTBV_01x14_GF_5.00mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_14-GF_1x14_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776002 12A -phoenix_contact connector MSTBV_01x14_GF_5.00mm_MH -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_15-GF-5,08_1x15_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777206 12A -phoenix_contact connector MSTBV_01x15_GF_5.08mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_15-GF-5,08_1x15_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777206 12A -phoenix_contact connector MSTBV_01x15_GF_5.08mm_MH -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_15-GF_1x15_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776015 12A -phoenix_contact connector MSTBV_01x15_GF_5.00mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_15-GF_1x15_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776015 12A -phoenix_contact connector MSTBV_01x15_GF_5.00mm_MH -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_16-GF-5,08_1x16_P5.08mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777219 12A -phoenix_contact connector MSTBV_01x16_GF_5.08mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_16-GF-5,08_1x16_P5.08mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777219 12A -phoenix_contact connector MSTBV_01x16_GF_5.08mm_MH -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_16-GF_1x16_P5.00mm_Vertical_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776028 12A -phoenix_contact connector MSTBV_01x16_GF_5.00mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTBV_2,5_16-GF_1x16_P5.00mm_Vertical_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776028 12A -phoenix_contact connector MSTBV_01x16_GF_5.00mm_MH -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_2-GF-5,08_1x02_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776508 12A || order number: 1924088 16A (HC) -phoenix_contact connector MSTB_01x02_GF_5.08mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_2-GF-5,08_1x02_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776508 12A || order number: 1924088 16A (HC) -phoenix_contact connector MSTB_01x02_GF_5.08mm_MH -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_2-GF_1x02_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776692 12A || order number: 1923979 16A (HC) -phoenix_contact connector MSTB_01x02_GF_5.00mm -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_2-GF_1x02_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776692 12A || order number: 1923979 16A (HC) -phoenix_contact connector MSTB_01x02_GF_5.00mm_MH -0 -2 -2 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_3-GF-5,08_1x03_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776511 12A || order number: 1924091 16A (HC) -phoenix_contact connector MSTB_01x03_GF_5.08mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_3-GF-5,08_1x03_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776511 12A || order number: 1924091 16A (HC) -phoenix_contact connector MSTB_01x03_GF_5.08mm_MH -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_3-GF_1x03_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776702 12A || order number: 1923982 16A (HC) -phoenix_contact connector MSTB_01x03_GF_5.00mm -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_3-GF_1x03_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776702 12A || order number: 1923982 16A (HC) -phoenix_contact connector MSTB_01x03_GF_5.00mm_MH -0 -3 -3 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_4-GF-5,08_1x04_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776524 12A || order number: 1924101 16A (HC) -phoenix_contact connector MSTB_01x04_GF_5.08mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_4-GF-5,08_1x04_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776524 12A || order number: 1924101 16A (HC) -phoenix_contact connector MSTB_01x04_GF_5.08mm_MH -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_4-GF_1x04_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776715 12A || order number: 1923995 16A (HC) -phoenix_contact connector MSTB_01x04_GF_5.00mm -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_4-GF_1x04_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776715 12A || order number: 1923995 16A (HC) -phoenix_contact connector MSTB_01x04_GF_5.00mm_MH -0 -4 -4 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_5-GF-5,08_1x05_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776537 12A || order number: 1924114 16A (HC) -phoenix_contact connector MSTB_01x05_GF_5.08mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_5-GF-5,08_1x05_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776537 12A || order number: 1924114 16A (HC) -phoenix_contact connector MSTB_01x05_GF_5.08mm_MH -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_5-GF_1x05_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776728 12A || order number: 1924004 16A (HC) -phoenix_contact connector MSTB_01x05_GF_5.00mm -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_5-GF_1x05_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776728 12A || order number: 1924004 16A (HC) -phoenix_contact connector MSTB_01x05_GF_5.00mm_MH -0 -5 -5 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_6-GF-5,08_1x06_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776540 12A || order number: 1924127 16A (HC) -phoenix_contact connector MSTB_01x06_GF_5.08mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_6-GF-5,08_1x06_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776540 12A || order number: 1924127 16A (HC) -phoenix_contact connector MSTB_01x06_GF_5.08mm_MH -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_6-GF_1x06_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776731 12A || order number: 1924017 16A (HC) -phoenix_contact connector MSTB_01x06_GF_5.00mm -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_6-GF_1x06_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776731 12A || order number: 1924017 16A (HC) -phoenix_contact connector MSTB_01x06_GF_5.00mm_MH -0 -6 -6 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_7-GF-5,08_1x07_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776553 12A || order number: 1924130 16A (HC) -phoenix_contact connector MSTB_01x07_GF_5.08mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_7-GF-5,08_1x07_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776553 12A || order number: 1924130 16A (HC) -phoenix_contact connector MSTB_01x07_GF_5.08mm_MH -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_7-GF_1x07_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776744 12A || order number: 1924020 16A (HC) -phoenix_contact connector MSTB_01x07_GF_5.00mm -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_7-GF_1x07_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776744 12A || order number: 1924020 16A (HC) -phoenix_contact connector MSTB_01x07_GF_5.00mm_MH -0 -7 -7 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_8-GF-5,08_1x08_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776566 12A || order number: 1924143 16A (HC) -phoenix_contact connector MSTB_01x08_GF_5.08mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_8-GF-5,08_1x08_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776566 12A || order number: 1924143 16A (HC) -phoenix_contact connector MSTB_01x08_GF_5.08mm_MH -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_8-GF_1x08_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776757 12A || order number: 1924033 16A (HC) -phoenix_contact connector MSTB_01x08_GF_5.00mm -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_8-GF_1x08_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776757 12A || order number: 1924033 16A (HC) -phoenix_contact connector MSTB_01x08_GF_5.00mm_MH -0 -8 -8 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_9-GF-5,08_1x09_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776579 12A || order number: 1924156 16A (HC) -phoenix_contact connector MSTB_01x09_GF_5.08mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_9-GF-5,08_1x09_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776579 12A || order number: 1924156 16A (HC) -phoenix_contact connector MSTB_01x09_GF_5.08mm_MH -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_9-GF_1x09_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776760 12A || order number: 1924046 16A (HC) -phoenix_contact connector MSTB_01x09_GF_5.00mm -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_9-GF_1x09_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776760 12A || order number: 1924046 16A (HC) -phoenix_contact connector MSTB_01x09_GF_5.00mm_MH -0 -9 -9 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_10-GF-5,08_1x10_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776582 12A || order number: 1924169 16A (HC) -phoenix_contact connector MSTB_01x10_GF_5.08mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_10-GF-5,08_1x10_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776582 12A || order number: 1924169 16A (HC) -phoenix_contact connector MSTB_01x10_GF_5.08mm_MH -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_10-GF_1x10_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776773 12A || order number: 1924059 16A (HC) -phoenix_contact connector MSTB_01x10_GF_5.00mm -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_10-GF_1x10_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776773 12A || order number: 1924059 16A (HC) -phoenix_contact connector MSTB_01x10_GF_5.00mm_MH -0 -10 -10 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_11-GF-5,08_1x11_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776595 12A || order number: 1924172 16A (HC) -phoenix_contact connector MSTB_01x11_GF_5.08mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_11-GF-5,08_1x11_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776595 12A || order number: 1924172 16A (HC) -phoenix_contact connector MSTB_01x11_GF_5.08mm_MH -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_11-GF_1x11_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776786 12A || order number: 1924062 16A (HC) -phoenix_contact connector MSTB_01x11_GF_5.00mm -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_11-GF_1x11_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776786 12A || order number: 1924062 16A (HC) -phoenix_contact connector MSTB_01x11_GF_5.00mm_MH -0 -11 -11 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_12-GF-5,08_1x12_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776605 12A || order number: 1924185 16A (HC) -phoenix_contact connector MSTB_01x12_GF_5.08mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_12-GF-5,08_1x12_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776605 12A || order number: 1924185 16A (HC) -phoenix_contact connector MSTB_01x12_GF_5.08mm_MH -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_12-GF_1x12_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776799 12A || order number: 1924075 16A (HC) -phoenix_contact connector MSTB_01x12_GF_5.00mm -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_12-GF_1x12_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776799 12A || order number: 1924075 16A (HC) -phoenix_contact connector MSTB_01x12_GF_5.00mm_MH -0 -12 -12 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_13-GF-5,08_1x13_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776618 12A -phoenix_contact connector MSTB_01x13_GF_5.08mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_13-GF-5,08_1x13_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776618 12A -phoenix_contact connector MSTB_01x13_GF_5.08mm_MH -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_13-GF_1x13_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776809 12A -phoenix_contact connector MSTB_01x13_GF_5.00mm -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_13-GF_1x13_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776809 12A -phoenix_contact connector MSTB_01x13_GF_5.00mm_MH -0 -13 -13 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_14-GF-5,08_1x14_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776621 12A -phoenix_contact connector MSTB_01x14_GF_5.08mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_14-GF-5,08_1x14_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776621 12A -phoenix_contact connector MSTB_01x14_GF_5.08mm_MH -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_14-GF_1x14_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776812 12A -phoenix_contact connector MSTB_01x14_GF_5.00mm -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_14-GF_1x14_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776812 12A -phoenix_contact connector MSTB_01x14_GF_5.00mm_MH -0 -14 -14 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_15-GF-5,08_1x15_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776634 12A -phoenix_contact connector MSTB_01x15_GF_5.08mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_15-GF-5,08_1x15_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776634 12A -phoenix_contact connector MSTB_01x15_GF_5.08mm_MH -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_15-GF_1x15_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776825 12A -phoenix_contact connector MSTB_01x15_GF_5.00mm -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_15-GF_1x15_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776825 12A -phoenix_contact connector MSTB_01x15_GF_5.00mm_MH -0 -15 -15 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_16-GF-5,08_1x16_P5.08mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776647 12A -phoenix_contact connector MSTB_01x16_GF_5.08mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_16-GF-5,08_1x16_P5.08mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776647 12A -phoenix_contact connector MSTB_01x16_GF_5.08mm_MH -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_16-GF_1x16_P5.00mm_Horizontal_ThreadedFlange -Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776838 12A -phoenix_contact connector MSTB_01x16_GF_5.00mm -0 -16 -16 -Connector_Phoenix_MSTB -PhoenixContact_MSTB_2,5_16-GF_1x16_P5.00mm_Horizontal_ThreadedFlange_MountHole -Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776838 12A -phoenix_contact connector MSTB_01x16_GF_5.00mm_MH -0 -16 -16 -Connector_Pin -Pin_D0.7mm_L6.5mm_W1.8mm_FlatFork -solder Pin_ with flat fork, hole diameter 0.7mm, length 6.5mm, width 1.8mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D0.9mm_L10.0mm_W2.4mm_FlatFork -solder Pin_ with flat fork, hole diameter 0.9mm, length 10.0mm, width 2.4mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.0mm_L10.0mm -solder Pin_ diameter 1.0mm, hole diameter 1.0mm (press fit), length 10.0mm -solder Pin_ press fit -0 -1 -1 -Connector_Pin -Pin_D1.0mm_L10.0mm_LooseFit -solder Pin_ diameter 1.0mm, hole diameter 1.2mm (loose fit), length 10.0mm -solder Pin_ loose fit -0 -1 -1 -Connector_Pin -Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork -solder Pin_ with flat fork, hole diameter 1.1mm, length 8.5mm, width 2.5mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.1mm_L10.2mm_W3.5mm_Flat -solder Pin_ with flat with hole, hole diameter 1.1mm, length 10.2mm, width 3.5mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.2mm_L10.2mm_W2.9mm_FlatFork -solder Pin_ with flat with fork, hole diameter 1.2mm, length 11.3mm, width 3.0mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.2mm_L11.3mm_W3.0mm_Flat -solder Pin_ with flat with hole, hole diameter 1.2mm, length 11.3mm, width 3.0mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.3mm_L10.0mm_W3.5mm_Flat -solder Pin_ with flat with hole, hole diameter 1.3mm, length 10.0mm, width 3.5mm, e.g. Ettinger 13.13.865, https://katalog.ettinger.de/#p=434 -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.3mm_L11.0mm -solder Pin_ diameter 1.3mm, hole diameter 1.3mm, length 11.0mm -solder Pin_ pressfit -0 -1 -1 -Connector_Pin -Pin_D1.3mm_L11.0mm_LooseFit -solder Pin_ diameter 1.3mm, hole diameter 1.5mm (loose fit), length 11.0mm -solder Pin_ loose fit -0 -1 -1 -Connector_Pin -Pin_D1.3mm_L11.3mm_W2.8mm_Flat -solder Pin_ with flat with hole, hole diameter 1.3mm, length 11.3mm, width 2.8mm -solder Pin_ with flat fork -0 -1 -1 -Connector_Pin -Pin_D1.4mm_L8.5mm_W2.8mm_FlatFork -solder Pin_ with flat with fork, hole diameter 1.4mm, length 8.5mm, width 2.8mm, e.g. Ettinger 13.13.890, https://katalog.ettinger.de/#p=434 -solder Pin_ with flat fork -0 -1 -1 -Connector_PinHeader_1.00mm -PinHeader_1x01_P1.00mm_Horizontal -Through hole angled pin header, 1x01, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x01 1.00mm single row -0 -1 -1 -Connector_PinHeader_1.00mm -PinHeader_1x01_P1.00mm_Vertical -Through hole straight pin header, 1x01, 1.00mm pitch, single row -Through hole pin header THT 1x01 1.00mm single row -0 -1 -1 -Connector_PinHeader_1.00mm -PinHeader_1x02_P1.00mm_Horizontal -Through hole angled pin header, 1x02, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x02 1.00mm single row -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_1x02_P1.00mm_Vertical -Through hole straight pin header, 1x02, 1.00mm pitch, single row -Through hole pin header THT 1x02 1.00mm single row -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_1x02_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x02, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x02 1.00mm single row style1 pin1 left -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_1x02_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x02, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x02 1.00mm single row style2 pin1 right -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_1x03_P1.00mm_Horizontal -Through hole angled pin header, 1x03, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x03 1.00mm single row -0 -3 -3 -Connector_PinHeader_1.00mm -PinHeader_1x03_P1.00mm_Vertical -Through hole straight pin header, 1x03, 1.00mm pitch, single row -Through hole pin header THT 1x03 1.00mm single row -0 -3 -3 -Connector_PinHeader_1.00mm -PinHeader_1x03_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x03, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x03 1.00mm single row style1 pin1 left -0 -3 -3 -Connector_PinHeader_1.00mm -PinHeader_1x03_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x03, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x03 1.00mm single row style2 pin1 right -0 -3 -3 -Connector_PinHeader_1.00mm -PinHeader_1x04_P1.00mm_Horizontal -Through hole angled pin header, 1x04, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x04 1.00mm single row -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_1x04_P1.00mm_Vertical -Through hole straight pin header, 1x04, 1.00mm pitch, single row -Through hole pin header THT 1x04 1.00mm single row -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_1x04_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x04, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x04 1.00mm single row style1 pin1 left -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_1x04_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x04, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x04 1.00mm single row style2 pin1 right -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_1x05_P1.00mm_Horizontal -Through hole angled pin header, 1x05, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x05 1.00mm single row -0 -5 -5 -Connector_PinHeader_1.00mm -PinHeader_1x05_P1.00mm_Vertical -Through hole straight pin header, 1x05, 1.00mm pitch, single row -Through hole pin header THT 1x05 1.00mm single row -0 -5 -5 -Connector_PinHeader_1.00mm -PinHeader_1x05_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x05, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x05 1.00mm single row style1 pin1 left -0 -5 -5 -Connector_PinHeader_1.00mm -PinHeader_1x05_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x05, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x05 1.00mm single row style2 pin1 right -0 -5 -5 -Connector_PinHeader_1.00mm -PinHeader_1x06_P1.00mm_Horizontal -Through hole angled pin header, 1x06, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x06 1.00mm single row -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_1x06_P1.00mm_Vertical -Through hole straight pin header, 1x06, 1.00mm pitch, single row -Through hole pin header THT 1x06 1.00mm single row -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_1x06_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x06, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x06 1.00mm single row style1 pin1 left -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_1x06_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x06, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x06 1.00mm single row style2 pin1 right -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_1x07_P1.00mm_Horizontal -Through hole angled pin header, 1x07, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x07 1.00mm single row -0 -7 -7 -Connector_PinHeader_1.00mm -PinHeader_1x07_P1.00mm_Vertical -Through hole straight pin header, 1x07, 1.00mm pitch, single row -Through hole pin header THT 1x07 1.00mm single row -0 -7 -7 -Connector_PinHeader_1.00mm -PinHeader_1x07_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x07, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x07 1.00mm single row style1 pin1 left -0 -7 -7 -Connector_PinHeader_1.00mm -PinHeader_1x07_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x07, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x07 1.00mm single row style2 pin1 right -0 -7 -7 -Connector_PinHeader_1.00mm -PinHeader_1x08_P1.00mm_Horizontal -Through hole angled pin header, 1x08, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x08 1.00mm single row -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_1x08_P1.00mm_Vertical -Through hole straight pin header, 1x08, 1.00mm pitch, single row -Through hole pin header THT 1x08 1.00mm single row -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_1x08_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x08, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x08 1.00mm single row style1 pin1 left -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_1x08_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x08, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x08 1.00mm single row style2 pin1 right -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_1x09_P1.00mm_Horizontal -Through hole angled pin header, 1x09, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x09 1.00mm single row -0 -9 -9 -Connector_PinHeader_1.00mm -PinHeader_1x09_P1.00mm_Vertical -Through hole straight pin header, 1x09, 1.00mm pitch, single row -Through hole pin header THT 1x09 1.00mm single row -0 -9 -9 -Connector_PinHeader_1.00mm -PinHeader_1x09_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x09, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x09 1.00mm single row style1 pin1 left -0 -9 -9 -Connector_PinHeader_1.00mm -PinHeader_1x09_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x09, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x09 1.00mm single row style2 pin1 right -0 -9 -9 -Connector_PinHeader_1.00mm -PinHeader_1x10_P1.00mm_Horizontal -Through hole angled pin header, 1x10, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x10 1.00mm single row -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_1x10_P1.00mm_Vertical -Through hole straight pin header, 1x10, 1.00mm pitch, single row -Through hole pin header THT 1x10 1.00mm single row -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_1x10_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x10, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x10 1.00mm single row style1 pin1 left -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_1x10_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x10, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x10 1.00mm single row style2 pin1 right -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_1x11_P1.00mm_Horizontal -Through hole angled pin header, 1x11, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x11 1.00mm single row -0 -11 -11 -Connector_PinHeader_1.00mm -PinHeader_1x11_P1.00mm_Vertical -Through hole straight pin header, 1x11, 1.00mm pitch, single row -Through hole pin header THT 1x11 1.00mm single row -0 -11 -11 -Connector_PinHeader_1.00mm -PinHeader_1x11_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x11, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x11 1.00mm single row style1 pin1 left -0 -11 -11 -Connector_PinHeader_1.00mm -PinHeader_1x11_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x11, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x11 1.00mm single row style2 pin1 right -0 -11 -11 -Connector_PinHeader_1.00mm -PinHeader_1x12_P1.00mm_Horizontal -Through hole angled pin header, 1x12, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x12 1.00mm single row -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_1x12_P1.00mm_Vertical -Through hole straight pin header, 1x12, 1.00mm pitch, single row -Through hole pin header THT 1x12 1.00mm single row -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_1x12_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x12, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x12 1.00mm single row style1 pin1 left -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_1x12_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x12, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x12 1.00mm single row style2 pin1 right -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_1x13_P1.00mm_Horizontal -Through hole angled pin header, 1x13, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x13 1.00mm single row -0 -13 -13 -Connector_PinHeader_1.00mm -PinHeader_1x13_P1.00mm_Vertical -Through hole straight pin header, 1x13, 1.00mm pitch, single row -Through hole pin header THT 1x13 1.00mm single row -0 -13 -13 -Connector_PinHeader_1.00mm -PinHeader_1x13_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x13, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x13 1.00mm single row style1 pin1 left -0 -13 -13 -Connector_PinHeader_1.00mm -PinHeader_1x13_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x13, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x13 1.00mm single row style2 pin1 right -0 -13 -13 -Connector_PinHeader_1.00mm -PinHeader_1x14_P1.00mm_Horizontal -Through hole angled pin header, 1x14, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x14 1.00mm single row -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_1x14_P1.00mm_Vertical -Through hole straight pin header, 1x14, 1.00mm pitch, single row -Through hole pin header THT 1x14 1.00mm single row -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_1x14_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x14, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x14 1.00mm single row style1 pin1 left -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_1x14_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x14, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x14 1.00mm single row style2 pin1 right -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_1x15_P1.00mm_Horizontal -Through hole angled pin header, 1x15, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x15 1.00mm single row -0 -15 -15 -Connector_PinHeader_1.00mm -PinHeader_1x15_P1.00mm_Vertical -Through hole straight pin header, 1x15, 1.00mm pitch, single row -Through hole pin header THT 1x15 1.00mm single row -0 -15 -15 -Connector_PinHeader_1.00mm -PinHeader_1x15_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x15, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x15 1.00mm single row style1 pin1 left -0 -15 -15 -Connector_PinHeader_1.00mm -PinHeader_1x15_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x15, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x15 1.00mm single row style2 pin1 right -0 -15 -15 -Connector_PinHeader_1.00mm -PinHeader_1x16_P1.00mm_Horizontal -Through hole angled pin header, 1x16, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x16 1.00mm single row -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_1x16_P1.00mm_Vertical -Through hole straight pin header, 1x16, 1.00mm pitch, single row -Through hole pin header THT 1x16 1.00mm single row -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_1x16_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x16, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x16 1.00mm single row style1 pin1 left -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_1x16_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x16, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x16 1.00mm single row style2 pin1 right -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_1x17_P1.00mm_Horizontal -Through hole angled pin header, 1x17, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x17 1.00mm single row -0 -17 -17 -Connector_PinHeader_1.00mm -PinHeader_1x17_P1.00mm_Vertical -Through hole straight pin header, 1x17, 1.00mm pitch, single row -Through hole pin header THT 1x17 1.00mm single row -0 -17 -17 -Connector_PinHeader_1.00mm -PinHeader_1x17_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x17, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x17 1.00mm single row style1 pin1 left -0 -17 -17 -Connector_PinHeader_1.00mm -PinHeader_1x17_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x17, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x17 1.00mm single row style2 pin1 right -0 -17 -17 -Connector_PinHeader_1.00mm -PinHeader_1x18_P1.00mm_Horizontal -Through hole angled pin header, 1x18, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x18 1.00mm single row -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_1x18_P1.00mm_Vertical -Through hole straight pin header, 1x18, 1.00mm pitch, single row -Through hole pin header THT 1x18 1.00mm single row -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_1x18_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x18, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x18 1.00mm single row style1 pin1 left -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_1x18_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x18, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x18 1.00mm single row style2 pin1 right -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_1x19_P1.00mm_Horizontal -Through hole angled pin header, 1x19, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x19 1.00mm single row -0 -19 -19 -Connector_PinHeader_1.00mm -PinHeader_1x19_P1.00mm_Vertical -Through hole straight pin header, 1x19, 1.00mm pitch, single row -Through hole pin header THT 1x19 1.00mm single row -0 -19 -19 -Connector_PinHeader_1.00mm -PinHeader_1x19_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x19, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x19 1.00mm single row style1 pin1 left -0 -19 -19 -Connector_PinHeader_1.00mm -PinHeader_1x19_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x19, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x19 1.00mm single row style2 pin1 right -0 -19 -19 -Connector_PinHeader_1.00mm -PinHeader_1x20_P1.00mm_Horizontal -Through hole angled pin header, 1x20, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x20 1.00mm single row -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_1x20_P1.00mm_Vertical -Through hole straight pin header, 1x20, 1.00mm pitch, single row -Through hole pin header THT 1x20 1.00mm single row -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_1x20_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x20, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x20 1.00mm single row style1 pin1 left -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_1x20_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x20, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x20 1.00mm single row style2 pin1 right -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_1x21_P1.00mm_Horizontal -Through hole angled pin header, 1x21, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x21 1.00mm single row -0 -21 -21 -Connector_PinHeader_1.00mm -PinHeader_1x21_P1.00mm_Vertical -Through hole straight pin header, 1x21, 1.00mm pitch, single row -Through hole pin header THT 1x21 1.00mm single row -0 -21 -21 -Connector_PinHeader_1.00mm -PinHeader_1x21_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x21, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x21 1.00mm single row style1 pin1 left -0 -21 -21 -Connector_PinHeader_1.00mm -PinHeader_1x21_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x21, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x21 1.00mm single row style2 pin1 right -0 -21 -21 -Connector_PinHeader_1.00mm -PinHeader_1x22_P1.00mm_Horizontal -Through hole angled pin header, 1x22, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x22 1.00mm single row -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_1x22_P1.00mm_Vertical -Through hole straight pin header, 1x22, 1.00mm pitch, single row -Through hole pin header THT 1x22 1.00mm single row -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_1x22_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x22, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x22 1.00mm single row style1 pin1 left -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_1x22_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x22, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x22 1.00mm single row style2 pin1 right -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_1x23_P1.00mm_Horizontal -Through hole angled pin header, 1x23, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x23 1.00mm single row -0 -23 -23 -Connector_PinHeader_1.00mm -PinHeader_1x23_P1.00mm_Vertical -Through hole straight pin header, 1x23, 1.00mm pitch, single row -Through hole pin header THT 1x23 1.00mm single row -0 -23 -23 -Connector_PinHeader_1.00mm -PinHeader_1x23_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x23, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x23 1.00mm single row style1 pin1 left -0 -23 -23 -Connector_PinHeader_1.00mm -PinHeader_1x23_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x23, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x23 1.00mm single row style2 pin1 right -0 -23 -23 -Connector_PinHeader_1.00mm -PinHeader_1x24_P1.00mm_Horizontal -Through hole angled pin header, 1x24, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x24 1.00mm single row -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_1x24_P1.00mm_Vertical -Through hole straight pin header, 1x24, 1.00mm pitch, single row -Through hole pin header THT 1x24 1.00mm single row -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_1x24_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x24, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x24 1.00mm single row style1 pin1 left -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_1x24_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x24, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x24 1.00mm single row style2 pin1 right -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_1x25_P1.00mm_Horizontal -Through hole angled pin header, 1x25, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x25 1.00mm single row -0 -25 -25 -Connector_PinHeader_1.00mm -PinHeader_1x25_P1.00mm_Vertical -Through hole straight pin header, 1x25, 1.00mm pitch, single row -Through hole pin header THT 1x25 1.00mm single row -0 -25 -25 -Connector_PinHeader_1.00mm -PinHeader_1x25_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x25, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x25 1.00mm single row style1 pin1 left -0 -25 -25 -Connector_PinHeader_1.00mm -PinHeader_1x25_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x25, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x25 1.00mm single row style2 pin1 right -0 -25 -25 -Connector_PinHeader_1.00mm -PinHeader_1x26_P1.00mm_Horizontal -Through hole angled pin header, 1x26, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x26 1.00mm single row -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_1x26_P1.00mm_Vertical -Through hole straight pin header, 1x26, 1.00mm pitch, single row -Through hole pin header THT 1x26 1.00mm single row -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_1x26_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x26, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x26 1.00mm single row style1 pin1 left -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_1x26_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x26, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x26 1.00mm single row style2 pin1 right -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_1x27_P1.00mm_Horizontal -Through hole angled pin header, 1x27, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x27 1.00mm single row -0 -27 -27 -Connector_PinHeader_1.00mm -PinHeader_1x27_P1.00mm_Vertical -Through hole straight pin header, 1x27, 1.00mm pitch, single row -Through hole pin header THT 1x27 1.00mm single row -0 -27 -27 -Connector_PinHeader_1.00mm -PinHeader_1x27_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x27, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x27 1.00mm single row style1 pin1 left -0 -27 -27 -Connector_PinHeader_1.00mm -PinHeader_1x27_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x27, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x27 1.00mm single row style2 pin1 right -0 -27 -27 -Connector_PinHeader_1.00mm -PinHeader_1x28_P1.00mm_Horizontal -Through hole angled pin header, 1x28, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x28 1.00mm single row -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_1x28_P1.00mm_Vertical -Through hole straight pin header, 1x28, 1.00mm pitch, single row -Through hole pin header THT 1x28 1.00mm single row -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_1x28_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x28, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x28 1.00mm single row style1 pin1 left -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_1x28_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x28, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x28 1.00mm single row style2 pin1 right -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_1x29_P1.00mm_Horizontal -Through hole angled pin header, 1x29, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x29 1.00mm single row -0 -29 -29 -Connector_PinHeader_1.00mm -PinHeader_1x29_P1.00mm_Vertical -Through hole straight pin header, 1x29, 1.00mm pitch, single row -Through hole pin header THT 1x29 1.00mm single row -0 -29 -29 -Connector_PinHeader_1.00mm -PinHeader_1x29_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x29, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x29 1.00mm single row style1 pin1 left -0 -29 -29 -Connector_PinHeader_1.00mm -PinHeader_1x29_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x29, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x29 1.00mm single row style2 pin1 right -0 -29 -29 -Connector_PinHeader_1.00mm -PinHeader_1x30_P1.00mm_Horizontal -Through hole angled pin header, 1x30, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x30 1.00mm single row -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_1x30_P1.00mm_Vertical -Through hole straight pin header, 1x30, 1.00mm pitch, single row -Through hole pin header THT 1x30 1.00mm single row -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_1x30_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x30, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x30 1.00mm single row style1 pin1 left -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_1x30_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x30, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x30 1.00mm single row style2 pin1 right -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_1x31_P1.00mm_Horizontal -Through hole angled pin header, 1x31, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x31 1.00mm single row -0 -31 -31 -Connector_PinHeader_1.00mm -PinHeader_1x31_P1.00mm_Vertical -Through hole straight pin header, 1x31, 1.00mm pitch, single row -Through hole pin header THT 1x31 1.00mm single row -0 -31 -31 -Connector_PinHeader_1.00mm -PinHeader_1x31_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x31, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x31 1.00mm single row style1 pin1 left -0 -31 -31 -Connector_PinHeader_1.00mm -PinHeader_1x31_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x31, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x31 1.00mm single row style2 pin1 right -0 -31 -31 -Connector_PinHeader_1.00mm -PinHeader_1x32_P1.00mm_Horizontal -Through hole angled pin header, 1x32, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x32 1.00mm single row -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_1x32_P1.00mm_Vertical -Through hole straight pin header, 1x32, 1.00mm pitch, single row -Through hole pin header THT 1x32 1.00mm single row -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_1x32_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x32, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x32 1.00mm single row style1 pin1 left -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_1x32_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x32, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x32 1.00mm single row style2 pin1 right -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_1x33_P1.00mm_Horizontal -Through hole angled pin header, 1x33, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x33 1.00mm single row -0 -33 -33 -Connector_PinHeader_1.00mm -PinHeader_1x33_P1.00mm_Vertical -Through hole straight pin header, 1x33, 1.00mm pitch, single row -Through hole pin header THT 1x33 1.00mm single row -0 -33 -33 -Connector_PinHeader_1.00mm -PinHeader_1x33_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x33, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x33 1.00mm single row style1 pin1 left -0 -33 -33 -Connector_PinHeader_1.00mm -PinHeader_1x33_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x33, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x33 1.00mm single row style2 pin1 right -0 -33 -33 -Connector_PinHeader_1.00mm -PinHeader_1x34_P1.00mm_Horizontal -Through hole angled pin header, 1x34, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x34 1.00mm single row -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_1x34_P1.00mm_Vertical -Through hole straight pin header, 1x34, 1.00mm pitch, single row -Through hole pin header THT 1x34 1.00mm single row -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_1x34_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x34, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x34 1.00mm single row style1 pin1 left -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_1x34_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x34, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x34 1.00mm single row style2 pin1 right -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_1x35_P1.00mm_Horizontal -Through hole angled pin header, 1x35, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x35 1.00mm single row -0 -35 -35 -Connector_PinHeader_1.00mm -PinHeader_1x35_P1.00mm_Vertical -Through hole straight pin header, 1x35, 1.00mm pitch, single row -Through hole pin header THT 1x35 1.00mm single row -0 -35 -35 -Connector_PinHeader_1.00mm -PinHeader_1x35_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x35, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x35 1.00mm single row style1 pin1 left -0 -35 -35 -Connector_PinHeader_1.00mm -PinHeader_1x35_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x35, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x35 1.00mm single row style2 pin1 right -0 -35 -35 -Connector_PinHeader_1.00mm -PinHeader_1x36_P1.00mm_Horizontal -Through hole angled pin header, 1x36, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x36 1.00mm single row -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_1x36_P1.00mm_Vertical -Through hole straight pin header, 1x36, 1.00mm pitch, single row -Through hole pin header THT 1x36 1.00mm single row -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_1x36_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x36, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x36 1.00mm single row style1 pin1 left -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_1x36_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x36, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x36 1.00mm single row style2 pin1 right -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_1x37_P1.00mm_Horizontal -Through hole angled pin header, 1x37, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x37 1.00mm single row -0 -37 -37 -Connector_PinHeader_1.00mm -PinHeader_1x37_P1.00mm_Vertical -Through hole straight pin header, 1x37, 1.00mm pitch, single row -Through hole pin header THT 1x37 1.00mm single row -0 -37 -37 -Connector_PinHeader_1.00mm -PinHeader_1x37_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x37, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x37 1.00mm single row style1 pin1 left -0 -37 -37 -Connector_PinHeader_1.00mm -PinHeader_1x37_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x37, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x37 1.00mm single row style2 pin1 right -0 -37 -37 -Connector_PinHeader_1.00mm -PinHeader_1x38_P1.00mm_Horizontal -Through hole angled pin header, 1x38, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x38 1.00mm single row -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_1x38_P1.00mm_Vertical -Through hole straight pin header, 1x38, 1.00mm pitch, single row -Through hole pin header THT 1x38 1.00mm single row -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_1x38_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x38, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x38 1.00mm single row style1 pin1 left -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_1x38_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x38, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x38 1.00mm single row style2 pin1 right -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_1x39_P1.00mm_Horizontal -Through hole angled pin header, 1x39, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x39 1.00mm single row -0 -39 -39 -Connector_PinHeader_1.00mm -PinHeader_1x39_P1.00mm_Vertical -Through hole straight pin header, 1x39, 1.00mm pitch, single row -Through hole pin header THT 1x39 1.00mm single row -0 -39 -39 -Connector_PinHeader_1.00mm -PinHeader_1x39_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x39, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x39 1.00mm single row style1 pin1 left -0 -39 -39 -Connector_PinHeader_1.00mm -PinHeader_1x39_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x39, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x39 1.00mm single row style2 pin1 right -0 -39 -39 -Connector_PinHeader_1.00mm -PinHeader_1x40_P1.00mm_Horizontal -Through hole angled pin header, 1x40, 1.00mm pitch, 2.0mm pin length, single row -Through hole angled pin header THT 1x40 1.00mm single row -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_1x40_P1.00mm_Vertical -Through hole straight pin header, 1x40, 1.00mm pitch, single row -Through hole pin header THT 1x40 1.00mm single row -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_1x40_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x40, 1.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x40 1.00mm single row style1 pin1 left -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_1x40_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x40, 1.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x40 1.00mm single row style2 pin1 right -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_2x01_P1.00mm_Horizontal -Through hole angled pin header, 2x01, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x01 1.00mm double row -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_2x01_P1.00mm_Vertical -Through hole straight pin header, 2x01, 1.00mm pitch, double rows -Through hole pin header THT 2x01 1.00mm double row -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_2x01_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x01, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x01 1.00mm double row -0 -2 -2 -Connector_PinHeader_1.00mm -PinHeader_2x02_P1.00mm_Horizontal -Through hole angled pin header, 2x02, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x02 1.00mm double row -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_2x02_P1.00mm_Vertical -Through hole straight pin header, 2x02, 1.00mm pitch, double rows -Through hole pin header THT 2x02 1.00mm double row -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_2x02_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x02, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x02 1.00mm double row -0 -4 -4 -Connector_PinHeader_1.00mm -PinHeader_2x03_P1.00mm_Horizontal -Through hole angled pin header, 2x03, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x03 1.00mm double row -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_2x03_P1.00mm_Vertical -Through hole straight pin header, 2x03, 1.00mm pitch, double rows -Through hole pin header THT 2x03 1.00mm double row -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_2x03_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x03, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x03 1.00mm double row -0 -6 -6 -Connector_PinHeader_1.00mm -PinHeader_2x04_P1.00mm_Horizontal -Through hole angled pin header, 2x04, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x04 1.00mm double row -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_2x04_P1.00mm_Vertical -Through hole straight pin header, 2x04, 1.00mm pitch, double rows -Through hole pin header THT 2x04 1.00mm double row -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_2x04_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x04, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x04 1.00mm double row -0 -8 -8 -Connector_PinHeader_1.00mm -PinHeader_2x05_P1.00mm_Horizontal -Through hole angled pin header, 2x05, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x05 1.00mm double row -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_2x05_P1.00mm_Vertical -Through hole straight pin header, 2x05, 1.00mm pitch, double rows -Through hole pin header THT 2x05 1.00mm double row -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_2x05_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x05, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x05 1.00mm double row -0 -10 -10 -Connector_PinHeader_1.00mm -PinHeader_2x06_P1.00mm_Horizontal -Through hole angled pin header, 2x06, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x06 1.00mm double row -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_2x06_P1.00mm_Vertical -Through hole straight pin header, 2x06, 1.00mm pitch, double rows -Through hole pin header THT 2x06 1.00mm double row -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_2x06_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x06, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x06 1.00mm double row -0 -12 -12 -Connector_PinHeader_1.00mm -PinHeader_2x07_P1.00mm_Horizontal -Through hole angled pin header, 2x07, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x07 1.00mm double row -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_2x07_P1.00mm_Vertical -Through hole straight pin header, 2x07, 1.00mm pitch, double rows -Through hole pin header THT 2x07 1.00mm double row -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_2x07_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x07, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x07 1.00mm double row -0 -14 -14 -Connector_PinHeader_1.00mm -PinHeader_2x08_P1.00mm_Horizontal -Through hole angled pin header, 2x08, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x08 1.00mm double row -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_2x08_P1.00mm_Vertical -Through hole straight pin header, 2x08, 1.00mm pitch, double rows -Through hole pin header THT 2x08 1.00mm double row -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_2x08_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x08, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x08 1.00mm double row -0 -16 -16 -Connector_PinHeader_1.00mm -PinHeader_2x09_P1.00mm_Horizontal -Through hole angled pin header, 2x09, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x09 1.00mm double row -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_2x09_P1.00mm_Vertical -Through hole straight pin header, 2x09, 1.00mm pitch, double rows -Through hole pin header THT 2x09 1.00mm double row -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_2x09_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x09, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x09 1.00mm double row -0 -18 -18 -Connector_PinHeader_1.00mm -PinHeader_2x10_P1.00mm_Horizontal -Through hole angled pin header, 2x10, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x10 1.00mm double row -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_2x10_P1.00mm_Vertical -Through hole straight pin header, 2x10, 1.00mm pitch, double rows -Through hole pin header THT 2x10 1.00mm double row -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_2x10_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x10, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x10 1.00mm double row -0 -20 -20 -Connector_PinHeader_1.00mm -PinHeader_2x11_P1.00mm_Horizontal -Through hole angled pin header, 2x11, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x11 1.00mm double row -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_2x11_P1.00mm_Vertical -Through hole straight pin header, 2x11, 1.00mm pitch, double rows -Through hole pin header THT 2x11 1.00mm double row -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_2x11_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x11, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x11 1.00mm double row -0 -22 -22 -Connector_PinHeader_1.00mm -PinHeader_2x12_P1.00mm_Horizontal -Through hole angled pin header, 2x12, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x12 1.00mm double row -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_2x12_P1.00mm_Vertical -Through hole straight pin header, 2x12, 1.00mm pitch, double rows -Through hole pin header THT 2x12 1.00mm double row -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_2x12_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x12, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x12 1.00mm double row -0 -24 -24 -Connector_PinHeader_1.00mm -PinHeader_2x13_P1.00mm_Horizontal -Through hole angled pin header, 2x13, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x13 1.00mm double row -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_2x13_P1.00mm_Vertical -Through hole straight pin header, 2x13, 1.00mm pitch, double rows -Through hole pin header THT 2x13 1.00mm double row -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_2x13_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x13, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x13 1.00mm double row -0 -26 -26 -Connector_PinHeader_1.00mm -PinHeader_2x14_P1.00mm_Horizontal -Through hole angled pin header, 2x14, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x14 1.00mm double row -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_2x14_P1.00mm_Vertical -Through hole straight pin header, 2x14, 1.00mm pitch, double rows -Through hole pin header THT 2x14 1.00mm double row -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_2x14_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x14, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x14 1.00mm double row -0 -28 -28 -Connector_PinHeader_1.00mm -PinHeader_2x15_P1.00mm_Horizontal -Through hole angled pin header, 2x15, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x15 1.00mm double row -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_2x15_P1.00mm_Vertical -Through hole straight pin header, 2x15, 1.00mm pitch, double rows -Through hole pin header THT 2x15 1.00mm double row -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_2x15_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x15, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x15 1.00mm double row -0 -30 -30 -Connector_PinHeader_1.00mm -PinHeader_2x16_P1.00mm_Horizontal -Through hole angled pin header, 2x16, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x16 1.00mm double row -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_2x16_P1.00mm_Vertical -Through hole straight pin header, 2x16, 1.00mm pitch, double rows -Through hole pin header THT 2x16 1.00mm double row -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_2x16_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x16, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x16 1.00mm double row -0 -32 -32 -Connector_PinHeader_1.00mm -PinHeader_2x17_P1.00mm_Horizontal -Through hole angled pin header, 2x17, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x17 1.00mm double row -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_2x17_P1.00mm_Vertical -Through hole straight pin header, 2x17, 1.00mm pitch, double rows -Through hole pin header THT 2x17 1.00mm double row -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_2x17_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x17, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x17 1.00mm double row -0 -34 -34 -Connector_PinHeader_1.00mm -PinHeader_2x18_P1.00mm_Horizontal -Through hole angled pin header, 2x18, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x18 1.00mm double row -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_2x18_P1.00mm_Vertical -Through hole straight pin header, 2x18, 1.00mm pitch, double rows -Through hole pin header THT 2x18 1.00mm double row -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_2x18_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x18, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x18 1.00mm double row -0 -36 -36 -Connector_PinHeader_1.00mm -PinHeader_2x19_P1.00mm_Horizontal -Through hole angled pin header, 2x19, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x19 1.00mm double row -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_2x19_P1.00mm_Vertical -Through hole straight pin header, 2x19, 1.00mm pitch, double rows -Through hole pin header THT 2x19 1.00mm double row -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_2x19_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x19, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x19 1.00mm double row -0 -38 -38 -Connector_PinHeader_1.00mm -PinHeader_2x20_P1.00mm_Horizontal -Through hole angled pin header, 2x20, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x20 1.00mm double row -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_2x20_P1.00mm_Vertical -Through hole straight pin header, 2x20, 1.00mm pitch, double rows -Through hole pin header THT 2x20 1.00mm double row -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_2x20_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x20, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x20 1.00mm double row -0 -40 -40 -Connector_PinHeader_1.00mm -PinHeader_2x21_P1.00mm_Horizontal -Through hole angled pin header, 2x21, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x21 1.00mm double row -0 -42 -42 -Connector_PinHeader_1.00mm -PinHeader_2x21_P1.00mm_Vertical -Through hole straight pin header, 2x21, 1.00mm pitch, double rows -Through hole pin header THT 2x21 1.00mm double row -0 -42 -42 -Connector_PinHeader_1.00mm -PinHeader_2x21_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x21, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x21 1.00mm double row -0 -42 -42 -Connector_PinHeader_1.00mm -PinHeader_2x22_P1.00mm_Horizontal -Through hole angled pin header, 2x22, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x22 1.00mm double row -0 -44 -44 -Connector_PinHeader_1.00mm -PinHeader_2x22_P1.00mm_Vertical -Through hole straight pin header, 2x22, 1.00mm pitch, double rows -Through hole pin header THT 2x22 1.00mm double row -0 -44 -44 -Connector_PinHeader_1.00mm -PinHeader_2x22_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x22, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x22 1.00mm double row -0 -44 -44 -Connector_PinHeader_1.00mm -PinHeader_2x23_P1.00mm_Horizontal -Through hole angled pin header, 2x23, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x23 1.00mm double row -0 -46 -46 -Connector_PinHeader_1.00mm -PinHeader_2x23_P1.00mm_Vertical -Through hole straight pin header, 2x23, 1.00mm pitch, double rows -Through hole pin header THT 2x23 1.00mm double row -0 -46 -46 -Connector_PinHeader_1.00mm -PinHeader_2x23_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x23, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x23 1.00mm double row -0 -46 -46 -Connector_PinHeader_1.00mm -PinHeader_2x24_P1.00mm_Horizontal -Through hole angled pin header, 2x24, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x24 1.00mm double row -0 -48 -48 -Connector_PinHeader_1.00mm -PinHeader_2x24_P1.00mm_Vertical -Through hole straight pin header, 2x24, 1.00mm pitch, double rows -Through hole pin header THT 2x24 1.00mm double row -0 -48 -48 -Connector_PinHeader_1.00mm -PinHeader_2x24_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x24, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x24 1.00mm double row -0 -48 -48 -Connector_PinHeader_1.00mm -PinHeader_2x25_P1.00mm_Horizontal -Through hole angled pin header, 2x25, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x25 1.00mm double row -0 -50 -50 -Connector_PinHeader_1.00mm -PinHeader_2x25_P1.00mm_Vertical -Through hole straight pin header, 2x25, 1.00mm pitch, double rows -Through hole pin header THT 2x25 1.00mm double row -0 -50 -50 -Connector_PinHeader_1.00mm -PinHeader_2x25_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x25, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x25 1.00mm double row -0 -50 -50 -Connector_PinHeader_1.00mm -PinHeader_2x26_P1.00mm_Horizontal -Through hole angled pin header, 2x26, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x26 1.00mm double row -0 -52 -52 -Connector_PinHeader_1.00mm -PinHeader_2x26_P1.00mm_Vertical -Through hole straight pin header, 2x26, 1.00mm pitch, double rows -Through hole pin header THT 2x26 1.00mm double row -0 -52 -52 -Connector_PinHeader_1.00mm -PinHeader_2x26_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x26, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x26 1.00mm double row -0 -52 -52 -Connector_PinHeader_1.00mm -PinHeader_2x27_P1.00mm_Horizontal -Through hole angled pin header, 2x27, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x27 1.00mm double row -0 -54 -54 -Connector_PinHeader_1.00mm -PinHeader_2x27_P1.00mm_Vertical -Through hole straight pin header, 2x27, 1.00mm pitch, double rows -Through hole pin header THT 2x27 1.00mm double row -0 -54 -54 -Connector_PinHeader_1.00mm -PinHeader_2x27_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x27, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x27 1.00mm double row -0 -54 -54 -Connector_PinHeader_1.00mm -PinHeader_2x28_P1.00mm_Horizontal -Through hole angled pin header, 2x28, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x28 1.00mm double row -0 -56 -56 -Connector_PinHeader_1.00mm -PinHeader_2x28_P1.00mm_Vertical -Through hole straight pin header, 2x28, 1.00mm pitch, double rows -Through hole pin header THT 2x28 1.00mm double row -0 -56 -56 -Connector_PinHeader_1.00mm -PinHeader_2x28_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x28, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x28 1.00mm double row -0 -56 -56 -Connector_PinHeader_1.00mm -PinHeader_2x29_P1.00mm_Horizontal -Through hole angled pin header, 2x29, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x29 1.00mm double row -0 -58 -58 -Connector_PinHeader_1.00mm -PinHeader_2x29_P1.00mm_Vertical -Through hole straight pin header, 2x29, 1.00mm pitch, double rows -Through hole pin header THT 2x29 1.00mm double row -0 -58 -58 -Connector_PinHeader_1.00mm -PinHeader_2x29_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x29, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x29 1.00mm double row -0 -58 -58 -Connector_PinHeader_1.00mm -PinHeader_2x30_P1.00mm_Horizontal -Through hole angled pin header, 2x30, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x30 1.00mm double row -0 -60 -60 -Connector_PinHeader_1.00mm -PinHeader_2x30_P1.00mm_Vertical -Through hole straight pin header, 2x30, 1.00mm pitch, double rows -Through hole pin header THT 2x30 1.00mm double row -0 -60 -60 -Connector_PinHeader_1.00mm -PinHeader_2x30_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x30, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x30 1.00mm double row -0 -60 -60 -Connector_PinHeader_1.00mm -PinHeader_2x31_P1.00mm_Horizontal -Through hole angled pin header, 2x31, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x31 1.00mm double row -0 -62 -62 -Connector_PinHeader_1.00mm -PinHeader_2x31_P1.00mm_Vertical -Through hole straight pin header, 2x31, 1.00mm pitch, double rows -Through hole pin header THT 2x31 1.00mm double row -0 -62 -62 -Connector_PinHeader_1.00mm -PinHeader_2x31_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x31, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x31 1.00mm double row -0 -62 -62 -Connector_PinHeader_1.00mm -PinHeader_2x32_P1.00mm_Horizontal -Through hole angled pin header, 2x32, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x32 1.00mm double row -0 -64 -64 -Connector_PinHeader_1.00mm -PinHeader_2x32_P1.00mm_Vertical -Through hole straight pin header, 2x32, 1.00mm pitch, double rows -Through hole pin header THT 2x32 1.00mm double row -0 -64 -64 -Connector_PinHeader_1.00mm -PinHeader_2x32_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x32, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x32 1.00mm double row -0 -64 -64 -Connector_PinHeader_1.00mm -PinHeader_2x33_P1.00mm_Horizontal -Through hole angled pin header, 2x33, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x33 1.00mm double row -0 -66 -66 -Connector_PinHeader_1.00mm -PinHeader_2x33_P1.00mm_Vertical -Through hole straight pin header, 2x33, 1.00mm pitch, double rows -Through hole pin header THT 2x33 1.00mm double row -0 -66 -66 -Connector_PinHeader_1.00mm -PinHeader_2x33_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x33, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x33 1.00mm double row -0 -66 -66 -Connector_PinHeader_1.00mm -PinHeader_2x34_P1.00mm_Horizontal -Through hole angled pin header, 2x34, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x34 1.00mm double row -0 -68 -68 -Connector_PinHeader_1.00mm -PinHeader_2x34_P1.00mm_Vertical -Through hole straight pin header, 2x34, 1.00mm pitch, double rows -Through hole pin header THT 2x34 1.00mm double row -0 -68 -68 -Connector_PinHeader_1.00mm -PinHeader_2x34_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x34, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x34 1.00mm double row -0 -68 -68 -Connector_PinHeader_1.00mm -PinHeader_2x35_P1.00mm_Horizontal -Through hole angled pin header, 2x35, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x35 1.00mm double row -0 -70 -70 -Connector_PinHeader_1.00mm -PinHeader_2x35_P1.00mm_Vertical -Through hole straight pin header, 2x35, 1.00mm pitch, double rows -Through hole pin header THT 2x35 1.00mm double row -0 -70 -70 -Connector_PinHeader_1.00mm -PinHeader_2x35_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x35, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x35 1.00mm double row -0 -70 -70 -Connector_PinHeader_1.00mm -PinHeader_2x36_P1.00mm_Horizontal -Through hole angled pin header, 2x36, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x36 1.00mm double row -0 -72 -72 -Connector_PinHeader_1.00mm -PinHeader_2x36_P1.00mm_Vertical -Through hole straight pin header, 2x36, 1.00mm pitch, double rows -Through hole pin header THT 2x36 1.00mm double row -0 -72 -72 -Connector_PinHeader_1.00mm -PinHeader_2x36_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x36, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x36 1.00mm double row -0 -72 -72 -Connector_PinHeader_1.00mm -PinHeader_2x37_P1.00mm_Horizontal -Through hole angled pin header, 2x37, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x37 1.00mm double row -0 -74 -74 -Connector_PinHeader_1.00mm -PinHeader_2x37_P1.00mm_Vertical -Through hole straight pin header, 2x37, 1.00mm pitch, double rows -Through hole pin header THT 2x37 1.00mm double row -0 -74 -74 -Connector_PinHeader_1.00mm -PinHeader_2x37_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x37, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x37 1.00mm double row -0 -74 -74 -Connector_PinHeader_1.00mm -PinHeader_2x38_P1.00mm_Horizontal -Through hole angled pin header, 2x38, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x38 1.00mm double row -0 -76 -76 -Connector_PinHeader_1.00mm -PinHeader_2x38_P1.00mm_Vertical -Through hole straight pin header, 2x38, 1.00mm pitch, double rows -Through hole pin header THT 2x38 1.00mm double row -0 -76 -76 -Connector_PinHeader_1.00mm -PinHeader_2x38_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x38, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x38 1.00mm double row -0 -76 -76 -Connector_PinHeader_1.00mm -PinHeader_2x39_P1.00mm_Horizontal -Through hole angled pin header, 2x39, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x39 1.00mm double row -0 -78 -78 -Connector_PinHeader_1.00mm -PinHeader_2x39_P1.00mm_Vertical -Through hole straight pin header, 2x39, 1.00mm pitch, double rows -Through hole pin header THT 2x39 1.00mm double row -0 -78 -78 -Connector_PinHeader_1.00mm -PinHeader_2x39_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x39, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x39 1.00mm double row -0 -78 -78 -Connector_PinHeader_1.00mm -PinHeader_2x40_P1.00mm_Horizontal -Through hole angled pin header, 2x40, 1.00mm pitch, 2.0mm pin length, double rows -Through hole angled pin header THT 2x40 1.00mm double row -0 -80 -80 -Connector_PinHeader_1.00mm -PinHeader_2x40_P1.00mm_Vertical -Through hole straight pin header, 2x40, 1.00mm pitch, double rows -Through hole pin header THT 2x40 1.00mm double row -0 -80 -80 -Connector_PinHeader_1.00mm -PinHeader_2x40_P1.00mm_Vertical_SMD -surface-mounted straight pin header, 2x40, 1.00mm pitch, double rows -Surface mounted pin header SMD 2x40 1.00mm double row -0 -80 -80 -Connector_PinHeader_1.27mm -PinHeader_1x01_P1.27mm_Horizontal -Through hole angled pin header, 1x01, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x01 1.27mm single row -0 -1 -1 -Connector_PinHeader_1.27mm -PinHeader_1x01_P1.27mm_Vertical -Through hole straight pin header, 1x01, 1.27mm pitch, single row -Through hole pin header THT 1x01 1.27mm single row -0 -1 -1 -Connector_PinHeader_1.27mm -PinHeader_1x02_P1.27mm_Horizontal -Through hole angled pin header, 1x02, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x02 1.27mm single row -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_1x02_P1.27mm_Vertical -Through hole straight pin header, 1x02, 1.27mm pitch, single row -Through hole pin header THT 1x02 1.27mm single row -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_1x02_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x02, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x02 1.27mm single row style1 pin1 left -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_1x02_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x02, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x02 1.27mm single row style2 pin1 right -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_1x03_P1.27mm_Horizontal -Through hole angled pin header, 1x03, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x03 1.27mm single row -0 -3 -3 -Connector_PinHeader_1.27mm -PinHeader_1x03_P1.27mm_Vertical -Through hole straight pin header, 1x03, 1.27mm pitch, single row -Through hole pin header THT 1x03 1.27mm single row -0 -3 -3 -Connector_PinHeader_1.27mm -PinHeader_1x03_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x03, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x03 1.27mm single row style1 pin1 left -0 -3 -3 -Connector_PinHeader_1.27mm -PinHeader_1x03_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x03, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x03 1.27mm single row style2 pin1 right -0 -3 -3 -Connector_PinHeader_1.27mm -PinHeader_1x04_P1.27mm_Horizontal -Through hole angled pin header, 1x04, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x04 1.27mm single row -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_1x04_P1.27mm_Vertical -Through hole straight pin header, 1x04, 1.27mm pitch, single row -Through hole pin header THT 1x04 1.27mm single row -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_1x04_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x04, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x04 1.27mm single row style1 pin1 left -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_1x04_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x04, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x04 1.27mm single row style2 pin1 right -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_1x05_P1.27mm_Horizontal -Through hole angled pin header, 1x05, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x05 1.27mm single row -0 -5 -5 -Connector_PinHeader_1.27mm -PinHeader_1x05_P1.27mm_Vertical -Through hole straight pin header, 1x05, 1.27mm pitch, single row -Through hole pin header THT 1x05 1.27mm single row -0 -5 -5 -Connector_PinHeader_1.27mm -PinHeader_1x05_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x05, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x05 1.27mm single row style1 pin1 left -0 -5 -5 -Connector_PinHeader_1.27mm -PinHeader_1x05_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x05, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x05 1.27mm single row style2 pin1 right -0 -5 -5 -Connector_PinHeader_1.27mm -PinHeader_1x06_P1.27mm_Horizontal -Through hole angled pin header, 1x06, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x06 1.27mm single row -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_1x06_P1.27mm_Vertical -Through hole straight pin header, 1x06, 1.27mm pitch, single row -Through hole pin header THT 1x06 1.27mm single row -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_1x06_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x06, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x06 1.27mm single row style1 pin1 left -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_1x06_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x06, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x06 1.27mm single row style2 pin1 right -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_1x07_P1.27mm_Horizontal -Through hole angled pin header, 1x07, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x07 1.27mm single row -0 -7 -7 -Connector_PinHeader_1.27mm -PinHeader_1x07_P1.27mm_Vertical -Through hole straight pin header, 1x07, 1.27mm pitch, single row -Through hole pin header THT 1x07 1.27mm single row -0 -7 -7 -Connector_PinHeader_1.27mm -PinHeader_1x07_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x07, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x07 1.27mm single row style1 pin1 left -0 -7 -7 -Connector_PinHeader_1.27mm -PinHeader_1x07_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x07, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x07 1.27mm single row style2 pin1 right -0 -7 -7 -Connector_PinHeader_1.27mm -PinHeader_1x08_P1.27mm_Horizontal -Through hole angled pin header, 1x08, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x08 1.27mm single row -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_1x08_P1.27mm_Vertical -Through hole straight pin header, 1x08, 1.27mm pitch, single row -Through hole pin header THT 1x08 1.27mm single row -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_1x08_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x08, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x08 1.27mm single row style1 pin1 left -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_1x08_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x08, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x08 1.27mm single row style2 pin1 right -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_1x09_P1.27mm_Horizontal -Through hole angled pin header, 1x09, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x09 1.27mm single row -0 -9 -9 -Connector_PinHeader_1.27mm -PinHeader_1x09_P1.27mm_Vertical -Through hole straight pin header, 1x09, 1.27mm pitch, single row -Through hole pin header THT 1x09 1.27mm single row -0 -9 -9 -Connector_PinHeader_1.27mm -PinHeader_1x09_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x09, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x09 1.27mm single row style1 pin1 left -0 -9 -9 -Connector_PinHeader_1.27mm -PinHeader_1x09_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x09, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x09 1.27mm single row style2 pin1 right -0 -9 -9 -Connector_PinHeader_1.27mm -PinHeader_1x10_P1.27mm_Horizontal -Through hole angled pin header, 1x10, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x10 1.27mm single row -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_1x10_P1.27mm_Vertical -Through hole straight pin header, 1x10, 1.27mm pitch, single row -Through hole pin header THT 1x10 1.27mm single row -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_1x10_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x10, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x10 1.27mm single row style1 pin1 left -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_1x10_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x10, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x10 1.27mm single row style2 pin1 right -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_1x11_P1.27mm_Horizontal -Through hole angled pin header, 1x11, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x11 1.27mm single row -0 -11 -11 -Connector_PinHeader_1.27mm -PinHeader_1x11_P1.27mm_Vertical -Through hole straight pin header, 1x11, 1.27mm pitch, single row -Through hole pin header THT 1x11 1.27mm single row -0 -11 -11 -Connector_PinHeader_1.27mm -PinHeader_1x11_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x11, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x11 1.27mm single row style1 pin1 left -0 -11 -11 -Connector_PinHeader_1.27mm -PinHeader_1x11_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x11, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x11 1.27mm single row style2 pin1 right -0 -11 -11 -Connector_PinHeader_1.27mm -PinHeader_1x12_P1.27mm_Horizontal -Through hole angled pin header, 1x12, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x12 1.27mm single row -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_1x12_P1.27mm_Vertical -Through hole straight pin header, 1x12, 1.27mm pitch, single row -Through hole pin header THT 1x12 1.27mm single row -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_1x12_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x12, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x12 1.27mm single row style1 pin1 left -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_1x12_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x12, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x12 1.27mm single row style2 pin1 right -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_1x13_P1.27mm_Horizontal -Through hole angled pin header, 1x13, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x13 1.27mm single row -0 -13 -13 -Connector_PinHeader_1.27mm -PinHeader_1x13_P1.27mm_Vertical -Through hole straight pin header, 1x13, 1.27mm pitch, single row -Through hole pin header THT 1x13 1.27mm single row -0 -13 -13 -Connector_PinHeader_1.27mm -PinHeader_1x13_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x13, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x13 1.27mm single row style1 pin1 left -0 -13 -13 -Connector_PinHeader_1.27mm -PinHeader_1x13_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x13, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x13 1.27mm single row style2 pin1 right -0 -13 -13 -Connector_PinHeader_1.27mm -PinHeader_1x14_P1.27mm_Horizontal -Through hole angled pin header, 1x14, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x14 1.27mm single row -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_1x14_P1.27mm_Vertical -Through hole straight pin header, 1x14, 1.27mm pitch, single row -Through hole pin header THT 1x14 1.27mm single row -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_1x14_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x14, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x14 1.27mm single row style1 pin1 left -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_1x14_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x14, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x14 1.27mm single row style2 pin1 right -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_1x15_P1.27mm_Horizontal -Through hole angled pin header, 1x15, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x15 1.27mm single row -0 -15 -15 -Connector_PinHeader_1.27mm -PinHeader_1x15_P1.27mm_Vertical -Through hole straight pin header, 1x15, 1.27mm pitch, single row -Through hole pin header THT 1x15 1.27mm single row -0 -15 -15 -Connector_PinHeader_1.27mm -PinHeader_1x15_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x15, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x15 1.27mm single row style1 pin1 left -0 -15 -15 -Connector_PinHeader_1.27mm -PinHeader_1x15_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x15, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x15 1.27mm single row style2 pin1 right -0 -15 -15 -Connector_PinHeader_1.27mm -PinHeader_1x16_P1.27mm_Horizontal -Through hole angled pin header, 1x16, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x16 1.27mm single row -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_1x16_P1.27mm_Vertical -Through hole straight pin header, 1x16, 1.27mm pitch, single row -Through hole pin header THT 1x16 1.27mm single row -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_1x16_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x16, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x16 1.27mm single row style1 pin1 left -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_1x16_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x16, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x16 1.27mm single row style2 pin1 right -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_1x17_P1.27mm_Horizontal -Through hole angled pin header, 1x17, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x17 1.27mm single row -0 -17 -17 -Connector_PinHeader_1.27mm -PinHeader_1x17_P1.27mm_Vertical -Through hole straight pin header, 1x17, 1.27mm pitch, single row -Through hole pin header THT 1x17 1.27mm single row -0 -17 -17 -Connector_PinHeader_1.27mm -PinHeader_1x17_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x17, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x17 1.27mm single row style1 pin1 left -0 -17 -17 -Connector_PinHeader_1.27mm -PinHeader_1x17_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x17, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x17 1.27mm single row style2 pin1 right -0 -17 -17 -Connector_PinHeader_1.27mm -PinHeader_1x18_P1.27mm_Horizontal -Through hole angled pin header, 1x18, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x18 1.27mm single row -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_1x18_P1.27mm_Vertical -Through hole straight pin header, 1x18, 1.27mm pitch, single row -Through hole pin header THT 1x18 1.27mm single row -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_1x18_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x18, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x18 1.27mm single row style1 pin1 left -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_1x18_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x18, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x18 1.27mm single row style2 pin1 right -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_1x19_P1.27mm_Horizontal -Through hole angled pin header, 1x19, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x19 1.27mm single row -0 -19 -19 -Connector_PinHeader_1.27mm -PinHeader_1x19_P1.27mm_Vertical -Through hole straight pin header, 1x19, 1.27mm pitch, single row -Through hole pin header THT 1x19 1.27mm single row -0 -19 -19 -Connector_PinHeader_1.27mm -PinHeader_1x19_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x19, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x19 1.27mm single row style1 pin1 left -0 -19 -19 -Connector_PinHeader_1.27mm -PinHeader_1x19_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x19, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x19 1.27mm single row style2 pin1 right -0 -19 -19 -Connector_PinHeader_1.27mm -PinHeader_1x20_P1.27mm_Horizontal -Through hole angled pin header, 1x20, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x20 1.27mm single row -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_1x20_P1.27mm_Vertical -Through hole straight pin header, 1x20, 1.27mm pitch, single row -Through hole pin header THT 1x20 1.27mm single row -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_1x20_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x20, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x20 1.27mm single row style1 pin1 left -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_1x20_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x20, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x20 1.27mm single row style2 pin1 right -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_1x21_P1.27mm_Horizontal -Through hole angled pin header, 1x21, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x21 1.27mm single row -0 -21 -21 -Connector_PinHeader_1.27mm -PinHeader_1x21_P1.27mm_Vertical -Through hole straight pin header, 1x21, 1.27mm pitch, single row -Through hole pin header THT 1x21 1.27mm single row -0 -21 -21 -Connector_PinHeader_1.27mm -PinHeader_1x21_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x21, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x21 1.27mm single row style1 pin1 left -0 -21 -21 -Connector_PinHeader_1.27mm -PinHeader_1x21_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x21, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x21 1.27mm single row style2 pin1 right -0 -21 -21 -Connector_PinHeader_1.27mm -PinHeader_1x22_P1.27mm_Horizontal -Through hole angled pin header, 1x22, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x22 1.27mm single row -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_1x22_P1.27mm_Vertical -Through hole straight pin header, 1x22, 1.27mm pitch, single row -Through hole pin header THT 1x22 1.27mm single row -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_1x22_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x22, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x22 1.27mm single row style1 pin1 left -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_1x22_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x22, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x22 1.27mm single row style2 pin1 right -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_1x23_P1.27mm_Horizontal -Through hole angled pin header, 1x23, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x23 1.27mm single row -0 -23 -23 -Connector_PinHeader_1.27mm -PinHeader_1x23_P1.27mm_Vertical -Through hole straight pin header, 1x23, 1.27mm pitch, single row -Through hole pin header THT 1x23 1.27mm single row -0 -23 -23 -Connector_PinHeader_1.27mm -PinHeader_1x23_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x23, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x23 1.27mm single row style1 pin1 left -0 -23 -23 -Connector_PinHeader_1.27mm -PinHeader_1x23_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x23, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x23 1.27mm single row style2 pin1 right -0 -23 -23 -Connector_PinHeader_1.27mm -PinHeader_1x24_P1.27mm_Horizontal -Through hole angled pin header, 1x24, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x24 1.27mm single row -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_1x24_P1.27mm_Vertical -Through hole straight pin header, 1x24, 1.27mm pitch, single row -Through hole pin header THT 1x24 1.27mm single row -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_1x24_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x24, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x24 1.27mm single row style1 pin1 left -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_1x24_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x24, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x24 1.27mm single row style2 pin1 right -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_1x25_P1.27mm_Horizontal -Through hole angled pin header, 1x25, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x25 1.27mm single row -0 -25 -25 -Connector_PinHeader_1.27mm -PinHeader_1x25_P1.27mm_Vertical -Through hole straight pin header, 1x25, 1.27mm pitch, single row -Through hole pin header THT 1x25 1.27mm single row -0 -25 -25 -Connector_PinHeader_1.27mm -PinHeader_1x25_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x25, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x25 1.27mm single row style1 pin1 left -0 -25 -25 -Connector_PinHeader_1.27mm -PinHeader_1x25_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x25, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x25 1.27mm single row style2 pin1 right -0 -25 -25 -Connector_PinHeader_1.27mm -PinHeader_1x26_P1.27mm_Horizontal -Through hole angled pin header, 1x26, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x26 1.27mm single row -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_1x26_P1.27mm_Vertical -Through hole straight pin header, 1x26, 1.27mm pitch, single row -Through hole pin header THT 1x26 1.27mm single row -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_1x26_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x26, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x26 1.27mm single row style1 pin1 left -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_1x26_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x26, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x26 1.27mm single row style2 pin1 right -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_1x27_P1.27mm_Horizontal -Through hole angled pin header, 1x27, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x27 1.27mm single row -0 -27 -27 -Connector_PinHeader_1.27mm -PinHeader_1x27_P1.27mm_Vertical -Through hole straight pin header, 1x27, 1.27mm pitch, single row -Through hole pin header THT 1x27 1.27mm single row -0 -27 -27 -Connector_PinHeader_1.27mm -PinHeader_1x27_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x27, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x27 1.27mm single row style1 pin1 left -0 -27 -27 -Connector_PinHeader_1.27mm -PinHeader_1x27_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x27, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x27 1.27mm single row style2 pin1 right -0 -27 -27 -Connector_PinHeader_1.27mm -PinHeader_1x28_P1.27mm_Horizontal -Through hole angled pin header, 1x28, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x28 1.27mm single row -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_1x28_P1.27mm_Vertical -Through hole straight pin header, 1x28, 1.27mm pitch, single row -Through hole pin header THT 1x28 1.27mm single row -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_1x28_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x28, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x28 1.27mm single row style1 pin1 left -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_1x28_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x28, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x28 1.27mm single row style2 pin1 right -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_1x29_P1.27mm_Horizontal -Through hole angled pin header, 1x29, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x29 1.27mm single row -0 -29 -29 -Connector_PinHeader_1.27mm -PinHeader_1x29_P1.27mm_Vertical -Through hole straight pin header, 1x29, 1.27mm pitch, single row -Through hole pin header THT 1x29 1.27mm single row -0 -29 -29 -Connector_PinHeader_1.27mm -PinHeader_1x29_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x29, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x29 1.27mm single row style1 pin1 left -0 -29 -29 -Connector_PinHeader_1.27mm -PinHeader_1x29_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x29, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x29 1.27mm single row style2 pin1 right -0 -29 -29 -Connector_PinHeader_1.27mm -PinHeader_1x30_P1.27mm_Horizontal -Through hole angled pin header, 1x30, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x30 1.27mm single row -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_1x30_P1.27mm_Vertical -Through hole straight pin header, 1x30, 1.27mm pitch, single row -Through hole pin header THT 1x30 1.27mm single row -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_1x30_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x30, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x30 1.27mm single row style1 pin1 left -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_1x30_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x30, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x30 1.27mm single row style2 pin1 right -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_1x31_P1.27mm_Horizontal -Through hole angled pin header, 1x31, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x31 1.27mm single row -0 -31 -31 -Connector_PinHeader_1.27mm -PinHeader_1x31_P1.27mm_Vertical -Through hole straight pin header, 1x31, 1.27mm pitch, single row -Through hole pin header THT 1x31 1.27mm single row -0 -31 -31 -Connector_PinHeader_1.27mm -PinHeader_1x31_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x31, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x31 1.27mm single row style1 pin1 left -0 -31 -31 -Connector_PinHeader_1.27mm -PinHeader_1x31_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x31, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x31 1.27mm single row style2 pin1 right -0 -31 -31 -Connector_PinHeader_1.27mm -PinHeader_1x32_P1.27mm_Horizontal -Through hole angled pin header, 1x32, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x32 1.27mm single row -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_1x32_P1.27mm_Vertical -Through hole straight pin header, 1x32, 1.27mm pitch, single row -Through hole pin header THT 1x32 1.27mm single row -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_1x32_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x32, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x32 1.27mm single row style1 pin1 left -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_1x32_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x32, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x32 1.27mm single row style2 pin1 right -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_1x33_P1.27mm_Horizontal -Through hole angled pin header, 1x33, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x33 1.27mm single row -0 -33 -33 -Connector_PinHeader_1.27mm -PinHeader_1x33_P1.27mm_Vertical -Through hole straight pin header, 1x33, 1.27mm pitch, single row -Through hole pin header THT 1x33 1.27mm single row -0 -33 -33 -Connector_PinHeader_1.27mm -PinHeader_1x33_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x33, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x33 1.27mm single row style1 pin1 left -0 -33 -33 -Connector_PinHeader_1.27mm -PinHeader_1x33_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x33, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x33 1.27mm single row style2 pin1 right -0 -33 -33 -Connector_PinHeader_1.27mm -PinHeader_1x34_P1.27mm_Horizontal -Through hole angled pin header, 1x34, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x34 1.27mm single row -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_1x34_P1.27mm_Vertical -Through hole straight pin header, 1x34, 1.27mm pitch, single row -Through hole pin header THT 1x34 1.27mm single row -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_1x34_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x34, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x34 1.27mm single row style1 pin1 left -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_1x34_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x34, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x34 1.27mm single row style2 pin1 right -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_1x35_P1.27mm_Horizontal -Through hole angled pin header, 1x35, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x35 1.27mm single row -0 -35 -35 -Connector_PinHeader_1.27mm -PinHeader_1x35_P1.27mm_Vertical -Through hole straight pin header, 1x35, 1.27mm pitch, single row -Through hole pin header THT 1x35 1.27mm single row -0 -35 -35 -Connector_PinHeader_1.27mm -PinHeader_1x35_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x35, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x35 1.27mm single row style1 pin1 left -0 -35 -35 -Connector_PinHeader_1.27mm -PinHeader_1x35_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x35, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x35 1.27mm single row style2 pin1 right -0 -35 -35 -Connector_PinHeader_1.27mm -PinHeader_1x36_P1.27mm_Horizontal -Through hole angled pin header, 1x36, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x36 1.27mm single row -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_1x36_P1.27mm_Vertical -Through hole straight pin header, 1x36, 1.27mm pitch, single row -Through hole pin header THT 1x36 1.27mm single row -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_1x36_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x36, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x36 1.27mm single row style1 pin1 left -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_1x36_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x36, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x36 1.27mm single row style2 pin1 right -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_1x37_P1.27mm_Horizontal -Through hole angled pin header, 1x37, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x37 1.27mm single row -0 -37 -37 -Connector_PinHeader_1.27mm -PinHeader_1x37_P1.27mm_Vertical -Through hole straight pin header, 1x37, 1.27mm pitch, single row -Through hole pin header THT 1x37 1.27mm single row -0 -37 -37 -Connector_PinHeader_1.27mm -PinHeader_1x37_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x37, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x37 1.27mm single row style1 pin1 left -0 -37 -37 -Connector_PinHeader_1.27mm -PinHeader_1x37_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x37, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x37 1.27mm single row style2 pin1 right -0 -37 -37 -Connector_PinHeader_1.27mm -PinHeader_1x38_P1.27mm_Horizontal -Through hole angled pin header, 1x38, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x38 1.27mm single row -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_1x38_P1.27mm_Vertical -Through hole straight pin header, 1x38, 1.27mm pitch, single row -Through hole pin header THT 1x38 1.27mm single row -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_1x38_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x38, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x38 1.27mm single row style1 pin1 left -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_1x38_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x38, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x38 1.27mm single row style2 pin1 right -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_1x39_P1.27mm_Horizontal -Through hole angled pin header, 1x39, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x39 1.27mm single row -0 -39 -39 -Connector_PinHeader_1.27mm -PinHeader_1x39_P1.27mm_Vertical -Through hole straight pin header, 1x39, 1.27mm pitch, single row -Through hole pin header THT 1x39 1.27mm single row -0 -39 -39 -Connector_PinHeader_1.27mm -PinHeader_1x39_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x39, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x39 1.27mm single row style1 pin1 left -0 -39 -39 -Connector_PinHeader_1.27mm -PinHeader_1x39_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x39, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x39 1.27mm single row style2 pin1 right -0 -39 -39 -Connector_PinHeader_1.27mm -PinHeader_1x40_P1.27mm_Horizontal -Through hole angled pin header, 1x40, 1.27mm pitch, 4.0mm pin length, single row -Through hole angled pin header THT 1x40 1.27mm single row -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_1x40_P1.27mm_Vertical -Through hole straight pin header, 1x40, 1.27mm pitch, single row -Through hole pin header THT 1x40 1.27mm single row -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_1x40_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x40, 1.27mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x40 1.27mm single row style1 pin1 left -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_1x40_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x40, 1.27mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x40 1.27mm single row style2 pin1 right -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_2x01_P1.27mm_Horizontal -Through hole angled pin header, 2x01, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x01 1.27mm double row -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_2x01_P1.27mm_Vertical -Through hole straight pin header, 2x01, 1.27mm pitch, double rows -Through hole pin header THT 2x01 1.27mm double row -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_2x01_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x01, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x01 1.27mm double row -0 -2 -2 -Connector_PinHeader_1.27mm -PinHeader_2x02_P1.27mm_Horizontal -Through hole angled pin header, 2x02, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x02 1.27mm double row -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_2x02_P1.27mm_Vertical -Through hole straight pin header, 2x02, 1.27mm pitch, double rows -Through hole pin header THT 2x02 1.27mm double row -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_2x02_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x02, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x02 1.27mm double row -0 -4 -4 -Connector_PinHeader_1.27mm -PinHeader_2x03_P1.27mm_Horizontal -Through hole angled pin header, 2x03, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x03 1.27mm double row -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_2x03_P1.27mm_Vertical -Through hole straight pin header, 2x03, 1.27mm pitch, double rows -Through hole pin header THT 2x03 1.27mm double row -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_2x03_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x03, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x03 1.27mm double row -0 -6 -6 -Connector_PinHeader_1.27mm -PinHeader_2x04_P1.27mm_Horizontal -Through hole angled pin header, 2x04, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x04 1.27mm double row -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_2x04_P1.27mm_Vertical -Through hole straight pin header, 2x04, 1.27mm pitch, double rows -Through hole pin header THT 2x04 1.27mm double row -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_2x04_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x04, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x04 1.27mm double row -0 -8 -8 -Connector_PinHeader_1.27mm -PinHeader_2x05_P1.27mm_Horizontal -Through hole angled pin header, 2x05, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x05 1.27mm double row -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_2x05_P1.27mm_Vertical -Through hole straight pin header, 2x05, 1.27mm pitch, double rows -Through hole pin header THT 2x05 1.27mm double row -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_2x05_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x05, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x05 1.27mm double row -0 -10 -10 -Connector_PinHeader_1.27mm -PinHeader_2x06_P1.27mm_Horizontal -Through hole angled pin header, 2x06, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x06 1.27mm double row -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_2x06_P1.27mm_Vertical -Through hole straight pin header, 2x06, 1.27mm pitch, double rows -Through hole pin header THT 2x06 1.27mm double row -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_2x06_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x06, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x06 1.27mm double row -0 -12 -12 -Connector_PinHeader_1.27mm -PinHeader_2x07_P1.27mm_Horizontal -Through hole angled pin header, 2x07, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x07 1.27mm double row -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_2x07_P1.27mm_Vertical -Through hole straight pin header, 2x07, 1.27mm pitch, double rows -Through hole pin header THT 2x07 1.27mm double row -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_2x07_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x07, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x07 1.27mm double row -0 -14 -14 -Connector_PinHeader_1.27mm -PinHeader_2x08_P1.27mm_Horizontal -Through hole angled pin header, 2x08, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x08 1.27mm double row -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_2x08_P1.27mm_Vertical -Through hole straight pin header, 2x08, 1.27mm pitch, double rows -Through hole pin header THT 2x08 1.27mm double row -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_2x08_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x08, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x08 1.27mm double row -0 -16 -16 -Connector_PinHeader_1.27mm -PinHeader_2x09_P1.27mm_Horizontal -Through hole angled pin header, 2x09, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x09 1.27mm double row -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_2x09_P1.27mm_Vertical -Through hole straight pin header, 2x09, 1.27mm pitch, double rows -Through hole pin header THT 2x09 1.27mm double row -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_2x09_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x09, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x09 1.27mm double row -0 -18 -18 -Connector_PinHeader_1.27mm -PinHeader_2x10_P1.27mm_Horizontal -Through hole angled pin header, 2x10, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x10 1.27mm double row -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_2x10_P1.27mm_Vertical -Through hole straight pin header, 2x10, 1.27mm pitch, double rows -Through hole pin header THT 2x10 1.27mm double row -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_2x10_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x10, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x10 1.27mm double row -0 -20 -20 -Connector_PinHeader_1.27mm -PinHeader_2x11_P1.27mm_Horizontal -Through hole angled pin header, 2x11, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x11 1.27mm double row -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_2x11_P1.27mm_Vertical -Through hole straight pin header, 2x11, 1.27mm pitch, double rows -Through hole pin header THT 2x11 1.27mm double row -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_2x11_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x11, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x11 1.27mm double row -0 -22 -22 -Connector_PinHeader_1.27mm -PinHeader_2x12_P1.27mm_Horizontal -Through hole angled pin header, 2x12, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x12 1.27mm double row -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_2x12_P1.27mm_Vertical -Through hole straight pin header, 2x12, 1.27mm pitch, double rows -Through hole pin header THT 2x12 1.27mm double row -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_2x12_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x12, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x12 1.27mm double row -0 -24 -24 -Connector_PinHeader_1.27mm -PinHeader_2x13_P1.27mm_Horizontal -Through hole angled pin header, 2x13, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x13 1.27mm double row -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_2x13_P1.27mm_Vertical -Through hole straight pin header, 2x13, 1.27mm pitch, double rows -Through hole pin header THT 2x13 1.27mm double row -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_2x13_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x13, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x13 1.27mm double row -0 -26 -26 -Connector_PinHeader_1.27mm -PinHeader_2x14_P1.27mm_Horizontal -Through hole angled pin header, 2x14, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x14 1.27mm double row -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_2x14_P1.27mm_Vertical -Through hole straight pin header, 2x14, 1.27mm pitch, double rows -Through hole pin header THT 2x14 1.27mm double row -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_2x14_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x14, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x14 1.27mm double row -0 -28 -28 -Connector_PinHeader_1.27mm -PinHeader_2x15_P1.27mm_Horizontal -Through hole angled pin header, 2x15, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x15 1.27mm double row -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_2x15_P1.27mm_Vertical -Through hole straight pin header, 2x15, 1.27mm pitch, double rows -Through hole pin header THT 2x15 1.27mm double row -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_2x15_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x15, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x15 1.27mm double row -0 -30 -30 -Connector_PinHeader_1.27mm -PinHeader_2x16_P1.27mm_Horizontal -Through hole angled pin header, 2x16, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x16 1.27mm double row -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_2x16_P1.27mm_Vertical -Through hole straight pin header, 2x16, 1.27mm pitch, double rows -Through hole pin header THT 2x16 1.27mm double row -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_2x16_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x16, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x16 1.27mm double row -0 -32 -32 -Connector_PinHeader_1.27mm -PinHeader_2x17_P1.27mm_Horizontal -Through hole angled pin header, 2x17, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x17 1.27mm double row -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_2x17_P1.27mm_Vertical -Through hole straight pin header, 2x17, 1.27mm pitch, double rows -Through hole pin header THT 2x17 1.27mm double row -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_2x17_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x17, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x17 1.27mm double row -0 -34 -34 -Connector_PinHeader_1.27mm -PinHeader_2x18_P1.27mm_Horizontal -Through hole angled pin header, 2x18, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x18 1.27mm double row -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_2x18_P1.27mm_Vertical -Through hole straight pin header, 2x18, 1.27mm pitch, double rows -Through hole pin header THT 2x18 1.27mm double row -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_2x18_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x18, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x18 1.27mm double row -0 -36 -36 -Connector_PinHeader_1.27mm -PinHeader_2x19_P1.27mm_Horizontal -Through hole angled pin header, 2x19, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x19 1.27mm double row -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_2x19_P1.27mm_Vertical -Through hole straight pin header, 2x19, 1.27mm pitch, double rows -Through hole pin header THT 2x19 1.27mm double row -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_2x19_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x19, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x19 1.27mm double row -0 -38 -38 -Connector_PinHeader_1.27mm -PinHeader_2x20_P1.27mm_Horizontal -Through hole angled pin header, 2x20, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x20 1.27mm double row -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_2x20_P1.27mm_Vertical -Through hole straight pin header, 2x20, 1.27mm pitch, double rows -Through hole pin header THT 2x20 1.27mm double row -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_2x20_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x20, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x20 1.27mm double row -0 -40 -40 -Connector_PinHeader_1.27mm -PinHeader_2x21_P1.27mm_Horizontal -Through hole angled pin header, 2x21, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x21 1.27mm double row -0 -42 -42 -Connector_PinHeader_1.27mm -PinHeader_2x21_P1.27mm_Vertical -Through hole straight pin header, 2x21, 1.27mm pitch, double rows -Through hole pin header THT 2x21 1.27mm double row -0 -42 -42 -Connector_PinHeader_1.27mm -PinHeader_2x21_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x21, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x21 1.27mm double row -0 -42 -42 -Connector_PinHeader_1.27mm -PinHeader_2x22_P1.27mm_Horizontal -Through hole angled pin header, 2x22, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x22 1.27mm double row -0 -44 -44 -Connector_PinHeader_1.27mm -PinHeader_2x22_P1.27mm_Vertical -Through hole straight pin header, 2x22, 1.27mm pitch, double rows -Through hole pin header THT 2x22 1.27mm double row -0 -44 -44 -Connector_PinHeader_1.27mm -PinHeader_2x22_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x22, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x22 1.27mm double row -0 -44 -44 -Connector_PinHeader_1.27mm -PinHeader_2x23_P1.27mm_Horizontal -Through hole angled pin header, 2x23, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x23 1.27mm double row -0 -46 -46 -Connector_PinHeader_1.27mm -PinHeader_2x23_P1.27mm_Vertical -Through hole straight pin header, 2x23, 1.27mm pitch, double rows -Through hole pin header THT 2x23 1.27mm double row -0 -46 -46 -Connector_PinHeader_1.27mm -PinHeader_2x23_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x23, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x23 1.27mm double row -0 -46 -46 -Connector_PinHeader_1.27mm -PinHeader_2x24_P1.27mm_Horizontal -Through hole angled pin header, 2x24, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x24 1.27mm double row -0 -48 -48 -Connector_PinHeader_1.27mm -PinHeader_2x24_P1.27mm_Vertical -Through hole straight pin header, 2x24, 1.27mm pitch, double rows -Through hole pin header THT 2x24 1.27mm double row -0 -48 -48 -Connector_PinHeader_1.27mm -PinHeader_2x24_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x24, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x24 1.27mm double row -0 -48 -48 -Connector_PinHeader_1.27mm -PinHeader_2x25_P1.27mm_Horizontal -Through hole angled pin header, 2x25, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x25 1.27mm double row -0 -50 -50 -Connector_PinHeader_1.27mm -PinHeader_2x25_P1.27mm_Vertical -Through hole straight pin header, 2x25, 1.27mm pitch, double rows -Through hole pin header THT 2x25 1.27mm double row -0 -50 -50 -Connector_PinHeader_1.27mm -PinHeader_2x25_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x25, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x25 1.27mm double row -0 -50 -50 -Connector_PinHeader_1.27mm -PinHeader_2x26_P1.27mm_Horizontal -Through hole angled pin header, 2x26, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x26 1.27mm double row -0 -52 -52 -Connector_PinHeader_1.27mm -PinHeader_2x26_P1.27mm_Vertical -Through hole straight pin header, 2x26, 1.27mm pitch, double rows -Through hole pin header THT 2x26 1.27mm double row -0 -52 -52 -Connector_PinHeader_1.27mm -PinHeader_2x26_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x26, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x26 1.27mm double row -0 -52 -52 -Connector_PinHeader_1.27mm -PinHeader_2x27_P1.27mm_Horizontal -Through hole angled pin header, 2x27, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x27 1.27mm double row -0 -54 -54 -Connector_PinHeader_1.27mm -PinHeader_2x27_P1.27mm_Vertical -Through hole straight pin header, 2x27, 1.27mm pitch, double rows -Through hole pin header THT 2x27 1.27mm double row -0 -54 -54 -Connector_PinHeader_1.27mm -PinHeader_2x27_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x27, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x27 1.27mm double row -0 -54 -54 -Connector_PinHeader_1.27mm -PinHeader_2x28_P1.27mm_Horizontal -Through hole angled pin header, 2x28, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x28 1.27mm double row -0 -56 -56 -Connector_PinHeader_1.27mm -PinHeader_2x28_P1.27mm_Vertical -Through hole straight pin header, 2x28, 1.27mm pitch, double rows -Through hole pin header THT 2x28 1.27mm double row -0 -56 -56 -Connector_PinHeader_1.27mm -PinHeader_2x28_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x28, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x28 1.27mm double row -0 -56 -56 -Connector_PinHeader_1.27mm -PinHeader_2x29_P1.27mm_Horizontal -Through hole angled pin header, 2x29, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x29 1.27mm double row -0 -58 -58 -Connector_PinHeader_1.27mm -PinHeader_2x29_P1.27mm_Vertical -Through hole straight pin header, 2x29, 1.27mm pitch, double rows -Through hole pin header THT 2x29 1.27mm double row -0 -58 -58 -Connector_PinHeader_1.27mm -PinHeader_2x29_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x29, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x29 1.27mm double row -0 -58 -58 -Connector_PinHeader_1.27mm -PinHeader_2x30_P1.27mm_Horizontal -Through hole angled pin header, 2x30, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x30 1.27mm double row -0 -60 -60 -Connector_PinHeader_1.27mm -PinHeader_2x30_P1.27mm_Vertical -Through hole straight pin header, 2x30, 1.27mm pitch, double rows -Through hole pin header THT 2x30 1.27mm double row -0 -60 -60 -Connector_PinHeader_1.27mm -PinHeader_2x30_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x30, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x30 1.27mm double row -0 -60 -60 -Connector_PinHeader_1.27mm -PinHeader_2x31_P1.27mm_Horizontal -Through hole angled pin header, 2x31, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x31 1.27mm double row -0 -62 -62 -Connector_PinHeader_1.27mm -PinHeader_2x31_P1.27mm_Vertical -Through hole straight pin header, 2x31, 1.27mm pitch, double rows -Through hole pin header THT 2x31 1.27mm double row -0 -62 -62 -Connector_PinHeader_1.27mm -PinHeader_2x31_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x31, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x31 1.27mm double row -0 -62 -62 -Connector_PinHeader_1.27mm -PinHeader_2x32_P1.27mm_Horizontal -Through hole angled pin header, 2x32, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x32 1.27mm double row -0 -64 -64 -Connector_PinHeader_1.27mm -PinHeader_2x32_P1.27mm_Vertical -Through hole straight pin header, 2x32, 1.27mm pitch, double rows -Through hole pin header THT 2x32 1.27mm double row -0 -64 -64 -Connector_PinHeader_1.27mm -PinHeader_2x32_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x32, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x32 1.27mm double row -0 -64 -64 -Connector_PinHeader_1.27mm -PinHeader_2x33_P1.27mm_Horizontal -Through hole angled pin header, 2x33, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x33 1.27mm double row -0 -66 -66 -Connector_PinHeader_1.27mm -PinHeader_2x33_P1.27mm_Vertical -Through hole straight pin header, 2x33, 1.27mm pitch, double rows -Through hole pin header THT 2x33 1.27mm double row -0 -66 -66 -Connector_PinHeader_1.27mm -PinHeader_2x33_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x33, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x33 1.27mm double row -0 -66 -66 -Connector_PinHeader_1.27mm -PinHeader_2x34_P1.27mm_Horizontal -Through hole angled pin header, 2x34, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x34 1.27mm double row -0 -68 -68 -Connector_PinHeader_1.27mm -PinHeader_2x34_P1.27mm_Vertical -Through hole straight pin header, 2x34, 1.27mm pitch, double rows -Through hole pin header THT 2x34 1.27mm double row -0 -68 -68 -Connector_PinHeader_1.27mm -PinHeader_2x34_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x34, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x34 1.27mm double row -0 -68 -68 -Connector_PinHeader_1.27mm -PinHeader_2x35_P1.27mm_Horizontal -Through hole angled pin header, 2x35, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x35 1.27mm double row -0 -70 -70 -Connector_PinHeader_1.27mm -PinHeader_2x35_P1.27mm_Vertical -Through hole straight pin header, 2x35, 1.27mm pitch, double rows -Through hole pin header THT 2x35 1.27mm double row -0 -70 -70 -Connector_PinHeader_1.27mm -PinHeader_2x35_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x35, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x35 1.27mm double row -0 -70 -70 -Connector_PinHeader_1.27mm -PinHeader_2x36_P1.27mm_Horizontal -Through hole angled pin header, 2x36, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x36 1.27mm double row -0 -72 -72 -Connector_PinHeader_1.27mm -PinHeader_2x36_P1.27mm_Vertical -Through hole straight pin header, 2x36, 1.27mm pitch, double rows -Through hole pin header THT 2x36 1.27mm double row -0 -72 -72 -Connector_PinHeader_1.27mm -PinHeader_2x36_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x36, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x36 1.27mm double row -0 -72 -72 -Connector_PinHeader_1.27mm -PinHeader_2x37_P1.27mm_Horizontal -Through hole angled pin header, 2x37, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x37 1.27mm double row -0 -74 -74 -Connector_PinHeader_1.27mm -PinHeader_2x37_P1.27mm_Vertical -Through hole straight pin header, 2x37, 1.27mm pitch, double rows -Through hole pin header THT 2x37 1.27mm double row -0 -74 -74 -Connector_PinHeader_1.27mm -PinHeader_2x37_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x37, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x37 1.27mm double row -0 -74 -74 -Connector_PinHeader_1.27mm -PinHeader_2x38_P1.27mm_Horizontal -Through hole angled pin header, 2x38, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x38 1.27mm double row -0 -76 -76 -Connector_PinHeader_1.27mm -PinHeader_2x38_P1.27mm_Vertical -Through hole straight pin header, 2x38, 1.27mm pitch, double rows -Through hole pin header THT 2x38 1.27mm double row -0 -76 -76 -Connector_PinHeader_1.27mm -PinHeader_2x38_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x38, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x38 1.27mm double row -0 -76 -76 -Connector_PinHeader_1.27mm -PinHeader_2x39_P1.27mm_Horizontal -Through hole angled pin header, 2x39, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x39 1.27mm double row -0 -78 -78 -Connector_PinHeader_1.27mm -PinHeader_2x39_P1.27mm_Vertical -Through hole straight pin header, 2x39, 1.27mm pitch, double rows -Through hole pin header THT 2x39 1.27mm double row -0 -78 -78 -Connector_PinHeader_1.27mm -PinHeader_2x39_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x39, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x39 1.27mm double row -0 -78 -78 -Connector_PinHeader_1.27mm -PinHeader_2x40_P1.27mm_Horizontal -Through hole angled pin header, 2x40, 1.27mm pitch, 4.0mm pin length, double rows -Through hole angled pin header THT 2x40 1.27mm double row -0 -80 -80 -Connector_PinHeader_1.27mm -PinHeader_2x40_P1.27mm_Vertical -Through hole straight pin header, 2x40, 1.27mm pitch, double rows -Through hole pin header THT 2x40 1.27mm double row -0 -80 -80 -Connector_PinHeader_1.27mm -PinHeader_2x40_P1.27mm_Vertical_SMD -surface-mounted straight pin header, 2x40, 1.27mm pitch, double rows -Surface mounted pin header SMD 2x40 1.27mm double row -0 -80 -80 -Connector_PinHeader_2.00mm -PinHeader_1x01_P2.00mm_Horizontal -Through hole angled pin header, 1x01, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x01 2.00mm single row -0 -1 -1 -Connector_PinHeader_2.00mm -PinHeader_1x01_P2.00mm_Vertical -Through hole straight pin header, 1x01, 2.00mm pitch, single row -Through hole pin header THT 1x01 2.00mm single row -0 -1 -1 -Connector_PinHeader_2.00mm -PinHeader_1x02_P2.00mm_Horizontal -Through hole angled pin header, 1x02, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x02 2.00mm single row -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_1x02_P2.00mm_Vertical -Through hole straight pin header, 1x02, 2.00mm pitch, single row -Through hole pin header THT 1x02 2.00mm single row -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_1x02_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x02, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x02 2.00mm single row style1 pin1 left -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_1x02_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x02, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x02 2.00mm single row style2 pin1 right -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_1x03_P2.00mm_Horizontal -Through hole angled pin header, 1x03, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x03 2.00mm single row -0 -3 -3 -Connector_PinHeader_2.00mm -PinHeader_1x03_P2.00mm_Vertical -Through hole straight pin header, 1x03, 2.00mm pitch, single row -Through hole pin header THT 1x03 2.00mm single row -0 -3 -3 -Connector_PinHeader_2.00mm -PinHeader_1x03_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x03, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x03 2.00mm single row style1 pin1 left -0 -3 -3 -Connector_PinHeader_2.00mm -PinHeader_1x03_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x03, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x03 2.00mm single row style2 pin1 right -0 -3 -3 -Connector_PinHeader_2.00mm -PinHeader_1x04_P2.00mm_Horizontal -Through hole angled pin header, 1x04, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x04 2.00mm single row -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_1x04_P2.00mm_Vertical -Through hole straight pin header, 1x04, 2.00mm pitch, single row -Through hole pin header THT 1x04 2.00mm single row -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_1x04_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x04, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x04 2.00mm single row style1 pin1 left -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_1x04_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x04, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x04 2.00mm single row style2 pin1 right -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_1x05_P2.00mm_Horizontal -Through hole angled pin header, 1x05, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x05 2.00mm single row -0 -5 -5 -Connector_PinHeader_2.00mm -PinHeader_1x05_P2.00mm_Vertical -Through hole straight pin header, 1x05, 2.00mm pitch, single row -Through hole pin header THT 1x05 2.00mm single row -0 -5 -5 -Connector_PinHeader_2.00mm -PinHeader_1x05_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x05, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x05 2.00mm single row style1 pin1 left -0 -5 -5 -Connector_PinHeader_2.00mm -PinHeader_1x05_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x05, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x05 2.00mm single row style2 pin1 right -0 -5 -5 -Connector_PinHeader_2.00mm -PinHeader_1x06_P2.00mm_Horizontal -Through hole angled pin header, 1x06, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x06 2.00mm single row -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_1x06_P2.00mm_Vertical -Through hole straight pin header, 1x06, 2.00mm pitch, single row -Through hole pin header THT 1x06 2.00mm single row -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_1x06_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x06, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x06 2.00mm single row style1 pin1 left -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_1x06_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x06, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x06 2.00mm single row style2 pin1 right -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_1x07_P2.00mm_Horizontal -Through hole angled pin header, 1x07, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x07 2.00mm single row -0 -7 -7 -Connector_PinHeader_2.00mm -PinHeader_1x07_P2.00mm_Vertical -Through hole straight pin header, 1x07, 2.00mm pitch, single row -Through hole pin header THT 1x07 2.00mm single row -0 -7 -7 -Connector_PinHeader_2.00mm -PinHeader_1x07_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x07, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x07 2.00mm single row style1 pin1 left -0 -7 -7 -Connector_PinHeader_2.00mm -PinHeader_1x07_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x07, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x07 2.00mm single row style2 pin1 right -0 -7 -7 -Connector_PinHeader_2.00mm -PinHeader_1x08_P2.00mm_Horizontal -Through hole angled pin header, 1x08, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x08 2.00mm single row -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_1x08_P2.00mm_Vertical -Through hole straight pin header, 1x08, 2.00mm pitch, single row -Through hole pin header THT 1x08 2.00mm single row -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_1x08_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x08, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x08 2.00mm single row style1 pin1 left -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_1x08_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x08, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x08 2.00mm single row style2 pin1 right -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_1x09_P2.00mm_Horizontal -Through hole angled pin header, 1x09, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x09 2.00mm single row -0 -9 -9 -Connector_PinHeader_2.00mm -PinHeader_1x09_P2.00mm_Vertical -Through hole straight pin header, 1x09, 2.00mm pitch, single row -Through hole pin header THT 1x09 2.00mm single row -0 -9 -9 -Connector_PinHeader_2.00mm -PinHeader_1x09_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x09, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x09 2.00mm single row style1 pin1 left -0 -9 -9 -Connector_PinHeader_2.00mm -PinHeader_1x09_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x09, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x09 2.00mm single row style2 pin1 right -0 -9 -9 -Connector_PinHeader_2.00mm -PinHeader_1x10_P2.00mm_Horizontal -Through hole angled pin header, 1x10, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x10 2.00mm single row -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_1x10_P2.00mm_Vertical -Through hole straight pin header, 1x10, 2.00mm pitch, single row -Through hole pin header THT 1x10 2.00mm single row -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_1x10_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x10, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x10 2.00mm single row style1 pin1 left -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_1x10_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x10, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x10 2.00mm single row style2 pin1 right -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_1x11_P2.00mm_Horizontal -Through hole angled pin header, 1x11, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x11 2.00mm single row -0 -11 -11 -Connector_PinHeader_2.00mm -PinHeader_1x11_P2.00mm_Vertical -Through hole straight pin header, 1x11, 2.00mm pitch, single row -Through hole pin header THT 1x11 2.00mm single row -0 -11 -11 -Connector_PinHeader_2.00mm -PinHeader_1x11_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x11, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x11 2.00mm single row style1 pin1 left -0 -11 -11 -Connector_PinHeader_2.00mm -PinHeader_1x11_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x11, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x11 2.00mm single row style2 pin1 right -0 -11 -11 -Connector_PinHeader_2.00mm -PinHeader_1x12_P2.00mm_Horizontal -Through hole angled pin header, 1x12, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x12 2.00mm single row -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_1x12_P2.00mm_Vertical -Through hole straight pin header, 1x12, 2.00mm pitch, single row -Through hole pin header THT 1x12 2.00mm single row -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_1x12_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x12, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x12 2.00mm single row style1 pin1 left -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_1x12_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x12, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x12 2.00mm single row style2 pin1 right -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_1x13_P2.00mm_Horizontal -Through hole angled pin header, 1x13, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x13 2.00mm single row -0 -13 -13 -Connector_PinHeader_2.00mm -PinHeader_1x13_P2.00mm_Vertical -Through hole straight pin header, 1x13, 2.00mm pitch, single row -Through hole pin header THT 1x13 2.00mm single row -0 -13 -13 -Connector_PinHeader_2.00mm -PinHeader_1x13_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x13, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x13 2.00mm single row style1 pin1 left -0 -13 -13 -Connector_PinHeader_2.00mm -PinHeader_1x13_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x13, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x13 2.00mm single row style2 pin1 right -0 -13 -13 -Connector_PinHeader_2.00mm -PinHeader_1x14_P2.00mm_Horizontal -Through hole angled pin header, 1x14, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x14 2.00mm single row -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_1x14_P2.00mm_Vertical -Through hole straight pin header, 1x14, 2.00mm pitch, single row -Through hole pin header THT 1x14 2.00mm single row -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_1x14_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x14, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x14 2.00mm single row style1 pin1 left -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_1x14_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x14, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x14 2.00mm single row style2 pin1 right -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_1x15_P2.00mm_Horizontal -Through hole angled pin header, 1x15, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x15 2.00mm single row -0 -15 -15 -Connector_PinHeader_2.00mm -PinHeader_1x15_P2.00mm_Vertical -Through hole straight pin header, 1x15, 2.00mm pitch, single row -Through hole pin header THT 1x15 2.00mm single row -0 -15 -15 -Connector_PinHeader_2.00mm -PinHeader_1x15_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x15, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x15 2.00mm single row style1 pin1 left -0 -15 -15 -Connector_PinHeader_2.00mm -PinHeader_1x15_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x15, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x15 2.00mm single row style2 pin1 right -0 -15 -15 -Connector_PinHeader_2.00mm -PinHeader_1x16_P2.00mm_Horizontal -Through hole angled pin header, 1x16, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x16 2.00mm single row -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_1x16_P2.00mm_Vertical -Through hole straight pin header, 1x16, 2.00mm pitch, single row -Through hole pin header THT 1x16 2.00mm single row -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_1x16_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x16, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x16 2.00mm single row style1 pin1 left -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_1x16_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x16, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x16 2.00mm single row style2 pin1 right -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_1x17_P2.00mm_Horizontal -Through hole angled pin header, 1x17, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x17 2.00mm single row -0 -17 -17 -Connector_PinHeader_2.00mm -PinHeader_1x17_P2.00mm_Vertical -Through hole straight pin header, 1x17, 2.00mm pitch, single row -Through hole pin header THT 1x17 2.00mm single row -0 -17 -17 -Connector_PinHeader_2.00mm -PinHeader_1x17_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x17, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x17 2.00mm single row style1 pin1 left -0 -17 -17 -Connector_PinHeader_2.00mm -PinHeader_1x17_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x17, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x17 2.00mm single row style2 pin1 right -0 -17 -17 -Connector_PinHeader_2.00mm -PinHeader_1x18_P2.00mm_Horizontal -Through hole angled pin header, 1x18, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x18 2.00mm single row -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_1x18_P2.00mm_Vertical -Through hole straight pin header, 1x18, 2.00mm pitch, single row -Through hole pin header THT 1x18 2.00mm single row -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_1x18_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x18, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x18 2.00mm single row style1 pin1 left -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_1x18_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x18, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x18 2.00mm single row style2 pin1 right -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_1x19_P2.00mm_Horizontal -Through hole angled pin header, 1x19, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x19 2.00mm single row -0 -19 -19 -Connector_PinHeader_2.00mm -PinHeader_1x19_P2.00mm_Vertical -Through hole straight pin header, 1x19, 2.00mm pitch, single row -Through hole pin header THT 1x19 2.00mm single row -0 -19 -19 -Connector_PinHeader_2.00mm -PinHeader_1x19_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x19, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x19 2.00mm single row style1 pin1 left -0 -19 -19 -Connector_PinHeader_2.00mm -PinHeader_1x19_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x19, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x19 2.00mm single row style2 pin1 right -0 -19 -19 -Connector_PinHeader_2.00mm -PinHeader_1x20_P2.00mm_Horizontal -Through hole angled pin header, 1x20, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x20 2.00mm single row -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_1x20_P2.00mm_Vertical -Through hole straight pin header, 1x20, 2.00mm pitch, single row -Through hole pin header THT 1x20 2.00mm single row -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_1x20_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x20, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x20 2.00mm single row style1 pin1 left -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_1x20_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x20, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x20 2.00mm single row style2 pin1 right -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_1x21_P2.00mm_Horizontal -Through hole angled pin header, 1x21, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x21 2.00mm single row -0 -21 -21 -Connector_PinHeader_2.00mm -PinHeader_1x21_P2.00mm_Vertical -Through hole straight pin header, 1x21, 2.00mm pitch, single row -Through hole pin header THT 1x21 2.00mm single row -0 -21 -21 -Connector_PinHeader_2.00mm -PinHeader_1x21_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x21, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x21 2.00mm single row style1 pin1 left -0 -21 -21 -Connector_PinHeader_2.00mm -PinHeader_1x21_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x21, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x21 2.00mm single row style2 pin1 right -0 -21 -21 -Connector_PinHeader_2.00mm -PinHeader_1x22_P2.00mm_Horizontal -Through hole angled pin header, 1x22, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x22 2.00mm single row -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_1x22_P2.00mm_Vertical -Through hole straight pin header, 1x22, 2.00mm pitch, single row -Through hole pin header THT 1x22 2.00mm single row -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_1x22_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x22, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x22 2.00mm single row style1 pin1 left -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_1x22_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x22, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x22 2.00mm single row style2 pin1 right -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_1x23_P2.00mm_Horizontal -Through hole angled pin header, 1x23, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x23 2.00mm single row -0 -23 -23 -Connector_PinHeader_2.00mm -PinHeader_1x23_P2.00mm_Vertical -Through hole straight pin header, 1x23, 2.00mm pitch, single row -Through hole pin header THT 1x23 2.00mm single row -0 -23 -23 -Connector_PinHeader_2.00mm -PinHeader_1x23_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x23, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x23 2.00mm single row style1 pin1 left -0 -23 -23 -Connector_PinHeader_2.00mm -PinHeader_1x23_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x23, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x23 2.00mm single row style2 pin1 right -0 -23 -23 -Connector_PinHeader_2.00mm -PinHeader_1x24_P2.00mm_Horizontal -Through hole angled pin header, 1x24, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x24 2.00mm single row -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_1x24_P2.00mm_Vertical -Through hole straight pin header, 1x24, 2.00mm pitch, single row -Through hole pin header THT 1x24 2.00mm single row -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_1x24_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x24, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x24 2.00mm single row style1 pin1 left -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_1x24_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x24, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x24 2.00mm single row style2 pin1 right -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_1x25_P2.00mm_Horizontal -Through hole angled pin header, 1x25, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x25 2.00mm single row -0 -25 -25 -Connector_PinHeader_2.00mm -PinHeader_1x25_P2.00mm_Vertical -Through hole straight pin header, 1x25, 2.00mm pitch, single row -Through hole pin header THT 1x25 2.00mm single row -0 -25 -25 -Connector_PinHeader_2.00mm -PinHeader_1x25_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x25, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x25 2.00mm single row style1 pin1 left -0 -25 -25 -Connector_PinHeader_2.00mm -PinHeader_1x25_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x25, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x25 2.00mm single row style2 pin1 right -0 -25 -25 -Connector_PinHeader_2.00mm -PinHeader_1x26_P2.00mm_Horizontal -Through hole angled pin header, 1x26, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x26 2.00mm single row -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_1x26_P2.00mm_Vertical -Through hole straight pin header, 1x26, 2.00mm pitch, single row -Through hole pin header THT 1x26 2.00mm single row -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_1x26_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x26, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x26 2.00mm single row style1 pin1 left -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_1x26_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x26, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x26 2.00mm single row style2 pin1 right -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_1x27_P2.00mm_Horizontal -Through hole angled pin header, 1x27, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x27 2.00mm single row -0 -27 -27 -Connector_PinHeader_2.00mm -PinHeader_1x27_P2.00mm_Vertical -Through hole straight pin header, 1x27, 2.00mm pitch, single row -Through hole pin header THT 1x27 2.00mm single row -0 -27 -27 -Connector_PinHeader_2.00mm -PinHeader_1x27_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x27, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x27 2.00mm single row style1 pin1 left -0 -27 -27 -Connector_PinHeader_2.00mm -PinHeader_1x27_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x27, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x27 2.00mm single row style2 pin1 right -0 -27 -27 -Connector_PinHeader_2.00mm -PinHeader_1x28_P2.00mm_Horizontal -Through hole angled pin header, 1x28, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x28 2.00mm single row -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_1x28_P2.00mm_Vertical -Through hole straight pin header, 1x28, 2.00mm pitch, single row -Through hole pin header THT 1x28 2.00mm single row -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_1x28_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x28, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x28 2.00mm single row style1 pin1 left -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_1x28_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x28, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x28 2.00mm single row style2 pin1 right -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_1x29_P2.00mm_Horizontal -Through hole angled pin header, 1x29, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x29 2.00mm single row -0 -29 -29 -Connector_PinHeader_2.00mm -PinHeader_1x29_P2.00mm_Vertical -Through hole straight pin header, 1x29, 2.00mm pitch, single row -Through hole pin header THT 1x29 2.00mm single row -0 -29 -29 -Connector_PinHeader_2.00mm -PinHeader_1x29_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x29, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x29 2.00mm single row style1 pin1 left -0 -29 -29 -Connector_PinHeader_2.00mm -PinHeader_1x29_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x29, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x29 2.00mm single row style2 pin1 right -0 -29 -29 -Connector_PinHeader_2.00mm -PinHeader_1x30_P2.00mm_Horizontal -Through hole angled pin header, 1x30, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x30 2.00mm single row -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_1x30_P2.00mm_Vertical -Through hole straight pin header, 1x30, 2.00mm pitch, single row -Through hole pin header THT 1x30 2.00mm single row -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_1x30_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x30, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x30 2.00mm single row style1 pin1 left -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_1x30_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x30, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x30 2.00mm single row style2 pin1 right -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_1x31_P2.00mm_Horizontal -Through hole angled pin header, 1x31, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x31 2.00mm single row -0 -31 -31 -Connector_PinHeader_2.00mm -PinHeader_1x31_P2.00mm_Vertical -Through hole straight pin header, 1x31, 2.00mm pitch, single row -Through hole pin header THT 1x31 2.00mm single row -0 -31 -31 -Connector_PinHeader_2.00mm -PinHeader_1x31_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x31, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x31 2.00mm single row style1 pin1 left -0 -31 -31 -Connector_PinHeader_2.00mm -PinHeader_1x31_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x31, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x31 2.00mm single row style2 pin1 right -0 -31 -31 -Connector_PinHeader_2.00mm -PinHeader_1x32_P2.00mm_Horizontal -Through hole angled pin header, 1x32, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x32 2.00mm single row -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_1x32_P2.00mm_Vertical -Through hole straight pin header, 1x32, 2.00mm pitch, single row -Through hole pin header THT 1x32 2.00mm single row -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_1x32_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x32, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x32 2.00mm single row style1 pin1 left -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_1x32_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x32, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x32 2.00mm single row style2 pin1 right -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_1x33_P2.00mm_Horizontal -Through hole angled pin header, 1x33, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x33 2.00mm single row -0 -33 -33 -Connector_PinHeader_2.00mm -PinHeader_1x33_P2.00mm_Vertical -Through hole straight pin header, 1x33, 2.00mm pitch, single row -Through hole pin header THT 1x33 2.00mm single row -0 -33 -33 -Connector_PinHeader_2.00mm -PinHeader_1x33_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x33, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x33 2.00mm single row style1 pin1 left -0 -33 -33 -Connector_PinHeader_2.00mm -PinHeader_1x33_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x33, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x33 2.00mm single row style2 pin1 right -0 -33 -33 -Connector_PinHeader_2.00mm -PinHeader_1x34_P2.00mm_Horizontal -Through hole angled pin header, 1x34, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x34 2.00mm single row -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_1x34_P2.00mm_Vertical -Through hole straight pin header, 1x34, 2.00mm pitch, single row -Through hole pin header THT 1x34 2.00mm single row -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_1x34_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x34, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x34 2.00mm single row style1 pin1 left -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_1x34_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x34, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x34 2.00mm single row style2 pin1 right -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_1x35_P2.00mm_Horizontal -Through hole angled pin header, 1x35, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x35 2.00mm single row -0 -35 -35 -Connector_PinHeader_2.00mm -PinHeader_1x35_P2.00mm_Vertical -Through hole straight pin header, 1x35, 2.00mm pitch, single row -Through hole pin header THT 1x35 2.00mm single row -0 -35 -35 -Connector_PinHeader_2.00mm -PinHeader_1x35_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x35, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x35 2.00mm single row style1 pin1 left -0 -35 -35 -Connector_PinHeader_2.00mm -PinHeader_1x35_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x35, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x35 2.00mm single row style2 pin1 right -0 -35 -35 -Connector_PinHeader_2.00mm -PinHeader_1x36_P2.00mm_Horizontal -Through hole angled pin header, 1x36, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x36 2.00mm single row -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_1x36_P2.00mm_Vertical -Through hole straight pin header, 1x36, 2.00mm pitch, single row -Through hole pin header THT 1x36 2.00mm single row -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_1x36_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x36, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x36 2.00mm single row style1 pin1 left -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_1x36_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x36, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x36 2.00mm single row style2 pin1 right -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_1x37_P2.00mm_Horizontal -Through hole angled pin header, 1x37, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x37 2.00mm single row -0 -37 -37 -Connector_PinHeader_2.00mm -PinHeader_1x37_P2.00mm_Vertical -Through hole straight pin header, 1x37, 2.00mm pitch, single row -Through hole pin header THT 1x37 2.00mm single row -0 -37 -37 -Connector_PinHeader_2.00mm -PinHeader_1x37_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x37, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x37 2.00mm single row style1 pin1 left -0 -37 -37 -Connector_PinHeader_2.00mm -PinHeader_1x37_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x37, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x37 2.00mm single row style2 pin1 right -0 -37 -37 -Connector_PinHeader_2.00mm -PinHeader_1x38_P2.00mm_Horizontal -Through hole angled pin header, 1x38, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x38 2.00mm single row -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_1x38_P2.00mm_Vertical -Through hole straight pin header, 1x38, 2.00mm pitch, single row -Through hole pin header THT 1x38 2.00mm single row -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_1x38_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x38, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x38 2.00mm single row style1 pin1 left -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_1x38_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x38, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x38 2.00mm single row style2 pin1 right -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_1x39_P2.00mm_Horizontal -Through hole angled pin header, 1x39, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x39 2.00mm single row -0 -39 -39 -Connector_PinHeader_2.00mm -PinHeader_1x39_P2.00mm_Vertical -Through hole straight pin header, 1x39, 2.00mm pitch, single row -Through hole pin header THT 1x39 2.00mm single row -0 -39 -39 -Connector_PinHeader_2.00mm -PinHeader_1x39_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x39, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x39 2.00mm single row style1 pin1 left -0 -39 -39 -Connector_PinHeader_2.00mm -PinHeader_1x39_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x39, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x39 2.00mm single row style2 pin1 right -0 -39 -39 -Connector_PinHeader_2.00mm -PinHeader_1x40_P2.00mm_Horizontal -Through hole angled pin header, 1x40, 2.00mm pitch, 4.2mm pin length, single row -Through hole angled pin header THT 1x40 2.00mm single row -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_1x40_P2.00mm_Vertical -Through hole straight pin header, 1x40, 2.00mm pitch, single row -Through hole pin header THT 1x40 2.00mm single row -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_1x40_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x40, 2.00mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x40 2.00mm single row style1 pin1 left -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_1x40_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x40, 2.00mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x40 2.00mm single row style2 pin1 right -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_2x01_P2.00mm_Horizontal -Through hole angled pin header, 2x01, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x01 2.00mm double row -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_2x01_P2.00mm_Vertical -Through hole straight pin header, 2x01, 2.00mm pitch, double rows -Through hole pin header THT 2x01 2.00mm double row -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_2x01_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x01, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x01 2.00mm double row -0 -2 -2 -Connector_PinHeader_2.00mm -PinHeader_2x02_P2.00mm_Horizontal -Through hole angled pin header, 2x02, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x02 2.00mm double row -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_2x02_P2.00mm_Vertical -Through hole straight pin header, 2x02, 2.00mm pitch, double rows -Through hole pin header THT 2x02 2.00mm double row -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_2x02_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x02, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x02 2.00mm double row -0 -4 -4 -Connector_PinHeader_2.00mm -PinHeader_2x03_P2.00mm_Horizontal -Through hole angled pin header, 2x03, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x03 2.00mm double row -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_2x03_P2.00mm_Vertical -Through hole straight pin header, 2x03, 2.00mm pitch, double rows -Through hole pin header THT 2x03 2.00mm double row -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_2x03_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x03, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x03 2.00mm double row -0 -6 -6 -Connector_PinHeader_2.00mm -PinHeader_2x04_P2.00mm_Horizontal -Through hole angled pin header, 2x04, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x04 2.00mm double row -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_2x04_P2.00mm_Vertical -Through hole straight pin header, 2x04, 2.00mm pitch, double rows -Through hole pin header THT 2x04 2.00mm double row -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_2x04_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x04, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x04 2.00mm double row -0 -8 -8 -Connector_PinHeader_2.00mm -PinHeader_2x05_P2.00mm_Horizontal -Through hole angled pin header, 2x05, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x05 2.00mm double row -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_2x05_P2.00mm_Vertical -Through hole straight pin header, 2x05, 2.00mm pitch, double rows -Through hole pin header THT 2x05 2.00mm double row -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_2x05_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x05, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x05 2.00mm double row -0 -10 -10 -Connector_PinHeader_2.00mm -PinHeader_2x06_P2.00mm_Horizontal -Through hole angled pin header, 2x06, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x06 2.00mm double row -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_2x06_P2.00mm_Vertical -Through hole straight pin header, 2x06, 2.00mm pitch, double rows -Through hole pin header THT 2x06 2.00mm double row -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_2x06_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x06, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x06 2.00mm double row -0 -12 -12 -Connector_PinHeader_2.00mm -PinHeader_2x07_P2.00mm_Horizontal -Through hole angled pin header, 2x07, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x07 2.00mm double row -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_2x07_P2.00mm_Vertical -Through hole straight pin header, 2x07, 2.00mm pitch, double rows -Through hole pin header THT 2x07 2.00mm double row -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_2x07_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x07, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x07 2.00mm double row -0 -14 -14 -Connector_PinHeader_2.00mm -PinHeader_2x08_P2.00mm_Horizontal -Through hole angled pin header, 2x08, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x08 2.00mm double row -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_2x08_P2.00mm_Vertical -Through hole straight pin header, 2x08, 2.00mm pitch, double rows -Through hole pin header THT 2x08 2.00mm double row -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_2x08_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x08, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x08 2.00mm double row -0 -16 -16 -Connector_PinHeader_2.00mm -PinHeader_2x09_P2.00mm_Horizontal -Through hole angled pin header, 2x09, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x09 2.00mm double row -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_2x09_P2.00mm_Vertical -Through hole straight pin header, 2x09, 2.00mm pitch, double rows -Through hole pin header THT 2x09 2.00mm double row -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_2x09_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x09, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x09 2.00mm double row -0 -18 -18 -Connector_PinHeader_2.00mm -PinHeader_2x10_P2.00mm_Horizontal -Through hole angled pin header, 2x10, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x10 2.00mm double row -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_2x10_P2.00mm_Vertical -Through hole straight pin header, 2x10, 2.00mm pitch, double rows -Through hole pin header THT 2x10 2.00mm double row -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_2x10_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x10, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x10 2.00mm double row -0 -20 -20 -Connector_PinHeader_2.00mm -PinHeader_2x11_P2.00mm_Horizontal -Through hole angled pin header, 2x11, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x11 2.00mm double row -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_2x11_P2.00mm_Vertical -Through hole straight pin header, 2x11, 2.00mm pitch, double rows -Through hole pin header THT 2x11 2.00mm double row -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_2x11_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x11, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x11 2.00mm double row -0 -22 -22 -Connector_PinHeader_2.00mm -PinHeader_2x12_P2.00mm_Horizontal -Through hole angled pin header, 2x12, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x12 2.00mm double row -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_2x12_P2.00mm_Vertical -Through hole straight pin header, 2x12, 2.00mm pitch, double rows -Through hole pin header THT 2x12 2.00mm double row -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_2x12_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x12, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x12 2.00mm double row -0 -24 -24 -Connector_PinHeader_2.00mm -PinHeader_2x13_P2.00mm_Horizontal -Through hole angled pin header, 2x13, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x13 2.00mm double row -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_2x13_P2.00mm_Vertical -Through hole straight pin header, 2x13, 2.00mm pitch, double rows -Through hole pin header THT 2x13 2.00mm double row -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_2x13_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x13, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x13 2.00mm double row -0 -26 -26 -Connector_PinHeader_2.00mm -PinHeader_2x14_P2.00mm_Horizontal -Through hole angled pin header, 2x14, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x14 2.00mm double row -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_2x14_P2.00mm_Vertical -Through hole straight pin header, 2x14, 2.00mm pitch, double rows -Through hole pin header THT 2x14 2.00mm double row -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_2x14_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x14, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x14 2.00mm double row -0 -28 -28 -Connector_PinHeader_2.00mm -PinHeader_2x15_P2.00mm_Horizontal -Through hole angled pin header, 2x15, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x15 2.00mm double row -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_2x15_P2.00mm_Vertical -Through hole straight pin header, 2x15, 2.00mm pitch, double rows -Through hole pin header THT 2x15 2.00mm double row -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_2x15_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x15, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x15 2.00mm double row -0 -30 -30 -Connector_PinHeader_2.00mm -PinHeader_2x16_P2.00mm_Horizontal -Through hole angled pin header, 2x16, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x16 2.00mm double row -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_2x16_P2.00mm_Vertical -Through hole straight pin header, 2x16, 2.00mm pitch, double rows -Through hole pin header THT 2x16 2.00mm double row -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_2x16_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x16, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x16 2.00mm double row -0 -32 -32 -Connector_PinHeader_2.00mm -PinHeader_2x17_P2.00mm_Horizontal -Through hole angled pin header, 2x17, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x17 2.00mm double row -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_2x17_P2.00mm_Vertical -Through hole straight pin header, 2x17, 2.00mm pitch, double rows -Through hole pin header THT 2x17 2.00mm double row -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_2x17_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x17, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x17 2.00mm double row -0 -34 -34 -Connector_PinHeader_2.00mm -PinHeader_2x18_P2.00mm_Horizontal -Through hole angled pin header, 2x18, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x18 2.00mm double row -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_2x18_P2.00mm_Vertical -Through hole straight pin header, 2x18, 2.00mm pitch, double rows -Through hole pin header THT 2x18 2.00mm double row -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_2x18_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x18, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x18 2.00mm double row -0 -36 -36 -Connector_PinHeader_2.00mm -PinHeader_2x19_P2.00mm_Horizontal -Through hole angled pin header, 2x19, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x19 2.00mm double row -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_2x19_P2.00mm_Vertical -Through hole straight pin header, 2x19, 2.00mm pitch, double rows -Through hole pin header THT 2x19 2.00mm double row -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_2x19_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x19, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x19 2.00mm double row -0 -38 -38 -Connector_PinHeader_2.00mm -PinHeader_2x20_P2.00mm_Horizontal -Through hole angled pin header, 2x20, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x20 2.00mm double row -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_2x20_P2.00mm_Vertical -Through hole straight pin header, 2x20, 2.00mm pitch, double rows -Through hole pin header THT 2x20 2.00mm double row -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_2x20_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x20, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x20 2.00mm double row -0 -40 -40 -Connector_PinHeader_2.00mm -PinHeader_2x21_P2.00mm_Horizontal -Through hole angled pin header, 2x21, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x21 2.00mm double row -0 -42 -42 -Connector_PinHeader_2.00mm -PinHeader_2x21_P2.00mm_Vertical -Through hole straight pin header, 2x21, 2.00mm pitch, double rows -Through hole pin header THT 2x21 2.00mm double row -0 -42 -42 -Connector_PinHeader_2.00mm -PinHeader_2x21_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x21, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x21 2.00mm double row -0 -42 -42 -Connector_PinHeader_2.00mm -PinHeader_2x22_P2.00mm_Horizontal -Through hole angled pin header, 2x22, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x22 2.00mm double row -0 -44 -44 -Connector_PinHeader_2.00mm -PinHeader_2x22_P2.00mm_Vertical -Through hole straight pin header, 2x22, 2.00mm pitch, double rows -Through hole pin header THT 2x22 2.00mm double row -0 -44 -44 -Connector_PinHeader_2.00mm -PinHeader_2x22_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x22, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x22 2.00mm double row -0 -44 -44 -Connector_PinHeader_2.00mm -PinHeader_2x23_P2.00mm_Horizontal -Through hole angled pin header, 2x23, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x23 2.00mm double row -0 -46 -46 -Connector_PinHeader_2.00mm -PinHeader_2x23_P2.00mm_Vertical -Through hole straight pin header, 2x23, 2.00mm pitch, double rows -Through hole pin header THT 2x23 2.00mm double row -0 -46 -46 -Connector_PinHeader_2.00mm -PinHeader_2x23_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x23, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x23 2.00mm double row -0 -46 -46 -Connector_PinHeader_2.00mm -PinHeader_2x24_P2.00mm_Horizontal -Through hole angled pin header, 2x24, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x24 2.00mm double row -0 -48 -48 -Connector_PinHeader_2.00mm -PinHeader_2x24_P2.00mm_Vertical -Through hole straight pin header, 2x24, 2.00mm pitch, double rows -Through hole pin header THT 2x24 2.00mm double row -0 -48 -48 -Connector_PinHeader_2.00mm -PinHeader_2x24_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x24, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x24 2.00mm double row -0 -48 -48 -Connector_PinHeader_2.00mm -PinHeader_2x25_P2.00mm_Horizontal -Through hole angled pin header, 2x25, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x25 2.00mm double row -0 -50 -50 -Connector_PinHeader_2.00mm -PinHeader_2x25_P2.00mm_Vertical -Through hole straight pin header, 2x25, 2.00mm pitch, double rows -Through hole pin header THT 2x25 2.00mm double row -0 -50 -50 -Connector_PinHeader_2.00mm -PinHeader_2x25_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x25, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x25 2.00mm double row -0 -50 -50 -Connector_PinHeader_2.00mm -PinHeader_2x26_P2.00mm_Horizontal -Through hole angled pin header, 2x26, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x26 2.00mm double row -0 -52 -52 -Connector_PinHeader_2.00mm -PinHeader_2x26_P2.00mm_Vertical -Through hole straight pin header, 2x26, 2.00mm pitch, double rows -Through hole pin header THT 2x26 2.00mm double row -0 -52 -52 -Connector_PinHeader_2.00mm -PinHeader_2x26_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x26, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x26 2.00mm double row -0 -52 -52 -Connector_PinHeader_2.00mm -PinHeader_2x27_P2.00mm_Horizontal -Through hole angled pin header, 2x27, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x27 2.00mm double row -0 -54 -54 -Connector_PinHeader_2.00mm -PinHeader_2x27_P2.00mm_Vertical -Through hole straight pin header, 2x27, 2.00mm pitch, double rows -Through hole pin header THT 2x27 2.00mm double row -0 -54 -54 -Connector_PinHeader_2.00mm -PinHeader_2x27_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x27, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x27 2.00mm double row -0 -54 -54 -Connector_PinHeader_2.00mm -PinHeader_2x28_P2.00mm_Horizontal -Through hole angled pin header, 2x28, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x28 2.00mm double row -0 -56 -56 -Connector_PinHeader_2.00mm -PinHeader_2x28_P2.00mm_Vertical -Through hole straight pin header, 2x28, 2.00mm pitch, double rows -Through hole pin header THT 2x28 2.00mm double row -0 -56 -56 -Connector_PinHeader_2.00mm -PinHeader_2x28_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x28, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x28 2.00mm double row -0 -56 -56 -Connector_PinHeader_2.00mm -PinHeader_2x29_P2.00mm_Horizontal -Through hole angled pin header, 2x29, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x29 2.00mm double row -0 -58 -58 -Connector_PinHeader_2.00mm -PinHeader_2x29_P2.00mm_Vertical -Through hole straight pin header, 2x29, 2.00mm pitch, double rows -Through hole pin header THT 2x29 2.00mm double row -0 -58 -58 -Connector_PinHeader_2.00mm -PinHeader_2x29_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x29, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x29 2.00mm double row -0 -58 -58 -Connector_PinHeader_2.00mm -PinHeader_2x30_P2.00mm_Horizontal -Through hole angled pin header, 2x30, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x30 2.00mm double row -0 -60 -60 -Connector_PinHeader_2.00mm -PinHeader_2x30_P2.00mm_Vertical -Through hole straight pin header, 2x30, 2.00mm pitch, double rows -Through hole pin header THT 2x30 2.00mm double row -0 -60 -60 -Connector_PinHeader_2.00mm -PinHeader_2x30_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x30, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x30 2.00mm double row -0 -60 -60 -Connector_PinHeader_2.00mm -PinHeader_2x31_P2.00mm_Horizontal -Through hole angled pin header, 2x31, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x31 2.00mm double row -0 -62 -62 -Connector_PinHeader_2.00mm -PinHeader_2x31_P2.00mm_Vertical -Through hole straight pin header, 2x31, 2.00mm pitch, double rows -Through hole pin header THT 2x31 2.00mm double row -0 -62 -62 -Connector_PinHeader_2.00mm -PinHeader_2x31_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x31, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x31 2.00mm double row -0 -62 -62 -Connector_PinHeader_2.00mm -PinHeader_2x32_P2.00mm_Horizontal -Through hole angled pin header, 2x32, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x32 2.00mm double row -0 -64 -64 -Connector_PinHeader_2.00mm -PinHeader_2x32_P2.00mm_Vertical -Through hole straight pin header, 2x32, 2.00mm pitch, double rows -Through hole pin header THT 2x32 2.00mm double row -0 -64 -64 -Connector_PinHeader_2.00mm -PinHeader_2x32_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x32, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x32 2.00mm double row -0 -64 -64 -Connector_PinHeader_2.00mm -PinHeader_2x33_P2.00mm_Horizontal -Through hole angled pin header, 2x33, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x33 2.00mm double row -0 -66 -66 -Connector_PinHeader_2.00mm -PinHeader_2x33_P2.00mm_Vertical -Through hole straight pin header, 2x33, 2.00mm pitch, double rows -Through hole pin header THT 2x33 2.00mm double row -0 -66 -66 -Connector_PinHeader_2.00mm -PinHeader_2x33_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x33, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x33 2.00mm double row -0 -66 -66 -Connector_PinHeader_2.00mm -PinHeader_2x34_P2.00mm_Horizontal -Through hole angled pin header, 2x34, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x34 2.00mm double row -0 -68 -68 -Connector_PinHeader_2.00mm -PinHeader_2x34_P2.00mm_Vertical -Through hole straight pin header, 2x34, 2.00mm pitch, double rows -Through hole pin header THT 2x34 2.00mm double row -0 -68 -68 -Connector_PinHeader_2.00mm -PinHeader_2x34_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x34, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x34 2.00mm double row -0 -68 -68 -Connector_PinHeader_2.00mm -PinHeader_2x35_P2.00mm_Horizontal -Through hole angled pin header, 2x35, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x35 2.00mm double row -0 -70 -70 -Connector_PinHeader_2.00mm -PinHeader_2x35_P2.00mm_Vertical -Through hole straight pin header, 2x35, 2.00mm pitch, double rows -Through hole pin header THT 2x35 2.00mm double row -0 -70 -70 -Connector_PinHeader_2.00mm -PinHeader_2x35_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x35, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x35 2.00mm double row -0 -70 -70 -Connector_PinHeader_2.00mm -PinHeader_2x36_P2.00mm_Horizontal -Through hole angled pin header, 2x36, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x36 2.00mm double row -0 -72 -72 -Connector_PinHeader_2.00mm -PinHeader_2x36_P2.00mm_Vertical -Through hole straight pin header, 2x36, 2.00mm pitch, double rows -Through hole pin header THT 2x36 2.00mm double row -0 -72 -72 -Connector_PinHeader_2.00mm -PinHeader_2x36_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x36, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x36 2.00mm double row -0 -72 -72 -Connector_PinHeader_2.00mm -PinHeader_2x37_P2.00mm_Horizontal -Through hole angled pin header, 2x37, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x37 2.00mm double row -0 -74 -74 -Connector_PinHeader_2.00mm -PinHeader_2x37_P2.00mm_Vertical -Through hole straight pin header, 2x37, 2.00mm pitch, double rows -Through hole pin header THT 2x37 2.00mm double row -0 -74 -74 -Connector_PinHeader_2.00mm -PinHeader_2x37_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x37, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x37 2.00mm double row -0 -74 -74 -Connector_PinHeader_2.00mm -PinHeader_2x38_P2.00mm_Horizontal -Through hole angled pin header, 2x38, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x38 2.00mm double row -0 -76 -76 -Connector_PinHeader_2.00mm -PinHeader_2x38_P2.00mm_Vertical -Through hole straight pin header, 2x38, 2.00mm pitch, double rows -Through hole pin header THT 2x38 2.00mm double row -0 -76 -76 -Connector_PinHeader_2.00mm -PinHeader_2x38_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x38, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x38 2.00mm double row -0 -76 -76 -Connector_PinHeader_2.00mm -PinHeader_2x39_P2.00mm_Horizontal -Through hole angled pin header, 2x39, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x39 2.00mm double row -0 -78 -78 -Connector_PinHeader_2.00mm -PinHeader_2x39_P2.00mm_Vertical -Through hole straight pin header, 2x39, 2.00mm pitch, double rows -Through hole pin header THT 2x39 2.00mm double row -0 -78 -78 -Connector_PinHeader_2.00mm -PinHeader_2x39_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x39, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x39 2.00mm double row -0 -78 -78 -Connector_PinHeader_2.00mm -PinHeader_2x40_P2.00mm_Horizontal -Through hole angled pin header, 2x40, 2.00mm pitch, 4.2mm pin length, double rows -Through hole angled pin header THT 2x40 2.00mm double row -0 -80 -80 -Connector_PinHeader_2.00mm -PinHeader_2x40_P2.00mm_Vertical -Through hole straight pin header, 2x40, 2.00mm pitch, double rows -Through hole pin header THT 2x40 2.00mm double row -0 -80 -80 -Connector_PinHeader_2.00mm -PinHeader_2x40_P2.00mm_Vertical_SMD -surface-mounted straight pin header, 2x40, 2.00mm pitch, double rows -Surface mounted pin header SMD 2x40 2.00mm double row -0 -80 -80 -Connector_PinHeader_2.54mm -PinHeader_1x01_P2.54mm_Horizontal -Through hole angled pin header, 1x01, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x01 2.54mm single row -0 -1 -1 -Connector_PinHeader_2.54mm -PinHeader_1x01_P2.54mm_Vertical -Through hole straight pin header, 1x01, 2.54mm pitch, single row -Through hole pin header THT 1x01 2.54mm single row -0 -1 -1 -Connector_PinHeader_2.54mm -PinHeader_1x02_P2.54mm_Horizontal -Through hole angled pin header, 1x02, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x02 2.54mm single row -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_1x02_P2.54mm_Vertical -Through hole straight pin header, 1x02, 2.54mm pitch, single row -Through hole pin header THT 1x02 2.54mm single row -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x02 2.54mm single row style1 pin1 left -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x02 2.54mm single row style2 pin1 right -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_1x03_P2.54mm_Horizontal -Through hole angled pin header, 1x03, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x03 2.54mm single row -0 -3 -3 -Connector_PinHeader_2.54mm -PinHeader_1x03_P2.54mm_Vertical -Through hole straight pin header, 1x03, 2.54mm pitch, single row -Through hole pin header THT 1x03 2.54mm single row -0 -3 -3 -Connector_PinHeader_2.54mm -PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left -0 -3 -3 -Connector_PinHeader_2.54mm -PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x03 2.54mm single row style2 pin1 right -0 -3 -3 -Connector_PinHeader_2.54mm -PinHeader_1x04_P2.54mm_Horizontal -Through hole angled pin header, 1x04, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x04 2.54mm single row -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_1x04_P2.54mm_Vertical -Through hole straight pin header, 1x04, 2.54mm pitch, single row -Through hole pin header THT 1x04 2.54mm single row -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x04 2.54mm single row style1 pin1 left -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x04 2.54mm single row style2 pin1 right -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_1x05_P2.54mm_Horizontal -Through hole angled pin header, 1x05, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x05 2.54mm single row -0 -5 -5 -Connector_PinHeader_2.54mm -PinHeader_1x05_P2.54mm_Vertical -Through hole straight pin header, 1x05, 2.54mm pitch, single row -Through hole pin header THT 1x05 2.54mm single row -0 -5 -5 -Connector_PinHeader_2.54mm -PinHeader_1x05_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x05 2.54mm single row style1 pin1 left -0 -5 -5 -Connector_PinHeader_2.54mm -PinHeader_1x05_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x05 2.54mm single row style2 pin1 right -0 -5 -5 -Connector_PinHeader_2.54mm -PinHeader_1x06_P2.54mm_Horizontal -Through hole angled pin header, 1x06, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x06 2.54mm single row -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_1x06_P2.54mm_Vertical -Through hole straight pin header, 1x06, 2.54mm pitch, single row -Through hole pin header THT 1x06 2.54mm single row -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x06 2.54mm single row style1 pin1 left -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x06 2.54mm single row style2 pin1 right -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_1x07_P2.54mm_Horizontal -Through hole angled pin header, 1x07, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x07 2.54mm single row -0 -7 -7 -Connector_PinHeader_2.54mm -PinHeader_1x07_P2.54mm_Vertical -Through hole straight pin header, 1x07, 2.54mm pitch, single row -Through hole pin header THT 1x07 2.54mm single row -0 -7 -7 -Connector_PinHeader_2.54mm -PinHeader_1x07_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x07 2.54mm single row style1 pin1 left -0 -7 -7 -Connector_PinHeader_2.54mm -PinHeader_1x07_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x07 2.54mm single row style2 pin1 right -0 -7 -7 -Connector_PinHeader_2.54mm -PinHeader_1x08_P2.54mm_Horizontal -Through hole angled pin header, 1x08, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x08 2.54mm single row -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_1x08_P2.54mm_Vertical -Through hole straight pin header, 1x08, 2.54mm pitch, single row -Through hole pin header THT 1x08 2.54mm single row -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_1x08_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x08 2.54mm single row style1 pin1 left -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_1x08_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x08 2.54mm single row style2 pin1 right -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_1x09_P2.54mm_Horizontal -Through hole angled pin header, 1x09, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x09 2.54mm single row -0 -9 -9 -Connector_PinHeader_2.54mm -PinHeader_1x09_P2.54mm_Vertical -Through hole straight pin header, 1x09, 2.54mm pitch, single row -Through hole pin header THT 1x09 2.54mm single row -0 -9 -9 -Connector_PinHeader_2.54mm -PinHeader_1x09_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x09 2.54mm single row style1 pin1 left -0 -9 -9 -Connector_PinHeader_2.54mm -PinHeader_1x09_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x09 2.54mm single row style2 pin1 right -0 -9 -9 -Connector_PinHeader_2.54mm -PinHeader_1x10_P2.54mm_Horizontal -Through hole angled pin header, 1x10, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x10 2.54mm single row -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_1x10_P2.54mm_Vertical -Through hole straight pin header, 1x10, 2.54mm pitch, single row -Through hole pin header THT 1x10 2.54mm single row -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_1x10_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x10 2.54mm single row style1 pin1 left -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_1x10_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x10 2.54mm single row style2 pin1 right -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_1x11_P2.54mm_Horizontal -Through hole angled pin header, 1x11, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x11 2.54mm single row -0 -11 -11 -Connector_PinHeader_2.54mm -PinHeader_1x11_P2.54mm_Vertical -Through hole straight pin header, 1x11, 2.54mm pitch, single row -Through hole pin header THT 1x11 2.54mm single row -0 -11 -11 -Connector_PinHeader_2.54mm -PinHeader_1x11_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x11 2.54mm single row style1 pin1 left -0 -11 -11 -Connector_PinHeader_2.54mm -PinHeader_1x11_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x11 2.54mm single row style2 pin1 right -0 -11 -11 -Connector_PinHeader_2.54mm -PinHeader_1x12_P2.54mm_Horizontal -Through hole angled pin header, 1x12, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x12 2.54mm single row -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_1x12_P2.54mm_Vertical -Through hole straight pin header, 1x12, 2.54mm pitch, single row -Through hole pin header THT 1x12 2.54mm single row -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_1x12_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x12 2.54mm single row style1 pin1 left -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_1x12_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x12 2.54mm single row style2 pin1 right -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_1x13_P2.54mm_Horizontal -Through hole angled pin header, 1x13, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x13 2.54mm single row -0 -13 -13 -Connector_PinHeader_2.54mm -PinHeader_1x13_P2.54mm_Vertical -Through hole straight pin header, 1x13, 2.54mm pitch, single row -Through hole pin header THT 1x13 2.54mm single row -0 -13 -13 -Connector_PinHeader_2.54mm -PinHeader_1x13_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x13 2.54mm single row style1 pin1 left -0 -13 -13 -Connector_PinHeader_2.54mm -PinHeader_1x13_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x13 2.54mm single row style2 pin1 right -0 -13 -13 -Connector_PinHeader_2.54mm -PinHeader_1x14_P2.54mm_Horizontal -Through hole angled pin header, 1x14, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x14 2.54mm single row -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_1x14_P2.54mm_Vertical -Through hole straight pin header, 1x14, 2.54mm pitch, single row -Through hole pin header THT 1x14 2.54mm single row -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_1x14_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x14 2.54mm single row style1 pin1 left -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_1x14_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x14 2.54mm single row style2 pin1 right -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_1x15_P2.54mm_Horizontal -Through hole angled pin header, 1x15, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x15 2.54mm single row -0 -15 -15 -Connector_PinHeader_2.54mm -PinHeader_1x15_P2.54mm_Vertical -Through hole straight pin header, 1x15, 2.54mm pitch, single row -Through hole pin header THT 1x15 2.54mm single row -0 -15 -15 -Connector_PinHeader_2.54mm -PinHeader_1x15_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x15 2.54mm single row style1 pin1 left -0 -15 -15 -Connector_PinHeader_2.54mm -PinHeader_1x15_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x15 2.54mm single row style2 pin1 right -0 -15 -15 -Connector_PinHeader_2.54mm -PinHeader_1x16_P2.54mm_Horizontal -Through hole angled pin header, 1x16, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x16 2.54mm single row -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_1x16_P2.54mm_Vertical -Through hole straight pin header, 1x16, 2.54mm pitch, single row -Through hole pin header THT 1x16 2.54mm single row -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_1x16_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x16 2.54mm single row style1 pin1 left -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_1x16_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x16 2.54mm single row style2 pin1 right -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_1x17_P2.54mm_Horizontal -Through hole angled pin header, 1x17, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x17 2.54mm single row -0 -17 -17 -Connector_PinHeader_2.54mm -PinHeader_1x17_P2.54mm_Vertical -Through hole straight pin header, 1x17, 2.54mm pitch, single row -Through hole pin header THT 1x17 2.54mm single row -0 -17 -17 -Connector_PinHeader_2.54mm -PinHeader_1x17_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x17 2.54mm single row style1 pin1 left -0 -17 -17 -Connector_PinHeader_2.54mm -PinHeader_1x17_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x17 2.54mm single row style2 pin1 right -0 -17 -17 -Connector_PinHeader_2.54mm -PinHeader_1x18_P2.54mm_Horizontal -Through hole angled pin header, 1x18, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x18 2.54mm single row -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_1x18_P2.54mm_Vertical -Through hole straight pin header, 1x18, 2.54mm pitch, single row -Through hole pin header THT 1x18 2.54mm single row -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_1x18_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x18 2.54mm single row style1 pin1 left -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_1x18_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x18 2.54mm single row style2 pin1 right -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_1x19_P2.54mm_Horizontal -Through hole angled pin header, 1x19, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x19 2.54mm single row -0 -19 -19 -Connector_PinHeader_2.54mm -PinHeader_1x19_P2.54mm_Vertical -Through hole straight pin header, 1x19, 2.54mm pitch, single row -Through hole pin header THT 1x19 2.54mm single row -0 -19 -19 -Connector_PinHeader_2.54mm -PinHeader_1x19_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x19 2.54mm single row style1 pin1 left -0 -19 -19 -Connector_PinHeader_2.54mm -PinHeader_1x19_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x19 2.54mm single row style2 pin1 right -0 -19 -19 -Connector_PinHeader_2.54mm -PinHeader_1x20_P2.54mm_Horizontal -Through hole angled pin header, 1x20, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x20 2.54mm single row -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_1x20_P2.54mm_Vertical -Through hole straight pin header, 1x20, 2.54mm pitch, single row -Through hole pin header THT 1x20 2.54mm single row -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_1x20_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x20 2.54mm single row style1 pin1 left -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_1x20_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x20 2.54mm single row style2 pin1 right -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_1x21_P2.54mm_Horizontal -Through hole angled pin header, 1x21, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x21 2.54mm single row -0 -21 -21 -Connector_PinHeader_2.54mm -PinHeader_1x21_P2.54mm_Vertical -Through hole straight pin header, 1x21, 2.54mm pitch, single row -Through hole pin header THT 1x21 2.54mm single row -0 -21 -21 -Connector_PinHeader_2.54mm -PinHeader_1x21_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x21 2.54mm single row style1 pin1 left -0 -21 -21 -Connector_PinHeader_2.54mm -PinHeader_1x21_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x21 2.54mm single row style2 pin1 right -0 -21 -21 -Connector_PinHeader_2.54mm -PinHeader_1x22_P2.54mm_Horizontal -Through hole angled pin header, 1x22, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x22 2.54mm single row -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_1x22_P2.54mm_Vertical -Through hole straight pin header, 1x22, 2.54mm pitch, single row -Through hole pin header THT 1x22 2.54mm single row -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_1x22_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x22 2.54mm single row style1 pin1 left -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_1x22_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x22 2.54mm single row style2 pin1 right -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_1x23_P2.54mm_Horizontal -Through hole angled pin header, 1x23, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x23 2.54mm single row -0 -23 -23 -Connector_PinHeader_2.54mm -PinHeader_1x23_P2.54mm_Vertical -Through hole straight pin header, 1x23, 2.54mm pitch, single row -Through hole pin header THT 1x23 2.54mm single row -0 -23 -23 -Connector_PinHeader_2.54mm -PinHeader_1x23_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x23 2.54mm single row style1 pin1 left -0 -23 -23 -Connector_PinHeader_2.54mm -PinHeader_1x23_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x23 2.54mm single row style2 pin1 right -0 -23 -23 -Connector_PinHeader_2.54mm -PinHeader_1x24_P2.54mm_Horizontal -Through hole angled pin header, 1x24, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x24 2.54mm single row -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_1x24_P2.54mm_Vertical -Through hole straight pin header, 1x24, 2.54mm pitch, single row -Through hole pin header THT 1x24 2.54mm single row -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_1x24_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x24 2.54mm single row style1 pin1 left -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_1x24_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x24 2.54mm single row style2 pin1 right -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_1x25_P2.54mm_Horizontal -Through hole angled pin header, 1x25, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x25 2.54mm single row -0 -25 -25 -Connector_PinHeader_2.54mm -PinHeader_1x25_P2.54mm_Vertical -Through hole straight pin header, 1x25, 2.54mm pitch, single row -Through hole pin header THT 1x25 2.54mm single row -0 -25 -25 -Connector_PinHeader_2.54mm -PinHeader_1x25_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x25 2.54mm single row style1 pin1 left -0 -25 -25 -Connector_PinHeader_2.54mm -PinHeader_1x25_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x25 2.54mm single row style2 pin1 right -0 -25 -25 -Connector_PinHeader_2.54mm -PinHeader_1x26_P2.54mm_Horizontal -Through hole angled pin header, 1x26, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x26 2.54mm single row -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_1x26_P2.54mm_Vertical -Through hole straight pin header, 1x26, 2.54mm pitch, single row -Through hole pin header THT 1x26 2.54mm single row -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_1x26_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x26 2.54mm single row style1 pin1 left -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_1x26_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x26 2.54mm single row style2 pin1 right -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_1x27_P2.54mm_Horizontal -Through hole angled pin header, 1x27, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x27 2.54mm single row -0 -27 -27 -Connector_PinHeader_2.54mm -PinHeader_1x27_P2.54mm_Vertical -Through hole straight pin header, 1x27, 2.54mm pitch, single row -Through hole pin header THT 1x27 2.54mm single row -0 -27 -27 -Connector_PinHeader_2.54mm -PinHeader_1x27_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x27 2.54mm single row style1 pin1 left -0 -27 -27 -Connector_PinHeader_2.54mm -PinHeader_1x27_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x27 2.54mm single row style2 pin1 right -0 -27 -27 -Connector_PinHeader_2.54mm -PinHeader_1x28_P2.54mm_Horizontal -Through hole angled pin header, 1x28, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x28 2.54mm single row -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_1x28_P2.54mm_Vertical -Through hole straight pin header, 1x28, 2.54mm pitch, single row -Through hole pin header THT 1x28 2.54mm single row -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_1x28_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x28 2.54mm single row style1 pin1 left -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_1x28_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x28 2.54mm single row style2 pin1 right -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_1x29_P2.54mm_Horizontal -Through hole angled pin header, 1x29, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x29 2.54mm single row -0 -29 -29 -Connector_PinHeader_2.54mm -PinHeader_1x29_P2.54mm_Vertical -Through hole straight pin header, 1x29, 2.54mm pitch, single row -Through hole pin header THT 1x29 2.54mm single row -0 -29 -29 -Connector_PinHeader_2.54mm -PinHeader_1x29_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x29 2.54mm single row style1 pin1 left -0 -29 -29 -Connector_PinHeader_2.54mm -PinHeader_1x29_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x29 2.54mm single row style2 pin1 right -0 -29 -29 -Connector_PinHeader_2.54mm -PinHeader_1x30_P2.54mm_Horizontal -Through hole angled pin header, 1x30, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x30 2.54mm single row -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_1x30_P2.54mm_Vertical -Through hole straight pin header, 1x30, 2.54mm pitch, single row -Through hole pin header THT 1x30 2.54mm single row -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_1x30_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x30 2.54mm single row style1 pin1 left -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_1x30_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x30 2.54mm single row style2 pin1 right -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_1x31_P2.54mm_Horizontal -Through hole angled pin header, 1x31, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x31 2.54mm single row -0 -31 -31 -Connector_PinHeader_2.54mm -PinHeader_1x31_P2.54mm_Vertical -Through hole straight pin header, 1x31, 2.54mm pitch, single row -Through hole pin header THT 1x31 2.54mm single row -0 -31 -31 -Connector_PinHeader_2.54mm -PinHeader_1x31_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x31 2.54mm single row style1 pin1 left -0 -31 -31 -Connector_PinHeader_2.54mm -PinHeader_1x31_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x31 2.54mm single row style2 pin1 right -0 -31 -31 -Connector_PinHeader_2.54mm -PinHeader_1x32_P2.54mm_Horizontal -Through hole angled pin header, 1x32, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x32 2.54mm single row -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_1x32_P2.54mm_Vertical -Through hole straight pin header, 1x32, 2.54mm pitch, single row -Through hole pin header THT 1x32 2.54mm single row -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_1x32_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x32 2.54mm single row style1 pin1 left -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_1x32_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x32 2.54mm single row style2 pin1 right -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_1x33_P2.54mm_Horizontal -Through hole angled pin header, 1x33, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x33 2.54mm single row -0 -33 -33 -Connector_PinHeader_2.54mm -PinHeader_1x33_P2.54mm_Vertical -Through hole straight pin header, 1x33, 2.54mm pitch, single row -Through hole pin header THT 1x33 2.54mm single row -0 -33 -33 -Connector_PinHeader_2.54mm -PinHeader_1x33_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x33 2.54mm single row style1 pin1 left -0 -33 -33 -Connector_PinHeader_2.54mm -PinHeader_1x33_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x33 2.54mm single row style2 pin1 right -0 -33 -33 -Connector_PinHeader_2.54mm -PinHeader_1x34_P2.54mm_Horizontal -Through hole angled pin header, 1x34, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x34 2.54mm single row -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_1x34_P2.54mm_Vertical -Through hole straight pin header, 1x34, 2.54mm pitch, single row -Through hole pin header THT 1x34 2.54mm single row -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_1x34_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x34 2.54mm single row style1 pin1 left -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_1x34_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x34 2.54mm single row style2 pin1 right -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_1x35_P2.54mm_Horizontal -Through hole angled pin header, 1x35, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x35 2.54mm single row -0 -35 -35 -Connector_PinHeader_2.54mm -PinHeader_1x35_P2.54mm_Vertical -Through hole straight pin header, 1x35, 2.54mm pitch, single row -Through hole pin header THT 1x35 2.54mm single row -0 -35 -35 -Connector_PinHeader_2.54mm -PinHeader_1x35_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x35 2.54mm single row style1 pin1 left -0 -35 -35 -Connector_PinHeader_2.54mm -PinHeader_1x35_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x35 2.54mm single row style2 pin1 right -0 -35 -35 -Connector_PinHeader_2.54mm -PinHeader_1x36_P2.54mm_Horizontal -Through hole angled pin header, 1x36, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x36 2.54mm single row -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_1x36_P2.54mm_Vertical -Through hole straight pin header, 1x36, 2.54mm pitch, single row -Through hole pin header THT 1x36 2.54mm single row -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_1x36_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x36 2.54mm single row style1 pin1 left -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_1x36_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x36 2.54mm single row style2 pin1 right -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_1x37_P2.54mm_Horizontal -Through hole angled pin header, 1x37, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x37 2.54mm single row -0 -37 -37 -Connector_PinHeader_2.54mm -PinHeader_1x37_P2.54mm_Vertical -Through hole straight pin header, 1x37, 2.54mm pitch, single row -Through hole pin header THT 1x37 2.54mm single row -0 -37 -37 -Connector_PinHeader_2.54mm -PinHeader_1x37_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x37 2.54mm single row style1 pin1 left -0 -37 -37 -Connector_PinHeader_2.54mm -PinHeader_1x37_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x37 2.54mm single row style2 pin1 right -0 -37 -37 -Connector_PinHeader_2.54mm -PinHeader_1x38_P2.54mm_Horizontal -Through hole angled pin header, 1x38, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x38 2.54mm single row -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_1x38_P2.54mm_Vertical -Through hole straight pin header, 1x38, 2.54mm pitch, single row -Through hole pin header THT 1x38 2.54mm single row -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_1x38_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x38 2.54mm single row style1 pin1 left -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_1x38_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x38 2.54mm single row style2 pin1 right -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_1x39_P2.54mm_Horizontal -Through hole angled pin header, 1x39, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x39 2.54mm single row -0 -39 -39 -Connector_PinHeader_2.54mm -PinHeader_1x39_P2.54mm_Vertical -Through hole straight pin header, 1x39, 2.54mm pitch, single row -Through hole pin header THT 1x39 2.54mm single row -0 -39 -39 -Connector_PinHeader_2.54mm -PinHeader_1x39_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x39 2.54mm single row style1 pin1 left -0 -39 -39 -Connector_PinHeader_2.54mm -PinHeader_1x39_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x39 2.54mm single row style2 pin1 right -0 -39 -39 -Connector_PinHeader_2.54mm -PinHeader_1x40_P2.54mm_Horizontal -Through hole angled pin header, 1x40, 2.54mm pitch, 6mm pin length, single row -Through hole angled pin header THT 1x40 2.54mm single row -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_1x40_P2.54mm_Vertical -Through hole straight pin header, 1x40, 2.54mm pitch, single row -Through hole pin header THT 1x40 2.54mm single row -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_1x40_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight pin header, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left) -Surface mounted pin header SMD 1x40 2.54mm single row style1 pin1 left -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_1x40_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight pin header, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right) -Surface mounted pin header SMD 1x40 2.54mm single row style2 pin1 right -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_2x01_P2.54mm_Horizontal -Through hole angled pin header, 2x01, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x01 2.54mm double row -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_2x01_P2.54mm_Vertical -Through hole straight pin header, 2x01, 2.54mm pitch, double rows -Through hole pin header THT 2x01 2.54mm double row -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_2x01_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x01, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x01 2.54mm double row -0 -2 -2 -Connector_PinHeader_2.54mm -PinHeader_2x02_P2.54mm_Horizontal -Through hole angled pin header, 2x02, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x02 2.54mm double row -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_2x02_P2.54mm_Vertical -Through hole straight pin header, 2x02, 2.54mm pitch, double rows -Through hole pin header THT 2x02 2.54mm double row -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_2x02_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x02, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x02 2.54mm double row -0 -4 -4 -Connector_PinHeader_2.54mm -PinHeader_2x03_P2.54mm_Horizontal -Through hole angled pin header, 2x03, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x03 2.54mm double row -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_2x03_P2.54mm_Vertical -Through hole straight pin header, 2x03, 2.54mm pitch, double rows -Through hole pin header THT 2x03 2.54mm double row -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_2x03_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x03, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x03 2.54mm double row -0 -6 -6 -Connector_PinHeader_2.54mm -PinHeader_2x04_P2.54mm_Horizontal -Through hole angled pin header, 2x04, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x04 2.54mm double row -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_2x04_P2.54mm_Vertical -Through hole straight pin header, 2x04, 2.54mm pitch, double rows -Through hole pin header THT 2x04 2.54mm double row -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_2x04_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x04, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x04 2.54mm double row -0 -8 -8 -Connector_PinHeader_2.54mm -PinHeader_2x05_P2.54mm_Horizontal -Through hole angled pin header, 2x05, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x05 2.54mm double row -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_2x05_P2.54mm_Vertical -Through hole straight pin header, 2x05, 2.54mm pitch, double rows -Through hole pin header THT 2x05 2.54mm double row -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_2x05_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x05, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x05 2.54mm double row -0 -10 -10 -Connector_PinHeader_2.54mm -PinHeader_2x06_P2.54mm_Horizontal -Through hole angled pin header, 2x06, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x06 2.54mm double row -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_2x06_P2.54mm_Vertical -Through hole straight pin header, 2x06, 2.54mm pitch, double rows -Through hole pin header THT 2x06 2.54mm double row -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_2x06_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x06, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x06 2.54mm double row -0 -12 -12 -Connector_PinHeader_2.54mm -PinHeader_2x07_P2.54mm_Horizontal -Through hole angled pin header, 2x07, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x07 2.54mm double row -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_2x07_P2.54mm_Vertical -Through hole straight pin header, 2x07, 2.54mm pitch, double rows -Through hole pin header THT 2x07 2.54mm double row -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_2x07_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x07, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x07 2.54mm double row -0 -14 -14 -Connector_PinHeader_2.54mm -PinHeader_2x08_P2.54mm_Horizontal -Through hole angled pin header, 2x08, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x08 2.54mm double row -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_2x08_P2.54mm_Vertical -Through hole straight pin header, 2x08, 2.54mm pitch, double rows -Through hole pin header THT 2x08 2.54mm double row -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_2x08_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x08, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x08 2.54mm double row -0 -16 -16 -Connector_PinHeader_2.54mm -PinHeader_2x09_P2.54mm_Horizontal -Through hole angled pin header, 2x09, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x09 2.54mm double row -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_2x09_P2.54mm_Vertical -Through hole straight pin header, 2x09, 2.54mm pitch, double rows -Through hole pin header THT 2x09 2.54mm double row -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_2x09_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x09, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x09 2.54mm double row -0 -18 -18 -Connector_PinHeader_2.54mm -PinHeader_2x10_P2.54mm_Horizontal -Through hole angled pin header, 2x10, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x10 2.54mm double row -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_2x10_P2.54mm_Vertical -Through hole straight pin header, 2x10, 2.54mm pitch, double rows -Through hole pin header THT 2x10 2.54mm double row -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_2x10_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x10, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x10 2.54mm double row -0 -20 -20 -Connector_PinHeader_2.54mm -PinHeader_2x11_P2.54mm_Horizontal -Through hole angled pin header, 2x11, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x11 2.54mm double row -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_2x11_P2.54mm_Vertical -Through hole straight pin header, 2x11, 2.54mm pitch, double rows -Through hole pin header THT 2x11 2.54mm double row -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_2x11_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x11, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x11 2.54mm double row -0 -22 -22 -Connector_PinHeader_2.54mm -PinHeader_2x12_P2.54mm_Horizontal -Through hole angled pin header, 2x12, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x12 2.54mm double row -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_2x12_P2.54mm_Vertical -Through hole straight pin header, 2x12, 2.54mm pitch, double rows -Through hole pin header THT 2x12 2.54mm double row -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_2x12_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x12, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x12 2.54mm double row -0 -24 -24 -Connector_PinHeader_2.54mm -PinHeader_2x13_P2.54mm_Horizontal -Through hole angled pin header, 2x13, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x13 2.54mm double row -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_2x13_P2.54mm_Vertical -Through hole straight pin header, 2x13, 2.54mm pitch, double rows -Through hole pin header THT 2x13 2.54mm double row -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_2x13_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x13, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x13 2.54mm double row -0 -26 -26 -Connector_PinHeader_2.54mm -PinHeader_2x14_P2.54mm_Horizontal -Through hole angled pin header, 2x14, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x14 2.54mm double row -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_2x14_P2.54mm_Vertical -Through hole straight pin header, 2x14, 2.54mm pitch, double rows -Through hole pin header THT 2x14 2.54mm double row -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_2x14_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x14, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x14 2.54mm double row -0 -28 -28 -Connector_PinHeader_2.54mm -PinHeader_2x15_P2.54mm_Horizontal -Through hole angled pin header, 2x15, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x15 2.54mm double row -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_2x15_P2.54mm_Vertical -Through hole straight pin header, 2x15, 2.54mm pitch, double rows -Through hole pin header THT 2x15 2.54mm double row -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_2x15_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x15, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x15 2.54mm double row -0 -30 -30 -Connector_PinHeader_2.54mm -PinHeader_2x16_P2.54mm_Horizontal -Through hole angled pin header, 2x16, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x16 2.54mm double row -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_2x16_P2.54mm_Vertical -Through hole straight pin header, 2x16, 2.54mm pitch, double rows -Through hole pin header THT 2x16 2.54mm double row -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_2x16_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x16, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x16 2.54mm double row -0 -32 -32 -Connector_PinHeader_2.54mm -PinHeader_2x17_P2.54mm_Horizontal -Through hole angled pin header, 2x17, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x17 2.54mm double row -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_2x17_P2.54mm_Vertical -Through hole straight pin header, 2x17, 2.54mm pitch, double rows -Through hole pin header THT 2x17 2.54mm double row -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_2x17_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x17, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x17 2.54mm double row -0 -34 -34 -Connector_PinHeader_2.54mm -PinHeader_2x18_P2.54mm_Horizontal -Through hole angled pin header, 2x18, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x18 2.54mm double row -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_2x18_P2.54mm_Vertical -Through hole straight pin header, 2x18, 2.54mm pitch, double rows -Through hole pin header THT 2x18 2.54mm double row -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_2x18_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x18, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x18 2.54mm double row -0 -36 -36 -Connector_PinHeader_2.54mm -PinHeader_2x19_P2.54mm_Horizontal -Through hole angled pin header, 2x19, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x19 2.54mm double row -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_2x19_P2.54mm_Vertical -Through hole straight pin header, 2x19, 2.54mm pitch, double rows -Through hole pin header THT 2x19 2.54mm double row -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_2x19_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x19, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x19 2.54mm double row -0 -38 -38 -Connector_PinHeader_2.54mm -PinHeader_2x20_P2.54mm_Horizontal -Through hole angled pin header, 2x20, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x20 2.54mm double row -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_2x20_P2.54mm_Vertical -Through hole straight pin header, 2x20, 2.54mm pitch, double rows -Through hole pin header THT 2x20 2.54mm double row -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_2x20_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x20, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x20 2.54mm double row -0 -40 -40 -Connector_PinHeader_2.54mm -PinHeader_2x21_P2.54mm_Horizontal -Through hole angled pin header, 2x21, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x21 2.54mm double row -0 -42 -42 -Connector_PinHeader_2.54mm -PinHeader_2x21_P2.54mm_Vertical -Through hole straight pin header, 2x21, 2.54mm pitch, double rows -Through hole pin header THT 2x21 2.54mm double row -0 -42 -42 -Connector_PinHeader_2.54mm -PinHeader_2x21_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x21, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x21 2.54mm double row -0 -42 -42 -Connector_PinHeader_2.54mm -PinHeader_2x22_P2.54mm_Horizontal -Through hole angled pin header, 2x22, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x22 2.54mm double row -0 -44 -44 -Connector_PinHeader_2.54mm -PinHeader_2x22_P2.54mm_Vertical -Through hole straight pin header, 2x22, 2.54mm pitch, double rows -Through hole pin header THT 2x22 2.54mm double row -0 -44 -44 -Connector_PinHeader_2.54mm -PinHeader_2x22_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x22, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x22 2.54mm double row -0 -44 -44 -Connector_PinHeader_2.54mm -PinHeader_2x23_P2.54mm_Horizontal -Through hole angled pin header, 2x23, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x23 2.54mm double row -0 -46 -46 -Connector_PinHeader_2.54mm -PinHeader_2x23_P2.54mm_Vertical -Through hole straight pin header, 2x23, 2.54mm pitch, double rows -Through hole pin header THT 2x23 2.54mm double row -0 -46 -46 -Connector_PinHeader_2.54mm -PinHeader_2x23_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x23, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x23 2.54mm double row -0 -46 -46 -Connector_PinHeader_2.54mm -PinHeader_2x24_P2.54mm_Horizontal -Through hole angled pin header, 2x24, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x24 2.54mm double row -0 -48 -48 -Connector_PinHeader_2.54mm -PinHeader_2x24_P2.54mm_Vertical -Through hole straight pin header, 2x24, 2.54mm pitch, double rows -Through hole pin header THT 2x24 2.54mm double row -0 -48 -48 -Connector_PinHeader_2.54mm -PinHeader_2x24_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x24, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x24 2.54mm double row -0 -48 -48 -Connector_PinHeader_2.54mm -PinHeader_2x25_P2.54mm_Horizontal -Through hole angled pin header, 2x25, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x25 2.54mm double row -0 -50 -50 -Connector_PinHeader_2.54mm -PinHeader_2x25_P2.54mm_Vertical -Through hole straight pin header, 2x25, 2.54mm pitch, double rows -Through hole pin header THT 2x25 2.54mm double row -0 -50 -50 -Connector_PinHeader_2.54mm -PinHeader_2x25_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x25, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x25 2.54mm double row -0 -50 -50 -Connector_PinHeader_2.54mm -PinHeader_2x26_P2.54mm_Horizontal -Through hole angled pin header, 2x26, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x26 2.54mm double row -0 -52 -52 -Connector_PinHeader_2.54mm -PinHeader_2x26_P2.54mm_Vertical -Through hole straight pin header, 2x26, 2.54mm pitch, double rows -Through hole pin header THT 2x26 2.54mm double row -0 -52 -52 -Connector_PinHeader_2.54mm -PinHeader_2x26_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x26, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x26 2.54mm double row -0 -52 -52 -Connector_PinHeader_2.54mm -PinHeader_2x27_P2.54mm_Horizontal -Through hole angled pin header, 2x27, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x27 2.54mm double row -0 -54 -54 -Connector_PinHeader_2.54mm -PinHeader_2x27_P2.54mm_Vertical -Through hole straight pin header, 2x27, 2.54mm pitch, double rows -Through hole pin header THT 2x27 2.54mm double row -0 -54 -54 -Connector_PinHeader_2.54mm -PinHeader_2x27_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x27, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x27 2.54mm double row -0 -54 -54 -Connector_PinHeader_2.54mm -PinHeader_2x28_P2.54mm_Horizontal -Through hole angled pin header, 2x28, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x28 2.54mm double row -0 -56 -56 -Connector_PinHeader_2.54mm -PinHeader_2x28_P2.54mm_Vertical -Through hole straight pin header, 2x28, 2.54mm pitch, double rows -Through hole pin header THT 2x28 2.54mm double row -0 -56 -56 -Connector_PinHeader_2.54mm -PinHeader_2x28_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x28, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x28 2.54mm double row -0 -56 -56 -Connector_PinHeader_2.54mm -PinHeader_2x29_P2.54mm_Horizontal -Through hole angled pin header, 2x29, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x29 2.54mm double row -0 -58 -58 -Connector_PinHeader_2.54mm -PinHeader_2x29_P2.54mm_Vertical -Through hole straight pin header, 2x29, 2.54mm pitch, double rows -Through hole pin header THT 2x29 2.54mm double row -0 -58 -58 -Connector_PinHeader_2.54mm -PinHeader_2x29_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x29, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x29 2.54mm double row -0 -58 -58 -Connector_PinHeader_2.54mm -PinHeader_2x30_P2.54mm_Horizontal -Through hole angled pin header, 2x30, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x30 2.54mm double row -0 -60 -60 -Connector_PinHeader_2.54mm -PinHeader_2x30_P2.54mm_Vertical -Through hole straight pin header, 2x30, 2.54mm pitch, double rows -Through hole pin header THT 2x30 2.54mm double row -0 -60 -60 -Connector_PinHeader_2.54mm -PinHeader_2x30_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x30, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x30 2.54mm double row -0 -60 -60 -Connector_PinHeader_2.54mm -PinHeader_2x31_P2.54mm_Horizontal -Through hole angled pin header, 2x31, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x31 2.54mm double row -0 -62 -62 -Connector_PinHeader_2.54mm -PinHeader_2x31_P2.54mm_Vertical -Through hole straight pin header, 2x31, 2.54mm pitch, double rows -Through hole pin header THT 2x31 2.54mm double row -0 -62 -62 -Connector_PinHeader_2.54mm -PinHeader_2x31_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x31, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x31 2.54mm double row -0 -62 -62 -Connector_PinHeader_2.54mm -PinHeader_2x32_P2.54mm_Horizontal -Through hole angled pin header, 2x32, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x32 2.54mm double row -0 -64 -64 -Connector_PinHeader_2.54mm -PinHeader_2x32_P2.54mm_Vertical -Through hole straight pin header, 2x32, 2.54mm pitch, double rows -Through hole pin header THT 2x32 2.54mm double row -0 -64 -64 -Connector_PinHeader_2.54mm -PinHeader_2x32_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x32, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x32 2.54mm double row -0 -64 -64 -Connector_PinHeader_2.54mm -PinHeader_2x33_P2.54mm_Horizontal -Through hole angled pin header, 2x33, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x33 2.54mm double row -0 -66 -66 -Connector_PinHeader_2.54mm -PinHeader_2x33_P2.54mm_Vertical -Through hole straight pin header, 2x33, 2.54mm pitch, double rows -Through hole pin header THT 2x33 2.54mm double row -0 -66 -66 -Connector_PinHeader_2.54mm -PinHeader_2x33_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x33, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x33 2.54mm double row -0 -66 -66 -Connector_PinHeader_2.54mm -PinHeader_2x34_P2.54mm_Horizontal -Through hole angled pin header, 2x34, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x34 2.54mm double row -0 -68 -68 -Connector_PinHeader_2.54mm -PinHeader_2x34_P2.54mm_Vertical -Through hole straight pin header, 2x34, 2.54mm pitch, double rows -Through hole pin header THT 2x34 2.54mm double row -0 -68 -68 -Connector_PinHeader_2.54mm -PinHeader_2x34_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x34, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x34 2.54mm double row -0 -68 -68 -Connector_PinHeader_2.54mm -PinHeader_2x35_P2.54mm_Horizontal -Through hole angled pin header, 2x35, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x35 2.54mm double row -0 -70 -70 -Connector_PinHeader_2.54mm -PinHeader_2x35_P2.54mm_Vertical -Through hole straight pin header, 2x35, 2.54mm pitch, double rows -Through hole pin header THT 2x35 2.54mm double row -0 -70 -70 -Connector_PinHeader_2.54mm -PinHeader_2x35_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x35, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x35 2.54mm double row -0 -70 -70 -Connector_PinHeader_2.54mm -PinHeader_2x36_P2.54mm_Horizontal -Through hole angled pin header, 2x36, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x36 2.54mm double row -0 -72 -72 -Connector_PinHeader_2.54mm -PinHeader_2x36_P2.54mm_Vertical -Through hole straight pin header, 2x36, 2.54mm pitch, double rows -Through hole pin header THT 2x36 2.54mm double row -0 -72 -72 -Connector_PinHeader_2.54mm -PinHeader_2x36_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x36, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x36 2.54mm double row -0 -72 -72 -Connector_PinHeader_2.54mm -PinHeader_2x37_P2.54mm_Horizontal -Through hole angled pin header, 2x37, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x37 2.54mm double row -0 -74 -74 -Connector_PinHeader_2.54mm -PinHeader_2x37_P2.54mm_Vertical -Through hole straight pin header, 2x37, 2.54mm pitch, double rows -Through hole pin header THT 2x37 2.54mm double row -0 -74 -74 -Connector_PinHeader_2.54mm -PinHeader_2x37_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x37, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x37 2.54mm double row -0 -74 -74 -Connector_PinHeader_2.54mm -PinHeader_2x38_P2.54mm_Horizontal -Through hole angled pin header, 2x38, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x38 2.54mm double row -0 -76 -76 -Connector_PinHeader_2.54mm -PinHeader_2x38_P2.54mm_Vertical -Through hole straight pin header, 2x38, 2.54mm pitch, double rows -Through hole pin header THT 2x38 2.54mm double row -0 -76 -76 -Connector_PinHeader_2.54mm -PinHeader_2x38_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x38, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x38 2.54mm double row -0 -76 -76 -Connector_PinHeader_2.54mm -PinHeader_2x39_P2.54mm_Horizontal -Through hole angled pin header, 2x39, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x39 2.54mm double row -0 -78 -78 -Connector_PinHeader_2.54mm -PinHeader_2x39_P2.54mm_Vertical -Through hole straight pin header, 2x39, 2.54mm pitch, double rows -Through hole pin header THT 2x39 2.54mm double row -0 -78 -78 -Connector_PinHeader_2.54mm -PinHeader_2x39_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x39, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x39 2.54mm double row -0 -78 -78 -Connector_PinHeader_2.54mm -PinHeader_2x40_P2.54mm_Horizontal -Through hole angled pin header, 2x40, 2.54mm pitch, 6mm pin length, double rows -Through hole angled pin header THT 2x40 2.54mm double row -0 -80 -80 -Connector_PinHeader_2.54mm -PinHeader_2x40_P2.54mm_Vertical -Through hole straight pin header, 2x40, 2.54mm pitch, double rows -Through hole pin header THT 2x40 2.54mm double row -0 -80 -80 -Connector_PinHeader_2.54mm -PinHeader_2x40_P2.54mm_Vertical_SMD -surface-mounted straight pin header, 2x40, 2.54mm pitch, double rows -Surface mounted pin header SMD 2x40 2.54mm double row -0 -80 -80 -Connector_PinSocket_1.00mm -PinSocket_1x02_P1.00mm_Vertical -Through hole straight socket strip, 1x02, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x02 1.00mm single row -0 -2 -2 -Connector_PinSocket_1.00mm -PinSocket_1x02_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x02, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x02 1.00mm single row style1 pin1 left -0 -2 -2 -Connector_PinSocket_1.00mm -PinSocket_1x02_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x02, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x02 1.00mm single row style2 pin1 right -0 -2 -2 -Connector_PinSocket_1.00mm -PinSocket_1x03_P1.00mm_Vertical -Through hole straight socket strip, 1x03, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x03 1.00mm single row -0 -3 -3 -Connector_PinSocket_1.00mm -PinSocket_1x03_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x03, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x03 1.00mm single row style1 pin1 left -0 -3 -3 -Connector_PinSocket_1.00mm -PinSocket_1x03_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x03, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x03 1.00mm single row style2 pin1 right -0 -3 -3 -Connector_PinSocket_1.00mm -PinSocket_1x04_P1.00mm_Vertical -Through hole straight socket strip, 1x04, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x04 1.00mm single row -0 -4 -4 -Connector_PinSocket_1.00mm -PinSocket_1x04_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x04, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x04 1.00mm single row style1 pin1 left -0 -4 -4 -Connector_PinSocket_1.00mm -PinSocket_1x04_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x04, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x04 1.00mm single row style2 pin1 right -0 -4 -4 -Connector_PinSocket_1.00mm -PinSocket_1x05_P1.00mm_Vertical -Through hole straight socket strip, 1x05, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x05 1.00mm single row -0 -5 -5 -Connector_PinSocket_1.00mm -PinSocket_1x05_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x05, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x05 1.00mm single row style1 pin1 left -0 -5 -5 -Connector_PinSocket_1.00mm -PinSocket_1x05_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x05, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x05 1.00mm single row style2 pin1 right -0 -5 -5 -Connector_PinSocket_1.00mm -PinSocket_1x06_P1.00mm_Vertical -Through hole straight socket strip, 1x06, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x06 1.00mm single row -0 -6 -6 -Connector_PinSocket_1.00mm -PinSocket_1x06_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x06, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x06 1.00mm single row style1 pin1 left -0 -6 -6 -Connector_PinSocket_1.00mm -PinSocket_1x06_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x06, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x06 1.00mm single row style2 pin1 right -0 -6 -6 -Connector_PinSocket_1.00mm -PinSocket_1x07_P1.00mm_Vertical -Through hole straight socket strip, 1x07, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x07 1.00mm single row -0 -7 -7 -Connector_PinSocket_1.00mm -PinSocket_1x07_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x07, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x07 1.00mm single row style1 pin1 left -0 -7 -7 -Connector_PinSocket_1.00mm -PinSocket_1x07_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x07, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x07 1.00mm single row style2 pin1 right -0 -7 -7 -Connector_PinSocket_1.00mm -PinSocket_1x08_P1.00mm_Vertical -Through hole straight socket strip, 1x08, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x08 1.00mm single row -0 -8 -8 -Connector_PinSocket_1.00mm -PinSocket_1x08_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x08, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x08 1.00mm single row style1 pin1 left -0 -8 -8 -Connector_PinSocket_1.00mm -PinSocket_1x08_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x08, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x08 1.00mm single row style2 pin1 right -0 -8 -8 -Connector_PinSocket_1.00mm -PinSocket_1x09_P1.00mm_Vertical -Through hole straight socket strip, 1x09, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x09 1.00mm single row -0 -9 -9 -Connector_PinSocket_1.00mm -PinSocket_1x09_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x09, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x09 1.00mm single row style1 pin1 left -0 -9 -9 -Connector_PinSocket_1.00mm -PinSocket_1x09_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x09, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x09 1.00mm single row style2 pin1 right -0 -9 -9 -Connector_PinSocket_1.00mm -PinSocket_1x10_P1.00mm_Vertical -Through hole straight socket strip, 1x10, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x10 1.00mm single row -0 -10 -10 -Connector_PinSocket_1.00mm -PinSocket_1x10_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x10, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x10 1.00mm single row style1 pin1 left -0 -10 -10 -Connector_PinSocket_1.00mm -PinSocket_1x10_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x10, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x10 1.00mm single row style2 pin1 right -0 -10 -10 -Connector_PinSocket_1.00mm -PinSocket_1x11_P1.00mm_Vertical -Through hole straight socket strip, 1x11, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x11 1.00mm single row -0 -11 -11 -Connector_PinSocket_1.00mm -PinSocket_1x11_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x11, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x11 1.00mm single row style1 pin1 left -0 -11 -11 -Connector_PinSocket_1.00mm -PinSocket_1x11_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x11, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x11 1.00mm single row style2 pin1 right -0 -11 -11 -Connector_PinSocket_1.00mm -PinSocket_1x12_P1.00mm_Vertical -Through hole straight socket strip, 1x12, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x12 1.00mm single row -0 -12 -12 -Connector_PinSocket_1.00mm -PinSocket_1x12_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x12, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x12 1.00mm single row style1 pin1 left -0 -12 -12 -Connector_PinSocket_1.00mm -PinSocket_1x12_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x12, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x12 1.00mm single row style2 pin1 right -0 -12 -12 -Connector_PinSocket_1.00mm -PinSocket_1x13_P1.00mm_Vertical -Through hole straight socket strip, 1x13, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x13 1.00mm single row -0 -13 -13 -Connector_PinSocket_1.00mm -PinSocket_1x13_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x13, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x13 1.00mm single row style1 pin1 left -0 -13 -13 -Connector_PinSocket_1.00mm -PinSocket_1x13_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x13, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x13 1.00mm single row style2 pin1 right -0 -13 -13 -Connector_PinSocket_1.00mm -PinSocket_1x14_P1.00mm_Vertical -Through hole straight socket strip, 1x14, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x14 1.00mm single row -0 -14 -14 -Connector_PinSocket_1.00mm -PinSocket_1x14_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x14, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x14 1.00mm single row style1 pin1 left -0 -14 -14 -Connector_PinSocket_1.00mm -PinSocket_1x14_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x14, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x14 1.00mm single row style2 pin1 right -0 -14 -14 -Connector_PinSocket_1.00mm -PinSocket_1x15_P1.00mm_Vertical -Through hole straight socket strip, 1x15, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x15 1.00mm single row -0 -15 -15 -Connector_PinSocket_1.00mm -PinSocket_1x15_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x15, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x15 1.00mm single row style1 pin1 left -0 -15 -15 -Connector_PinSocket_1.00mm -PinSocket_1x15_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x15, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x15 1.00mm single row style2 pin1 right -0 -15 -15 -Connector_PinSocket_1.00mm -PinSocket_1x16_P1.00mm_Vertical -Through hole straight socket strip, 1x16, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x16 1.00mm single row -0 -16 -16 -Connector_PinSocket_1.00mm -PinSocket_1x16_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x16, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x16 1.00mm single row style1 pin1 left -0 -16 -16 -Connector_PinSocket_1.00mm -PinSocket_1x16_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x16, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x16 1.00mm single row style2 pin1 right -0 -16 -16 -Connector_PinSocket_1.00mm -PinSocket_1x17_P1.00mm_Vertical -Through hole straight socket strip, 1x17, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x17 1.00mm single row -0 -17 -17 -Connector_PinSocket_1.00mm -PinSocket_1x17_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x17, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x17 1.00mm single row style1 pin1 left -0 -17 -17 -Connector_PinSocket_1.00mm -PinSocket_1x17_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x17, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x17 1.00mm single row style2 pin1 right -0 -17 -17 -Connector_PinSocket_1.00mm -PinSocket_1x18_P1.00mm_Vertical -Through hole straight socket strip, 1x18, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x18 1.00mm single row -0 -18 -18 -Connector_PinSocket_1.00mm -PinSocket_1x18_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x18, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x18 1.00mm single row style1 pin1 left -0 -18 -18 -Connector_PinSocket_1.00mm -PinSocket_1x18_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x18, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x18 1.00mm single row style2 pin1 right -0 -18 -18 -Connector_PinSocket_1.00mm -PinSocket_1x19_P1.00mm_Vertical -Through hole straight socket strip, 1x19, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x19 1.00mm single row -0 -19 -19 -Connector_PinSocket_1.00mm -PinSocket_1x19_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x19, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x19 1.00mm single row style1 pin1 left -0 -19 -19 -Connector_PinSocket_1.00mm -PinSocket_1x19_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x19, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x19 1.00mm single row style2 pin1 right -0 -19 -19 -Connector_PinSocket_1.00mm -PinSocket_1x20_P1.00mm_Vertical -Through hole straight socket strip, 1x20, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x20 1.00mm single row -0 -20 -20 -Connector_PinSocket_1.00mm -PinSocket_1x20_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x20, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x20 1.00mm single row style1 pin1 left -0 -20 -20 -Connector_PinSocket_1.00mm -PinSocket_1x20_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x20, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x20 1.00mm single row style2 pin1 right -0 -20 -20 -Connector_PinSocket_1.00mm -PinSocket_1x21_P1.00mm_Vertical -Through hole straight socket strip, 1x21, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x21 1.00mm single row -0 -21 -21 -Connector_PinSocket_1.00mm -PinSocket_1x21_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x21, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x21 1.00mm single row style1 pin1 left -0 -21 -21 -Connector_PinSocket_1.00mm -PinSocket_1x21_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x21, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x21 1.00mm single row style2 pin1 right -0 -21 -21 -Connector_PinSocket_1.00mm -PinSocket_1x22_P1.00mm_Vertical -Through hole straight socket strip, 1x22, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x22 1.00mm single row -0 -22 -22 -Connector_PinSocket_1.00mm -PinSocket_1x22_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x22, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x22 1.00mm single row style1 pin1 left -0 -22 -22 -Connector_PinSocket_1.00mm -PinSocket_1x22_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x22, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x22 1.00mm single row style2 pin1 right -0 -22 -22 -Connector_PinSocket_1.00mm -PinSocket_1x23_P1.00mm_Vertical -Through hole straight socket strip, 1x23, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x23 1.00mm single row -0 -23 -23 -Connector_PinSocket_1.00mm -PinSocket_1x23_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x23, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x23 1.00mm single row style1 pin1 left -0 -23 -23 -Connector_PinSocket_1.00mm -PinSocket_1x23_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x23, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x23 1.00mm single row style2 pin1 right -0 -23 -23 -Connector_PinSocket_1.00mm -PinSocket_1x24_P1.00mm_Vertical -Through hole straight socket strip, 1x24, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x24 1.00mm single row -0 -24 -24 -Connector_PinSocket_1.00mm -PinSocket_1x24_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x24, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x24 1.00mm single row style1 pin1 left -0 -24 -24 -Connector_PinSocket_1.00mm -PinSocket_1x24_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x24, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x24 1.00mm single row style2 pin1 right -0 -24 -24 -Connector_PinSocket_1.00mm -PinSocket_1x25_P1.00mm_Vertical -Through hole straight socket strip, 1x25, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x25 1.00mm single row -0 -25 -25 -Connector_PinSocket_1.00mm -PinSocket_1x25_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x25, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x25 1.00mm single row style1 pin1 left -0 -25 -25 -Connector_PinSocket_1.00mm -PinSocket_1x25_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x25, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x25 1.00mm single row style2 pin1 right -0 -25 -25 -Connector_PinSocket_1.00mm -PinSocket_1x26_P1.00mm_Vertical -Through hole straight socket strip, 1x26, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x26 1.00mm single row -0 -26 -26 -Connector_PinSocket_1.00mm -PinSocket_1x26_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x26, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x26 1.00mm single row style1 pin1 left -0 -26 -26 -Connector_PinSocket_1.00mm -PinSocket_1x26_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x26, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x26 1.00mm single row style2 pin1 right -0 -26 -26 -Connector_PinSocket_1.00mm -PinSocket_1x27_P1.00mm_Vertical -Through hole straight socket strip, 1x27, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x27 1.00mm single row -0 -27 -27 -Connector_PinSocket_1.00mm -PinSocket_1x27_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x27, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x27 1.00mm single row style1 pin1 left -0 -27 -27 -Connector_PinSocket_1.00mm -PinSocket_1x27_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x27, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x27 1.00mm single row style2 pin1 right -0 -27 -27 -Connector_PinSocket_1.00mm -PinSocket_1x28_P1.00mm_Vertical -Through hole straight socket strip, 1x28, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x28 1.00mm single row -0 -28 -28 -Connector_PinSocket_1.00mm -PinSocket_1x28_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x28, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x28 1.00mm single row style1 pin1 left -0 -28 -28 -Connector_PinSocket_1.00mm -PinSocket_1x28_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x28, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x28 1.00mm single row style2 pin1 right -0 -28 -28 -Connector_PinSocket_1.00mm -PinSocket_1x29_P1.00mm_Vertical -Through hole straight socket strip, 1x29, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x29 1.00mm single row -0 -29 -29 -Connector_PinSocket_1.00mm -PinSocket_1x29_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x29, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x29 1.00mm single row style1 pin1 left -0 -29 -29 -Connector_PinSocket_1.00mm -PinSocket_1x29_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x29, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x29 1.00mm single row style2 pin1 right -0 -29 -29 -Connector_PinSocket_1.00mm -PinSocket_1x30_P1.00mm_Vertical -Through hole straight socket strip, 1x30, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x30 1.00mm single row -0 -30 -30 -Connector_PinSocket_1.00mm -PinSocket_1x30_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x30, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x30 1.00mm single row style1 pin1 left -0 -30 -30 -Connector_PinSocket_1.00mm -PinSocket_1x30_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x30, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x30 1.00mm single row style2 pin1 right -0 -30 -30 -Connector_PinSocket_1.00mm -PinSocket_1x31_P1.00mm_Vertical -Through hole straight socket strip, 1x31, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x31 1.00mm single row -0 -31 -31 -Connector_PinSocket_1.00mm -PinSocket_1x31_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x31, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x31 1.00mm single row style1 pin1 left -0 -31 -31 -Connector_PinSocket_1.00mm -PinSocket_1x31_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x31, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x31 1.00mm single row style2 pin1 right -0 -31 -31 -Connector_PinSocket_1.00mm -PinSocket_1x32_P1.00mm_Vertical -Through hole straight socket strip, 1x32, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x32 1.00mm single row -0 -32 -32 -Connector_PinSocket_1.00mm -PinSocket_1x32_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x32, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x32 1.00mm single row style1 pin1 left -0 -32 -32 -Connector_PinSocket_1.00mm -PinSocket_1x32_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x32, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x32 1.00mm single row style2 pin1 right -0 -32 -32 -Connector_PinSocket_1.00mm -PinSocket_1x33_P1.00mm_Vertical -Through hole straight socket strip, 1x33, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x33 1.00mm single row -0 -33 -33 -Connector_PinSocket_1.00mm -PinSocket_1x33_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x33, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x33 1.00mm single row style1 pin1 left -0 -33 -33 -Connector_PinSocket_1.00mm -PinSocket_1x33_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x33, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x33 1.00mm single row style2 pin1 right -0 -33 -33 -Connector_PinSocket_1.00mm -PinSocket_1x34_P1.00mm_Vertical -Through hole straight socket strip, 1x34, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x34 1.00mm single row -0 -34 -34 -Connector_PinSocket_1.00mm -PinSocket_1x34_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x34, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x34 1.00mm single row style1 pin1 left -0 -34 -34 -Connector_PinSocket_1.00mm -PinSocket_1x34_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x34, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x34 1.00mm single row style2 pin1 right -0 -34 -34 -Connector_PinSocket_1.00mm -PinSocket_1x35_P1.00mm_Vertical -Through hole straight socket strip, 1x35, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x35 1.00mm single row -0 -35 -35 -Connector_PinSocket_1.00mm -PinSocket_1x35_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x35, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x35 1.00mm single row style1 pin1 left -0 -35 -35 -Connector_PinSocket_1.00mm -PinSocket_1x35_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x35, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x35 1.00mm single row style2 pin1 right -0 -35 -35 -Connector_PinSocket_1.00mm -PinSocket_1x36_P1.00mm_Vertical -Through hole straight socket strip, 1x36, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x36 1.00mm single row -0 -36 -36 -Connector_PinSocket_1.00mm -PinSocket_1x36_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x36, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x36 1.00mm single row style1 pin1 left -0 -36 -36 -Connector_PinSocket_1.00mm -PinSocket_1x36_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x36, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x36 1.00mm single row style2 pin1 right -0 -36 -36 -Connector_PinSocket_1.00mm -PinSocket_1x37_P1.00mm_Vertical -Through hole straight socket strip, 1x37, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x37 1.00mm single row -0 -37 -37 -Connector_PinSocket_1.00mm -PinSocket_1x37_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x37, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x37 1.00mm single row style1 pin1 left -0 -37 -37 -Connector_PinSocket_1.00mm -PinSocket_1x37_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x37, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x37 1.00mm single row style2 pin1 right -0 -37 -37 -Connector_PinSocket_1.00mm -PinSocket_1x38_P1.00mm_Vertical -Through hole straight socket strip, 1x38, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x38 1.00mm single row -0 -38 -38 -Connector_PinSocket_1.00mm -PinSocket_1x38_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x38, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x38 1.00mm single row style1 pin1 left -0 -38 -38 -Connector_PinSocket_1.00mm -PinSocket_1x38_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x38, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x38 1.00mm single row style2 pin1 right -0 -38 -38 -Connector_PinSocket_1.00mm -PinSocket_1x39_P1.00mm_Vertical -Through hole straight socket strip, 1x39, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x39 1.00mm single row -0 -39 -39 -Connector_PinSocket_1.00mm -PinSocket_1x39_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x39, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x39 1.00mm single row style1 pin1 left -0 -39 -39 -Connector_PinSocket_1.00mm -PinSocket_1x39_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x39, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x39 1.00mm single row style2 pin1 right -0 -39 -39 -Connector_PinSocket_1.00mm -PinSocket_1x40_P1.00mm_Vertical -Through hole straight socket strip, 1x40, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated -Through hole socket strip THT 1x40 1.00mm single row -0 -40 -40 -Connector_PinSocket_1.00mm -PinSocket_1x40_P1.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x40, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x40 1.00mm single row style1 pin1 left -0 -40 -40 -Connector_PinSocket_1.00mm -PinSocket_1x40_P1.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x40, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated -Surface mounted socket strip SMD 1x40 1.00mm single row style2 pin1 right -0 -40 -40 -Connector_PinSocket_1.00mm -PinSocket_2x02_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x02, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x02 1.00mm double row -0 -4 -4 -Connector_PinSocket_1.00mm -PinSocket_2x03_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x03, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x03 1.00mm double row -0 -6 -6 -Connector_PinSocket_1.00mm -PinSocket_2x04_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x04, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x04 1.00mm double row -0 -8 -8 -Connector_PinSocket_1.00mm -PinSocket_2x05_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x05, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x05 1.00mm double row -0 -10 -10 -Connector_PinSocket_1.00mm -PinSocket_2x06_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x06, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x06 1.00mm double row -0 -12 -12 -Connector_PinSocket_1.00mm -PinSocket_2x07_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x07, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x07 1.00mm double row -0 -14 -14 -Connector_PinSocket_1.00mm -PinSocket_2x08_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x08, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x08 1.00mm double row -0 -16 -16 -Connector_PinSocket_1.00mm -PinSocket_2x09_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x09, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x09 1.00mm double row -0 -18 -18 -Connector_PinSocket_1.00mm -PinSocket_2x10_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x10, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x10 1.00mm double row -0 -20 -20 -Connector_PinSocket_1.00mm -PinSocket_2x11_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x11, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x11 1.00mm double row -0 -22 -22 -Connector_PinSocket_1.00mm -PinSocket_2x12_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x12, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x12 1.00mm double row -0 -24 -24 -Connector_PinSocket_1.00mm -PinSocket_2x13_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x13, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x13 1.00mm double row -0 -26 -26 -Connector_PinSocket_1.00mm -PinSocket_2x14_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x14, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x14 1.00mm double row -0 -28 -28 -Connector_PinSocket_1.00mm -PinSocket_2x15_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x15, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x15 1.00mm double row -0 -30 -30 -Connector_PinSocket_1.00mm -PinSocket_2x16_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x16, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x16 1.00mm double row -0 -32 -32 -Connector_PinSocket_1.00mm -PinSocket_2x17_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x17, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x17 1.00mm double row -0 -34 -34 -Connector_PinSocket_1.00mm -PinSocket_2x18_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x18, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x18 1.00mm double row -0 -36 -36 -Connector_PinSocket_1.00mm -PinSocket_2x19_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x19, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x19 1.00mm double row -0 -38 -38 -Connector_PinSocket_1.00mm -PinSocket_2x20_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x20, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x20 1.00mm double row -0 -40 -40 -Connector_PinSocket_1.00mm -PinSocket_2x21_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x21, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x21 1.00mm double row -0 -42 -42 -Connector_PinSocket_1.00mm -PinSocket_2x22_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x22, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x22 1.00mm double row -0 -44 -44 -Connector_PinSocket_1.00mm -PinSocket_2x23_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x23, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x23 1.00mm double row -0 -46 -46 -Connector_PinSocket_1.00mm -PinSocket_2x24_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x24, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x24 1.00mm double row -0 -48 -48 -Connector_PinSocket_1.00mm -PinSocket_2x25_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x25, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x25 1.00mm double row -0 -50 -50 -Connector_PinSocket_1.00mm -PinSocket_2x26_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x26, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x26 1.00mm double row -0 -52 -52 -Connector_PinSocket_1.00mm -PinSocket_2x27_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x27, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x27 1.00mm double row -0 -54 -54 -Connector_PinSocket_1.00mm -PinSocket_2x28_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x28, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x28 1.00mm double row -0 -56 -56 -Connector_PinSocket_1.00mm -PinSocket_2x29_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x29, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x29 1.00mm double row -0 -58 -58 -Connector_PinSocket_1.00mm -PinSocket_2x30_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x30, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x30 1.00mm double row -0 -60 -60 -Connector_PinSocket_1.00mm -PinSocket_2x31_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x31, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x31 1.00mm double row -0 -62 -62 -Connector_PinSocket_1.00mm -PinSocket_2x32_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x32, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x32 1.00mm double row -0 -64 -64 -Connector_PinSocket_1.00mm -PinSocket_2x33_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x33, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x33 1.00mm double row -0 -66 -66 -Connector_PinSocket_1.00mm -PinSocket_2x34_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x34, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x34 1.00mm double row -0 -68 -68 -Connector_PinSocket_1.00mm -PinSocket_2x35_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x35, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x35 1.00mm double row -0 -70 -70 -Connector_PinSocket_1.00mm -PinSocket_2x36_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x36, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x36 1.00mm double row -0 -72 -72 -Connector_PinSocket_1.00mm -PinSocket_2x37_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x37, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x37 1.00mm double row -0 -74 -74 -Connector_PinSocket_1.00mm -PinSocket_2x38_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x38, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x38 1.00mm double row -0 -76 -76 -Connector_PinSocket_1.00mm -PinSocket_2x39_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x39, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x39 1.00mm double row -0 -78 -78 -Connector_PinSocket_1.00mm -PinSocket_2x40_P1.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x40, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated -Surface mounted socket strip SMD 2x40 1.00mm double row -0 -80 -80 -Connector_PinSocket_1.27mm -PinSocket_1x01_P1.27mm_Vertical -Through hole straight socket strip, 1x01, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x01 1.27mm single row -0 -1 -1 -Connector_PinSocket_1.27mm -PinSocket_1x02_P1.27mm_Vertical -Through hole straight socket strip, 1x02, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x02 1.27mm single row -0 -2 -2 -Connector_PinSocket_1.27mm -PinSocket_1x02_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x02, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x02 1.27mm single row style1 pin1 left -0 -2 -2 -Connector_PinSocket_1.27mm -PinSocket_1x02_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x02, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x02 1.27mm single row style2 pin1 right -0 -2 -2 -Connector_PinSocket_1.27mm -PinSocket_1x03_P1.27mm_Vertical -Through hole straight socket strip, 1x03, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x03 1.27mm single row -0 -3 -3 -Connector_PinSocket_1.27mm -PinSocket_1x03_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x03, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x03 1.27mm single row style1 pin1 left -0 -3 -3 -Connector_PinSocket_1.27mm -PinSocket_1x03_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x03, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x03 1.27mm single row style2 pin1 right -0 -3 -3 -Connector_PinSocket_1.27mm -PinSocket_1x04_P1.27mm_Vertical -Through hole straight socket strip, 1x04, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x04 1.27mm single row -0 -4 -4 -Connector_PinSocket_1.27mm -PinSocket_1x04_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x04, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x04 1.27mm single row style1 pin1 left -0 -4 -4 -Connector_PinSocket_1.27mm -PinSocket_1x04_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x04, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x04 1.27mm single row style2 pin1 right -0 -4 -4 -Connector_PinSocket_1.27mm -PinSocket_1x05_P1.27mm_Vertical -Through hole straight socket strip, 1x05, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x05 1.27mm single row -0 -5 -5 -Connector_PinSocket_1.27mm -PinSocket_1x05_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x05, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x05 1.27mm single row style1 pin1 left -0 -5 -5 -Connector_PinSocket_1.27mm -PinSocket_1x05_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x05, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x05 1.27mm single row style2 pin1 right -0 -5 -5 -Connector_PinSocket_1.27mm -PinSocket_1x06_P1.27mm_Vertical -Through hole straight socket strip, 1x06, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x06 1.27mm single row -0 -6 -6 -Connector_PinSocket_1.27mm -PinSocket_1x06_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x06, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x06 1.27mm single row style1 pin1 left -0 -6 -6 -Connector_PinSocket_1.27mm -PinSocket_1x06_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x06, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x06 1.27mm single row style2 pin1 right -0 -6 -6 -Connector_PinSocket_1.27mm -PinSocket_1x07_P1.27mm_Vertical -Through hole straight socket strip, 1x07, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x07 1.27mm single row -0 -7 -7 -Connector_PinSocket_1.27mm -PinSocket_1x07_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x07, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x07 1.27mm single row style1 pin1 left -0 -7 -7 -Connector_PinSocket_1.27mm -PinSocket_1x07_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x07, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x07 1.27mm single row style2 pin1 right -0 -7 -7 -Connector_PinSocket_1.27mm -PinSocket_1x08_P1.27mm_Vertical -Through hole straight socket strip, 1x08, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x08 1.27mm single row -0 -8 -8 -Connector_PinSocket_1.27mm -PinSocket_1x08_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x08, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x08 1.27mm single row style1 pin1 left -0 -8 -8 -Connector_PinSocket_1.27mm -PinSocket_1x08_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x08, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x08 1.27mm single row style2 pin1 right -0 -8 -8 -Connector_PinSocket_1.27mm -PinSocket_1x09_P1.27mm_Vertical -Through hole straight socket strip, 1x09, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x09 1.27mm single row -0 -9 -9 -Connector_PinSocket_1.27mm -PinSocket_1x09_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x09, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x09 1.27mm single row style1 pin1 left -0 -9 -9 -Connector_PinSocket_1.27mm -PinSocket_1x09_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x09, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x09 1.27mm single row style2 pin1 right -0 -9 -9 -Connector_PinSocket_1.27mm -PinSocket_1x10_P1.27mm_Vertical -Through hole straight socket strip, 1x10, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x10 1.27mm single row -0 -10 -10 -Connector_PinSocket_1.27mm -PinSocket_1x10_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x10, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x10 1.27mm single row style1 pin1 left -0 -10 -10 -Connector_PinSocket_1.27mm -PinSocket_1x10_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x10, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x10 1.27mm single row style2 pin1 right -0 -10 -10 -Connector_PinSocket_1.27mm -PinSocket_1x11_P1.27mm_Vertical -Through hole straight socket strip, 1x11, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x11 1.27mm single row -0 -11 -11 -Connector_PinSocket_1.27mm -PinSocket_1x11_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x11, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x11 1.27mm single row style1 pin1 left -0 -11 -11 -Connector_PinSocket_1.27mm -PinSocket_1x11_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x11, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x11 1.27mm single row style2 pin1 right -0 -11 -11 -Connector_PinSocket_1.27mm -PinSocket_1x12_P1.27mm_Vertical -Through hole straight socket strip, 1x12, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x12 1.27mm single row -0 -12 -12 -Connector_PinSocket_1.27mm -PinSocket_1x12_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x12, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x12 1.27mm single row style1 pin1 left -0 -12 -12 -Connector_PinSocket_1.27mm -PinSocket_1x12_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x12, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x12 1.27mm single row style2 pin1 right -0 -12 -12 -Connector_PinSocket_1.27mm -PinSocket_1x13_P1.27mm_Vertical -Through hole straight socket strip, 1x13, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x13 1.27mm single row -0 -13 -13 -Connector_PinSocket_1.27mm -PinSocket_1x13_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x13, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x13 1.27mm single row style1 pin1 left -0 -13 -13 -Connector_PinSocket_1.27mm -PinSocket_1x13_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x13, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x13 1.27mm single row style2 pin1 right -0 -13 -13 -Connector_PinSocket_1.27mm -PinSocket_1x14_P1.27mm_Vertical -Through hole straight socket strip, 1x14, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x14 1.27mm single row -0 -14 -14 -Connector_PinSocket_1.27mm -PinSocket_1x14_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x14, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x14 1.27mm single row style1 pin1 left -0 -14 -14 -Connector_PinSocket_1.27mm -PinSocket_1x14_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x14, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x14 1.27mm single row style2 pin1 right -0 -14 -14 -Connector_PinSocket_1.27mm -PinSocket_1x15_P1.27mm_Vertical -Through hole straight socket strip, 1x15, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x15 1.27mm single row -0 -15 -15 -Connector_PinSocket_1.27mm -PinSocket_1x15_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x15, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x15 1.27mm single row style1 pin1 left -0 -15 -15 -Connector_PinSocket_1.27mm -PinSocket_1x15_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x15, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x15 1.27mm single row style2 pin1 right -0 -15 -15 -Connector_PinSocket_1.27mm -PinSocket_1x16_P1.27mm_Vertical -Through hole straight socket strip, 1x16, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x16 1.27mm single row -0 -16 -16 -Connector_PinSocket_1.27mm -PinSocket_1x16_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x16, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x16 1.27mm single row style1 pin1 left -0 -16 -16 -Connector_PinSocket_1.27mm -PinSocket_1x16_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x16, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x16 1.27mm single row style2 pin1 right -0 -16 -16 -Connector_PinSocket_1.27mm -PinSocket_1x17_P1.27mm_Vertical -Through hole straight socket strip, 1x17, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x17 1.27mm single row -0 -17 -17 -Connector_PinSocket_1.27mm -PinSocket_1x17_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x17, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x17 1.27mm single row style1 pin1 left -0 -17 -17 -Connector_PinSocket_1.27mm -PinSocket_1x17_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x17, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x17 1.27mm single row style2 pin1 right -0 -17 -17 -Connector_PinSocket_1.27mm -PinSocket_1x18_P1.27mm_Vertical -Through hole straight socket strip, 1x18, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x18 1.27mm single row -0 -18 -18 -Connector_PinSocket_1.27mm -PinSocket_1x18_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x18, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x18 1.27mm single row style1 pin1 left -0 -18 -18 -Connector_PinSocket_1.27mm -PinSocket_1x18_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x18, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x18 1.27mm single row style2 pin1 right -0 -18 -18 -Connector_PinSocket_1.27mm -PinSocket_1x19_P1.27mm_Vertical -Through hole straight socket strip, 1x19, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x19 1.27mm single row -0 -19 -19 -Connector_PinSocket_1.27mm -PinSocket_1x19_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x19, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x19 1.27mm single row style1 pin1 left -0 -19 -19 -Connector_PinSocket_1.27mm -PinSocket_1x19_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x19, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x19 1.27mm single row style2 pin1 right -0 -19 -19 -Connector_PinSocket_1.27mm -PinSocket_1x20_P1.27mm_Vertical -Through hole straight socket strip, 1x20, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x20 1.27mm single row -0 -20 -20 -Connector_PinSocket_1.27mm -PinSocket_1x20_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x20, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x20 1.27mm single row style1 pin1 left -0 -20 -20 -Connector_PinSocket_1.27mm -PinSocket_1x20_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x20, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x20 1.27mm single row style2 pin1 right -0 -20 -20 -Connector_PinSocket_1.27mm -PinSocket_1x21_P1.27mm_Vertical -Through hole straight socket strip, 1x21, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x21 1.27mm single row -0 -21 -21 -Connector_PinSocket_1.27mm -PinSocket_1x21_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x21, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x21 1.27mm single row style1 pin1 left -0 -21 -21 -Connector_PinSocket_1.27mm -PinSocket_1x21_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x21, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x21 1.27mm single row style2 pin1 right -0 -21 -21 -Connector_PinSocket_1.27mm -PinSocket_1x22_P1.27mm_Vertical -Through hole straight socket strip, 1x22, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x22 1.27mm single row -0 -22 -22 -Connector_PinSocket_1.27mm -PinSocket_1x22_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x22, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x22 1.27mm single row style1 pin1 left -0 -22 -22 -Connector_PinSocket_1.27mm -PinSocket_1x22_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x22, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x22 1.27mm single row style2 pin1 right -0 -22 -22 -Connector_PinSocket_1.27mm -PinSocket_1x23_P1.27mm_Vertical -Through hole straight socket strip, 1x23, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x23 1.27mm single row -0 -23 -23 -Connector_PinSocket_1.27mm -PinSocket_1x23_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x23, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x23 1.27mm single row style1 pin1 left -0 -23 -23 -Connector_PinSocket_1.27mm -PinSocket_1x23_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x23, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x23 1.27mm single row style2 pin1 right -0 -23 -23 -Connector_PinSocket_1.27mm -PinSocket_1x24_P1.27mm_Vertical -Through hole straight socket strip, 1x24, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x24 1.27mm single row -0 -24 -24 -Connector_PinSocket_1.27mm -PinSocket_1x24_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x24, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x24 1.27mm single row style1 pin1 left -0 -24 -24 -Connector_PinSocket_1.27mm -PinSocket_1x24_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x24, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x24 1.27mm single row style2 pin1 right -0 -24 -24 -Connector_PinSocket_1.27mm -PinSocket_1x25_P1.27mm_Vertical -Through hole straight socket strip, 1x25, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x25 1.27mm single row -0 -25 -25 -Connector_PinSocket_1.27mm -PinSocket_1x25_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x25, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x25 1.27mm single row style1 pin1 left -0 -25 -25 -Connector_PinSocket_1.27mm -PinSocket_1x25_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x25, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x25 1.27mm single row style2 pin1 right -0 -25 -25 -Connector_PinSocket_1.27mm -PinSocket_1x26_P1.27mm_Vertical -Through hole straight socket strip, 1x26, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x26 1.27mm single row -0 -26 -26 -Connector_PinSocket_1.27mm -PinSocket_1x26_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x26, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x26 1.27mm single row style1 pin1 left -0 -26 -26 -Connector_PinSocket_1.27mm -PinSocket_1x26_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x26, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x26 1.27mm single row style2 pin1 right -0 -26 -26 -Connector_PinSocket_1.27mm -PinSocket_1x27_P1.27mm_Vertical -Through hole straight socket strip, 1x27, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x27 1.27mm single row -0 -27 -27 -Connector_PinSocket_1.27mm -PinSocket_1x27_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x27, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x27 1.27mm single row style1 pin1 left -0 -27 -27 -Connector_PinSocket_1.27mm -PinSocket_1x27_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x27, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x27 1.27mm single row style2 pin1 right -0 -27 -27 -Connector_PinSocket_1.27mm -PinSocket_1x28_P1.27mm_Vertical -Through hole straight socket strip, 1x28, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x28 1.27mm single row -0 -28 -28 -Connector_PinSocket_1.27mm -PinSocket_1x28_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x28, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x28 1.27mm single row style1 pin1 left -0 -28 -28 -Connector_PinSocket_1.27mm -PinSocket_1x28_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x28, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x28 1.27mm single row style2 pin1 right -0 -28 -28 -Connector_PinSocket_1.27mm -PinSocket_1x29_P1.27mm_Vertical -Through hole straight socket strip, 1x29, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x29 1.27mm single row -0 -29 -29 -Connector_PinSocket_1.27mm -PinSocket_1x29_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x29, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x29 1.27mm single row style1 pin1 left -0 -29 -29 -Connector_PinSocket_1.27mm -PinSocket_1x29_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x29, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x29 1.27mm single row style2 pin1 right -0 -29 -29 -Connector_PinSocket_1.27mm -PinSocket_1x30_P1.27mm_Vertical -Through hole straight socket strip, 1x30, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x30 1.27mm single row -0 -30 -30 -Connector_PinSocket_1.27mm -PinSocket_1x30_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x30, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x30 1.27mm single row style1 pin1 left -0 -30 -30 -Connector_PinSocket_1.27mm -PinSocket_1x30_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x30, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x30 1.27mm single row style2 pin1 right -0 -30 -30 -Connector_PinSocket_1.27mm -PinSocket_1x31_P1.27mm_Vertical -Through hole straight socket strip, 1x31, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x31 1.27mm single row -0 -31 -31 -Connector_PinSocket_1.27mm -PinSocket_1x31_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x31, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x31 1.27mm single row style1 pin1 left -0 -31 -31 -Connector_PinSocket_1.27mm -PinSocket_1x31_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x31, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x31 1.27mm single row style2 pin1 right -0 -31 -31 -Connector_PinSocket_1.27mm -PinSocket_1x32_P1.27mm_Vertical -Through hole straight socket strip, 1x32, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x32 1.27mm single row -0 -32 -32 -Connector_PinSocket_1.27mm -PinSocket_1x32_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x32, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x32 1.27mm single row style1 pin1 left -0 -32 -32 -Connector_PinSocket_1.27mm -PinSocket_1x32_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x32, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x32 1.27mm single row style2 pin1 right -0 -32 -32 -Connector_PinSocket_1.27mm -PinSocket_1x33_P1.27mm_Vertical -Through hole straight socket strip, 1x33, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x33 1.27mm single row -0 -33 -33 -Connector_PinSocket_1.27mm -PinSocket_1x33_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x33, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x33 1.27mm single row style1 pin1 left -0 -33 -33 -Connector_PinSocket_1.27mm -PinSocket_1x33_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x33, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x33 1.27mm single row style2 pin1 right -0 -33 -33 -Connector_PinSocket_1.27mm -PinSocket_1x34_P1.27mm_Vertical -Through hole straight socket strip, 1x34, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x34 1.27mm single row -0 -34 -34 -Connector_PinSocket_1.27mm -PinSocket_1x34_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x34, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x34 1.27mm single row style1 pin1 left -0 -34 -34 -Connector_PinSocket_1.27mm -PinSocket_1x34_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x34, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x34 1.27mm single row style2 pin1 right -0 -34 -34 -Connector_PinSocket_1.27mm -PinSocket_1x35_P1.27mm_Vertical -Through hole straight socket strip, 1x35, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x35 1.27mm single row -0 -35 -35 -Connector_PinSocket_1.27mm -PinSocket_1x35_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x35, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x35 1.27mm single row style1 pin1 left -0 -35 -35 -Connector_PinSocket_1.27mm -PinSocket_1x35_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x35, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x35 1.27mm single row style2 pin1 right -0 -35 -35 -Connector_PinSocket_1.27mm -PinSocket_1x36_P1.27mm_Vertical -Through hole straight socket strip, 1x36, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x36 1.27mm single row -0 -36 -36 -Connector_PinSocket_1.27mm -PinSocket_1x36_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x36, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x36 1.27mm single row style1 pin1 left -0 -36 -36 -Connector_PinSocket_1.27mm -PinSocket_1x36_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x36, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x36 1.27mm single row style2 pin1 right -0 -36 -36 -Connector_PinSocket_1.27mm -PinSocket_1x37_P1.27mm_Vertical -Through hole straight socket strip, 1x37, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x37 1.27mm single row -0 -37 -37 -Connector_PinSocket_1.27mm -PinSocket_1x37_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x37, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x37 1.27mm single row style1 pin1 left -0 -37 -37 -Connector_PinSocket_1.27mm -PinSocket_1x37_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x37, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x37 1.27mm single row style2 pin1 right -0 -37 -37 -Connector_PinSocket_1.27mm -PinSocket_1x38_P1.27mm_Vertical -Through hole straight socket strip, 1x38, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x38 1.27mm single row -0 -38 -38 -Connector_PinSocket_1.27mm -PinSocket_1x38_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x38, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x38 1.27mm single row style1 pin1 left -0 -38 -38 -Connector_PinSocket_1.27mm -PinSocket_1x38_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x38, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x38 1.27mm single row style2 pin1 right -0 -38 -38 -Connector_PinSocket_1.27mm -PinSocket_1x39_P1.27mm_Vertical -Through hole straight socket strip, 1x39, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x39 1.27mm single row -0 -39 -39 -Connector_PinSocket_1.27mm -PinSocket_1x39_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x39, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x39 1.27mm single row style1 pin1 left -0 -39 -39 -Connector_PinSocket_1.27mm -PinSocket_1x39_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x39, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x39 1.27mm single row style2 pin1 right -0 -39 -39 -Connector_PinSocket_1.27mm -PinSocket_1x40_P1.27mm_Vertical -Through hole straight socket strip, 1x40, 1.27mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x40 1.27mm single row -0 -40 -40 -Connector_PinSocket_1.27mm -PinSocket_1x40_P1.27mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x40, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x40 1.27mm single row style1 pin1 left -0 -40 -40 -Connector_PinSocket_1.27mm -PinSocket_1x40_P1.27mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x40, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated -Surface mounted socket strip SMD 1x40 1.27mm single row style2 pin1 right -0 -40 -40 -Connector_PinSocket_1.27mm -PinSocket_2x01_P1.27mm_Vertical -Through hole straight socket strip, 2x01, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x01 1.27mm double row -0 -2 -2 -Connector_PinSocket_1.27mm -PinSocket_2x01_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x01, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x01 1.27mm double row -0 -2 -2 -Connector_PinSocket_1.27mm -PinSocket_2x02_P1.27mm_Vertical -Through hole straight socket strip, 2x02, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x02 1.27mm double row -0 -4 -4 -Connector_PinSocket_1.27mm -PinSocket_2x02_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x02, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x02 1.27mm double row -0 -4 -4 -Connector_PinSocket_1.27mm -PinSocket_2x03_P1.27mm_Horizontal -Through hole angled socket strip, 2x03, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x03 1.27mm double row -0 -6 -6 -Connector_PinSocket_1.27mm -PinSocket_2x03_P1.27mm_Vertical -Through hole straight socket strip, 2x03, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x03 1.27mm double row -0 -6 -6 -Connector_PinSocket_1.27mm -PinSocket_2x03_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x03, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x03 1.27mm double row -0 -6 -6 -Connector_PinSocket_1.27mm -PinSocket_2x04_P1.27mm_Horizontal -Through hole angled socket strip, 2x04, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x04 1.27mm double row -0 -8 -8 -Connector_PinSocket_1.27mm -PinSocket_2x04_P1.27mm_Vertical -Through hole straight socket strip, 2x04, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x04 1.27mm double row -0 -8 -8 -Connector_PinSocket_1.27mm -PinSocket_2x04_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x04, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x04 1.27mm double row -0 -8 -8 -Connector_PinSocket_1.27mm -PinSocket_2x05_P1.27mm_Horizontal -Through hole angled socket strip, 2x05, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x05 1.27mm double row -0 -10 -10 -Connector_PinSocket_1.27mm -PinSocket_2x05_P1.27mm_Vertical -Through hole straight socket strip, 2x05, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x05 1.27mm double row -0 -10 -10 -Connector_PinSocket_1.27mm -PinSocket_2x05_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x05, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x05 1.27mm double row -0 -10 -10 -Connector_PinSocket_1.27mm -PinSocket_2x06_P1.27mm_Horizontal -Through hole angled socket strip, 2x06, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x06 1.27mm double row -0 -12 -12 -Connector_PinSocket_1.27mm -PinSocket_2x06_P1.27mm_Vertical -Through hole straight socket strip, 2x06, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x06 1.27mm double row -0 -12 -12 -Connector_PinSocket_1.27mm -PinSocket_2x06_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x06, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x06 1.27mm double row -0 -12 -12 -Connector_PinSocket_1.27mm -PinSocket_2x07_P1.27mm_Horizontal -Through hole angled socket strip, 2x07, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x07 1.27mm double row -0 -14 -14 -Connector_PinSocket_1.27mm -PinSocket_2x07_P1.27mm_Vertical -Through hole straight socket strip, 2x07, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x07 1.27mm double row -0 -14 -14 -Connector_PinSocket_1.27mm -PinSocket_2x07_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x07, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x07 1.27mm double row -0 -14 -14 -Connector_PinSocket_1.27mm -PinSocket_2x08_P1.27mm_Horizontal -Through hole angled socket strip, 2x08, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x08 1.27mm double row -0 -16 -16 -Connector_PinSocket_1.27mm -PinSocket_2x08_P1.27mm_Vertical -Through hole straight socket strip, 2x08, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x08 1.27mm double row -0 -16 -16 -Connector_PinSocket_1.27mm -PinSocket_2x08_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x08, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x08 1.27mm double row -0 -16 -16 -Connector_PinSocket_1.27mm -PinSocket_2x09_P1.27mm_Horizontal -Through hole angled socket strip, 2x09, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x09 1.27mm double row -0 -18 -18 -Connector_PinSocket_1.27mm -PinSocket_2x09_P1.27mm_Vertical -Through hole straight socket strip, 2x09, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x09 1.27mm double row -0 -18 -18 -Connector_PinSocket_1.27mm -PinSocket_2x09_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x09, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x09 1.27mm double row -0 -18 -18 -Connector_PinSocket_1.27mm -PinSocket_2x10_P1.27mm_Horizontal -Through hole angled socket strip, 2x10, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x10 1.27mm double row -0 -20 -20 -Connector_PinSocket_1.27mm -PinSocket_2x10_P1.27mm_Vertical -Through hole straight socket strip, 2x10, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x10 1.27mm double row -0 -20 -20 -Connector_PinSocket_1.27mm -PinSocket_2x10_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x10, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x10 1.27mm double row -0 -20 -20 -Connector_PinSocket_1.27mm -PinSocket_2x11_P1.27mm_Horizontal -Through hole angled socket strip, 2x11, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x11 1.27mm double row -0 -22 -22 -Connector_PinSocket_1.27mm -PinSocket_2x11_P1.27mm_Vertical -Through hole straight socket strip, 2x11, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x11 1.27mm double row -0 -22 -22 -Connector_PinSocket_1.27mm -PinSocket_2x11_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x11, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x11 1.27mm double row -0 -22 -22 -Connector_PinSocket_1.27mm -PinSocket_2x12_P1.27mm_Horizontal -Through hole angled socket strip, 2x12, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x12 1.27mm double row -0 -24 -24 -Connector_PinSocket_1.27mm -PinSocket_2x12_P1.27mm_Vertical -Through hole straight socket strip, 2x12, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x12 1.27mm double row -0 -24 -24 -Connector_PinSocket_1.27mm -PinSocket_2x12_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x12, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x12 1.27mm double row -0 -24 -24 -Connector_PinSocket_1.27mm -PinSocket_2x13_P1.27mm_Horizontal -Through hole angled socket strip, 2x13, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x13 1.27mm double row -0 -26 -26 -Connector_PinSocket_1.27mm -PinSocket_2x13_P1.27mm_Vertical -Through hole straight socket strip, 2x13, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x13 1.27mm double row -0 -26 -26 -Connector_PinSocket_1.27mm -PinSocket_2x13_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x13, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x13 1.27mm double row -0 -26 -26 -Connector_PinSocket_1.27mm -PinSocket_2x14_P1.27mm_Horizontal -Through hole angled socket strip, 2x14, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x14 1.27mm double row -0 -28 -28 -Connector_PinSocket_1.27mm -PinSocket_2x14_P1.27mm_Vertical -Through hole straight socket strip, 2x14, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x14 1.27mm double row -0 -28 -28 -Connector_PinSocket_1.27mm -PinSocket_2x14_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x14, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x14 1.27mm double row -0 -28 -28 -Connector_PinSocket_1.27mm -PinSocket_2x15_P1.27mm_Horizontal -Through hole angled socket strip, 2x15, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x15 1.27mm double row -0 -30 -30 -Connector_PinSocket_1.27mm -PinSocket_2x15_P1.27mm_Vertical -Through hole straight socket strip, 2x15, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x15 1.27mm double row -0 -30 -30 -Connector_PinSocket_1.27mm -PinSocket_2x15_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x15, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x15 1.27mm double row -0 -30 -30 -Connector_PinSocket_1.27mm -PinSocket_2x16_P1.27mm_Horizontal -Through hole angled socket strip, 2x16, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x16 1.27mm double row -0 -32 -32 -Connector_PinSocket_1.27mm -PinSocket_2x16_P1.27mm_Vertical -Through hole straight socket strip, 2x16, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x16 1.27mm double row -0 -32 -32 -Connector_PinSocket_1.27mm -PinSocket_2x16_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x16, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x16 1.27mm double row -0 -32 -32 -Connector_PinSocket_1.27mm -PinSocket_2x17_P1.27mm_Horizontal -Through hole angled socket strip, 2x17, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x17 1.27mm double row -0 -34 -34 -Connector_PinSocket_1.27mm -PinSocket_2x17_P1.27mm_Vertical -Through hole straight socket strip, 2x17, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x17 1.27mm double row -0 -34 -34 -Connector_PinSocket_1.27mm -PinSocket_2x17_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x17, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x17 1.27mm double row -0 -34 -34 -Connector_PinSocket_1.27mm -PinSocket_2x18_P1.27mm_Horizontal -Through hole angled socket strip, 2x18, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x18 1.27mm double row -0 -36 -36 -Connector_PinSocket_1.27mm -PinSocket_2x18_P1.27mm_Vertical -Through hole straight socket strip, 2x18, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x18 1.27mm double row -0 -36 -36 -Connector_PinSocket_1.27mm -PinSocket_2x18_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x18, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x18 1.27mm double row -0 -36 -36 -Connector_PinSocket_1.27mm -PinSocket_2x19_P1.27mm_Horizontal -Through hole angled socket strip, 2x19, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x19 1.27mm double row -0 -38 -38 -Connector_PinSocket_1.27mm -PinSocket_2x19_P1.27mm_Vertical -Through hole straight socket strip, 2x19, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x19 1.27mm double row -0 -38 -38 -Connector_PinSocket_1.27mm -PinSocket_2x19_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x19, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x19 1.27mm double row -0 -38 -38 -Connector_PinSocket_1.27mm -PinSocket_2x20_P1.27mm_Horizontal -Through hole angled socket strip, 2x20, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x20 1.27mm double row -0 -40 -40 -Connector_PinSocket_1.27mm -PinSocket_2x20_P1.27mm_Vertical -Through hole straight socket strip, 2x20, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x20 1.27mm double row -0 -40 -40 -Connector_PinSocket_1.27mm -PinSocket_2x20_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x20, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x20 1.27mm double row -0 -40 -40 -Connector_PinSocket_1.27mm -PinSocket_2x21_P1.27mm_Horizontal -Through hole angled socket strip, 2x21, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x21 1.27mm double row -0 -42 -42 -Connector_PinSocket_1.27mm -PinSocket_2x21_P1.27mm_Vertical -Through hole straight socket strip, 2x21, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x21 1.27mm double row -0 -42 -42 -Connector_PinSocket_1.27mm -PinSocket_2x21_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x21, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x21 1.27mm double row -0 -42 -42 -Connector_PinSocket_1.27mm -PinSocket_2x22_P1.27mm_Horizontal -Through hole angled socket strip, 2x22, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x22 1.27mm double row -0 -44 -44 -Connector_PinSocket_1.27mm -PinSocket_2x22_P1.27mm_Vertical -Through hole straight socket strip, 2x22, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x22 1.27mm double row -0 -44 -44 -Connector_PinSocket_1.27mm -PinSocket_2x22_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x22, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x22 1.27mm double row -0 -44 -44 -Connector_PinSocket_1.27mm -PinSocket_2x23_P1.27mm_Horizontal -Through hole angled socket strip, 2x23, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x23 1.27mm double row -0 -46 -46 -Connector_PinSocket_1.27mm -PinSocket_2x23_P1.27mm_Vertical -Through hole straight socket strip, 2x23, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x23 1.27mm double row -0 -46 -46 -Connector_PinSocket_1.27mm -PinSocket_2x23_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x23, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x23 1.27mm double row -0 -46 -46 -Connector_PinSocket_1.27mm -PinSocket_2x24_P1.27mm_Horizontal -Through hole angled socket strip, 2x24, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x24 1.27mm double row -0 -48 -48 -Connector_PinSocket_1.27mm -PinSocket_2x24_P1.27mm_Vertical -Through hole straight socket strip, 2x24, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x24 1.27mm double row -0 -48 -48 -Connector_PinSocket_1.27mm -PinSocket_2x24_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x24, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x24 1.27mm double row -0 -48 -48 -Connector_PinSocket_1.27mm -PinSocket_2x25_P1.27mm_Horizontal -Through hole angled socket strip, 2x25, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x25 1.27mm double row -0 -50 -50 -Connector_PinSocket_1.27mm -PinSocket_2x25_P1.27mm_Vertical -Through hole straight socket strip, 2x25, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x25 1.27mm double row -0 -50 -50 -Connector_PinSocket_1.27mm -PinSocket_2x25_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x25, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x25 1.27mm double row -0 -50 -50 -Connector_PinSocket_1.27mm -PinSocket_2x26_P1.27mm_Horizontal -Through hole angled socket strip, 2x26, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x26 1.27mm double row -0 -52 -52 -Connector_PinSocket_1.27mm -PinSocket_2x26_P1.27mm_Vertical -Through hole straight socket strip, 2x26, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x26 1.27mm double row -0 -52 -52 -Connector_PinSocket_1.27mm -PinSocket_2x26_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x26, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x26 1.27mm double row -0 -52 -52 -Connector_PinSocket_1.27mm -PinSocket_2x27_P1.27mm_Horizontal -Through hole angled socket strip, 2x27, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x27 1.27mm double row -0 -54 -54 -Connector_PinSocket_1.27mm -PinSocket_2x27_P1.27mm_Vertical -Through hole straight socket strip, 2x27, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x27 1.27mm double row -0 -54 -54 -Connector_PinSocket_1.27mm -PinSocket_2x27_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x27, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x27 1.27mm double row -0 -54 -54 -Connector_PinSocket_1.27mm -PinSocket_2x28_P1.27mm_Horizontal -Through hole angled socket strip, 2x28, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x28 1.27mm double row -0 -56 -56 -Connector_PinSocket_1.27mm -PinSocket_2x28_P1.27mm_Vertical -Through hole straight socket strip, 2x28, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x28 1.27mm double row -0 -56 -56 -Connector_PinSocket_1.27mm -PinSocket_2x28_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x28, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x28 1.27mm double row -0 -56 -56 -Connector_PinSocket_1.27mm -PinSocket_2x29_P1.27mm_Horizontal -Through hole angled socket strip, 2x29, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x29 1.27mm double row -0 -58 -58 -Connector_PinSocket_1.27mm -PinSocket_2x29_P1.27mm_Vertical -Through hole straight socket strip, 2x29, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x29 1.27mm double row -0 -58 -58 -Connector_PinSocket_1.27mm -PinSocket_2x29_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x29, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x29 1.27mm double row -0 -58 -58 -Connector_PinSocket_1.27mm -PinSocket_2x30_P1.27mm_Horizontal -Through hole angled socket strip, 2x30, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x30 1.27mm double row -0 -60 -60 -Connector_PinSocket_1.27mm -PinSocket_2x30_P1.27mm_Vertical -Through hole straight socket strip, 2x30, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x30 1.27mm double row -0 -60 -60 -Connector_PinSocket_1.27mm -PinSocket_2x30_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x30, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x30 1.27mm double row -0 -60 -60 -Connector_PinSocket_1.27mm -PinSocket_2x31_P1.27mm_Horizontal -Through hole angled socket strip, 2x31, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x31 1.27mm double row -0 -62 -62 -Connector_PinSocket_1.27mm -PinSocket_2x31_P1.27mm_Vertical -Through hole straight socket strip, 2x31, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x31 1.27mm double row -0 -62 -62 -Connector_PinSocket_1.27mm -PinSocket_2x31_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x31, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x31 1.27mm double row -0 -62 -62 -Connector_PinSocket_1.27mm -PinSocket_2x32_P1.27mm_Horizontal -Through hole angled socket strip, 2x32, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x32 1.27mm double row -0 -64 -64 -Connector_PinSocket_1.27mm -PinSocket_2x32_P1.27mm_Vertical -Through hole straight socket strip, 2x32, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x32 1.27mm double row -0 -64 -64 -Connector_PinSocket_1.27mm -PinSocket_2x32_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x32, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x32 1.27mm double row -0 -64 -64 -Connector_PinSocket_1.27mm -PinSocket_2x33_P1.27mm_Horizontal -Through hole angled socket strip, 2x33, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x33 1.27mm double row -0 -66 -66 -Connector_PinSocket_1.27mm -PinSocket_2x33_P1.27mm_Vertical -Through hole straight socket strip, 2x33, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x33 1.27mm double row -0 -66 -66 -Connector_PinSocket_1.27mm -PinSocket_2x33_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x33, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x33 1.27mm double row -0 -66 -66 -Connector_PinSocket_1.27mm -PinSocket_2x34_P1.27mm_Horizontal -Through hole angled socket strip, 2x34, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x34 1.27mm double row -0 -68 -68 -Connector_PinSocket_1.27mm -PinSocket_2x34_P1.27mm_Vertical -Through hole straight socket strip, 2x34, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x34 1.27mm double row -0 -68 -68 -Connector_PinSocket_1.27mm -PinSocket_2x34_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x34, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x34 1.27mm double row -0 -68 -68 -Connector_PinSocket_1.27mm -PinSocket_2x35_P1.27mm_Horizontal -Through hole angled socket strip, 2x35, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x35 1.27mm double row -0 -70 -70 -Connector_PinSocket_1.27mm -PinSocket_2x35_P1.27mm_Vertical -Through hole straight socket strip, 2x35, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x35 1.27mm double row -0 -70 -70 -Connector_PinSocket_1.27mm -PinSocket_2x35_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x35, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x35 1.27mm double row -0 -70 -70 -Connector_PinSocket_1.27mm -PinSocket_2x36_P1.27mm_Horizontal -Through hole angled socket strip, 2x36, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x36 1.27mm double row -0 -72 -72 -Connector_PinSocket_1.27mm -PinSocket_2x36_P1.27mm_Vertical -Through hole straight socket strip, 2x36, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x36 1.27mm double row -0 -72 -72 -Connector_PinSocket_1.27mm -PinSocket_2x36_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x36, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x36 1.27mm double row -0 -72 -72 -Connector_PinSocket_1.27mm -PinSocket_2x37_P1.27mm_Horizontal -Through hole angled socket strip, 2x37, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x37 1.27mm double row -0 -74 -74 -Connector_PinSocket_1.27mm -PinSocket_2x37_P1.27mm_Vertical -Through hole straight socket strip, 2x37, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x37 1.27mm double row -0 -74 -74 -Connector_PinSocket_1.27mm -PinSocket_2x37_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x37, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x37 1.27mm double row -0 -74 -74 -Connector_PinSocket_1.27mm -PinSocket_2x38_P1.27mm_Horizontal -Through hole angled socket strip, 2x38, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x38 1.27mm double row -0 -76 -76 -Connector_PinSocket_1.27mm -PinSocket_2x38_P1.27mm_Vertical -Through hole straight socket strip, 2x38, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x38 1.27mm double row -0 -76 -76 -Connector_PinSocket_1.27mm -PinSocket_2x38_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x38, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x38 1.27mm double row -0 -76 -76 -Connector_PinSocket_1.27mm -PinSocket_2x39_P1.27mm_Horizontal -Through hole angled socket strip, 2x39, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x39 1.27mm double row -0 -78 -78 -Connector_PinSocket_1.27mm -PinSocket_2x39_P1.27mm_Vertical -Through hole straight socket strip, 2x39, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x39 1.27mm double row -0 -78 -78 -Connector_PinSocket_1.27mm -PinSocket_2x39_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x39, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x39 1.27mm double row -0 -78 -78 -Connector_PinSocket_1.27mm -PinSocket_2x40_P1.27mm_Horizontal -Through hole angled socket strip, 2x40, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x40 1.27mm double row -0 -80 -80 -Connector_PinSocket_1.27mm -PinSocket_2x40_P1.27mm_Vertical -Through hole straight socket strip, 2x40, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x40 1.27mm double row -0 -80 -80 -Connector_PinSocket_1.27mm -PinSocket_2x40_P1.27mm_Vertical_SMD -surface-mounted straight socket strip, 2x40, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated -Surface mounted socket strip SMD 2x40 1.27mm double row -0 -80 -80 -Connector_PinSocket_1.27mm -PinSocket_2x41_P1.27mm_Horizontal -Through hole angled socket strip, 2x41, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x41 1.27mm double row -0 -82 -82 -Connector_PinSocket_1.27mm -PinSocket_2x42_P1.27mm_Horizontal -Through hole angled socket strip, 2x42, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x42 1.27mm double row -0 -84 -84 -Connector_PinSocket_1.27mm -PinSocket_2x43_P1.27mm_Horizontal -Through hole angled socket strip, 2x43, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x43 1.27mm double row -0 -86 -86 -Connector_PinSocket_1.27mm -PinSocket_2x44_P1.27mm_Horizontal -Through hole angled socket strip, 2x44, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x44 1.27mm double row -0 -88 -88 -Connector_PinSocket_1.27mm -PinSocket_2x45_P1.27mm_Horizontal -Through hole angled socket strip, 2x45, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x45 1.27mm double row -0 -90 -90 -Connector_PinSocket_1.27mm -PinSocket_2x46_P1.27mm_Horizontal -Through hole angled socket strip, 2x46, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x46 1.27mm double row -0 -92 -92 -Connector_PinSocket_1.27mm -PinSocket_2x47_P1.27mm_Horizontal -Through hole angled socket strip, 2x47, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x47 1.27mm double row -0 -94 -94 -Connector_PinSocket_1.27mm -PinSocket_2x48_P1.27mm_Horizontal -Through hole angled socket strip, 2x48, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x48 1.27mm double row -0 -96 -96 -Connector_PinSocket_1.27mm -PinSocket_2x49_P1.27mm_Horizontal -Through hole angled socket strip, 2x49, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x49 1.27mm double row -0 -98 -98 -Connector_PinSocket_1.27mm -PinSocket_2x50_P1.27mm_Horizontal -Through hole angled socket strip, 2x50, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated -Through hole angled socket strip THT 2x50 1.27mm double row -0 -100 -100 -Connector_PinSocket_2.00mm -PinSocket_1x01_P2.00mm_Horizontal -Through hole angled socket strip, 1x01, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x01 2.00mm single row -0 -1 -1 -Connector_PinSocket_2.00mm -PinSocket_1x01_P2.00mm_Vertical -Through hole straight socket strip, 1x01, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x01 2.00mm single row -0 -1 -1 -Connector_PinSocket_2.00mm -PinSocket_1x02_P2.00mm_Horizontal -Through hole angled socket strip, 1x02, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x02 2.00mm single row -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_1x02_P2.00mm_Vertical -Through hole straight socket strip, 1x02, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x02 2.00mm single row -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_1x02_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x02, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x02 2.00mm single row style1 pin1 left -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_1x02_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x02, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x02 2.00mm single row style2 pin1 right -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_1x03_P2.00mm_Horizontal -Through hole angled socket strip, 1x03, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x03 2.00mm single row -0 -3 -3 -Connector_PinSocket_2.00mm -PinSocket_1x03_P2.00mm_Vertical -Through hole straight socket strip, 1x03, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x03 2.00mm single row -0 -3 -3 -Connector_PinSocket_2.00mm -PinSocket_1x03_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x03, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x03 2.00mm single row style1 pin1 left -0 -3 -3 -Connector_PinSocket_2.00mm -PinSocket_1x03_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x03, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x03 2.00mm single row style2 pin1 right -0 -3 -3 -Connector_PinSocket_2.00mm -PinSocket_1x04_P2.00mm_Horizontal -Through hole angled socket strip, 1x04, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x04 2.00mm single row -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_1x04_P2.00mm_Vertical -Through hole straight socket strip, 1x04, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x04 2.00mm single row -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_1x04_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x04, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x04 2.00mm single row style1 pin1 left -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_1x04_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x04, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x04 2.00mm single row style2 pin1 right -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_1x05_P2.00mm_Horizontal -Through hole angled socket strip, 1x05, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x05 2.00mm single row -0 -5 -5 -Connector_PinSocket_2.00mm -PinSocket_1x05_P2.00mm_Vertical -Through hole straight socket strip, 1x05, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x05 2.00mm single row -0 -5 -5 -Connector_PinSocket_2.00mm -PinSocket_1x05_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x05, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x05 2.00mm single row style1 pin1 left -0 -5 -5 -Connector_PinSocket_2.00mm -PinSocket_1x05_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x05, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x05 2.00mm single row style2 pin1 right -0 -5 -5 -Connector_PinSocket_2.00mm -PinSocket_1x06_P2.00mm_Horizontal -Through hole angled socket strip, 1x06, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x06 2.00mm single row -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_1x06_P2.00mm_Vertical -Through hole straight socket strip, 1x06, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x06 2.00mm single row -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_1x06_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x06, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x06 2.00mm single row style1 pin1 left -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_1x06_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x06, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x06 2.00mm single row style2 pin1 right -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_1x07_P2.00mm_Horizontal -Through hole angled socket strip, 1x07, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x07 2.00mm single row -0 -7 -7 -Connector_PinSocket_2.00mm -PinSocket_1x07_P2.00mm_Vertical -Through hole straight socket strip, 1x07, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x07 2.00mm single row -0 -7 -7 -Connector_PinSocket_2.00mm -PinSocket_1x07_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x07, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x07 2.00mm single row style1 pin1 left -0 -7 -7 -Connector_PinSocket_2.00mm -PinSocket_1x07_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x07, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x07 2.00mm single row style2 pin1 right -0 -7 -7 -Connector_PinSocket_2.00mm -PinSocket_1x08_P2.00mm_Horizontal -Through hole angled socket strip, 1x08, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x08 2.00mm single row -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_1x08_P2.00mm_Vertical -Through hole straight socket strip, 1x08, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x08 2.00mm single row -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_1x08_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x08, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x08 2.00mm single row style1 pin1 left -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_1x08_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x08, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x08 2.00mm single row style2 pin1 right -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_1x09_P2.00mm_Horizontal -Through hole angled socket strip, 1x09, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x09 2.00mm single row -0 -9 -9 -Connector_PinSocket_2.00mm -PinSocket_1x09_P2.00mm_Vertical -Through hole straight socket strip, 1x09, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x09 2.00mm single row -0 -9 -9 -Connector_PinSocket_2.00mm -PinSocket_1x09_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x09, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x09 2.00mm single row style1 pin1 left -0 -9 -9 -Connector_PinSocket_2.00mm -PinSocket_1x09_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x09, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x09 2.00mm single row style2 pin1 right -0 -9 -9 -Connector_PinSocket_2.00mm -PinSocket_1x10_P2.00mm_Horizontal -Through hole angled socket strip, 1x10, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x10 2.00mm single row -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_1x10_P2.00mm_Vertical -Through hole straight socket strip, 1x10, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x10 2.00mm single row -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_1x10_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x10, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x10 2.00mm single row style1 pin1 left -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_1x10_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x10, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x10 2.00mm single row style2 pin1 right -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_1x11_P2.00mm_Horizontal -Through hole angled socket strip, 1x11, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x11 2.00mm single row -0 -11 -11 -Connector_PinSocket_2.00mm -PinSocket_1x11_P2.00mm_Vertical -Through hole straight socket strip, 1x11, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x11 2.00mm single row -0 -11 -11 -Connector_PinSocket_2.00mm -PinSocket_1x11_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x11, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x11 2.00mm single row style1 pin1 left -0 -11 -11 -Connector_PinSocket_2.00mm -PinSocket_1x11_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x11, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x11 2.00mm single row style2 pin1 right -0 -11 -11 -Connector_PinSocket_2.00mm -PinSocket_1x12_P2.00mm_Horizontal -Through hole angled socket strip, 1x12, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x12 2.00mm single row -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_1x12_P2.00mm_Vertical -Through hole straight socket strip, 1x12, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x12 2.00mm single row -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_1x12_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x12, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x12 2.00mm single row style1 pin1 left -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_1x12_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x12, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x12 2.00mm single row style2 pin1 right -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_1x13_P2.00mm_Horizontal -Through hole angled socket strip, 1x13, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x13 2.00mm single row -0 -13 -13 -Connector_PinSocket_2.00mm -PinSocket_1x13_P2.00mm_Vertical -Through hole straight socket strip, 1x13, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x13 2.00mm single row -0 -13 -13 -Connector_PinSocket_2.00mm -PinSocket_1x13_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x13, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x13 2.00mm single row style1 pin1 left -0 -13 -13 -Connector_PinSocket_2.00mm -PinSocket_1x13_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x13, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x13 2.00mm single row style2 pin1 right -0 -13 -13 -Connector_PinSocket_2.00mm -PinSocket_1x14_P2.00mm_Horizontal -Through hole angled socket strip, 1x14, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x14 2.00mm single row -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_1x14_P2.00mm_Vertical -Through hole straight socket strip, 1x14, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x14 2.00mm single row -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_1x14_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x14, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x14 2.00mm single row style1 pin1 left -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_1x14_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x14, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x14 2.00mm single row style2 pin1 right -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_1x15_P2.00mm_Horizontal -Through hole angled socket strip, 1x15, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x15 2.00mm single row -0 -15 -15 -Connector_PinSocket_2.00mm -PinSocket_1x15_P2.00mm_Vertical -Through hole straight socket strip, 1x15, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x15 2.00mm single row -0 -15 -15 -Connector_PinSocket_2.00mm -PinSocket_1x15_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x15, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x15 2.00mm single row style1 pin1 left -0 -15 -15 -Connector_PinSocket_2.00mm -PinSocket_1x15_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x15, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x15 2.00mm single row style2 pin1 right -0 -15 -15 -Connector_PinSocket_2.00mm -PinSocket_1x16_P2.00mm_Horizontal -Through hole angled socket strip, 1x16, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x16 2.00mm single row -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_1x16_P2.00mm_Vertical -Through hole straight socket strip, 1x16, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x16 2.00mm single row -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_1x16_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x16, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x16 2.00mm single row style1 pin1 left -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_1x16_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x16, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x16 2.00mm single row style2 pin1 right -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_1x17_P2.00mm_Horizontal -Through hole angled socket strip, 1x17, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x17 2.00mm single row -0 -17 -17 -Connector_PinSocket_2.00mm -PinSocket_1x17_P2.00mm_Vertical -Through hole straight socket strip, 1x17, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x17 2.00mm single row -0 -17 -17 -Connector_PinSocket_2.00mm -PinSocket_1x17_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x17, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x17 2.00mm single row style1 pin1 left -0 -17 -17 -Connector_PinSocket_2.00mm -PinSocket_1x17_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x17, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x17 2.00mm single row style2 pin1 right -0 -17 -17 -Connector_PinSocket_2.00mm -PinSocket_1x18_P2.00mm_Horizontal -Through hole angled socket strip, 1x18, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x18 2.00mm single row -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_1x18_P2.00mm_Vertical -Through hole straight socket strip, 1x18, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x18 2.00mm single row -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_1x18_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x18, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x18 2.00mm single row style1 pin1 left -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_1x18_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x18, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x18 2.00mm single row style2 pin1 right -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_1x19_P2.00mm_Horizontal -Through hole angled socket strip, 1x19, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x19 2.00mm single row -0 -19 -19 -Connector_PinSocket_2.00mm -PinSocket_1x19_P2.00mm_Vertical -Through hole straight socket strip, 1x19, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x19 2.00mm single row -0 -19 -19 -Connector_PinSocket_2.00mm -PinSocket_1x19_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x19, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x19 2.00mm single row style1 pin1 left -0 -19 -19 -Connector_PinSocket_2.00mm -PinSocket_1x19_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x19, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x19 2.00mm single row style2 pin1 right -0 -19 -19 -Connector_PinSocket_2.00mm -PinSocket_1x20_P2.00mm_Horizontal -Through hole angled socket strip, 1x20, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x20 2.00mm single row -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_1x20_P2.00mm_Vertical -Through hole straight socket strip, 1x20, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x20 2.00mm single row -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_1x20_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x20, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x20 2.00mm single row style1 pin1 left -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_1x20_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x20, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x20 2.00mm single row style2 pin1 right -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_1x21_P2.00mm_Horizontal -Through hole angled socket strip, 1x21, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x21 2.00mm single row -0 -21 -21 -Connector_PinSocket_2.00mm -PinSocket_1x21_P2.00mm_Vertical -Through hole straight socket strip, 1x21, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x21 2.00mm single row -0 -21 -21 -Connector_PinSocket_2.00mm -PinSocket_1x21_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x21, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x21 2.00mm single row style1 pin1 left -0 -21 -21 -Connector_PinSocket_2.00mm -PinSocket_1x21_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x21, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x21 2.00mm single row style2 pin1 right -0 -21 -21 -Connector_PinSocket_2.00mm -PinSocket_1x22_P2.00mm_Horizontal -Through hole angled socket strip, 1x22, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x22 2.00mm single row -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_1x22_P2.00mm_Vertical -Through hole straight socket strip, 1x22, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x22 2.00mm single row -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_1x22_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x22, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x22 2.00mm single row style1 pin1 left -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_1x22_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x22, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x22 2.00mm single row style2 pin1 right -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_1x23_P2.00mm_Horizontal -Through hole angled socket strip, 1x23, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x23 2.00mm single row -0 -23 -23 -Connector_PinSocket_2.00mm -PinSocket_1x23_P2.00mm_Vertical -Through hole straight socket strip, 1x23, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x23 2.00mm single row -0 -23 -23 -Connector_PinSocket_2.00mm -PinSocket_1x23_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x23, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x23 2.00mm single row style1 pin1 left -0 -23 -23 -Connector_PinSocket_2.00mm -PinSocket_1x23_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x23, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x23 2.00mm single row style2 pin1 right -0 -23 -23 -Connector_PinSocket_2.00mm -PinSocket_1x24_P2.00mm_Horizontal -Through hole angled socket strip, 1x24, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x24 2.00mm single row -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_1x24_P2.00mm_Vertical -Through hole straight socket strip, 1x24, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x24 2.00mm single row -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_1x24_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x24, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x24 2.00mm single row style1 pin1 left -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_1x24_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x24, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x24 2.00mm single row style2 pin1 right -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_1x25_P2.00mm_Horizontal -Through hole angled socket strip, 1x25, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x25 2.00mm single row -0 -25 -25 -Connector_PinSocket_2.00mm -PinSocket_1x25_P2.00mm_Vertical -Through hole straight socket strip, 1x25, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x25 2.00mm single row -0 -25 -25 -Connector_PinSocket_2.00mm -PinSocket_1x25_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x25, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x25 2.00mm single row style1 pin1 left -0 -25 -25 -Connector_PinSocket_2.00mm -PinSocket_1x25_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x25, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x25 2.00mm single row style2 pin1 right -0 -25 -25 -Connector_PinSocket_2.00mm -PinSocket_1x26_P2.00mm_Horizontal -Through hole angled socket strip, 1x26, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x26 2.00mm single row -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_1x26_P2.00mm_Vertical -Through hole straight socket strip, 1x26, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x26 2.00mm single row -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_1x26_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x26, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x26 2.00mm single row style1 pin1 left -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_1x26_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x26, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x26 2.00mm single row style2 pin1 right -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_1x27_P2.00mm_Horizontal -Through hole angled socket strip, 1x27, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x27 2.00mm single row -0 -27 -27 -Connector_PinSocket_2.00mm -PinSocket_1x27_P2.00mm_Vertical -Through hole straight socket strip, 1x27, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x27 2.00mm single row -0 -27 -27 -Connector_PinSocket_2.00mm -PinSocket_1x27_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x27, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x27 2.00mm single row style1 pin1 left -0 -27 -27 -Connector_PinSocket_2.00mm -PinSocket_1x27_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x27, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x27 2.00mm single row style2 pin1 right -0 -27 -27 -Connector_PinSocket_2.00mm -PinSocket_1x28_P2.00mm_Horizontal -Through hole angled socket strip, 1x28, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x28 2.00mm single row -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_1x28_P2.00mm_Vertical -Through hole straight socket strip, 1x28, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x28 2.00mm single row -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_1x28_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x28, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x28 2.00mm single row style1 pin1 left -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_1x28_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x28, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x28 2.00mm single row style2 pin1 right -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_1x29_P2.00mm_Horizontal -Through hole angled socket strip, 1x29, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x29 2.00mm single row -0 -29 -29 -Connector_PinSocket_2.00mm -PinSocket_1x29_P2.00mm_Vertical -Through hole straight socket strip, 1x29, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x29 2.00mm single row -0 -29 -29 -Connector_PinSocket_2.00mm -PinSocket_1x29_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x29, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x29 2.00mm single row style1 pin1 left -0 -29 -29 -Connector_PinSocket_2.00mm -PinSocket_1x29_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x29, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x29 2.00mm single row style2 pin1 right -0 -29 -29 -Connector_PinSocket_2.00mm -PinSocket_1x30_P2.00mm_Horizontal -Through hole angled socket strip, 1x30, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x30 2.00mm single row -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_1x30_P2.00mm_Vertical -Through hole straight socket strip, 1x30, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x30 2.00mm single row -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_1x30_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x30, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x30 2.00mm single row style1 pin1 left -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_1x30_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x30, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x30 2.00mm single row style2 pin1 right -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_1x31_P2.00mm_Horizontal -Through hole angled socket strip, 1x31, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x31 2.00mm single row -0 -31 -31 -Connector_PinSocket_2.00mm -PinSocket_1x31_P2.00mm_Vertical -Through hole straight socket strip, 1x31, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x31 2.00mm single row -0 -31 -31 -Connector_PinSocket_2.00mm -PinSocket_1x31_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x31, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x31 2.00mm single row style1 pin1 left -0 -31 -31 -Connector_PinSocket_2.00mm -PinSocket_1x31_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x31, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x31 2.00mm single row style2 pin1 right -0 -31 -31 -Connector_PinSocket_2.00mm -PinSocket_1x32_P2.00mm_Horizontal -Through hole angled socket strip, 1x32, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x32 2.00mm single row -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_1x32_P2.00mm_Vertical -Through hole straight socket strip, 1x32, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x32 2.00mm single row -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_1x32_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x32, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x32 2.00mm single row style1 pin1 left -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_1x32_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x32, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x32 2.00mm single row style2 pin1 right -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_1x33_P2.00mm_Horizontal -Through hole angled socket strip, 1x33, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x33 2.00mm single row -0 -33 -33 -Connector_PinSocket_2.00mm -PinSocket_1x33_P2.00mm_Vertical -Through hole straight socket strip, 1x33, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x33 2.00mm single row -0 -33 -33 -Connector_PinSocket_2.00mm -PinSocket_1x33_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x33, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x33 2.00mm single row style1 pin1 left -0 -33 -33 -Connector_PinSocket_2.00mm -PinSocket_1x33_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x33, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x33 2.00mm single row style2 pin1 right -0 -33 -33 -Connector_PinSocket_2.00mm -PinSocket_1x34_P2.00mm_Horizontal -Through hole angled socket strip, 1x34, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x34 2.00mm single row -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_1x34_P2.00mm_Vertical -Through hole straight socket strip, 1x34, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x34 2.00mm single row -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_1x34_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x34, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x34 2.00mm single row style1 pin1 left -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_1x34_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x34, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x34 2.00mm single row style2 pin1 right -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_1x35_P2.00mm_Horizontal -Through hole angled socket strip, 1x35, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x35 2.00mm single row -0 -35 -35 -Connector_PinSocket_2.00mm -PinSocket_1x35_P2.00mm_Vertical -Through hole straight socket strip, 1x35, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x35 2.00mm single row -0 -35 -35 -Connector_PinSocket_2.00mm -PinSocket_1x35_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x35, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x35 2.00mm single row style1 pin1 left -0 -35 -35 -Connector_PinSocket_2.00mm -PinSocket_1x35_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x35, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x35 2.00mm single row style2 pin1 right -0 -35 -35 -Connector_PinSocket_2.00mm -PinSocket_1x36_P2.00mm_Horizontal -Through hole angled socket strip, 1x36, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x36 2.00mm single row -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_1x36_P2.00mm_Vertical -Through hole straight socket strip, 1x36, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x36 2.00mm single row -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_1x36_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x36, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x36 2.00mm single row style1 pin1 left -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_1x36_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x36, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x36 2.00mm single row style2 pin1 right -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_1x37_P2.00mm_Horizontal -Through hole angled socket strip, 1x37, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x37 2.00mm single row -0 -37 -37 -Connector_PinSocket_2.00mm -PinSocket_1x37_P2.00mm_Vertical -Through hole straight socket strip, 1x37, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x37 2.00mm single row -0 -37 -37 -Connector_PinSocket_2.00mm -PinSocket_1x37_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x37, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x37 2.00mm single row style1 pin1 left -0 -37 -37 -Connector_PinSocket_2.00mm -PinSocket_1x37_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x37, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x37 2.00mm single row style2 pin1 right -0 -37 -37 -Connector_PinSocket_2.00mm -PinSocket_1x38_P2.00mm_Horizontal -Through hole angled socket strip, 1x38, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x38 2.00mm single row -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_1x38_P2.00mm_Vertical -Through hole straight socket strip, 1x38, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x38 2.00mm single row -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_1x38_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x38, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x38 2.00mm single row style1 pin1 left -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_1x38_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x38, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x38 2.00mm single row style2 pin1 right -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_1x39_P2.00mm_Horizontal -Through hole angled socket strip, 1x39, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x39 2.00mm single row -0 -39 -39 -Connector_PinSocket_2.00mm -PinSocket_1x39_P2.00mm_Vertical -Through hole straight socket strip, 1x39, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x39 2.00mm single row -0 -39 -39 -Connector_PinSocket_2.00mm -PinSocket_1x39_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x39, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x39 2.00mm single row style1 pin1 left -0 -39 -39 -Connector_PinSocket_2.00mm -PinSocket_1x39_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x39, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x39 2.00mm single row style2 pin1 right -0 -39 -39 -Connector_PinSocket_2.00mm -PinSocket_1x40_P2.00mm_Horizontal -Through hole angled socket strip, 1x40, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x40 2.00mm single row -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_1x40_P2.00mm_Vertical -Through hole straight socket strip, 1x40, 2.00mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x40 2.00mm single row -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_1x40_P2.00mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x40, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x40 2.00mm single row style1 pin1 left -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_1x40_P2.00mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x40, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated -Surface mounted socket strip SMD 1x40 2.00mm single row style2 pin1 right -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_2x01_P2.00mm_Horizontal -Through hole angled socket strip, 2x01, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x01 2.00mm double row -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_2x01_P2.00mm_Vertical -Through hole straight socket strip, 2x01, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x01 2.00mm double row -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_2x01_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x01, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x01 2.00mm double row -0 -2 -2 -Connector_PinSocket_2.00mm -PinSocket_2x02_P2.00mm_Horizontal -Through hole angled socket strip, 2x02, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x02 2.00mm double row -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_2x02_P2.00mm_Vertical -Through hole straight socket strip, 2x02, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x02 2.00mm double row -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_2x02_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x02, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x02 2.00mm double row -0 -4 -4 -Connector_PinSocket_2.00mm -PinSocket_2x03_P2.00mm_Horizontal -Through hole angled socket strip, 2x03, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x03 2.00mm double row -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_2x03_P2.00mm_Vertical -Through hole straight socket strip, 2x03, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x03 2.00mm double row -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_2x03_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x03, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x03 2.00mm double row -0 -6 -6 -Connector_PinSocket_2.00mm -PinSocket_2x04_P2.00mm_Horizontal -Through hole angled socket strip, 2x04, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x04 2.00mm double row -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_2x04_P2.00mm_Vertical -Through hole straight socket strip, 2x04, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x04 2.00mm double row -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_2x04_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x04, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x04 2.00mm double row -0 -8 -8 -Connector_PinSocket_2.00mm -PinSocket_2x05_P2.00mm_Horizontal -Through hole angled socket strip, 2x05, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x05 2.00mm double row -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_2x05_P2.00mm_Vertical -Through hole straight socket strip, 2x05, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x05 2.00mm double row -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_2x05_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x05, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x05 2.00mm double row -0 -10 -10 -Connector_PinSocket_2.00mm -PinSocket_2x06_P2.00mm_Horizontal -Through hole angled socket strip, 2x06, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x06 2.00mm double row -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_2x06_P2.00mm_Vertical -Through hole straight socket strip, 2x06, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x06 2.00mm double row -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_2x06_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x06, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x06 2.00mm double row -0 -12 -12 -Connector_PinSocket_2.00mm -PinSocket_2x07_P2.00mm_Horizontal -Through hole angled socket strip, 2x07, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x07 2.00mm double row -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_2x07_P2.00mm_Vertical -Through hole straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x07 2.00mm double row -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_2x07_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x07 2.00mm double row -0 -14 -14 -Connector_PinSocket_2.00mm -PinSocket_2x08_P2.00mm_Horizontal -Through hole angled socket strip, 2x08, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x08 2.00mm double row -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_2x08_P2.00mm_Vertical -Through hole straight socket strip, 2x08, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x08 2.00mm double row -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_2x08_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x08, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x08 2.00mm double row -0 -16 -16 -Connector_PinSocket_2.00mm -PinSocket_2x09_P2.00mm_Horizontal -Through hole angled socket strip, 2x09, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x09 2.00mm double row -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_2x09_P2.00mm_Vertical -Through hole straight socket strip, 2x09, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x09 2.00mm double row -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_2x09_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x09, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x09 2.00mm double row -0 -18 -18 -Connector_PinSocket_2.00mm -PinSocket_2x10_P2.00mm_Horizontal -Through hole angled socket strip, 2x10, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x10 2.00mm double row -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_2x10_P2.00mm_Vertical -Through hole straight socket strip, 2x10, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x10 2.00mm double row -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_2x10_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x10, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x10 2.00mm double row -0 -20 -20 -Connector_PinSocket_2.00mm -PinSocket_2x11_P2.00mm_Horizontal -Through hole angled socket strip, 2x11, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x11 2.00mm double row -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_2x11_P2.00mm_Vertical -Through hole straight socket strip, 2x11, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x11 2.00mm double row -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_2x11_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x11, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x11 2.00mm double row -0 -22 -22 -Connector_PinSocket_2.00mm -PinSocket_2x12_P2.00mm_Horizontal -Through hole angled socket strip, 2x12, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x12 2.00mm double row -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_2x12_P2.00mm_Vertical -Through hole straight socket strip, 2x12, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x12 2.00mm double row -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_2x12_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x12, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x12 2.00mm double row -0 -24 -24 -Connector_PinSocket_2.00mm -PinSocket_2x13_P2.00mm_Horizontal -Through hole angled socket strip, 2x13, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x13 2.00mm double row -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_2x13_P2.00mm_Vertical -Through hole straight socket strip, 2x13, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x13 2.00mm double row -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_2x13_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x13, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x13 2.00mm double row -0 -26 -26 -Connector_PinSocket_2.00mm -PinSocket_2x14_P2.00mm_Horizontal -Through hole angled socket strip, 2x14, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x14 2.00mm double row -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_2x14_P2.00mm_Vertical -Through hole straight socket strip, 2x14, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x14 2.00mm double row -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_2x14_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x14, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x14 2.00mm double row -0 -28 -28 -Connector_PinSocket_2.00mm -PinSocket_2x15_P2.00mm_Horizontal -Through hole angled socket strip, 2x15, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x15 2.00mm double row -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_2x15_P2.00mm_Vertical -Through hole straight socket strip, 2x15, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x15 2.00mm double row -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_2x15_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x15, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x15 2.00mm double row -0 -30 -30 -Connector_PinSocket_2.00mm -PinSocket_2x16_P2.00mm_Horizontal -Through hole angled socket strip, 2x16, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x16 2.00mm double row -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_2x16_P2.00mm_Vertical -Through hole straight socket strip, 2x16, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x16 2.00mm double row -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_2x16_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x16, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x16 2.00mm double row -0 -32 -32 -Connector_PinSocket_2.00mm -PinSocket_2x17_P2.00mm_Horizontal -Through hole angled socket strip, 2x17, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x17 2.00mm double row -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_2x17_P2.00mm_Vertical -Through hole straight socket strip, 2x17, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x17 2.00mm double row -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_2x17_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x17, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x17 2.00mm double row -0 -34 -34 -Connector_PinSocket_2.00mm -PinSocket_2x18_P2.00mm_Horizontal -Through hole angled socket strip, 2x18, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x18 2.00mm double row -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_2x18_P2.00mm_Vertical -Through hole straight socket strip, 2x18, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x18 2.00mm double row -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_2x18_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x18, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x18 2.00mm double row -0 -36 -36 -Connector_PinSocket_2.00mm -PinSocket_2x19_P2.00mm_Horizontal -Through hole angled socket strip, 2x19, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x19 2.00mm double row -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_2x19_P2.00mm_Vertical -Through hole straight socket strip, 2x19, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x19 2.00mm double row -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_2x19_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x19, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x19 2.00mm double row -0 -38 -38 -Connector_PinSocket_2.00mm -PinSocket_2x20_P2.00mm_Horizontal -Through hole angled socket strip, 2x20, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x20 2.00mm double row -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_2x20_P2.00mm_Vertical -Through hole straight socket strip, 2x20, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x20 2.00mm double row -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_2x20_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x20, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x20 2.00mm double row -0 -40 -40 -Connector_PinSocket_2.00mm -PinSocket_2x21_P2.00mm_Horizontal -Through hole angled socket strip, 2x21, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x21 2.00mm double row -0 -42 -42 -Connector_PinSocket_2.00mm -PinSocket_2x21_P2.00mm_Vertical -Through hole straight socket strip, 2x21, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x21 2.00mm double row -0 -42 -42 -Connector_PinSocket_2.00mm -PinSocket_2x21_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x21, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x21 2.00mm double row -0 -42 -42 -Connector_PinSocket_2.00mm -PinSocket_2x22_P2.00mm_Horizontal -Through hole angled socket strip, 2x22, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x22 2.00mm double row -0 -44 -44 -Connector_PinSocket_2.00mm -PinSocket_2x22_P2.00mm_Vertical -Through hole straight socket strip, 2x22, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x22 2.00mm double row -0 -44 -44 -Connector_PinSocket_2.00mm -PinSocket_2x22_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x22, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x22 2.00mm double row -0 -44 -44 -Connector_PinSocket_2.00mm -PinSocket_2x23_P2.00mm_Horizontal -Through hole angled socket strip, 2x23, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x23 2.00mm double row -0 -46 -46 -Connector_PinSocket_2.00mm -PinSocket_2x23_P2.00mm_Vertical -Through hole straight socket strip, 2x23, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x23 2.00mm double row -0 -46 -46 -Connector_PinSocket_2.00mm -PinSocket_2x23_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x23, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x23 2.00mm double row -0 -46 -46 -Connector_PinSocket_2.00mm -PinSocket_2x24_P2.00mm_Horizontal -Through hole angled socket strip, 2x24, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x24 2.00mm double row -0 -48 -48 -Connector_PinSocket_2.00mm -PinSocket_2x24_P2.00mm_Vertical -Through hole straight socket strip, 2x24, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x24 2.00mm double row -0 -48 -48 -Connector_PinSocket_2.00mm -PinSocket_2x24_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x24, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x24 2.00mm double row -0 -48 -48 -Connector_PinSocket_2.00mm -PinSocket_2x25_P2.00mm_Horizontal -Through hole angled socket strip, 2x25, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x25 2.00mm double row -0 -50 -50 -Connector_PinSocket_2.00mm -PinSocket_2x25_P2.00mm_Vertical -Through hole straight socket strip, 2x25, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x25 2.00mm double row -0 -50 -50 -Connector_PinSocket_2.00mm -PinSocket_2x25_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x25, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x25 2.00mm double row -0 -50 -50 -Connector_PinSocket_2.00mm -PinSocket_2x26_P2.00mm_Horizontal -Through hole angled socket strip, 2x26, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x26 2.00mm double row -0 -52 -52 -Connector_PinSocket_2.00mm -PinSocket_2x26_P2.00mm_Vertical -Through hole straight socket strip, 2x26, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x26 2.00mm double row -0 -52 -52 -Connector_PinSocket_2.00mm -PinSocket_2x26_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x26, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x26 2.00mm double row -0 -52 -52 -Connector_PinSocket_2.00mm -PinSocket_2x27_P2.00mm_Horizontal -Through hole angled socket strip, 2x27, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x27 2.00mm double row -0 -54 -54 -Connector_PinSocket_2.00mm -PinSocket_2x27_P2.00mm_Vertical -Through hole straight socket strip, 2x27, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x27 2.00mm double row -0 -54 -54 -Connector_PinSocket_2.00mm -PinSocket_2x27_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x27, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x27 2.00mm double row -0 -54 -54 -Connector_PinSocket_2.00mm -PinSocket_2x28_P2.00mm_Horizontal -Through hole angled socket strip, 2x28, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x28 2.00mm double row -0 -56 -56 -Connector_PinSocket_2.00mm -PinSocket_2x28_P2.00mm_Vertical -Through hole straight socket strip, 2x28, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x28 2.00mm double row -0 -56 -56 -Connector_PinSocket_2.00mm -PinSocket_2x28_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x28, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x28 2.00mm double row -0 -56 -56 -Connector_PinSocket_2.00mm -PinSocket_2x29_P2.00mm_Horizontal -Through hole angled socket strip, 2x29, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x29 2.00mm double row -0 -58 -58 -Connector_PinSocket_2.00mm -PinSocket_2x29_P2.00mm_Vertical -Through hole straight socket strip, 2x29, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x29 2.00mm double row -0 -58 -58 -Connector_PinSocket_2.00mm -PinSocket_2x29_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x29, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x29 2.00mm double row -0 -58 -58 -Connector_PinSocket_2.00mm -PinSocket_2x30_P2.00mm_Horizontal -Through hole angled socket strip, 2x30, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x30 2.00mm double row -0 -60 -60 -Connector_PinSocket_2.00mm -PinSocket_2x30_P2.00mm_Vertical -Through hole straight socket strip, 2x30, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x30 2.00mm double row -0 -60 -60 -Connector_PinSocket_2.00mm -PinSocket_2x30_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x30, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x30 2.00mm double row -0 -60 -60 -Connector_PinSocket_2.00mm -PinSocket_2x31_P2.00mm_Horizontal -Through hole angled socket strip, 2x31, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x31 2.00mm double row -0 -62 -62 -Connector_PinSocket_2.00mm -PinSocket_2x31_P2.00mm_Vertical -Through hole straight socket strip, 2x31, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x31 2.00mm double row -0 -62 -62 -Connector_PinSocket_2.00mm -PinSocket_2x31_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x31, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x31 2.00mm double row -0 -62 -62 -Connector_PinSocket_2.00mm -PinSocket_2x32_P2.00mm_Horizontal -Through hole angled socket strip, 2x32, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x32 2.00mm double row -0 -64 -64 -Connector_PinSocket_2.00mm -PinSocket_2x32_P2.00mm_Vertical -Through hole straight socket strip, 2x32, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x32 2.00mm double row -0 -64 -64 -Connector_PinSocket_2.00mm -PinSocket_2x32_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x32, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x32 2.00mm double row -0 -64 -64 -Connector_PinSocket_2.00mm -PinSocket_2x33_P2.00mm_Horizontal -Through hole angled socket strip, 2x33, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x33 2.00mm double row -0 -66 -66 -Connector_PinSocket_2.00mm -PinSocket_2x33_P2.00mm_Vertical -Through hole straight socket strip, 2x33, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x33 2.00mm double row -0 -66 -66 -Connector_PinSocket_2.00mm -PinSocket_2x33_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x33, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x33 2.00mm double row -0 -66 -66 -Connector_PinSocket_2.00mm -PinSocket_2x34_P2.00mm_Horizontal -Through hole angled socket strip, 2x34, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x34 2.00mm double row -0 -68 -68 -Connector_PinSocket_2.00mm -PinSocket_2x34_P2.00mm_Vertical -Through hole straight socket strip, 2x34, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x34 2.00mm double row -0 -68 -68 -Connector_PinSocket_2.00mm -PinSocket_2x34_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x34, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x34 2.00mm double row -0 -68 -68 -Connector_PinSocket_2.00mm -PinSocket_2x35_P2.00mm_Horizontal -Through hole angled socket strip, 2x35, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x35 2.00mm double row -0 -70 -70 -Connector_PinSocket_2.00mm -PinSocket_2x35_P2.00mm_Vertical -Through hole straight socket strip, 2x35, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x35 2.00mm double row -0 -70 -70 -Connector_PinSocket_2.00mm -PinSocket_2x35_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x35, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x35 2.00mm double row -0 -70 -70 -Connector_PinSocket_2.00mm -PinSocket_2x36_P2.00mm_Horizontal -Through hole angled socket strip, 2x36, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x36 2.00mm double row -0 -72 -72 -Connector_PinSocket_2.00mm -PinSocket_2x36_P2.00mm_Vertical -Through hole straight socket strip, 2x36, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x36 2.00mm double row -0 -72 -72 -Connector_PinSocket_2.00mm -PinSocket_2x36_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x36, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x36 2.00mm double row -0 -72 -72 -Connector_PinSocket_2.00mm -PinSocket_2x37_P2.00mm_Horizontal -Through hole angled socket strip, 2x37, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x37 2.00mm double row -0 -74 -74 -Connector_PinSocket_2.00mm -PinSocket_2x37_P2.00mm_Vertical -Through hole straight socket strip, 2x37, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x37 2.00mm double row -0 -74 -74 -Connector_PinSocket_2.00mm -PinSocket_2x37_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x37, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x37 2.00mm double row -0 -74 -74 -Connector_PinSocket_2.00mm -PinSocket_2x38_P2.00mm_Horizontal -Through hole angled socket strip, 2x38, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x38 2.00mm double row -0 -76 -76 -Connector_PinSocket_2.00mm -PinSocket_2x38_P2.00mm_Vertical -Through hole straight socket strip, 2x38, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x38 2.00mm double row -0 -76 -76 -Connector_PinSocket_2.00mm -PinSocket_2x38_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x38, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x38 2.00mm double row -0 -76 -76 -Connector_PinSocket_2.00mm -PinSocket_2x39_P2.00mm_Horizontal -Through hole angled socket strip, 2x39, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x39 2.00mm double row -0 -78 -78 -Connector_PinSocket_2.00mm -PinSocket_2x39_P2.00mm_Vertical -Through hole straight socket strip, 2x39, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x39 2.00mm double row -0 -78 -78 -Connector_PinSocket_2.00mm -PinSocket_2x39_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x39, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x39 2.00mm double row -0 -78 -78 -Connector_PinSocket_2.00mm -PinSocket_2x40_P2.00mm_Horizontal -Through hole angled socket strip, 2x40, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x40 2.00mm double row -0 -80 -80 -Connector_PinSocket_2.00mm -PinSocket_2x40_P2.00mm_Vertical -Through hole straight socket strip, 2x40, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x40 2.00mm double row -0 -80 -80 -Connector_PinSocket_2.00mm -PinSocket_2x40_P2.00mm_Vertical_SMD -surface-mounted straight socket strip, 2x40, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x40 2.00mm double row -0 -80 -80 -Connector_PinSocket_2.54mm -PinSocket_1x01_P2.54mm_Horizontal -Through hole angled socket strip, 1x01, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x01 2.54mm single row -0 -1 -1 -Connector_PinSocket_2.54mm -PinSocket_1x01_P2.54mm_Vertical -Through hole straight socket strip, 1x01, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x01 2.54mm single row -0 -1 -1 -Connector_PinSocket_2.54mm -PinSocket_1x02_P2.54mm_Horizontal -Through hole angled socket strip, 1x02, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x02 2.54mm single row -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_1x02_P2.54mm_Vertical -Through hole straight socket strip, 1x02, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x02 2.54mm single row -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x02 2.54mm single row style1 pin1 left -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x02 2.54mm single row style2 pin1 right -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_1x03_P2.54mm_Horizontal -Through hole angled socket strip, 1x03, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x03 2.54mm single row -0 -3 -3 -Connector_PinSocket_2.54mm -PinSocket_1x03_P2.54mm_Vertical -Through hole straight socket strip, 1x03, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x03 2.54mm single row -0 -3 -3 -Connector_PinSocket_2.54mm -PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x03 2.54mm single row style1 pin1 left -0 -3 -3 -Connector_PinSocket_2.54mm -PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x03 2.54mm single row style2 pin1 right -0 -3 -3 -Connector_PinSocket_2.54mm -PinSocket_1x04_P2.54mm_Horizontal -Through hole angled socket strip, 1x04, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x04 2.54mm single row -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_1x04_P2.54mm_Vertical -Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x04 2.54mm single row -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x04 2.54mm single row style1 pin1 left -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x04 2.54mm single row style2 pin1 right -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_1x05_P2.54mm_Horizontal -Through hole angled socket strip, 1x05, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x05 2.54mm single row -0 -5 -5 -Connector_PinSocket_2.54mm -PinSocket_1x05_P2.54mm_Vertical -Through hole straight socket strip, 1x05, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x05 2.54mm single row -0 -5 -5 -Connector_PinSocket_2.54mm -PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x05 2.54mm single row style1 pin1 left -0 -5 -5 -Connector_PinSocket_2.54mm -PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x05 2.54mm single row style2 pin1 right -0 -5 -5 -Connector_PinSocket_2.54mm -PinSocket_1x06_P2.54mm_Horizontal -Through hole angled socket strip, 1x06, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x06 2.54mm single row -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_1x06_P2.54mm_Vertical -Through hole straight socket strip, 1x06, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x06 2.54mm single row -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x06 2.54mm single row style1 pin1 left -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x06 2.54mm single row style2 pin1 right -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_1x07_P2.54mm_Horizontal -Through hole angled socket strip, 1x07, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x07 2.54mm single row -0 -7 -7 -Connector_PinSocket_2.54mm -PinSocket_1x07_P2.54mm_Vertical -Through hole straight socket strip, 1x07, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x07 2.54mm single row -0 -7 -7 -Connector_PinSocket_2.54mm -PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x07 2.54mm single row style1 pin1 left -0 -7 -7 -Connector_PinSocket_2.54mm -PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x07 2.54mm single row style2 pin1 right -0 -7 -7 -Connector_PinSocket_2.54mm -PinSocket_1x08_P2.54mm_Horizontal -Through hole angled socket strip, 1x08, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x08 2.54mm single row -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_1x08_P2.54mm_Vertical -Through hole straight socket strip, 1x08, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x08 2.54mm single row -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x08 2.54mm single row style1 pin1 left -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x08 2.54mm single row style2 pin1 right -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_1x09_P2.54mm_Horizontal -Through hole angled socket strip, 1x09, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x09 2.54mm single row -0 -9 -9 -Connector_PinSocket_2.54mm -PinSocket_1x09_P2.54mm_Vertical -Through hole straight socket strip, 1x09, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x09 2.54mm single row -0 -9 -9 -Connector_PinSocket_2.54mm -PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x09 2.54mm single row style1 pin1 left -0 -9 -9 -Connector_PinSocket_2.54mm -PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x09 2.54mm single row style2 pin1 right -0 -9 -9 -Connector_PinSocket_2.54mm -PinSocket_1x10_P2.54mm_Horizontal -Through hole angled socket strip, 1x10, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x10 2.54mm single row -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_1x10_P2.54mm_Vertical -Through hole straight socket strip, 1x10, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x10 2.54mm single row -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x10 2.54mm single row style1 pin1 left -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x10 2.54mm single row style2 pin1 right -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_1x11_P2.54mm_Horizontal -Through hole angled socket strip, 1x11, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x11 2.54mm single row -0 -11 -11 -Connector_PinSocket_2.54mm -PinSocket_1x11_P2.54mm_Vertical -Through hole straight socket strip, 1x11, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x11 2.54mm single row -0 -11 -11 -Connector_PinSocket_2.54mm -PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x11 2.54mm single row style1 pin1 left -0 -11 -11 -Connector_PinSocket_2.54mm -PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x11 2.54mm single row style2 pin1 right -0 -11 -11 -Connector_PinSocket_2.54mm -PinSocket_1x12_P2.54mm_Horizontal -Through hole angled socket strip, 1x12, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x12 2.54mm single row -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_1x12_P2.54mm_Vertical -Through hole straight socket strip, 1x12, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x12 2.54mm single row -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x12 2.54mm single row style1 pin1 left -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x12 2.54mm single row style2 pin1 right -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_1x13_P2.54mm_Horizontal -Through hole angled socket strip, 1x13, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x13 2.54mm single row -0 -13 -13 -Connector_PinSocket_2.54mm -PinSocket_1x13_P2.54mm_Vertical -Through hole straight socket strip, 1x13, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x13 2.54mm single row -0 -13 -13 -Connector_PinSocket_2.54mm -PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x13 2.54mm single row style1 pin1 left -0 -13 -13 -Connector_PinSocket_2.54mm -PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x13 2.54mm single row style2 pin1 right -0 -13 -13 -Connector_PinSocket_2.54mm -PinSocket_1x14_P2.54mm_Horizontal -Through hole angled socket strip, 1x14, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x14 2.54mm single row -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_1x14_P2.54mm_Vertical -Through hole straight socket strip, 1x14, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x14 2.54mm single row -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x14 2.54mm single row style1 pin1 left -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x14 2.54mm single row style2 pin1 right -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_1x15_P2.54mm_Horizontal -Through hole angled socket strip, 1x15, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x15 2.54mm single row -0 -15 -15 -Connector_PinSocket_2.54mm -PinSocket_1x15_P2.54mm_Vertical -Through hole straight socket strip, 1x15, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x15 2.54mm single row -0 -15 -15 -Connector_PinSocket_2.54mm -PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x15 2.54mm single row style1 pin1 left -0 -15 -15 -Connector_PinSocket_2.54mm -PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x15 2.54mm single row style2 pin1 right -0 -15 -15 -Connector_PinSocket_2.54mm -PinSocket_1x16_P2.54mm_Horizontal -Through hole angled socket strip, 1x16, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x16 2.54mm single row -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_1x16_P2.54mm_Vertical -Through hole straight socket strip, 1x16, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x16 2.54mm single row -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x16 2.54mm single row style1 pin1 left -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x16 2.54mm single row style2 pin1 right -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_1x17_P2.54mm_Horizontal -Through hole angled socket strip, 1x17, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x17 2.54mm single row -0 -17 -17 -Connector_PinSocket_2.54mm -PinSocket_1x17_P2.54mm_Vertical -Through hole straight socket strip, 1x17, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x17 2.54mm single row -0 -17 -17 -Connector_PinSocket_2.54mm -PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x17 2.54mm single row style1 pin1 left -0 -17 -17 -Connector_PinSocket_2.54mm -PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x17 2.54mm single row style2 pin1 right -0 -17 -17 -Connector_PinSocket_2.54mm -PinSocket_1x18_P2.54mm_Horizontal -Through hole angled socket strip, 1x18, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x18 2.54mm single row -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_1x18_P2.54mm_Vertical -Through hole straight socket strip, 1x18, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x18 2.54mm single row -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x18 2.54mm single row style1 pin1 left -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x18 2.54mm single row style2 pin1 right -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_1x19_P2.54mm_Horizontal -Through hole angled socket strip, 1x19, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x19 2.54mm single row -0 -19 -19 -Connector_PinSocket_2.54mm -PinSocket_1x19_P2.54mm_Vertical -Through hole straight socket strip, 1x19, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x19 2.54mm single row -0 -19 -19 -Connector_PinSocket_2.54mm -PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x19 2.54mm single row style1 pin1 left -0 -19 -19 -Connector_PinSocket_2.54mm -PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x19 2.54mm single row style2 pin1 right -0 -19 -19 -Connector_PinSocket_2.54mm -PinSocket_1x20_P2.54mm_Horizontal -Through hole angled socket strip, 1x20, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x20 2.54mm single row -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_1x20_P2.54mm_Vertical -Through hole straight socket strip, 1x20, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x20 2.54mm single row -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x20 2.54mm single row style1 pin1 left -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x20 2.54mm single row style2 pin1 right -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_1x21_P2.54mm_Horizontal -Through hole angled socket strip, 1x21, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x21 2.54mm single row -0 -21 -21 -Connector_PinSocket_2.54mm -PinSocket_1x21_P2.54mm_Vertical -Through hole straight socket strip, 1x21, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x21 2.54mm single row -0 -21 -21 -Connector_PinSocket_2.54mm -PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x21 2.54mm single row style1 pin1 left -0 -21 -21 -Connector_PinSocket_2.54mm -PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x21 2.54mm single row style2 pin1 right -0 -21 -21 -Connector_PinSocket_2.54mm -PinSocket_1x22_P2.54mm_Horizontal -Through hole angled socket strip, 1x22, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x22 2.54mm single row -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_1x22_P2.54mm_Vertical -Through hole straight socket strip, 1x22, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x22 2.54mm single row -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x22 2.54mm single row style1 pin1 left -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x22 2.54mm single row style2 pin1 right -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_1x23_P2.54mm_Horizontal -Through hole angled socket strip, 1x23, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x23 2.54mm single row -0 -23 -23 -Connector_PinSocket_2.54mm -PinSocket_1x23_P2.54mm_Vertical -Through hole straight socket strip, 1x23, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x23 2.54mm single row -0 -23 -23 -Connector_PinSocket_2.54mm -PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x23 2.54mm single row style1 pin1 left -0 -23 -23 -Connector_PinSocket_2.54mm -PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x23 2.54mm single row style2 pin1 right -0 -23 -23 -Connector_PinSocket_2.54mm -PinSocket_1x24_P2.54mm_Horizontal -Through hole angled socket strip, 1x24, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x24 2.54mm single row -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_1x24_P2.54mm_Vertical -Through hole straight socket strip, 1x24, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x24 2.54mm single row -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x24 2.54mm single row style1 pin1 left -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x24 2.54mm single row style2 pin1 right -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_1x25_P2.54mm_Horizontal -Through hole angled socket strip, 1x25, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x25 2.54mm single row -0 -25 -25 -Connector_PinSocket_2.54mm -PinSocket_1x25_P2.54mm_Vertical -Through hole straight socket strip, 1x25, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x25 2.54mm single row -0 -25 -25 -Connector_PinSocket_2.54mm -PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x25 2.54mm single row style1 pin1 left -0 -25 -25 -Connector_PinSocket_2.54mm -PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x25 2.54mm single row style2 pin1 right -0 -25 -25 -Connector_PinSocket_2.54mm -PinSocket_1x26_P2.54mm_Horizontal -Through hole angled socket strip, 1x26, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x26 2.54mm single row -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_1x26_P2.54mm_Vertical -Through hole straight socket strip, 1x26, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x26 2.54mm single row -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x26 2.54mm single row style1 pin1 left -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x26 2.54mm single row style2 pin1 right -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_1x27_P2.54mm_Horizontal -Through hole angled socket strip, 1x27, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x27 2.54mm single row -0 -27 -27 -Connector_PinSocket_2.54mm -PinSocket_1x27_P2.54mm_Vertical -Through hole straight socket strip, 1x27, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x27 2.54mm single row -0 -27 -27 -Connector_PinSocket_2.54mm -PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x27 2.54mm single row style1 pin1 left -0 -27 -27 -Connector_PinSocket_2.54mm -PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x27 2.54mm single row style2 pin1 right -0 -27 -27 -Connector_PinSocket_2.54mm -PinSocket_1x28_P2.54mm_Horizontal -Through hole angled socket strip, 1x28, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x28 2.54mm single row -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_1x28_P2.54mm_Vertical -Through hole straight socket strip, 1x28, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x28 2.54mm single row -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x28 2.54mm single row style1 pin1 left -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x28 2.54mm single row style2 pin1 right -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_1x29_P2.54mm_Horizontal -Through hole angled socket strip, 1x29, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x29 2.54mm single row -0 -29 -29 -Connector_PinSocket_2.54mm -PinSocket_1x29_P2.54mm_Vertical -Through hole straight socket strip, 1x29, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x29 2.54mm single row -0 -29 -29 -Connector_PinSocket_2.54mm -PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x29 2.54mm single row style1 pin1 left -0 -29 -29 -Connector_PinSocket_2.54mm -PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x29 2.54mm single row style2 pin1 right -0 -29 -29 -Connector_PinSocket_2.54mm -PinSocket_1x30_P2.54mm_Horizontal -Through hole angled socket strip, 1x30, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x30 2.54mm single row -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_1x30_P2.54mm_Vertical -Through hole straight socket strip, 1x30, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x30 2.54mm single row -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x30 2.54mm single row style1 pin1 left -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x30 2.54mm single row style2 pin1 right -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_1x31_P2.54mm_Horizontal -Through hole angled socket strip, 1x31, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x31 2.54mm single row -0 -31 -31 -Connector_PinSocket_2.54mm -PinSocket_1x31_P2.54mm_Vertical -Through hole straight socket strip, 1x31, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x31 2.54mm single row -0 -31 -31 -Connector_PinSocket_2.54mm -PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x31 2.54mm single row style1 pin1 left -0 -31 -31 -Connector_PinSocket_2.54mm -PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x31 2.54mm single row style2 pin1 right -0 -31 -31 -Connector_PinSocket_2.54mm -PinSocket_1x32_P2.54mm_Horizontal -Through hole angled socket strip, 1x32, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x32 2.54mm single row -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_1x32_P2.54mm_Vertical -Through hole straight socket strip, 1x32, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x32 2.54mm single row -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x32 2.54mm single row style1 pin1 left -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x32 2.54mm single row style2 pin1 right -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_1x33_P2.54mm_Horizontal -Through hole angled socket strip, 1x33, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x33 2.54mm single row -0 -33 -33 -Connector_PinSocket_2.54mm -PinSocket_1x33_P2.54mm_Vertical -Through hole straight socket strip, 1x33, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x33 2.54mm single row -0 -33 -33 -Connector_PinSocket_2.54mm -PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x33 2.54mm single row style1 pin1 left -0 -33 -33 -Connector_PinSocket_2.54mm -PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x33 2.54mm single row style2 pin1 right -0 -33 -33 -Connector_PinSocket_2.54mm -PinSocket_1x34_P2.54mm_Horizontal -Through hole angled socket strip, 1x34, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x34 2.54mm single row -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_1x34_P2.54mm_Vertical -Through hole straight socket strip, 1x34, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x34 2.54mm single row -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x34 2.54mm single row style1 pin1 left -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x34 2.54mm single row style2 pin1 right -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_1x35_P2.54mm_Horizontal -Through hole angled socket strip, 1x35, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x35 2.54mm single row -0 -35 -35 -Connector_PinSocket_2.54mm -PinSocket_1x35_P2.54mm_Vertical -Through hole straight socket strip, 1x35, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x35 2.54mm single row -0 -35 -35 -Connector_PinSocket_2.54mm -PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x35 2.54mm single row style1 pin1 left -0 -35 -35 -Connector_PinSocket_2.54mm -PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x35 2.54mm single row style2 pin1 right -0 -35 -35 -Connector_PinSocket_2.54mm -PinSocket_1x36_P2.54mm_Horizontal -Through hole angled socket strip, 1x36, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x36 2.54mm single row -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_1x36_P2.54mm_Vertical -Through hole straight socket strip, 1x36, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x36 2.54mm single row -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x36 2.54mm single row style1 pin1 left -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x36 2.54mm single row style2 pin1 right -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_1x37_P2.54mm_Horizontal -Through hole angled socket strip, 1x37, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x37 2.54mm single row -0 -37 -37 -Connector_PinSocket_2.54mm -PinSocket_1x37_P2.54mm_Vertical -Through hole straight socket strip, 1x37, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x37 2.54mm single row -0 -37 -37 -Connector_PinSocket_2.54mm -PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x37 2.54mm single row style1 pin1 left -0 -37 -37 -Connector_PinSocket_2.54mm -PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x37 2.54mm single row style2 pin1 right -0 -37 -37 -Connector_PinSocket_2.54mm -PinSocket_1x38_P2.54mm_Horizontal -Through hole angled socket strip, 1x38, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x38 2.54mm single row -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_1x38_P2.54mm_Vertical -Through hole straight socket strip, 1x38, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x38 2.54mm single row -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x38 2.54mm single row style1 pin1 left -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x38 2.54mm single row style2 pin1 right -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_1x39_P2.54mm_Horizontal -Through hole angled socket strip, 1x39, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x39 2.54mm single row -0 -39 -39 -Connector_PinSocket_2.54mm -PinSocket_1x39_P2.54mm_Vertical -Through hole straight socket strip, 1x39, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x39 2.54mm single row -0 -39 -39 -Connector_PinSocket_2.54mm -PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x39 2.54mm single row style1 pin1 left -0 -39 -39 -Connector_PinSocket_2.54mm -PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x39 2.54mm single row style2 pin1 right -0 -39 -39 -Connector_PinSocket_2.54mm -PinSocket_1x40_P2.54mm_Horizontal -Through hole angled socket strip, 1x40, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 1x40 2.54mm single row -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_1x40_P2.54mm_Vertical -Through hole straight socket strip, 1x40, 2.54mm pitch, single row (from Kicad 4.0.7), script generated -Through hole socket strip THT 1x40 2.54mm single row -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Left -surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x40 2.54mm single row style1 pin1 left -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Right -surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated -Surface mounted socket strip SMD 1x40 2.54mm single row style2 pin1 right -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_2x01_P2.54mm_Horizontal -Through hole angled socket strip, 2x01, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x01 2.54mm double row -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_2x01_P2.54mm_Vertical -Through hole straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x01 2.54mm double row -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_2x01_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x01 2.54mm double row -0 -2 -2 -Connector_PinSocket_2.54mm -PinSocket_2x02_P2.54mm_Horizontal -Through hole angled socket strip, 2x02, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x02 2.54mm double row -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_2x02_P2.54mm_Vertical -Through hole straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x02 2.54mm double row -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_2x02_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x02 2.54mm double row -0 -4 -4 -Connector_PinSocket_2.54mm -PinSocket_2x03_P2.54mm_Horizontal -Through hole angled socket strip, 2x03, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x03 2.54mm double row -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_2x03_P2.54mm_Vertical -Through hole straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x03 2.54mm double row -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_2x03_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x03 2.54mm double row -0 -6 -6 -Connector_PinSocket_2.54mm -PinSocket_2x04_P2.54mm_Horizontal -Through hole angled socket strip, 2x04, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x04 2.54mm double row -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_2x04_P2.54mm_Vertical -Through hole straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x04 2.54mm double row -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_2x04_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x04 2.54mm double row -0 -8 -8 -Connector_PinSocket_2.54mm -PinSocket_2x05_P2.54mm_Horizontal -Through hole angled socket strip, 2x05, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x05 2.54mm double row -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_2x05_P2.54mm_Vertical -Through hole straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x05 2.54mm double row -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_2x05_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x05 2.54mm double row -0 -10 -10 -Connector_PinSocket_2.54mm -PinSocket_2x06_P2.54mm_Horizontal -Through hole angled socket strip, 2x06, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x06 2.54mm double row -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_2x06_P2.54mm_Vertical -Through hole straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x06 2.54mm double row -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_2x06_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x06 2.54mm double row -0 -12 -12 -Connector_PinSocket_2.54mm -PinSocket_2x07_P2.54mm_Horizontal -Through hole angled socket strip, 2x07, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x07 2.54mm double row -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_2x07_P2.54mm_Vertical -Through hole straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x07 2.54mm double row -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_2x07_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x07 2.54mm double row -0 -14 -14 -Connector_PinSocket_2.54mm -PinSocket_2x08_P2.54mm_Horizontal -Through hole angled socket strip, 2x08, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x08 2.54mm double row -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_2x08_P2.54mm_Vertical -Through hole straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x08 2.54mm double row -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_2x08_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x08 2.54mm double row -0 -16 -16 -Connector_PinSocket_2.54mm -PinSocket_2x09_P2.54mm_Horizontal -Through hole angled socket strip, 2x09, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x09 2.54mm double row -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_2x09_P2.54mm_Vertical -Through hole straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x09 2.54mm double row -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_2x09_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x09 2.54mm double row -0 -18 -18 -Connector_PinSocket_2.54mm -PinSocket_2x10_P2.54mm_Horizontal -Through hole angled socket strip, 2x10, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x10 2.54mm double row -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_2x10_P2.54mm_Vertical -Through hole straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x10 2.54mm double row -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_2x10_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x10 2.54mm double row -0 -20 -20 -Connector_PinSocket_2.54mm -PinSocket_2x11_P2.54mm_Horizontal -Through hole angled socket strip, 2x11, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x11 2.54mm double row -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_2x11_P2.54mm_Vertical -Through hole straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x11 2.54mm double row -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_2x11_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x11 2.54mm double row -0 -22 -22 -Connector_PinSocket_2.54mm -PinSocket_2x12_P2.54mm_Horizontal -Through hole angled socket strip, 2x12, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x12 2.54mm double row -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_2x12_P2.54mm_Vertical -Through hole straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x12 2.54mm double row -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_2x12_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x12 2.54mm double row -0 -24 -24 -Connector_PinSocket_2.54mm -PinSocket_2x13_P2.54mm_Horizontal -Through hole angled socket strip, 2x13, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x13 2.54mm double row -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_2x13_P2.54mm_Vertical -Through hole straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x13 2.54mm double row -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_2x13_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x13 2.54mm double row -0 -26 -26 -Connector_PinSocket_2.54mm -PinSocket_2x14_P2.54mm_Horizontal -Through hole angled socket strip, 2x14, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x14 2.54mm double row -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_2x14_P2.54mm_Vertical -Through hole straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x14 2.54mm double row -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_2x14_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x14 2.54mm double row -0 -28 -28 -Connector_PinSocket_2.54mm -PinSocket_2x15_P2.54mm_Horizontal -Through hole angled socket strip, 2x15, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x15 2.54mm double row -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_2x15_P2.54mm_Vertical -Through hole straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x15 2.54mm double row -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_2x15_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x15 2.54mm double row -0 -30 -30 -Connector_PinSocket_2.54mm -PinSocket_2x16_P2.54mm_Horizontal -Through hole angled socket strip, 2x16, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x16 2.54mm double row -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_2x16_P2.54mm_Vertical -Through hole straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x16 2.54mm double row -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_2x16_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x16 2.54mm double row -0 -32 -32 -Connector_PinSocket_2.54mm -PinSocket_2x17_P2.54mm_Horizontal -Through hole angled socket strip, 2x17, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x17 2.54mm double row -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_2x17_P2.54mm_Vertical -Through hole straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x17 2.54mm double row -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_2x17_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x17 2.54mm double row -0 -34 -34 -Connector_PinSocket_2.54mm -PinSocket_2x18_P2.54mm_Horizontal -Through hole angled socket strip, 2x18, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x18 2.54mm double row -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_2x18_P2.54mm_Vertical -Through hole straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x18 2.54mm double row -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_2x18_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x18 2.54mm double row -0 -36 -36 -Connector_PinSocket_2.54mm -PinSocket_2x19_P2.54mm_Horizontal -Through hole angled socket strip, 2x19, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x19 2.54mm double row -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_2x19_P2.54mm_Vertical -Through hole straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x19 2.54mm double row -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_2x19_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x19 2.54mm double row -0 -38 -38 -Connector_PinSocket_2.54mm -PinSocket_2x20_P2.54mm_Horizontal -Through hole angled socket strip, 2x20, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x20 2.54mm double row -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_2x20_P2.54mm_Vertical -Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x20 2.54mm double row -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_2x20_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x20 2.54mm double row -0 -40 -40 -Connector_PinSocket_2.54mm -PinSocket_2x21_P2.54mm_Horizontal -Through hole angled socket strip, 2x21, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x21 2.54mm double row -0 -42 -42 -Connector_PinSocket_2.54mm -PinSocket_2x21_P2.54mm_Vertical -Through hole straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x21 2.54mm double row -0 -42 -42 -Connector_PinSocket_2.54mm -PinSocket_2x21_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x21 2.54mm double row -0 -42 -42 -Connector_PinSocket_2.54mm -PinSocket_2x22_P2.54mm_Horizontal -Through hole angled socket strip, 2x22, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x22 2.54mm double row -0 -44 -44 -Connector_PinSocket_2.54mm -PinSocket_2x22_P2.54mm_Vertical -Through hole straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x22 2.54mm double row -0 -44 -44 -Connector_PinSocket_2.54mm -PinSocket_2x22_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x22 2.54mm double row -0 -44 -44 -Connector_PinSocket_2.54mm -PinSocket_2x23_P2.54mm_Horizontal -Through hole angled socket strip, 2x23, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x23 2.54mm double row -0 -46 -46 -Connector_PinSocket_2.54mm -PinSocket_2x23_P2.54mm_Vertical -Through hole straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x23 2.54mm double row -0 -46 -46 -Connector_PinSocket_2.54mm -PinSocket_2x23_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x23 2.54mm double row -0 -46 -46 -Connector_PinSocket_2.54mm -PinSocket_2x24_P2.54mm_Horizontal -Through hole angled socket strip, 2x24, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x24 2.54mm double row -0 -48 -48 -Connector_PinSocket_2.54mm -PinSocket_2x24_P2.54mm_Vertical -Through hole straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x24 2.54mm double row -0 -48 -48 -Connector_PinSocket_2.54mm -PinSocket_2x24_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x24 2.54mm double row -0 -48 -48 -Connector_PinSocket_2.54mm -PinSocket_2x25_P2.54mm_Horizontal -Through hole angled socket strip, 2x25, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x25 2.54mm double row -0 -50 -50 -Connector_PinSocket_2.54mm -PinSocket_2x25_P2.54mm_Vertical -Through hole straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x25 2.54mm double row -0 -50 -50 -Connector_PinSocket_2.54mm -PinSocket_2x25_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x25 2.54mm double row -0 -50 -50 -Connector_PinSocket_2.54mm -PinSocket_2x26_P2.54mm_Horizontal -Through hole angled socket strip, 2x26, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x26 2.54mm double row -0 -52 -52 -Connector_PinSocket_2.54mm -PinSocket_2x26_P2.54mm_Vertical -Through hole straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x26 2.54mm double row -0 -52 -52 -Connector_PinSocket_2.54mm -PinSocket_2x26_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x26 2.54mm double row -0 -52 -52 -Connector_PinSocket_2.54mm -PinSocket_2x27_P2.54mm_Horizontal -Through hole angled socket strip, 2x27, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x27 2.54mm double row -0 -54 -54 -Connector_PinSocket_2.54mm -PinSocket_2x27_P2.54mm_Vertical -Through hole straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x27 2.54mm double row -0 -54 -54 -Connector_PinSocket_2.54mm -PinSocket_2x27_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x27 2.54mm double row -0 -54 -54 -Connector_PinSocket_2.54mm -PinSocket_2x28_P2.54mm_Horizontal -Through hole angled socket strip, 2x28, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x28 2.54mm double row -0 -56 -56 -Connector_PinSocket_2.54mm -PinSocket_2x28_P2.54mm_Vertical -Through hole straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x28 2.54mm double row -0 -56 -56 -Connector_PinSocket_2.54mm -PinSocket_2x28_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x28 2.54mm double row -0 -56 -56 -Connector_PinSocket_2.54mm -PinSocket_2x29_P2.54mm_Horizontal -Through hole angled socket strip, 2x29, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x29 2.54mm double row -0 -58 -58 -Connector_PinSocket_2.54mm -PinSocket_2x29_P2.54mm_Vertical -Through hole straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x29 2.54mm double row -0 -58 -58 -Connector_PinSocket_2.54mm -PinSocket_2x29_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x29 2.54mm double row -0 -58 -58 -Connector_PinSocket_2.54mm -PinSocket_2x30_P2.54mm_Horizontal -Through hole angled socket strip, 2x30, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x30 2.54mm double row -0 -60 -60 -Connector_PinSocket_2.54mm -PinSocket_2x30_P2.54mm_Vertical -Through hole straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x30 2.54mm double row -0 -60 -60 -Connector_PinSocket_2.54mm -PinSocket_2x30_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x30 2.54mm double row -0 -60 -60 -Connector_PinSocket_2.54mm -PinSocket_2x31_P2.54mm_Horizontal -Through hole angled socket strip, 2x31, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x31 2.54mm double row -0 -62 -62 -Connector_PinSocket_2.54mm -PinSocket_2x31_P2.54mm_Vertical -Through hole straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x31 2.54mm double row -0 -62 -62 -Connector_PinSocket_2.54mm -PinSocket_2x31_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x31 2.54mm double row -0 -62 -62 -Connector_PinSocket_2.54mm -PinSocket_2x32_P2.54mm_Horizontal -Through hole angled socket strip, 2x32, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x32 2.54mm double row -0 -64 -64 -Connector_PinSocket_2.54mm -PinSocket_2x32_P2.54mm_Vertical -Through hole straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x32 2.54mm double row -0 -64 -64 -Connector_PinSocket_2.54mm -PinSocket_2x32_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x32 2.54mm double row -0 -64 -64 -Connector_PinSocket_2.54mm -PinSocket_2x33_P2.54mm_Horizontal -Through hole angled socket strip, 2x33, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x33 2.54mm double row -0 -66 -66 -Connector_PinSocket_2.54mm -PinSocket_2x33_P2.54mm_Vertical -Through hole straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x33 2.54mm double row -0 -66 -66 -Connector_PinSocket_2.54mm -PinSocket_2x33_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x33 2.54mm double row -0 -66 -66 -Connector_PinSocket_2.54mm -PinSocket_2x34_P2.54mm_Horizontal -Through hole angled socket strip, 2x34, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x34 2.54mm double row -0 -68 -68 -Connector_PinSocket_2.54mm -PinSocket_2x34_P2.54mm_Vertical -Through hole straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x34 2.54mm double row -0 -68 -68 -Connector_PinSocket_2.54mm -PinSocket_2x34_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x34 2.54mm double row -0 -68 -68 -Connector_PinSocket_2.54mm -PinSocket_2x35_P2.54mm_Horizontal -Through hole angled socket strip, 2x35, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x35 2.54mm double row -0 -70 -70 -Connector_PinSocket_2.54mm -PinSocket_2x35_P2.54mm_Vertical -Through hole straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x35 2.54mm double row -0 -70 -70 -Connector_PinSocket_2.54mm -PinSocket_2x35_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x35 2.54mm double row -0 -70 -70 -Connector_PinSocket_2.54mm -PinSocket_2x36_P2.54mm_Horizontal -Through hole angled socket strip, 2x36, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x36 2.54mm double row -0 -72 -72 -Connector_PinSocket_2.54mm -PinSocket_2x36_P2.54mm_Vertical -Through hole straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x36 2.54mm double row -0 -72 -72 -Connector_PinSocket_2.54mm -PinSocket_2x36_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x36 2.54mm double row -0 -72 -72 -Connector_PinSocket_2.54mm -PinSocket_2x37_P2.54mm_Horizontal -Through hole angled socket strip, 2x37, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x37 2.54mm double row -0 -74 -74 -Connector_PinSocket_2.54mm -PinSocket_2x37_P2.54mm_Vertical -Through hole straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x37 2.54mm double row -0 -74 -74 -Connector_PinSocket_2.54mm -PinSocket_2x37_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x37 2.54mm double row -0 -74 -74 -Connector_PinSocket_2.54mm -PinSocket_2x38_P2.54mm_Horizontal -Through hole angled socket strip, 2x38, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x38 2.54mm double row -0 -76 -76 -Connector_PinSocket_2.54mm -PinSocket_2x38_P2.54mm_Vertical -Through hole straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x38 2.54mm double row -0 -76 -76 -Connector_PinSocket_2.54mm -PinSocket_2x38_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x38 2.54mm double row -0 -76 -76 -Connector_PinSocket_2.54mm -PinSocket_2x39_P2.54mm_Horizontal -Through hole angled socket strip, 2x39, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x39 2.54mm double row -0 -78 -78 -Connector_PinSocket_2.54mm -PinSocket_2x39_P2.54mm_Vertical -Through hole straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x39 2.54mm double row -0 -78 -78 -Connector_PinSocket_2.54mm -PinSocket_2x39_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x39 2.54mm double row -0 -78 -78 -Connector_PinSocket_2.54mm -PinSocket_2x40_P2.54mm_Horizontal -Through hole angled socket strip, 2x40, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated -Through hole angled socket strip THT 2x40 2.54mm double row -0 -80 -80 -Connector_PinSocket_2.54mm -PinSocket_2x40_P2.54mm_Vertical -Through hole straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Through hole socket strip THT 2x40 2.54mm double row -0 -80 -80 -Connector_PinSocket_2.54mm -PinSocket_2x40_P2.54mm_Vertical_SMD -surface-mounted straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated -Surface mounted socket strip SMD 2x40 2.54mm double row -0 -80 -80 -Connector_RJ -RJ12_Amphenol_54601 -RJ12 connector https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0082.pdf -RJ12 connector -0 -6 -6 -Connector_RJ -RJ25_Wayconn_MJEA-660X1_Horizontal -RJ25 6P6C Socket 90 degrees, https://wayconn.com/wp-content/themes/way/datasheet/MJEA-660X1XXX_RJ25_6P6C_PCB_RA.pdf -RJ12 RJ18 RJ25 jack connector 6P6C -0 -6 -6 -Connector_RJ -RJ45_Abracon_ARJP11A-MA_Horizontal -Shielded RJ45 ethernet connector with transformer and POE (https://abracon.com/Magnetics/lan/ARJP11A.PDF) -ethernet 8p8c transformer poe rj45 -0 -15 -14 -Connector_RJ -RJ45_Amphenol_54602-x08_Horizontal -8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf) -RJ45 -0 -8 -8 -Connector_RJ -RJ45_Amphenol_RJHSE538X -Shielded, 2 LED, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf -RJ45 8p8c ethernet cat5 -0 -14 -13 -Connector_RJ -RJ45_Amphenol_RJHSE538X-02 -Shielded, 2 LED, 2 Ports, http://www.amphenolinfocom.eu/NavData/Drawings/RJHSE-538X-02-REVC.pdf -RJ45 8p8c dual ethernet cat5 -0 -26 -25 -Connector_RJ -RJ45_Amphenol_RJHSE5380 -Shielded, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf -RJ45 8p8c ethernet cat5 -0 -10 -9 -Connector_RJ -RJ45_Amphenol_RJHSE5380-08 -Shielded, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X08.pdf -RJ45 8p8c ethernet cat5 -0 -68 -65 -Connector_RJ -RJ45_Amphenol_RJMG1BD3B8K1ANR -1 Port RJ45 Magjack Connector Through Hole 10/100 Base-T, AutoMDIX, https://www.amphenolcanada.com/ProductSearch/Drawings/AC/RJMG1BD3B8K1ANR.PDF -RJ45 Magjack -0 -14 -13 -Connector_RJ -RJ45_BEL_SS74301-00x_Vertical -https://belfuse.com/resources/drawings/stewartconnector/dr-stw-ss-74301-001-ss-74301-002-ss-74301-005.pdf -RJ45 Vertical Shield LED Green Yellow -0 -14 -13 -Connector_RJ -RJ45_Cetus_J1B1211CCD_Horizontal -1 Port RJ45 Magjack Connector Through Hole 10/100 Base-T, Cetus, used and distributed by WIZnet (https://wizwiki.net/wiki/lib/exe/fetch.php?media=products:wiz550web:wiz550webds_kr:j1b1211ccd.pdf) -RJ45 Magjack -0 -14 -13 -Connector_RJ -RJ45_Hanrun_HR911105A -http://www.kosmodrom.com.ua/pdf/HR911105A.pdf -RJ45 Magjack -0 -14 -13 -Connector_RJ -RJ45_OST_PJ012-8P8CX_Vertical -RJ45 vertical connector http://www.on-shore.com/wp-content/uploads/2015/09/PJ012-8P8CX.pdf -RJ45 PJ012 -0 -8 -8 -Connector_RJ -RJ45_Plug_Metz_AJP92A8813 -plug, ethernet, 8P8C, RJ45 Plug -AJP92A8813 8P8C RJ45 ethernet plug -0 -8 -8 -Connector_RJ -RJ45_Pulse_JK0654219NL_Horizontal -10/100/1000 Base-T RJ45 single port with LEDs https://media.digikey.com/pdf/Data%20Sheets/Pulse%20PDFs/JK%20Series.pdf#page=2 -RJ45 8p8c ethernet -0 -18 -17 -Connector_RJ -RJ45_Pulse_JXD6-0001NL_Horizontal -RJ45 ethernet transformer with magnetics (https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/JXD6-0001NL/doc_part/JXD6-0001NL.pdf) -ethernet 8p8c transformer magjack -0 -12 -11 -Connector_RJ -RJ45_Wuerth_7499010121A_Horizontal -10/100Base-TX RJ45 ethernet magnetic transformer connector horizontal https://katalog.we-online.de/pbs/datasheet/7499010121A.pdf -RJ45 ethernet magnetic -0 -14 -13 -Connector_RJ -RJ45_Wuerth_7499151120_Horizontal -Wuerth 7499151120, LAN-Transformer WE-RJ45LAN 10/100/1000 BaseT, Dual Ethernet Jack (http://katalog.we-online.de/pbs/datasheet/7499151120.pdf) -ethernet lan connector -0 -32 -29 -Connector_RJ -RJ45_Wuerth_74980111211_Horizontal -RJ45 LAN Transformer 10/100BaseT (https://katalog.we-online.de/pbs/datasheet/74980111211.pdf) -lan magnetics transformer -0 -14 -13 -Connector_SATA_SAS -SAS-mini_TEConnectivity_1888174_Vertical -36pin mini SAS connector, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=1888174&DocType=Customer+Drawing&DocLang=English -SAS mini connector -0 -44 -44 -Connector_SATA_SAS -SATA_Amphenol_10029364-001LF_Horizontal -https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10029364.pdf -SATA -0 -24 -23 -Connector_Samtec -Samtec_FMC_ASP-134486-01_10x40_P1.27mm_Vertical -http://suddendocs.samtec.com/prints/asp-134486-01-mkt.pdf -FMC HPC -0 -400 -400 -Connector_Samtec -Samtec_FMC_ASP-134602-01_10x40_P1.27mm_Vertical -https://www.marutsu.co.jp/contents/shop/marutsu/ds/asp-134602-01.pdf -FMC HPC -0 -400 -400 -Connector_Samtec -Samtec_FMC_ASP-134604-01_4x40_Vertical -http://www.samtec.com/standards/vita.aspx -FMC LPC VITA -0 -162 -160 -Connector_Samtec -Samtec_LSHM-105-xx.x-x-DV-N_2x05_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-105-xx.x-x-DV-N, 5 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -10 -10 -Connector_Samtec -Samtec_LSHM-105-xx.x-x-DV-S_2x05-1SH_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-105-xx.x-x-DV-S, 5 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -12 -11 -Connector_Samtec -Samtec_LSHM-110-xx.x-x-DV-N_2x10_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-110-xx.x-x-DV-N, 10 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -20 -20 -Connector_Samtec -Samtec_LSHM-110-xx.x-x-DV-S_2x10-1SH_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-110-xx.x-x-DV-S, 10 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -22 -21 -Connector_Samtec -Samtec_LSHM-120-xx.x-x-DV-N_2x20_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-120-xx.x-x-DV-N, 20 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -40 -40 -Connector_Samtec -Samtec_LSHM-120-xx.x-x-DV-S_2x20-1SH_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-120-xx.x-x-DV-S, 20 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -42 -41 -Connector_Samtec -Samtec_LSHM-130-xx.x-x-DV-N_2x30_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-130-xx.x-x-DV-N, 30 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -60 -60 -Connector_Samtec -Samtec_LSHM-130-xx.x-x-DV-S_2x30-1SH_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-130-xx.x-x-DV-S, 30 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -62 -61 -Connector_Samtec -Samtec_LSHM-140-xx.x-x-DV-N_2x40_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-140-xx.x-x-DV-N, 40 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -80 -80 -Connector_Samtec -Samtec_LSHM-140-xx.x-x-DV-S_2x40-1SH_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-140-xx.x-x-DV-S, 40 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -82 -81 -Connector_Samtec -Samtec_LSHM-150-xx.x-x-DV-N_2x50_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-150-xx.x-x-DV-N, 50 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -100 -100 -Connector_Samtec -Samtec_LSHM-150-xx.x-x-DV-S_2x50-1SH_P0.50mm_Vertical -Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-150-xx.x-x-DV-S, 50 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator -connector Samtec side entry -0 -102 -101 -Connector_Samtec_HLE_SMD -Samtec_HLE-102-02-xxx-DV-BE-LC_2x02_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-BE-LC, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -4 -4 -Connector_Samtec_HLE_SMD -Samtec_HLE-102-02-xxx-DV-BE_2x02_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-BE, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -4 -4 -Connector_Samtec_HLE_SMD -Samtec_HLE-102-02-xxx-DV-LC_2x02_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-LC, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -4 -4 -Connector_Samtec_HLE_SMD -Samtec_HLE-102-02-xxx-DV_2x02_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -4 -4 -Connector_Samtec_HLE_SMD -Samtec_HLE-103-02-xxx-DV-BE-LC_2x03_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-BE-LC, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -6 -6 -Connector_Samtec_HLE_SMD -Samtec_HLE-103-02-xxx-DV-BE_2x03_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-BE, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -6 -6 -Connector_Samtec_HLE_SMD -Samtec_HLE-103-02-xxx-DV-LC_2x03_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-LC, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -6 -6 -Connector_Samtec_HLE_SMD -Samtec_HLE-103-02-xxx-DV_2x03_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -6 -6 -Connector_Samtec_HLE_SMD -Samtec_HLE-104-02-xxx-DV-A_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-A, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_SMD -Samtec_HLE-104-02-xxx-DV-BE-A_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE-A, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_SMD -Samtec_HLE-104-02-xxx-DV-BE-LC_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_SMD -Samtec_HLE-104-02-xxx-DV-BE_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_SMD -Samtec_HLE-104-02-xxx-DV-LC_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_SMD -Samtec_HLE-104-02-xxx-DV_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_SMD -Samtec_HLE-105-02-xxx-DV-A_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-A, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_SMD -Samtec_HLE-105-02-xxx-DV-BE-A_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE-A, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_SMD -Samtec_HLE-105-02-xxx-DV-BE-LC_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_SMD -Samtec_HLE-105-02-xxx-DV-BE_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_SMD -Samtec_HLE-105-02-xxx-DV-LC_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_SMD -Samtec_HLE-105-02-xxx-DV_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_SMD -Samtec_HLE-106-02-xxx-DV-A_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-A, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_SMD -Samtec_HLE-106-02-xxx-DV-BE-A_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE-A, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_SMD -Samtec_HLE-106-02-xxx-DV-BE-LC_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_SMD -Samtec_HLE-106-02-xxx-DV-BE_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_SMD -Samtec_HLE-106-02-xxx-DV-LC_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_SMD -Samtec_HLE-106-02-xxx-DV_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_SMD -Samtec_HLE-107-02-xxx-DV-A_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-A, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_SMD -Samtec_HLE-107-02-xxx-DV-BE-A_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE-A, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_SMD -Samtec_HLE-107-02-xxx-DV-BE-LC_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_SMD -Samtec_HLE-107-02-xxx-DV-BE_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_SMD -Samtec_HLE-107-02-xxx-DV-LC_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_SMD -Samtec_HLE-107-02-xxx-DV_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_SMD -Samtec_HLE-108-02-xxx-DV-A_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-A, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_SMD -Samtec_HLE-108-02-xxx-DV-BE-A_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE-A, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_SMD -Samtec_HLE-108-02-xxx-DV-BE-LC_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_SMD -Samtec_HLE-108-02-xxx-DV-BE_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_SMD -Samtec_HLE-108-02-xxx-DV-LC_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_SMD -Samtec_HLE-108-02-xxx-DV_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_SMD -Samtec_HLE-109-02-xxx-DV-A_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-A, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_SMD -Samtec_HLE-109-02-xxx-DV-BE-A_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE-A, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_SMD -Samtec_HLE-109-02-xxx-DV-BE-LC_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_SMD -Samtec_HLE-109-02-xxx-DV-BE_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_SMD -Samtec_HLE-109-02-xxx-DV-LC_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_SMD -Samtec_HLE-109-02-xxx-DV_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_SMD -Samtec_HLE-110-02-xxx-DV-A_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-A, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_SMD -Samtec_HLE-110-02-xxx-DV-BE-A_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE-A, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_SMD -Samtec_HLE-110-02-xxx-DV-BE-LC_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_SMD -Samtec_HLE-110-02-xxx-DV-BE_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_SMD -Samtec_HLE-110-02-xxx-DV-LC_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_SMD -Samtec_HLE-110-02-xxx-DV_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_SMD -Samtec_HLE-111-02-xxx-DV-A_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-A, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_SMD -Samtec_HLE-111-02-xxx-DV-BE-A_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE-A, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_SMD -Samtec_HLE-111-02-xxx-DV-BE-LC_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_SMD -Samtec_HLE-111-02-xxx-DV-BE_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_SMD -Samtec_HLE-111-02-xxx-DV-LC_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_SMD -Samtec_HLE-111-02-xxx-DV_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_SMD -Samtec_HLE-112-02-xxx-DV-A_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-A, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_SMD -Samtec_HLE-112-02-xxx-DV-BE-A_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE-A, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_SMD -Samtec_HLE-112-02-xxx-DV-BE-LC_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_SMD -Samtec_HLE-112-02-xxx-DV-BE_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_SMD -Samtec_HLE-112-02-xxx-DV-LC_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_SMD -Samtec_HLE-112-02-xxx-DV_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_SMD -Samtec_HLE-113-02-xxx-DV-A_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-A, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_SMD -Samtec_HLE-113-02-xxx-DV-BE-A_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE-A, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_SMD -Samtec_HLE-113-02-xxx-DV-BE-LC_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_SMD -Samtec_HLE-113-02-xxx-DV-BE_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_SMD -Samtec_HLE-113-02-xxx-DV-LC_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_SMD -Samtec_HLE-113-02-xxx-DV_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_SMD -Samtec_HLE-114-02-xxx-DV-A_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_SMD -Samtec_HLE-114-02-xxx-DV-BE-A_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE-A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_SMD -Samtec_HLE-114-02-xxx-DV-BE-LC_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_SMD -Samtec_HLE-114-02-xxx-DV-BE_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_SMD -Samtec_HLE-114-02-xxx-DV-LC_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_SMD -Samtec_HLE-114-02-xxx-DV_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_SMD -Samtec_HLE-115-02-xxx-DV-A_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-A, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_SMD -Samtec_HLE-115-02-xxx-DV-BE-A_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE-A, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_SMD -Samtec_HLE-115-02-xxx-DV-BE-LC_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_SMD -Samtec_HLE-115-02-xxx-DV-BE_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_SMD -Samtec_HLE-115-02-xxx-DV-LC_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_SMD -Samtec_HLE-115-02-xxx-DV_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_SMD -Samtec_HLE-116-02-xxx-DV-A_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-A, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_SMD -Samtec_HLE-116-02-xxx-DV-BE-A_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE-A, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_SMD -Samtec_HLE-116-02-xxx-DV-BE-LC_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_SMD -Samtec_HLE-116-02-xxx-DV-BE_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_SMD -Samtec_HLE-116-02-xxx-DV-LC_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_SMD -Samtec_HLE-116-02-xxx-DV_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_SMD -Samtec_HLE-117-02-xxx-DV-A_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-A, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_SMD -Samtec_HLE-117-02-xxx-DV-BE-A_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE-A, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_SMD -Samtec_HLE-117-02-xxx-DV-BE-LC_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_SMD -Samtec_HLE-117-02-xxx-DV-BE_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_SMD -Samtec_HLE-117-02-xxx-DV-LC_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_SMD -Samtec_HLE-117-02-xxx-DV_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_SMD -Samtec_HLE-118-02-xxx-DV-A_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-A, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_SMD -Samtec_HLE-118-02-xxx-DV-BE-A_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE-A, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_SMD -Samtec_HLE-118-02-xxx-DV-BE-LC_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_SMD -Samtec_HLE-118-02-xxx-DV-BE_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_SMD -Samtec_HLE-118-02-xxx-DV-LC_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_SMD -Samtec_HLE-118-02-xxx-DV_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_SMD -Samtec_HLE-119-02-xxx-DV-A_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-A, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_SMD -Samtec_HLE-119-02-xxx-DV-BE-A_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE-A, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_SMD -Samtec_HLE-119-02-xxx-DV-BE-LC_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_SMD -Samtec_HLE-119-02-xxx-DV-BE_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_SMD -Samtec_HLE-119-02-xxx-DV-LC_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_SMD -Samtec_HLE-119-02-xxx-DV_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_SMD -Samtec_HLE-120-02-xxx-DV-A_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-A, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_SMD -Samtec_HLE-120-02-xxx-DV-BE-A_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE-A, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_SMD -Samtec_HLE-120-02-xxx-DV-BE-LC_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_SMD -Samtec_HLE-120-02-xxx-DV-BE_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_SMD -Samtec_HLE-120-02-xxx-DV-LC_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_SMD -Samtec_HLE-120-02-xxx-DV_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_SMD -Samtec_HLE-121-02-xxx-DV-A_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-A, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_SMD -Samtec_HLE-121-02-xxx-DV-BE-A_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE-A, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_SMD -Samtec_HLE-121-02-xxx-DV-BE-LC_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_SMD -Samtec_HLE-121-02-xxx-DV-BE_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_SMD -Samtec_HLE-121-02-xxx-DV-LC_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_SMD -Samtec_HLE-121-02-xxx-DV_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_SMD -Samtec_HLE-122-02-xxx-DV-A_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-A, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_SMD -Samtec_HLE-122-02-xxx-DV-BE-A_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE-A, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_SMD -Samtec_HLE-122-02-xxx-DV-BE-LC_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_SMD -Samtec_HLE-122-02-xxx-DV-BE_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_SMD -Samtec_HLE-122-02-xxx-DV-LC_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_SMD -Samtec_HLE-122-02-xxx-DV_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_SMD -Samtec_HLE-123-02-xxx-DV-A_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-A, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_SMD -Samtec_HLE-123-02-xxx-DV-BE-A_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE-A, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_SMD -Samtec_HLE-123-02-xxx-DV-BE-LC_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_SMD -Samtec_HLE-123-02-xxx-DV-BE_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_SMD -Samtec_HLE-123-02-xxx-DV-LC_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_SMD -Samtec_HLE-123-02-xxx-DV_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_SMD -Samtec_HLE-124-02-xxx-DV-A_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-A, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_SMD -Samtec_HLE-124-02-xxx-DV-BE-A_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE-A, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_SMD -Samtec_HLE-124-02-xxx-DV-BE-LC_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_SMD -Samtec_HLE-124-02-xxx-DV-BE_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_SMD -Samtec_HLE-124-02-xxx-DV-LC_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_SMD -Samtec_HLE-124-02-xxx-DV_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_SMD -Samtec_HLE-125-02-xxx-DV-A_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-A, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_SMD -Samtec_HLE-125-02-xxx-DV-BE-A_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE-A, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_SMD -Samtec_HLE-125-02-xxx-DV-BE-LC_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_SMD -Samtec_HLE-125-02-xxx-DV-BE_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_SMD -Samtec_HLE-125-02-xxx-DV-LC_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_SMD -Samtec_HLE-125-02-xxx-DV_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_SMD -Samtec_HLE-126-02-xxx-DV-A_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-A, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_SMD -Samtec_HLE-126-02-xxx-DV-BE-A_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-A, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_SMD -Samtec_HLE-126-02-xxx-DV-BE-LC_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_SMD -Samtec_HLE-126-02-xxx-DV-BE_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_SMD -Samtec_HLE-126-02-xxx-DV-LC_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_SMD -Samtec_HLE-126-02-xxx-DV_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_SMD -Samtec_HLE-127-02-xxx-DV-A_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-A, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_SMD -Samtec_HLE-127-02-xxx-DV-BE-A_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE-A, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_SMD -Samtec_HLE-127-02-xxx-DV-BE-LC_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_SMD -Samtec_HLE-127-02-xxx-DV-BE_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_SMD -Samtec_HLE-127-02-xxx-DV-LC_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_SMD -Samtec_HLE-127-02-xxx-DV_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_SMD -Samtec_HLE-128-02-xxx-DV-A_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-A, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_SMD -Samtec_HLE-128-02-xxx-DV-BE-A_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE-A, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_SMD -Samtec_HLE-128-02-xxx-DV-BE-LC_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_SMD -Samtec_HLE-128-02-xxx-DV-BE_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_SMD -Samtec_HLE-128-02-xxx-DV-LC_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_SMD -Samtec_HLE-128-02-xxx-DV_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_SMD -Samtec_HLE-129-02-xxx-DV-A_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-A, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_SMD -Samtec_HLE-129-02-xxx-DV-BE-A_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE-A, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_SMD -Samtec_HLE-129-02-xxx-DV-BE-LC_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_SMD -Samtec_HLE-129-02-xxx-DV-BE_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_SMD -Samtec_HLE-129-02-xxx-DV-LC_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_SMD -Samtec_HLE-129-02-xxx-DV_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_SMD -Samtec_HLE-130-02-xxx-DV-A_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-A, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_SMD -Samtec_HLE-130-02-xxx-DV-BE-A_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE-A, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_SMD -Samtec_HLE-130-02-xxx-DV-BE-LC_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_SMD -Samtec_HLE-130-02-xxx-DV-BE_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_SMD -Samtec_HLE-130-02-xxx-DV-LC_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_SMD -Samtec_HLE-130-02-xxx-DV_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_SMD -Samtec_HLE-131-02-xxx-DV-A_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_SMD -Samtec_HLE-131-02-xxx-DV-BE-A_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_SMD -Samtec_HLE-131-02-xxx-DV-BE-LC_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_SMD -Samtec_HLE-131-02-xxx-DV-BE_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_SMD -Samtec_HLE-131-02-xxx-DV-LC_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_SMD -Samtec_HLE-131-02-xxx-DV_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_SMD -Samtec_HLE-132-02-xxx-DV-A_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-A, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_SMD -Samtec_HLE-132-02-xxx-DV-BE-A_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE-A, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_SMD -Samtec_HLE-132-02-xxx-DV-BE-LC_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_SMD -Samtec_HLE-132-02-xxx-DV-BE_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_SMD -Samtec_HLE-132-02-xxx-DV-LC_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_SMD -Samtec_HLE-132-02-xxx-DV_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_SMD -Samtec_HLE-133-02-xxx-DV-A_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-A, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_SMD -Samtec_HLE-133-02-xxx-DV-BE-A_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE-A, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_SMD -Samtec_HLE-133-02-xxx-DV-BE-LC_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_SMD -Samtec_HLE-133-02-xxx-DV-BE_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_SMD -Samtec_HLE-133-02-xxx-DV-LC_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_SMD -Samtec_HLE-133-02-xxx-DV_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_SMD -Samtec_HLE-134-02-xxx-DV-A_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-A, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_SMD -Samtec_HLE-134-02-xxx-DV-BE-A_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE-A, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_SMD -Samtec_HLE-134-02-xxx-DV-BE-LC_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_SMD -Samtec_HLE-134-02-xxx-DV-BE_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_SMD -Samtec_HLE-134-02-xxx-DV-LC_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_SMD -Samtec_HLE-134-02-xxx-DV_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_SMD -Samtec_HLE-135-02-xxx-DV-A_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-A, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_SMD -Samtec_HLE-135-02-xxx-DV-BE-A_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE-A, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_SMD -Samtec_HLE-135-02-xxx-DV-BE-LC_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_SMD -Samtec_HLE-135-02-xxx-DV-BE_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_SMD -Samtec_HLE-135-02-xxx-DV-LC_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_SMD -Samtec_HLE-135-02-xxx-DV_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_SMD -Samtec_HLE-136-02-xxx-DV-A_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-A, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_SMD -Samtec_HLE-136-02-xxx-DV-BE-A_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE-A, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_SMD -Samtec_HLE-136-02-xxx-DV-BE-LC_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_SMD -Samtec_HLE-136-02-xxx-DV-BE_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_SMD -Samtec_HLE-136-02-xxx-DV-LC_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_SMD -Samtec_HLE-136-02-xxx-DV_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_SMD -Samtec_HLE-137-02-xxx-DV-A_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-A, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_SMD -Samtec_HLE-137-02-xxx-DV-BE-A_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE-A, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_SMD -Samtec_HLE-137-02-xxx-DV-BE-LC_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_SMD -Samtec_HLE-137-02-xxx-DV-BE_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_SMD -Samtec_HLE-137-02-xxx-DV-LC_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_SMD -Samtec_HLE-137-02-xxx-DV_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_SMD -Samtec_HLE-138-02-xxx-DV-A_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-A, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_SMD -Samtec_HLE-138-02-xxx-DV-BE-A_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE-A, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_SMD -Samtec_HLE-138-02-xxx-DV-BE-LC_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_SMD -Samtec_HLE-138-02-xxx-DV-BE_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_SMD -Samtec_HLE-138-02-xxx-DV-LC_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_SMD -Samtec_HLE-138-02-xxx-DV_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_SMD -Samtec_HLE-139-02-xxx-DV-A_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-A, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_SMD -Samtec_HLE-139-02-xxx-DV-BE-A_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE-A, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_SMD -Samtec_HLE-139-02-xxx-DV-BE-LC_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_SMD -Samtec_HLE-139-02-xxx-DV-BE_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_SMD -Samtec_HLE-139-02-xxx-DV-LC_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_SMD -Samtec_HLE-139-02-xxx-DV_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_SMD -Samtec_HLE-140-02-xxx-DV-A_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-A, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_SMD -Samtec_HLE-140-02-xxx-DV-BE-A_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE-A, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_SMD -Samtec_HLE-140-02-xxx-DV-BE-LC_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_SMD -Samtec_HLE-140-02-xxx-DV-BE_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_SMD -Samtec_HLE-140-02-xxx-DV-LC_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_SMD -Samtec_HLE-140-02-xxx-DV_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_SMD -Samtec_HLE-141-02-xxx-DV-A_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-A, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_SMD -Samtec_HLE-141-02-xxx-DV-BE-A_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE-A, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_SMD -Samtec_HLE-141-02-xxx-DV-BE-LC_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_SMD -Samtec_HLE-141-02-xxx-DV-BE_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_SMD -Samtec_HLE-141-02-xxx-DV-LC_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_SMD -Samtec_HLE-141-02-xxx-DV_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_SMD -Samtec_HLE-142-02-xxx-DV-A_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-A, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_SMD -Samtec_HLE-142-02-xxx-DV-BE-A_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE-A, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_SMD -Samtec_HLE-142-02-xxx-DV-BE-LC_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_SMD -Samtec_HLE-142-02-xxx-DV-BE_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_SMD -Samtec_HLE-142-02-xxx-DV-LC_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_SMD -Samtec_HLE-142-02-xxx-DV_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_SMD -Samtec_HLE-143-02-xxx-DV-A_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-A, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_SMD -Samtec_HLE-143-02-xxx-DV-BE-A_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE-A, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_SMD -Samtec_HLE-143-02-xxx-DV-BE-LC_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_SMD -Samtec_HLE-143-02-xxx-DV-BE_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_SMD -Samtec_HLE-143-02-xxx-DV-LC_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_SMD -Samtec_HLE-143-02-xxx-DV_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_SMD -Samtec_HLE-144-02-xxx-DV-A_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-A, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_SMD -Samtec_HLE-144-02-xxx-DV-BE-A_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE-A, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_SMD -Samtec_HLE-144-02-xxx-DV-BE-LC_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_SMD -Samtec_HLE-144-02-xxx-DV-BE_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_SMD -Samtec_HLE-144-02-xxx-DV-LC_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_SMD -Samtec_HLE-144-02-xxx-DV_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_SMD -Samtec_HLE-145-02-xxx-DV-A_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-A, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_SMD -Samtec_HLE-145-02-xxx-DV-BE-A_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE-A, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_SMD -Samtec_HLE-145-02-xxx-DV-BE-LC_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_SMD -Samtec_HLE-145-02-xxx-DV-BE_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_SMD -Samtec_HLE-145-02-xxx-DV-LC_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_SMD -Samtec_HLE-145-02-xxx-DV_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_SMD -Samtec_HLE-146-02-xxx-DV-A_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-A, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_SMD -Samtec_HLE-146-02-xxx-DV-BE-A_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE-A, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_SMD -Samtec_HLE-146-02-xxx-DV-BE-LC_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_SMD -Samtec_HLE-146-02-xxx-DV-BE_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_SMD -Samtec_HLE-146-02-xxx-DV-LC_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_SMD -Samtec_HLE-146-02-xxx-DV_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_SMD -Samtec_HLE-147-02-xxx-DV-A_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-A, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_SMD -Samtec_HLE-147-02-xxx-DV-BE-A_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE-A, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_SMD -Samtec_HLE-147-02-xxx-DV-BE-LC_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_SMD -Samtec_HLE-147-02-xxx-DV-BE_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_SMD -Samtec_HLE-147-02-xxx-DV-LC_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_SMD -Samtec_HLE-147-02-xxx-DV_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_SMD -Samtec_HLE-148-02-xxx-DV-A_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-A, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_SMD -Samtec_HLE-148-02-xxx-DV-BE-A_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE-A, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_SMD -Samtec_HLE-148-02-xxx-DV-BE-LC_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_SMD -Samtec_HLE-148-02-xxx-DV-BE_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_SMD -Samtec_HLE-148-02-xxx-DV-LC_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_SMD -Samtec_HLE-148-02-xxx-DV_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_SMD -Samtec_HLE-149-02-xxx-DV-A_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-A, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_SMD -Samtec_HLE-149-02-xxx-DV-BE-A_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE-A, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_SMD -Samtec_HLE-149-02-xxx-DV-BE-LC_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_SMD -Samtec_HLE-149-02-xxx-DV-BE_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_SMD -Samtec_HLE-149-02-xxx-DV-LC_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_SMD -Samtec_HLE-149-02-xxx-DV_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_SMD -Samtec_HLE-150-02-xxx-DV-A_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-A, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_SMD -Samtec_HLE-150-02-xxx-DV-BE-A_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE-A, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_SMD -Samtec_HLE-150-02-xxx-DV-BE-LC_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_SMD -Samtec_HLE-150-02-xxx-DV-BE_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_SMD -Samtec_HLE-150-02-xxx-DV-LC_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_SMD -Samtec_HLE-150-02-xxx-DV_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_THT -Samtec_HLE-104-02-xx-DV-PE-LC_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-PE-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_THT -Samtec_HLE-104-02-xx-DV-PE_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-PE (compatible alternatives: HLE-104-02-xx-DV-PE-BE), 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_THT -Samtec_HLE-104-02-xx-DV-TE_2x04_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-TE, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -8 -8 -Connector_Samtec_HLE_THT -Samtec_HLE-105-02-xx-DV-PE-LC_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-PE-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_THT -Samtec_HLE-105-02-xx-DV-PE_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-PE (compatible alternatives: HLE-105-02-xx-DV-PE-BE), 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_THT -Samtec_HLE-105-02-xx-DV-TE_2x05_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-TE, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -10 -10 -Connector_Samtec_HLE_THT -Samtec_HLE-106-02-xx-DV-PE-LC_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-PE-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_THT -Samtec_HLE-106-02-xx-DV-PE_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-PE (compatible alternatives: HLE-106-02-xx-DV-PE-BE), 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_THT -Samtec_HLE-106-02-xx-DV-TE_2x06_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-TE, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -12 -12 -Connector_Samtec_HLE_THT -Samtec_HLE-107-02-xx-DV-PE-LC_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-PE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_THT -Samtec_HLE-107-02-xx-DV-PE_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-PE (compatible alternatives: HLE-107-02-xx-DV-PE-BE), 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_THT -Samtec_HLE-107-02-xx-DV-TE_2x07_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-TE, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -14 -14 -Connector_Samtec_HLE_THT -Samtec_HLE-108-02-xx-DV-PE-LC_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_THT -Samtec_HLE-108-02-xx-DV-PE_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE (compatible alternatives: HLE-108-02-xx-DV-PE-BE), 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_THT -Samtec_HLE-108-02-xx-DV-TE_2x08_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-TE, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -16 -16 -Connector_Samtec_HLE_THT -Samtec_HLE-109-02-xx-DV-PE-LC_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-PE-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_THT -Samtec_HLE-109-02-xx-DV-PE_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-PE (compatible alternatives: HLE-109-02-xx-DV-PE-BE), 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_THT -Samtec_HLE-109-02-xx-DV-TE_2x09_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-TE, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -18 -18 -Connector_Samtec_HLE_THT -Samtec_HLE-110-02-xx-DV-PE-LC_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-PE-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_THT -Samtec_HLE-110-02-xx-DV-PE_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-PE (compatible alternatives: HLE-110-02-xx-DV-PE-BE), 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_THT -Samtec_HLE-110-02-xx-DV-TE_2x10_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-TE, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -20 -20 -Connector_Samtec_HLE_THT -Samtec_HLE-111-02-xx-DV-PE-LC_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-PE-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_THT -Samtec_HLE-111-02-xx-DV-PE_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-PE (compatible alternatives: HLE-111-02-xx-DV-PE-BE), 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_THT -Samtec_HLE-111-02-xx-DV-TE_2x11_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-TE, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -22 -22 -Connector_Samtec_HLE_THT -Samtec_HLE-112-02-xx-DV-PE-LC_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-PE-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_THT -Samtec_HLE-112-02-xx-DV-PE_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-PE (compatible alternatives: HLE-112-02-xx-DV-PE-BE), 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_THT -Samtec_HLE-112-02-xx-DV-TE_2x12_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-TE, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -24 -24 -Connector_Samtec_HLE_THT -Samtec_HLE-113-02-xx-DV-PE-LC_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-PE-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_THT -Samtec_HLE-113-02-xx-DV-PE_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-PE (compatible alternatives: HLE-113-02-xx-DV-PE-BE), 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_THT -Samtec_HLE-113-02-xx-DV-TE_2x13_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-TE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -26 -26 -Connector_Samtec_HLE_THT -Samtec_HLE-114-02-xx-DV-PE-LC_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-PE-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_THT -Samtec_HLE-114-02-xx-DV-PE_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-PE (compatible alternatives: HLE-114-02-xx-DV-PE-BE), 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_THT -Samtec_HLE-114-02-xx-DV-TE_2x14_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-TE, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -28 -28 -Connector_Samtec_HLE_THT -Samtec_HLE-115-02-xx-DV-PE-LC_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-PE-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_THT -Samtec_HLE-115-02-xx-DV-PE_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-PE (compatible alternatives: HLE-115-02-xx-DV-PE-BE), 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_THT -Samtec_HLE-115-02-xx-DV-TE_2x15_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-TE, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -30 -30 -Connector_Samtec_HLE_THT -Samtec_HLE-116-02-xx-DV-PE-LC_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-PE-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_THT -Samtec_HLE-116-02-xx-DV-PE_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-PE (compatible alternatives: HLE-116-02-xx-DV-PE-BE), 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_THT -Samtec_HLE-116-02-xx-DV-TE_2x16_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-TE, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -32 -32 -Connector_Samtec_HLE_THT -Samtec_HLE-117-02-xx-DV-PE-LC_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-PE-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_THT -Samtec_HLE-117-02-xx-DV-PE_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-PE (compatible alternatives: HLE-117-02-xx-DV-PE-BE), 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_THT -Samtec_HLE-117-02-xx-DV-TE_2x17_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-TE, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -34 -34 -Connector_Samtec_HLE_THT -Samtec_HLE-118-02-xx-DV-PE-LC_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-PE-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_THT -Samtec_HLE-118-02-xx-DV-PE_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-PE (compatible alternatives: HLE-118-02-xx-DV-PE-BE), 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_THT -Samtec_HLE-118-02-xx-DV-TE_2x18_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-TE, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -36 -36 -Connector_Samtec_HLE_THT -Samtec_HLE-119-02-xx-DV-PE-LC_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-PE-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_THT -Samtec_HLE-119-02-xx-DV-PE_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-PE (compatible alternatives: HLE-119-02-xx-DV-PE-BE), 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_THT -Samtec_HLE-119-02-xx-DV-TE_2x19_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-TE, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -38 -38 -Connector_Samtec_HLE_THT -Samtec_HLE-120-02-xx-DV-PE-LC_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-PE-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_THT -Samtec_HLE-120-02-xx-DV-PE_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-PE (compatible alternatives: HLE-120-02-xx-DV-PE-BE), 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_THT -Samtec_HLE-120-02-xx-DV-TE_2x20_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-TE, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -40 -40 -Connector_Samtec_HLE_THT -Samtec_HLE-121-02-xx-DV-PE-LC_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-PE-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_THT -Samtec_HLE-121-02-xx-DV-PE_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-PE (compatible alternatives: HLE-121-02-xx-DV-PE-BE), 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_THT -Samtec_HLE-121-02-xx-DV-TE_2x21_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-TE, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -42 -42 -Connector_Samtec_HLE_THT -Samtec_HLE-122-02-xx-DV-PE-LC_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-PE-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_THT -Samtec_HLE-122-02-xx-DV-PE_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-PE (compatible alternatives: HLE-122-02-xx-DV-PE-BE), 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_THT -Samtec_HLE-122-02-xx-DV-TE_2x22_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-TE, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -44 -44 -Connector_Samtec_HLE_THT -Samtec_HLE-123-02-xx-DV-PE-LC_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-PE-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_THT -Samtec_HLE-123-02-xx-DV-PE_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-PE (compatible alternatives: HLE-123-02-xx-DV-PE-BE), 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_THT -Samtec_HLE-123-02-xx-DV-TE_2x23_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-TE, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -46 -46 -Connector_Samtec_HLE_THT -Samtec_HLE-124-02-xx-DV-PE-LC_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-PE-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_THT -Samtec_HLE-124-02-xx-DV-PE_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-PE (compatible alternatives: HLE-124-02-xx-DV-PE-BE), 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_THT -Samtec_HLE-124-02-xx-DV-TE_2x24_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-TE, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -48 -48 -Connector_Samtec_HLE_THT -Samtec_HLE-125-02-xx-DV-PE-LC_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-PE-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_THT -Samtec_HLE-125-02-xx-DV-PE_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-PE (compatible alternatives: HLE-125-02-xx-DV-PE-BE), 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_THT -Samtec_HLE-125-02-xx-DV-TE_2x25_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-TE, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -50 -50 -Connector_Samtec_HLE_THT -Samtec_HLE-126-02-xx-DV-PE-LC_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-PE-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_THT -Samtec_HLE-126-02-xx-DV-PE_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-PE (compatible alternatives: HLE-126-02-xx-DV-PE-BE), 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_THT -Samtec_HLE-126-02-xx-DV-TE_2x26_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-TE, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -52 -52 -Connector_Samtec_HLE_THT -Samtec_HLE-127-02-xx-DV-PE-LC_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-PE-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_THT -Samtec_HLE-127-02-xx-DV-PE_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-PE (compatible alternatives: HLE-127-02-xx-DV-PE-BE), 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_THT -Samtec_HLE-127-02-xx-DV-TE_2x27_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-TE, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -54 -54 -Connector_Samtec_HLE_THT -Samtec_HLE-128-02-xx-DV-PE-LC_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-PE-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_THT -Samtec_HLE-128-02-xx-DV-PE_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-PE (compatible alternatives: HLE-128-02-xx-DV-PE-BE), 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_THT -Samtec_HLE-128-02-xx-DV-TE_2x28_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-TE, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -56 -56 -Connector_Samtec_HLE_THT -Samtec_HLE-129-02-xx-DV-PE-LC_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-PE-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_THT -Samtec_HLE-129-02-xx-DV-PE_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-PE (compatible alternatives: HLE-129-02-xx-DV-PE-BE), 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_THT -Samtec_HLE-129-02-xx-DV-TE_2x29_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-TE, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -58 -58 -Connector_Samtec_HLE_THT -Samtec_HLE-130-02-xx-DV-PE-LC_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-PE-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_THT -Samtec_HLE-130-02-xx-DV-PE_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-PE (compatible alternatives: HLE-130-02-xx-DV-PE-BE), 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_THT -Samtec_HLE-130-02-xx-DV-TE_2x30_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-TE, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -60 -60 -Connector_Samtec_HLE_THT -Samtec_HLE-131-02-xx-DV-PE-LC_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-PE-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_THT -Samtec_HLE-131-02-xx-DV-PE_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-PE (compatible alternatives: HLE-131-02-xx-DV-PE-BE), 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_THT -Samtec_HLE-131-02-xx-DV-TE_2x31_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-TE, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -62 -62 -Connector_Samtec_HLE_THT -Samtec_HLE-132-02-xx-DV-PE-LC_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-PE-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_THT -Samtec_HLE-132-02-xx-DV-PE_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-PE (compatible alternatives: HLE-132-02-xx-DV-PE-BE), 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_THT -Samtec_HLE-132-02-xx-DV-TE_2x32_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-TE, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -64 -64 -Connector_Samtec_HLE_THT -Samtec_HLE-133-02-xx-DV-PE-LC_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-PE-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_THT -Samtec_HLE-133-02-xx-DV-PE_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-PE (compatible alternatives: HLE-133-02-xx-DV-PE-BE), 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_THT -Samtec_HLE-133-02-xx-DV-TE_2x33_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-TE, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -66 -66 -Connector_Samtec_HLE_THT -Samtec_HLE-134-02-xx-DV-PE-LC_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-PE-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_THT -Samtec_HLE-134-02-xx-DV-PE_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-PE (compatible alternatives: HLE-134-02-xx-DV-PE-BE), 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_THT -Samtec_HLE-134-02-xx-DV-TE_2x34_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-TE, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -68 -68 -Connector_Samtec_HLE_THT -Samtec_HLE-135-02-xx-DV-PE-LC_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-PE-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_THT -Samtec_HLE-135-02-xx-DV-PE_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-PE (compatible alternatives: HLE-135-02-xx-DV-PE-BE), 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_THT -Samtec_HLE-135-02-xx-DV-TE_2x35_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-TE, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -70 -70 -Connector_Samtec_HLE_THT -Samtec_HLE-136-02-xx-DV-PE-LC_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-PE-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_THT -Samtec_HLE-136-02-xx-DV-PE_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-PE (compatible alternatives: HLE-136-02-xx-DV-PE-BE), 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_THT -Samtec_HLE-136-02-xx-DV-TE_2x36_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-TE, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -72 -72 -Connector_Samtec_HLE_THT -Samtec_HLE-137-02-xx-DV-PE-LC_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-PE-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_THT -Samtec_HLE-137-02-xx-DV-PE_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-PE (compatible alternatives: HLE-137-02-xx-DV-PE-BE), 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_THT -Samtec_HLE-137-02-xx-DV-TE_2x37_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-TE, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -74 -74 -Connector_Samtec_HLE_THT -Samtec_HLE-138-02-xx-DV-PE-LC_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-PE-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_THT -Samtec_HLE-138-02-xx-DV-PE_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-PE (compatible alternatives: HLE-138-02-xx-DV-PE-BE), 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_THT -Samtec_HLE-138-02-xx-DV-TE_2x38_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-TE, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -76 -76 -Connector_Samtec_HLE_THT -Samtec_HLE-139-02-xx-DV-PE-LC_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-PE-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_THT -Samtec_HLE-139-02-xx-DV-PE_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-PE (compatible alternatives: HLE-139-02-xx-DV-PE-BE), 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_THT -Samtec_HLE-139-02-xx-DV-TE_2x39_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-TE, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -78 -78 -Connector_Samtec_HLE_THT -Samtec_HLE-140-02-xx-DV-PE-LC_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-PE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_THT -Samtec_HLE-140-02-xx-DV-PE_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-PE (compatible alternatives: HLE-140-02-xx-DV-PE-BE), 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_THT -Samtec_HLE-140-02-xx-DV-TE_2x40_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-TE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -80 -80 -Connector_Samtec_HLE_THT -Samtec_HLE-141-02-xx-DV-PE-LC_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-PE-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_THT -Samtec_HLE-141-02-xx-DV-PE_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-PE (compatible alternatives: HLE-141-02-xx-DV-PE-BE), 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_THT -Samtec_HLE-141-02-xx-DV-TE_2x41_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-TE, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -82 -82 -Connector_Samtec_HLE_THT -Samtec_HLE-142-02-xx-DV-PE-LC_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-PE-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_THT -Samtec_HLE-142-02-xx-DV-PE_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-PE (compatible alternatives: HLE-142-02-xx-DV-PE-BE), 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_THT -Samtec_HLE-142-02-xx-DV-TE_2x42_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-TE, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -84 -84 -Connector_Samtec_HLE_THT -Samtec_HLE-143-02-xx-DV-PE-LC_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-PE-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_THT -Samtec_HLE-143-02-xx-DV-PE_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-PE (compatible alternatives: HLE-143-02-xx-DV-PE-BE), 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_THT -Samtec_HLE-143-02-xx-DV-TE_2x43_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-TE, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -86 -86 -Connector_Samtec_HLE_THT -Samtec_HLE-144-02-xx-DV-PE-LC_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-PE-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_THT -Samtec_HLE-144-02-xx-DV-PE_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-PE (compatible alternatives: HLE-144-02-xx-DV-PE-BE), 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_THT -Samtec_HLE-144-02-xx-DV-TE_2x44_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-TE, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -88 -88 -Connector_Samtec_HLE_THT -Samtec_HLE-145-02-xx-DV-PE-LC_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-PE-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_THT -Samtec_HLE-145-02-xx-DV-PE_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-PE (compatible alternatives: HLE-145-02-xx-DV-PE-BE), 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_THT -Samtec_HLE-145-02-xx-DV-TE_2x45_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-TE, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -90 -90 -Connector_Samtec_HLE_THT -Samtec_HLE-146-02-xx-DV-PE-LC_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-PE-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_THT -Samtec_HLE-146-02-xx-DV-PE_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-PE (compatible alternatives: HLE-146-02-xx-DV-PE-BE), 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_THT -Samtec_HLE-146-02-xx-DV-TE_2x46_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-TE, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -92 -92 -Connector_Samtec_HLE_THT -Samtec_HLE-147-02-xx-DV-PE-LC_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-PE-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_THT -Samtec_HLE-147-02-xx-DV-PE_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-PE (compatible alternatives: HLE-147-02-xx-DV-PE-BE), 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_THT -Samtec_HLE-147-02-xx-DV-TE_2x47_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-TE, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -94 -94 -Connector_Samtec_HLE_THT -Samtec_HLE-148-02-xx-DV-PE-LC_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-PE-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_THT -Samtec_HLE-148-02-xx-DV-PE_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-PE (compatible alternatives: HLE-148-02-xx-DV-PE-BE), 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_THT -Samtec_HLE-148-02-xx-DV-TE_2x48_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-TE, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -96 -96 -Connector_Samtec_HLE_THT -Samtec_HLE-149-02-xx-DV-PE-LC_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-PE-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_THT -Samtec_HLE-149-02-xx-DV-PE_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-PE (compatible alternatives: HLE-149-02-xx-DV-PE-BE), 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_THT -Samtec_HLE-149-02-xx-DV-TE_2x49_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-TE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -98 -98 -Connector_Samtec_HLE_THT -Samtec_HLE-150-02-xx-DV-PE-LC_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-PE-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_THT -Samtec_HLE-150-02-xx-DV-PE_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-PE (compatible alternatives: HLE-150-02-xx-DV-PE-BE), 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Samtec_HLE_THT -Samtec_HLE-150-02-xx-DV-TE_2x50_P2.54mm_Horizontal -Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-TE, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator -connector Samtec HLE top entry -0 -100 -100 -Connector_Stocko -Stocko_MKS_1651-6-0-202_1x2_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -2 -2 -Connector_Stocko -Stocko_MKS_1652-6-0-202_1x2_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -2 -2 -Connector_Stocko -Stocko_MKS_1653-6-0-303_1x3_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -3 -3 -Connector_Stocko -Stocko_MKS_1654-6-0-404_1x4_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -4 -4 -Connector_Stocko -Stocko_MKS_1655-6-0-505_1x5_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -5 -5 -Connector_Stocko -Stocko_MKS_1656-6-0-606_1x6_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -6 -6 -Connector_Stocko -Stocko_MKS_1657-6-0-707_1x7_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -7 -7 -Connector_Stocko -Stocko_MKS_1658-6-0-808_1x8_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -8 -8 -Connector_Stocko -Stocko_MKS_1659-6-0-909_1x9_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -9 -9 -Connector_Stocko -Stocko_MKS_1660-6-0-1010_1x10_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -10 -10 -Connector_Stocko -Stocko_MKS_1661-6-0-1111_1x11_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -11 -11 -Connector_Stocko -Stocko_MKS_1662-6-0-1212_1x12_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -12 -12 -Connector_Stocko -Stocko_MKS_1663-6-0-1313_1x13_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -13 -13 -Connector_Stocko -Stocko_MKS_1664-6-0-1414_1x14_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -14 -14 -Connector_Stocko -Stocko_MKS_1665-6-0-1515_1x15_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -15 -15 -Connector_Stocko -Stocko_MKS_1666-6-0-1616_1x16_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -16 -16 -Connector_Stocko -Stocko_MKS_1667-6-0-1717_1x17_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -17 -17 -Connector_Stocko -Stocko_MKS_1668-6-0-1818_1x18_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -18 -18 -Connector_Stocko -Stocko_MKS_1669-6-0-1919_1x19_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -19 -19 -Connector_Stocko -Stocko_MKS_1670-6-0-2020_1x20_P2.50mm_Vertical -Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator -Stocko RFK MKS 16xx -0 -20 -20 -Connector_TE-Connectivity -TE_1-826576-3_1x13_P3.96mm_Vertical -TE, 1-826576-3, 13 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -13 -13 -Connector_TE-Connectivity -TE_1-826576-5_1x15_P3.96mm_Vertical -TE, 1-826576-5, 15 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -15 -15 -Connector_TE-Connectivity -TE_1-826576-6_1x16_P3.96mm_Vertical -TE, 1-826576-6, 16 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -16 -16 -Connector_TE-Connectivity -TE_1-826576-7_1x17_P3.96mm_Vertical -TE, 1-826576-7, 17 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -17 -17 -Connector_TE-Connectivity -TE_1-826576-8_1x18_P3.96mm_Vertical -TE, 1-826576-8, 18 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -18 -18 -Connector_TE-Connectivity -TE_2-826576-0_1x20_P3.96mm_Vertical -TE, 2-826576-0, 20 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -20 -20 -Connector_TE-Connectivity -TE_3-826576-6_1x36_P3.96mm_Vertical -TE, 3-826576-6, 36 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -36 -36 -Connector_TE-Connectivity -TE_826576-2_1x02_P3.96mm_Vertical -TE, 826576-2, 2 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -2 -2 -Connector_TE-Connectivity -TE_826576-3_1x03_P3.96mm_Vertical -TE, 826576-3, 3 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -3 -3 -Connector_TE-Connectivity -TE_826576-5_1x05_P3.96mm_Vertical -TE, 826576-5, 5 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -5 -5 -Connector_TE-Connectivity -TE_826576-6_1x06_P3.96mm_Vertical -TE, 826576-6, 6 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -6 -6 -Connector_TE-Connectivity -TE_826576-7_1x07_P3.96mm_Vertical -TE, 826576-7, 7 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -7 -7 -Connector_TE-Connectivity -TE_826576-8_1x08_P3.96mm_Vertical -TE, 826576-8, 8 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -8 -8 -Connector_TE-Connectivity -TE_826576-9_1x09_P3.96mm_Vertical -TE, 826576-9, 9 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator -connector TE 826576 vertical -0 -9 -9 -Connector_TE-Connectivity -TE_AMPSEAL_1-776087-x_3Rows_23_P0.4mm_Horizontal -Connector -TE 776087 -0 -23 -23 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770182-x_3x03_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770182-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -9 -9 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770186-x_3x04_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770186-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -12 -12 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770190-x_3x05_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770190-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -15 -15 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770621-x_2x06_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770621-x, 6 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -12 -12 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770858-x_2x05_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770858-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -10 -10 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770866-x_1x02_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770866-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -2 -2 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770870-x_1x03_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770870-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -3 -3 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770874-x_2x02_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770874-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -4 -4 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770875-x_2x03_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770875-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -6 -6 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770966-x_1x02_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770966-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -2 -2 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770967-x_1x03_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770967-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -3 -3 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770968-x_2x02_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770968-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -4 -4 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770969-x_2x03_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770969-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -6 -6 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770970-x_2x04_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770970-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -8 -8 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770971-x_2x05_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770971-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -10 -10 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770972-x_2x06_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770972-x, 6 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -12 -12 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770973-x_2x07_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770973-x, 7 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -14 -14 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-770974-x_2x08_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770974-x, 8 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -16 -16 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794067-x_2x07_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794067-x, 7 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -14 -14 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794068-x_2x08_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794068-x, 8 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -16 -16 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794069-x_2x09_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794069-x, 9 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -18 -18 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794070-x_2x10_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794070-x, 10 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -20 -20 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794071-x_2x11_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794071-x, 11 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -22 -22 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794072-x_2x12_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794072-x, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -24 -24 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794073-x_2x04_P4.14mm_Vertical -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794073-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK side entry -0 -8 -8 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794105-x_2x09_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794105-x, 9 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -18 -18 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794106-x_2x10_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794106-x, 10 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -20 -20 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794107-x_2x11_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794107-x, 11 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -22 -22 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794108-x_2x12_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794108-x, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -24 -24 -Connector_TE-Connectivity -TE_MATE-N-LOK_1-794374-x_1x01_P4.14mm_Horizontal -Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794374-x, 1 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator -connector TE MATE-N-LOK top entry -0 -1 -1 -Connector_TE-Connectivity -TE_MATE-N-LOK_350211-1_1x04_P5.08mm_Vertical -https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F350211%7FU5%7Fpdf%7FEnglish%7FENG_CD_350211_U5.pdf%7F350211-1 -connector TE MATE-N-LOK top entry ATA PATA IDE 5.25 inch floppy drive power -0 -4 -4 -Connector_USB -USB3_A_Molex_48393-001 -USB 3.0, type A, right angle (http://www.molex.com/pdm_docs/sd/483930003_sd.pdf) -USB 3.0 type A right angle -0 -13 -10 -Connector_USB -USB3_A_Plug_Wuerth_692112030100_Horizontal -USB type A Plug, Horizontal, http://katalog.we-online.de/em/datasheet/692112030100.pdf -usb A plug horizontal -0 -11 -10 -Connector_USB -USB_A_CNCTech_1001-011-01101_Horizontal -http://cnctech.us/pdfs/1001-011-01101.pdf -USB-A -0 -6 -5 -Connector_USB -USB_A_Molex_105057_Vertical -https://www.molex.com/pdm_docs/sd/1050570001_sd.pdf -USB A Vertical -0 -7 -5 -Connector_USB -USB_A_Stewart_SS-52100-001_Horizontal -USB A connector https://belfuse.com/resources/drawings/stewartconnector/dr-stw-ss-52100-001.pdf -USB_A Female Connector receptacle -0 -6 -5 -Connector_USB -USB_A_Wuerth_61400826021_Horizontal_Stacked -Stacked USB A connector http://katalog.we-online.de/em/datasheet/61400826021.pdf -Wuerth stacked USB_A -0 -12 -9 -Connector_USB -USB_B_Amphenol_MUSB-D511_Vertical_Rugged -A,phenol MUSB_D511, USB B female connector, straight, rugged, https://www.amphenolcanada.com/ProductSearch/drawings/AC/MUSBD511XX.pdf -USB_B_MUSB_Straight female connector straight rugged MUSB D511 -0 -6 -5 -Connector_USB -USB_B_OST_USB-B1HSxx_Horizontal -USB B receptacle, Horizontal, through-hole, http://www.on-shore.com/wp-content/uploads/2015/09/usb-b1hsxx.pdf -USB-B receptacle horizontal through-hole -0 -6 -5 -Connector_USB -USB_B_TE_5787834_Vertical -http://www.mouser.com/ds/2/418/NG_CD_5787834_A4-669110.pdf -USB_B USB B vertical female connector -0 -6 -5 -Connector_USB -USB_C_Plug_JAE_DX07P024AJ1 -Universal Serial Bus (USB) Shielded I/O Plug, Type C, Right Angle, Surface Mount, https://www.jae.com/en/searchfilter/?topics_keyword=DX07P024AJ1&mainItemSelect=1 -USB Type-C Plug Edge Mount -0 -30 -25 -Connector_USB -USB_C_Plug_Molex_105444 -Universal Serial Bus (USB) Shielded I/O Plug, Type C, Right Angle, Surface Mount, http://www.molex.com/pdm_docs/sd/1054440001_sd.pdf -USB Type-C Plug Edge Mount -0 -24 -23 -Connector_USB -USB_C_Receptacle_Amphenol_12401548E4-2A -USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A -USB C Type-C Receptacle Hybrid -0 -28 -25 -Connector_USB -USB_C_Receptacle_Amphenol_12401548E4-2A_CircularHoles -USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A -USB C Type-C Receptacle Hybrid -0 -28 -25 -Connector_USB -USB_C_Receptacle_Amphenol_12401610E4-2A -USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A -USB C Type-C Receptacle SMD -0 -28 -25 -Connector_USB -USB_C_Receptacle_Amphenol_12401610E4-2A_CircularHoles -USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A -USB C Type-C Receptacle SMD -0 -28 -25 -Connector_USB -USB_C_Receptacle_GCT_USB4085 -USB 2.0 Type C Receptacle, https://gct.co/Files/Drawings/USB4085.pdf -USB Type-C Receptacle Through-hole Right angle -0 -20 -17 -Connector_USB -USB_C_Receptacle_HRO_TYPE-C-31-M-12 -USB Type-C receptacle for USB 2.0 and PD, http://www.krhro.com/uploads/soft/180320/1-1P320120243.pdf -usb usb-c 2.0 pd -0 -20 -17 -Connector_USB -USB_C_Receptacle_JAE_DX07S024WJ1R350 -http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ117219.pdf -USB C Type-C Receptacle SMD -0 -30 -25 -Connector_USB -USB_C_Receptacle_JAE_DX07S024WJ3R400 -USB TYPE C, VERT RCPT PCB, SMT, http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ117928.pdf -USB C Type-C Receptacle SMD -0 -28 -25 -Connector_USB -USB_C_Receptacle_Palconn_UTC16-G -http://www.palpilot.com/wp-content/uploads/2017/05/UTC027-GKN-OR-Rev-A.pdf -USB C Type-C Receptacle USB2.0 -0 -20 -17 -Connector_USB -USB_Micro-AB_Molex_47590-0001 -Micro USB AB receptable, right-angle inverted (https://www.molex.com/pdm_docs/sd/475900001_sd.pdf) -Micro AB USB SMD -0 -14 -6 -Connector_USB -USB_Micro-B_Amphenol_10103594-0001LF_Horizontal -Micro USB Type B 10103594-0001LF, http://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10103594.pdf -USB USB_B USB_micro USB_OTG -0 -17 -6 -Connector_USB -USB_Micro-B_GCT_USB3076-30-A -GCT Micro USB https://gct.co/files/drawings/usb3076.pdf -Micro-USB SMD Typ-B GCT -0 -11 -6 -Connector_USB -USB_Micro-B_Molex-105017-0001 -http://www.molex.com/pdm_docs/sd/1050170001_sd.pdf -Micro-USB SMD Typ-B -0 -13 -6 -Connector_USB -USB_Micro-B_Molex-105133-0001 -Molex Vertical Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330001_sd.pdf) -Micro-USB SMD Typ-B Vertical -0 -8 -6 -Connector_USB -USB_Micro-B_Molex-105133-0031 -Molex Vertical Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330031_sd.pdf) -Micro-USB SMD Typ-B Vertical -0 -8 -6 -Connector_USB -USB_Micro-B_Molex_47346-0001 -Micro USB B receptable with flange, bottom-mount, SMD, right-angle (http://www.molex.com/pdm_docs/sd/473460001_sd.pdf) -Micro B USB SMD -0 -11 -6 -Connector_USB -USB_Micro-B_Wuerth_614105150721_Vertical -USB Micro-B receptacle, through-hole, vertical, http://katalog.we-online.de/em/datasheet/614105150721.pdf -usb micro receptacle vertical -0 -7 -6 -Connector_USB -USB_Micro-B_Wuerth_614105150721_Vertical_CircularHoles -USB Micro-B receptacle, through-hole, vertical, http://katalog.we-online.de/em/datasheet/614105150721.pdf -usb micro receptacle vertical -0 -7 -6 -Connector_USB -USB_Micro-B_Wuerth_629105150521 -USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf -usb micro receptacle -0 -9 -6 -Connector_USB -USB_Micro-B_Wuerth_629105150521_CircularHoles -USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf -usb micro receptacle -0 -9 -6 -Connector_USB -USB_Mini-B_AdamTech_MUSB-B5-S-VT-TSMT-1_SMD_Vertical -http://www.adam-tech.com/upload/MUSB-B5-S-VT-TSMT-1.pdf -USB Mini-B -0 -7 -6 -Connector_USB -USB_Mini-B_Lumberg_2486_01_Horizontal -USB Mini-B 5-pin SMD connector, http://downloads.lumberg.com/datenblaetter/en/2486_01.pdf -USB USB_B USB_Mini connector -0 -9 -6 -Connector_USB -USB_Mini-B_Tensility_54-00023_Vertical -http://www.tensility.com/pdffiles/54-00023.pdf -usb mini receptacle vertical -0 -7 -6 -Connector_USB -USB_Mini-B_Tensility_54-00023_Vertical_CircularHoles -http://www.tensility.com/pdffiles/54-00023.pdf -usb mini receptacle vertical -0 -7 -6 -Connector_USB -USB_Mini-B_Wuerth_65100516121_Horizontal -Mini USB 2.0 Type B SMT Horizontal 5 Contacts (https://katalog.we-online.de/em/datasheet/65100516121.pdf) -Mini USB 2.0 Type B -0 -9 -6 -Connector_Wago -Wago_734-132_1x02_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-132 , 2 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -2 -2 -Connector_Wago -Wago_734-133_1x03_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-133 , 3 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -3 -3 -Connector_Wago -Wago_734-134_1x04_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-134 , 4 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -4 -4 -Connector_Wago -Wago_734-135_1x05_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-135 , 5 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -5 -5 -Connector_Wago -Wago_734-136_1x06_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-136 , 6 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -6 -6 -Connector_Wago -Wago_734-137_1x07_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-137 , 7 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -7 -7 -Connector_Wago -Wago_734-138_1x08_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-138 , 8 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -8 -8 -Connector_Wago -Wago_734-139_1x09_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-139 , 9 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -9 -9 -Connector_Wago -Wago_734-140_1x10_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-140 , 10 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -10 -10 -Connector_Wago -Wago_734-141_1x11_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-141 , 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -11 -11 -Connector_Wago -Wago_734-142_1x12_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-142 , 12 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -12 -12 -Connector_Wago -Wago_734-143_1x13_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-143 , 13 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -13 -13 -Connector_Wago -Wago_734-144_1x14_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-144 , 14 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -14 -14 -Connector_Wago -Wago_734-146_1x16_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-146 , 16 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -16 -16 -Connector_Wago -Wago_734-148_1x18_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-148 , 18 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -18 -18 -Connector_Wago -Wago_734-150_1x20_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-150 , 20 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -20 -20 -Connector_Wago -Wago_734-154_1x24_P3.50mm_Vertical -Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-154 , 24 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago side entry -0 -24 -24 -Connector_Wago -Wago_734-162_1x02_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-162 , 2 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -2 -2 -Connector_Wago -Wago_734-163_1x03_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-163 , 3 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -3 -3 -Connector_Wago -Wago_734-164_1x04_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-164 , 4 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -4 -4 -Connector_Wago -Wago_734-165_1x05_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-165 , 5 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -5 -5 -Connector_Wago -Wago_734-166_1x06_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-166 , 6 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -6 -6 -Connector_Wago -Wago_734-167_1x07_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-167 , 7 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -7 -7 -Connector_Wago -Wago_734-168_1x08_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-168 , 8 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -8 -8 -Connector_Wago -Wago_734-169_1x09_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-169 , 9 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -9 -9 -Connector_Wago -Wago_734-170_1x10_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-170 , 10 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -10 -10 -Connector_Wago -Wago_734-171_1x11_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-171 , 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -11 -11 -Connector_Wago -Wago_734-172_1x12_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-172 , 12 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -12 -12 -Connector_Wago -Wago_734-173_1x13_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-173 , 13 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -13 -13 -Connector_Wago -Wago_734-174_1x14_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-174 , 14 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -14 -14 -Connector_Wago -Wago_734-176_1x16_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-176 , 16 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -16 -16 -Connector_Wago -Wago_734-178_1x18_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-178 , 18 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -18 -18 -Connector_Wago -Wago_734-180_1x20_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-180 , 20 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -20 -20 -Connector_Wago -Wago_734-184_1x24_P3.50mm_Horizontal -Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-184 , 24 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator -connector Wago top entry -0 -24 -24 -Connector_Wire -SolderWirePad_1x01_Drill0.8mm -Wire solder connection -connector -0 -1 -1 -Connector_Wire -SolderWirePad_1x01_Drill1.2mm -Wire solder connection -connector -0 -1 -1 -Connector_Wire -SolderWirePad_1x01_Drill1.5mm -Wire solder connection -connector -0 -1 -1 -Connector_Wire -SolderWirePad_1x01_Drill1mm -Wire solder connection -connector -0 -1 -1 -Connector_Wire -SolderWirePad_1x01_Drill2.5mm -Wire solder connection -connector -0 -1 -1 -Connector_Wire -SolderWirePad_1x01_Drill2mm -Wire solder connection -connector -0 -1 -1 -Connector_Wire -SolderWirePad_1x01_SMD_5x10mm -Wire Pad, Square, SMD Pad, 5mm x 10mm, -MesurementPoint Square SMDPad 5mmx10mm -0 -1 -1 -Connector_Wire -SolderWirePad_1x02_P3.81mm_Drill0.8mm -Wire solder connection -connector -0 -2 -2 -Connector_Wire -SolderWirePad_1x02_P3.81mm_Drill1.2mm -Wire solder connection -connector -0 -2 -2 -Connector_Wire -SolderWirePad_1x02_P3.81mm_Drill1mm -Wire solder connection -connector -0 -2 -2 -Connector_Wire -SolderWirePad_1x02_P5.08mm_Drill1.5mm -Wire solder connection -connector -0 -2 -2 -Connector_Wire -SolderWirePad_1x02_P7.62mm_Drill2.5mm -Wire solder connection -connector -0 -2 -2 -Connector_Wire -SolderWirePad_1x02_P7.62mm_Drill2mm -Wire solder connection -connector -0 -2 -2 -Connector_Wire -SolderWirePad_1x03_P3.81mm_Drill1.2mm -Wire solder connection -connector -0 -3 -3 -Connector_Wire -SolderWirePad_1x03_P3.175mm_Drill0.8mm -Wire solder connection -connector -0 -3 -3 -Connector_Wire -SolderWirePad_1x03_P3.175mm_Drill1mm -Wire solder connection -connector -0 -3 -3 -Connector_Wire -SolderWirePad_1x03_P4.445mm_Drill1.5mm -Wire solder connection -connector -0 -3 -3 -Connector_Wire -SolderWirePad_1x03_P5.715mm_Drill2mm -Wire solder connection -connector -0 -3 -3 -Connector_Wire -SolderWirePad_1x03_P7.62mm_Drill2.5mm -Wire solder connection -connector -0 -3 -3 -Connector_Wire -SolderWirePad_1x04_P3.81mm_Drill1.2mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_1x04_P3.81mm_Drill1mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_1x04_P3.175mm_Drill0.8mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_1x04_P5.08mm_Drill1.5mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_1x04_P6.35mm_Drill2mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_1x04_P7.62mm_Drill2.5mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_2x02_P2.54mm_Drill0.8mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_2x02_P3.81mm_Drill1.2mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_2x02_P3.81mm_Drill1mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_2x02_P5.08mm_Drill1.5mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_2x02_P6.35mm_Drill2mm -Wire solder connection -connector -0 -4 -4 -Connector_Wire -SolderWirePad_2x02_P7.62mm_Drill2.5mm -Wire solder connection -connector -0 -4 -4 -Connector_Wuerth -Wuerth_WR-WTB_64800211622_1x02_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800211622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -2 -2 -Connector_Wuerth -Wuerth_WR-WTB_64800311622_1x03_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800311622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -3 -3 -Connector_Wuerth -Wuerth_WR-WTB_64800411622_1x04_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800411622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -4 -4 -Connector_Wuerth -Wuerth_WR-WTB_64800511622_1x05_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800511622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -5 -5 -Connector_Wuerth -Wuerth_WR-WTB_64800611622_1x06_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800611622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -6 -6 -Connector_Wuerth -Wuerth_WR-WTB_64800711622_1x07_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800711622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -7 -7 -Connector_Wuerth -Wuerth_WR-WTB_64800811622_1x08_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800811622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -8 -8 -Connector_Wuerth -Wuerth_WR-WTB_64800911622_1x09_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64800911622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -9 -9 -Connector_Wuerth -Wuerth_WR-WTB_64801011622_1x10_P1.50mm_Vertical -Wuerth WR-WTB series connector, 64801011622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator -connector Wuerth WR-WTB vertical -0 -10 -10 -Converter_ACDC -Converter_ACDC_CUI_PBO-3-Sxx_THT_Vertical -ACDC-Converter, 3W, CUI PBO-3, THT https://www.cui.com/product/resource/pbo-3.pdf -Converter AC-DC THT Vertical -0 -6 -6 -Converter_ACDC -Converter_ACDC_Hahn_HS-400xx_THT -ACDC-Converter, 3W, Hahn-HS-400xx, THT https://www.schukat.com/schukat/schukat_cms_de.nsf/index/FrameView?OpenDocument&art=HS40009&wg=M7942 -Hahn ACDC-Converter THT -0 -4 -4 -Converter_ACDC -Converter_ACDC_HiLink_HLK-PMxx -ACDC-Converter, 3W, HiLink, HLK-PMxx, THT, http://www.hlktech.net/product_detail.php?ProId=54 -ACDC-Converter 3W THT HiLink board mount module -0 -4 -4 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-02-xx_SMD -ACDC-Converter, 3W, Meanwell, IRM-02, SMD, https://www.meanwell.com/Upload/PDF/IRM-02/IRM-02-SPEC.PDF -ACDC-Converter 3W -0 -14 -14 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-02-xx_THT -ACDC-Converter, 2W, Meanwell, IRM-02, THT, https://www.meanwell.co.uk/media/productPDF/IRM-02-spec.pdf -ACDC-Converter 2W THT -0 -4 -4 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-03-xx_SMD -ACDC-Converter, 3W, Meanwell, IRM-03, SMD, http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-03 -ACDC-Converter 3W -0 -14 -14 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-03-xx_THT -ACDC-Converter, 3W, Meanwell, IRM-03, THT, https://www.meanwell.com/Upload/PDF/IRM-03/IRM-03-SPEC.PDF -ACDC-Converter 3W THT -0 -5 -5 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-05-xx_THT -http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-05 -ACDC-Converter 5W Meanwell IRM-05 -0 -4 -4 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-10-xx_THT -http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-10 -ACDC-Converter 10W Meanwell IRM-10 -0 -4 -4 -Converter_ACDC -Converter_ACDC_MeanWell_IRM-20-xx_THT -ACDC-Converter, 20W, Meanwell, IRM-20, THT http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-20 -ACDC-Converter 20W Meanwell IRM-20 -0 -4 -4 -Converter_ACDC -Converter_ACDC_RECOM_RAC01-xxSGB_THT -https://www.recom-power.com/pdf/Powerline-AC-DC/RAC01-GB.pdf -recom power ac dc rac01xxgb rac01-05sgb rac01-12sgb -0 -4 -4 -Converter_ACDC -Converter_ACDC_RECOM_RAC04-xxSGx_THT -https://www.recom-power.com/pdf/Powerline-AC-DC/RAC04-GA.pdf -recom power ac dc -0 -5 -5 -Converter_ACDC -Converter_ACDC_RECOM_RAC05-xxSK_THT -https://www.recom-power.com/pdf/Powerline-AC-DC/RAC05-K.pdf -recom power ac dc -0 -5 -5 -Converter_ACDC -Converter_ACDC_TRACO_TMG-15_THT -ACDC-Converter, TRACO, TMG Series 15 https://www.tracopower.com/products/tmg.pdf -ACDC-Converter TRACO TMG Series 15 -0 -4 -4 -Converter_ACDC -Converter_ACDC_TRACO_TMLM-04_THT -ACDC-Converter, TRACO, TMLM Series 04 https://www.tracopower.com/products/tmlm.pdf -ACDC-Converter TRACO TMLM Series 04 -0 -7 -7 -Converter_ACDC -Converter_ACDC_TRACO_TMLM-05_THT -ACDC-Converter, TRACO TMLM 05,https://www.tracopower.com/products/tmlm.pdf -ACDC-Converter TRACO TMLM 05 -0 -4 -4 -Converter_ACDC -Converter_ACDC_TRACO_TMLM-10-20_THT -ACDC-Converter, TRACO TMLM 10, TRACO TMLM 20, https://www.tracopower.com/products/tmlm.pdf -ACDC-Converter TRACO TMLM 10 and TMLM 20 -0 -4 -4 -Converter_ACDC -Converter_ACDC_Vigortronix_VTX-214-010-xxx_THT -Vigortronix VTX-214-010-xxx serie of ACDC converter, http://www.vigortronix.com/10WattACDCPCBPowerModule.aspx -Vigortronix VTX-214-010-xxx serie of ACDC converter -0 -4 -4 -Converter_ACDC -Converter_ACDC_Vigortronix_VTX-214-015-1xx_THT -Vigortronix VTX-214-010-xxx serie of ACDC converter, http://www.vigortronix.com/10WattACDCPCBPowerModule.aspx -Vigortronix VTX-214-010-xxx serie of ACDC converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_Artesyn_ATA_SMD -DCDC-Converter, Artesyn, ATA Series, 3W Single and Dual Output, 1500VDC Isolation, 24.0x13.7x8.0mm https://www.artesyn.com/power/assets/ata_series_ds_01apr2015_79c25814fd.pdf https://www.artesyn.com/power/assets/trn_dc-dc_ata_3w_series_releas1430412818_techref.pdf -DCDC SMD -0 -7 -7 -Converter_DCDC -Converter_DCDC_Bothhand_CFUDxxxx_THT -DCDC-Converter, BOTHHAND, Type CFxxxx-Serie, (Very dodgy url but was the only at hand), -DCDC-Converter BOTHHAND Type CFxxxx-Serie -0 -10 -10 -Converter_DCDC -Converter_DCDC_Bothhand_CFUSxxxxEH_THT -DCDC-Converter, BOTHHAND, Type CFxxxx-Serie, (Very dodgy url but was the only at hand), -DCDC-Converter BOTHHAND Type CFxxxx-Serie -0 -9 -9 -Converter_DCDC -Converter_DCDC_Bothhand_CFUSxxxx_THT -DCDC-Converter, BOTHHAND, Type CFxxxx-Serie, (Very dodgy url but was the only at hand), -DCDC-Converter BOTHHAND Type CFxxxx-Serie -0 -8 -8 -Converter_DCDC -Converter_DCDC_Cincon_EC5BExx_Dual_THT -DCDC-Converter, CINCON, EC5BExx, 18-36VDC to Dual output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/B%20CASE/SPEC-EC5BE-V24.pdf -DCDC-Converter CINCON EC5BExx 18-36VDC to Dual output -0 -6 -6 -Converter_DCDC -Converter_DCDC_Cincon_EC5BExx_Single_THT -DCDC-Converter, CINCON, EC5BExx, 18-36VDC to dual output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/B%20CASE/SPEC-EC5BE-V24.pdf -DCDC-Converter CINCON EC5BExx 18-36VDC to dual output -0 -4 -4 -Converter_DCDC -Converter_DCDC_Cincon_EC6Cxx_Dual-Triple_THT -DCDC-Converter, CINCON, EC6Cxx, dual or tripple output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf -DCDC-Converter CINCON EC6Cxx dual or tripple output -0 -7 -7 -Converter_DCDC -Converter_DCDC_Cincon_EC6Cxx_Single_THT -DCDC-Converter, CINCON, EC6Cxx, single output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf -DCDC-Converter CINCON EC6Cxx single output -0 -6 -6 -Converter_DCDC -Converter_DCDC_MeanWell_NID30_THT -Meanwell DCDC non-isolated converter SIP module, http://www.meanwell.com/webapp/product/search.aspx?prod=nid30 -DCDC non-isolated converter -0 -11 -11 -Converter_DCDC -Converter_DCDC_MeanWell_NID60_THT -MeanWell NID60, http://www.meanwell.com/Upload/PDF/NID60/NID60-SPEC.PDF -MeanWell NID60 -0 -11 -11 -Converter_DCDC -Converter_DCDC_Murata_MGJ2DxxxxxxSC_THT -Murata MGJ2DxxxxxxSC, 19.5x9.8x12.5mm, 5.2kVDC Isolated, 2W, SIP package style, https://power.murata.com/data/power/ncl/kdc_mgj2.pdf -Murata MGJ2DxxxxxxSC -0 -5 -5 -Converter_DCDC -Converter_DCDC_Murata_MGJ3 -Murata MGJ3, 5.2kVDC Isolated 3W Gate Drive, 15V/5V/5V Configurable, 22.61x23.11x14.19mm, https://power.murata.com/datasheet?/data/power/ncl/kdc_mgj3.pdf -DCDC SMD -0 -7 -7 -Converter_DCDC -Converter_DCDC_Murata_NCS1SxxxxSC_THT -Murata NCS1SxxxxSC https://power.murata.com/data/power/ncl/kdc_ncs1.pdf (Script generated with StandardBox.py) (Murata NCS1SxxxxSC https://power.murata.com/data/power/ncl/kdc_ncs1.pdf) -Murata NCS1SxxxxSC -0 -5 -5 -Converter_DCDC -Converter_DCDC_RECOM_R-78B-2.0_THT -DCDC-Converter, RECOM, RECOM_R-78B-2.0, SIP-3, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78Bxx-2.0.pdf -dc-dc recom buck sip-3 pitch 2.54mm -0 -3 -3 -Converter_DCDC -Converter_DCDC_RECOM_R-78E-0.5_THT -DCDC-Converter, RECOM, RECOM_R-78E-0.5, SIP-3, pitch 2.54mm, package size 11.6x8.5x10.4mm^3, https://www.recom-power.com/pdf/Innoline/R-78Exx-0.5.pdf -dc-dc recom buck sip-3 pitch 2.54mm -0 -3 -3 -Converter_DCDC -Converter_DCDC_RECOM_R-78HB-0.5L_THT -DCDC-Converter, RECOM, RECOM_R-78HB-0.5L, SIP-3, Horizontally Mounted, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78HBxx-0.5_L.pdf -dc-dc recom buck sip-3 pitch 2.54mm -0 -3 -3 -Converter_DCDC -Converter_DCDC_RECOM_R-78HB-0.5_THT -DCDC-Converter, RECOM, RECOM_R-78HB-0.5, SIP-3, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78HBxx-0.5_L.pdf -dc-dc recom buck sip-3 pitch 2.54mm -0 -3 -3 -Converter_DCDC -Converter_DCDC_RECOM_R-78S-0.1_THT -DCDC-Converter, RECOM, RECOM_R-78S-0.1, SIP-4, pitch 2.54mm, package size 11.6x8.5x10.4mm^3, https://www.recom-power.com/pdf/Innoline/R-78Sxx-0.1.pdf -dc-dc recom buck sip-4 pitch 2.54mm -0 -4 -4 -Converter_DCDC -Converter_DCDC_RECOM_R5xxxDA_THT -DCDC-Converter, RECOM, RECOM_R5xxxDA, SIP-12, Horizontally Mounted, pitch 2.54mm, package size 32.2x9.1x15mm^3, https://www.recom-power.com/pdf/Innoline/R-5xxxPA_DA.pdf -dc-dc recom buck sip-12 pitch 2.54mm -0 -12 -12 -Converter_DCDC -Converter_DCDC_RECOM_R5xxxPA_THT -DCDC-Converter, RECOM, RECOM_R5xxxPA, SIP-12, pitch 2.54mm, package size 32.2x9.1x15mm^3, https://www.recom-power.com/pdf/Innoline/R-5xxxPA_DA.pdf -dc-dc recom buck sip-12 pitch 2.54mm -0 -12 -12 -Converter_DCDC -Converter_DCDC_RECOM_RPMx.x-x.0 -https://www.recom-power.com/pdf/Innoline/RPM-6.0.pdf -dc-dc recom buck lga-25 pitch 2.29mm -0 -25 -25 -Converter_DCDC -Converter_DCDC_TRACO_TEN10-xxxx_Dual_THT -DCDC-Converter, TRACO, TEN10-xxxx, single output, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf -DCDC-Converter TRACO TEN10-xxxx single output -0 -5 -5 -Converter_DCDC -Converter_DCDC_TRACO_TEN10-xxxx_Single_THT -DCDC-Converter, TRACO, TEN10-xxxx, single output, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf -DCDC-Converter TRACO TEN10-xxxx single output -0 -4 -4 -Converter_DCDC -Converter_DCDC_TRACO_TEN10-xxxx_THT -DCDC-Converter, TRACO, TEN10-xxxx, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf -DCDC-Converter TRACO TEN10-xxxx -0 -4 -4 -Converter_DCDC -Converter_DCDC_TRACO_TEN20-xxxx-N4_THT -DCDC-Converter TRACO TEN20 Generic, https://assets.tracopower.com/20171102100522/TEN20/documents/ten20-datasheet.pdf -DCDC-Converter TRACO TEN20 Generic -0 -5 -5 -Converter_DCDC -Converter_DCDC_TRACO_TEN20-xxxx_THT -DCDC-Converter TRACO TEN20 Generic, https://assets.tracopower.com/20171102100522/TEN20/documents/ten20-datasheet.pdf -DCDC-Converter TRACO TEN20 Generic -0 -6 -6 -Converter_DCDC -Converter_DCDC_TRACO_TMR-1-xxxx_Dual_THT -DCDC-Converter, TRACO, TMR 1-xxxx, Dual output, Rev. March 21.2016 -DCDC-Converter TRACO TMR1-xxxx Dual_output -0 -5 -5 -Converter_DCDC -Converter_DCDC_TRACO_TMR-1-xxxx_Single_THT -DCDC-Converter, TRACO, TMR 1-xxxx, Single output, Rev. March 21.2016 -DCDC-Converter TRACO TMR1-xxxx Single_output -0 -4 -4 -Converter_DCDC -Converter_DCDC_TRACO_TMR-1SM_SMD -http://assets.tracopower.com/TMR1SM/documents/tmr1sm-datasheet.pdf -DCDC SMD TRACO TMR-1SM -0 -7 -7 -Converter_DCDC -Converter_DCDC_TRACO_TMR-2xxxxWI_THT -https://www.tracopower.com/products/tmr2wi.pdf -DCDC-Converter TRACO TMRxxxxWI Single/Dual_output -0 -7 -7 -Converter_DCDC -Converter_DCDC_TRACO_TMR-xxxx_THT -DCDC-Converter, TRACO, TMR xxxx, Single/Dual output, http://www.datasheetlib.com/datasheet/135136/tmr-2-2410e_traco-power.html?page=3#datasheet -DCDC-Converter TRACO TMRxxxx Single/Dual_output -0 -7 -7 -Converter_DCDC -Converter_DCDC_TRACO_TSR-1_THT -DCDC-Converter, TRACO, TSR 1-xxxx -DCDC-Converter TRACO TSR-1 -0 -3 -3 -Converter_DCDC -Converter_DCDC_XP_POWER-IA48xxD_THT -XP_POWER IA48xxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator -XP_POWER IA48xxD DIP DCDC-Converter -0 -6 -6 -Converter_DCDC -Converter_DCDC_XP_POWER-IA48xxS_THT -XP_POWER IA48xxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator -XP_POWER IA48xxS SIP DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_XP_POWER-IAxxxxD_THT -XP_POWER IAxxxxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator -XP_POWER IAxxxxD DIP DCDC-Converter -0 -6 -6 -Converter_DCDC -Converter_DCDC_XP_POWER-IAxxxxS_THT -XP_POWER IAxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator -XP_POWER IAxxxxS SIP DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_XP_POWER-IHxxxxDH_THT -XP_POWER IHxxxxDH, DIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator -XP_POWER IHxxxxDH DIP DCDC-Converter -0 -6 -6 -Converter_DCDC -Converter_DCDC_XP_POWER-IHxxxxD_THT -XP_POWER IHxxxxD, DIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator -XP_POWER IHxxxxD DIP DCDC-Converter -0 -6 -6 -Converter_DCDC -Converter_DCDC_XP_POWER-IHxxxxSH_THT -XP_POWER IHxxxxSH, SIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator -XP_POWER IHxxxxSH SIP DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_XP_POWER-IHxxxxS_THT -XP_POWER IHxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator -XP_POWER IHxxxxS SIP DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_XP_POWER-ISU02_SMD -DCDC-Converter, XP POWER, ISU02 Series, 2W Single and Dual Output, 1500VDC Isolation, 19.0x17.0x8.7mm https://www.xppower.com/Portals/0/pdfs/SF_ISU02.pdf -DCDC SMD XP POWER ISU02 -0 -7 -7 -Converter_DCDC -Converter_DCDC_XP_POWER-ITQxxxxS-H_THT -XP_POWER ITQxxxxS-H, SIP, (https://www.xppower.com/pdfs/SF_ITQ.pdf), generated with kicad-footprint-generator -XP_POWER ITQxxxxS-H SIP DCDC-Converter -0 -6 -6 -Converter_DCDC -Converter_DCDC_XP_POWER-ITXxxxxSA_THT -XP_POWER ITXxxxxSA, SIP, (https://www.xppower.com/pdfs/SF_ITX.pdf), generated with kicad-footprint-generator -XP_POWER ITXxxxxSA SIP DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_XP_POWER-ITxxxxxS_THT -XP_POWER ITxxxxxS, SIP, (https://www.xppower.com/pdfs/SF_ITX.pdf https://www.xppower.com/pdfs/SF_ITQ.pdf), generated with kicad-footprint-generator -XP_POWER ITxxxxxS SIP DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_XP_POWER_JTExxxxDxx_THT -DCDC-Converter, XP POWER, Type JTE06 Series, Dual Output -DCDC-Converter XP_POWER JTE06 Dual -0 -8 -8 -Converter_DCDC -Converter_DCDC_muRata_CRE1xxxxxx3C_THT -Isolated 1W single output DC/DC, http://power.murata.com/data/power/ncl/kdc_cre1.pdf -Isolated 1W single output DC/DC -0 -4 -4 -Converter_DCDC -Converter_DCDC_muRata_CRE1xxxxxxDC_THT -Isloated DC-DC, http://power.murata.com/data/power/ncl/kdc_cre1.pdf -Isloated DC-DC -0 -4 -4 -Converter_DCDC -Converter_DCDC_muRata_CRE1xxxxxxSC_THT -http://power.murata.com/data/power/ncl/kdc_cre1.pdf -murata dc-dc transformer -0 -4 -4 -Converter_DCDC -Converter_DCDC_muRata_NMAxxxxDC_THT -Isolated 1W DCDC-Converter, http://power.murata.com/data/power/ncl/kdc_nma.pdf -Isolated 1W DCDC-Converter -0 -6 -6 -Converter_DCDC -Converter_DCDC_muRata_NMAxxxxSC_THT -muRata NMAxxxxSC footprint based on SIP7, http://power.murata.com/data/power/ncl/kdc_nma.pdf -muRata NMAxxxxSC DCDC-Converter -0 -5 -5 -Converter_DCDC -Converter_DCDC_muRata_NXE2SxxxxMC_THT -Isolated 2W Single Output SM DC/DC Converters, http://power.murata.com/data/power/ncl/kdc_nxe2.pdf -Isolated 2W Single Output SM DC/DC Converters -0 -5 -5 -Converter_DCDC -Converter_DCDC_muRata_OKI-78SR_Horizontal -https://power.murata.com/data/power/oki-78sr.pdf -78sr3.3 78sr5 78sr9 78sr12 78srXX -0 -3 -3 -Converter_DCDC -Converter_DCDC_muRata_OKI-78SR_Vertical -https://power.murata.com/data/power/oki-78sr.pdf -78sr3.3 78sr5 78sr9 78sr12 78srXX -0 -3 -3 -Crystal -Crystal_AT310_D3.0mm_L10.0mm_Horizontal -Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf -['AT310'] -0 -2 -2 -Crystal -Crystal_AT310_D3.0mm_L10.0mm_Horizontal_1EP_style1 -Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf -['AT310'] -0 -3 -3 -Crystal -Crystal_AT310_D3.0mm_L10.0mm_Horizontal_1EP_style2 -Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf -['AT310'] -0 -5 -3 -Crystal -Crystal_AT310_D3.0mm_L10.0mm_Vertical -Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf -['AT310'] -0 -2 -2 -Crystal -Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal -Crystal THT C26-LF 6.5mm length 2.06mm diameter -['C26-LF'] -0 -2 -2 -Crystal -Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal_1EP_style1 -Crystal THT C26-LF 6.5mm length 2.06mm diameter -['C26-LF'] -0 -3 -3 -Crystal -Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal_1EP_style2 -Crystal THT C26-LF 6.5mm length 2.06mm diameter -['C26-LF'] -0 -5 -3 -Crystal -Crystal_C26-LF_D2.1mm_L6.5mm_Vertical -Crystal THT C26-LF 6.5mm length 2.06mm diameter -['C26-LF'] -0 -2 -2 -Crystal -Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal -Crystal THT C38-LF 8.0mm length 3.0mm diameter -['C38-LF'] -0 -2 -2 -Crystal -Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal_1EP_style1 -Crystal THT C38-LF 8.0mm length 3.0mm diameter -['C38-LF'] -0 -3 -3 -Crystal -Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal_1EP_style2 -Crystal THT C38-LF 8.0mm length 3.0mm diameter -['C38-LF'] -0 -5 -3 -Crystal -Crystal_C38-LF_D3.0mm_L8.0mm_Vertical -Crystal THT C38-LF 8.0mm length 3.0mm diameter -['C38-LF'] -0 -2 -2 -Crystal -Crystal_DS10_D1.0mm_L4.3mm_Horizontal -Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS10'] -0 -2 -2 -Crystal -Crystal_DS10_D1.0mm_L4.3mm_Horizontal_1EP_style1 -Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS10'] -0 -3 -3 -Crystal -Crystal_DS10_D1.0mm_L4.3mm_Horizontal_1EP_style2 -Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS10'] -0 -5 -3 -Crystal -Crystal_DS10_D1.0mm_L4.3mm_Vertical -Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS10'] -0 -2 -2 -Crystal -Crystal_DS15_D1.5mm_L5.0mm_Horizontal -Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS15'] -0 -2 -2 -Crystal -Crystal_DS15_D1.5mm_L5.0mm_Horizontal_1EP_style1 -Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS15'] -0 -3 -3 -Crystal -Crystal_DS15_D1.5mm_L5.0mm_Horizontal_1EP_style2 -Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS15'] -0 -5 -3 -Crystal -Crystal_DS15_D1.5mm_L5.0mm_Vertical -Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS15'] -0 -2 -2 -Crystal -Crystal_DS26_D2.0mm_L6.0mm_Horizontal -Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS26'] -0 -2 -2 -Crystal -Crystal_DS26_D2.0mm_L6.0mm_Horizontal_1EP_style1 -Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS26'] -0 -3 -3 -Crystal -Crystal_DS26_D2.0mm_L6.0mm_Horizontal_1EP_style2 -Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS26'] -0 -5 -3 -Crystal -Crystal_DS26_D2.0mm_L6.0mm_Vertical -Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS26'] -0 -2 -2 -Crystal -Crystal_HC18-U_Horizontal -Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC18-U_Horizontal_1EP_style1 -Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC18-U_Horizontal_1EP_style2 -Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC18-U_Vertical -Crystal THT HC-18/U, http://5hertz.com/pdfs/04404_D.pdf -THT crystalHC-18/U -0 -2 -2 -Crystal -Crystal_HC33-U_Horizontal -Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC33-U_Horizontal_1EP_style1 -Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC33-U_Horizontal_1EP_style2 -Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC33-U_Vertical -Crystal THT HC-33/U, http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf -THT crystalHC-33/U -0 -2 -2 -Crystal -Crystal_HC35-U -Crystal, Quarz, HC35/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/TO71xx.pdf -Crystal Quarz HC35/U -0 -3 -3 -Crystal -Crystal_HC49-4H_Vertical -Crystal THT HC-49-4H http://5hertz.com/pdfs/04404_D.pdf -THT crystalHC-49-4H -0 -2 -2 -Crystal -Crystal_HC49-U-3Pin_Vertical -Crystal THT HC-49/U, 3pin-version, http://www.raltron.com/products/pdfspecs/crystal_hc_49_45_51.pdf -THT crystalHC-49/U -0 -3 -3 -Crystal -Crystal_HC49-U_Horizontal -Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC49-U_Horizontal_1EP_style1 -Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC49-U_Horizontal_1EP_style2 -Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC49-U_Vertical -Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf -THT crystalHC-49/U -0 -2 -2 -Crystal -Crystal_HC50_Horizontal -Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC50_Horizontal_1EP_style1 -Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC50_Horizontal_1EP_style2 -Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC50_Vertical -Crystal THT HC-50, http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf -THT crystalHC-50 -0 -2 -2 -Crystal -Crystal_HC51-U_Vertical -Crystal THT HC-51/U, http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf -THT crystalHC-51/U -0 -2 -2 -Crystal -Crystal_HC51_Horizontal -Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC51_Horizontal_1EP_style1 -Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC51_Horizontal_1EP_style2 -Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC52-6mm_Horizontal -Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC52-6mm_Horizontal_1EP_style1 -Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC52-6mm_Horizontal_1EP_style2 -Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC52-6mm_Vertical -Crystal THT HC-52/6mm, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystalHC-49/U -0 -2 -2 -Crystal -Crystal_HC52-8mm_Horizontal -Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC52-8mm_Horizontal_1EP_style1 -Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC52-8mm_Horizontal_1EP_style2 -Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC52-8mm_Vertical -Crystal THT HC-52/8mm, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystalHC-49/U -0 -2 -2 -Crystal -Crystal_HC52-U-3Pin_Vertical -Crystal THT HC-52/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystalHC-52/U -0 -3 -3 -Crystal -Crystal_HC52-U_Horizontal -Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -2 -2 -Crystal -Crystal_HC52-U_Horizontal_1EP_style1 -Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -3 -3 -Crystal -Crystal_HC52-U_Horizontal_1EP_style2 -Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal -0 -5 -3 -Crystal -Crystal_HC52-U_Vertical -Crystal THT HC-52/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf -THT crystal HC-52/U -0 -2 -2 -Crystal -Crystal_Round_D1.0mm_Vertical -Crystal THT DS10 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS10'] -0 -2 -2 -Crystal -Crystal_Round_D1.5mm_Vertical -Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS15'] -0 -2 -2 -Crystal -Crystal_Round_D2.0mm_Vertical -Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf -['DS26'] -0 -2 -2 -Crystal -Crystal_Round_D3.0mm_Vertical -Crystal THT C38-LF 8.0mm length 3.0mm diameter -['C38-LF'] -0 -2 -2 -Crystal -Crystal_SMD_0603-2Pin_6.0x3.5mm -SMD Crystal SERIES SMD0603/2 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-2.pdf, 6.0x3.5mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_0603-2Pin_6.0x3.5mm_HandSoldering -SMD Crystal SERIES SMD0603/2 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-2.pdf, hand-soldering, 6.0x3.5mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_0603-4Pin_6.0x3.5mm -SMD Crystal SERIES SMD0603/4 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-4.pdf, 6.0x3.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_0603-4Pin_6.0x3.5mm_HandSoldering -SMD Crystal SERIES SMD0603/4 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-4.pdf, hand-soldering, 6.0x3.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_2012-2Pin_2.0x1.2mm -SMD Crystal 2012/2 http://txccrystal.com/images/pdf/9ht11.pdf, 2.0x1.2mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_2012-2Pin_2.0x1.2mm_HandSoldering -SMD Crystal 2012/2 http://txccrystal.com/images/pdf/9ht11.pdf, hand-soldering, 2.0x1.2mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_2016-4Pin_2.0x1.6mm -SMD Crystal SERIES SMD2016/4 http://www.q-crystal.com/upload/5/2015552223166229.pdf, 2.0x1.6mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_2520-4Pin_2.5x2.0mm -SMD Crystal SERIES SMD2520/4 http://www.newxtal.com/UploadFiles/Images/2012-11-12-09-29-09-776.pdf, 2.5x2.0mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_3215-2Pin_3.2x1.5mm -SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf -SMD SMT Crystal -0 -2 -2 -Crystal -Crystal_SMD_3225-4Pin_3.2x2.5mm -SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_3225-4Pin_3.2x2.5mm_HandSoldering -SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_5032-2Pin_5.0x3.2mm -SMD Crystal SERIES SMD2520/2 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, 5.0x3.2mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_5032-2Pin_5.0x3.2mm_HandSoldering -SMD Crystal SERIES SMD2520/2 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_5032-4Pin_5.0x3.2mm -SMD Crystal SERIES SMD2520/4 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, 5.0x3.2mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_7050-2Pin_7.0x5.0mm -SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_7050-2Pin_7.0x5.0mm_HandSoldering -SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_7050-4Pin_7.0x5.0mm -SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_Abracon_ABM3-2Pin_5.0x3.2mm -Abracon Miniature Ceramic Smd Crystal ABM3 http://www.abracon.com/Resonators/abm3.pdf, 5.0x3.2mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_Abracon_ABM3-2Pin_5.0x3.2mm_HandSoldering -Abracon Miniature Ceramic Smd Crystal ABM3 http://www.abracon.com/Resonators/abm3.pdf, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_Abracon_ABM3B-4Pin_5.0x3.2mm -Abracon Miniature Ceramic Smd Crystal ABM3B http://www.abracon.com/Resonators/abm3b.pdf, 5.0x3.2mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_Abracon_ABM3C-4Pin_5.0x3.2mm -Abracon Miniature Ceramic Smd Crystal ABM3C http://www.abracon.com/Resonators/abm3c.pdf, 5.0x3.2mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_Abracon_ABM7-2Pin_6.0x3.5mm -SMD Crystal Abracon ABM7, https://abracon.com/Resonators/abm7.pdf -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_Abracon_ABM8G-4Pin_3.2x2.5mm -Abracon Miniature Ceramic Smd Crystal ABM8G http://www.abracon.com/Resonators/ABM8G.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_Abracon_ABM10-4Pin_2.5x2.0mm -Abracon Miniature Ceramic Smd Crystal ABM10 http://www.abracon.com/Resonators/ABM10.pdf -SMD SMT crystal Abracon ABM10 -0 -4 -4 -Crystal -Crystal_SMD_Abracon_ABS25-4Pin_8.0x3.8mm -Abracon Miniature Ceramic SMD Crystal ABS25 https://abracon.com/Resonators/abs25.pdf, 8.0x3.8mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_ECS_CSM3X-2Pin_7.6x4.1mm -http://www.ecsxtal.com/store/pdf/CSM-3X.pdf -Crystal CSM-3X -0 -2 -2 -Crystal -Crystal_SMD_EuroQuartz_EQ161-2Pin_3.2x1.5mm -SMD Crystal EuroQuartz EQ161 series http://cdn-reichelt.de/documents/datenblatt/B400/PG32768C.pdf, 3.2x1.5mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_EuroQuartz_EQ161-2Pin_3.2x1.5mm_HandSoldering -SMD Crystal EuroQuartz EQ161 series http://cdn-reichelt.de/documents/datenblatt/B400/PG32768C.pdf, hand-soldering, 3.2x1.5mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_EuroQuartz_MJ-4Pin_5.0x3.2mm -SMD Crystal EuroQuartz MJ series http://cdn-reichelt.de/documents/datenblatt/B400/MJ.pdf, 5.0x3.2mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_MJ-4Pin_5.0x3.2mm_HandSoldering -SMD Crystal EuroQuartz MJ series http://cdn-reichelt.de/documents/datenblatt/B400/MJ.pdf, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_MQ-4Pin_7.0x5.0mm -SMD Crystal EuroQuartz MQ series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, 7.0x5.0mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_MQ-4Pin_7.0x5.0mm_HandSoldering -SMD Crystal EuroQuartz MQ series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_MQ2-2Pin_7.0x5.0mm -SMD Crystal EuroQuartz MQ2 series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, 7.0x5.0mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_EuroQuartz_MQ2-2Pin_7.0x5.0mm_HandSoldering -SMD Crystal EuroQuartz MQ2 series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_EuroQuartz_MT-4Pin_3.2x2.5mm -SMD Crystal EuroQuartz MT series http://cdn-reichelt.de/documents/datenblatt/B400/MT.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_MT-4Pin_3.2x2.5mm_HandSoldering -SMD Crystal EuroQuartz MT series http://cdn-reichelt.de/documents/datenblatt/B400/MT.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_X22-4Pin_2.5x2.0mm -SMD Crystal EuroQuartz X22 series http://cdn-reichelt.de/documents/datenblatt/B400/DS_X22.pdf, 2.5x2.0mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_EuroQuartz_X22-4Pin_2.5x2.0mm_HandSoldering -SMD Crystal EuroQuartz X22 series http://cdn-reichelt.de/documents/datenblatt/B400/DS_X22.pdf, hand-soldering, 2.5x2.0mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_FOX_FE-2Pin_7.5x5.0mm -crystal Ceramic Resin Sealed SMD http://www.foxonline.com/pdfs/fe.pdf, 7.5x5.0mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_FOX_FE-2Pin_7.5x5.0mm_HandSoldering -crystal Ceramic Resin Sealed SMD http://www.foxonline.com/pdfs/fe.pdf, hand-soldering, 7.5x5.0mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_FOX_FQ7050-2Pin_7.0x5.0mm -FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_FOX_FQ7050-2Pin_7.0x5.0mm_HandSoldering -FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_FOX_FQ7050-4Pin_7.0x5.0mm -FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_FrontierElectronics_FM206 -SMD Watch Crystal FrontierElectronics FM206 6.0mm length 1.9mm diameter http://www.chinafronter.com/wp-content/uploads/2013/12/FM206.pdf -['FM206'] -0 -3 -3 -Crystal -Crystal_SMD_G8-2Pin_3.2x1.5mm -SMD Crystal G8, 3.2x1.5mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_G8-2Pin_3.2x1.5mm_HandSoldering -SMD Crystal G8, hand-soldering, 3.2x1.5mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_HC49-SD -SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, 11.4x4.7mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_HC49-SD_HandSoldering -SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, hand-soldering, 11.4x4.7mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC1V-T1A-2Pin_8.0x3.7mm -SMD Crystal MicroCrystal CC1V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC1V-T1A.pdf, 8.0x3.7mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC1V-T1A-2Pin_8.0x3.7mm_HandSoldering -SMD Crystal MicroCrystal CC1V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC1V-T1A.pdf, hand-soldering, 8.0x3.7mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm -SMD Crystal MicroCrystal CC4V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC4V-T1A.pdf, 5.0x1.9mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm_HandSoldering -SMD Crystal MicroCrystal CC4V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC4V-T1A.pdf, hand-soldering, 5.0x1.9mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC5V-T1A-2Pin_4.1x1.5mm -SMD Crystal MicroCrystal CC5V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC5V-T1A.pdf, 4.1x1.5mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC5V-T1A-2Pin_4.1x1.5mm_HandSoldering -SMD Crystal MicroCrystal CC5V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC5V-T1A.pdf, hand-soldering, 4.1x1.5mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC7V-T1A-2Pin_3.2x1.5mm -SMD Crystal MicroCrystal CC7V-T1A/CM7V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC7V-T1A.pdf, 3.2x1.5mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC7V-T1A-2Pin_3.2x1.5mm_HandSoldering -SMD Crystal MicroCrystal CC7V-T1A/CM7V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CC1V-T1A.pdf, hand-soldering, 3.2x1.5mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC8V-T1A-2Pin_2.0x1.2mm -SMD Crystal MicroCrystal CC8V-T1A/CM8V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC8V-T1A.pdf, 2.0x1.2mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CC8V-T1A-2Pin_2.0x1.2mm_HandSoldering -SMD Crystal MicroCrystal CC8V-T1A/CM8V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CC8V-T1A.pdf, hand-soldering, 2.0x1.2mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CM9V-T1A-2Pin_1.6x1.0mm -SMD Crystal MicroCrystal CM9V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CM9V-T1A.pdf, 1.6x1.0mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_CM9V-T1A-2Pin_1.6x1.0mm_HandSoldering -SMD Crystal MicroCrystal CM9V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CM9V-T1A.pdf, hand-soldering, 1.6x1.0mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_MicroCrystal_MS1V-T1K -SMD Watch Crystal MicroCrystal MS1V-T1K 6.1mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/MS1V-T1K.pdf -['MS1V-T1K'] -0 -3 -3 -Crystal -Crystal_SMD_MicroCrystal_MS3V-T1R -SMD Watch Crystal MicroCrystal MS3V-T1R 5.2mm length 1.4mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/MS3V-T1R.pdf -['MS3V-T1R'] -0 -3 -3 -Crystal -Crystal_SMD_Qantek_QC5CB-2Pin_5x3.2mm -SMD Crystal Qantek QC5CB, https://www.qantek.com/tl_files/products/crystals/QC5CB.pdf -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_SeikoEpson_FA238-4Pin_3.2x2.5mm -crystal Epson Toyocom FA-238 https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_FA238-4Pin_3.2x2.5mm_HandSoldering -crystal Epson Toyocom FA-238 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_FA238V-4Pin_3.2x2.5mm -crystal Epson Toyocom FA-238 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_FA238V-4Pin_3.2x2.5mm_HandSoldering -crystal Epson Toyocom FA-238 series http://www.mouser.com/ds/2/137/1721499-465440.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MA406-4Pin_11.7x4.0mm -SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 11.7x4.0mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MA406-4Pin_11.7x4.0mm_HandSoldering -SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 11.7x4.0mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MA505-2Pin_12.7x5.1mm -SMD Crystal Seiko Epson MC-505 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 12.7x5.1mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_SeikoEpson_MA505-2Pin_12.7x5.1mm_HandSoldering -SMD Crystal Seiko Epson MC-505 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 12.7x5.1mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_SeikoEpson_MA506-4Pin_12.7x5.1mm -SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 12.7x5.1mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MA506-4Pin_12.7x5.1mm_HandSoldering -SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 12.7x5.1mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC146-4Pin_6.7x1.5mm -SMD Crystal Seiko Epson MC-146 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, 6.7x1.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC146-4Pin_6.7x1.5mm_HandSoldering -SMD Crystal Seiko Epson MC-146 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, hand-soldering, 6.7x1.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC156-4Pin_7.1x2.5mm -SMD Crystal Seiko Epson MC-156 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, 7.1x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC156-4Pin_7.1x2.5mm_HandSoldering -SMD Crystal Seiko Epson MC-156 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, hand-soldering, 7.1x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC306-4Pin_8.0x3.2mm -SMD Crystal Seiko Epson MC-306 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 8.0x3.2mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC306-4Pin_8.0x3.2mm_HandSoldering -SMD Crystal Seiko Epson MC-306 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 8.0x3.2mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC405-2Pin_9.6x4.1mm -SMD Crystal Seiko Epson MC-405 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 9.6x4.1mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_SeikoEpson_MC405-2Pin_9.6x4.1mm_HandSoldering -SMD Crystal Seiko Epson MC-405 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 9.6x4.1mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_SeikoEpson_MC406-4Pin_9.6x4.1mm -SMD Crystal Seiko Epson MC-406 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 9.6x4.1mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_MC406-4Pin_9.6x4.1mm_HandSoldering -SMD Crystal Seiko Epson MC-406 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 9.6x4.1mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm -crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering -crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_TXC_7A-2Pin_5x3.2mm -SMD Crystal TXC 7A http://txccrystal.com/images/pdf/7a.pdf -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_TXC_7M-4Pin_3.2x2.5mm -SMD Crystal TXC 7M http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package -SMD SMT crystal -0 -4 -4 -Crystal -Crystal_SMD_TXC_7M-4Pin_3.2x2.5mm_HandSoldering -SMD Crystal TXC 7M http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal hand-soldering -0 -4 -4 -Crystal -Crystal_SMD_TXC_9HT11-2Pin_2.0x1.2mm -SMD Crystal TXC 9HT11 http://txccrystal.com/images/pdf/9ht11.pdf, 2.0x1.2mm^2 package -SMD SMT crystal -0 -2 -2 -Crystal -Crystal_SMD_TXC_9HT11-2Pin_2.0x1.2mm_HandSoldering -SMD Crystal TXC 9HT11 http://txccrystal.com/images/pdf/9ht11.pdf, hand-soldering, 2.0x1.2mm^2 package -SMD SMT crystal hand-soldering -0 -2 -2 -Crystal -Crystal_SMD_TXC_AX_8045-2Pin_8.0x4.5mm -http://www.txccrystal.com/images/pdf/ax-automotive.pdf -SMD SMT crystal -0 -2 -2 -Crystal -Resonator-2Pin_W6.0mm_H3.0mm -Ceramic Resomator/Filter 6.0x3.0mm^2, length*width=6.0x3.0mm^2 package, package length=6.0mm, package width=3.0mm, 2 pins -THT ceramic resonator filter -0 -2 -2 -Crystal -Resonator-2Pin_W7.0mm_H2.5mm -Ceramic Resomator/Filter 7.0x2.5mm^2, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 2 pins -THT ceramic resonator filter -0 -2 -2 -Crystal -Resonator-2Pin_W8.0mm_H3.5mm -Ceramic Resomator/Filter 8.0x3.5mm^2, length*width=8.0x3.5mm^2 package, package length=8.0mm, package width=3.5mm, 2 pins -THT ceramic resonator filter -0 -2 -2 -Crystal -Resonator-2Pin_W10.0mm_H5.0mm -Ceramic Resomator/Filter 10.0x5.0 RedFrequency MG/MT/MX series, http://www.red-frequency.com/download/datenblatt/redfrequency-datenblatt-ir-zta.pdf, length*width=10.0x5.0mm^2 package, package length=10.0mm, package width=5.0mm, 2 pins -THT ceramic resonator filter -0 -2 -2 -Crystal -Resonator-3Pin_W6.0mm_H3.0mm -Ceramic Resomator/Filter 6.0x3.0mm^2, length*width=6.0x3.0mm^2 package, package length=6.0mm, package width=3.0mm, 3 pins -THT ceramic resonator filter -0 -3 -3 -Crystal -Resonator-3Pin_W7.0mm_H2.5mm -Ceramic Resomator/Filter 7.0x2.5mm^2, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins -THT ceramic resonator filter -0 -3 -3 -Crystal -Resonator-3Pin_W8.0mm_H3.5mm -Ceramic Resomator/Filter 8.0x3.5mm^2, length*width=8.0x3.5mm^2 package, package length=8.0mm, package width=3.5mm, 3 pins -THT ceramic resonator filter -0 -3 -3 -Crystal -Resonator-3Pin_W10.0mm_H5.0mm -Ceramic Resomator/Filter 10.0x5.0mm^2 RedFrequency MG/MT/MX series, http://www.red-frequency.com/download/datenblatt/redfrequency-datenblatt-ir-zta.pdf, length*width=10.0x5.0mm^2 package, package length=10.0mm, package width=5.0mm, 3 pins -THT ceramic resonator filter -0 -3 -3 -Crystal -Resonator_SMD-3Pin_7.2x3.0mm -SMD Resomator/Filter 7.2x3.0mm, Murata CSTCC8M00G53-R0; 8MHz resonator, SMD, Farnell (Element 14) #1170435, http://www.farnell.com/datasheets/19296.pdf?_ga=1.247244932.122297557.1475167906, 7.2x3.0mm^2 package -SMD SMT ceramic resonator filter filter -0 -3 -3 -Crystal -Resonator_SMD-3Pin_7.2x3.0mm_HandSoldering -SMD Resomator/Filter 7.2x3.0mm, Murata CSTCC8M00G53-R0; 8MHz resonator, SMD, Farnell (Element 14) #1170435, http://www.farnell.com/datasheets/19296.pdf?_ga=1.247244932.122297557.1475167906, hand-soldering, 7.2x3.0mm^2 package -SMD SMT ceramic resonator filter filter hand-soldering -0 -3 -3 -Crystal -Resonator_SMD_muRata_CDSCB-2Pin_4.5x2.0mm -SMD Resomator/Filter Murata CDSCB, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 4.5x2.0mm^2 package -SMD SMT ceramic resonator filter filter -0 -2 -2 -Crystal -Resonator_SMD_muRata_CDSCB-2Pin_4.5x2.0mm_HandSoldering -SMD Resomator/Filter Murata CDSCB, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 4.5x2.0mm^2 package -SMD SMT ceramic resonator filter filter hand-soldering -0 -2 -2 -Crystal -Resonator_SMD_muRata_CSTxExxV-3Pin_3.0x1.1mm -SMD Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf -SMD SMT ceramic resonator filter -0 -3 -3 -Crystal -Resonator_SMD_muRata_CSTxExxV-3Pin_3.0x1.1mm_HandSoldering -SMD Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf -SMD SMT ceramic resonator filter -0 -3 -3 -Crystal -Resonator_SMD_muRata_SFECV-3Pin_6.9x2.9mm -SMD Resomator/Filter Murata SFECV, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 6.9x2.9mm^2 package -SMD SMT ceramic resonator filter filter -0 -3 -3 -Crystal -Resonator_SMD_muRata_SFECV-3Pin_6.9x2.9mm_HandSoldering -SMD Resomator/Filter Murata SFECV, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 6.9x2.9mm^2 package -SMD SMT ceramic resonator filter filter hand-soldering -0 -3 -3 -Crystal -Resonator_SMD_muRata_SFSKA-3Pin_7.9x3.8mm -SMD Resomator/Filter Murata SFSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 7.9x3.8mm^2 package -SMD SMT ceramic resonator filter filter -0 -3 -3 -Crystal -Resonator_SMD_muRata_SFSKA-3Pin_7.9x3.8mm_HandSoldering -SMD Resomator/Filter Murata SFSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 7.9x3.8mm^2 package -SMD SMT ceramic resonator filter filter hand-soldering -0 -3 -3 -Crystal -Resonator_SMD_muRata_TPSKA-3Pin_7.9x3.8mm -SMD Resomator/Filter Murata TPSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 7.9x3.8mm^2 package -SMD SMT ceramic resonator filter filter -0 -3 -3 -Crystal -Resonator_SMD_muRata_TPSKA-3Pin_7.9x3.8mm_HandSoldering -SMD Resomator/Filter Murata TPSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 7.9x3.8mm^2 package -SMD SMT ceramic resonator filter filter hand-soldering -0 -3 -3 -Crystal -Resonator_muRata_CSTLSxxxG-3Pin_W8.0mm_H3.0mm -Ceramic Resomator/Filter Murata CSTLSxxxG, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/timingdevice/ceralock/p17e.ashx, length*width=8.0x3.0mm^2 package, package length=8.0mm, package width=3.0mm, 3 pins -THT ceramic resonator filter CSTLSxxxG -0 -3 -3 -Crystal -Resonator_muRata_CSTLSxxxX-3Pin_W5.5mm_H3.0mm -Ceramic Resomator/Filter Murata CSTLSxxxX, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/timingdevice/ceralock/p17e.ashx, length*width=5.5x3.0mm^2 package, package length=5.5mm, package width=3.0mm, 3 pins -THT ceramic resonator filter CSTLSxxxX -0 -3 -3 -Crystal -Resonator_muRata_DSN6-3Pin_W7.0mm_H2.5mm -Ceramic Resomator/Filter Murata DSN6, http://cdn-reichelt.de/documents/datenblatt/B400/DSN6NC51H.pdf, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins -THT ceramic resonator filter DSN6 -0 -3 -3 -Crystal -Resonator_muRata_DSS6-3Pin_W7.0mm_H2.5mm -Ceramic Resomator/Filter Murata DSS6, http://cdn-reichelt.de/documents/datenblatt/B400/DSN6NC51H.pdf, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins -THT ceramic resonator filter DSS6 -0 -3 -3 -Diode_SMD -D_0201_0603Metric -Diode SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator -diode -0 -4 -2 -Diode_SMD -D_0402_1005Metric -Diode SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_0603_1608Metric -Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_0603_1608Metric_Castellated -Diode SMD 0603 (1608 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_0603_1608Metric_Pad1.05x0.95mm_HandSolder -Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_0805_2012Metric -Diode SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_0805_2012Metric_Castellated -Diode SMD 0805 (2012 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_0805_2012Metric_Pad1.15x1.40mm_HandSolder -Diode SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_01005_0402Metric -Diode SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator -diode -0 -4 -2 -Diode_SMD -D_1206_3216Metric -Diode SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_1206_3216Metric_Castellated -Diode SMD 1206 (3216 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_1206_3216Metric_Pad1.42x1.75mm_HandSolder -Diode SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_1210_3225Metric -Diode SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_1210_3225Metric_Castellated -Diode SMD 1210 (3225 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_1210_3225Metric_Pad1.42x2.65mm_HandSolder -Diode SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_1806_4516Metric -Diode SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_1806_4516Metric_Castellated -Diode SMD 1806 (4516 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_1806_4516Metric_Pad1.57x1.80mm_HandSolder -Diode SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_1812_4532Metric -Diode SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_1812_4532Metric_Castellated -Diode SMD 1812 (4532 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_1812_4532Metric_Pad1.30x3.40mm_HandSolder -Diode SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_2010_5025Metric -Diode SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_2010_5025Metric_Castellated -Diode SMD 2010 (5025 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_2010_5025Metric_Pad1.52x2.65mm_HandSolder -Diode SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_2114_3652Metric -Diode SMD 2114 (3652 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_2114_3652Metric_Castellated -Diode SMD 2114 (3652 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_2114_3652Metric_Pad1.85x3.75mm_HandSolder -Diode SMD 2114 (3652 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_2512_6332Metric -Diode SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_2512_6332Metric_Castellated -Diode SMD 2512 (6332 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_2512_6332Metric_Pad1.52x3.35mm_HandSolder -Diode SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_2816_7142Metric -Diode SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_2816_7142Metric_Castellated -Diode SMD 2816 (7142 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_2816_7142Metric_Pad3.20x4.45mm_HandSolder -Diode SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_3220_8050Metric -Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -Diode_SMD -D_3220_8050Metric_Castellated -Diode SMD 3220 (8050 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator -diode castellated -0 -2 -2 -Diode_SMD -D_3220_8050Metric_Pad2.65x5.15mm_HandSolder -Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator -diode handsolder -0 -2 -2 -Diode_SMD -D_MELF -Diode, MELF,, -Diode MELF -0 -2 -2 -Diode_SMD -D_MELF-RM10_Universal_Handsoldering -Diode, Universal, MELF, RM10, Handsoldering, SMD, Thruhole, -Diode Universal MELF RM10 Handsoldering SMD Thruhole -0 -2 -2 -Diode_SMD -D_MELF_Handsoldering -Diode MELF Handsoldering -Diode MELF Handsoldering -0 -2 -2 -Diode_SMD -D_MicroMELF -Diode, MicroMELF, Reflow Soldering, http://www.vishay.com/docs/85597/bzm55.pdf -MicroMELF Diode -0 -2 -2 -Diode_SMD -D_MicroMELF_Handsoldering -Diode, MicroMELF, Hand Soldering, http://www.vishay.com/docs/85597/bzm55.pdf -MicroMELF Diode -0 -2 -2 -Diode_SMD -D_MiniMELF -Diode Mini-MELF -Diode Mini-MELF -0 -2 -2 -Diode_SMD -D_MiniMELF_Handsoldering -Diode Mini-MELF Handsoldering -Diode Mini-MELF Handsoldering -0 -2 -2 -Diode_SMD -D_PowerDI-5 -PowerDI,Diode,Vishay,https://www.diodes.com/assets/Package-Files/PowerDI5.pdf -PowerDI diode vishay -0 -3 -2 -Diode_SMD -D_PowerDI-123 -http://www.diodes.com/_files/datasheets/ds30497.pdf -PowerDI diode vishay -0 -2 -2 -Diode_SMD -D_Powermite2_AK -Microsemi Powermite 2 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5341) -PowerMite2 -0 -2 -2 -Diode_SMD -D_Powermite2_KA -Microsemi Powermite 2 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5341) -PowerMite2 -0 -2 -2 -Diode_SMD -D_Powermite3 -Microsemi Powermite 3 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5340) -PowerMite3 -0 -3 -3 -Diode_SMD -D_Powermite_AK -Microsemi Powermite SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5339, https://www.onsemi.com/pub/Collateral/457-04.PDF) -Powermite -0 -2 -2 -Diode_SMD -D_Powermite_KA -Microsemi Powermite SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5339, https://www.onsemi.com/pub/Collateral/457-04.PDF) -Powermite -0 -2 -2 -Diode_SMD -D_QFN_3.3x3.3mm_P0.65mm -QFN, diode, 3.3x3.3x1mm (https://www.wolfspeed.com/media/downloads/846/C3D1P7060Q.pdf) -diode qfn 3.3 -0 -3 -2 -Diode_SMD -D_SC-80 -JEITA SC-80 -SC-80 -0 -2 -2 -Diode_SMD -D_SC-80_HandSoldering -JEITA SC-80 -SC-80 -0 -2 -2 -Diode_SMD -D_SMA -Diode SMA (DO-214AC) -Diode SMA (DO-214AC) -0 -2 -2 -Diode_SMD -D_SMA-SMB_Universal_Handsoldering -Diode, Universal, SMA (DO-214AC) or SMB (DO-214AA), Handsoldering, -Diode Universal SMA (DO-214AC) SMB (DO-214AA) Handsoldering -0 -2 -2 -Diode_SMD -D_SMA_Handsoldering -Diode SMA (DO-214AC) Handsoldering -Diode SMA (DO-214AC) Handsoldering -0 -2 -2 -Diode_SMD -D_SMB -Diode SMB (DO-214AA) -Diode SMB (DO-214AA) -0 -2 -2 -Diode_SMD -D_SMB-SMC_Universal_Handsoldering -Diode, Universal, SMB(DO-214AA) or SMC (DO-214AB), Handsoldering, -Diode Universal SMB(DO-214AA) SMC (DO-214AB) Handsoldering -0 -2 -2 -Diode_SMD -D_SMB_Handsoldering -Diode SMB (DO-214AA) Handsoldering -Diode SMB (DO-214AA) Handsoldering -0 -2 -2 -Diode_SMD -D_SMB_Modified -Diode SMB (DO-214AA) Modified (http://www.littelfuse.com/~/media/electronics/datasheets/sidactors/littelfuse_sidactor_battrax_positive_negative_modified_do_214_datasheet.pdf.pdf) -Diode SMB (DO-214AA) -0 -3 -3 -Diode_SMD -D_SMC -Diode SMC (DO-214AB) -Diode SMC (DO-214AB) -0 -2 -2 -Diode_SMD -D_SMC-RM10_Universal_Handsoldering -Diode, Universal, SMC (DO-214AB), RM10, Handsoldering, SMD, Thruhole -Diode Universal SMC (DO-214AB) RM10 Handsoldering SMD Thruhole -0 -2 -2 -Diode_SMD -D_SMC_Handsoldering -Diode SMC (DO-214AB) Handsoldering -Diode SMC (DO-214AB) Handsoldering -0 -2 -2 -Diode_SMD -D_SMF -Diode SMF (DO-219AB), http://www.vishay.com/docs/95572/smf_do-219ab.pdf -Diode SMF (DO-214AB) -0 -2 -2 -Diode_SMD -D_SOD-110 -SOD-110 -SOD-110 -0 -2 -2 -Diode_SMD -D_SOD-123 -SOD-123 -SOD-123 -0 -2 -2 -Diode_SMD -D_SOD-123F -D_SOD-123F -D_SOD-123F -0 -2 -2 -Diode_SMD -D_SOD-128 -D_SOD-128 (CFP5 SlimSMAW), https://assets.nexperia.com/documents/outline-drawing/SOD128.pdf -D_SOD-128 -0 -2 -2 -Diode_SMD -D_SOD-323 -SOD-323 -SOD-323 -0 -2 -2 -Diode_SMD -D_SOD-323F -SOD-323F http://www.nxp.com/documents/outline_drawing/SOD323F.pdf -SOD-323F -0 -2 -2 -Diode_SMD -D_SOD-323_HandSoldering -SOD-323 -SOD-323 -0 -2 -2 -Diode_SMD -D_SOD-523 -http://www.diodes.com/datasheets/ap02001.pdf p.144 -Diode SOD523 -0 -2 -2 -Diode_SMD -D_SOT-23_ANK -SOT-23, Single Diode -SOT-23 -0 -3 -2 -Diode_SMD -D_SOT-23_NKA -SOT-23, Single Diode -SOT-23 -0 -3 -2 -Diode_SMD -D_TUMD2 -ROHM - TUMD2 -TUMD2 -0 -2 -2 -Diode_SMD -Diode_Bridge_Bourns_CD-DF4xxS -8.1x10.5mm, 4A, single phase bridge rectifier, https://www.bourns.com/docs/Product-Datasheets/CD-DF4xxSL.pdf -Surface Mount Bridge Rectifier Diode -0 -4 -4 -Diode_SMD -Diode_Bridge_Diotec_ABS -SMD diode bridge ABS (Diotec), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/abs2.pdf -ABS MBLS -0 -4 -4 -Diode_SMD -Diode_Bridge_Diotec_MicroDil_3.0x3.0x1.8mm -SMD package Diotec Diotec MicroDil, body 3.0x3.0x1.8mm (e.g. diode bridge), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/mys40.pdf -Diotec MicroDil diode bridge -0 -4 -4 -Diode_SMD -Diode_Bridge_Diotec_SO-DIL-Slim -SMD diode bridge Diotec SO-DIL Slim, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40fs.pdf -DFS SO-DIL Slim -0 -4 -4 -Diode_SMD -Diode_Bridge_Vishay_DFS -SMD diode bridge DFS, see http://www.vishay.com/docs/88854/padlayouts.pdf -DFS -0 -4 -4 -Diode_SMD -Diode_Bridge_Vishay_DFSFlat -SMD diode bridge Low Profile DFS "Flat", see http://www.vishay.com/docs/88874/dfl15005.pdf -DFS -0 -4 -4 -Diode_SMD -Diode_Bridge_Vishay_MBLS -SMD diode bridge MBLS, see http://www.vishay.com/docs/89959/mbl104s.pdf http://www.vishay.com/docs/88854/padlayouts.pdf -DFS -0 -4 -4 -Diode_SMD -Littelfuse_PolyZen-LS -http://m.littelfuse.com/~/media/electronics/datasheets/polyzen_devices/littelfuse_polyzen_standard_polyzen_catalog_datasheet.pdf.pdf -Diode Polymer Protected Zener Diode Littelfuse LS -0 -3 -3 -Diode_THT -D_5KPW_P7.62mm_Vertical_AnodeUp -Diode, 5KPW series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KPW series Axial Vertical pin pitch 7.62mm length 9mm diameter 8mm -0 -2 -2 -Diode_THT -D_5KPW_P7.62mm_Vertical_KathodeUp -Diode, 5KPW series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KPW series Axial Vertical pin pitch 7.62mm length 9mm diameter 8mm -0 -2 -2 -Diode_THT -D_5KPW_P12.70mm_Horizontal -Diode, 5KPW series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KPW series Axial Horizontal pin pitch 12.7mm length 9mm diameter 8mm -0 -2 -2 -Diode_THT -D_5KP_P7.62mm_Vertical_AnodeUp -Diode, 5KP series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KP series Axial Vertical pin pitch 7.62mm length 7.62mm diameter 9.53mm -0 -2 -2 -Diode_THT -D_5KP_P7.62mm_Vertical_KathodeUp -Diode, 5KP series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KP series Axial Vertical pin pitch 7.62mm length 7.62mm diameter 9.53mm -0 -2 -2 -Diode_THT -D_5KP_P10.16mm_Horizontal -Diode, 5KP series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KP series Axial Horizontal pin pitch 10.16mm length 7.62mm diameter 9.53mm -0 -2 -2 -Diode_THT -D_5KP_P12.70mm_Horizontal -Diode, 5KP series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5KP series Axial Horizontal pin pitch 12.7mm length 7.62mm diameter 9.53mm -0 -2 -2 -Diode_THT -D_5W_P5.08mm_Vertical_AnodeUp -Diode, 5W series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5W series Axial Vertical pin pitch 5.08mm length 8.9mm diameter 3.7mm -0 -2 -2 -Diode_THT -D_5W_P5.08mm_Vertical_KathodeUp -Diode, 5W series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5W series Axial Vertical pin pitch 5.08mm length 8.9mm diameter 3.7mm -0 -2 -2 -Diode_THT -D_5W_P10.16mm_Horizontal -Diode, 5W series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5W series Axial Horizontal pin pitch 10.16mm length 8.9mm diameter 3.7mm -0 -2 -2 -Diode_THT -D_5W_P12.70mm_Horizontal -Diode, 5W series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif -Diode 5W series Axial Horizontal pin pitch 12.7mm length 8.9mm diameter 3.7mm -0 -2 -2 -Diode_THT -D_A-405_P2.54mm_Vertical_AnodeUp -Diode, A-405 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_A-405_P2.54mm_Vertical_KathodeUp -Diode, A-405 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_A-405_P5.08mm_Vertical_AnodeUp -Diode, A-405 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_A-405_P5.08mm_Vertical_KathodeUp -Diode, A-405 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_A-405_P7.62mm_Horizontal -Diode, A-405 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_A-405_P10.16mm_Horizontal -Diode, A-405 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Horizontal pin pitch 10.16mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_A-405_P12.70mm_Horizontal -Diode, A-405 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf -Diode A-405 series Axial Horizontal pin pitch 12.7mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-15_P2.54mm_Vertical_AnodeUp -Diode, DO-15 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Vertical pin pitch 2.54mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P2.54mm_Vertical_KathodeUp -Diode, DO-15 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Vertical pin pitch 2.54mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P3.81mm_Vertical_AnodeUp -Diode, DO-15 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Vertical pin pitch 3.81mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P3.81mm_Vertical_KathodeUp -Diode, DO-15 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Vertical pin pitch 3.81mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P5.08mm_Vertical_AnodeUp -Diode, DO-15 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Vertical pin pitch 5.08mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P5.08mm_Vertical_KathodeUp -Diode, DO-15 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Vertical pin pitch 5.08mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P10.16mm_Horizontal -Diode, DO-15 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Horizontal pin pitch 10.16mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P12.70mm_Horizontal -Diode, DO-15 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Horizontal pin pitch 12.7mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-15_P15.24mm_Horizontal -Diode, DO-15 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf -Diode DO-15 series Axial Horizontal pin pitch 15.24mm length 7.6mm diameter 3.6mm -0 -2 -2 -Diode_THT -D_DO-27_P5.08mm_Vertical_AnodeUp -Diode, DO-27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg -Diode DO-27 series Axial Vertical pin pitch 5.08mm length 9.52mm diameter 5.33mm -0 -2 -2 -Diode_THT -D_DO-27_P5.08mm_Vertical_KathodeUp -Diode, DO-27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg -Diode DO-27 series Axial Vertical pin pitch 5.08mm length 9.52mm diameter 5.33mm -0 -2 -2 -Diode_THT -D_DO-27_P12.70mm_Horizontal -Diode, DO-27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg -Diode DO-27 series Axial Horizontal pin pitch 12.7mm length 9.52mm diameter 5.33mm -0 -2 -2 -Diode_THT -D_DO-27_P15.24mm_Horizontal -Diode, DO-27 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg -Diode DO-27 series Axial Horizontal pin pitch 15.24mm length 9.52mm diameter 5.33mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P2.54mm_Vertical_AnodeUp -Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Vertical pin pitch 2.54mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P2.54mm_Vertical_KathodeUp -Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Vertical pin pitch 2.54mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P5.08mm_Vertical_AnodeUp -Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Vertical pin pitch 5.08mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P5.08mm_Vertical_KathodeUp -Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Vertical pin pitch 5.08mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P7.62mm_Horizontal -Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Horizontal pin pitch 7.62mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P10.16mm_Horizontal -Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Horizontal pin pitch 10.16mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-34_SOD68_P12.70mm_Horizontal -Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf -Diode DO-34_SOD68 series Axial Horizontal pin pitch 12.7mm length 3.04mm diameter 1.6mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P2.54mm_Vertical_AnodeUp -Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Vertical pin pitch 2.54mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P2.54mm_Vertical_KathodeUp -Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Vertical pin pitch 2.54mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P3.81mm_Vertical_AnodeUp -Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Vertical pin pitch 3.81mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P3.81mm_Vertical_KathodeUp -Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Vertical pin pitch 3.81mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P5.08mm_Vertical_AnodeUp -Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Vertical pin pitch 5.08mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P5.08mm_Vertical_KathodeUp -Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Vertical pin pitch 5.08mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P7.62mm_Horizontal -Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P10.16mm_Horizontal -Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-35_SOD27_P12.70mm_Horizontal -Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf -Diode DO-35_SOD27 series Axial Horizontal pin pitch 12.7mm length 4mm diameter 2mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P2.54mm_Vertical_AnodeUp -Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P2.54mm_Vertical_KathodeUp -Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P3.81mm_Vertical_AnodeUp -Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=5.2*2.7mm^2, , https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf -Diode DO-41_SOD81 series Axial Vertical pin pitch 3.81mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P3.81mm_Vertical_KathodeUp -Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=5.2*2.7mm^2, , https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf -Diode DO-41_SOD81 series Axial Vertical pin pitch 3.81mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P5.08mm_Vertical_AnodeUp -Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P5.08mm_Vertical_KathodeUp -Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P7.62mm_Horizontal -Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P10.16mm_Horizontal -Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Horizontal pin pitch 10.16mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-41_SOD81_P12.70mm_Horizontal -Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf -Diode DO-41_SOD81 series Axial Horizontal pin pitch 12.7mm length 5.2mm diameter 2.7mm -0 -2 -2 -Diode_THT -D_DO-201AD_P3.81mm_Vertical_AnodeUp -Diode, DO-201AD series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf -Diode DO-201AD series Axial Vertical pin pitch 3.81mm length 9.5mm diameter 5.2mm -0 -2 -2 -Diode_THT -D_DO-201AD_P3.81mm_Vertical_KathodeUp -Diode, DO-201AD series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf -Diode DO-201AD series Axial Vertical pin pitch 3.81mm length 9.5mm diameter 5.2mm -0 -2 -2 -Diode_THT -D_DO-201AD_P5.08mm_Vertical_AnodeUp -Diode, DO-201AD series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf -Diode DO-201AD series Axial Vertical pin pitch 5.08mm length 9.5mm diameter 5.2mm -0 -2 -2 -Diode_THT -D_DO-201AD_P5.08mm_Vertical_KathodeUp -Diode, DO-201AD series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf -Diode DO-201AD series Axial Vertical pin pitch 5.08mm length 9.5mm diameter 5.2mm -0 -2 -2 -Diode_THT -D_DO-201AD_P12.70mm_Horizontal -Diode, DO-201AD series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf -Diode DO-201AD series Axial Horizontal pin pitch 12.7mm length 9.5mm diameter 5.2mm -0 -2 -2 -Diode_THT -D_DO-201AD_P15.24mm_Horizontal -Diode, DO-201AD series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf -Diode DO-201AD series Axial Horizontal pin pitch 15.24mm length 9.5mm diameter 5.2mm -0 -2 -2 -Diode_THT -D_DO-201AE_P3.81mm_Vertical_AnodeUp -Diode, DO-201AE series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf -Diode DO-201AE series Axial Vertical pin pitch 3.81mm length 9mm diameter 5.3mm -0 -2 -2 -Diode_THT -D_DO-201AE_P3.81mm_Vertical_KathodeUp -Diode, DO-201AE series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf -Diode DO-201AE series Axial Vertical pin pitch 3.81mm length 9mm diameter 5.3mm -0 -2 -2 -Diode_THT -D_DO-201AE_P5.08mm_Vertical_AnodeUp -Diode, DO-201AE series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf -Diode DO-201AE series Axial Vertical pin pitch 5.08mm length 9mm diameter 5.3mm -0 -2 -2 -Diode_THT -D_DO-201AE_P5.08mm_Vertical_KathodeUp -Diode, DO-201AE series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf -Diode DO-201AE series Axial Vertical pin pitch 5.08mm length 9mm diameter 5.3mm -0 -2 -2 -Diode_THT -D_DO-201AE_P12.70mm_Horizontal -Diode, DO-201AE series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf -Diode DO-201AE series Axial Horizontal pin pitch 12.7mm length 9mm diameter 5.3mm -0 -2 -2 -Diode_THT -D_DO-201AE_P15.24mm_Horizontal -Diode, DO-201AE series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf -Diode DO-201AE series Axial Horizontal pin pitch 15.24mm length 9mm diameter 5.3mm -0 -2 -2 -Diode_THT -D_DO-201_P3.81mm_Vertical_AnodeUp -Diode, DO-201 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf -Diode DO-201 series Axial Vertical pin pitch 3.81mm length 9.53mm diameter 5.21mm -0 -2 -2 -Diode_THT -D_DO-201_P3.81mm_Vertical_KathodeUp -Diode, DO-201 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf -Diode DO-201 series Axial Vertical pin pitch 3.81mm length 9.53mm diameter 5.21mm -0 -2 -2 -Diode_THT -D_DO-201_P5.08mm_Vertical_AnodeUp -Diode, DO-201 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf -Diode DO-201 series Axial Vertical pin pitch 5.08mm length 9.53mm diameter 5.21mm -0 -2 -2 -Diode_THT -D_DO-201_P5.08mm_Vertical_KathodeUp -Diode, DO-201 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf -Diode DO-201 series Axial Vertical pin pitch 5.08mm length 9.53mm diameter 5.21mm -0 -2 -2 -Diode_THT -D_DO-201_P12.70mm_Horizontal -Diode, DO-201 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf -Diode DO-201 series Axial Horizontal pin pitch 12.7mm length 9.53mm diameter 5.21mm -0 -2 -2 -Diode_THT -D_DO-201_P15.24mm_Horizontal -Diode, DO-201 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf -Diode DO-201 series Axial Horizontal pin pitch 15.24mm length 9.53mm diameter 5.21mm -0 -2 -2 -Diode_THT -D_P600_R-6_P7.62mm_Vertical_AnodeUp -Diode, P600_R-6 series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf -Diode P600_R-6 series Axial Vertical pin pitch 7.62mm length 9.1mm diameter 9.1mm -0 -2 -2 -Diode_THT -D_P600_R-6_P7.62mm_Vertical_KathodeUp -Diode, P600_R-6 series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf -Diode P600_R-6 series Axial Vertical pin pitch 7.62mm length 9.1mm diameter 9.1mm -0 -2 -2 -Diode_THT -D_P600_R-6_P12.70mm_Horizontal -Diode, P600_R-6 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf -Diode P600_R-6 series Axial Horizontal pin pitch 12.7mm length 9.1mm diameter 9.1mm -0 -2 -2 -Diode_THT -D_P600_R-6_P20.00mm_Horizontal -Diode, P600_R-6 series, Axial, Horizontal, pin pitch=20mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf -Diode P600_R-6 series Axial Horizontal pin pitch 20mm length 9.1mm diameter 9.1mm -0 -2 -2 -Diode_THT -D_T-1_P2.54mm_Vertical_AnodeUp -Diode, T-1 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf -Diode T-1 series Axial Vertical pin pitch 2.54mm length 3.2mm diameter 2.6mm -0 -2 -2 -Diode_THT -D_T-1_P2.54mm_Vertical_KathodeUp -Diode, T-1 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf -Diode T-1 series Axial Vertical pin pitch 2.54mm length 3.2mm diameter 2.6mm -0 -2 -2 -Diode_THT -D_T-1_P5.08mm_Horizontal -Diode, T-1 series, Axial, Horizontal, pin pitch=5.08mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf -Diode T-1 series Axial Horizontal pin pitch 5.08mm length 3.2mm diameter 2.6mm -0 -2 -2 -Diode_THT -D_T-1_P10.16mm_Horizontal -Diode, T-1 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf -Diode T-1 series Axial Horizontal pin pitch 10.16mm length 3.2mm diameter 2.6mm -0 -2 -2 -Diode_THT -D_T-1_P12.70mm_Horizontal -Diode, T-1 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf -Diode T-1 series Axial Horizontal pin pitch 12.7mm length 3.2mm diameter 2.6mm -0 -2 -2 -Diode_THT -Diode_Bridge_15.1x15.1x6.3mm_P10.9mm -Single phase bridge rectifier case 15.1x15.1mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf -Diode Bridge PB10xxS -0 -4 -4 -Diode_THT -Diode_Bridge_15.2x15.2x6.3mm_P10.9mm -Single phase bridge rectifier case 15.2x15.2mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc600.pdf -Diode Bridge KBPC6xx -0 -4 -4 -Diode_THT -Diode_Bridge_15.7x15.7x6.3mm_P10.8mm -Single phase bridge rectifier case 15.7x15.7 -Diode Bridge -0 -4 -4 -Diode_THT -Diode_Bridge_16.7x16.7x6.3mm_P10.8mm -Single phase bridge rectifier case 16.7x16.7 -Diode Bridge -0 -4 -4 -Diode_THT -Diode_Bridge_19.0x3.5x10.0mm_P5.0mm -Vishay GBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88606/g3sba20.pdf -Vishay GBU rectifier diode bridge -0 -4 -4 -Diode_THT -Diode_Bridge_19.0x19.0x6.8mm_P12.7mm -Single phase bridge rectifier case 19x19mm, pitch 12.7mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf -Diode Bridge PB10xx -0 -4 -4 -Diode_THT -Diode_Bridge_28.6x28.6x7.3mm_P18.0mm_P11.6mm -Single phase bridge rectifier case 28.6x28.6mm, pitch 18.0mm & 11.6mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc1500fw.pdf -Diode Bridge KBPCxxxxWP -0 -4 -4 -Diode_THT -Diode_Bridge_32.0x5.6x17.0mm_P10.0mm_P7.5mm -Diotec 32x5.6x17mm rectifier package, 7.5mm/10mm pitch, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40c3700.pdf -Diotec rectifier diode bridge -0 -4 -4 -Diode_THT -Diode_Bridge_DIP-4_W5.08mm_P2.54mm -4-lead dip package for diode bridges, row spacing 5.08mm, pin-spacing 2.54mm, see http://www.vishay.com/docs/88898/b2m.pdf -DIL DIP PDIP 5.08mm 2.54 -0 -4 -4 -Diode_THT -Diode_Bridge_DIP-4_W7.62mm_P5.08mm -4-lead dip package for diode bridges, row spacing 7.62 mm (300 mils), see http://cdn-reichelt.de/documents/datenblatt/A400/HDBL101G_20SERIES-TSC.pdf -DIL DIP PDIP 5.08mm 7.62mm 300mil -0 -4 -4 -Diode_THT -Diode_Bridge_Round_D8.9mm -4-lead round diode bridge package, diameter 8.9mm, pin pitch 5.08mm, see http://cdn-reichelt.de/documents/datenblatt/A400/W005M-W10M_SEP.PDF -diode bridge 8.9mm 8.85mm WOB pitch 5.08mm -0 -4 -4 -Diode_THT -Diode_Bridge_Round_D9.0mm -4-lead round diode bridge package, diameter 9.0mm, pin pitch 5.0mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40r.pdf -diode bridge 9.0mm 8.85mm WOB pitch 5.0mm -0 -4 -4 -Diode_THT -Diode_Bridge_Round_D9.8mm -4-lead round diode bridge package, diameter 9.8mm, pin pitch 5.08mm, see http://www.vishay.com/docs/88769/woo5g.pdf -diode bridge 9.8mm WOG pitch 5.08mm -0 -4 -4 -Diode_THT -Diode_Bridge_Vishay_GBL -Vishay GBL rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88609/gbl005.pdf -Vishay GBL rectifier diode bridge -0 -4 -4 -Diode_THT -Diode_Bridge_Vishay_GBU -Vishay GBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88606/g3sba20.pdf -Vishay GBU rectifier diode bridge -0 -4 -4 -Diode_THT -Diode_Bridge_Vishay_KBL -Vishay KBL rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88655/kbl005.pdf -Vishay KBL rectifier diode bridge -0 -4 -4 -Diode_THT -Diode_Bridge_Vishay_KBPC1 -Single phase bridge rectifier case KBPC1, see http://www.vishay.com/docs/93585/vs-kbpc1series.pdf -Diode Bridge -0 -4 -4 -Diode_THT -Diode_Bridge_Vishay_KBPC6 -Single phase bridge rectifier case KBPC6, see http://www.vishay.com/docs/93585/vs-kbpc1series.pdf -Diode Bridge -0 -4 -4 -Diode_THT -Diode_Bridge_Vishay_KBU -Vishay KBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88656/kbu4.pdf -Vishay KBU rectifier diode bridge -0 -4 -4 -Display -AG12864E -STN/FSTN LCD 128x64 dot https://www.digchip.com/datasheets/parts/datasheet/1121/AG-12864E-pdf.php -AG12864E Graphics Display 128x64 Ampire -0 -24 -20 -Display -Adafruit_SSD1306 -Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI https://learn.adafruit.com/monochrome-oled-breakouts/downloads -Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI -0 -8 -8 -Display -Adafruit_SSD1306_No_Mounting_Holes -Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI https://learn.adafruit.com/monochrome-oled-breakouts/downloads -Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI -0 -8 -8 -Display -CR2013-MI2120 -CR2013-MI2120 ILI9341 LCD Breakout http://pan.baidu.com/s/11Y990 -CR2013-MI2120 ILI9341 LCD Breakout -0 -18 -14 -Display -EA-eDIP128B-XXX -LCD-graphical display with LED backlight 128x64 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip128-6e.pdf -LCD-graphical display with LED backlight 128x64 RS-232 I2C or SPI -0 -32 -32 -Display -EA_DOGS104X-A -LCD 4x10 character 3.3V VDD I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/doma/dogs104e.pdf -LCD 4x10 character 3.3V VDD I2C or SPI -0 -14 -14 -Display -EA_DOGXL160-7 -Grapchical,Display,LCD,160x104 http://www.lcd-module.com/eng/pdf/grafik/dogxl160-7e.pdf -EA_DOGXL160-7 -0 -22 -22 -Display -EA_DOGXL160-7_Backlight -Grapchical,Display,LCD,160x104 http://www.lcd-module.com/eng/pdf/grafik/dogxl160-7e.pdf -EA_DOGXL160-7_Backlight -0 -22 -22 -Display -EA_T123X-I2C -http://www.lcd-module.de/pdf/doma/t123-i2c.pdf -3 Line 12 character wide alpha numeric LCD -0 -6 -6 -Display -EA_eDIP160-XXX -LCD-graphical display with LED backlight 160x104 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip160-7e.pdf -LCD-graphical display with LED backlight 160x104 RS-232 I2C or SPI -0 -40 -40 -Display -EA_eDIP240-XXX -LCD graphical display LED backlight 240x128 http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip240-7e.pdf -LCD graphical display LED backlight 240x128 -0 -40 -40 -Display -EA_eDIP320X-XXX -LCD display 320x340 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip320-8e.pdf -LCD display 320x340 RS-232 I2C or SPI -0 -48 -48 -Display -EA_eDIPTFT32-XXX -TFT-graphic display 320x240 16 bit colour with led backlight http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft32-ae.pdf -TFT-graphic display 320x240 16 bit colour with led backlight -0 -40 -40 -Display -EA_eDIPTFT43-ATC -http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft43-ae.pdf -TFT graphical display 480x272 16-bit colour with LED backlight -0 -40 -40 -Display -EA_eDIPTFT43-XXX -TFT graphical display 480x272 16-bit colour with LED backlight http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft43-ae.pdf -TFT graphical display 480x272 16-bit colour with LED backlight -0 -40 -40 -Display -EA_eDIPTFT57-XXX -http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft57-ae.pdf -TFT-graphic display 640x480 16 bit colour -0 -48 -48 -Display -EA_eDIPTFT70-ATC -TFT-graphical display 800x480 16-bit colours with capacitive touch panel http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft70-ae.pdf -TFT-graphical display 800x480 16-bit colours with capacitive touch panel -0 -48 -48 -Display -EA_eDIPTFT70-XXX -TFT-graphical display 800x480 16-bit colours http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft70-ae.pdf -TFT-graphical display 800x480 16-bit colours and touch display -0 -48 -48 -Display -HDSM-441B_HDSM-443B -2 Digit 7 segemnt blue LED, right hand decimal, https://docs.broadcom.com/docs/AV02-1589EN -2 Digit 7 segment blue LED -0 -10 -10 -Display -HDSM-541B_HDSM-543B -2 digit 7 segement blue LED with right hand decimal, https://docs.broadcom.com/docs/AV02-1588EN -2 digit 7 segement blue LED with right hand decimal -0 -10 -10 -Display -HDSP-48xx -10-Element Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Bar Graph Array -0 -20 -20 -Display -HDSP-4830 -10-Element Red Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Red Bar Graph Array -0 -20 -20 -Display -HDSP-4832 -10-Element Red Yellow Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Red Yellow Green Bar Graph Array -0 -20 -20 -Display -HDSP-4836 -10-Element Red Yellow Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Red Yellow Green Bar Graph Array -0 -20 -20 -Display -HDSP-4840 -10-Element Yellow Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Yellow Bar Graph Array -0 -20 -20 -Display -HDSP-4850 -10-Element Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Green Bar Graph Array -0 -20 -20 -Display -HLCP-J100 -10-Element Red Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN -10-Element Red Bar Graph Array -0 -20 -20 -Display -HY1602E -http://www.icbank.com/data/ICBShop/board/HY1602E.pdf -LCD 16x2 Alphanumeric 16pin -0 -20 -16 -Display -LCD-016N002L -16 x 2 Character LCD, http://www.vishay.com/product?docid=37299 -LCD-016N002L 16 x 2 Character LCD -0 -24 -20 -Display -LM16255 -LCD LM16255 16x2 character http://www.datasheetlib.com/datasheet/259542/lm16255_sharp-electronics.html -LCD 12x2 -0 -14 -14 -Display -NHD-0420H1Z -NHD-0420H1Z LCD http://www.newhavendisplay.com/specs/NHD-0420H1Z-FSW-GBW-33V3.pdf -NHD-0420H1Z LCD -0 -16 -16 -Display -RC1602A -http://www.raystar-optronics.com/down.php?ProID=18 -LCD 16x2 Alphanumeric 16pin -0 -22 -18 -Display -WC1602A -LCD 16x2 http://www.wincomlcd.com/pdf/WC1602A-SFYLYHTC06.pdf -LCD 16x2 Alphanumeric 16pin -0 -20 -16 -Display_7Segment -7SEGMENT-LED__HDSM531_HDSM533_SMD -7-Segment Display, HDSM53x, https://docs.broadcom.com/docs/AV02-0713EN -7segment LED HDSM531 HDSM533 -0 -10 -10 -Display_7Segment -7SegmentLED_LTS6760_LTS6780 -7-Segment Display, LTS67x0, http://optoelectronics.liteon.com/upload/download/DS30-2001-355/S6760jd.pdf -7Segment LED LTS6760 LTS6780 -0 -10 -10 -Display_7Segment -AD-121F2 -Single Digit 7-segment RGB LED Display, 1-inch digit height, common anode, http://usasyck.com/products/AD-121F2_cat_e.pdf -RGB LED digit -0 -22 -22 -Display_7Segment -AFF_2x7SEG-DIGIT_10mm -Afficheur 7 segments 10mm DIGIT -AFFICHEUR -0 -16 -16 -Display_7Segment -CA56-12CGKWA -4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12CGKWA(Ver.9A).pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CA56-12EWA -4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-12EWA.pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CA56-12SEKWA -4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SEKWA(Ver.7A).pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CA56-12SRWA -4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-12SRWA.pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CA56-12SURKWA -4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SURKWA(Ver.8A).pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CA56-12SYKWA -4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SYKWA(Ver.6A).pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CC56-12GWA -4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-11GWA.pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -CC56-12YWA -4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CC56-12YWA.pdf -4 digit 7 segment green LED -0 -12 -12 -Display_7Segment -DA04-11CGKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11CGKWA(Ver.6A).pdf -Dubble digit green 7 segment LED display -0 -16 -16 -Display_7Segment -DA04-11SEKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SEKWA(Ver.9A).pdf -Dubble digit super bright orange 7 segment LED display -0 -16 -16 -Display_7Segment -DA04-11SURKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SURKWA(Ver.10A).pdf -Dubble digit hyper red 7 segment LED display -0 -16 -16 -Display_7Segment -DA04-11SYKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SYKWA(Ver.6A).pdf -Dubble digit super bright yellow 7 segment LED display -0 -16 -16 -Display_7Segment -DA56-11CGKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11CGKWA(Ver.16A).pdf -Double digit seven segment green LED display -0 -18 -18 -Display_7Segment -DA56-11SEKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SEKWA(Ver.9A).pdf -Double digit seven segment super bright orange LED display -0 -18 -18 -Display_7Segment -DA56-11SURKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SURKWA(Ver.11A).pdf -Double digit seven segment hyper red LED display -0 -18 -18 -Display_7Segment -DA56-11SYKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SYKWA(Ver.11A).pdf -Double digit seven segment super bright yellow LED display -0 -18 -18 -Display_7Segment -DE113-XX-XX -http://www.display-elektronik.de/filter/DE113-RS-20_635.pdf -3 1/5 digit LOW BAT + 7-Segment LCD -0 -40 -40 -Display_7Segment -DE114-RS-20 -http://www.display-elektronik.de/filter/DE113-RS-20_635.pdf -3 1/5 digit reflective LCD LOW-BAT + 7-Segment -0 -40 -40 -Display_7Segment -DE122-XX-XX -http://www.display-elektronik.de/filter/DE122-RS-20_635.pdf -6 digit 7 segment LCD -0 -50 -50 -Display_7Segment -DE170-XX-XX -http://www.display-elektronik.de/filter/DE170-RS-20_75.pdf -3 1/5 digit reflective arrow bat + 7 segment LCD -0 -40 -40 -Display_7Segment -ELD_426XXXX -http://www.everlight.com/file/ProductFile/D426SYGWA-S530-E2.pdf -Double digit 7 segment brilliant yellow green LED -0 -10 -10 -Display_7Segment -HDSP-7401 -One digit 7 segment yellow, https://docs.broadcom.com/docs/AV02-2553EN -One digit 7 segment yellow -0 -10 -10 -Display_7Segment -HDSP-7507 -+-1 overflow 7 segment high efficiency red, https://docs.broadcom.com/docs/AV02-2553EN -+-1 overflow 7 segment high efficiency red -0 -10 -10 -Display_7Segment -HDSP-7801 -One digit 7 segment green, https://docs.broadcom.com/docs/AV02-2553EN -One digit 7 segment green -0 -10 -10 -Display_7Segment -HDSP-7807 -+-1 overflow 7 segment green, https://docs.broadcom.com/docs/AV02-2553EN -+-1 overflow 7 segment green -0 -10 -10 -Display_7Segment -HDSP-A151 -One digit 7 segment red, https://docs.broadcom.com/docs/AV02-2553EN -One digit 7 segment high efficiency red -0 -10 -10 -Display_7Segment -HDSP-A401 -One digit 7 segment orange, common anode, https://docs.broadcom.com/docs/AV02-2553EN -One digit 7 segment orange common anode -0 -10 -10 -Display_7Segment -KCSC02-105 -http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-105(Ver.9A).pdf -Single digit 7 segement hyper red LED -0 -10 -10 -Display_7Segment -KCSC02-106 -http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-106(Ver.10A).pdf -Single digit 7 segement super bright orange LED -0 -10 -10 -Display_7Segment -KCSC02-107 -http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-107(Ver.9A).pdf -Single digit 7 segement super bright yellow LED -0 -10 -10 -Display_7Segment -KCSC02-123 -http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-123(Ver.10A).pdf -Single digit 7 segement super bright yellow LED -0 -10 -10 -Display_7Segment -KCSC02-136 -http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-136(Ver.6B).pdf -Single digit 7 segement super bright yellow LED -0 -10 -10 -Display_7Segment -MAN71A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment red LED with right dot -0 -14 -14 -Display_7Segment -MAN72A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment red LED with left dot -0 -14 -14 -Display_7Segment -MAN73A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -Overflow +- 1 red LED -0 -14 -14 -Display_7Segment -MAN3410A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment green LED with dot -0 -14 -14 -Display_7Segment -MAN3420A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment green LED with left dot -0 -14 -14 -Display_7Segment -MAN3610A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment orange LED with right dot -0 -14 -14 -Display_7Segment -MAN3620A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment orange LED with left dot -0 -14 -14 -Display_7Segment -MAN3630A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -Overflow +- 1 orange LED -0 -14 -14 -Display_7Segment -MAN3810A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment yellow LED with right dot -0 -14 -14 -Display_7Segment -MAN3820A -https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php -One digit 7 segment yellow LED with left dot -0 -14 -14 -Display_7Segment -SA15-11xxx -http://www.kingbrightusa.com/images/catalog/SPEC/SA15-11SRWA.pdf -SA15-11xxx single digit 7 segment display 38.1mm 1.5inch -0 -10 -10 -Display_7Segment -SBC18-11SURKCGKWA -http://www.kingbright.com/attachments/file/psearch/000/00/00/SBC18-11SURKCGKWA(Ver.6A).pdf -single digit 7 segemnt red/green LED -0 -10 -10 -Display_7Segment -Sx39-1xxxxx -Single digit 7 segment LED display in red, yellow or green colour http://www.kingbrightusa.com/images/catalog/SPEC/sa39-11ewa.pdf -One digit LED 7 segment SA39-11 SC39-11 SA39-12 SC39-12 -0 -10 -10 -Ferrite_THT -LairdTech_28C0236-0JW-10 -Ferrite, vertical, LairdTech 28C0236-0JW-10, https://assets.lairdtech.com/home/brandworld/files/28C0236-0JW-10.pdf, JW Miller core https://www.bourns.com/products/magnetic-products/j.w.-miller-through-hole-ferrite-beads-emi-filters -Ferrite vertical LairdTech 28C0236-0JW-10 -0 -2 -2 -Fiducial -Fiducial_0.5mm_Mask1.5mm -Circular Fiducial, 0.5mm bare copper, 1.5mm soldermask opening -fiducial -0 -1 -0 -Fiducial -Fiducial_0.5mm_Mask1mm -Circular Fiducial, 0.5mm bare copper, 1mm soldermask opening (Level C) -fiducial -0 -1 -0 -Fiducial -Fiducial_0.75mm_Mask1.5mm -Circular Fiducial, 0.75mm bare copper, 1.5mm soldermask opening (Level B) -fiducial -0 -1 -0 -Fiducial -Fiducial_0.75mm_Mask2.25mm -Circular Fiducial, 0.75mm bare copper, 2.25mm soldermask opening -fiducial -0 -1 -0 -Fiducial -Fiducial_1.5mm_Mask3mm -Circular Fiducial, 1.5mm bare copper, 3mm soldermask opening -fiducial -0 -1 -0 -Fiducial -Fiducial_1.5mm_Mask4.5mm -Circular Fiducial, 1.5mm bare copper, 4.5mm soldermask opening -fiducial -0 -1 -0 -Fiducial -Fiducial_1mm_Mask2mm -Circular Fiducial, 1mm bare copper, 2mm soldermask opening (Level A) -fiducial -0 -1 -0 -Fiducial -Fiducial_1mm_Mask3mm -Circular Fiducial, 1mm bare copper, 3mm soldermask opening (recommended) -fiducial -0 -1 -0 -Filter -Filter_1109-5_1.1x0.9mm -5-pin SAW filter package - 1.1x0.9 mm Body; (see https://www.murata.com/~/media/webrenewal/support/library/catalog/products/filter/rf/p73e.ashx?la=en-gb) -Filter 5 -0 -5 -5 -Filter -Filter_1411-5_1.4x1.1mm -5-pin filter package - 1.4x1.1 mm Body; (see https://global.kyocera.com/prdct/electro/product/pdf/sf14_tdlte.pdf) -Filter 5 -0 -5 -5 -Filter -Filter_Bourns_SRF0905_6.0x9.2mm -https://www.bourns.com/docs/Product-Datasheets/SRF0905.pdf -Line Filter -0 -4 -4 -Filter -Filter_Mini-Circuits_FV1206 -Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206.pdf -Mini-Circuits Filter SMD 1206 -0 -6 -4 -Filter -Filter_Mini-Circuits_FV1206-1 -Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-1.pdf -Mini-Circuits Filter SMD 1206 -0 -6 -6 -Filter -Filter_Mini-Circuits_FV1206-4 -Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-4.pdf -Mini-Circuits Filter SMD 1206 -0 -8 -4 -Filter -Filter_Mini-Circuits_FV1206-5 -Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-5.pdf -Mini-Circuits Filter SMD 1206 -0 -8 -4 -Filter -Filter_Mini-Circuits_FV1206-6 -Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-6.pdf -Mini-Circuits Filter SMD 1206 -0 -14 -8 -Filter -Filter_Mini-Circuits_FV1206-7 -Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-7.pdf -Mini-Circuits Filter SMD 1206 -0 -5 -3 -Filter -Filter_Murata_BNX025 -https://www.murata.com/en-us/products/productdata/8796778004510/QNFH9101.pdf?1496719830000 -EMI Filter -0 -6 -4 -Filter -Filter_Murata_BNX025_ThermalVias -https://www.murata.com/en-us/products/productdata/8796778004510/QNFH9101.pdf?1496719830000 -EMI Filter -0 -19 -4 -Filter -Filter_Schaffner_FN405 -Compact PCB mounting EMI filter (https://www.schaffner.com/de/produkte/download/product/datasheet/fn-405-pcb-mounting-filter/) -EMI filter -0 -5 -5 -Filter -Filter_Schaffner_FN406 -Ultra Compact EMC Filter (https://www.schaffner.com/products/download/product/datasheet/fn-406-ultra-compact-emc-filter/) -emi filter -0 -5 -5 -Fuse -Fuse_0201_0603Metric -Fuse SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator -resistor -0 -4 -2 -Fuse -Fuse_0402_1005Metric -Fuse SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_0603_1608Metric -Fuse SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_0603_1608Metric_Pad1.05x0.95mm_HandSolder -Fuse SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_0805_2012Metric -Fuse SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_0805_2012Metric_Pad1.15x1.40mm_HandSolder -Fuse SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_01005_0402Metric -Fuse SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator -resistor -0 -4 -2 -Fuse -Fuse_1206_3216Metric -Fuse SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder -Fuse SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_1210_3225Metric -Fuse SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_1210_3225Metric_Pad1.42x2.65mm_HandSolder -Fuse SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_1806_4516Metric -Fuse SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_1806_4516Metric_Pad1.57x1.80mm_HandSolder -Fuse SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_1812_4532Metric -Fuse SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_1812_4532Metric_Pad1.30x3.40mm_HandSolder -Fuse SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_2010_5025Metric -Fuse SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_2010_5025Metric_Pad1.52x2.65mm_HandSolder -Fuse SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_2512_6332Metric -Fuse SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_2512_6332Metric_Pad1.52x3.35mm_HandSolder -Fuse SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_2816_7142Metric -Fuse SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_2816_7142Metric_Pad3.20x4.45mm_HandSolder -Fuse SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_2920_7451Metric -Fuse SMD 2920 (7451 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://www.megastar.com/products/fusetronic/polyswitch/PDF/smd2920.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Fuse -Fuse_2920_7451Metric_Pad2.10x5.45mm_HandSolder -Fuse SMD 2920 (7451 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://www.megastar.com/products/fusetronic/polyswitch/PDF/smd2920.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0005FF_L8.3mm_W3.8mm -Fuse 0ZRE0005FF, BelFuse, Radial Leaded PTC, https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0008FF_L8.3mm_W3.8mm -Fuse 0ZRE0008FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0012FF_L8.3mm_W3.8mm -Fuse 0ZRE0012FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0016FF_L9.9mm_W3.8mm -Fuse 0ZRE0016FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0025FF_L9.6mm_W3.8mm -Fuse 0ZRE0025FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0033FF_L11.4mm_W3.8mm -Fuse 0ZRE0033FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0040FF_L11.5mm_W3.8mm -Fuse 0ZRE0040FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0055FF_L14.0mm_W4.1mm -Fuse 0ZRE0055FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0075FF_L11.5mm_W4.8mm -Fuse 0ZRE0075FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0100FF_L18.7mm_W5.1mm -Fuse 0ZRE0100FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0125FF_L21.2mm_W5.3mm -Fuse 0ZRE0125FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0150FF_L23.4mm_W5.3mm -Fuse 0ZRE0150FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_BelFuse_0ZRE0200FF_L24.9mm_W6.1mm -Fuse 0ZRE0200FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf -0ZRE BelFuse radial PTC -0 -2 -2 -Fuse -Fuse_Blade_ATO_directSolder -car blade fuse direct solder -car blade fuse -0 -2 -2 -Fuse -Fuse_Blade_Mini_directSolder -car blade fuse mini, direct solder -car blade fuse mini -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG300 -PTC Resettable Fuse, Ihold = 3.0A, Itrip=5.1A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG400 -PTC Resettable Fuse, Ihold = 4.0A, Itrip=6.8A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG500 -PTC Resettable Fuse, Ihold = 5.0A, Itrip=8.5A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG600 -PTC Resettable Fuse, Ihold = 6.0A, Itrip=10.2A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG650 -PTC Resettable Fuse, Ihold = 6.5A, Itrip=11.1A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG700 -PTC Resettable Fuse, Ihold = 7.0A, Itrip=11.9A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG800 -PTC Resettable Fuse, Ihold = 8.0A, Itrip=13.6A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG900 -PTC Resettable Fuse, Ihold = 9.0A, Itrip=15.3A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG1000 -PTC Resettable Fuse, Ihold = 10.0A, Itrip=17.0A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RG1100 -PTC Resettable Fuse, Ihold = 11.0A, Itrip=18.7A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT050 -PTC Resettable Fuse, Ihold = 0.5A, Itrip=0.92A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT070 -PTC Resettable Fuse, Ihold = 0.7A, Itrip=1.4A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT100 -PTC Resettable Fuse, Ihold = 1.0A, Itrip=1.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT200 -PTC Resettable Fuse, Ihold = 2.0A, Itrip=3.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT300 -PTC Resettable Fuse, Ihold = 3.0A, Itrip=6.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT400 -PTC Resettable Fuse, Ihold = 4.0A, Itrip=7.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT500 -PTC Resettable Fuse, Ihold = 5.0A, Itrip=9.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT550 -PTC Resettable Fuse, Ihold = 5.5A, Itrip=10.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT600 -PTC Resettable Fuse, Ihold = 6.0A, Itrip=10.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT650 -PTC Resettable Fuse, Ihold = 6.5A, Itrip=12.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT700 -PTC Resettable Fuse, Ihold = 7.0A, Itrip=13.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT750 -PTC Resettable Fuse, Ihold = 7.5A, Itrip=13.1A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT800 -PTC Resettable Fuse, Ihold = 8.0A, Itrip=15.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT900 -PTC Resettable Fuse, Ihold = 9.0A, Itrip=16.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT1000 -PTC Resettable Fuse, Ihold = 10.0A, Itrip=18.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT1100 -PTC Resettable Fuse, Ihold = 11.0A, Itrip=20.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-RHT1300 -PTC Resettable Fuse, Ihold = 13.0A, Itrip=24.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf -ptc resettable fuse polyfuse THT -0 -2 -2 -Fuse -Fuse_Bourns_MF-SM_7.98x5.44mm -https://www.bourns.com/docs/Product-Datasheets/mfsm.pdf -bourns ptc resettable fuse polyfuse MF-SM MF-SMHT -0 -2 -2 -Fuse -Fuse_Bourns_MF-SM_9.5x6.71mm -https://www.bourns.com/docs/Product-Datasheets/mfsm.pdf -bourns ptc resettable fuse polyfuse MF-SM MF-SMHT -0 -2 -2 -Fuse -Fuse_Littelfuse-LVR100 -Littelfuse, resettable fuse, PTC, polyswitch LVR100, Ih 1A http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf -LVR100 PTC resettable polyswitch -0 -2 -2 -Fuse -Fuse_Littelfuse-LVR125 -Littelfuse, resettable fuse, PTC, polyswitch LVR125, Ih 1.25A, http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf -LVR125 PTC resettable polyswitch -0 -2 -2 -Fuse -Fuse_Littelfuse-LVR200 -Littelfuse, resettable fuse, PTC, polyswitch LVR200, Ih 2A, http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf -LVR200 PTC resettable polyswitch -0 -2 -2 -Fuse -Fuse_Littelfuse-NANO2-451_453 -Littelfuse NANO2 https://www.littelfuse.com/~/media/electronics/datasheets/fuses/littelfuse_fuse_451_453_datasheet.pdf.pdf -Fuse Nano2 -0 -2 -2 -Fuse -Fuse_Littelfuse_372_D8.50mm -Fuse, Littelfuse, 372, 8.5x8mm, https://www.littelfuse.com/~/media/electronics/datasheets/fuses/littelfuse_fuse_372_datasheet.pdf.pdf -fuse tht radial -0 -2 -2 -Fuse -Fuse_Littelfuse_395Series -Fuse, TE5, Littelfuse/Wickmann, No. 460, No560, -Fuse TE5 Littelfuse/Wickmann No. 460 No560 -0 -2 -2 -Fuse -Fuse_Schurter_UMT250 -Surface Mount Fuse, 3 x 10.1 mm, Time-Lag T, 250 VAC, 125 VDC (https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_UMT_250.pdf) -Schurter fuse smd -0 -2 -2 -Fuse -Fuse_SunFuse-6HP -SunFuse Ceramic Slow Blow Fuse 6H_6HP.PDF -UL/CSA 6x32mm Ceramic Slow Blow Fuse -0 -2 -2 -Fuse -Fuseholder_Blade_ATO_Littelfuse_Pudenz_2_Pin -Fuseholder ATO Blade littelfuse Pudenz 2 Pin -Fuseholder ATO Blade littelfuse Pudenz 2 Pin -0 -2 -2 -Fuse -Fuseholder_Blade_Mini_Keystone_3568 -fuse holder, car blade fuse mini, http://www.keyelco.com/product-pdf.cfm?p=306 -car blade fuse mini -0 -4 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Bulgin_FX0456_Vertical_Closed -Fuseholder, 5x20, closed, vertical, Bulgin, FX0456, https://www.bulgin.com/products/pub/media/bulgin/data/Fuseholders.pdf -Fuseholder 5x20 closed vertical Bulgin FX0456 Sicherungshalter -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Bulgin_FX0457_Horizontal_Closed -Fuseholder, 5x20, closed, horizontal, Bulgin, FX0457, Sicherungshalter, -Fuseholder 5x20 closed horizontal Bulgin FX0457 Sicherungshalter -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_EATON_H15-V-1_Vertical_Closed -PCB fuse holders for 5 mm x 20 mm fuses; 250V; 10A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/bus-elx-ds-4426-h15.pdf) -fuse holder vertical 5x20mm -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_EATON_HBV_Vertical_Closed -5 mm x 20 mm fuse holders; Vertical w/ Stability Pins; 250V; 6.3-16A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/Bus_Elx_DS_2118_HB_PCB_Series.pdf) -fuse holder vertical 5x20mm -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_EATON_HBW_Vertical_Closed -5 mm x 20 mm fuse holders; Vertical w/o Stability Pins; 250V; 6.3-16A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/Bus_Elx_DS_2118_HB_PCB_Series.pdf) -fuse holder vertical 5x20mm -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Schurter_0031_8201_Horizontal_Open -Fuseholder horizontal open, 5x20mm, 500V, 16A, Schurter 0031.8201, https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_OGN.pdf -Fuseholder horizontal open 5x20 Schurter 0031.8201 -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Schurter_FAB_0031-355x_Horizontal_Closed -Fuseholder 5x20mm horizontal Shurter model FAB, Suitable for order numbers 0031.3551 and 0031.3558 (https://www.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FAB.pdf) -Fuseholder 5x20mm closed horizontal -0 -2 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Schurter_FPG4_Vertical_Closed -Shock-Safe Fuseholder, 5 x 20 mm, Slotted Cap/Fingergrip, vertical, IEC 60335-1; 250VAC/10A VDE; 500V/16A UL/CSA (https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FPG4.pdf) -fuse holder vertical 5x20mm -0 -4 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Schurter_FUP_0031.2510_Horizontal_Closed -Shock-Safe closed Fuseholder, Schurter FUP Series, 5.0 x 20mm, Slotted Cap, horizontal, 500 VAC 4W/16A (VDE), 600V 30A (UL/CSA), order numbers: 0031.2510 (0031.2500 + 0031.2323), http://www.schurter.ch/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FUP.pdf -Fuseholder 5x20mm horizontal closed -0 -3 -2 -Fuse -Fuseholder_Cylinder-5x20mm_Stelvio-Kontek_PTF78_Horizontal_Open -https://www.tme.eu/en/Document/3b48dbe2b9714a62652c97b08fcd464b/PTF78.pdf -Fuseholder horizontal open 5x20 Stelvio-Kontek PTF/78 -0 -2 -2 -Fuse -Fuseholder_Cylinder-6.3x32mm_Schurter_0031-8002_Horizontal_Open -Fuseholder, horizontal, open, 6.3x32, Schurter, 0031.8002, https://www.schurter.com/en/datasheet/typ_OG__Holder__6.3x32.pdf -Fuseholder horizontal open 6.3x32 Schurter 0031.8002 -0 -2 -2 -Fuse -Fuseholder_Cylinder-6.3x32mm_Schurter_FUP_0031.2520_Horizontal_Closed -Shock-Safe closed Fuseholder, Schurter FUP Series, 6.3 x 32 mm, Slotted Cap, horizontal, 500 VAC 4W/16A (VDE), 600V 30A (UL/CSA), order numbers: 0031.2520 (0031.2500 + 0031.2321), http://www.schurter.ch/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FUP.pdf -Fuseholder 6.3x32mm horizontal closed -0 -3 -2 -Fuse -Fuseholder_TR5_Littelfuse_No560_No460 -Fuse, Fuseholder, TR5, Littelfuse/Wickmann, No. 460, No560, https://www.littelfuse.com/~/media/electronics/datasheets/fuse_holders/littelfuse_fuse_holder_559_560_datasheet.pdf.pdf -Fuse Fuseholder TR5 Littelfuse/Wickmann No. 460 No560 -0 -2 -2 -Heatsink -Heatsink_35x26mm_1xFixation3mm_Fischer-SK486-35 -Heatsink, 35mm x 26mm, 1x Fixation 3mm, Fischer SK486-35 -heatsink -0 -1 -1 -Heatsink -Heatsink_38x38mm_SpringFixation -Heatsink, 38x38mm, Spring Fixation, diagonal, -heatsink -0 -4 -1 -Heatsink -Heatsink_62x40mm_2xFixation3mm -Heatsink, 62 x 40mm, 2x 3mm Drills, -heatsink -0 -2 -1 -Heatsink -Heatsink_125x35x50mm_3xFixationM3 -Heatsink, 125x35x50mm, 3 fixation holes 3.2mm -heatsink -0 -0 -0 -Heatsink -Heatsink_AAVID_573300D00010G_TO-263 -Heatsink, 12.70mm x 26.16mm x 10.16, SMD, 18K/W, TO-263, D2 Pak, https://www.shopaavid.com/Product/573300D00000G -Heatsink AAVID TO-263 D2 Pak -0 -2 -1 -Heatsink -Heatsink_Aavid-TV5G_TO220_Horizontal -Heatsink TV5G TO-220 Horizontal, https://www.shopaavid.com/Product/TV-5G -Heatsink TV5G TO-220 Horizontal -0 -0 -0 -Heatsink -Heatsink_Fischer_FK24413D2PAK_26x13mm -26x13 mm SMD heatsink for TO-252 TO-263 TO-268, https://www.fischerelektronik.de/pim/upload/fischerData/cadpdf/base/fk_244_13_d2_pak.pdf -heatsink TO-252 TO-263 TO-268 -0 -2 -1 -Heatsink -Heatsink_Fischer_SK104-STC-STIC_35x13mm_2xDrill2.5mm -Heatsink, 35mm x 13mm, 2x Fixation 2,5mm Drill, Soldering, Fischer SK104-STC-STIC, -Heatsink fischer TO-220 -0 -2 -1 -Heatsink -Heatsink_Fischer_SK104-STCB_35x13mm__2xDrill3.5mm_ScrewM3 -Heatsink, 35mm x 13mm, 2x Fixation 2,5mm Drill, Soldering, Fischer SK104-STC-STIC, -Heatsink fischer TO-220 -0 -2 -1 -Heatsink -Heatsink_Fischer_SK129-STS_42x25mm_2xDrill2.5mm -Heatsink, Fischer SK129 -heatsink fischer -0 -2 -1 -Heatsink -Heatsink_SheetType_50x7mm_2Fixations -Heatsink, Sheet type, 50x7mm, 2 fixations (solder), -Heatsink sheet -0 -2 -1 -Heatsink -Heatsink_Stonecold_HS-132_32x14mm_2xFixation1.5mm -Heatsink, StoneCold HS -heatsink -0 -2 -1 -Inductor_SMD -L_6.3x6.3_H3 -Choke, SMD, 6.3x6.3mm 3mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_7.3x7.3_H3.5 -Choke, SMD, 7.3x7.3mm 3.5mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_7.3x7.3_H4.5 -Choke, SMD, 7.3x7.3mm 4.5mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_10.4x10.4_H4.8 -Choke, SMD, 10.4x10.4mm 4.8mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_12x12mm_H4.5mm -Choke, SMD, 12x12mm 4.5mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_12x12mm_H6mm -Choke, SMD, 12x12mm 6mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_12x12mm_H8mm -Choke, SMD, 12x12mm 8mm height -Choke SMD -0 -2 -2 -Inductor_SMD -L_0201_0603Metric -Inductor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator -inductor -0 -4 -2 -Inductor_SMD -L_0402_1005Metric -Inductor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_0603_1608Metric -Inductor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_0603_1608Metric_Pad1.05x0.95mm_HandSolder -Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_0805_2012Metric -Inductor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_0805_2012Metric_Pad1.15x1.40mm_HandSolder -Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_01005_0402Metric -Inductor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator -inductor -0 -4 -2 -Inductor_SMD -L_1008_2520Metric -Inductor SMD 1008 (2520 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://ecsxtal.com/store/pdf/ECS-MPI2520-SMD-POWER-INDUCTOR.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_1206_3216Metric -Inductor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_1206_3216Metric_Pad1.42x1.75mm_HandSolder -Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_1210_3225Metric -Inductor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_1210_3225Metric_Pad1.42x2.65mm_HandSolder -Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_1806_4516Metric -Inductor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_1806_4516Metric_Pad1.57x1.80mm_HandSolder -Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_1812_4532Metric -Inductor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_1812_4532Metric_Pad1.30x3.40mm_HandSolder -Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_2010_5025Metric -Inductor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_2010_5025Metric_Pad1.52x2.65mm_HandSolder -Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_2512_6332Metric -Inductor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_2512_6332Metric_Pad1.52x3.35mm_HandSolder -Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_2816_7142Metric -Inductor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -inductor -0 -2 -2 -Inductor_SMD -L_2816_7142Metric_Pad3.20x4.45mm_HandSolder -Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -inductor handsolder -0 -2 -2 -Inductor_SMD -L_Abracon_ASPI-0630LR -smd shielded power inductor https://abracon.com/Magnetics/power/ASPI-0630LR.pdf -inductor abracon smd shielded -0 -2 -2 -Inductor_SMD -L_Abracon_ASPI-3012S -smd shielded power inductor http://www.abracon.com/Magnetics/power/ASPI-3012S.pdf -inductor abracon smd shielded -0 -2 -2 -Inductor_SMD -L_Bourns-SRN1060 -Bourns SRN1060 series SMD inductor https://www.bourns.com/docs/Product-Datasheets/SRN1060.pdf -Bourns SRN1060 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns-SRN4018 -Bourns SRN4018 series SMD inductor, https://www.bourns.com/docs/Product-Datasheets/SRN4018.pdf -Bourns SRN4018 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns-SRN6028 -Bourns SRN6028 series SMD inductor -Bourns SRN6028 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns-SRN8040_8x8.15mm -Bourns SRN8040 series SMD inductor 8x8.15mm, https://www.bourns.com/docs/Product-Datasheets/SRN8040.pdf -Bourns SRN8040 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns-SRR1005 -Bourns SRR1005 series SMD inductor -Bourns SRR1005 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns-SRU1028_10.0x10.0mm -Bourns SRU1028 series SMD inductor, https://www.bourns.com/docs/Product-Datasheets/SRU1028.pdf -Bourns SRU1028 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns-SRU8043 -Bourns SRU8043 series SMD inductor -Bourns SRU8043 SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns_SDR1806 -https://www.bourns.com/docs/Product-Datasheets/SDR1806.pdf -Bourns SDR1806 -0 -2 -2 -Inductor_SMD -L_Bourns_SRN6045TA -http://www.bourns.com/docs/product-datasheets/srn6045ta.pdf -Semi-shielded Power Inductor -0 -2 -2 -Inductor_SMD -L_Bourns_SRN8040TA -https://www.bourns.com/docs/product-datasheets/srn8040ta.pdf -Inductor -0 -2 -2 -Inductor_SMD -L_Bourns_SRP1245A -Bourns SRP1245A series SMD inductor http://www.bourns.com/docs/Product-Datasheets/SRP1245A.pdf -Bourns SRP1245A SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns_SRP2313AA -Bourns SRR1260 series SMD inductor http://www.bourns.com/docs/product-datasheets/srp2313aa.pdf -Bourns SRR1260 SMD inductor -0 -4 -2 -Inductor_SMD -L_Bourns_SRP7028A_7.3x6.6mm -Shielded Power Inductors (https://www.bourns.com/docs/product-datasheets/srp7028a.pdf) -Shielded Inductors Bourns SMD SRP7028A -0 -2 -2 -Inductor_SMD -L_Bourns_SRR1210A -Bourns SRR1210A series SMD inductor https://www.bourns.com/docs/Product-Datasheets/SRR1210A.pdf -Bourns SRR1210A SMD inductor -0 -2 -2 -Inductor_SMD -L_Bourns_SRR1260 -Bourns SRR1260 series SMD inductor http://www.bourns.com/docs/Product-Datasheets/SRR1260.pdf -Bourns SRR1260 SMD inductor -0 -2 -2 -Inductor_SMD -L_Coilcraft_LPS4018 -SMD Inductor Coilcraft LPS4018 https://www.coilcraft.com/pdfs/lps4018.pdf -L Coilcraft LPS4018 -0 -2 -2 -Inductor_SMD -L_Coilcraft_LPS5030 -Shielded Power Inductor SMD, Coilcraft LPS5030, https://www.coilcraft.com/pdfs/lps5030.pdf, StepUp generated footprint -inductor -0 -2 -2 -Inductor_SMD -L_Coilcraft_XAL60xx_6.36x6.56mm -Coilcraft XAL60xx series, https://www.coilcraft.com/pdfs/xal60xx.pdf -L Coilcraft XAL60xx -0 -2 -2 -Inductor_SMD -L_Coilcraft_XAL5030 -L_Coilcraft_XAL5030 -L Coilcraft XAL5030 -0 -2 -2 -Inductor_SMD -L_Coilcraft_XxL4020 -L_Coilcraft_XxL4020 https://www.coilcraft.com/pdfs/xfl4020.pdf -L Coilcraft XxL4020 -0 -2 -2 -Inductor_SMD -L_Coilcraft_XxL4030 -L_Coilcraft_XxL4030 https://www.coilcraft.com/pdfs/xfl4030.pdf -L Coilcraft XxL4030 -0 -2 -2 -Inductor_SMD -L_Coilcraft_XxL4040 -L_Coilcraft_XxL4040 https://www.coilcraft.com/pdfs/xal4000.pdf -L Coilcraft XxL4040 -0 -2 -2 -Inductor_SMD -L_CommonMode_Delevan_4222 -API Delevan, Surface Mount Common Mode Bead, 4222 4222R, http://www.delevan.com/seriesPDFs/4222.pdf -surface mount common mode bead -0 -4 -4 -Inductor_SMD -L_CommonMode_Wuerth_WE-SL2 -http://katalog.we-online.de/en/pbs/WE-SL2?sid=5fbec16187#vs_t1:c1_ct:1 -Wuerth WE-SL2 -0 -4 -4 -Inductor_SMD -L_Fastron_PISN -Choke, Drossel, PISN, SMD, Fastron, -Choke Drossel PISN SMD Fastron -0 -2 -2 -Inductor_SMD -L_Fastron_PISN_Handsoldering -Choke, Drossel, PISN, SMD, Fastron, -Choke Drossel PISN SMD Fastron -0 -2 -2 -Inductor_SMD -L_Fastron_PISR -Choke, Drossel, PISR, Fastron, SMD, -Choke Drossel PISR Fastron SMD -0 -2 -2 -Inductor_SMD -L_Fastron_PISR_Handsoldering -Choke, Drossel, PISR, Fastron, SMD, -Choke Drossel PISR Fastron SMD -0 -2 -2 -Inductor_SMD -L_Murata_DEM35xxC -https://www.murata.com/~/media/webrenewal/products/inductor/chip/tokoproducts/wirewoundferritetypeforpl/m_dem3518c.ashx -Inductor SMD DEM35xxC -0 -2 -2 -Inductor_SMD -L_Murata_LQH2MCNxxxx02_2.0x1.6mm -Inductor, Murata, LQH2MCN_02 series, 1.6x2.0x0.9mm (https://search.murata.co.jp/Ceramy/image/img/P02/JELF243A-0053.pdf) -chip coil inductor Murata LQH2MC -0 -2 -2 -Inductor_SMD -L_Murata_LQH55DN_5.7x5.0mm -Inductor, SMD, 5.7x5.0x4.7mm, https://search.murata.co.jp/Ceramy/image/img/P02/JELF243A-0045.pdf -inductor smd -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_1turn_HDM0131A -Neosid, Air-Coil, SML, 1turn, HDM0131A, -Neosid Air-Coil SML 1turn HDM0131A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_2turn_HAM0231A -Neosid, Air-Coil, SML, 2turn, HAM0231A, -Neosid Air-Coil SML 2turn HAM0231A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_2turn_HDM0231A -Neosid, Air-Coil, SML, 2turn, HDM0231A, -Neosid Air-Coil SML 2turn HDM0231A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_3turn_HAM0331A -Neosid, Air-Coil, SML, 2turn, HAM0331A, -Neosid Air-Coil SML 3turn HAM0331A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_3turn_HDM0331A -Neosid, Air-Coil, SML, 3turn, HDM0331A, -Neosid Air-Coil SML 3turn HDM0331A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_4turn_HAM0431A -Neosid, Air-Coil, SML, 4turn, HAM0431A, -Neosid Air-Coil SML 4turn HAM0431A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_4turn_HDM0431A -Neosid, Air-Coil, SML, 4turn, HDM0431A, -Neosid Air-Coil SML 4turn HDM0431A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_5turn_HAM0531A -Neosid, Air-Coil, SML, 5turn, HAM0531A, -Neosid Air-Coil SML 5turn HAM0531A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_5turn_HDM0531A -Neosid, Air-Coil, SML, 5turn, HDM0531A, -Neosid Air-Coil SML 5turn HDM0531A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_6-10turn_HAM0631A-HAM1031A -Neosid, Air-Coil, SML, 6-10turn, HAM0631A-HAM1031A, -Neosid Air-Coil SML 6-10turn HAM0631A-HAM1031A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_6-10turn_HDM0431A-HDM1031A -Neosid, Air-Coil, SML, 6-10turn, HDM0431A-HDM1031A, -Neosid Air-Coil SML 6-10turn HDM0431A-HDM1031A -0 -2 -2 -Inductor_SMD -L_Neosid_Air-Coil_SML_6turn_HAM0631A -Neosid, Air-Coil, SML, 6turn, HAM0631A, -Neosid Air-Coil SML 6turn HAM0631A -0 -2 -2 -Inductor_SMD -L_Neosid_MicroCoil_Ms36-L -Neosid, Micro Coil, Inductor, Ms36-L, SMD, Fixed inductor, anti clockwise, https://neosid.de/en/products/inductors/rod-core-chokes/smd-rod-core-chokes/52026/ms-36/7-h?c=94 -Neosid Micro Coil Inductor Ms36-L SMD Fixed inductor anti clockwise -0 -2 -2 -Inductor_SMD -L_Neosid_Ms42 -Neosid, Inductor, SMs42, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_Ms42.pdf -Neosid Inductor SMs42 Fixed inductor SMD magneticaly shielded -0 -2 -2 -Inductor_SMD -L_Neosid_Ms50 -Neosid, Power Inductor, Ms50, SMD, Fixed inductor, https://neosid.de/import-data/product-pdf/neoFestind_Ms50.pdf -Neosid Power Inductor Ms50 SMD Fixed inductor -0 -2 -2 -Inductor_SMD -L_Neosid_Ms50T -Neosid, Power Inductor, Ms50T, SMD, Fixed inductor, high temperature, https://neosid.de/import-data/product-pdf/neoFestind_Ms50T.pdf -Neosid Power Inductor Ms50T SMD Fixed inductor high temperature -0 -2 -2 -Inductor_SMD -L_Neosid_Ms85 -Neosid, Ms85, Ms85T, SMD Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms85.pdf -Neosid Ms85 Ms85T SMD Inductor Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_Ms85T -Neosid, Ms85, Ms85T, SMD Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms85T.pdf -Neosid Ms85 Ms85T SMD Inductor Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_Ms95 -Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95.pdf -NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_Ms95T -Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95T.pdf -NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_Ms95a -Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95a.pdf -NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-NE95H -Neosid, Inductor,SM-NE95H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE95H.pdf -Neosid Inductor SM-NE95H Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-NE127 -Neosid, Inductor, SM-NE127, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE127.pdf -Neosid Inductor SM-NE127 Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-NE127_HandSoldering -Neosid, Inductor, SM-NE127, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE127.pdf -Neosid Inductor SM-NE127 Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-NE150 -Neosid, Inductor, SM-NE150, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE150.pdf -Neosid Inductor SM-NE150 Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-PIC0512H -Neosid, Inductor, PIC0512H, Power Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0512H.pdf -Neosid Inductor PIC0512H Power Inductor Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-PIC0602H -Neosid, Power Inductor, SM-PIC0602H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0602H.pdf -Neosid Power Inductor SM-PIC0602H Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-PIC0612H -Neosid, Power Inductor, SM-PIC0612H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0612H.pdf -Neosid Power Inductor SM-PIC0612H Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SM-PIC1004H -Neosid, Inductor, SM-PIC1004H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC1004H.pdf -Neosid Inductor SM-PIC1004H Fixed inductor SMD -0 -2 -2 -Inductor_SMD -L_Neosid_SMS-ME3010 -Neosid, Inductor, SMS-ME3010, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMSME3010.pdf -Neosid Inductor SMS-ME3010 Fixed inductor SMD magnetically shielded -0 -2 -2 -Inductor_SMD -L_Neosid_SMS-ME3015 -Neosid, Power Inductor, SMS-ME3015, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMSME3015.pdf -Neosid Power Inductor SMS-ME3015 Fixed inductor SMD magnetically shielded -0 -2 -2 -Inductor_SMD -L_Neosid_SMs42 -Neosid, Inductor, SMs42, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs42.pdf -Neosid Inductor SMs42 Fixed inductor SMD magneticaly shielded -0 -2 -2 -Inductor_SMD -L_Neosid_SMs50 -Neosid, Inductor, SMs50, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs50.pdf -Neosid Inductor SMs50 Fixed inductor SMD magneticaly shielded -0 -2 -2 -Inductor_SMD -L_Neosid_SMs85 -Neosid, Inductor, SMs85, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs85.pdf -Neosid Inductor SMs85 Fixed inductor SMD magnetically shielded -0 -2 -2 -Inductor_SMD -L_Neosid_SMs95_SMs95p -Neosid, Inductor, SMs95, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMs95SMs95p.pdf -Neosid Inductor SMs95 Fixed inductor SMD magnetically shielded -0 -2 -2 -Inductor_SMD -L_Pulse_PA4320 -Inductor SMD Pulse PA4320 http://productfinder.pulseeng.com/products/datasheets/P787.pdf -Inductor SMD Pulse PA4320 -0 -2 -2 -Inductor_SMD -L_Sagami_CER1242B -Inductor, Sagami, h=4.5mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf -inductor sagami cer12xxb smd -0 -2 -2 -Inductor_SMD -L_Sagami_CER1257B -Inductor, Sagami, h=6.0mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf -inductor sagami cer12xxb smd -0 -2 -2 -Inductor_SMD -L_Sagami_CER1277B -Inductor, Sagami, h=8.0mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf -inductor sagami cer12xxb smd -0 -2 -2 -Inductor_SMD -L_Sagami_CWR1242C -Sagami power inductor, CWR1242C, H=4.5mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf) -inductor sagami cwr12xx smd -0 -4 -2 -Inductor_SMD -L_Sagami_CWR1257C -Sagami power inductor, CWR1242C, H=6.0mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf) -inductor sagami cwr12xx smd -0 -4 -2 -Inductor_SMD -L_Sagami_CWR1277C -Sagami power inductor, CWR1242C, H=7.7mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf) -inductor sagami cwr12xx smd -0 -4 -2 -Inductor_SMD -L_SigTra_SC3316F -http://www.signaltransformer.com/sites/all/pdf/smd/P080_SC3316F.pdf -Choke -0 -2 -2 -Inductor_SMD -L_Sumida_CDMC6D28_7.25x6.5mm -SMD Power Inductor (http://products.sumida.com/products/pdf/CDMC6D28.pdf) -Inductor Sumida SMD CDMC6D28 -0 -2 -2 -Inductor_SMD -L_Sunlord_MWSA0518_5.4x5.2mm -Inductor, Sunlord, MWSA0518, 5.4mmx5.2mm -inductor Sunlord smd -0 -2 -2 -Inductor_SMD -L_TDK_NLV25_2.5x2.0mm -TDK NLV25, 2.5x2.0x1.8mm, https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_standard_nlv25-ef_en.pdf -tdk nlv25 nlcv25 nlfv25 -0 -2 -2 -Inductor_SMD -L_TDK_NLV32_3.2x2.5mm -TDK NLV32, 3.2x2.5x2.2mm, https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_standard_nlv32-ef_en.pdf -tdk nlv32 nlcv32 nlfv32 -0 -2 -2 -Inductor_SMD -L_TDK_SLF6025 -Inductor, TDK, SLF6025, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6025_en.pdf) -Inductor TDK_SLF6025 -0 -2 -2 -Inductor_SMD -L_TDK_SLF6028 -Inductor, TDK, SLF6028, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6028_en.pdf) -Inductor TDK_SLF6028 -0 -2 -2 -Inductor_SMD -L_TDK_SLF6045 -Inductor, TDK, SLF6045, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6045_en.pdf) -Inductor TDK_SLF6045 -0 -2 -2 -Inductor_SMD -L_TDK_SLF7032 -Inductor, TDK, SLF7032, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7032_en.pdf) -Inductor TDK_SLF7032 -0 -2 -2 -Inductor_SMD -L_TDK_SLF7045 -Inductor, TDK, SLF7045, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7045_en.pdf) -Inductor TDK_SLF7045 -0 -2 -2 -Inductor_SMD -L_TDK_SLF7055 -Inductor, TDK, SLF7055, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7055_en.pdf) -Inductor TDK_SLF7055 -0 -2 -2 -Inductor_SMD -L_TDK_SLF10145 -Inductor, TDK, SLF10145, 10.1mmx10.1mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf10145-h_en.pdf) -Inductor TDK_SLF10145 -0 -2 -2 -Inductor_SMD -L_TDK_SLF10165 -Inductor, TDK, SLF10165, 10.1mmx10.1mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_power_slf10165_en.pdf) -Inductor TDK_SLF10165 -0 -2 -2 -Inductor_SMD -L_TDK_SLF12555 -Inductor, TDK, SLF12555, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_power_slf12555_en.pdf) -Inductor SLF12555 -0 -2 -2 -Inductor_SMD -L_TDK_SLF12565 -Inductor, TDK, SLF12565, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf12565-h_en.pdf) -Inductor SLF12565 -0 -2 -2 -Inductor_SMD -L_TDK_SLF12575 -Inductor, TDK, SLF12575, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf12575-h_en.pdf) -Inductor SLF12575 -0 -2 -2 -Inductor_SMD -L_TDK_VLF10040 -Inductor,TDK, TDK-VLP-8040, 8.6mmx8.6mm -inductor TDK VLP smd VLF10040 -0 -2 -2 -Inductor_SMD -L_TDK_VLP8040 -Inductor,TDK, TDK-VLP-8040, 8.6mmx8.6mm -inductor TDK VLP smd VLP8040 -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_MD-1616 -Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-1616, 1.6mmx1.6mm -inductor taiyo-yuden md smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_MD-2020 -Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-2020, 2.0mmx2.0mm -inductor taiyo-yuden md smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_MD-3030 -Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-3030, 3.0mmx3.0mm -inductor taiyo-yuden md smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_MD-4040 -Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-4040, 4.0mmx4.0mm -inductor taiyo-yuden md smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_MD-5050 -Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-5050, 5.0mmx5.0mm -inductor taiyo-yuden md smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-20xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-20xx, 2.0mmx2.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-20xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-20xx, 2.0mmx2.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-24xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-24xx, 2.4mmx2.4mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-24xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-24xx, 2.4mmx2.4mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-30xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-30xx, 3.0mmx3.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-30xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-30xx, 3.0mmx3.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-40xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-40xx, 4.0mmx4.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-40xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-40xx, 4.0mmx4.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-50xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-50xx, 4.9mmx4.9mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-50xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-50xx, 4.9mmx4.9mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-60xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-60xx, 6.0mmx6.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-60xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-60xx, 6.0mmx6.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-80xx -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-80xx, 8.0mmx8.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-80xx_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-80xx, 8.0mmx8.0mm -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-10050_9.8x10.0mm -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-10050, 9.8mmx10.0mm, https://ds.yuden.co.jp/TYCOMPAS/or/specSheet?pn=NR10050T1R3N -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_Taiyo-Yuden_NR-10050_9.8x10.0mm_HandSoldering -Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-10050, 9.8mmx10.0mm, https://ds.yuden.co.jp/TYCOMPAS/or/specSheet?pn=NR10050T1R3N -inductor taiyo-yuden nr smd -0 -2 -2 -Inductor_SMD -L_TracoPower_TCK-141 -Choke, SMD, 4.0x4.0mm 2.1mm height, https://www.tracopower.com/products/tck141.pdf -Choke SMD -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-1212 -Inductor, Vishay, IHLP series, 3.0mmx3.0mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-1616 -Inductor, Vishay, IHLP series, 4.1mmx4.1mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-2020 -Inductor, Vishay, IHLP series, 5.1mmx5.1mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-2525 -Inductor, Vishay, IHLP series, 6.3mmx6.3mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-4040 -Inductor, Vishay, IHLP series, 10.2mmx10.2mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-5050 -Inductor, Vishay, IHLP series, 12.7mmx12.7mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHLP-6767 -Inductor, Vishay, IHLP series, 17.0mmx17.0mm -inductor vishay ihlp smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHSM-3825 -Inductor, Vishay, Vishay_IHSM-3825, http://www.vishay.com/docs/34018/ihsm3825.pdf, 11.2mmx6.3mm -inductor vishay icsm smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHSM-4825 -Inductor, Vishay, Vishay_IHSM-4825, http://www.vishay.com/docs/34019/ihsm4825.pdf, 13.7mmx6.3mm -inductor vishay icsm smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHSM-5832 -Inductor, Vishay, Vishay_IHSM-5832, http://www.vishay.com/docs/34020/ihsm5832.pdf, 16.3mmx8.1mm -inductor vishay icsm smd -0 -2 -2 -Inductor_SMD -L_Vishay_IHSM-7832 -Inductor, Vishay, Vishay_IHSM-7832, http://www.vishay.com/docs/34021/ihsm7832.pdf, 19.8mmx8.1mm -inductor vishay icsm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1030 -Inductor, Wuerth Elektronik, Wuerth_HCI-1030, 10.6mmx10.6mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1040 -Inductor, Wuerth Elektronik, Wuerth_HCI-1040, 10.2mmx10.2mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1050 -Inductor, Wuerth Elektronik, Wuerth_HCI-1050, 10.2mmx10.2mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1335 -Inductor, Wuerth Elektronik, Wuerth_HCI-1335, 12.8mmx12.8mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1350 -Inductor, Wuerth Elektronik, Wuerth_HCI-1350, 12.8mmx12.8mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1365 -Inductor, Wuerth Elektronik, Wuerth_HCI-1365, 12.8mmx12.8mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-1890 -Inductor, Wuerth Elektronik, Wuerth_HCI-1890, 18.2mmx18.2mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-2212 -Inductor, Wuerth Elektronik, Wuerth_HCI-2212, 22.5mmx22.0mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-5040 -Inductor, Wuerth Elektronik, Wuerth_HCI-5040, 5.5mmx5.2mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-7030 -Inductor, Wuerth Elektronik, Wuerth_HCI-7030, 6.9mmx6.9mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-7040 -Inductor, Wuerth Elektronik, Wuerth_HCI-7040, 6.9mmx6.9mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCI-7050 -Inductor, Wuerth Elektronik, Wuerth_HCI-7050, 6.9mmx6.9mm -inductor Wuerth hci smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1050 -Inductor, Wuerth Elektronik, Wuerth_HCM-1050, 10.2mmx7.0mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1052 -Inductor, Wuerth Elektronik, Wuerth_HCM-1052, 10.5mmx10.3mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1070 -Inductor, Wuerth Elektronik, Wuerth_HCM-1070, 10.1mmx7.0mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1078 -Inductor, Wuerth Elektronik, Wuerth_HCM-1078, 9.4mmx6.2mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1190 -Inductor, Wuerth Elektronik, Wuerth_HCM-1190, 10.5mmx11.0mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1240 -Inductor, Wuerth Elektronik, Wuerth_HCM-1240, 10.0mmx11.8mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1350 -Inductor, Wuerth Elektronik, Wuerth_HCM-1350, 13.5mmx13.3mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-1390 -Inductor, Wuerth Elektronik, Wuerth_HCM-1390, 12.5mmx13.0mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-7050 -Inductor, Wuerth Elektronik, Wuerth_HCM-7050, 7.2mmx7.0mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_HCM-7070 -Inductor, Wuerth Elektronik, Wuerth_HCM-7070, 7.4mmx7.2mm -inductor Wuerth hcm smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-1610 -Inductor, Wuerth Elektronik, Wuerth_MAPI-1610, 1.6mmx1.6mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-2010 -Inductor, Wuerth Elektronik, Wuerth_MAPI-2010, 2.0mmx1.6mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-2506 -Inductor, Wuerth Elektronik, Wuerth_MAPI-2506, 2.5mmx2.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-2508 -Inductor, Wuerth Elektronik, Wuerth_MAPI-2508, 2.5mmx2.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-2510 -Inductor, Wuerth Elektronik, Wuerth_MAPI-2510, 2.5mmx2.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-2512 -Inductor, Wuerth Elektronik, Wuerth_MAPI-2512, 2.5mmx2.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-3010 -Inductor, Wuerth Elektronik, Wuerth_MAPI-3010, 3.0mmx3.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-3012 -Inductor, Wuerth Elektronik, Wuerth_MAPI-3012, 3.0mmx3.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-3015 -Inductor, Wuerth Elektronik, Wuerth_MAPI-3015, 3.0mmx3.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-3020 -Inductor, Wuerth Elektronik, Wuerth_MAPI-3020, 3.0mmx3.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-4020 -Inductor, Wuerth Elektronik, Wuerth_MAPI-4020, 4.0mmx4.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_MAPI-4030 -Inductor, Wuerth Elektronik, Wuerth_MAPI-4030, 4.0mmx4.0mm -inductor Wuerth smd -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-DD-Typ-L-Typ-XL-Typ-XXL -Shielded Coupled Inductor, Wuerth Elektronik, WE-DD, SMD, Typ L, Typ XL, Typ XXL, https://katalog.we-online.com/pbs/datasheet/744874001.pdf -Choke Coupled Double Inductor SMD Wuerth WE-DD TypL TypXL TypXXL -0 -4 -4 -Inductor_SMD -L_Wuerth_WE-DD-Typ-M-Typ-S -Shielded Coupled Inductor, Wuerth Elektronik, WE-DD, SMD, Typ M, Typ S, https://katalog.we-online.com/pbs/datasheet/744878001.pdf, https://katalog.we-online.de/pbs/datasheet/744877001.pdf -Choke Coupled Double Inductor SMD Wuerth WE-DD TypM TypS -0 -4 -4 -Inductor_SMD -L_Wuerth_WE-PD-Typ-7345 -Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, 7345, https://katalog.we-online.com/pbs/datasheet/744777001.pdf -Choke Shielded Power Inductor WE-PD 7345 Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD-Typ-LS -Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, Typ LS, https://katalog.we-online.com/pbs/datasheet/7447715906.pdf -Choke Shielded Power Inductor WE-PD TypLS Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD-Typ-LS_Handsoldering -Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, Typ LS, Handsoldering, https://katalog.we-online.com/pbs/datasheet/7447715906.pdf -Choke Shielded Power Inductor WE-PD TypLS Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD-Typ-M-Typ-S -Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMT, Typ M, Typ S, https://katalog.we-online.com/pbs/datasheet/744778005.pdf -Choke Shielded Power Inductor WE-PD TypM TypS Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD-Typ-M-Typ-S_Handsoldering -Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMT, Typ M, Typ S, Handsoldering, https://katalog.we-online.com/pbs/datasheet/744778005.pdf -Choke Shielded Power Inductor WE-PD TypM TypS Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD2-Typ-L -Power Inductor, Wuerth Elektronik, WE-PD2, SMD, Typ L, , https://katalog.we-online.com/pbs/datasheet/74477510.pdf -Choke Power Inductor WE-PD2 TypL Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD2-Typ-MS -Power Inductor, Wuerth Elektronik, WE-PD2, SMD, Typ MS, https://katalog.we-online.com/pbs/datasheet/744774022.pdf -Choke Power Inductor WE-PD2 TypMS Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD2-Typ-XL -Power Inductor, Wuerth Elektronik, WE-PD2, SMT, Typ XL, https://katalog.we-online.com/pbs/datasheet/744776012.pdf -Choke Power Inductor WE-PD2 TypXL Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PD4-Typ-X -Power Inductor, Wuerth Elektronik, WE-PD4, SMT, Typ X, https://katalog.we-online.de/pbs/datasheet/74458001.pdf -Choke Power Inductor WE-PD4 TypX Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PDF -Shielded Power Inductor, Wuerth Elektronik, WE-PDF, SMD, https://katalog.we-online.de/pbs/datasheet/7447797022.pdf -Choke Shielded Power Inductor WE-PDF Wuerth -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-PDF_Handsoldering -Shielded Power Inductor, Wuerth Elektronik, WE-PDF, SMD, Handsoldering, https://katalog.we-online.de/pbs/datasheet/7447797022.pdf -Choke Shielded Power Inductor WE-PDF Wuerth Handsoldering -0 -2 -2 -Inductor_SMD -L_Wuerth_WE-TPC-3816 -L_Wuerth_WE-TPC-3816 StepUp generated footprint, http://katalog.we-online.de/pbs/datasheet/7440310047.pdf -wurth wuerth smd inductor -0 -2 -2 -Inductor_THT -Choke_EPCOS_B82722A -Current-Compensated Ring Core Double Chokes, EPCOS, B82722A, 22.3mmx22.7mm, https://en.tdk.eu/inf/30/db/ind_2008/b82722a_j.pdf -chokes epcos tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN102-04-14.0x14.0mm -Current-compensated Chokes, Scaffner, RN102-04, 14.0mmx14.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN112-04-17.7x17.1mm -Current-compensated Chokes, Scaffner, RN112-04, 17.7mmx17.1mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN114-04-22.5x21.5mm -Current-compensated Chokes, Scaffner, RN114-04, 22.5mmx21.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN116-04-22.5x21.5mm -Current-compensated Chokes, Scaffner, RN116-04, 22.5mmx21.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN122-04-28.0x27.0mm -Current-compensated Chokes, Scaffner, RN122-04, 28.0mmx27.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN142-04-33.1x32.5mm -Current-compensated Chokes, Scaffner, RN142-04, 33.1mmx32.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN143-04-33.1x32.5mm -Current-compensated Chokes, Scaffner, RN143-04, 33.1mmx32.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN152-04-43.0x41.8mm -Current-compensated Chokes, Scaffner, RN152-04, 43.0mmx41.8mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN202-04-8.8x18.2mm -Current-compensated Chokes, Scaffner, RN202-04, 8.8mmx18.2mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN204-04-9.0x14.0mm -Current-compensated Chokes, Scaffner, RN204-04, 9.0mmx14.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN212-04-12.5x18.0mm -Current-compensated Chokes, Scaffner, RN212-04, 12.5mmx18.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN214-04-15.5x23.0mm -Current-compensated Chokes, Scaffner, RN214-04, 15.5mmx23.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN216-04-15.5x23.0mm -Current-compensated Chokes, Scaffner, RN216-04, 15.5mmx23.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN222-04-18.0x31.0mm -Current-compensated Chokes, Scaffner, RN222-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN232-04-18.0x31.0mm -Current-compensated Chokes, Scaffner, RN232-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -Choke_Schaffner_RN242-04-18.0x31.0mm -Current-compensated Chokes, Scaffner, RN242-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ -chokes schaffner tht -0 -4 -4 -Inductor_THT -L_Axial_L5.0mm_D3.6mm_P10.00mm_Horizontal_Murata_BL01RN1A2A2 -Inductor, Murata BL01RN1A2A2, Axial, Horizontal, pin pitch=10.00mm, length*diameter=5*3.6mm, https://www.murata.com/en-global/products/productdetail?partno=BL01RN1A2A2%23 -inductor axial horizontal -0 -2 -2 -Inductor_THT -L_Axial_L5.3mm_D2.2mm_P2.54mm_Vertical_Vishay_IM-1 -Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf -Inductor Axial series Axial Vertical pin pitch 2.54mm length 5.3mm diameter 2.2mm Vishay IM-1 -0 -2 -2 -Inductor_THT -L_Axial_L5.3mm_D2.2mm_P7.62mm_Horizontal_Vishay_IM-1 -Inductor, Axial series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf -Inductor Axial series Axial Horizontal pin pitch 7.62mm length 5.3mm diameter 2.2mm Vishay IM-1 -0 -2 -2 -Inductor_THT -L_Axial_L5.3mm_D2.2mm_P10.16mm_Horizontal_Vishay_IM-1 -Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf -Inductor Axial series Axial Horizontal pin pitch 10.16mm length 5.3mm diameter 2.2mm Vishay IM-1 -0 -2 -2 -Inductor_THT -L_Axial_L6.6mm_D2.7mm_P2.54mm_Vertical_Vishay_IM-2 -Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=6.6*2.7mm^2, Vishay, IM-2, http://www.vishay.com/docs/34030/im.pdf -Inductor Axial series Axial Vertical pin pitch 2.54mm length 6.6mm diameter 2.7mm Vishay IM-2 -0 -2 -2 -Inductor_THT -L_Axial_L6.6mm_D2.7mm_P10.16mm_Horizontal_Vishay_IM-2 -Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=6.6*2.7mm^2, Vishay, IM-2, http://www.vishay.com/docs/34030/im.pdf -Inductor Axial series Axial Horizontal pin pitch 10.16mm length 6.6mm diameter 2.7mm Vishay IM-2 -0 -2 -2 -Inductor_THT -L_Axial_L7.0mm_D3.3mm_P2.54mm_Vertical_Fastron_MICC -Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 2.54mm length 7mm diameter 3.3mm Fastron MICC -0 -2 -2 -Inductor_THT -L_Axial_L7.0mm_D3.3mm_P5.08mm_Vertical_Fastron_MICC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 7mm diameter 3.3mm Fastron MICC -0 -2 -2 -Inductor_THT -L_Axial_L7.0mm_D3.3mm_P10.16mm_Horizontal_Fastron_MICC -Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 10.16mm length 7mm diameter 3.3mm Fastron MICC -0 -2 -2 -Inductor_THT -L_Axial_L7.0mm_D3.3mm_P12.70mm_Horizontal_Fastron_MICC -Inductor, Axial series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 12.7mm length 7mm diameter 3.3mm Fastron MICC -0 -2 -2 -Inductor_THT -L_Axial_L9.5mm_D4.0mm_P2.54mm_Vertical_Fastron_SMCC -Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf -Inductor Axial series Axial Vertical pin pitch 2.54mm length 9.5mm diameter 4mm Fastron SMCC -0 -2 -2 -Inductor_THT -L_Axial_L9.5mm_D4.0mm_P5.08mm_Vertical_Fastron_SMCC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 9.5mm diameter 4mm Fastron SMCC -0 -2 -2 -Inductor_THT -L_Axial_L9.5mm_D4.0mm_P12.70mm_Horizontal_Fastron_SMCC -Inductor, Axial series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf -Inductor Axial series Axial Horizontal pin pitch 12.7mm length 9.5mm diameter 4mm Fastron SMCC -0 -2 -2 -Inductor_THT -L_Axial_L9.5mm_D4.0mm_P15.24mm_Horizontal_Fastron_SMCC -Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf -Inductor Axial series Axial Horizontal pin pitch 15.24mm length 9.5mm diameter 4mm Fastron SMCC -0 -2 -2 -Inductor_THT -L_Axial_L11.0mm_D4.5mm_P5.08mm_Vertical_Fastron_MECC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 11mm diameter 4.5mm Fastron MECC -0 -2 -2 -Inductor_THT -L_Axial_L11.0mm_D4.5mm_P7.62mm_Vertical_Fastron_MECC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 11mm diameter 4.5mm Fastron MECC -0 -2 -2 -Inductor_THT -L_Axial_L11.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_MECC -Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 15.24mm length 11mm diameter 4.5mm Fastron MECC -0 -2 -2 -Inductor_THT -L_Axial_L12.0mm_D5.0mm_P5.08mm_Vertical_Fastron_MISC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 12mm diameter 5mm Fastron MISC -0 -2 -2 -Inductor_THT -L_Axial_L12.0mm_D5.0mm_P7.62mm_Vertical_Fastron_MISC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 12mm diameter 5mm Fastron MISC -0 -2 -2 -Inductor_THT -L_Axial_L12.0mm_D5.0mm_P15.24mm_Horizontal_Fastron_MISC -Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf -Inductor Axial series Axial Horizontal pin pitch 15.24mm length 12mm diameter 5mm Fastron MISC -0 -2 -2 -Inductor_THT -L_Axial_L12.8mm_D5.8mm_P5.08mm_Vertical_Fastron_HBCC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 12.8mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L12.8mm_D5.8mm_P7.62mm_Vertical_Fastron_HBCC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 12.8mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L12.8mm_D5.8mm_P20.32mm_Horizontal_Fastron_HBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 20.32mm length 12.8mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L12.8mm_D5.8mm_P25.40mm_Horizontal_Fastron_HBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 25.4mm length 12.8mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L13.0mm_D4.5mm_P5.08mm_Vertical_Fastron_HCCC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 13mm diameter 4.5mm Fastron HCCC -0 -2 -2 -Inductor_THT -L_Axial_L13.0mm_D4.5mm_P7.62mm_Vertical_Fastron_HCCC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 13mm diameter 4.5mm Fastron HCCC -0 -2 -2 -Inductor_THT -L_Axial_L13.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_HCCC -Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 15.24mm length 13mm diameter 4.5mm Fastron HCCC -0 -2 -2 -Inductor_THT -L_Axial_L14.0mm_D4.5mm_P5.08mm_Vertical_Fastron_LACC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 14mm diameter 4.5mm Fastron LACC -0 -2 -2 -Inductor_THT -L_Axial_L14.0mm_D4.5mm_P7.62mm_Vertical_Fastron_LACC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 14mm diameter 4.5mm Fastron LACC -0 -2 -2 -Inductor_THT -L_Axial_L14.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_LACC -Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 15.24mm length 14mm diameter 4.5mm Fastron LACC -0 -2 -2 -Inductor_THT -L_Axial_L14.5mm_D5.8mm_P5.08mm_Vertical_Fastron_HBCC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 14.5mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L14.5mm_D5.8mm_P7.62mm_Vertical_Fastron_HBCC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 14.5mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L14.5mm_D5.8mm_P20.32mm_Horizontal_Fastron_HBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 20.32mm length 14.5mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L14.5mm_D5.8mm_P25.40mm_Horizontal_Fastron_HBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 25.4mm length 14.5mm diameter 5.8mm Fastron HBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D6.3mm_P5.08mm_Vertical_Fastron_VHBCC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 16mm diameter 6.3mm Fastron VHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D6.3mm_P7.62mm_Vertical_Fastron_VHBCC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 16mm diameter 6.3mm Fastron VHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D6.3mm_P20.32mm_Horizontal_Fastron_VHBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 20.32mm length 16mm diameter 6.3mm Fastron VHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D6.3mm_P25.40mm_Horizontal_Fastron_VHBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 25.4mm length 16mm diameter 6.3mm Fastron VHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D7.5mm_P5.08mm_Vertical_Fastron_XHBCC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 5.08mm length 16mm diameter 7.5mm Fastron XHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D7.5mm_P7.62mm_Vertical_Fastron_XHBCC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Vertical pin pitch 7.62mm length 16mm diameter 7.5mm Fastron XHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D7.5mm_P20.32mm_Horizontal_Fastron_XHBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 20.32mm length 16mm diameter 7.5mm Fastron XHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D7.5mm_P25.40mm_Horizontal_Fastron_XHBCC -Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series -Inductor Axial series Axial Horizontal pin pitch 25.4mm length 16mm diameter 7.5mm Fastron XHBCC -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D9.5mm_P5.08mm_Vertical_Vishay_IM-10-37 -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*9.5mm^2, Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 16mm diameter 9.5mm Vishay IM-10-37 -0 -2 -2 -Inductor_THT -L_Axial_L16.0mm_D9.5mm_P20.32mm_Horizontal_Vishay_IM-10-37 -Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*9.5mm^2, Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf -Inductor Axial series Axial Horizontal pin pitch 20.32mm length 16mm diameter 9.5mm Vishay IM-10-37 -0 -2 -2 -Inductor_THT -L_Axial_L17.5mm_D12.0mm_P7.62mm_Vertical_Vishay_IM-10-46 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=17.5*12mm^2, Vishay, IM-10-46, http://www.vishay.com/docs/34030/im10.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 17.5mm diameter 12mm Vishay IM-10-46 -0 -2 -2 -Inductor_THT -L_Axial_L17.5mm_D12.0mm_P20.32mm_Horizontal_Vishay_IM-10-46 -Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=17.5*12mm^2, Vishay, IM-10-46, http://www.vishay.com/docs/34030/im10.pdf -Inductor Axial series Axial Horizontal pin pitch 20.32mm length 17.5mm diameter 12mm Vishay IM-10-46 -0 -2 -2 -Inductor_THT -L_Axial_L20.0mm_D8.0mm_P5.08mm_Vertical -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=20*8mm^2 -Inductor Axial series Axial Vertical pin pitch 5.08mm length 20mm diameter 8mm -0 -2 -2 -Inductor_THT -L_Axial_L20.0mm_D8.0mm_P7.62mm_Vertical -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20*8mm^2 -Inductor Axial series Axial Vertical pin pitch 7.62mm length 20mm diameter 8mm -0 -2 -2 -Inductor_THT -L_Axial_L20.0mm_D8.0mm_P25.40mm_Horizontal -Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=20*8mm^2 -Inductor Axial series Axial Horizontal pin pitch 25.4mm length 20mm diameter 8mm -0 -2 -2 -Inductor_THT -L_Axial_L20.3mm_D12.1mm_P7.62mm_Vertical_Vishay_IHA-101 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20.32*12.07mm^2, Vishay, IHA-101, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 20.32mm diameter 12.07mm Vishay IHA-101 -0 -2 -2 -Inductor_THT -L_Axial_L20.3mm_D12.1mm_P28.50mm_Horizontal_Vishay_IHA-101 -Inductor, Axial series, Axial, Horizontal, pin pitch=28.5mm, , length*diameter=20.32*12.07mm^2, Vishay, IHA-101, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Horizontal pin pitch 28.5mm length 20.32mm diameter 12.07mm Vishay IHA-101 -0 -2 -2 -Inductor_THT -L_Axial_L20.3mm_D12.7mm_P7.62mm_Vertical_Vishay_IHA-201 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20.32*12.7mm^2, Vishay, IHA-201, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 20.32mm diameter 12.7mm Vishay IHA-201 -0 -2 -2 -Inductor_THT -L_Axial_L20.3mm_D12.7mm_P25.40mm_Horizontal_Vishay_IHA-201 -Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=20.32*12.7mm^2, Vishay, IHA-201, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Horizontal pin pitch 25.4mm length 20.32mm diameter 12.7mm Vishay IHA-201 -0 -2 -2 -Inductor_THT -L_Axial_L23.4mm_D12.7mm_P7.62mm_Vertical_Vishay_IHA-203 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=23.37*12.7mm^2, Vishay, IHA-203, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 23.37mm diameter 12.7mm Vishay IHA-203 -0 -2 -2 -Inductor_THT -L_Axial_L23.4mm_D12.7mm_P32.00mm_Horizontal_Vishay_IHA-203 -Inductor, Axial series, Axial, Horizontal, pin pitch=32mm, , length*diameter=23.37*12.7mm^2, Vishay, IHA-203, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Horizontal pin pitch 32mm length 23.37mm diameter 12.7mm Vishay IHA-203 -0 -2 -2 -Inductor_THT -L_Axial_L24.0mm_D7.1mm_P5.08mm_Vertical_Vishay_IM-10-28 -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=24*7.1mm^2, Vishay, IM-10-28, http://www.vishay.com/docs/34035/im10.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 24mm diameter 7.1mm Vishay IM-10-28 -0 -2 -2 -Inductor_THT -L_Axial_L24.0mm_D7.1mm_P30.48mm_Horizontal_Vishay_IM-10-28 -Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=24*7.1mm^2, Vishay, IM-10-28, http://www.vishay.com/docs/34035/im10.pdf -Inductor Axial series Axial Horizontal pin pitch 30.48mm length 24mm diameter 7.1mm Vishay IM-10-28 -0 -2 -2 -Inductor_THT -L_Axial_L24.0mm_D7.5mm_P5.08mm_Vertical_Fastron_MESC -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 24mm diameter 7.5mm Fastron MESC -0 -2 -2 -Inductor_THT -L_Axial_L24.0mm_D7.5mm_P7.62mm_Vertical_Fastron_MESC -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 24mm diameter 7.5mm Fastron MESC -0 -2 -2 -Inductor_THT -L_Axial_L24.0mm_D7.5mm_P27.94mm_Horizontal_Fastron_MESC -Inductor, Axial series, Axial, Horizontal, pin pitch=27.94mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf -Inductor Axial series Axial Horizontal pin pitch 27.94mm length 24mm diameter 7.5mm Fastron MESC -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D9.0mm_P5.08mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 26mm diameter 9mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D9.0mm_P7.62mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 26mm diameter 9mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D9.0mm_P30.48mm_Horizontal_Fastron_77A -Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Horizontal pin pitch 30.48mm length 26mm diameter 9mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D10.0mm_P5.08mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 26mm diameter 10mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D10.0mm_P7.62mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 26mm diameter 10mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D10.0mm_P30.48mm_Horizontal_Fastron_77A -Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Horizontal pin pitch 30.48mm length 26mm diameter 10mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D11.0mm_P5.08mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 26mm diameter 11mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D11.0mm_P7.62mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 26mm diameter 11mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.0mm_D11.0mm_P30.48mm_Horizontal_Fastron_77A -Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Horizontal pin pitch 30.48mm length 26mm diameter 11mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L26.7mm_D12.1mm_P7.62mm_Vertical_Vishay_IHA-103 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26.67*12.07mm^2, Vishay, IHA-103, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 26.67mm diameter 12.07mm Vishay IHA-103 -0 -2 -2 -Inductor_THT -L_Axial_L26.7mm_D12.1mm_P35.00mm_Horizontal_Vishay_IHA-103 -Inductor, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=26.67*12.07mm^2, Vishay, IHA-103, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Horizontal pin pitch 35mm length 26.67mm diameter 12.07mm Vishay IHA-103 -0 -2 -2 -Inductor_THT -L_Axial_L26.7mm_D14.0mm_P7.62mm_Vertical_Vishay_IHA-104 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26.67*13.97mm^2, Vishay, IHA-104, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 26.67mm diameter 13.97mm Vishay IHA-104 -0 -2 -2 -Inductor_THT -L_Axial_L26.7mm_D14.0mm_P35.00mm_Horizontal_Vishay_IHA-104 -Inductor, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=26.67*13.97mm^2, Vishay, IHA-104, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Horizontal pin pitch 35mm length 26.67mm diameter 13.97mm Vishay IHA-104 -0 -2 -2 -Inductor_THT -L_Axial_L29.9mm_D14.0mm_P7.62mm_Vertical_Vishay_IHA-105 -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=29.85*13.97mm^2, Vishay, IHA-105, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 29.85mm diameter 13.97mm Vishay IHA-105 -0 -2 -2 -Inductor_THT -L_Axial_L29.9mm_D14.0mm_P38.00mm_Horizontal_Vishay_IHA-105 -Inductor, Axial series, Axial, Horizontal, pin pitch=38mm, , length*diameter=29.85*13.97mm^2, Vishay, IHA-105, http://www.vishay.com/docs/34014/iha.pdf -Inductor Axial series Axial Horizontal pin pitch 38mm length 29.85mm diameter 13.97mm Vishay IHA-105 -0 -2 -2 -Inductor_THT -L_Axial_L30.0mm_D8.0mm_P5.08mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 5.08mm length 30mm diameter 8mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L30.0mm_D8.0mm_P7.62mm_Vertical_Fastron_77A -Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Vertical pin pitch 7.62mm length 30mm diameter 8mm Fastron 77A -0 -2 -2 -Inductor_THT -L_Axial_L30.0mm_D8.0mm_P35.56mm_Horizontal_Fastron_77A -Inductor, Axial series, Axial, Horizontal, pin pitch=35.56mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf -Inductor Axial series Axial Horizontal pin pitch 35.56mm length 30mm diameter 8mm Fastron 77A -0 -2 -2 -Inductor_THT -L_CommonMode_Toroid_Vertical_L19.3mm_W10.8mm_Px6.35mm_Py15.24mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=6.35*15.24mm^2, , length*width=19.304*10.795mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 6.35*15.24mm^2 length 19.304mm width 10.795mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L21.0mm_W10.0mm_Px5.08mm_Py12.70mm_muRATA_5100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=5.08*12.70mm^2, , length*width=21*10mm^2, muRATA, 5100, http://www.murata-ps.com/data/magnetics/kmp_5100.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 5.08*12.70mm^2 length 21mm width 10mm muRATA 5100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L24.0mm_W16.3mm_Px10.16mm_Py20.32mm_muRATA_5200 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=10.16*20.32mm^2, , length*width=24*16.3mm^2, muRATA, 5200, http://www.murata-ps.com/data/magnetics/kmp_5200.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 10.16*20.32mm^2 length 24mm width 16.3mm muRATA 5200 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L30.5mm_W15.2mm_Px10.16mm_Py20.32mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=10.16*20.32mm^2, , length*width=30.479999999999997*15.239999999999998mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 10.16*20.32mm^2 length 30.479999999999997mm width 15.239999999999998mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L34.3mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=34.29*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 34.29mm width 20.32mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L36.8mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=36.83*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 36.83mm width 20.32mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L38.1mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=38.099999999999994*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 38.099999999999994mm width 20.32mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L39.4mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=39.37*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 39.37mm width 20.32mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L41.9mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=41.91*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 41.91mm width 20.32mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Toroid_Vertical_L43.2mm_W22.9mm_Px17.78mm_Py30.48mm_Bourns_8100 -L_CommonMode_Toroid, Vertical series, Radial, pin pitch=17.78*30.48mm^2, , length*width=43.18*22.86mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf -L_CommonMode_Toroid Vertical series Radial pin pitch 17.78*30.48mm^2 length 43.18mm width 22.86mm Bourns 8100 -0 -4 -4 -Inductor_THT -L_CommonMode_Wuerth_WE-CMB-L -Wuerth, WE-CMB, Bauform L, -CommonModeChoke Gleichtaktdrossel -0 -4 -4 -Inductor_THT -L_CommonMode_Wuerth_WE-CMB-M -Wuerth, WE-CMB, Bauform M, -CommonModeChoke Gleichtaktdrossel -0 -4 -4 -Inductor_THT -L_CommonMode_Wuerth_WE-CMB-S -Wuerth, WE-CMB, Bauform S, -CommonModeChoke Gleichtaktdrossel -0 -4 -4 -Inductor_THT -L_CommonMode_Wuerth_WE-CMB-XL -Wuerth, WE-CMB, Bauform XL, -CommonModeChoke Gleichtaktdrossel -0 -4 -4 -Inductor_THT -L_CommonMode_Wuerth_WE-CMB-XS -Wuerth, WE-CMB, Bauform XS, -CommonModeChoke Gleichtaktdrossel -0 -4 -4 -Inductor_THT -L_CommonMode_Wuerth_WE-CMB-XXL -Wuerth, WE-CMB, Bauform XXL, -CommonModeChoke Gleichtaktdrossel -0 -4 -4 -Inductor_THT -L_Mount_Lodestone_VTM120 -Lodestone Pacific, 30.48mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf -vertical inductor toroid mount -0 -4 -4 -Inductor_THT -L_Mount_Lodestone_VTM160 -Lodestone Pacific, 40.64mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf -vertical inductor toroid mount -0 -4 -4 -Inductor_THT -L_Mount_Lodestone_VTM254 -Lodestone Pacific, 64.51mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf -vertical inductor toroid mount -0 -4 -4 -Inductor_THT -L_Mount_Lodestone_VTM280 -Lodestone Pacific, 71.12mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf -vertical inductor toroid mount -0 -4 -4 -Inductor_THT -L_Mount_Lodestone_VTM950-6 -Lodestone Pacific, vertical toroid mount, 11x19mm, 6 pins, http://www.lodestonepacific.com/CatKpdf/VTM950-6.pdf -vertical inductor toroid mount -0 -6 -6 -Inductor_THT -L_Radial_D6.0mm_P4.00mm -Inductor, Radial series, Radial, pin pitch=4.00mm, , diameter=6.0mm, http://www.abracon.com/Magnetics/radial/AIUR-07.pdf -Inductor Radial series Radial pin pitch 4.00mm diameter 6.0mm -0 -2 -2 -Inductor_THT -L_Radial_D7.0mm_P3.00mm -Inductor, Radial series, Radial, pin pitch=3.00mm, , diameter=7mm, http://www.abracon.com/Magnetics/radial/AIUR-16.pdf -Inductor Radial series Radial pin pitch 3.00mm diameter 7mm -0 -2 -2 -Inductor_THT -L_Radial_D7.2mm_P3.00mm_MuRATA_1700 -Inductor, Radial series, Radial, pin pitch=3.00mm, , diameter=7.2mm, MuRATA, 1700, http://www.murata-ps.com/data/magnetics/kmp_1700.pdf -Inductor Radial series Radial pin pitch 3.00mm diameter 7.2mm MuRATA 1700 -0 -2 -2 -Inductor_THT -L_Radial_D7.5mm_P3.50mm_Fastron_07P -Inductor, Radial series, Radial, pin pitch=3.50mm, , diameter=7.5mm, Fastron, 07P, http://www.fastrongroup.com/image-show/39/07P.pdf?type=Complete-DataSheet&productType=series -Inductor Radial series Radial pin pitch 3.50mm diameter 7.5mm Fastron 07P -0 -2 -2 -Inductor_THT -L_Radial_D7.5mm_P5.00mm_Fastron_07P -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=7.5mm, Fastron, 07P, http://www.fastrongroup.com/image-show/39/07P.pdf?type=Complete-DataSheet&productType=series -Inductor Radial series Radial pin pitch 5.00mm diameter 7.5mm Fastron 07P -0 -2 -2 -Inductor_THT -L_Radial_D7.8mm_P5.00mm_Fastron_07HCP -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=7.8mm, Fastron, 07HCP, http://www.abracon.com/Magnetics/radial/AISR875.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 7.8mm Fastron 07HCP -0 -2 -2 -Inductor_THT -L_Radial_D8.7mm_P5.00mm_Fastron_07HCP -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=8.7mm, Fastron, 07HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_07HCP.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 8.7mm Fastron 07HCP -0 -2 -2 -Inductor_THT -L_Radial_D9.5mm_P5.00mm_Fastron_07HVP -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=9.5mm, Fastron, 07HVP, http://www.fastrongroup.com/image-show/107/07HVP%2007HVP_T.pdf?type=Complete-DataSheet&productType=series -Inductor Radial series Radial pin pitch 5.00mm diameter 9.5mm Fastron 07HVP -0 -2 -2 -Inductor_THT -L_Radial_D10.0mm_P5.00mm_Fastron_07M -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Fastron, 07M, http://www.fastrongroup.com/image-show/37/07M.pdf?type=Complete-DataSheet&productType=series -Inductor Radial series Radial pin pitch 5.00mm diameter 10mm Fastron 07M -0 -2 -2 -Inductor_THT -L_Radial_D10.0mm_P5.00mm_Fastron_07P -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Fastron, 07P, http://www.fastrongroup.com/image-show/37/07M.pdf?type=Complete-DataSheet&productType=series -Inductor Radial series Radial pin pitch 5.00mm diameter 10mm Fastron 07P -0 -2 -2 -Inductor_THT -L_Radial_D10.0mm_P5.00mm_Neosid_SD12_style3 -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.0mm, Neosid, SD12, style3, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 10.0mm Neosid SD12 style3 -0 -2 -2 -Inductor_THT -L_Radial_D10.0mm_P5.00mm_Neosid_SD12k_style3 -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.0mm, Neosid, SD12k, style3, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 10.0mm Neosid SD12k style3 -0 -2 -2 -Inductor_THT -L_Radial_D10.5mm_P4.00x5.00mm_Murata_1200RS -Inductor, Radial, Pitch=4.00x5.00mm, Diameter=10.5mm, Murata 1200RS, http://www.murata-ps.com/data/magnetics/kmp_1200rs.pdf -Inductor Radial Murata 1200RS -0 -4 -2 -Inductor_THT -L_Radial_D10.5mm_P5.00mm_Abacron_AISR-01 -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.5mm, Abacron, AISR-01, http://www.abracon.com/Magnetics/radial/AISR-01.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 10.5mm Abacron AISR-01 -0 -2 -2 -Inductor_THT -L_Radial_D12.0mm_P5.00mm_Fastron_11P -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Fastron, 11P, http://cdn-reichelt.de/documents/datenblatt/B400/DS_11P.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 12.0mm Fastron 11P -0 -2 -2 -Inductor_THT -L_Radial_D12.0mm_P5.00mm_Neosid_SD12_style2 -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Neosid, SD12, style2, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 12.0mm Neosid SD12 style2 -0 -2 -2 -Inductor_THT -L_Radial_D12.0mm_P5.00mm_Neosid_SD12k_style2 -Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Neosid, SD12k, style2, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf -Inductor Radial series Radial pin pitch 5.00mm diameter 12.0mm Neosid SD12k style2 -0 -2 -2 -Inductor_THT -L_Radial_D12.0mm_P6.00mm_MuRATA_1900R -Inductor, Radial series, Radial, pin pitch=6.00mm, , diameter=12.0mm, MuRATA, 1900R, http://www.murata-ps.com/data/magnetics/kmp_1900r.pdf -Inductor Radial series Radial pin pitch 6.00mm diameter 12.0mm MuRATA 1900R -0 -2 -2 -Inductor_THT -L_Radial_D12.0mm_P10.00mm_Neosid_SD12_style1 -Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=12.0mm, Neosid, SD12, style1, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf -Inductor Radial series Radial pin pitch 10.00mm diameter 12.0mm Neosid SD12 style1 -0 -2 -2 -Inductor_THT -L_Radial_D12.0mm_P10.00mm_Neosid_SD12k_style1 -Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=12.0mm, Neosid, SD12k, style1, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf -Inductor Radial series Radial pin pitch 10.00mm diameter 12.0mm Neosid SD12k style1 -0 -2 -2 -Inductor_THT -L_Radial_D12.5mm_P7.00mm_Fastron_09HCP -Inductor, Radial series, Radial, pin pitch=7.00mm, , diameter=12.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf -Inductor Radial series Radial pin pitch 7.00mm diameter 12.5mm Fastron 09HCP -0 -2 -2 -Inductor_THT -L_Radial_D12.5mm_P9.00mm_Fastron_09HCP -Inductor, Radial series, Radial, pin pitch=9.00mm, , diameter=12.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf -Inductor Radial series Radial pin pitch 9.00mm diameter 12.5mm Fastron 09HCP -0 -2 -2 -Inductor_THT -L_Radial_D13.5mm_P7.00mm_Fastron_09HCP -Inductor, Radial series, Radial, pin pitch=7.00mm, , diameter=13.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf -Inductor Radial series Radial pin pitch 7.00mm diameter 13.5mm Fastron 09HCP -0 -2 -2 -Inductor_THT -L_Radial_D14.2mm_P10.00mm_Neosid_SD14 -Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=14.2mm, Neosid, SD14, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd14.pdf -Inductor Radial series Radial pin pitch 10.00mm diameter 14.2mm Neosid SD14 -0 -2 -2 -Inductor_THT -L_Radial_D16.8mm_P11.43mm_Vishay_IHB-1 -Inductor, Radial series, Radial, pin pitch=11.43mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 11.43mm diameter 16.8mm Vishay IHB-1 -0 -2 -2 -Inductor_THT -L_Radial_D16.8mm_P12.07mm_Vishay_IHB-1 -Inductor, Radial series, Radial, pin pitch=12.07mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 12.07mm diameter 16.8mm Vishay IHB-1 -0 -2 -2 -Inductor_THT -L_Radial_D16.8mm_P12.70mm_Vishay_IHB-1 -Inductor, Radial series, Radial, pin pitch=12.70mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 12.70mm diameter 16.8mm Vishay IHB-1 -0 -2 -2 -Inductor_THT -L_Radial_D18.0mm_P10.00mm -Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=18mm, http://www.abracon.com/Magnetics/radial/AIUR-15.pdf -Inductor Radial series Radial pin pitch 10.00mm diameter 18mm -0 -2 -2 -Inductor_THT -L_Radial_D21.0mm_P14.61mm_Vishay_IHB-2 -Inductor, Radial series, Radial, pin pitch=14.61mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 14.61mm diameter 21mm Vishay IHB-2 -0 -2 -2 -Inductor_THT -L_Radial_D21.0mm_P15.00mm_Vishay_IHB-2 -Inductor, Radial series, Radial, pin pitch=15.00mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 15.00mm diameter 21mm Vishay IHB-2 -0 -2 -2 -Inductor_THT -L_Radial_D21.0mm_P15.24mm_Vishay_IHB-2 -Inductor, Radial series, Radial, pin pitch=15.24mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 15.24mm diameter 21mm Vishay IHB-2 -0 -2 -2 -Inductor_THT -L_Radial_D21.0mm_P15.75mm_Vishay_IHB-2 -Inductor, Radial series, Radial, pin pitch=15.75mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 15.75mm diameter 21mm Vishay IHB-2 -0 -2 -2 -Inductor_THT -L_Radial_D21.0mm_P19.00mm -Inductor, Radial series, Radial, pin pitch=19.00mm, , diameter=21mm, http://www.abracon.com/Magnetics/radial/AIRD02.pdf -Inductor Radial series Radial pin pitch 19.00mm diameter 21mm -0 -2 -2 -Inductor_THT -L_Radial_D24.0mm_P24.00mm -Inductor, Radial series, Radial, pin pitch=24.00mm, , diameter=24mm -Inductor Radial series Radial pin pitch 24.00mm diameter 24mm -0 -2 -2 -Inductor_THT -L_Radial_D24.4mm_P22.90mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=22.90mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 22.90mm diameter 24.4mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D24.4mm_P23.10mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=23.10mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 23.10mm diameter 24.4mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D24.4mm_P23.40mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=23.40mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 23.40mm diameter 24.4mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D24.4mm_P23.70mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=23.70mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 23.70mm diameter 24.4mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D24.4mm_P23.90mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=23.90mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 23.90mm diameter 24.4mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D27.9mm_P18.29mm_Vishay_IHB-3 -Inductor, Radial series, Radial, pin pitch=18.29mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 18.29mm diameter 27.9mm Vishay IHB-3 -0 -2 -2 -Inductor_THT -L_Radial_D27.9mm_P19.05mm_Vishay_IHB-3 -Inductor, Radial series, Radial, pin pitch=19.05mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 19.05mm diameter 27.9mm Vishay IHB-3 -0 -2 -2 -Inductor_THT -L_Radial_D27.9mm_P20.07mm_Vishay_IHB-3 -Inductor, Radial series, Radial, pin pitch=20.07mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 20.07mm diameter 27.9mm Vishay IHB-3 -0 -2 -2 -Inductor_THT -L_Radial_D28.0mm_P29.20mm -Inductor, Radial series, Radial, pin pitch=29.20mm, , diameter=28mm -Inductor Radial series Radial pin pitch 29.20mm diameter 28mm -0 -2 -2 -Inductor_THT -L_Radial_D29.8mm_P28.30mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=28.30mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 28.30mm diameter 29.8mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D29.8mm_P28.50mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=28.50mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 28.50mm diameter 29.8mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D29.8mm_P28.80mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=28.80mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 28.80mm diameter 29.8mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D29.8mm_P29.00mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=29.00mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 29.00mm diameter 29.8mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D29.8mm_P29.30mm_muRATA_1400series -Inductor, Radial series, Radial, pin pitch=29.30mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf -Inductor Radial series Radial pin pitch 29.30mm diameter 29.8mm muRATA 1400series -0 -2 -2 -Inductor_THT -L_Radial_D40.6mm_P26.16mm_Vishay_IHB-5 -Inductor, Radial series, Radial, pin pitch=26.16mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 26.16mm diameter 40.64mm Vishay IHB-5 -0 -2 -2 -Inductor_THT -L_Radial_D40.6mm_P27.18mm_Vishay_IHB-4 -Inductor, Radial series, Radial, pin pitch=27.18mm, , diameter=40.64mm, Vishay, IHB-4, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 27.18mm diameter 40.64mm Vishay IHB-4 -0 -2 -2 -Inductor_THT -L_Radial_D40.6mm_P27.94mm_Vishay_IHB-4 -Inductor, Radial series, Radial, pin pitch=27.94mm, , diameter=40.64mm, Vishay, IHB-4, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 27.94mm diameter 40.64mm Vishay IHB-4 -0 -2 -2 -Inductor_THT -L_Radial_D40.6mm_P27.94mm_Vishay_IHB-5 -Inductor, Radial series, Radial, pin pitch=27.94mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 27.94mm diameter 40.64mm Vishay IHB-5 -0 -2 -2 -Inductor_THT -L_Radial_D40.6mm_P28.70mm_Vishay_IHB-5 -Inductor, Radial series, Radial, pin pitch=28.70mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 28.70mm diameter 40.64mm Vishay IHB-5 -0 -2 -2 -Inductor_THT -L_Radial_D50.8mm_P33.27mm_Vishay_IHB-6 -Inductor, Radial series, Radial, pin pitch=33.27mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 33.27mm diameter 50.8mm Vishay IHB-6 -0 -2 -2 -Inductor_THT -L_Radial_D50.8mm_P34.29mm_Vishay_IHB-6 -Inductor, Radial series, Radial, pin pitch=34.29mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 34.29mm diameter 50.8mm Vishay IHB-6 -0 -2 -2 -Inductor_THT -L_Radial_D50.8mm_P35.81mm_Vishay_IHB-6 -Inductor, Radial series, Radial, pin pitch=35.81mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 35.81mm diameter 50.8mm Vishay IHB-6 -0 -2 -2 -Inductor_THT -L_Radial_D50.8mm_P36.32mm_Vishay_IHB-6 -Inductor, Radial series, Radial, pin pitch=36.32mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 36.32mm diameter 50.8mm Vishay IHB-6 -0 -2 -2 -Inductor_THT -L_Radial_D50.8mm_P38.86mm_Vishay_IHB-6 -Inductor, Radial series, Radial, pin pitch=38.86mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf -Inductor Radial series Radial pin pitch 38.86mm diameter 50.8mm Vishay IHB-6 -0 -2 -2 -Inductor_THT -L_Radial_L7.5mm_W4.6mm_P5.00mm_Neosid_SD75 -Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=7.5*4.6mm^2, Neosid, SD75, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd75.pdf -Inductor Radial series Radial pin pitch 5.00mm length 7.5mm width 4.6mm Neosid SD75 -0 -2 -2 -Inductor_THT -L_Radial_L8.0mm_W8.0mm_P5.00mm_Neosid_NE-CPB-07E -Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=8*8mm^2, Neosid, NE-CPB-07E, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB07E.pdf -Inductor Radial series Radial pin pitch 5.00mm length 8mm width 8mm Neosid NE-CPB-07E -0 -2 -2 -Inductor_THT -L_Radial_L8.0mm_W8.0mm_P5.00mm_Neosid_SD8 -Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=8*8mm^2, Neosid, SD8, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd8.pdf -Inductor Radial series Radial pin pitch 5.00mm length 8mm width 8mm Neosid SD8 -0 -2 -2 -Inductor_THT -L_Radial_L9.1mm_W9.1mm_Px6.35mm_Py6.35mm_Pulse_LP-25 -Inductor, Radial series, Radial, pin pitch=6.35*6.35mm^2, , length*width=9.14*9.14mm^2, Pulse, LP-25, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf -Inductor Radial series Radial pin pitch 6.35*6.35mm^2 length 9.14mm width 9.14mm Pulse LP-25 -0 -2 -2 -Inductor_THT -L_Radial_L10.2mm_W10.2mm_Px7.62mm_Py7.62mm_Pulse_LP-30 -Inductor, Radial series, Radial, pin pitch=7.62*7.62mm^2, , length*width=10.16*10.16mm^2, Pulse, LP-30, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf -Inductor Radial series Radial pin pitch 7.62*7.62mm^2 length 10.16mm width 10.16mm Pulse LP-30 -0 -2 -2 -Inductor_THT -L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.3mm -Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.3mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf -Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.3mm -0 -2 -2 -Inductor_THT -L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.5mm -Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.5mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf -Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.5mm -0 -2 -2 -Inductor_THT -L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.7mm -Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.7mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf -Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.7mm -0 -2 -2 -Inductor_THT -L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.8mm -Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.8mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf -Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.8mm -0 -2 -2 -Inductor_THT -L_Radial_L12.6mm_W12.6mm_Px9.52mm_Py9.52mm_Pulse_LP-37 -Inductor, Radial series, Radial, pin pitch=9.52*9.52mm^2, , length*width=12.57*12.57mm^2, Pulse, LP-37, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf -Inductor Radial series Radial pin pitch 9.52*9.52mm^2 length 12.57mm width 12.57mm Pulse LP-37 -0 -2 -2 -Inductor_THT -L_Radial_L16.1mm_W16.1mm_Px7.62mm_Py12.70mm_Pulse_LP-44 -Inductor, Radial series, Radial, pin pitch=7.62*12.70mm^2, , length*width=16.13*16.13mm^2, Pulse, LP-44, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf -Inductor Radial series Radial pin pitch 7.62*12.70mm^2 length 16.13mm width 16.13mm Pulse LP-44 -0 -2 -2 -Inductor_THT -L_SELF1408 -Self Ferrite 14 - 08 -SELF -0 -7 -3 -Inductor_THT -L_SELF1418 -Self Ferrite 14 - 18 -SELF -0 -10 -4 -Inductor_THT -L_Toroid_Horizontal_D3.2mm_P6.40mm_Diameter3-5mm_Amidon-T12 -L_Toroid, Horizontal series, Radial, pin pitch=6.40mm, , diameter=3.175mm, Diameter3-5mm, Amidon-T12 -L_Toroid Horizontal series Radial pin pitch 6.40mm diameter 3.175mm Diameter3-5mm Amidon-T12 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D4.1mm_P8.00mm_Diameter4-5mm_Amidon-T16 -L_Toroid, Horizontal series, Radial, pin pitch=8.00mm, , diameter=4.064mm, Diameter4-5mm, Amidon-T16 -L_Toroid Horizontal series Radial pin pitch 8.00mm diameter 4.064mm Diameter4-5mm Amidon-T16 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D5.1mm_P9.00mm_Diameter6-5mm_Amidon-T20 -L_Toroid, Horizontal series, Radial, pin pitch=9.00mm, , diameter=5.08mm, Diameter6-5mm, Amidon-T20 -L_Toroid Horizontal series Radial pin pitch 9.00mm diameter 5.08mm Diameter6-5mm Amidon-T20 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D6.5mm_P10.00mm_Diameter7-5mm_Amidon-T25 -L_Toroid, Horizontal series, Radial, pin pitch=10.00mm, , diameter=6.476999999999999mm, Diameter7-5mm, Amidon-T25 -L_Toroid Horizontal series Radial pin pitch 10.00mm diameter 6.476999999999999mm Diameter7-5mm Amidon-T25 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D7.8mm_P13.00mm_Diameter9-5mm_Amidon-T30 -L_Toroid, Horizontal series, Radial, pin pitch=13.00mm, , diameter=7.7978mm, Diameter9-5mm, Amidon-T30 -L_Toroid Horizontal series Radial pin pitch 13.00mm diameter 7.7978mm Diameter9-5mm Amidon-T30 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D9.5mm_P15.00mm_Diameter10-5mm_Amidon-T37 -L_Toroid, Horizontal series, Radial, pin pitch=15.00mm, , diameter=9.524999999999999mm, Diameter10-5mm, Amidon-T37 -L_Toroid Horizontal series Radial pin pitch 15.00mm diameter 9.524999999999999mm Diameter10-5mm Amidon-T37 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D11.2mm_P17.00mm_Diameter12-5mm_Amidon-T44 -L_Toroid, Horizontal series, Radial, pin pitch=17.00mm, , diameter=11.176mm, Diameter12-5mm, Amidon-T44 -L_Toroid Horizontal series Radial pin pitch 17.00mm diameter 11.176mm Diameter12-5mm Amidon-T44 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D12.7mm_P20.00mm_Diameter14-5mm_Amidon-T50 -L_Toroid, Horizontal series, Radial, pin pitch=20.00mm, , diameter=12.7mm, Diameter14-5mm, Amidon-T50 -L_Toroid Horizontal series Radial pin pitch 20.00mm diameter 12.7mm Diameter14-5mm Amidon-T50 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D16.8mm_P14.70mm_Vishay_TJ3 -L_Toroid, Horizontal series, Radial, pin pitch=14.70mm, , diameter=16.8mm, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 14.70mm diameter 16.8mm Vishay TJ3 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D16.8mm_P14.70mm_Vishay_TJ3_BigPads -L_Toroid, Horizontal series, Radial, pin pitch=14.70mm, , diameter=16.8mm, Vishay, TJ3, BigPads, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 14.70mm diameter 16.8mm Vishay TJ3 BigPads -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D17.3mm_P15.24mm_Bourns_2000 -L_Toroid, Horizontal series, Radial, pin pitch=15.24mm, , diameter=17.3mm, Bourns, 2000, http://www.bourns.com/docs/Product-Datasheets/2000_series.pdf?sfvrsn=5 -L_Toroid Horizontal series Radial pin pitch 15.24mm diameter 17.3mm Bourns 2000 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D21.8mm_P19.10mm_Bourns_2100 -L_Toroid, Horizontal series, Radial, pin pitch=19.10mm, , diameter=21.8mm, Bourns, 2100, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 19.10mm diameter 21.8mm Bourns 2100 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D21.8mm_P19.60mm_Bourns_2100 -L_Toroid, Horizontal series, Radial, pin pitch=19.60mm, , diameter=21.8mm, Bourns, 2100, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 19.60mm diameter 21.8mm Bourns 2100 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D22.4mm_P19.80mm_Vishay_TJ4 -L_Toroid, Horizontal series, Radial, pin pitch=19.80mm, , diameter=22.4mm, Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 19.80mm diameter 22.4mm Vishay TJ4 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D24.1mm_P21.80mm_Bourns_2200 -L_Toroid, Horizontal series, Radial, pin pitch=21.80mm, , diameter=24.1mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 21.80mm diameter 24.1mm Bourns 2200 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D24.1mm_P23.10mm_Bourns_2200 -L_Toroid, Horizontal series, Radial, pin pitch=23.10mm, , diameter=24.1mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 23.10mm diameter 24.1mm Bourns 2200 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D25.4mm_P22.90mm_Vishay_TJ5 -L_Toroid, Horizontal series, Radial, pin pitch=22.90mm, , diameter=25.4mm, Vishay, TJ5, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 22.90mm diameter 25.4mm Vishay TJ5 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D25.4mm_P22.90mm_Vishay_TJ5_BigPads -L_Toroid, Horizontal series, Radial, pin pitch=22.90mm, , diameter=25.4mm, Vishay, TJ5, BigPads, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 22.90mm diameter 25.4mm Vishay TJ5 BigPads -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D26.0mm_P5.08mm -inductor 26mm diameter toroid -SELF INDUCTOR -0 -3 -2 -Inductor_THT -L_Toroid_Horizontal_D28.0mm_P25.10mm_Bourns_2200 -L_Toroid, Horizontal series, Radial, pin pitch=25.10mm, , diameter=28mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 25.10mm diameter 28mm Bourns 2200 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D28.0mm_P26.67mm_Bourns_2200 -L_Toroid, Horizontal series, Radial, pin pitch=26.67mm, , diameter=28mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 26.67mm diameter 28mm Bourns 2200 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D32.5mm_P28.90mm_Bourns_2300 -L_Toroid, Horizontal series, Radial, pin pitch=28.90mm, , diameter=32.5mm, Bourns, 2300, http://www.bourns.com/docs/Product-Datasheets/2300_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 28.90mm diameter 32.5mm Bourns 2300 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D32.5mm_P30.00mm_Bourns_2300 -L_Toroid, Horizontal series, Radial, pin pitch=30.00mm, , diameter=32.5mm, Bourns, 2300, http://www.bourns.com/docs/Product-Datasheets/2300_series.pdf?sfvrsn=3 -L_Toroid Horizontal series Radial pin pitch 30.00mm diameter 32.5mm Bourns 2300 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D35.1mm_P31.00mm_Vishay_TJ6 -L_Toroid, Horizontal series, Radial, pin pitch=31.00mm, , diameter=35.1mm, Vishay, TJ6, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 31.00mm diameter 35.1mm Vishay TJ6 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D40.0mm_P48.26mm -L_Toroid, Horizontal series, Radial, pin pitch=48.26mm, , diameter=40mm -L_Toroid Horizontal series Radial pin pitch 48.26mm diameter 40mm -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D41.9mm_P37.60mm_Vishay_TJ7 -L_Toroid, Horizontal series, Radial, pin pitch=37.60mm, , diameter=41.9mm, Vishay, TJ7, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 37.60mm diameter 41.9mm Vishay TJ7 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D49.3mm_P44.60mm_Vishay_TJ8 -L_Toroid, Horizontal series, Radial, pin pitch=44.60mm, , diameter=49.3mm, Vishay, TJ8, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 44.60mm diameter 49.3mm Vishay TJ8 -0 -2 -2 -Inductor_THT -L_Toroid_Horizontal_D69.1mm_P63.20mm_Vishay_TJ9 -L_Toroid, Horizontal series, Radial, pin pitch=63.20mm, , diameter=69.1mm, Vishay, TJ9, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Horizontal series Radial pin pitch 63.20mm diameter 69.1mm Vishay TJ9 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L10.0mm_W5.0mm_P5.08mm -L_Toroid, Vertical series, Radial, pin pitch=5.08mm, , length*width=10*5mm^2 -L_Toroid Vertical series Radial pin pitch 5.08mm length 10mm width 5mm -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L13.0mm_W6.5mm_P5.60mm -L_Toroid, Vertical series, Radial, pin pitch=5.60mm, , length*width=13*6.5mm^2 -L_Toroid Vertical series Radial pin pitch 5.60mm length 13mm width 6.5mm -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L14.0mm_W5.6mm_P5.30mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=5.30mm, , length*width=14*5.6mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 5.30mm length 14mm width 5.6mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L14.0mm_W6.3mm_P4.57mm_Pulse_A -L_Toroid, Vertical series, Radial, pin pitch=4.57mm, , length*width=13.97*6.35mm^2, Pulse, A, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 4.57mm length 13.97mm width 6.35mm Pulse A -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L14.7mm_W8.6mm_P5.58mm_Pulse_KM-1 -L_Toroid, Vertical series, Radial, pin pitch=5.58mm, , length*width=14.73*8.64mm^2, Pulse, KM-1, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 5.58mm length 14.73mm width 8.64mm Pulse KM-1 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L16.0mm_W8.0mm_P7.62mm -L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=16*8mm^2 -L_Toroid Vertical series Radial pin pitch 7.62mm length 16mm width 8mm -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L16.3mm_W7.1mm_P7.11mm_Pulse_H -L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=16.26*7.11mm^2, Pulse, H, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 7.11mm length 16.26mm width 7.11mm Pulse H -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L16.4mm_W7.6mm_P6.60mm_Vishay_TJ3 -L_Toroid, Vertical series, Radial, pin pitch=6.60mm, , length*width=16.4*7.6mm^2, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 6.60mm length 16.4mm width 7.6mm Vishay TJ3 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L16.5mm_W11.4mm_P7.62mm_Pulse_KM-2 -L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=16.51*11.43mm^2, Pulse, KM-2, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 7.62mm length 16.51mm width 11.43mm Pulse KM-2 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L16.8mm_W9.2mm_P7.10mm_Vishay_TJ3 -L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=16.8*9.2mm^2, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 7.10mm length 16.8mm width 9.2mm Vishay TJ3 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L16.8mm_W9.2mm_P7.10mm_Vishay_TJ3_BigPads -L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=16.8*9.2mm^2, Vishay, TJ3, BigPads, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 7.10mm length 16.8mm width 9.2mm Vishay TJ3 BigPads -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L17.8mm_W8.1mm_P7.62mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=17.8*8.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 7.62mm length 17.8mm width 8.1mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L17.8mm_W9.7mm_P7.11mm_Pulse_B -L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=17.78*9.65mm^2, Pulse, B, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 7.11mm length 17.78mm width 9.65mm Pulse B -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L19.1mm_W8.1mm_P7.10mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=19.1*8.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 7.10mm length 19.1mm width 8.1mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L21.6mm_W8.4mm_P8.38mm_Pulse_G -L_Toroid, Vertical series, Radial, pin pitch=8.38mm, , length*width=21.59*8.38mm^2, Pulse, G, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 8.38mm length 21.59mm width 8.38mm Pulse G -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L21.6mm_W9.1mm_P8.40mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=8.40mm, , length*width=21.6*9.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 8.40mm length 21.6mm width 9.1mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L21.6mm_W9.5mm_P7.11mm_Pulse_C -L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=21.59*9.53mm^2, Pulse, C, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 7.11mm length 21.59mm width 9.53mm Pulse C -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L21.6mm_W11.4mm_P7.62mm_Pulse_KM-3 -L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=21.59*11.43mm^2, Pulse, KM-3, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 7.62mm length 21.59mm width 11.43mm Pulse KM-3 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L22.4mm_W10.2mm_P7.90mm_Vishay_TJ4 -L_Toroid, Vertical series, Radial, pin pitch=7.90mm, , length*width=22.4*10.2mm^2, Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 7.90mm length 22.4mm width 10.2mm Vishay TJ4 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L24.6mm_W15.5mm_P11.44mm_Pulse_KM-4 -L_Toroid, Vertical series, Radial, pin pitch=11.44mm, , length*width=24.64*15.5mm^2, Pulse, KM-4, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 11.44mm length 24.64mm width 15.5mm Pulse KM-4 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L25.4mm_W14.7mm_P12.20mm_Vishay_TJ5 -L_Toroid, Vertical series, Radial, pin pitch=12.20mm, , length*width=25.4*14.7mm^2, Vishay, TJ5, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 12.20mm length 25.4mm width 14.7mm Vishay TJ5 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L25.4mm_W14.7mm_P12.20mm_Vishay_TJ5_BigPads -L_Toroid, Vertical series, Radial, pin pitch=12.20mm, , length*width=25.4*14.7mm^2, Vishay, TJ5, BigPads, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 12.20mm length 25.4mm width 14.7mm Vishay TJ5 BigPads -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L26.7mm_W14.0mm_P10.16mm_Pulse_D -L_Toroid, Vertical series, Radial, pin pitch=10.16mm, , length*width=26.67*13.97mm^2, Pulse, D, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 10.16mm length 26.67mm width 13.97mm Pulse D -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L28.6mm_W14.3mm_P11.43mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=11.43mm, , length*width=28.6*14.3mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 11.43mm length 28.6mm width 14.3mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L31.8mm_W15.9mm_P13.50mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=13.50mm, , length*width=31.8*15.9mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 13.50mm length 31.8mm width 15.9mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L33.0mm_W17.8mm_P12.70mm_Pulse_KM-5 -L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=33.02*17.78mm^2, Pulse, KM-5, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 12.70mm length 33.02mm width 17.78mm Pulse KM-5 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L35.1mm_W21.1mm_P18.50mm_Vishay_TJ6 -L_Toroid, Vertical series, Radial, pin pitch=18.50mm, , length*width=35.1*21.1mm^2, Vishay, TJ6, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 18.50mm length 35.1mm width 21.1mm Vishay TJ6 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L35.6mm_W17.8mm_P12.70mm_Pulse_E -L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=35.56*17.78mm^2, Pulse, E, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 12.70mm length 35.56mm width 17.78mm Pulse E -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L41.9mm_W17.8mm_P12.70mm_Pulse_F -L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=41.91*17.78mm^2, Pulse, F, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf -L_Toroid Vertical series Radial pin pitch 12.70mm length 41.91mm width 17.78mm Pulse F -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L41.9mm_W19.1mm_P15.80mm_Vishay_TJ7 -L_Toroid, Vertical series, Radial, pin pitch=15.80mm, , length*width=41.9*19.1mm^2, Vishay, TJ7, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 15.80mm length 41.9mm width 19.1mm Vishay TJ7 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L46.0mm_W19.1mm_P21.80mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=21.80mm, , length*width=46*19.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 21.80mm length 46mm width 19.1mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L48.8mm_W25.4mm_P20.80mm_Vishay_TJ8 -L_Toroid, Vertical series, Radial, pin pitch=20.80mm, , length*width=48.8*25.4mm^2, Vishay, TJ8, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 20.80mm length 48.8mm width 25.4mm Vishay TJ8 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L54.0mm_W23.8mm_P20.10mm_Bourns_5700 -L_Toroid, Vertical series, Radial, pin pitch=20.10mm, , length*width=54*23.8mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf -L_Toroid Vertical series Radial pin pitch 20.10mm length 54mm width 23.8mm Bourns 5700 -0 -2 -2 -Inductor_THT -L_Toroid_Vertical_L67.6mm_W36.1mm_P31.80mm_Vishay_TJ9 -L_Toroid, Vertical series, Radial, pin pitch=31.80mm, , length*width=67.6*36.1mm^2, Vishay, TJ9, http://www.vishay.com/docs/34079/tj.pdf -L_Toroid Vertical series Radial pin pitch 31.80mm length 67.6mm width 36.1mm Vishay TJ9 -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Bridged2Bar_Pad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, bridged with 2 copper strips -solder jumper open -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Bridged2Bar_RoundedPad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, bridged with 2 copper strips -solder jumper open -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Bridged_Pad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, bridged with 1 copper strip -solder jumper open -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, bridged with 1 copper strip -solder jumper open -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Open_Pad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, open -solder jumper open -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, open -solder jumper open -0 -2 -2 -Jumper -SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open -solder jumper open -0 -2 -2 -Jumper -SolderJumper-3_P1.3mm_Bridged2Bar12_Pad1.0x1.5mm -SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged2Bar12_Pad1.0x1.5mm_NumberLabels -SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip, labeled with numbers -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged2Bar12_RoundedPad1.0x1.5mm -SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged2Bar12_RoundedPad1.0x1.5mm_NumberLabels -SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip, labeled with numbers -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged12_Pad1.0x1.5mm -SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged12_Pad1.0x1.5mm_NumberLabels -SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip, labeled with numbers -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm -SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm_NumberLabels -SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip, labeled with numbers -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm -SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, open -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm_NumberLabels -SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, open, labeled with numbers -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm -SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels -SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open, labeled with numbers -solder jumper open -0 -3 -3 -Jumper -SolderJumper-3_P2.0mm_Open_TrianglePad1.0x1.5mm -SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open -solder jumper open -0 -5 -3 -Jumper -SolderJumper-3_P2.0mm_Open_TrianglePad1.0x1.5mm_NumberLabels -SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open, labeled with numbers -solder jumper open -0 -5 -3 -LED_SMD -LED-APA102-2020 -http://www.led-color.com/upload/201604/APA102-2020%20SMD%20LED.pdf -LED RGB SPI -0 -8 -6 -LED_SMD -LED-L1T2_LUMILEDS -http://www.lumileds.com/uploads/438/DS133-pdf -LUMILEDS LUXEON TX L1T2 LED -0 -3 -3 -LED_SMD -LED_1W_3W_R8 -https://www.gme.cz/data/attachments/dsh.518-234.1.pdf -LED 1W 3W 5W -0 -3 -3 -LED_SMD -LED_0201_0603Metric -LED SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator -LED -0 -4 -2 -LED_SMD -LED_0402_1005Metric -LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED -0 -2 -2 -LED_SMD -LED_0603_1608Metric -LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_0603_1608Metric_Castellated -LED SMD 0603 (1608 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder -LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_0805_2012Metric -LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_0805_2012Metric_Castellated -LED SMD 0805 (2012 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_0805_2012Metric_Pad1.15x1.40mm_HandSolder -LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_01005_0402Metric -LED SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator -LED -0 -4 -2 -LED_SMD -LED_1206_3216Metric -LED SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_1206_3216Metric_Castellated -LED SMD 1206 (3216 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_1206_3216Metric_Pad1.42x1.75mm_HandSolder -LED SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_1206_3216Metric_ReverseMount_Hole1.8x2.4mm -LED SMD 1206 (3216 Metric), reverse mount, square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode reverse -0 -2 -2 -LED_SMD -LED_1210_3225Metric -LED SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_1210_3225Metric_Castellated -LED SMD 1210 (3225 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_1210_3225Metric_Pad1.42x2.65mm_HandSolder -LED SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_1806_4516Metric -LED SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_1806_4516Metric_Castellated -LED SMD 1806 (4516 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_1806_4516Metric_Pad1.57x1.80mm_HandSolder -LED SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_1812_4532Metric -LED SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_1812_4532Metric_Castellated -LED SMD 1812 (4532 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_1812_4532Metric_Pad1.30x3.40mm_HandSolder -LED SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_2010_5025Metric -LED SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_2010_5025Metric_Castellated -LED SMD 2010 (5025 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_2010_5025Metric_Pad1.52x2.65mm_HandSolder -LED SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_2512_6332Metric -LED SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_2512_6332Metric_Castellated -LED SMD 2512 (6332 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_2512_6332Metric_Pad1.52x3.35mm_HandSolder -LED SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_2816_7142Metric -LED SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -diode -0 -2 -2 -LED_SMD -LED_2816_7142Metric_Castellated -LED SMD 2816 (7142 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -LED castellated -0 -2 -2 -LED_SMD -LED_2816_7142Metric_Pad3.20x4.45mm_HandSolder -LED SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -LED handsolder -0 -2 -2 -LED_SMD -LED_Avago_PLCC4_3.2x2.8mm_CW -https://docs.broadcom.com/docs/AV02-4186EN -LED Avago PLCC-4 ASMB-MTB0-0A3A2 -0 -4 -4 -LED_SMD -LED_Avago_PLCC6_3x2.8mm -https://docs.broadcom.com/docs/AV02-3793EN -LED Avago PLCC-6 ASMT-YTB7-0AA02 -0 -6 -6 -LED_SMD -LED_Cree-PLCC4_2x2mm_CW -2.0mm x 2.0mm PLCC4 LED, http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/HB/Data-Sheets/CLMVBFKA.pdf -LED Cree PLCC-4 -0 -4 -4 -LED_SMD -LED_Cree-PLCC4_3.2x2.8mm_CCW -3.2mm x 2.8mm PLCC4 LED, http://www.cree.com/led-components/media/documents/CLV1AFKB(874).pdf -LED Cree PLCC-4 -0 -4 -4 -LED_SMD -LED_Cree-PLCC4_5x5mm_CW -5.0mm x 5.0mm PLCC4 LED -LED Cree PLCC-4 -0 -4 -4 -LED_SMD -LED_Cree-PLCC6_4.7x1.5mm -4.7mm x 1.5mm PLCC6 LED, http://www.cree.com/led-components/media/documents/1381-QLS6AFKW.pdf -LED Cree PLCC-6 -0 -6 -6 -LED_SMD -LED_Cree-XB -http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/XLampXBD.pdf -LED Cree XB -0 -5 -3 -LED_SMD -LED_Cree-XH -http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XHB.pdf -LED Cree XH -0 -8 -2 -LED_SMD -LED_Cree-XHP35 -http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds--XHP35.pdf -LED Cree XHP35 -0 -6 -3 -LED_SMD -LED_Cree-XHP50_6V -Cree XHP50, 6V footprint, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP50.pdf -LED Cree XHP50 -0 -17 -3 -LED_SMD -LED_Cree-XHP50_12V -Cree XHP50, 12V footprint, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP50.pdf -LED XHP50 Cree -0 -15 -3 -LED_SMD -LED_Cree-XHP70_6V -Cree XHP70 LED, 6V version, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP70.pdf -LED Cree XHP70 -0 -17 -3 -LED_SMD -LED_Cree-XHP70_12V -Cree XHP70 LED, 12V version, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP70.pdf -LED Cree XHP70 -0 -15 -3 -LED_SMD -LED_Cree-XP -LED Cree-XP http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/XLampXPE2.pdf -LED Cree XP -0 -6 -3 -LED_SMD -LED_Cree-XP-G -LED Cree-XP-G http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/XLampXPG.pdf -LED Cree XP-G -0 -6 -3 -LED_SMD -LED_Cree-XQ -LED Cree-XQ http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XQB.pdf -LED Cree XQ -0 -2 -2 -LED_SMD -LED_Cree-XQ_HandSoldering -LED Cree-XQ handsoldering pads http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XQB.pdf -LED Cree XQ -0 -2 -2 -LED_SMD -LED_Dialight_591 -LED SMD 3mm Right Angle series (http://www.dialightsignalsandcomponents.com/Assets/Drawings/2D_Drawings_DrawingDetailedSpec/C17354.pdf) -LED Dialight 591 -0 -2 -2 -LED_SMD -LED_Inolux_IN-PI554FCH_PLCC4_5.0x5.0mm_P3.2mm -http://www.inolux-corp.com/datasheet/SMDLED/Addressable%20LED/IN-PI554FCH.pdf -RGB LED NeoPixel addressable -0 -4 -4 -LED_SMD -LED_Kingbright_AAA3528ESGCT -Kingbright, dual LED, 3.5 x 2.8 mm Surface Mount LED Lamp (http://www.kingbrightusa.com/images/catalog/SPEC/AAA3528ESGCT.pdf) -dual led smd -0 -4 -4 -LED_SMD -LED_Kingbright_APFA3010_3x1.5mm_Horizontal -LED RGB, APFA3010, http://www.kingbrightusa.com/images/catalog/SPEC/APFA3010LSEEZGKQBKC.pdf -LED RGB APFA3010 KINGBRIGHT 3x1.5mm -0 -4 -4 -LED_SMD -LED_LiteOn_LTST-C19HE1WT -LiteOn RGB LED; https://optoelectronics.liteon.com/upload/download/DS22-2008-0044/LTST-C19HE1WT.pdf -LED RGB Chip SMD -0 -4 -4 -LED_SMD -LED_LiteOn_LTST-S326 -http://optoelectronics.liteon.com/upload/download/DS22-2000-287/LTST-S326KGJRKT.PDF -LED SMD right angle CCA -0 -3 -3 -LED_SMD -LED_Osram_Lx_P47F_D2mm_ReverseMount -OSRAM, reverse-mount LED, SMD, 2mm diameter, http://www.farnell.com/datasheets/2711587.pdf -LED ReverseMount Reverse -0 -4 -2 -LED_SMD -LED_PLCC-2 -LED PLCC-2 SMD package -LED PLCC-2 SMD -0 -2 -2 -LED_SMD -LED_PLCC_2835 -https://www.luckylight.cn/media/component/data-sheet/R2835BC-B2M-M10.pdf -LED -0 -2 -2 -LED_SMD -LED_PLCC_2835_Handsoldering -https://www.luckylight.cn/media/component/data-sheet/R2835BC-B2M-M10.pdf -LED -0 -2 -2 -LED_SMD -LED_RGB_1210 -RGB LED 3.2x2.7mm http://www.avagotech.com/docs/AV02-0610EN -LED 3227 -0 -4 -4 -LED_SMD -LED_RGB_5050-6 -http://cdn.sparkfun.com/datasheets/Components/LED/5060BRG4.pdf -RGB LED 5050-6 -0 -6 -6 -LED_SMD -LED_RGB_Cree-PLCC-6_6x5mm_P2.1mm -http://www.farnell.com/datasheets/2003905.pdf -LED RGB PLCC-6 CLP6C-FBK -0 -6 -6 -LED_SMD -LED_RGB_Getian_GT-P6PRGB4303 -https://www.gme.sk/img/cache/doc/518/177/vykonova-led-getian-gt-p6prgb4303-datasheet-1.pdf -LED RGB -0 -7 -7 -LED_SMD -LED_RGB_PLCC-6 -RGB LED PLCC-6 -RGB LED PLCC-6 -0 -6 -6 -LED_SMD -LED_ROHM_SMLVN6 -https://www.rohm.com/datasheet/SMLVN6RGB1U -LED ROHM SMLVN6 -0 -6 -6 -LED_SMD -LED_SK6805_PLCC4_2.4x2.7mm_P1.3mm -https://cdn-shop.adafruit.com/product-files/3484/3484_Datasheet.pdf -LED RGB NeoPixel Nano -0 -4 -4 -LED_SMD -LED_SK6812MINI_PLCC4_3.5x3.5mm_P1.75mm -https://cdn-shop.adafruit.com/product-files/2686/SK6812MINI_REV.01-1-2.pdf -LED RGB NeoPixel Mini -0 -4 -4 -LED_SMD -LED_SK6812_EC15_1.5x1.5mm -http://www.newstar-ledstrip.com/product/20181119172602110.pdf -LED RGB NeoPixel -0 -4 -4 -LED_SMD -LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm -https://cdn-shop.adafruit.com/product-files/1138/SK6812+LED+datasheet+.pdf -LED RGB NeoPixel -0 -4 -4 -LED_SMD -LED_WS2812B_PLCC4_5.0x5.0mm_P3.2mm -https://cdn-shop.adafruit.com/datasheets/WS2812B.pdf -LED RGB NeoPixel -0 -4 -4 -LED_SMD -LED_WS2812_PLCC6_5.0x5.0mm_P1.6mm -https://cdn-shop.adafruit.com/datasheets/WS2812.pdf -LED RGB NeoPixel -0 -6 -6 -LED_SMD -LED_Yuji_5730 -LED,Yuji,5730,https://cdn.shopify.com/s/files/1/0344/6401/files/YJWJ014-1.1_YJ-BC-5730L-G02.pdf -LED Yuji 5730 -0 -3 -2 -LED_SMD -LED_miniPLCC_2315 -https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DAV02-2205EN_DS_ASMT-TxBM_2014-05-09.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430858274704&ssbinary=true -LED -0 -2 -2 -LED_SMD -LED_miniPLCC_2315_Handsoldering -https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DAV02-2205EN_DS_ASMT-TxBM_2014-05-09.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430858274704&ssbinary=true -LED -0 -2 -2 -LED_THT -LED_BL-FL7680RGB -'Piranha' RGB LED, through hole, common anode, 7.62x7.62mm, BGRA pin order, https://cdn-shop.adafruit.com/datasheets/BL-FL7680RGB.pdf -RGB LED Piranha Super-Flux BetLux -0 -4 -4 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z1.6mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z4.9mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z8.2mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z1.6mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z4.9mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z8.2mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z1.6mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z4.9mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z8.2mm -LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins -LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins -0 -2 -2 -LED_THT -LED_D1.8mm_W3.3mm_H2.4mm -LED, Round, Rectangular size 3.3x2.4mm^2 diameter 1.8mm, 2 pins -LED Round Rectangular size 3.3x2.4mm^2 diameter 1.8mm 2 pins -0 -2 -2 -LED_THT -LED_D2.0mm_W4.0mm_H2.8mm_FlatTop -LED, Round, FlatTop, Rectangular size 4.0x2.8mm^2 diameter 2.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-1034IDT(Ver.9A).pdf -LED Round FlatTop Rectangular size 4.0x2.8mm^2 diameter 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D2.0mm_W4.8mm_H2.5mm_FlatTop -LED, Round, FlatTop, Rectangular size 4.8x2.5mm^2 diameter 2.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-13GD(Ver.11B).pdf -LED Round FlatTop Rectangular size 4.8x2.5mm^2 diameter 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm -LED, diameter 3.0mm, 2 pins -LED diameter 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm-3 -LED, diameter 3.0mm, 2 pins, diameter 3.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-3VSURKCGKC(Ver.8A).pdf -LED diameter 3.0mm 2 pins diameter 3.0mm 3 pins -0 -3 -3 -LED_THT -LED_D3.0mm_Clear -IR-LED, diameter 3.0mm, 2 pins, color: clear -IR infrared LED diameter 3.0mm 2 pins clear -0 -2 -2 -LED_THT -LED_D3.0mm_FlatTop -LED, Round, FlatTop, diameter 3.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-47XEC(Ver.9A).pdf -LED Round FlatTop diameter 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_Clear -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_IRBlack -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_IRGrey -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O1.27mm_Z6.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O1.27mm_Z10.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O3.81mm_Z2.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O3.81mm_Z6.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O3.81mm_Z10.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O6.35mm_Z2.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O6.35mm_Z6.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_Horizontal_O6.35mm_Z10.0mm -LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins -LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins -0 -2 -2 -LED_THT -LED_D3.0mm_IRBlack -IR-ED, diameter 3.0mm, 2 pins, color: black -IR infrared LED diameter 3.0mm 2 pins black -0 -2 -2 -LED_THT -LED_D3.0mm_IRGrey -IR-LED, diameter 3.0mm, 2 pins, color: grey -IR infrared LED diameter 3.0mm 2 pins grey -0 -2 -2 -LED_THT -LED_D4.0mm -LED, diameter 4.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-43GD(Ver.12B).pdf -LED diameter 4.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm -LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf -LED diameter 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm-3 -LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-59EGC(Ver.17A).pdf -LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins -0 -3 -3 -LED_THT -LED_D5.0mm-3_Horizontal_O3.81mm_Z3.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 3 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 3 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -3 -3 -LED_THT -LED_D5.0mm-4_RGB -LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf -LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED -0 -4 -4 -LED_THT -LED_D5.0mm-4_RGB_Staggered_Pins -LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf -LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED -0 -4 -4 -LED_THT -LED_D5.0mm-4_RGB_Wide_Pins -LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf -LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED -0 -4 -4 -LED_THT -LED_D5.0mm_Clear -LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf -LED diameter 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_FlatTop -LED, Round, FlatTop, diameter 5.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-483GDT(Ver.15B).pdf -LED Round FlatTop diameter 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_Clear -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_IRBlack -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_IRGrey -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O1.27mm_Z9.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O1.27mm_Z15.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O3.81mm_Z3.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O3.81mm_Z9.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O3.81mm_Z15.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O6.35mm_Z3.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O6.35mm_Z9.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_Horizontal_O6.35mm_Z15.0mm -LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins -LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_IRBlack -LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf -LED diameter 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_D5.0mm_IRGrey -LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf -LED diameter 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_D8.0mm -LED, diameter 8.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED8MMGE_LED8MMGN_LED8MMRT%23KIN.pdf -LED diameter 8.0mm 2 pins -0 -2 -2 -LED_THT -LED_D8.0mm-3 -LED, diameter 8.0mm, 2 pins, diameter 8.0mm, 3 pins -LED diameter 8.0mm 2 pins diameter 8.0mm 3 pins -0 -3 -3 -LED_THT -LED_D10.0mm -LED, diameter 10.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED10-4500RT%23KIN.pdf -LED diameter 10.0mm 2 pins -0 -2 -2 -LED_THT -LED_D10.0mm-3 -LED, diameter 10.0mm, 2 pins, diameter 10.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-819EGW(Ver.14A).pdf -LED diameter 10.0mm 2 pins diameter 10.0mm 3 pins -0 -3 -3 -LED_THT -LED_D20.0mm -LED, diameter 20.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/DLC2-6GD%28V6%29.pdf -LED diameter 20.0mm 2 pins -0 -2 -2 -LED_THT -LED_Oval_W5.2mm_H3.8mm -LED_Oval, Oval, Oval size 5.2x3.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-5603QBC-D(Ver.12B).pdf -LED_Oval Oval Oval size 5.2x3.8mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W3.0mm_H2.0mm -LED_Rectangular, Rectangular, Rectangular size 3.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf -LED_Rectangular Rectangular Rectangular size 3.0x2.0mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W3.9mm_H1.8mm -LED_Rectangular, Rectangular, Rectangular size 3.9x1.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-2774GD(Ver.7B).pdf -LED_Rectangular Rectangular Rectangular size 3.9x1.8mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W3.9mm_H1.8mm_FlatTop -LED_Rectangular, Rectangular, Rectangular size 3.9x1.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-2774GD(Ver.7B).pdf -LED_Rectangular Rectangular Rectangular size 3.9x1.8mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W3.9mm_H1.9mm -LED_Rectangular, Rectangular, Rectangular size 3.9x1.9mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-144GDT(Ver.14B).pdf -LED_Rectangular Rectangular Rectangular size 3.9x1.9mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm-3Pins -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 3 pins -0 -3 -3 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z1.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z3.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z5.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z1.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z3.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z5.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z1.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z3.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z5.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins -LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W5.0mm_H5.0mm -LED_Rectangular, Rectangular, Rectangular size 5.0x5.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf -LED_Rectangular Rectangular Rectangular size 5.0x5.0mm^2 2 pins -0 -2 -2 -LED_THT -LED_Rectangular_W7.62mm_H4.55mm_P5.08mm_R3 -Datasheet can be found at https://www.gme.cz/data/attachments/dsh.511-795.1.pdf -LED automotive super flux 7.62mm -0 -4 -2 -LED_THT -LED_SideEmitter_Rectangular_W4.5mm_H1.6mm -LED_SideEmitter_Rectangular, Rectangular, SideEmitter, Rectangular size 4.5x1.6mm^2, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED15MMGE_LED15MMGN%23KIN.pdf -LED_SideEmitter_Rectangular Rectangular SideEmitter Rectangular size 4.5x1.6mm^2 2 pins -0 -2 -2 -LED_THT -LED_VCCLite_5381H1_6.35x6.35mm -Red 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf -Red 5381 Series LED -0 -2 -2 -LED_THT -LED_VCCLite_5381H3_6.35x6.35mm -Amber 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf -Amber 5381 Series LED -0 -2 -2 -LED_THT -LED_VCCLite_5381H5_6.35x6.35mm -Green 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf -Green 5381 Series LED -0 -2 -2 -LED_THT -LED_VCCLite_5381H7_6.35x6.35mm -Yellow 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf -Yellow 5381 Series LED -0 -2 -2 -Module -A20_OLINUXINO_LIME2 -A20 Olinuxino LIME2, 1.2GHz, 512-1024MB RAM, Micro-SD, NAND or eMMC, 1000Mbit Ethernet -A20 Olimex Olinuxino LIME2 development board -0 -180 -180 -Module -Adafruit_HUZZAH_ESP8266_breakout -32-bit microcontroller module with WiFi, https://www.adafruit.com/product/2471 -ESP8266 WiFi microcontroller -0 -20 -20 -Module -Adafruit_HUZZAH_ESP8266_breakout_WithMountingHoles -32-bit microcontroller module with WiFi, https://www.adafruit.com/product/2471 -ESP8266 WiFi microcontroller -0 -20 -20 -Module -Arduino_Nano -Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf -Arduino Nano -0 -30 -30 -Module -Arduino_Nano_WithMountingHoles -Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf -Arduino Nano -0 -30 -30 -Module -Arduino_UNO_R2 -Arduino UNO R2, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf -Arduino UNO R2 -0 -30 -30 -Module -Arduino_UNO_R2_WithMountingHoles -Arduino UNO R2, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf -Arduino UNO R2 -0 -30 -30 -Module -Arduino_UNO_R3 -Arduino UNO R3, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf -Arduino UNO R3 -0 -32 -32 -Module -Arduino_UNO_R3_WithMountingHoles -Arduino UNO R3, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf -Arduino UNO R3 -0 -32 -32 -Module -BeagleBoard_PocketBeagle -PocketBeagle, https://github.com/beagleboard/pocketbeagle/wiki/System-Reference-Manual#71_Expansion_Header_Connectors -PocketBeagle -0 -72 -72 -Module -Maple_Mini -Maple Mini, http://docs.leaflabs.com/static.leaflabs.com/pub/leaflabs/maple-docs/0.0.12/hardware/maple-mini.html -Maple Mini -0 -40 -40 -Module -Onion_Omega2+ -https://onion.io/omega2/ -Omega Onion module -0 -32 -32 -Module -Onion_Omega2S -https://github.com/OnionIoT/Omega2/raw/master/Documents/Omega2S%20Datasheet.pdf -onion omega module -0 -89 -64 -Module -Pololu_Breakout-16_15.2x20.3mm -Pololu Breakout 16-pin 15.2x20.3mm 0.6x0.8\ -Pololu Breakout -0 -16 -16 -Module -Raspberry_Pi_Zero_Socketed_THT_FaceDown_MountingHoles -Raspberry Pi Zero using through hole straight pin socket, 2x20, 2.54mm pitch, https://www.raspberrypi.org/documentation/hardware/raspberrypi/mechanical/rpi_MECH_Zero_1p2.pdf -raspberry pi zero through hole -0 -40 -40 -Module -ST_Morpho_Connector_144_STLink -ST Morpho Connector 144 With STLink -ST Morpho Connector 144 STLink -0 -148 -148 -Module -ST_Morpho_Connector_144_STLink_MountingHoles -ST Morpho Connector 144 With STLink -ST Morpho Connector 144 STLink -0 -148 -148 -Module -WEMOS_D1_mini_light -16-pin module, column spacing 22.86 mm (900 mils), https://wiki.wemos.cc/products:d1:d1_mini, https://c1.staticflickr.com/1/734/31400410271_f278b087db_z.jpg -ESP8266 WiFi microcontroller -0 -16 -16 -MountingEquipment -DINRailAdapter_3xM3_PhoenixContact_1201578 -https://www.phoenixcontact.com/online/portal/us?uri=pxc-oc-itemdetail:pid=1201578&library=usen&tab=1 -DIN rail adapter universal three M3 clearance holes -0 -0 -0 -MountingHole -MountingHole_2.1mm -Mounting Hole 2.1mm, no annular -mounting hole 2.1mm no annular -0 -0 -0 -MountingHole -MountingHole_2.2mm_M2 -Mounting Hole 2.2mm, no annular, M2 -mounting hole 2.2mm no annular m2 -0 -0 -0 -MountingHole -MountingHole_2.2mm_M2_DIN965 -Mounting Hole 2.2mm, no annular, M2, DIN965 -mounting hole 2.2mm no annular m2 din965 -0 -0 -0 -MountingHole -MountingHole_2.2mm_M2_DIN965_Pad -Mounting Hole 2.2mm, M2, DIN965 -mounting hole 2.2mm m2 din965 -0 -1 -1 -MountingHole -MountingHole_2.2mm_M2_ISO7380 -Mounting Hole 2.2mm, no annular, M2, ISO7380 -mounting hole 2.2mm no annular m2 iso7380 -0 -0 -0 -MountingHole -MountingHole_2.2mm_M2_ISO7380_Pad -Mounting Hole 2.2mm, M2, ISO7380 -mounting hole 2.2mm m2 iso7380 -0 -1 -1 -MountingHole -MountingHole_2.2mm_M2_ISO14580 -Mounting Hole 2.2mm, no annular, M2, ISO14580 -mounting hole 2.2mm no annular m2 iso14580 -0 -0 -0 -MountingHole -MountingHole_2.2mm_M2_ISO14580_Pad -Mounting Hole 2.2mm, M2, ISO14580 -mounting hole 2.2mm m2 iso14580 -0 -1 -1 -MountingHole -MountingHole_2.2mm_M2_Pad -Mounting Hole 2.2mm, M2 -mounting hole 2.2mm m2 -0 -1 -1 -MountingHole -MountingHole_2.2mm_M2_Pad_Via -Mounting Hole 2.2mm, M2 -mounting hole 2.2mm m2 -0 -9 -1 -MountingHole -MountingHole_2.5mm -Mounting Hole 2.5mm, no annular -mounting hole 2.5mm no annular -0 -0 -0 -MountingHole -MountingHole_2.5mm_Pad -Mounting Hole 2.5mm -mounting hole 2.5mm -0 -1 -1 -MountingHole -MountingHole_2.5mm_Pad_Via -Mounting Hole 2.5mm -mounting hole 2.5mm -0 -9 -1 -MountingHole -MountingHole_2.7mm -Mounting Hole 2.7mm, no annular -mounting hole 2.7mm no annular -0 -0 -0 -MountingHole -MountingHole_2.7mm_M2.5 -Mounting Hole 2.7mm, no annular, M2.5 -mounting hole 2.7mm no annular m2.5 -0 -0 -0 -MountingHole -MountingHole_2.7mm_M2.5_DIN965 -Mounting Hole 2.7mm, no annular, M2.5, DIN965 -mounting hole 2.7mm no annular m2.5 din965 -0 -0 -0 -MountingHole -MountingHole_2.7mm_M2.5_DIN965_Pad -Mounting Hole 2.7mm, M2.5, DIN965 -mounting hole 2.7mm m2.5 din965 -0 -1 -1 -MountingHole -MountingHole_2.7mm_M2.5_ISO7380 -Mounting Hole 2.7mm, no annular, M2.5, ISO7380 -mounting hole 2.7mm no annular m2.5 iso7380 -0 -0 -0 -MountingHole -MountingHole_2.7mm_M2.5_ISO7380_Pad -Mounting Hole 2.7mm, M2.5, ISO7380 -mounting hole 2.7mm m2.5 iso7380 -0 -1 -1 -MountingHole -MountingHole_2.7mm_M2.5_ISO14580 -Mounting Hole 2.7mm, no annular, M2.5, ISO14580 -mounting hole 2.7mm no annular m2.5 iso14580 -0 -0 -0 -MountingHole -MountingHole_2.7mm_M2.5_ISO14580_Pad -Mounting Hole 2.7mm, M2.5, ISO14580 -mounting hole 2.7mm m2.5 iso14580 -0 -1 -1 -MountingHole -MountingHole_2.7mm_M2.5_Pad -Mounting Hole 2.7mm, M2.5 -mounting hole 2.7mm m2.5 -0 -1 -1 -MountingHole -MountingHole_2.7mm_M2.5_Pad_Via -Mounting Hole 2.7mm -mounting hole 2.7mm -0 -9 -1 -MountingHole -MountingHole_2.7mm_Pad -Mounting Hole 2.7mm -mounting hole 2.7mm -0 -1 -1 -MountingHole -MountingHole_2.7mm_Pad_Via -Mounting Hole 2.7mm -mounting hole 2.7mm -0 -9 -1 -MountingHole -MountingHole_2mm -Mounting Hole 2mm, no annular -mounting hole 2mm no annular -0 -0 -0 -MountingHole -MountingHole_3.2mm_M3 -Mounting Hole 3.2mm, no annular, M3 -mounting hole 3.2mm no annular m3 -0 -0 -0 -MountingHole -MountingHole_3.2mm_M3_DIN965 -Mounting Hole 3.2mm, no annular, M3, DIN965 -mounting hole 3.2mm no annular m3 din965 -0 -0 -0 -MountingHole -MountingHole_3.2mm_M3_DIN965_Pad -Mounting Hole 3.2mm, M3, DIN965 -mounting hole 3.2mm m3 din965 -0 -1 -1 -MountingHole -MountingHole_3.2mm_M3_ISO7380 -Mounting Hole 3.2mm, no annular, M3, ISO7380 -mounting hole 3.2mm no annular m3 iso7380 -0 -0 -0 -MountingHole -MountingHole_3.2mm_M3_ISO7380_Pad -Mounting Hole 3.2mm, M3, ISO7380 -mounting hole 3.2mm m3 iso7380 -0 -1 -1 -MountingHole -MountingHole_3.2mm_M3_ISO14580 -Mounting Hole 3.2mm, no annular, M3, ISO14580 -mounting hole 3.2mm no annular m3 iso14580 -0 -0 -0 -MountingHole -MountingHole_3.2mm_M3_ISO14580_Pad -Mounting Hole 3.2mm, M3, ISO14580 -mounting hole 3.2mm m3 iso14580 -0 -1 -1 -MountingHole -MountingHole_3.2mm_M3_Pad -Mounting Hole 3.2mm, M3 -mounting hole 3.2mm m3 -0 -1 -1 -MountingHole -MountingHole_3.2mm_M3_Pad_Via -Mounting Hole 3.2mm, M3 -mounting hole 3.2mm m3 -0 -9 -1 -MountingHole -MountingHole_3.5mm -Mounting Hole 3.5mm, no annular -mounting hole 3.5mm no annular -0 -0 -0 -MountingHole -MountingHole_3.5mm_Pad -Mounting Hole 3.5mm -mounting hole 3.5mm -0 -1 -1 -MountingHole -MountingHole_3.5mm_Pad_Via -Mounting Hole 3.5mm -mounting hole 3.5mm -0 -9 -1 -MountingHole -MountingHole_3.7mm -Mounting Hole 3.7mm, no annular -mounting hole 3.7mm no annular -0 -0 -0 -MountingHole -MountingHole_3.7mm_Pad -Mounting Hole 3.7mm -mounting hole 3.7mm -0 -1 -1 -MountingHole -MountingHole_3.7mm_Pad_Via -Mounting Hole 3.7mm -mounting hole 3.7mm -0 -9 -1 -MountingHole -MountingHole_3mm -Mounting Hole 3mm, no annular -mounting hole 3mm no annular -0 -0 -0 -MountingHole -MountingHole_3mm_Pad -Mounting Hole 3mm -mounting hole 3mm -0 -1 -1 -MountingHole -MountingHole_3mm_Pad_Via -Mounting Hole 3mm -mounting hole 3mm -0 -9 -1 -MountingHole -MountingHole_4.3mm_M4 -Mounting Hole 4.3mm, no annular, M4 -mounting hole 4.3mm no annular m4 -0 -0 -0 -MountingHole -MountingHole_4.3mm_M4_DIN965 -Mounting Hole 4.3mm, no annular, M4, DIN965 -mounting hole 4.3mm no annular m4 din965 -0 -0 -0 -MountingHole -MountingHole_4.3mm_M4_DIN965_Pad -Mounting Hole 4.3mm, M4, DIN965 -mounting hole 4.3mm m4 din965 -0 -1 -1 -MountingHole -MountingHole_4.3mm_M4_ISO7380 -Mounting Hole 4.3mm, no annular, M4, ISO7380 -mounting hole 4.3mm no annular m4 iso7380 -0 -0 -0 -MountingHole -MountingHole_4.3mm_M4_ISO7380_Pad -Mounting Hole 4.3mm, M4, ISO7380 -mounting hole 4.3mm m4 iso7380 -0 -1 -1 -MountingHole -MountingHole_4.3mm_M4_ISO14580 -Mounting Hole 4.3mm, no annular, M4, ISO14580 -mounting hole 4.3mm no annular m4 iso14580 -0 -0 -0 -MountingHole -MountingHole_4.3mm_M4_ISO14580_Pad -Mounting Hole 4.3mm, M4, ISO14580 -mounting hole 4.3mm m4 iso14580 -0 -1 -1 -MountingHole -MountingHole_4.3mm_M4_Pad -Mounting Hole 4.3mm, M4 -mounting hole 4.3mm m4 -0 -1 -1 -MountingHole -MountingHole_4.3mm_M4_Pad_Via -Mounting Hole 4.3mm, M4 -mounting hole 4.3mm m4 -0 -9 -1 -MountingHole -MountingHole_4.3x6.2mm_M4_Pad -Mounting Hole 4.3x6.2mm, M4 -mounting hole 4.3x6.2mm m4 -0 -1 -1 -MountingHole -MountingHole_4.3x6.2mm_M4_Pad_Via -Mounting Hole 4.3x6.2mm, M4 -mounting hole 4.3x6.2mm m4 -0 -17 -1 -MountingHole -MountingHole_4.5mm -Mounting Hole 4.5mm, no annular -mounting hole 4.5mm no annular -0 -0 -0 -MountingHole -MountingHole_4.5mm_Pad -Mounting Hole 4.5mm -mounting hole 4.5mm -0 -1 -1 -MountingHole -MountingHole_4.5mm_Pad_Via -Mounting Hole 4.5mm -mounting hole 4.5mm -0 -9 -1 -MountingHole -MountingHole_4mm -Mounting Hole 4mm, no annular -mounting hole 4mm no annular -0 -0 -0 -MountingHole -MountingHole_4mm_Pad -Mounting Hole 4mm -mounting hole 4mm -0 -1 -1 -MountingHole -MountingHole_4mm_Pad_Via -Mounting Hole 4mm -mounting hole 4mm -0 -9 -1 -MountingHole -MountingHole_5.3mm_M5 -Mounting Hole 5.3mm, no annular, M5 -mounting hole 5.3mm no annular m5 -0 -0 -0 -MountingHole -MountingHole_5.3mm_M5_DIN965 -Mounting Hole 5.3mm, no annular, M5, DIN965 -mounting hole 5.3mm no annular m5 din965 -0 -0 -0 -MountingHole -MountingHole_5.3mm_M5_DIN965_Pad -Mounting Hole 5.3mm, M5, DIN965 -mounting hole 5.3mm m5 din965 -0 -1 -1 -MountingHole -MountingHole_5.3mm_M5_ISO7380 -Mounting Hole 5.3mm, no annular, M5, ISO7380 -mounting hole 5.3mm no annular m5 iso7380 -0 -0 -0 -MountingHole -MountingHole_5.3mm_M5_ISO7380_Pad -Mounting Hole 5.3mm, M5, ISO7380 -mounting hole 5.3mm m5 iso7380 -0 -1 -1 -MountingHole -MountingHole_5.3mm_M5_ISO14580 -Mounting Hole 5.3mm, no annular, M5, ISO14580 -mounting hole 5.3mm no annular m5 iso14580 -0 -0 -0 -MountingHole -MountingHole_5.3mm_M5_ISO14580_Pad -Mounting Hole 5.3mm, M5, ISO14580 -mounting hole 5.3mm m5 iso14580 -0 -1 -1 -MountingHole -MountingHole_5.3mm_M5_Pad -Mounting Hole 5.3mm, M5 -mounting hole 5.3mm m5 -0 -1 -1 -MountingHole -MountingHole_5.3mm_M5_Pad_Via -Mounting Hole 5.3mm, M5 -mounting hole 5.3mm m5 -0 -9 -1 -MountingHole -MountingHole_5.5mm -Mounting Hole 5.5mm, no annular -mounting hole 5.5mm no annular -0 -0 -0 -MountingHole -MountingHole_5.5mm_Pad -Mounting Hole 5.5mm -mounting hole 5.5mm -0 -1 -1 -MountingHole -MountingHole_5.5mm_Pad_Via -Mounting Hole 5.5mm -mounting hole 5.5mm -0 -9 -1 -MountingHole -MountingHole_5mm -Mounting Hole 5mm, no annular -mounting hole 5mm no annular -0 -0 -0 -MountingHole -MountingHole_5mm_Pad -Mounting Hole 5mm -mounting hole 5mm -0 -1 -1 -MountingHole -MountingHole_5mm_Pad_Via -Mounting Hole 5mm -mounting hole 5mm -0 -9 -1 -MountingHole -MountingHole_6.4mm_M6 -Mounting Hole 6.4mm, no annular, M6 -mounting hole 6.4mm no annular m6 -0 -0 -0 -MountingHole -MountingHole_6.4mm_M6_DIN965 -Mounting Hole 6.4mm, no annular, M6, DIN965 -mounting hole 6.4mm no annular m6 din965 -0 -0 -0 -MountingHole -MountingHole_6.4mm_M6_DIN965_Pad -Mounting Hole 6.4mm, M6, DIN965 -mounting hole 6.4mm m6 din965 -0 -1 -1 -MountingHole -MountingHole_6.4mm_M6_ISO7380 -Mounting Hole 6.4mm, no annular, M6, ISO7380 -mounting hole 6.4mm no annular m6 iso7380 -0 -0 -0 -MountingHole -MountingHole_6.4mm_M6_ISO7380_Pad -Mounting Hole 6.4mm, M6, ISO7380 -mounting hole 6.4mm m6 iso7380 -0 -1 -1 -MountingHole -MountingHole_6.4mm_M6_ISO14580 -Mounting Hole 6.4mm, no annular, M6, ISO14580 -mounting hole 6.4mm no annular m6 iso14580 -0 -0 -0 -MountingHole -MountingHole_6.4mm_M6_ISO14580_Pad -Mounting Hole 6.4mm, M6, ISO14580 -mounting hole 6.4mm m6 iso14580 -0 -1 -1 -MountingHole -MountingHole_6.4mm_M6_Pad -Mounting Hole 6.4mm, M6 -mounting hole 6.4mm m6 -0 -1 -1 -MountingHole -MountingHole_6.4mm_M6_Pad_Via -Mounting Hole 6.4mm, M6 -mounting hole 6.4mm m6 -0 -9 -1 -MountingHole -MountingHole_6.5mm -Mounting Hole 6.5mm, no annular -mounting hole 6.5mm no annular -0 -0 -0 -MountingHole -MountingHole_6.5mm_Pad -Mounting Hole 6.5mm -mounting hole 6.5mm -0 -1 -1 -MountingHole -MountingHole_6.5mm_Pad_Via -Mounting Hole 6.5mm -mounting hole 6.5mm -0 -9 -1 -MountingHole -MountingHole_6mm -Mounting Hole 6mm, no annular -mounting hole 6mm no annular -0 -0 -0 -MountingHole -MountingHole_6mm_Pad -Mounting Hole 6mm -mounting hole 6mm -0 -1 -1 -MountingHole -MountingHole_6mm_Pad_Via -Mounting Hole 6mm -mounting hole 6mm -0 -9 -1 -MountingHole -MountingHole_8.4mm_M8 -Mounting Hole 8.4mm, no annular, M8 -mounting hole 8.4mm no annular m8 -0 -0 -0 -MountingHole -MountingHole_8.4mm_M8_Pad -Mounting Hole 8.4mm, M8 -mounting hole 8.4mm m8 -0 -1 -1 -MountingHole -MountingHole_8.4mm_M8_Pad_Via -Mounting Hole 8.4mm, M8 -mounting hole 8.4mm m8 -0 -9 -1 -NetTie -NetTie-2_SMD_Pad0.5mm -Net tie, 2 pin, 0.5mm square SMD pads -net tie -0 -2 -2 -NetTie -NetTie-2_SMD_Pad2.0mm -Net tie, 2 pin, 2.0mm square SMD pads -net tie -0 -2 -2 -NetTie -NetTie-2_THT_Pad0.3mm -Net tie, 2 pin, 0.3mm round THT pads -net tie -0 -2 -2 -NetTie -NetTie-2_THT_Pad1.0mm -Net tie, 2 pin, 1.0mm round THT pads -net tie -0 -2 -2 -NetTie -NetTie-3_SMD_Pad0.5mm -Net tie, 3 pin, 0.5mm square SMD pads -net tie -0 -3 -3 -NetTie -NetTie-3_SMD_Pad2.0mm -Net tie, 3 pin, 2.0mm square SMD pads -net tie -0 -3 -3 -NetTie -NetTie-3_THT_Pad0.3mm -Net tie, 3 pin, 0.3mm round THT pads -net tie -0 -3 -3 -NetTie -NetTie-3_THT_Pad1.0mm -Net tie, 3 pin, 1.0mm round THT pads -net tie -0 -3 -3 -NetTie -NetTie-4_SMD_Pad0.5mm -Net tie, 4 pin, 0.5mm square SMD pads -net tie -0 -4 -4 -NetTie -NetTie-4_SMD_Pad2.0mm -Net tie, 4 pin, 2.0mm square SMD pads -net tie -0 -4 -4 -NetTie -NetTie-4_THT_Pad0.3mm -Net tie, 4 pin, 0.3mm round THT pads -net tie -0 -4 -4 -NetTie -NetTie-4_THT_Pad1.0mm -Net tie, 4 pin, 1.0mm round THT pads -net tie -0 -4 -4 -OptoDevice -ADNS-9800 -Laser Gaming Sensor ADNS-9800 -MOUSE MOUSE_SENSOR LASER_GAMING_SENSOR -0 -16 -16 -OptoDevice -AGILENT_HFBR-152x -Fiberoptic Transmitter TX, HFBR series (https://docs.broadcom.com/docs/AV02-3283EN) -Fiberoptic Transmitter -0 -6 -6 -OptoDevice -AGILENT_HFBR-252x -Fiberoptic Receiver RX, HFBR series (https://docs.broadcom.com/docs/AV02-3283EN) -Fiberoptic Transmitter -0 -6 -6 -OptoDevice -AMS_TSL2550_SMD -http://ams.com/eng/content/download/250130/975613/142977 -TSL2550 ambient light sensor -0 -4 -4 -OptoDevice -Broadcom_AFBR-16xxZ_Horizontal -Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN -Fiber Optic Transmitter and Receiver -0 -6 -6 -OptoDevice -Broadcom_AFBR-16xxZ_Tilted -Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN -Fiber Optic Transmitter and Receiver -0 -6 -6 -OptoDevice -Broadcom_AFBR-16xxZ_Vertical -Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN -Fiber Optic Transmitter and Receiver -0 -6 -6 -OptoDevice -Broadcom_APDS-9301 -ambient light sensor, i2c interface, 6-pin chipled package, https://docs.broadcom.com/docs/AV02-2315EN -ambient light sensor chipled -0 -6 -6 -OptoDevice -Broadcom_DFN-6_2x2mm_P0.65mm -Broadcom DFN, 6 Pin (https://docs.broadcom.com/docs/AV02-4755EN), generated with kicad-footprint-generator ipc_noLead_generator.py -Broadcom DFN NoLead -0 -6 -6 -OptoDevice -Broadcom_LGA-8_2x2mm_P0.53mm -Broadcom LGA, 8 Pin (https://docs.broadcom.com/docs/AV02-4755EN), generated with kicad-footprint-generator ipc_noLead_generator.py -Broadcom LGA NoLead -0 -8 -8 -OptoDevice -Everlight_ITR8307 -package for Everlight ITR8307 with PCB cutout, light-direction upwards, see http://www.everlight.com/file/ProductFile/ITR8307.pdf -refective opto couple photo coupler -0 -4 -4 -OptoDevice -Everlight_ITR8307F43 -package for Everlight ITR8307/F43, see https://everlighteurope.com/index.php?controller=attachment&id_attachment=5385 -refective opto couple photo coupler -0 -4 -4 -OptoDevice -Everlight_ITR8307_Reverse -package for Everlight ITR8307 with PCB cutout, light-direction downwards, see http://www.everlight.com/file/ProductFile/ITR8307.pdf -refective opto couple photo coupler -0 -4 -4 -OptoDevice -Finder_34.81 -Relay SPST, Finder Type 34.81 (opto relays/coupler), vertical/standing form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf -Relay SPST Finder -0 -4 -4 -OptoDevice -Hamamatsu_C12880 -Hamamatsu spectrometer, see http://www.hamamatsu.com/resources/pdf/ssd/c12880ma_kacc1226e.pdf -opto spectrometer Hamamatsu -0 -10 -10 -OptoDevice -Hamamatsu_S13360-30CS -SiPM, 2pin -Hamamatsu SiPM -0 -2 -2 -OptoDevice -Kingbright_KPS-5130 -http://www.kingbright.com/attachments/file/psearch/000/00/00/KPS-5130PD7C(Ver.14).pdf -KPS-5130 photodiode RGB sensor -0 -4 -4 -OptoDevice -Kingbright_KRC011_Horizontal -Subminiature Reflective Optical Sensor, http://www.kingbright.com/attachments/file/psearch/000/00/00/KRC011(Ver.15).pdf -Subminiature Reflective Optical Sensor -0 -4 -4 -OptoDevice -Kingbright_KRC011_Vertical -Subminiature Reflective Optical Sensor, http://www.kingbright.com/attachments/file/psearch/000/00/00/KRC011(Ver.15).pdf -Subminiature Reflective Optical Sensor -0 -4 -4 -OptoDevice -Kodenshi_LG206D -http://kodenshi.co.jp/products/pdf/sensor/photointerrupter_ic/LG206D.pdf -Photointerrupter infrared LED with photo IC -0 -5 -5 -OptoDevice -Kodenshi_LG206L -http://kodenshi.co.jp/products/pdf/sensor/photointerrupter_ic/LG205L.pdf -Photointerrupter infrared LED with photo IC -0 -5 -5 -OptoDevice -Kodenshi_SG105 -package for Kodenshi SG-105 with PCB cutout, light-direction upwards, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105.pdf -refective opto couple photo coupler -0 -4 -4 -OptoDevice -Kodenshi_SG105F -package for Kodenshi SG-105F, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105F.pdf -refective opto couple photo coupler -0 -4 -4 -OptoDevice -Kodenshi_SG105_Reverse -package for Kodenshi SG-105 with PCB cutout, light-direction downwards, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105.pdf -refective opto couple photo coupler -0 -4 -4 -OptoDevice -LaserDiode_TO3.3-D3.3-3 -Laser Diode, TO-3.3mm, 3pin -Laser Diode TO3.3 -0 -3 -3 -OptoDevice -LaserDiode_TO5-D9-3 -Laser Diode, TO5-like (D=9mm), 3pin -Laser Diode TO5-like -0 -3 -3 -OptoDevice -LaserDiode_TO18-D5.6-3 -Laser Diode, TO18-like (D=5.6mm), 3pin -Laser Diode TO18-like -0 -3 -3 -OptoDevice -LaserDiode_TO38ICut-3 -Laser Diode, TO-38-ICut, 3pin -Laser Diode TO38-ICut -0 -3 -3 -OptoDevice -LaserDiode_TO56-3 -Laser Diode, TO-56, 3pin -Laser Diode TO56 -0 -3 -3 -OptoDevice -Lightpipe_LPF-C012303S -https://www.lumex.com/spec/LPF-C012303S.pdf -lightpipe dual tower right angle 3mm -0 -0 -0 -OptoDevice -Lightpipe_Mentor_1276.1004 -https://www.mentor-bauelemente.de/katalog/ll/MENTOR-LL.pdf -spherical light pipe 4 way 3mm PLCC-2 PLCC-4 -0 -0 -0 -OptoDevice -Lightpipe_Mentor_1276.2004 -https://www.mentor-bauelemente.de/katalog/ll/MENTOR-LL.pdf -planar light pipe 4 way 3mm PLCC-2 PLCC-4 -0 -0 -0 -OptoDevice -Lite-On_LTR-303ALS-01 -ambient light sensor, i2c interface, 6-pin chipled package, http://optoelectronics.liteon.com/upload/download/DS86-2013-0004/LTR-303ALS-01_DS_V1.pdf -ambient light sensor chipled -0 -6 -6 -OptoDevice -Luna_NSL-32 -Optoisolator with LED and photoresistor -optoisolator -0 -4 -4 -OptoDevice -Maxim_OLGA-14_3.3x5.6mm_P0.8mm -https://pdfserv.maximintegrated.com/land_patterns/90-0602.PDF -OLGA-14 OESIP-14 -0 -14 -14 -OptoDevice -ONSemi_QSE15x -3 Lead Plastic Package -ONSemi QSE158 QSE159 -0 -3 -3 -OptoDevice -OnSemi_CASE100CY -OnSemi CASE 100CY, light-direction upwards, see http://www.onsemi.com/pub/Collateral/QRE1113-D.PDF -refective opto couple photo coupler -0 -4 -4 -OptoDevice -Osram_BPW82 -PhotoDiode, BPW82, RM2.54 -PhotoDiode BPW82 RM2.54 -0 -2 -2 -OptoDevice -Osram_DIL2_4.3x4.65mm_P5.08mm -PhotoDiode, plastic DIL, 4.3x4.65mm², RM5.08 -PhotoDiode plastic DIL RM5.08 -0 -2 -2 -OptoDevice -Osram_LPT80A -PhotoTransistor, sidelooker package, RM2.54 -PhotoTransistor sidelooker package RM2.54 -0 -2 -2 -OptoDevice -Osram_SFH9x0x -package for Osram SFH9x0x series of reflective photo interrupters/couplers, see http://www.osram-os.com/Graphics/XPic6/00200860_0.pdf -reflective photo interrupter SMD -0 -6 -6 -OptoDevice -Osram_SFH205 -PhotoDiode, SFH205, RM2.54 -PhotoDiode SFH205 RM2.54 -0 -2 -2 -OptoDevice -Osram_SFH225 -PhotoDiode, SFH225, RM2.54 -PhotoDiode SFH225 RM2.54 -0 -2 -2 -OptoDevice -Osram_SMD-DIL2_4.5x4.0mm -PhotoDiode, plastic SMD DIL, 4.5x4mm² -PhotoDiode plastic SMD DIL -0 -2 -2 -OptoDevice -Osram_SMD-SmartDIL -PhotoDiode, plastic SMD SmatDIL -PhotoDiode plastic SMD SmatDIL -0 -3 -3 -OptoDevice -Panasonic_APV-AQY_SSOP-4_4.45x2.65mm_P1.27mm -https://www.panasonic-electric-works.com/cps/rde/xbcr/pew_eu_en/technical_information_photomos_en.pdf -SSOP4 APV21 AQY22 -0 -4 -4 -OptoDevice -PerkinElmer_VTL5C -Axial Vactrol (http://www.qsl.net/wa1ion/vactrol/vactrol.pdf) -vactrol -0 -4 -4 -OptoDevice -PerkinElmer_VTL5Cx2 -Axial Vactrol (http://www.qsl.net/wa1ion/vactrol/vactrol.pdf) -vactrol -0 -5 -5 -OptoDevice -R_LDR_4.9x4.2mm_P2.54mm_Vertical -Resistor, LDR 4.9x4.2mm -Resistor LDR4.9x4.2 -0 -2 -2 -OptoDevice -R_LDR_5.0x4.1mm_P3mm_Vertical -Resistor, LDR 5x4.1mm, see http://cdn-reichelt.de/documents/datenblatt/A500/A90xxxx%23PE.pdf -Resistor LDR5x4.1mm -0 -2 -2 -OptoDevice -R_LDR_5.1x4.3mm_P3.4mm_Vertical -Resistor, LDR 5.1x3.4mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf -Resistor LDR5.1x3.4mm -0 -2 -2 -OptoDevice -R_LDR_5.2x5.2mm_P3.5mm_Horizontal -Resistor, LDR 5.2x5.2, upright, see http://cdn-reichelt.de/documents/datenblatt/A500/M996011A.pdf -Resistor LDR5.2x5.2 -0 -2 -2 -OptoDevice -R_LDR_7x6mm_P5.1mm_Vertical -Resistor, LDR 7x6mm -Resistor LDR7x6mm -0 -2 -2 -OptoDevice -R_LDR_10x8.5mm_P7.6mm_Vertical -Resistor, LDR 10x8.5mm -Resistor LDR10.8.5mm -0 -2 -2 -OptoDevice -R_LDR_11x9.4mm_P8.2mm_Vertical -Resistor, LDR 11x9.4mm -Resistor LDR11x9.4mm -0 -2 -2 -OptoDevice -R_LDR_12x10.8mm_P9.0mm_Vertical -Resistor, LDR 12x10.8mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf -Resistor LDR12x10.8mm -0 -2 -2 -OptoDevice -R_LDR_D6.4mm_P3.4mm_Vertical -Resistor, LDR D=6.4mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf -Resistor LDRD=6.4mm -0 -2 -2 -OptoDevice -R_LDR_D13.8mm_P9.0mm_Vertical -Resistor, diameter 13.8mm pitch 9mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf -Resistor LDR -0 -2 -2 -OptoDevice -R_LDR_D20mm_P17.5mm_Vertical -Resistor, LDR 20mm diameter, pin pitch 17.5mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf -Resistor LDR -0 -2 -2 -OptoDevice -ST_VL53L0X -https://www.st.com/resource/en/datasheet/vl53l1x.pdf -laser-ranging sensor -0 -12 -12 -OptoDevice -ST_VL53L1X -https://www.st.com/resource/en/datasheet/vl53l1x.pdf -laser-ranging sensor -0 -12 -12 -OptoDevice -Sharp_GP2Y0A41SK0F -http://www.sharp-world.com/products/device/lineup/data/pdf/datasheet/gp2y0a41sk_e.pdf -Distance Sensor Sharp -0 -2 -2 -OptoDevice -Sharp_IS471F -Sharp OPIC IS471F, see http://pdf.datasheetcatalog.com/datasheet/Sharp/mXvrzty.pdf -Sharp OPIC IS471F -0 -4 -4 -OptoDevice -Sharp_IS485 -Sharp OPIC, IS485, IS486, see http://microrato.ua.pt/main/Actividades/Estagios/Docs/IS485_6.pdf -Sharp OPIC IS485 IS486 -0 -3 -3 -OptoDevice -Siemens_SFH900 -package for Siemens SFH900 reflex photo interrupter/coupler/object detector, see https://www.batronix.com/pdf/sfh900.pdf -Siemens SFH900 reflex photo interrupter coupler object detector -0 -3 -3 -OptoDevice -Toshiba_TORX170_TORX173_TORX193_TORX194 -Fiberoptic Reciver, RX, Toshiba, Toslink, TORX170, TORX173, TORX193, TORX194 -Fiberoptic Reciver RX Toshiba Toslink TORX170 TORX173 TORX193 TORX194 -0 -6 -6 -OptoDevice -Toshiba_TOTX170_TOTX173_TOTX193_TOTX194 -Fiberoptic Reciver, RX, Toshiba, Toslink, TORX170, TORX173, TORX193, TORX194 -Fiberoptic Reciver RX Toshiba Toslink TORX170 TORX173 TORX193 TORX194 -0 -6 -6 -OptoDevice -Vishay_CAST-3Pin -IR Receiver Vishay TSOP-xxxx, CAST package, see https://www.vishay.com/docs/82493/tsop311.pdf -IRReceiverVishayTSOP-xxxx CAST -0 -3 -3 -OptoDevice -Vishay_CNY70 -package for Vishay CNY70 refective photo coupler/interrupter -Vishay CNY70 refective photo coupler -0 -4 -4 -OptoDevice -Vishay_MINICAST-3Pin -IR Receiver Vishay TSOP-xxxx, MINICAST package, see https://www.vishay.com/docs/82669/tsop32s40f.pdf -IR Receiver Vishay TSOP-xxxx MINICAST -0 -3 -3 -OptoDevice -Vishay_MINIMOLD-3Pin -IR Receiver Vishay TSOP-xxxx, MINIMOLD package, see https://www.vishay.com/docs/82742/tsop331.pdf -IR Receiver Vishay TSOP-xxxx MINIMOLD -0 -3 -3 -OptoDevice -Vishay_MOLD-3Pin -IR Receiver Vishay TSOP-xxxx, MOLD package, see https://www.vishay.com/docs/82669/tsop32s40f.pdf -IR Receiver Vishay TSOP-xxxx MOLD -0 -3 -3 -Oscillator -Oscillator_DIP-8 -Oscillator, DIP8,http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf -oscillator -0 -4 -4 -Oscillator -Oscillator_DIP-8_LargePads -Oscillator, DIP8, Large Pads, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf -oscillator -0 -4 -4 -Oscillator -Oscillator_DIP-14 -Oscillator, DIP14, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf -oscillator -0 -4 -4 -Oscillator -Oscillator_DIP-14_LargePads -Oscillator, DIP14, Large Pads, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf -oscillator -0 -4 -4 -Oscillator -Oscillator_OCXO_Morion_MV267 -http://www.morion.com.ru/catalog_pdf/MV267.pdf -OCXO -0 -5 -5 -Oscillator -Oscillator_OCXO_Morion_MV317 -https://www.morion-us.com/catalog_pdf/mv317.pdf -OCXO -0 -5 -5 -Oscillator -Oscillator_SMD_Abracon_ABLNO -https://abracon.com/Precisiontiming/ABLNO.pdf -VCXO XO -0 -4 -4 -Oscillator -Oscillator_SMD_Abracon_ASCO-4Pin_1.6x1.2mm -Miniature Crystal Clock Oscillator Abracon ASCO series, https://abracon.com/Oscillators/ASCO.pdf, 1.6x1.2mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Abracon_ASDMB-4Pin_2.5x2.0mm -Miniature Crystal Clock Oscillator Abracon ASDMB series, 2.5x2.0mm package, http://www.abracon.com/Oscillators/ASDMB.pdf -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm -Miniature Crystal Clock Oscillator Abracon ASE series, http://www.abracon.com/Oscillators/ASEseries.pdf, 3.2x2.5mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm_HandSoldering -Miniature Crystal Clock Oscillator Abracon ASE series, http://www.abracon.com/Oscillators/ASEseries.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Abracon_ASV-4Pin_7.0x5.1mm -Miniature Crystal Clock Oscillator Abracon ASV series, http://www.abracon.com/Oscillators/ASV.pdf, 7.0x5.1mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Abracon_ASV-4Pin_7.0x5.1mm_HandSoldering -Miniature Crystal Clock Oscillator Abracon ASV series, http://www.abracon.com/Oscillators/ASV.pdf, hand-soldering, 7.0x5.1mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Diodes_FN-4Pin_7.0x5.0mm -FN Series Crystal Clock Oscillator (XO) (https://www.diodes.com/assets/Datasheets/FN_3-3V.pdf) -Oscillator Crystal SMD SMT -0 -4 -4 -Oscillator -Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm -Miniature Crystal Clock Oscillator ECS 2520MV series, https://www.ecsxtal.com/store/pdf/ECS-2520MV.pdf -Miniature Crystal Clock Oscillator ECS 2520MV series SMD SMT HCMOS -0 -4 -4 -Oscillator -Oscillator_SMD_EuroQuartz_XO32-4Pin_3.2x2.5mm -Miniature Crystal Clock Oscillator EuroQuartz XO32 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO32.pdf, 3.2x2.5mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_EuroQuartz_XO32-4Pin_3.2x2.5mm_HandSoldering -Miniature Crystal Clock Oscillator EuroQuartz XO32 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO32.pdf, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_EuroQuartz_XO53-4Pin_5.0x3.2mm -Miniature Crystal Clock Oscillator EuroQuartz XO53 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO53.pdf, 5.0x3.2mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_EuroQuartz_XO53-4Pin_5.0x3.2mm_HandSoldering -Miniature Crystal Clock Oscillator EuroQuartz XO53 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO53.pdf, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_EuroQuartz_XO91-4Pin_7.0x5.0mm -Miniature Crystal Clock Oscillator EuroQuartz XO91 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO91.pdf, 7.0x5.0mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_EuroQuartz_XO91-4Pin_7.0x5.0mm_HandSoldering -Miniature Crystal Clock Oscillator EuroQuartz XO91 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO91.pdf, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS1-6Pin_14.8x9.1mm -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S1-KHZ/LHZ, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 14.8x9.1mm^2 package -SMD SMT crystal oscillator -0 -6 -6 -Oscillator -Oscillator_SMD_Fordahl_DFAS2-4Pin_7.3x5.1mm -Mminiature Crystal Clock Oscillator TXCO Fordahl DFA S2-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.3x5.1mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS2-4Pin_7.3x5.1mm_HandSoldering -Mminiature Crystal Clock Oscillator TXCO Fordahl DFA S2-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.3x5.1mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS3-4Pin_9.1x7.2mm -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S3-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 9.1x7.2mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS3-4Pin_9.1x7.2mm_HandSoldering -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S3-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 9.1x7.2mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS7-4Pin_19.9x12.9mm -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S7-K/L, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 19.9x12.9mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS7-4Pin_19.9x12.9mm_HandSoldering -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S7-K/L, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 19.9x12.9mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS11-4Pin_7.0x5.0mm -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.0x5.0mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS11-4Pin_7.0x5.0mm_HandSoldering -Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS15-4Pin_5.0x3.2mm -Ultraminiature Crystal Clock Oscillator TXCO Fordahl DFA S15-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 5.0x3.2mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_Fordahl_DFAS15-4Pin_5.0x3.2mm_HandSoldering -Ultraminiature Crystal Clock Oscillator TXCO Fordahl DFA S15-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_IDT_JS6-6_5.0x3.2mm_P1.27mm -SMD Crystal Oscillator IDT https://www.idt.com/document/dst/xu-family-datasheet#page=15, 5.0x3.2mm -SMD SMT crystal oscillator -0 -6 -6 -Oscillator -Oscillator_SMD_IDT_JU6-6_7.0x5.0mm_P2.54mm -SMD Crystal Oscillator IDT https://www.idt.com/document/dst/xu-family-datasheet#page=17, 7.0x5.0mm -SMD SMT crystal oscillator -0 -6 -6 -Oscillator -Oscillator_SMD_IQD_IQXO70-4Pin_7.5x5.0mm -IQD Crystal Clock Oscillator IQXO-70, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.5x5.0mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_IQD_IQXO70-4Pin_7.5x5.0mm_HandSoldering -IQD Crystal Clock Oscillator IQXO-70, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.5x5.0mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Kyocera_2520-6Pin_2.5x2.0mm -https://global.kyocera.com/prdct/electro/product/pdf/kt2520_e.pdf -2.5mm 2mm SMD -0 -6 -6 -Oscillator -Oscillator_SMD_OCXO_ConnorWinfield_OH300 -http://www.conwin.com/datasheets/cx/cx282.pdf -OCXO -0 -7 -7 -Oscillator -Oscillator_SMD_SI570_SI571_HandSoldering -SI570, SI571, Programmable oscillator, Standard -SI570 SI571 Programmable oscillator Standard -0 -8 -8 -Oscillator -Oscillator_SMD_SI570_SI571_Standard -SI570, SI571, Programmable oscillator, Standard -SI570 SI571 Programmable oscillator Standard -0 -8 -8 -Oscillator -Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm -SMD Crystal Oscillator Seiko Epson SG-210 https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-210SED, 2.5x2.0mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm_HandSoldering -SMD Crystal Oscillator Seiko Epson SG-210 https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-210SED, hand-soldering, 2.5x2.0mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG3030CM -SMD Crystal Oscillator Seiko Epson SG-3030CM package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002CA-4Pin_7.0x5.0mm -SMD Crystal Oscillator Seiko Epson SG-8002CA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 7.0x5.0mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002CA-4Pin_7.0x5.0mm_HandSoldering -SMD Crystal Oscillator Seiko Epson SG-8002CA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 7.0x5.0mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm -SMD Crystal Oscillator Seiko Epson SG-8002CE https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 3.2x2.5mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm_HandSoldering -SMD Crystal Oscillator Seiko Epson SG-8002CE https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 3.2x2.5mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002JA-4Pin_14.0x8.7mm -SMD Crystal Oscillator Seiko Epson SG-8002JA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 14.0x8.7mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002JA-4Pin_14.0x8.7mm_HandSoldering -SMD Crystal Oscillator Seiko Epson SG-8002JA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 14.0x8.7mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002JC-4Pin_10.5x5.0mm -SMD Crystal Oscillator Seiko Epson SG-8002JC https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 10.5x5.0mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002JC-4Pin_10.5x5.0mm_HandSoldering -SMD Crystal Oscillator Seiko Epson SG-8002JC https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 10.5x5.0mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002LB-4Pin_5.0x3.2mm -SMD Crystal Oscillator Seiko Epson SG-8002LB https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 5.0x3.2mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_SeikoEpson_SG8002LB-4Pin_5.0x3.2mm_HandSoldering -SMD Crystal Oscillator Seiko Epson SG-8002LB https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SMD_Silicon_Labs_LGA-6_2.5x3.2mm_P1.25mm -Silicon_Labs LGA, 6 Pin (https://www.silabs.com/documents/public/data-sheets/si512-13.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -Silicon_Labs LGA NoLead -0 -6 -6 -Oscillator -Oscillator_SMD_TCXO_G158 -TCXO -TCXO -0 -4 -4 -Oscillator -Oscillator_SMD_TXC_7C-4Pin_5.0x3.2mm -Miniature Crystal Clock Oscillator TXC 7C series, http://www.txccorp.com/download/products/osc/7C_o.pdf, 5.0x3.2mm^2 package -SMD SMT crystal oscillator -0 -4 -4 -Oscillator -Oscillator_SMD_TXC_7C-4Pin_5.0x3.2mm_HandSoldering -Miniature Crystal Clock Oscillator TXC 7C series, http://www.txccorp.com/download/products/osc/7C_o.pdf, hand-soldering, 5.0x3.2mm^2 package -SMD SMT crystal oscillator hand-soldering -0 -4 -4 -Oscillator -Oscillator_SeikoEpson_SG-8002DB -14-lead dip package, row spacing 7.62 mm (300 mils) -DIL DIP PDIP 2.54mm 7.62mm 300mil -0 -4 -4 -Oscillator -Oscillator_SeikoEpson_SG-8002DC -8-lead dip package, row spacing 7.62 mm (300 mils) -DIL DIP PDIP 2.54mm 7.62mm 300mil -0 -4 -4 -Package_BGA -Analog_BGA-28_4.0x6.25mm_Layout4x7_P0.8mm_Ball0.45mm_Pad0.4 -Analog BGA-28 4.0mm x 6.25mm package, pitch 0.4mm pad, based on https://www.analog.com/media/en/technical-documentation/data-sheets/8063fa.pdf -BGA 28 0.8 -0 -28 -28 -Package_BGA -BGA-9_1.6x1.6mm_Layout3x3_P0.5mm -BGA-9, http://www.ti.com/lit/ds/symlink/bq27421-g1.pdf -BGA-9 -0 -9 -9 -Package_BGA -BGA-16_1.92x1.92mm_Layout4x4_P0.5mm -BGA-16, http://www.st.com/content/ccc/resource/technical/document/datasheet/group2/bc/cd/62/9e/8f/30/47/69/CD00151267/files/CD00151267.pdf/jcr:content/translations/en.CD00151267.pdf -BGA-16 -0 -16 -16 -Package_BGA -BGA-25_6.35x6.35mm_Layout5x5_P1.27mm -BGA-25, http://cds.linear.com/docs/en/datasheet/4624fc.pdf -BGA-25 uModule -0 -25 -25 -Package_BGA -BGA-36_3.396x3.466mm_Layout6x6_P0.4mm_Ball0.25mm_Pad0.2mm_NSMD -Altera V36, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00486-00.pdf -Altera BGA-36 V36 VBGA -0 -36 -36 -Package_BGA -BGA-48_8.0x9.0mm_Layout6x8_P0.8mm -BGA-48 - pitch 0.8 mm -BGA-48 -0 -48 -48 -Package_BGA -BGA-64_9.0x9.0mm_Layout10x10_P0.8mm -BGA-64, 10x10 raster, 9x9mm package, pitch 0.8mm -BGA-64 -0 -64 -64 -Package_BGA -BGA-68_5.0x5.0mm_Layout9x9_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD -Altera MBGA-68, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00344-01.pdf -Altera BGA-68 M68 MBGA -0 -68 -68 -Package_BGA -BGA-81_4.496x4.377mm_Layout9x9_P0.4mm_Ball0.25mm_Pad0.2mm_NSMD -Altera V81, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00478-01.pdf -Altera VBGA V81 BGA-81 -0 -81 -81 -Package_BGA -BGA-90_8.0x13.0mm_Layout2x3x15_P0.8mm -BGA-90, http://www.issi.com/WW/pdf/42-45S32800J.pdf -BGA-90 -0 -90 -90 -Package_BGA -BGA-96_9.0x13.0mm_Layout2x3x16_P0.8mm -BGA-96, http://www.mouser.com/ds/2/198/43-46TR16640B-81280BL-706483.pdf -BGA-96 -0 -96 -96 -Package_BGA -BGA-100_6.0x6.0mm_Layout11x11_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD -Altera MBGA-100, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00345-01.pdf -Altera BGA-100 M100 MBGA -0 -100 -100 -Package_BGA -BGA-100_11.0x11.0mm_Layout10x10_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD -BGA-100, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00223-02.pdf -BGA-100 -0 -100 -100 -Package_BGA -BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD -121-ball, 0.8mm BGA (based on http://www.latticesemi.com/view_document?document_id=213) -BGA 0.8mm 9mm 121 -0 -121 -121 -Package_BGA -BGA-121_12.0x12.0mm_Layout11x11_P1.0mm -BGA-121, http://cds.linear.com/docs/en/packaging/05081891_A_bga121.pdf -BGA-121 -0 -121 -121 -Package_BGA -BGA-132_12x18mm_Layout11x17_P0.5mm -BGA-132 11x17 12x18mm 0.5pitch -BGA-132 -0 -132 -132 -Package_BGA -BGA-144_7.0x7.0mm_Layout13x13_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD -Altera MBGA-144, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00346-00.pdf -Altera BGA-144 M144 MBGA -0 -144 -144 -Package_BGA -BGA-144_13.0x13.0mm_Layout12x12_P1.0mm -BGA-144, http://www.topline.tv/drawings/pdf/BGA%201,0mm%20pitch/LBGA144T1.0-DC128.pdf -BGA-144 -0 -144 -144 -Package_BGA -BGA-152_14x18mm_Layout13x17_P0.5mm -BGA-152_14x18mm_Layout13x17_P0.5mm -VBGA-152 -0 -152 -152 -Package_BGA -BGA-153_8.0x8.0mm_Layout15x15_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD -Altera MBGA-153, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00471-00.pdf -Altera BGA-153 M153 MBGA -0 -153 -153 -Package_BGA -BGA-169_11.0x11.0mm_Layout13x13_P0.8mm_Ball0.5mm_Pad0.4mm_NSMD -Altera U169, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00470-01.pdf -Altera UBGA U169 BGA-169 -0 -169 -169 -Package_BGA -BGA-256_11.0x11.0mm_Layout20x20_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD -Altera MBGA-256, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00348-01.pdf -Altera BGA-256 M256 MBGA -0 -256 -256 -Package_BGA -BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_Ball0.45mm_Pad0.32mm_NSMD -BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf -BGA-256 -0 -256 -256 -Package_BGA -BGA-256_17.0x17.0mm_Layout16x16_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD -BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf -BGA-256 -0 -256 -256 -Package_BGA -BGA-324_15.0x15.0mm_Layout18x18_P0.8mm_Ball0.5mm_Pad0.4mm_NSMD -Altera U324, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00474-02.pdf -Altera UBGA U324 BGA-324 -0 -324 -324 -Package_BGA -BGA-324_19.0x19.0mm_Layout18x18_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD -BGA-324, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00233-03.pdf -BGA-324 -0 -324 -324 -Package_BGA -BGA-352_35.0x35.0mm_Layout26x26_P1.27mm -BGA-352, https://www.fujitsu.com/downloads/MICRO/fma/pdfmcu/b352p05.pdf -BGA-352 -0 -352 -352 -Package_BGA -BGA-400_21.0x21.0mm_Layout20x20_P1.0mm -BGA-400, https://www.xilinx.com/support/documentation/package_specs/fg400.pdf -BGA-400 -0 -400 -400 -Package_BGA -BGA-484_23.0x23.0mm_Layout22x22_P1.0mm -BGA-484, https://www.xilinx.com/support/documentation/package_specs/fg484.pdf -BGA-484 -0 -484 -484 -Package_BGA -BGA-624_21.0x21.0mm_Layout25x25_P0.8mm -BGA-624, 25x25 grid, 21x21mm package, pitch 0.8mm; https://www.nxp.com/docs/en/package-information/SOT1529-1.pdf -BGA 624 0.8 -0 -624 -624 -Package_BGA -BGA-625_21.0x21.0mm_Layout25x25_P0.8mm -BGA-625 -BGA-625 -0 -625 -625 -Package_BGA -BGA-672_27.0x27.0mm_Layout26x26_P1.0mm_Ball0.6mm_Pad0.5mm_NSMD -Altera BGA-672, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00472-00.pdf -Altera BGA-672 F672 FBGA -0 -672 -672 -Package_BGA -BGA-676_27.0x27.0mm_Layout26x26_P1.0mm_Ball0.6mm_Pad0.5mm_NSMD -XILINX BGA-676, https://www.xilinx.com/support/documentation/package_specs/fg676.pdf -XILINX BGA-676 FG676/FGG676 -0 -676 -676 -Package_BGA -BGA-1023_33.0x33.0mm_Layout32x32_P1.0mm -BGA-1023 -BGA-1023 -0 -1023 -1023 -Package_BGA -BGA-1156_35.0x35.0mm_Layout34x34_P1.0mm -BGA-1156 -BGA-1156 -0 -1156 -1156 -Package_BGA -BGA-1295_37.5x37.5mm_Layout36x36_P1.0mm -BGA-1295 -BGA-1295 -0 -1295 -1295 -Package_BGA -FB-BGA-484_23.0x23.0mm_Layout22x22_P1.0mm -Xilinx FB-484, https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf -FB-BGA-484 -0 -484 -484 -Package_BGA -FBGA-78_7.5x11mm_Layout2x3x13_P0.8mm -FBGA-78, https://www.skhynix.com/product/filedata/fileDownload.do?seq=7687 -FBGA-78 -0 -78 -78 -Package_BGA -Fujitsu_WLP-15_2.28x3.092mm_Layout3x5_P0.4mm -WLP-15, 3x5 raster, 2.28x3.092mm package, pitch 0.4mm; http://www.fujitsu.com/global/documents/products/devices/semiconductor/fram/lineup/MB85RS1MT-DS501-00022-7v0-E.pdf -BGA 8 0.4 -0 -8 -8 -Package_BGA -LFBGA-100_10x10mm_Layout10x10_P0.8mm -LFBGA-100, 10x10 raster, 10x10mm package, pitch 0.8mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf -BGA 100 0.8 -0 -100 -100 -Package_BGA -LFBGA-144_10x10mm_Layout12x12_P0.8mm -LFBGA-144, 12x12 raster, 10x10mm package, pitch 0.8mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf -BGA 144 0.8 -0 -144 -144 -Package_BGA -LFBGA-169_16x12mm_Layout28x14_P0.5mm_Ball0.3_Pad0.3mm_NSMD -https://4donline.ihs.com/images/VipMasterIC/IC/SGST/SGSTS20279/SGSTS20279-1.pdf?hkey=EF798316E3902B6ED9A73243A3159BB0 -eMMC Flash LFBGA169 -0 -169 -169 -Package_BGA -Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD -Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213 -BGA 381 0.8 -0 -381 -381 -Package_BGA -Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.6mm_SMD -Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213 -BGA 381 0.8 -0 -381 -381 -Package_BGA -Linear_BGA-133_15.0x15.0_Layout12x12_P1.27mm -Analog Devices (Linear Tech), 133-pin BGA uModule, 15.0x15.0x4.92mm, https://www.analog.com/media/en/technical-documentation/data-sheets/4637fc.pdf -133 pin bga -0 -134 -134 -Package_BGA -Maxim_WLP-12 -Maxim_WLP-12 W121B2+1 http://pdfserv.maximintegrated.com/package_dwgs/21-0009.PDF -Maxim_WLP-12 -0 -12 -12 -Package_BGA -TFBGA-64_5x5mm_Layout8x8_P0.5mm -TFBGA-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f100v8.pdf -BGA 64 0.5 -0 -64 -64 -Package_BGA -TFBGA-100_8x8mm_Layout10x10_P0.8mm -TFBGA-100, 10x10 raster, 8x8mm package, pitch 0.8mm; see section 6.2 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf -BGA 100 0.8 -0 -100 -100 -Package_BGA -TFBGA-100_9.0x9.0mm_Layout10x10_P0.8mm -TFBGA-100, 10x10, 9x9mm package, pitch 0.8mm -TFBGA-100 -0 -100 -100 -Package_BGA -TFBGA-121_10x10mm_Layout11x11_P0.8mm -TFBGA-121, 11x11 raster, 10x10mm package, pitch 0.8mm; http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#p495 -BGA 121 0.8 -0 -121 -121 -Package_BGA -TFBGA-216_13x13mm_Layout15x15_P0.8mm -TFBGA-216, 15x15 raster, 13x13mm package, pitch 0.8mm; see section 6.8 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf -BGA 216 0.8 -0 -216 -216 -Package_BGA -TFBGA-265_14x14mm_Layout17x17_P0.8mm -TFBGA-265, 17x17 raster, 14x14mm package, pitch 0.8mm; see section 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf -BGA 265 0.8 -0 -265 -265 -Package_BGA -Texas_DSBGA-5_0.822x1.116mm_Layout2x1x2_P0.4mm -Texas Instruments, DSBGA, 0.822x1.116mm, 5 bump 2x1x2 array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/opa330.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -Texas Instruments DSBGA BGA YFF S-XBGA-N5 -0 -10 -5 -Package_BGA -Texas_DSBGA-6_0.9x1.4mm_Layout2x3_P0.5mm -Texas Instruments, DSBGA, 0.9x1.4mm, 6 bump 2x3 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/ts5a3159a.pdf) -Texas Instruments DSBGA BGA YZP R-XBGA-N6 -0 -12 -6 -Package_BGA -Texas_DSBGA-8_0.9x1.9mm_Layout2x4_P0.5mm -Texas Instruments, DSBGA, 0.9x1.9mm, 8 bump 2x4 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0102.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -Texas Instruments DSBGA BGA YZP R-XBGA-N8 -0 -16 -8 -Package_BGA -Texas_DSBGA-8_1.43x1.41mm_Layout3x3_P0.5mm -Texas Instruments, DSBGA, 1.43x1.41mm, 8 bump 3x3 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lmc555.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -Texas Instruments DSBGA BGA YZP R-XBGA-N8 -0 -16 -8 -Package_BGA -Texas_DSBGA-8_1.5195x1.5195mm_Layout3x3_P0.5mm -Texas Instruments, DSBGA, 1.5195x1.5195x0.600mm, 8 ball 3x3 area grid, YZR pad definition (http://www.ti.com/lit/ml/mxbg270/mxbg270.pdf) -BGA 8 0.5 -0 -8 -8 -Package_BGA -Texas_DSBGA-9_1.4715x1.4715mm_Layout3x3_P0.5mm -Texas Instruments, DSBGA, 1.4715x1.4715mm, 9 bump 3x3 array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lm4990.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -Texas Instruments DSBGA BGA YZR0009 -0 -18 -9 -Package_BGA -Texas_DSBGA-10_1.36x1.86mm_Layout3x4_P0.5mm -Texas Instruments, DSBGA, 1.36x1.86mm, 10 bump 3x4 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -Texas Instruments DSBGA BGA -0 -20 -10 -Package_BGA -Texas_DSBGA-12_1.36x1.86mm_Layout3x4_P0.5mm -Texas Instruments, DSBGA, 1.36x1.86mm, 12 bump 3x4 (area) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -Texas Instruments DSBGA BGA -0 -24 -12 -Package_BGA -Texas_DSBGA-28_1.9x3.0mm_Layout4x7_P0.4mm -Texas Instruments, DSBGA, 3.0x1.9x0.625mm, 28 ball 7x4 area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/bq51050b.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -BGA 28 0.4 -0 -28 -28 -Package_BGA -Texas_DSBGA-49_3.33x3.488mm_Layout7x7_P0.4mm -Texas Instruments, DSBGA, 3.33x3.488x0.625mm, 49 ball 7x7 area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/msp430f2234.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -texas dsbga 49 -0 -49 -49 -Package_BGA -Texas_DSBGA-64_3.415x3.535mm_Layout8x8_P0.4mm -Texas Instruments, DSBGA, 3.415x3.535x0.625mm, 64 ball 8x8 area grid, NSMD pad definition (http://www.ti.com/lit/ds/slas718g/slas718g.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) -texas dsbga 64 -0 -64 -64 -Package_BGA -Texas_MicroStar_Junior_BGA-12_2.0x2.5mm_Layout4x3_P0.5mm -Texas Instruments, BGA Microstar Junior, 2x2.5mm, 12 bump 4x3 grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf) -Texas_Junior_BGA-12 -0 -12 -12 -Package_BGA -Texas_MicroStar_Junior_BGA-80_5.0x5.0mm_Layout9x9_P0.5mm -Texas Instruments, BGA Microstar Junior, 5x5mm, 80 ball 9x9 grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/tlv320aic23b.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf) -Texas_Junior_BGA-80 -0 -80 -80 -Package_BGA -Texas_MicroStar_Junior_BGA-113_7.0x7.0mm_Layout12x12_P0.5mm -Texas Instruments, BGA Microstar Junior, 7x7mm, 113 ball 12x12 grid, NSMD pad definition (http://www.ti.com/lit/ml/mpbg674/mpbg674.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf) -Texas_Junior_BGA-113 -0 -113 -113 -Package_BGA -UCBGA-36_2.5x2.5mm_Layout6x6_P0.4mm -UCBGA-36, 6x6 raster, 2.5x2.5mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 -BGA 36 0.4 -0 -36 -36 -Package_BGA -UCBGA-49_3x3mm_Layout7x7_P0.4mm -UCBGA-49, 7x7 raster, 3x3mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 -BGA 49 0.4 -0 -49 -49 -Package_BGA -UCBGA-81_4x4mm_Layout9x9_P0.4mm -UCBGA-81, 9x9 raster, 4x4mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 -BGA 81 0.4 -0 -81 -81 -Package_BGA -UFBGA-15_3.0x3.0mm_Layout4x4_P0.65mm -UFBGA-15, 4x4, 3x3mm package, pitch 0.65mm -UFBGA-15 -0 -15 -15 -Package_BGA -UFBGA-32_4.0x4.0mm_Layout6x6_P0.5mm -UFBGA-32, 6x6, 4x4mm package, pitch 0.5mm -UFBGA-32 -0 -32 -32 -Package_BGA -UFBGA-64_5x5mm_Layout8x8_P0.5mm -UFBGA-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf -BGA 64 0.5 -0 -64 -64 -Package_BGA -UFBGA-100_7x7mm_Layout12x12_P0.5mm -UFBGA-100, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf -BGA 100 0.5 -0 -100 -100 -Package_BGA -UFBGA-132_7x7mm_Layout12x12_P0.5mm -UFBGA-132, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf -BGA 132 0.5 -0 -132 -132 -Package_BGA -UFBGA-132_7x7mm_P0.5mm -UFBGA 132 Pins, 0.5mm Pitch, 0.3mm Ball, http://www.st.com/resource/en/datasheet/stm32l486qg.pdf -ufbga bga small-pitch -0 -132 -132 -Package_BGA -UFBGA-144_7x7mm_Layout12x12_P0.5mm -UFBGA-144, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf -BGA 144 0.5 -0 -144 -144 -Package_BGA -UFBGA-144_10x10mm_Layout12x12_P0.8mm -UFBGA-144, 12x12 raster, 10x10mm package, pitch 0.8mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf -BGA 144 0.8 -0 -144 -144 -Package_BGA -UFBGA-169_7x7mm_Layout13x13_P0.5mm -UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf -BGA 169 0.5 -0 -169 -169 -Package_BGA -UFBGA-201_10x10mm_Layout15x15_P0.65mm -UFBGA-201, 15x15 raster, 10x10mm package, pitch 0.65mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf -BGA 201 0.65 -0 -201 -201 -Package_BGA -VFBGA-49_5.0x5.0mm_Layout7x7_P0.65mm -VFBGA-49, 7x7, 5x5mm package, pitch 0.65mm -VFBGA-49 -0 -49 -49 -Package_BGA -VFBGA-100_7.0x7.0mm_Layout10x10_P0.65mm -VFBGA-100, 10x10, 7x7mm package, pitch 0.65mm -VFBGA-100 -0 -100 -100 -Package_BGA -WLP-4_0.73x0.73mm_Layout2x2_P0.35mm_Ball0.22mm_Pad0.2mm_NSMD -WLP-4, 2x2 raster, 0.73x0.73mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf -BGA 4 0.35 -0 -4 -4 -Package_BGA -WLP-4_0.83x0.83mm_P0.4mm -WLP-4_0.83x0.83mm_P0.4mm https://pdfserv.maximintegrated.com/package_dwgs/21-100107.PDF, https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891 -WLP-4 -0 -4 -4 -Package_BGA -WLP-4_0.86x0.86mm_P0.4mm -WLP-4_0.86x0.86mm_P0.4mm https://pdfserv.maximintegrated.com/package_dwgs/21-0612.PDF, https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891 -WLP-4 -0 -4 -4 -Package_BGA -XBGA-121_10x10mm_Layout11x11_P0.8mm -XBGA-121, 11x11 raster, 10x10mm package, pitch 0.6mm; http://ww1.microchip.com/downloads/en/DeviceDoc/39969b.pdf -BGA 121 0.8 -0 -121 -121 -Package_BGA -XFBGA-36_3.5x3.5mm_Layout6x6_P0.5mm -XFBGA-36, https://www.nxp.com/docs/en/package-information/SOT1555-1.pdf -XFBGA-36 -0 -36 -36 -Package_BGA -XFBGA-64_5.0x5.0mm_Layout8x8_P0.5mm -XFBGA-64, https://www.nxp.com/docs/en/package-information/SOT1555-1.pdf -XFBGA-64 -0 -64 -64 -Package_BGA -XFBGA-121_8x8mm_Layout11x11_P0.65mm -XFBGA-121, https://www.nxp.com/docs/en/package-information/SOT1533-1.pdf -XFBGA-121 -0 -121 -121 -Package_BGA -Xilinx_CLG225 -Zynq-7000 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=77, NSMD pad definition Appendix A -BGA 225 0.8 CLG225 -0 -225 -225 -Package_BGA -Xilinx_CLG400 -Zynq-7000 BGA, 20x20 grid, 17x17mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=78, NSMD pad definition Appendix A -BGA 400 0.8 CLG400 CL400 -0 -400 -400 -Package_BGA -Xilinx_CLG484_CLG485 -Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=79, NSMD pad definition Appendix A -BGA 484 0.8 CLG484 CL484 CLG485 CL485 -0 -484 -484 -Package_BGA -Xilinx_CPG236 -Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=266, NSMD pad definition Appendix A -BGA 238 0.5 CP236 CPG236 -0 -238 -238 -Package_BGA -Xilinx_CPG238 -Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=267, NSMD pad definition Appendix A -BGA 238 0.5 CPG238 -0 -238 -238 -Package_BGA -Xilinx_CPGA196 -Spartan-7 BGA, 14x14 grid, 8x8mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=260, NSMD pad definition Appendix A -BGA 196 0.5 CPGA196 -0 -196 -196 -Package_BGA -Xilinx_CSG324 -Artix-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A -BGA 324 0.8 CS324 CSG324 -0 -324 -324 -Package_BGA -Xilinx_CSG325 -Artix-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A -BGA 324 0.8 CS325 CSG235 -0 -324 -324 -Package_BGA -Xilinx_CSGA225 -Spartan-7 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=262, NSMD pad definition Appendix A -BGA 225 0.8 CSGA225 -0 -225 -225 -Package_BGA -Xilinx_CSGA324 -Spartan-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=263, NSMD pad definition Appendix A -BGA 324 0.8 CSGA324 -0 -324 -324 -Package_BGA -Xilinx_FBG484 -Artix-7, Kintex-7 and Zynq-7000 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=271, ttps://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=281, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=82, NSMD pad definition Appendix A -BGA 484 1 FB484 FBG484 FBV484 -0 -484 -484 -Package_BGA -Xilinx_FBG676 -Artix-7, Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=273, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=284, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=84, NSMD pad definition Appendix A -BGA 676 1 FB676 FBG676 FBV676 -0 -676 -676 -Package_BGA -Xilinx_FBG900 -Kintex-7 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=289, NSMD pad definition Appendix A -BGA 900 1 FB900 FBG900 FBV900 -0 -900 -900 -Package_BGA -Xilinx_FFG676 -Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=292, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=88, NSMD pad definition Appendix A -BGA 676 1 FF676 FFG676 FFV676 -0 -676 -676 -Package_BGA -Xilinx_FFG900_FFG901 -Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=294, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=90, NSMD pad definition Appendix A -BGA 900 1 FF900 FFG900 FFV900 FF901 FFG901 FFV901 -0 -900 -900 -Package_BGA -Xilinx_FFG1156 -Artix-7, Kintex-7 and Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=277, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=296, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=91, NSMD pad definition Appendix A -BGA 1156 1 FF1156 FFG1156 FFV1156 -0 -1156 -1156 -Package_BGA -Xilinx_FFG1157_FFG1158 -Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=299, NSMD pad definition Appendix A -BGA 1156 1 FF1157 FFG1157 FFV1157 FF1158 FFG1158 FFV1158 -0 -1156 -1156 -Package_BGA -Xilinx_FFG1761 -Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=300, NSMD pad definition Appendix A -BGA 1760 1 FF1761 FFG1761 -0 -1760 -1760 -Package_BGA -Xilinx_FFG1926_FFG1927_FFG1928_FFG1930 -Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=303, NSMD pad definition Appendix A -BGA 1924 1 FF1926 FFG1926 FF1927 FFG1927 FFV1927 FF1928 FFG1928 FF1930 FFG1930 -0 -1924 -1924 -Package_BGA -Xilinx_FFV1761 -Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=301, NSMD pad definition Appendix A -BGA 1760 1 FFV1761 -0 -1760 -1760 -Package_BGA -Xilinx_FGG484 -Artix-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=275, NSMD pad definition Appendix A -BGA 484 1 FG484 FGG484 -0 -484 -484 -Package_BGA -Xilinx_FGG676 -Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=276, NSMD pad definition Appendix A -BGA 676 1 FG676 FGG676 -0 -676 -676 -Package_BGA -Xilinx_FGGA484 -Spartan-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=264, NSMD pad definition Appendix A -BGA 484 1 FGGA484 -0 -484 -484 -Package_BGA -Xilinx_FGGA676 -Spartan-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=265, NSMD pad definition Appendix A -BGA 676 1 FGGA676 -0 -676 -676 -Package_BGA -Xilinx_FHG1761 -Virtex-7 BGA, 42x42 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=302, NSMD pad definition Appendix A -BGA 1760 1 FH1761 FHG1761 -0 -1760 -1760 -Package_BGA -Xilinx_FLG1925_FLG1926_FLG1928_FLG1930 -Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=304, NSMD pad definition Appendix A -BGA 1924 1 FL1925 FLG1925 FL1926 FLG1926 FL1928 FLG1928 FL1930 FLG1930 -0 -1924 -1924 -Package_BGA -Xilinx_FTG256 -Artix-7 BGA, 16x16 grid, 17x17mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=269, NSMD pad definition Appendix A -BGA 256 1 FT256 FTG256 -0 -256 -256 -Package_BGA -Xilinx_FTGB196 -Spartan-7 BGA, 14x14 grid, 15x15mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=261, NSMD pad definition Appendix A -BGA 196 1 FTGB196 -0 -196 -196 -Package_BGA -Xilinx_RB484 -Artix-7 and Zynq-7000 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition Appendix A -BGA 484 1 RB484 -0 -484 -484 -Package_BGA -Xilinx_RB676 -Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=280, NSMD pad definition Appendix A -BGA 676 1 RB676 -0 -676 -676 -Package_BGA -Xilinx_RF676 -Kintex-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=297, NSMD pad definition Appendix A -BGA 676 1 RF676 -0 -676 -676 -Package_BGA -Xilinx_RF900 -Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=298, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=94, NSMD pad definition Appendix A -BGA 900 1 RF900 -0 -900 -900 -Package_BGA -Xilinx_RF1156 -Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=95, NSMD pad definition Appendix A -BGA 1156 1 RF1156 -0 -1156 -1156 -Package_BGA -Xilinx_RF1157_RF1158 -Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=305, NSMD pad definition Appendix A -BGA 1156 1 RF1157 RF1158 -0 -1156 -1156 -Package_BGA -Xilinx_RF1761 -Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=306, NSMD pad definition Appendix A -BGA 1760 1 RF1761 -0 -1760 -1760 -Package_BGA -Xilinx_RF1930 -Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=307, NSMD pad definition Appendix A -BGA 1924 1 RF1930 -0 -1924 -1924 -Package_BGA -Xilinx_RFG676 -Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=93, NSMD pad definition Appendix A -BGA 676 1 RF676 RFG676 -0 -676 -676 -Package_BGA -Xilinx_RS484 -Artix-7 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=279, NSMD pad definition Appendix A -BGA 484 0.8 RS484 -0 -484 -484 -Package_BGA -Xilinx_SBG484 -Artix-7 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=270, NSMD pad definition Appendix A -BGA 484 0.8 SB484 SBG484 SBV484 -0 -484 -484 -Package_BGA -Xilinx_SBG485 -Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=80, NSMD pad definition Appendix A -BGA 484 0.8 SBG485 SBV485 -0 -484 -484 -Package_CSP -Analog_LFCSP-8-1EP_3x3mm_P0.5mm_EP1.53x1.85mm -LFCSP, exposed pad, Analog Devices (http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5542.pdf) -LFCSP 8 0.5 -0 -12 -5 -Package_CSP -LFCSP-8-1EP_3x2mm_P0.5mm_EP1.6x1.65mm -LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/57080735642908cp_8_4.pdf -LFCSP 8pin thermal pad 3x2mm Pitch 0.5mm -0 -9 -9 -Package_CSP -LFCSP-8-1EP_3x3mm_P0.5mm_EP1.45x1.74mm -LFCSP, 8 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-8/CP_8_13.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -LFCSP DFN_QFN -0 -13 -9 -Package_CSP -LFCSP-8_2x2mm_P0.5mm -LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_8_6.pdf -LFCSP 8pin 2x2mm Pitch 0.5mm -0 -8 -8 -Package_CSP -LFCSP-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm -LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/CP_16_22.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -21 -17 -Package_CSP -LFCSP-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias -LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/CP_16_22.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -26 -17 -Package_CSP -LFCSP-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm -LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7992.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -21 -17 -Package_CSP -LFCSP-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm_ThermalVias -LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7992.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -26 -17 -Package_CSP -LFCSP-16-1EP_3x3mm_P0.5mm_EP1.854x1.854mm -16-Lead Lead Frame Chip Scale Package, 3x3mm, 0.5mm pitch, 1.854mm thermal pad (CP-16-22, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_16_22.pdf) -LFCSP 16 0.5 -0 -21 -17 -Package_CSP -LFCSP-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm -LFCSP, 16 pin, 4x4mm, 2.1mm sq pad (http://www.analog.com/media/en/technical-documentation/data-sheets/ADG633.pdf) -LFCSP 16 0.65 -0 -21 -17 -Package_CSP -LFCSP-16-1EP_4x4mm_P0.65mm_EP2.4x2.4mm -LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/cp-16-40.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -21 -17 -Package_CSP -LFCSP-16-1EP_4x4mm_P0.65mm_EP2.4x2.4mm_ThermalVias -LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/cp-16-40.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -31 -17 -Package_CSP -LFCSP-20-1EP_4x4mm_P0.5mm_EP2.1x2.1mm -20-Lead Frame Chip Scale Package - 4x4x0.9 mm Body [LFCSP], (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_20_6.pdf) -LFCSP 0.5 -0 -25 -21 -Package_CSP -LFCSP-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm -LFCSP, 20 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -LFCSP DFN_QFN -0 -25 -21 -Package_CSP -LFCSP-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias -LFCSP, 20 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -LFCSP DFN_QFN -0 -35 -21 -Package_CSP -LFCSP-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm -LFCSP, 20 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-20/CP_20_8.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -25 -21 -Package_CSP -LFCSP-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias -LFCSP, 20 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-20/CP_20_8.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -35 -21 -Package_CSP -LFCSP-24-1EP_4x4mm_P0.5mm_EP2.3x2.3mm -LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -29 -25 -Package_CSP -LFCSP-24-1EP_4x4mm_P0.5mm_EP2.3x2.3mm_ThermalVias -LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -39 -25 -Package_CSP -LFCSP-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm -LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -29 -25 -Package_CSP -LFCSP-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias -LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -39 -25 -Package_CSP -LFCSP-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm -LFCSP, 32 Pin (https://www.analog.com/media/en/package-pcb-resources/package/414143737956480539664569cp_32_2.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -42 -33 -Package_CSP -LFCSP-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias -LFCSP, 32 Pin (https://www.analog.com/media/en/package-pcb-resources/package/414143737956480539664569cp_32_2.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -59 -33 -Package_CSP -LFCSP-32-1EP_5x5mm_P0.5mm_EP3.25x3.25mm -32-Lead Frame Chip Scale Package LFCSP (5mm x 5mm); (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-32/CP_32_27.pdf -LFCSP 0.5 -0 -37 -33 -Package_CSP -LFCSP-48-1EP_7x7mm_P0.5mm_EP4.1x4.1mm -LFCSP, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -58 -49 -Package_CSP -LFCSP-48-1EP_7x7mm_P0.5mm_EP4.1x4.1mm_ThermalVias -LFCSP, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -75 -49 -Package_CSP -LFCSP-64-1EP_9x9mm_P0.5mm_EP5.21x5.21mm -LFCSP, 64 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_64_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -69 -65 -Package_CSP -LFCSP-64-1EP_9x9mm_P0.5mm_EP5.21x5.21mm_ThermalVias -LFCSP, 64 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_64_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -86 -65 -Package_CSP -LFCSP-72-1EP_10x10mm_P0.5mm_EP5.3x5.3mm -LFCSP, 72 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -82 -73 -Package_CSP -LFCSP-72-1EP_10x10mm_P0.5mm_EP5.3x5.3mm_ThermalVias -LFCSP, 72 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP NoLead -0 -99 -73 -Package_CSP -LFCSP-72-1EP_10x10mm_P0.5mm_EP6.15x6.15mm -72-Lead Frame Chip Scale Package - 10x10x0.9 mm Body [LFCSP]; (see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf) -LFCSP 0.5 -0 -77 -73 -Package_CSP -LFCSP-VQ-24-1EP_4x4mm_P0.5mm_EP2.642x2.642mm -LFCSP VQ, 24 pin, exposed pad, 4x4mm body, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf) -LFCSP 0.5 -0 -29 -25 -Package_CSP -LFCSP-VQ-48-1EP_7x7mm_P0.5mm -LFCSP VQ, 48 pin, exposed pad, 7x7mm body (http://www.analog.com/media/en/technical-documentation/data-sheets/AD7951.pdf, http://www.analog.com/en/design-center/packaging-quality-symbols-footprints/symbols-and-footprints/AD7951.html) -LFCSP 48 -0 -49 -49 -Package_CSP -LFCSP-WD-10-1EP_3x3mm_P0.5mm_EP1.64x2.38mm -LFCSP-WD, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-10/CP_10_9.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP-WD NoLead -0 -17 -11 -Package_CSP -LFCSP-WD-10-1EP_3x3mm_P0.5mm_EP1.64x2.38mm_ThermalVias -LFCSP-WD, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-10/CP_10_9.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -LFCSP-WD NoLead -0 -24 -11 -Package_CSP -ST_WLCSP-25_Die425 -WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf -BGA 25 0.4 -0 -25 -25 -Package_CSP -ST_WLCSP-25_Die444 -WLCSP-25, 5x5 raster, 2.423x2.325mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f031k6.pdf -BGA 25 0.4 -0 -25 -25 -Package_CSP -ST_WLCSP-25_Die457 -WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32l011k3.pdf -BGA 25 0.4 -0 -25 -25 -Package_CSP -ST_WLCSP-36_Die417 -WLCSP-36, 6x6 raster, 2.61x2.88mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l052t8.pdf -BGA 36 0.4 -0 -36 -36 -Package_CSP -ST_WLCSP-36_Die440 -WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf -BGA 36 0.4 -0 -36 -36 -Package_CSP -ST_WLCSP-36_Die445 -WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32f042k6.pdf -BGA 36 0.4 -0 -36 -36 -Package_CSP -ST_WLCSP-36_Die458 -WLCSP-36, 6x6 raster, 2.553x2.579mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f410t8.pdf -BGA 36 0.4 -0 -36 -36 -Package_CSP -ST_WLCSP-49_Die423 -WLCSP-49, 7x7 raster, 2.965x2.965mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f401vc.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die431 -WLCSP-49, 7x7 raster, 2.999x3.185mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f411vc.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die433 -WLCSP-49, 7x7 raster, 3.029x3.029mm package, pitch 0.4mm; see section 7.1.1 of http://www.st.com/resource/en/datasheet/stm32f401ce.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die435 -WLCSP-49, 7x7 raster, 3.141x3.127mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/DM00257211.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die438 -WLCSP-49, 7x7 raster, 3.89x3.74mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303r8.pdf -BGA 49 0.5 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die439 -WLCSP-49, 7x7 raster, 3.417x3.151mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f301r8.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die447 -WLCSP-49, 7x7 raster, 3.294x3.258mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-49_Die448 -WLCSP-49, 7x7 raster, 3.277x3.109mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f071v8.pdf -BGA 49 0.4 -0 -49 -49 -Package_CSP -ST_WLCSP-63_Die427 -WLCSP-63, 7x9 raster, 3.228x4.164mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l151cc.pdf -BGA 63 0.4 -0 -63 -63 -Package_CSP -ST_WLCSP-64_Die414 -WLCSP-64, 8x8 raster, 4.466x4.395mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf -BGA 64 0.5 -0 -64 -64 -Package_CSP -ST_WLCSP-64_Die427 -WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf -BGA 64 0.4 -0 -64 -64 -Package_CSP -ST_WLCSP-64_Die435 -WLCSP-64, 8x8 raster, 3.141x3.127mm package, pitch 0.35mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00257211.pdf -BGA 64 0.35 -0 -64 -64 -Package_CSP -ST_WLCSP-64_Die436 -WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zd.pdf -BGA 64 0.4 -0 -64 -64 -Package_CSP -ST_WLCSP-64_Die441 -WLCSP-64, 8x8 raster, 3.623x3.651mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00213872.pdf -BGA 64 0.4 -0 -64 -64 -Package_CSP -ST_WLCSP-64_Die442 -WLCSP-64, 8x8 raster, 3.347x3.585mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f091vb.pdf -BGA 64 0.4 -0 -64 -64 -Package_CSP -ST_WLCSP-64_Die462 -WLCSP-64, 8x8 raster, 3.357x3.657mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00340475.pdf -BGA 64 0.4 -0 -64 -64 -Package_CSP -ST_WLCSP-66_Die411 -WLCSP-66, 9x9 raster, 3.639x3.971mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf -BGA 66 0.4 -0 -66 -66 -Package_CSP -ST_WLCSP-66_Die432 -WLCSP-66, 8x9 raster, 3.767x4.229mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f378vc.pdf -BGA 66 0.4 -0 -66 -66 -Package_CSP -ST_WLCSP-72_Die415 -WLCSP-72, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf -BGA 72 0.4 -0 -72 -72 -Package_CSP -ST_WLCSP-81_Die415 -WLCSP-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf -BGA 81 0.4 -0 -81 -81 -Package_CSP -ST_WLCSP-81_Die421 -WLCSP-81, 9x9 raster, 3.693x3.815mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf -BGA 81 0.4 -0 -81 -81 -Package_CSP -ST_WLCSP-81_Die463 -WLCSP-81, 9x9 raster, 4.039x3.951mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf -BGA 81 0.4 -0 -81 -81 -Package_CSP -ST_WLCSP-90_Die413 -WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f405og.pdf -BGA 90 0.4 -0 -90 -90 -Package_CSP -ST_WLCSP-100_Die422 -WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f302vc.pdf -BGA 100 0.4 -0 -100 -100 -Package_CSP -ST_WLCSP-100_Die446 -WLCSP-100, 10x10 raster, 4.775x5.041mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303zd.pdf -BGA 100 0.4 -0 -100 -100 -Package_CSP -ST_WLCSP-100_Die452 -WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.7 of http://www.st.com/resource/en/datasheet/DM00330506.pdf -BGA 100 0.4 -0 -100 -100 -Package_CSP -ST_WLCSP-100_Die461 -WLCSP-100, 10x10 raster, 4.618x4.142mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00284211.pdf -BGA 100 0.4 -0 -100 -100 -Package_CSP -ST_WLCSP-104_Die437 -WLCSP-104, 9x12 raster, 4.095x5.094mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152ze.pdf -BGA 104 0.4 -0 -104 -104 -Package_CSP -ST_WLCSP-143_Die419 -WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf -BGA 143 0.4 -0 -143 -143 -Package_CSP -ST_WLCSP-143_Die449 -WLCSP-143, 11x13 raster, 4.539x5.849mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf -BGA 143 0.4 -0 -143 -143 -Package_CSP -ST_WLCSP-144_Die470 -WLCSP-144, 12x12 raster, 5.24x5.24mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/DM00366448.pdf -BGA 144 0.4 -0 -144 -144 -Package_CSP -ST_WLCSP-168_Die434 -WLCSP-168, 12x14 raster, 4.891x5.692mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf -BGA 168 0.4 -0 -168 -168 -Package_CSP -ST_WLCSP-180_Die451 -WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 6.6 of http://www.st.com/resource/en/datasheet/DM00273119.pdf -BGA 180 0.4 -0 -180 -180 -Package_CSP -WLCSP-6_1.4x1.0mm_P0.4mm -6pin Pitch 0.4mm -6pin Pitch 0.4mm WLCSP -0 -6 -6 -Package_CSP -WLCSP-8_1.58x1.63x0.35mm_Layout3x5_P0.35x0.4mm_Ball0.25mm_Pad0.25mm_NSMD -WLCSP/XFBGA 8-pin package, staggered pins, http://www.adestotech.com/wp-content/uploads/DS-AT25DF041B_040.pdf -WLCSP WLCSP-8 XFBGA XFBGA-8 CSP BGA Chip-Scale Glass-Top -0 -8 -8 -Package_CSP -WLCSP-12_1.56x1.56mm_P0.4mm -WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf -BMM150 WLCSP -0 -12 -12 -Package_CSP -WLCSP-12_1.403x1.555mm_P0.4mm_Stagger -WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; http://ww1.microchip.com/downloads/en/devicedoc/atmel-8235-8-bit-avr-microcontroller-attiny20_datasheet.pdf#page=208 -CSP 12 0.2x0.346333 -0 -12 -12 -Package_CSP -WLCSP-16_4x4_B2.17x2.32mm_P0.5mm -WLCSP-16, http://www.nxp.com/documents/data_sheet/LPC1102_1104.pdf, http://www.nxp.com/assets/documents/data/en/application-notes/AN3846.pdf -WLCSP-16 NXP -0 -16 -16 -Package_CSP -WLCSP-20_1.934x2.434mm_Layout4x5_P0.4mm -WLCSP-20, 4x5 raster, 1.934x2.434mm package, pitch 0.4mm; see section 36.2.3 of http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42363-SAM-D11_Datasheet.pdf -BGA 20 0.4 -0 -20 -20 -Package_CSP -WLCSP-20_1.994x1.94mm_Layout4x5_P0.4mm -WLCSP-20, https://www.nxp.com/docs/en/package-information/98ASA00539D.pdf -WLCSP-20 -0 -20 -20 -Package_CSP -WLCSP-20_1.994x1.609mm_Layout5x4_P0.4mm -WLCSP-20, https://www.nxp.com/docs/en/package-information/98ASA00676D.pdf -WLCSP-20 -0 -20 -20 -Package_CSP -WLCSP-36_2.82x2.67mm_Layout6x6_P0.4mm -WLCSP-36, https://www.nxp.com/docs/en/package-information/98ASA00949D.pdf -WLCSP-36 -0 -36 -36 -Package_CSP -WLCSP-36_2.374x2.459mm_Layout6x6_P0.35mm -WLCSP-36, https://www.nxp.com/docs/en/package-information/98ASA00604D.pdf -WLCSP-36 -0 -36 -36 -Package_CSP -WLCSP-56_3.170x3.444mm_Layout7x8_P0.4mm -WLCSP-56, 7x8 raster, 3.170x3.444mm package, pitch 0.4mm; see section 48.2.4 of http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001479B.pdf -BGA 56 0.4 -0 -56 -56 -Package_CSP -WLCSP-81_4.41x3.76mm_P0.4mm -WLCSP-81, 9x9, 0.4mm Pitch, http://www.st.com/content/ccc/resource/technical/document/technical_note/92/30/3c/a1/4c/bb/43/6f/DM00103228.pdf/files/DM00103228.pdf/jcr:content/translations/en.DM00103228.pdf -WLCSP ST -0 -81 -81 -Package_CSP -pSemi_CSP-16_1.64x2.04mm_P0.4mm -pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf) -psemi csp 16 -0 -16 -16 -Package_CSP -pSemi_CSP-16_1.64x2.04mm_P0.4mm_Pad0.18mm -pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf) -psemi csp 16 -0 -16 -16 -Package_DFN_QFN -AMS_QFN-4-1EP_2x2mm_P0.95mm_EP0.7x1.6mm -UFD Package, 4-Lead Plastic QFN (2mm x 2mm), http://ams.com/eng/content/download/950231/2267959/483138 -QFN 0.95 -0 -6 -5 -Package_DFN_QFN -Cypress_QFN-56-1EP_8x8mm_P0.5mm_EP6.22x6.22mm_ThermalVias -56-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8x0.9 mm Body [QFN] (see datasheet at http://www.cypress.com/file/138911/download and app note at http://www.cypress.com/file/140006/download) -QFN 0.5 -0 -87 -57 -Package_DFN_QFN -DFN-6-1EP_1.2x1.2mm_P0.4mm_EP0.3x0.94mm_PullBack -DFN, 6 Pin (http://www.onsemi.com/pub/Collateral/NCP133-D.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -9 -7 -Package_DFN_QFN -DFN-6-1EP_2x1.8mm_P0.5mm_EP1.2x1.6mm -DFN, 6 Pin (https://www.diodes.com/assets/Package-Files/U-DFN2018-6.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -11 -7 -Package_DFN_QFN -DFN-6-1EP_2x2mm_P0.5mm_EP0.61x1.42mm -DC6 Package; 6-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_6_05-08-1703.pdf) -DFN 0.5 -0 -9 -7 -Package_DFN_QFN -DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm -6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.65 -0 -9 -7 -Package_DFN_QFN -DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm -DFN, 6 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/(DCB6)%20DFN%2005-08-1715%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -11 -7 -Package_DFN_QFN -DFN-6-1EP_3x3mm_P0.95mm_EP1.7x2.6mm -DFN6 3*3 MM, 0.95 PITCH; CASE 506AH-01 (see ON Semiconductor 506AH.PDF) -DFN 0.95 -0 -13 -7 -Package_DFN_QFN -DFN-6-1EP_3x3mm_P1mm_EP1.5x2.4mm -DFN, 6 Pin (https://www.silabs.com/documents/public/data-sheets/Si7020-A20.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -11 -7 -Package_DFN_QFN -DFN-6_1.3x1.2mm_P0.4mm -6-Lead Plastic DFN (1.3mm x 1.2mm) -DFN 0.4 -0 -6 -6 -Package_DFN_QFN -DFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.3mm -DFN, 8 Pin (https://www.onsemi.com/pub/Collateral/NB3N551-D.PDF#page=7), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.5mm -DFN, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8127-AVR-8-bit-Microcontroller-ATtiny4-ATtiny5-ATtiny9-ATtiny10_Datasheet.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_2x2mm_P0.5mm_EP1.05x1.75mm -DFN8 2x2, 0.5P; CASE 506CN (see ON Semiconductor 506CN.PDF) -DFN 0.5 -0 -11 -9 -Package_DFN_QFN -DFN-8-1EP_2x2mm_P0.45mm_EP0.64x1.38mm -DC8 Package 8-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_8_05-08-1719.pdf) -DFN 0.45 -0 -11 -9 -Package_DFN_QFN -DFN-8-1EP_2x3mm_P0.5mm_EP0.61x2.2mm -DDB Package; 8-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_8_05-08-1702.pdf) -DFN 0.5 -0 -12 -9 -Package_DFN_QFN -DFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.5mm -8-Lead Plastic Dual Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body [UDFN] (see Atmel-8815-SEEPROM-AT24CS01-02-Datasheet.pdf) -DFN 0.5 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_3x2mm_P0.5mm_EP1.36x1.46mm -8-Lead Plastic Dual Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body (http://ww1.microchip.com/downloads/en/DeviceDoc/20005010F.pdf) -DFN 0.5 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_3x2mm_P0.5mm_EP1.75x1.45mm -8-Lead Plastic Dual Flat, No Lead Package (MC) - 2x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.5 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_3x2mm_P0.45mm_EP1.66x1.36mm -DCB Package 8-Lead Plastic DFN (2mm x 3mm) (see Linear Technology DFN_8_05-08-1718.pdf) -DFN 0.45 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_3x3mm_P0.5mm_EP1.66x2.38mm -DD Package; 8-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_8_05-08-1698.pdf) -DFN 0.5 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_3x3mm_P0.65mm_EP1.7x2.05mm -DFN, 8 Pin (http://www.ixysic.com/home/pdfs.nsf/www/IX4426-27-28.pdf/$file/IX4426-27-28.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_3x3mm_P0.65mm_EP1.55x2.4mm -8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.65 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_4x4mm_P0.8mm_EP2.3x3.24mm -DFN, 8 Pin (https://www.st.com/resource/en/datasheet/ld1086.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm -8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.8 -0 -15 -9 -Package_DFN_QFN -DFN-8-1EP_4x4mm_P0.8mm_EP2.39x2.21mm -8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN] (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF) -DFN 0.8 -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_6x5mm_P1.27mm_EP2x2mm -DD Package; 8-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download) -dfn -0 -13 -9 -Package_DFN_QFN -DFN-8-1EP_6x5mm_P1.27mm_EP4x4mm -DD Package; 8-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download) -dfn -0 -25 -9 -Package_DFN_QFN -DFN-8_2x2mm_P0.5mm -DFN8 2x2, 0.5P; No exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF -DFN 0.5 -0 -8 -8 -Package_DFN_QFN -DFN-10-1EP_2x3mm_P0.5mm_EP0.64x2.4mm -DDB Package; 10-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_10_05-08-1722.pdf) -DFN 0.5 -0 -13 -11 -Package_DFN_QFN -DFN-10-1EP_3x3mm_P0.5mm_EP1.7x2.5mm -DFN, 10 Pin (https://www.monolithicpower.com/pub/media/document/MPQ2483_r1.05.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -15 -11 -Package_DFN_QFN -DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm -10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.5 -0 -15 -11 -Package_DFN_QFN -DFN-10-1EP_3x3mm_P0.5mm_EP1.65x2.38mm -DFN, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -15 -11 -Package_DFN_QFN -DFN-10-1EP_3x3mm_P0.5mm_EP1.65x2.38mm_ThermalVias -DFN, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py -DFN NoLead -0 -22 -11 -Package_DFN_QFN -DFN-10-1EP_3x3mm_P0.5mm_EP1.75x2.7mm -10-Lead Plastic Dual Flat No-Lead Package, 3x3mm Body (see Atmel Appnote 8826) -DFN 0.5 -0 -15 -11 -Package_DFN_QFN -DFN-10_2x2mm_P0.4mm -10-Lead Plastic DFN (2mm x 2mm) 0.40mm pitch -DFN 10 0.4mm -0 -10 -10 -Package_DFN_QFN -DFN-12-1EP_2x3mm_P0.45mm_EP0.64x2.4mm -DDB Package; 12-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_12_05-08-1723.pdf) -DFN 0.45 -0 -15 -13 -Package_DFN_QFN -DFN-12-1EP_3x3mm_P0.5mm_EP2.05x2.86mm -10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.5 -0 -17 -13 -Package_DFN_QFN -DFN-12-1EP_3x3mm_P0.45mm_EP1.66x2.38mm -DD Package; 12-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_12_05-08-1725.pdf) -DFN 0.45 -0 -17 -13 -Package_DFN_QFN -DFN-12-1EP_3x4mm_P0.5mm_EP1.7x3.3mm -DE/UE Package; 12-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_12_05-08-1695.pdf) -DFN 0.5 -0 -21 -13 -Package_DFN_QFN -DFN-12-1EP_4x4mm_P0.5mm_EP2.66x3.38mm -DF Package; 12-Lead Plastic DFN (4mm x 4mm) (see Linear Technology 05081733_A_DF12.pdf) -DFN 0.5 -0 -21 -13 -Package_DFN_QFN -DFN-12-1EP_4x4mm_P0.65mm_EP2.64x3.54mm -DFN12, 4x4, 0.65P; CASE 506CE (see ON Semiconductor 506CE.PDF) -DFN 0.65 -0 -21 -13 -Package_DFN_QFN -DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm -DD Package; 14-Lead Plastic DFN (3mm x 3mm) (http://pdfserv.maximintegrated.com/land_patterns/90-0063.PDF) -DFN 0.40 -0 -19 -15 -Package_DFN_QFN -DFN-14-1EP_3x4.5mm_P0.65mm_EP1.65x4.25mm -14-lead very thin plastic quad flat, 3.0x4.5mm size, 0.65mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/14L_VDFN_4_5x3_0mm_JHA_C041198A.pdf) -VDFN DFN 0.65mm -0 -23 -15 -Package_DFN_QFN -DFN-14-1EP_3x4.5mm_P0.65mm_EP1.65x4.25mm_ThermalVias -14-lead very thin plastic quad flat, 3.0x4.5mm size, 0.65mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/14L_VDFN_4_5x3_0mm_JHA_C041198A.pdf) -VDFN DFN 0.65mm -0 -33 -15 -Package_DFN_QFN -DFN-14-1EP_3x4mm_P0.5mm_EP1.7x3.3mm -DE Package; 14-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_14_05-08-1708.pdf) -DFN 0.5 -0 -23 -15 -Package_DFN_QFN -DFN-14-1EP_4x4mm_P0.5mm_EP2.86x3.6mm -DFN14, 4x4, 0.5P; CASE 506CM (see ON Semiconductor 506CM.PDF) -DFN 0.5 -0 -23 -15 -Package_DFN_QFN -DFN-16-1EP_3x4mm_P0.45mm_EP1.7x3.3mm -DE Package; 16-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_16_05-08-1732.pdf) -DFN 0.45 -0 -25 -17 -Package_DFN_QFN -DFN-16-1EP_3x5mm_P0.5mm_EP1.66x4.4mm -DHC Package; 16-Lead Plastic DFN (5mm x 3mm) (see Linear Technology DFN_16_05-08-1706.pdf) -DFN 0.5 -0 -27 -17 -Package_DFN_QFN -DFN-16-1EP_4x5mm_P0.5mm_EP2.44x4.34mm -DHD Package; 16-Lead Plastic DFN (5mm x 4mm) (see Linear Technology 05081707_A_DHD16.pdf) -DFN 0.5 -0 -25 -17 -Package_DFN_QFN -DFN-16-1EP_5x5mm_P0.5mm_EP3.46x4mm -DH Package; 16-Lead Plastic DFN (5mm x 5mm) (see Linear Technology DFN_16_05-08-1709.pdf) -DFN 0.5 -0 -26 -17 -Package_DFN_QFN -DFN-18-1EP_3x5mm_P0.5mm_EP1.66x4.4mm -DHC Package; 18-Lead Plastic DFN (5mm x 3mm) (see Linear Technology 05081955_0_DHC18.pdf) -DFN 0.5 -0 -29 -19 -Package_DFN_QFN -DFN-18-1EP_4x5mm_P0.5mm_EP2.44x4.34mm -DHD Package; 18-Lead Plastic DFN (5mm x 4mm) (see Linear Technology DFN_18_05-08-1778.pdf) -DFN 0.5 -0 -27 -19 -Package_DFN_QFN -DFN-20-1EP_5x6mm_P0.5mm_EP3.24x4.24mm -DFN20, 6x5, 0.5P; CASE 505AB (see ON Semiconductor 505AB.PDF) -DFN 0.5 -0 -33 -21 -Package_DFN_QFN -DFN-22-1EP_5x6mm_P0.5mm_EP3.14x4.3mm -DFN22 6*5*0.9 MM, 0.5 P; CASE 506AF\xe2\x88\x9201 (see ON Semiconductor 506AF.PDF) -DFN 0.5 -0 -35 -23 -Package_DFN_QFN -DFN-24-1EP_4x7mm_P0.5mm_EP2.64x6.44mm -DKD Package; 24-Lead Plastic DFN (7mm x 4mm) (see Linear Technology DFN_24_05-08-1864.pdf) -DFN 0.5 -0 -35 -25 -Package_DFN_QFN -DFN-32-1EP_4x7mm_P0.4mm_EP2.64x6.44mm -DKD Package; 32-Lead Plastic DFN (7mm x 4mm) (see Linear Technology DFN_32_05-08-1734.pdf) -DFN 0.4 -0 -43 -33 -Package_DFN_QFN -DFN-44-1EP_5x8.9mm_P0.4mm_EP3.7x8.4mm -DFN44 8.9x5, 0.4P; CASE 506BU-01 (see ON Semiconductor 506BU.PDF) -DFN 0.4 -0 -63 -45 -Package_DFN_QFN -DFN-S-8-1EP_6x5mm_P1.27mm -8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 1.27 -0 -16 -9 -Package_DFN_QFN -Diodes_DFN1006-3 -DFN package size 1006 3 pins -DFN package size 1006 3 pins -0 -3 -3 -Package_DFN_QFN -Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm -MLPQ 32 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) -mlpq 32 7x7mm -0 -19 -15 -Package_DFN_QFN -Infineon_MLPQ-40-32-1EP_7x7mm_P0.5mm -MLPQ 32 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) -mlpq 32 7x7mm -0 -76 -33 -Package_DFN_QFN -Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_EP5.55x5.55mm -MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2093mpbf.pdf?fileId=5546d462533600a401535675fb892793) -mlpq 32 7x7mm -0 -113 -49 -Package_DFN_QFN -Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_Pad5.15x5.15mm -MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2052mpbf.pdf?fileId=5546d462533600a401535675d3b32788) -mlpq 32 7x7mm -0 -117 -49 -Package_DFN_QFN -Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_Pad5.55x5.55mm -MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2093mpbf.pdf?fileId=5546d462533600a401535675fb892793) -mlpq 32 7x7mm -0 -117 -49 -Package_DFN_QFN -Infineon_PQFN-22-15-4EP_6x5mm_P0.65mm -PQFN 22 leads, 5x6mm, 0.127mm stencil (https://www.infineon.com/dgdl/ir4301.pdf?fileId=5546d462533600a4015355d5fc691819, https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) -pqfn 22 5x6mm -0 -56 -15 -Package_DFN_QFN -Infineon_PQFN-44-31-5EP_7x7mm_P0.5mm -PQFN 44 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/ir4302.pdf?fileId=5546d462533600a4015355d602a9181d, https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) -pqfn 44 7x7mm -0 -125 -27 -Package_DFN_QFN -Linear_DE14MA -14-Lead Plastic DFN, 4mm x 3mm (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/05081731_C_DE14MA.pdf) -DFN 0.5 -0 -14 -14 -Package_DFN_QFN -Linear_UGK52_QFN-46-52 -Linear UKG52(46) package, QFN-52-1EP variant (see http://cds.linear.com/docs/en/datasheet/3886fe.pdf) -QFN 0.5 -0 -62 -47 -Package_DFN_QFN -MLF-6-1EP_1.6x1.6mm_P0.5mm_EP0.5x1.26mm -MLF, 6 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5353.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -MLF NoLead -0 -9 -7 -Package_DFN_QFN -MLF-8-1EP_3x3mm_P0.65mm_EP1.55x2.3mm -8-Pin ePad 3mm x 3mm MLF - 3x3x0.85 mm Body (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf) -DFN MLF 0.65 -0 -12 -9 -Package_DFN_QFN -MLF-8-1EP_3x3mm_P0.65mm_EP1.55x2.3mm_ThermalVias -8-Pin ePad 3mm x 3mm MLF - 3x3x0.85 mm Body (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf) -DFN MLF 0.65 -0 -15 -9 -Package_DFN_QFN -MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm -MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=263), generated with kicad-footprint-generator ipc_noLead_generator.py -MLF NoLead -0 -25 -21 -Package_DFN_QFN -MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias -MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=263), generated with kicad-footprint-generator ipc_noLead_generator.py -MLF NoLead -0 -30 -21 -Package_DFN_QFN -MLPQ-16-1EP_4x4mm_P0.65mm_EP2.8x2.8mm -Micro Leadframe Package, 16 pin with exposed pad -MLPQ- 0.65 -0 -21 -17 -Package_DFN_QFN -Micrel_MLF-8-1EP_2x2mm_P0.5mm_EP0.8x1.3mm_ThermalVias -http://ww1.microchip.com/downloads/en/DeviceDoc/mic2290.pdf -mlf 8 2x2 mm -0 -14 -9 -Package_DFN_QFN -Microchip_8E-16 -16-Lead Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf) -QFN Microchip 8E 16 -0 -20 -17 -Package_DFN_QFN -Microchip_DRQFN-44-1EP_5x5mm_P0.7mm_EP2.65x2.65mm -QFN, 44 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/44L_VQFN_5x5mm_Dual_Row_%5BS3B%5D_C04-21399a.pdf) -QFN dual row -0 -49 -45 -Package_DFN_QFN -Microchip_DRQFN-44-1EP_5x5mm_P0.7mm_EP2.65x2.65mm_ThermalVias -QFN, 44 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/44L_VQFN_5x5mm_Dual_Row_%5BS3B%5D_C04-21399a.pdf) -QFN dual row -0 -59 -45 -Package_DFN_QFN -Microchip_DRQFN-64-1EP_7x7mm_P0.65mm_EP4.1x4.1mm -QFN, 64 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_7x7_Dual_Row_%5BSVB%5D_C04-21420a.pdf) -QFN dual row -0 -74 -65 -Package_DFN_QFN -Microchip_DRQFN-64-1EP_7x7mm_P0.65mm_EP4.1x4.1mm_ThermalVias -QFN, 64 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_7x7_Dual_Row_%5BSVB%5D_C04-21420a.pdf) -QFN dual row -0 -91 -65 -Package_DFN_QFN -Microsemi_QFN-40-32-2EP_6x8mm_P0.5mm -40-Lead (32-Lead Populated) Plastic Quad Flat, No Lead Package - 6x8x0.9mm Body (https://www.microsemi.com/document-portal/doc_download/131677-pd70224-data-sheet) -QFN 0.5 -0 -92 -34 -Package_DFN_QFN -Mini-Circuits_DL805 -https://ww2.minicircuits.com/case_style/DL805.pdf -RF Switch -0 -11 -9 -Package_DFN_QFN -Mini-Circuits_FG873-4_3x3mm -Mini Circuits Case style FG (https://ww2.minicircuits.com/case_style/FG873.pdf) -FG873 -0 -4 -4 -Package_DFN_QFN -Nordic_AQFN-73-1EP_7x7mm_P0.5mm -http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fchips%2Fnrf52840.html -AQFN 7mm -0 -78 -74 -Package_DFN_QFN -OnSemi_DFN-8_2x2mm_P0.5mm -DFN8 2x2, 0.5P (https://www.onsemi.com/pub/Collateral/511AT.PDF) -DFN 0.5 -0 -8 -8 -Package_DFN_QFN -OnSemi_UDFN-8_1.2x1.8mm_P0.4mm -8-Lead Plastic Dual Flat, No Lead Package, 1.2x1.8x1.55 mm Body [UDFN] (See http://www.onsemi.com/pub/Collateral/NLSV2T244-D.PDF) -dfn udfn dual flat -0 -8 -8 -Package_DFN_QFN -OnSemi_VCT-28_3.5x3.5mm_P0.4mm -OnSemi VCT, 28 Pin (http://www.onsemi.com/pub/Collateral/601AE.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -OnSemi VCT DFN_QFN -0 -28 -28 -Package_DFN_QFN -Panasonic_HQFN-16-1EP_4x4mm_P0.65mm_EP2.9x2.9mm -Panasonic HQFN-16, 4x4x0.85mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HQFN016-A-0404XZL_EN.pdf) -panasonic hqfn -0 -37 -17 -Package_DFN_QFN -Panasonic_HSON-8_8x8mm_P2.00mm -Panasonic HSON-8, 8x8x1.25mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HSON008-A-0808XXI_EN.pdf) -panasonic hson -0 -27 -9 -Package_DFN_QFN -QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm -QFN, 12 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_12_%2005-08-1855.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -17 -13 -Package_DFN_QFN -QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm_ThermalVias -QFN, 12 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_12_%2005-08-1855.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -22 -13 -Package_DFN_QFN -QFN-12-1EP_3x3mm_P0.51mm_EP1.45x1.45mm -QFN, 12 Pin (https://ww2.minicircuits.com/case_style/DQ1225.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -17 -13 -Package_DFN_QFN -QFN-14-1EP_1.6x1.6mm_P0.4mm_EP0.74x0.74mm -QFN, 14 Pin (http://www.skyworksinc.com/uploads/documents/SKY13575_639LF_203270D.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -19 -15 -Package_DFN_QFN -QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm -QFN, 16 Pin (https://www.st.com/content/ccc/resource/technical/document/datasheet/4a/50/94/16/69/af/4b/58/DM00047334.pdf/files/DM00047334.pdf/jcr:content/translations/en.DM00047334.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm_ThermalVias -QFN, 16 Pin (http://www.cypress.com/file/46236/download), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_3x3mm_P0.5mm_EP1.9x1.9mm -QFN, 16 Pin (https://www.nxp.com/docs/en/package-information/98ASA00525D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 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(https://www.onsemi.com/pub/Collateral/NCN4555-D.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -26 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.5mm_EP2.45x2.45mm -QFN, 16 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/isl8117.pdf#page=22), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias -QFN, 16 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/isl8117.pdf#page=22), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm -QFN, 16 Pin (http://www.thatcorp.com/datashts/THAT_1580_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm_ThermalVias -QFN, 16 Pin (http://www.thatcorp.com/datashts/THAT_1580_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.5x2.5mm -QFN, 16 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=266), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.5x2.5mm_ThermalVias -QFN, 16 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=266), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm -QFN, 16 Pin (https://www.allegromicro.com/~/media/Files/Datasheets/A4403-Datasheet.ashx), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_PullBack -QFN, 16 Pin (https://ams.com/documents/20143/36005/AS5055A_DS000304_2-00.pdf#page=24), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_PullBack_ThermalVias -QFN, 16 Pin (https://ams.com/documents/20143/36005/AS5055A_DS000304_2-00.pdf#page=24), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_ThermalVias -QFN, 16 Pin (https://www.allegromicro.com/~/media/Files/Datasheets/A4403-Datasheet.ashx), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.15x2.15mm -QFN, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4001f.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_4x4mm_P0.65mm_EP2.15x2.15mm_ThermalVias -QFN, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4001f.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-16-1EP_5x5mm_P0.8mm_EP2.7x2.7mm -QFN, 16 Pin (http://www.intersil.com/content/dam/Intersil/documents/l16_/l16.5x5.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -QFN-16-1EP_5x5mm_P0.8mm_EP2.7x2.7mm_ThermalVias -QFN, 16 Pin (http://www.intersil.com/content/dam/Intersil/documents/l16_/l16.5x5.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm -QFN, 20 Pin (http://www.ti.com/lit/ml/mpqf239/mpqf239.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -25 -21 -Package_DFN_QFN -QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm_ThermalVias -QFN, 20 Pin (http://www.ti.com/lit/ml/mpqf239/mpqf239.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -30 -21 -Package_DFN_QFN -QFN-20-1EP_3x3mm_P0.4mm_EP1.65x1.65mm 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kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -30 -21 -Package_DFN_QFN -QFN-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm -QFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc2535.pdf#page=164), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -25 -21 -Package_DFN_QFN -QFN-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias -QFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc2535.pdf#page=164), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -30 -21 -Package_DFN_QFN -QFN-20-1EP_4x4mm_P0.5mm_EP2.7x2.7mm -QFN, 20 Pin (https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -25 -21 -Package_DFN_QFN -QFN-20-1EP_4x4mm_P0.5mm_EP2.7x2.7mm_ThermalVias -QFN, 20 Pin (https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -30 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ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -35 -21 -Package_DFN_QFN -QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm -QFN, 24 Pin (https://www.invensense.com/wp-content/uploads/2015/02/PS-MPU-9250A-01-v1.1.pdf#page=39), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -29 -25 -Package_DFN_QFN -QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm_ThermalVias -QFN, 24 Pin (https://www.invensense.com/wp-content/uploads/2015/02/PS-MPU-9250A-01-v1.1.pdf#page=39), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -34 -25 -Package_DFN_QFN -QFN-24-1EP_3x4mm_P0.4mm_EP1.65x2.65mm -QFN, 24 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1742.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -31 -25 -Package_DFN_QFN -QFN-24-1EP_3x4mm_P0.4mm_EP1.65x2.65mm_ThermalVias -QFN, 24 Pin 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Pin (https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -39 -25 -Package_DFN_QFN -QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm -QFN, 24 Pin (http://www.alfarzpp.lv/eng/sc/AS3330.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -29 -25 -Package_DFN_QFN -QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm_ThermalVias -QFN, 24 Pin (http://www.alfarzpp.lv/eng/sc/AS3330.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -39 -25 -Package_DFN_QFN -QFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm -QFN, 24 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/hmc431.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -29 -25 -Package_DFN_QFN -QFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_ThermalVias -QFN, 24 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/hmc431.pdf), generated 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ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -44 -25 -Package_DFN_QFN -QFN-24-1EP_5x5mm_P0.65mm_EP3.2x3.2mm -QFN, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UH24)%20QFN%2005-08-1747%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -29 -25 -Package_DFN_QFN -QFN-24-1EP_5x5mm_P0.65mm_EP3.2x3.2mm_ThermalVias -QFN, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UH24)%20QFN%2005-08-1747%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -51 -25 -Package_DFN_QFN -QFN-24-1EP_5x5mm_P0.65mm_EP3.4x3.4mm -QFN, 24 Pin (http://www.thatcorp.com/datashts/THAT_5173_Datasheet.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -29 -25 -Package_DFN_QFN -QFN-24-1EP_5x5mm_P0.65mm_EP3.4x3.4mm_ThermalVias -QFN, 24 Pin (http://www.thatcorp.com/datashts/THAT_5173_Datasheet.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -39 -25 -Package_DFN_QFN -QFN-24-1EP_5x5mm_P0.65mm_EP3.6x3.6mm -QFN, 24 Pin (https://www.nxp.com/docs/en/package-information/98ASA00734D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -34 -25 -Package_DFN_QFN -QFN-24-1EP_5x5mm_P0.65mm_EP3.6x3.6mm_ThermalVias -QFN, 24 Pin (https://www.nxp.com/docs/en/package-information/98ASA00734D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -67 -25 -Package_DFN_QFN -QFN-28-1EP_3x6mm_P0.5mm_EP1.7x4.75mm -QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081926_0_UDE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -37 -29 -Package_DFN_QFN -QFN-28-1EP_3x6mm_P0.5mm_EP1.7x4.75mm_ThermalVias -QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081926_0_UDE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -53 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.4mm_EP2.3x2.3mm -QFN, 28 Pin (http://www.issi.com/WW/pdf/31FL3731.pdf#page=21), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -33 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.4mm_EP2.3x2.3mm_ThermalVias -QFN, 28 Pin (http://www.issi.com/WW/pdf/31FL3731.pdf#page=21), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -43 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.4mm_EP2.4x2.4mm -QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=280), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -33 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.4mm_EP2.4x2.4mm_ThermalVias -QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=280), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -43 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.4mm_EP2.6x2.6mm -QFN, 28 Pin (package code T2844-1; https://pdfserv.maximintegrated.com/package_dwgs/21-0139.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -33 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.4mm_EP2.6x2.6mm_ThermalVias -QFN, 28 Pin (package code T2844-1; https://pdfserv.maximintegrated.com/package_dwgs/21-0139.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -43 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm -QFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf#page=16), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -33 -29 -Package_DFN_QFN -QFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm_ThermalVias -QFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf#page=16), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -43 -29 -Package_DFN_QFN -QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm -QFN, 28 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/3555fe.pdf#page=32), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -35 -29 -Package_DFN_QFN -QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm_ThermalVias -QFN, 28 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/3555fe.pdf#page=32), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -48 -29 -Package_DFN_QFN -QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm -QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=283), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -38 -29 -Package_DFN_QFN -QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm_ThermalVias -QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=283), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -55 -29 -Package_DFN_QFN -QFN-28-1EP_5x6mm_P0.5mm_EP3.65x4.65mm -QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081932_0_UHE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -41 -29 -Package_DFN_QFN -QFN-28-1EP_5x6mm_P0.5mm_EP3.65x4.65mm_ThermalVias -QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081932_0_UHE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -62 -29 -Package_DFN_QFN -QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm -QFN, 28 Pin (https://www.semtech.com/uploads/documents/sx1272.pdf#page=125), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -38 -29 -Package_DFN_QFN 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(http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8153-8-and-16-bit-avr-microcontroller-xmega-e-atxmega8e5-atxmega16e5-atxmega32e5_datasheet.pdf (Page 70)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -37 -33 -Package_DFN_QFN -QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm_ThermalVias -QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8153-8-and-16-bit-avr-microcontroller-xmega-e-atxmega8e5-atxmega16e5-atxmega32e5_datasheet.pdf (Page 70)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -47 -33 -Package_DFN_QFN -QFN-32-1EP_4x4mm_P0.4mm_EP2.65x2.65mm -QFN, 32 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/l32.4x4a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -37 -33 -Package_DFN_QFN -QFN-32-1EP_4x4mm_P0.4mm_EP2.65x2.65mm_ThermalVias -QFN, 32 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/l32.4x4a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -59 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm -QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf (Page 20)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -42 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias -QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf (Page 20)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -59 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.6x3.6mm -QFN, 32 Pin (http://infocenter.nordicsemi.com/pdf/nRF52810_PS_v1.1.pdf (Page 468)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -42 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.6x3.6mm_ThermalVias -QFN, 32 Pin (http://infocenter.nordicsemi.com/pdf/nRF52810_PS_v1.1.pdf (Page 468)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -59 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm -QFN, 32 Pin (https://www.espressif.com/sites/default/files/documentation/0a-esp8285_datasheet_en.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -37 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm_ThermalVias -QFN, 32 Pin (https://www.espressif.com/sites/default/files/documentation/0a-esp8285_datasheet_en.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -59 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm -QFN, 32 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_32_05-08-1693.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -42 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm_ThermalVias -QFN, 32 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_32_05-08-1693.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -59 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.65x3.65mm -QFN, 32 Pin (https://www.exar.com/ds/mxl7704.pdf (Page 35)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -42 -33 -Package_DFN_QFN -QFN-32-1EP_5x5mm_P0.5mm_EP3.65x3.65mm_ThermalVias -QFN, 32 Pin (https://www.exar.com/ds/mxl7704.pdf (Page 35)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -59 -33 -Package_DFN_QFN -QFN-32-1EP_7x7mm_P0.65mm_EP4.7x4.7mm -QFN, 32 Pin (https://www.nxp.com/docs/en/data-sheet/LPC111X.pdf (Page 108)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -49 -33 -Package_DFN_QFN -QFN-32-1EP_7x7mm_P0.65mm_EP4.7x4.7mm_ThermalVias -QFN, 32 Pin (https://www.nxp.com/docs/en/data-sheet/LPC111X.pdf (Page 108)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -75 -33 -Package_DFN_QFN -QFN-32-1EP_7x7mm_P0.65mm_EP4.65x4.65mm -QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8209-8-bit%20AVR%20ATmega16M1-32M1-64M1_Datasheet.pdf (Page 426)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -49 -33 -Package_DFN_QFN -QFN-32-1EP_7x7mm_P0.65mm_EP4.65x4.65mm_ThermalVias -QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8209-8-bit%20AVR%20ATmega16M1-32M1-64M1_Datasheet.pdf (Page 426)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -75 -33 -Package_DFN_QFN -QFN-32-1EP_7x7mm_P0.65mm_EP5.4x5.4mm -QFN, 32 Pin (http://www.thatcorp.com/datashts/THAT_5171_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -49 -33 -Package_DFN_QFN -QFN-32-1EP_7x7mm_P0.65mm_EP5.4x5.4mm_ThermalVias -QFN, 32 Pin (http://www.thatcorp.com/datashts/THAT_5171_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 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(https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UHE36)%20QFN%2005-08-1876%20Rev%20%C3%98.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -56 -37 -Package_DFN_QFN -QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm -QFN, 36 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/36L_QFN_6x6_with_3_7x3_7_EP_Punch_Dimpled_4E_C04-0241A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -46 -37 -Package_DFN_QFN -QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm_ThermalVias -QFN, 36 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/36L_QFN_6x6_with_3_7x3_7_EP_Punch_Dimpled_4E_C04-0241A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -63 -37 -Package_DFN_QFN -QFN-36-1EP_6x6mm_P0.5mm_EP4.1x4.1mm -QFN, 36 Pin (www.st.com/resource/en/datasheet/stm32f101t6.pdf (page 72)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -46 -37 -Package_DFN_QFN -QFN-36-1EP_6x6mm_P0.5mm_EP4.1x4.1mm_ThermalVias -QFN, 36 Pin (www.st.com/resource/en/datasheet/stm32f101t6.pdf (page 72)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -63 -37 -Package_DFN_QFN -QFN-38-1EP_4x6mm_P0.4mm_EP2.65x4.65mm -QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1750.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -47 -39 -Package_DFN_QFN -QFN-38-1EP_4x6mm_P0.4mm_EP2.65x4.65mm_ThermalVias -QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1750.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -56 -39 -Package_DFN_QFN -QFN-38-1EP_5x7mm_P0.5mm_EP3.15x5.15mm -QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1701.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -54 -39 -Package_DFN_QFN -QFN-38-1EP_5x7mm_P0.5mm_EP3.15x5.15mm_ThermalVias -QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1701.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -63 -39 -Package_DFN_QFN -QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm -QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=297), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -50 -41 -Package_DFN_QFN -QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm_ThermalVias -QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=297), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -67 -41 -Package_DFN_QFN -QFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm -QFN, 40 Pin (http://www.issi.com/WW/pdf/31FL3736.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -50 -41 -Package_DFN_QFN -QFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm_ThermalVias -QFN, 40 Pin (http://www.issi.com/WW/pdf/31FL3736.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -67 -41 -Package_DFN_QFN -QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm -QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=295), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -57 -41 -Package_DFN_QFN -QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm_ThermalVias -QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=295), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -83 -41 -Package_DFN_QFN -QFN-42-1EP_5x6mm_P0.4mm_EP3.7x4.7mm -QFN, 42 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081875_0_UHE42.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -55 -43 -Package_DFN_QFN -QFN-42-1EP_5x6mm_P0.4mm_EP3.7x4.7mm_ThermalVias -QFN, 42 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081875_0_UHE42.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -76 -43 -Package_DFN_QFN -QFN-44-1EP_7x7mm_P0.5mm_EP5.2x5.2mm -QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/2512S.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -61 -45 -Package_DFN_QFN -QFN-44-1EP_7x7mm_P0.5mm_EP5.2x5.2mm_ThermalVias -QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/2512S.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -87 -45 -Package_DFN_QFN -QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm -QFN, 44 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_44_05-08-1763.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -61 -45 -Package_DFN_QFN -QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias -QFN, 44 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_44_05-08-1763.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -87 -45 -Package_DFN_QFN -QFN-44-1EP_8x8mm_P0.65mm_EP6.45x6.45mm -QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf#page=152), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -70 -45 -Package_DFN_QFN -QFN-44-1EP_8x8mm_P0.65mm_EP6.45x6.45mm_ThermalVias -QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf#page=152), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -107 -45 -Package_DFN_QFN -QFN-44-1EP_9x9mm_P0.65mm_EP7.5x7.5mm -44-Lead Plastic Quad Flat, No Lead Package - 9x9 mm Body [QFN]; see section 10.3 of https://www.parallax.com/sites/default/files/downloads/P8X32A-Propeller-Datasheet-v1.4.0_0.pdf -QFN 0.65 -0 -49 -45 -Package_DFN_QFN -QFN-44-1EP_9x9mm_P0.65mm_EP7.5x7.5mm_ThermalVias -44-Lead Plastic Quad Flat, No Lead Package - 9x9 mm Body [QFN] with thermal vias; see section 10.3 of https://www.parallax.com/sites/default/files/downloads/P8X32A-Propeller-Datasheet-v1.4.0_0.pdf -QFN 0.65 -0 -55 -45 -Package_DFN_QFN -QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm -QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -58 -49 -Package_DFN_QFN -QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm_ThermalVias -QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -75 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm -QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -58 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm_ThermalVias -QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.3x4.3mm -QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -58 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.3x4.3mm_ThermalVias -QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -75 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm -QFN, 48 Pin (http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.3.pdf#page=67), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -58 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm_ThermalVias -QFN, 48 Pin (http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.3.pdf#page=67), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.66x4.66mm -QFN, 48 Pin (https://www.onsemi.com/pub/Collateral/485BA.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -58 -49 -Package_DFN_QFN -QFN-48-1EP_6x6mm_P0.4mm_EP4.66x4.66mm_ThermalVias -QFN, 48 Pin (https://www.onsemi.com/pub/Collateral/485BA.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm -QFN, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2041_datasheet.pdf#page=62), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -65 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm_ThermalVias -QFN, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2041_datasheet.pdf#page=62), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm -QFN, 48 Pin (http://www.st.com/resource/en/datasheet/stm32f042k6.pdf#page=94), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -65 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm_ThermalVias -QFN, 48 Pin (http://www.st.com/resource/en/datasheet/stm32f042k6.pdf#page=94), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm -QFN, 48 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_48_05-08-1704.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -65 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias -QFN, 48 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_48_05-08-1704.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.45x5.45mm -QFN, 48 Pin (http://www.thatcorp.com/datashts/THAT_626x_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -65 -49 -Package_DFN_QFN -QFN-48-1EP_7x7mm_P0.5mm_EP5.45x5.45mm_ThermalVias -QFN, 48 Pin (http://www.thatcorp.com/datashts/THAT_626x_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -49 -Package_DFN_QFN -QFN-48-1EP_8x8mm_P0.5mm_EP6.2x6.2mm -QFN, 48 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf#page=49), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -74 -49 -Package_DFN_QFN -QFN-48-1EP_8x8mm_P0.5mm_EP6.2x6.2mm_ThermalVias -QFN, 48 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf#page=49), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -111 -49 -Package_DFN_QFN -QFN-52-1EP_7x8mm_P0.5mm_EP5.41x6.45mm -QFN, 52 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_52_05-08-1729.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -73 -53 -Package_DFN_QFN -QFN-52-1EP_7x8mm_P0.5mm_EP5.41x6.45mm_ThermalVias -QFN, 52 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_52_05-08-1729.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -104 -53 -Package_DFN_QFN -QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm -QFN, 56 Pin (http://www.cypress.com/file/416486/download#page=40), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -73 -57 -Package_DFN_QFN -QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm_ThermalVias -QFN, 56 Pin (http://www.cypress.com/file/416486/download#page=40), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -99 -57 -Package_DFN_QFN -QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm -QFN, 56 Pin (http://www.ti.com/lit/an/scea032/scea032.pdf#page=4), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -73 -57 -Package_DFN_QFN -QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm_ThermalVias -QFN, 56 Pin (http://www.ti.com/lit/an/scea032/scea032.pdf#page=4), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -99 -57 -Package_DFN_QFN -QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm_ThermalVias_TopTented -QFN, 56 Pin top tented version (manually modified). For information see: http://www.cypress.com/file/138911/download -QFN DFN_QFN -0 -115 -57 -Package_DFN_QFN -QFN-56-1EP_8x8mm_P0.5mm_EP5.6x5.6mm -QFN, 56 Pin (http://www.ti.com/lit/ds/symlink/tlc5957.pdf#page=23), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -73 -57 -Package_DFN_QFN -QFN-56-1EP_8x8mm_P0.5mm_EP5.6x5.6mm_ThermalVias -QFN, 56 Pin (http://www.ti.com/lit/ds/symlink/tlc5957.pdf#page=23), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -99 -57 -Package_DFN_QFN -QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_8x8_with%206_5x6_5%20EP_JXX_C04-0437A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -90 -65 -Package_DFN_QFN -QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm_ThermalVias -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_8x8_with%206_5x6_5%20EP_JXX_C04-0437A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -127 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP3.8x3.8mm -QFN, 64 Pin (https://datasheet.lcsc.com/szlcsc/Realtek-Semicon-RTL8211EG-VB-CG_C69264.pdf#page=77), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -74 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP3.8x3.8mm_ThermalVias -QFN, 64 Pin (https://datasheet.lcsc.com/szlcsc/Realtek-Semicon-RTL8211EG-VB-CG_C69264.pdf#page=77), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -79 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP4.7x4.7mm -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/60001477A.pdf (page 1083)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -74 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP4.7x4.7mm_ThermalVias -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/60001477A.pdf (page 1083)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -91 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP4.35x4.35mm -QFN, 64 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf#page=57), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -74 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP4.35x4.35mm_ThermalVias -QFN, 64 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf#page=57), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -91 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP5.4x5.4mm -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/70593d.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -81 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP5.4x5.4mm_ThermalVias -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/70593d.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -107 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP5.45x5.45mm -QFN, 64 Pin (https://www.infineon.com/dgdl/Infineon-MA12040-DS-v01_00-EN.pdf?fileId=5546d46264a8de7e0164b7467a3d617c#page=81), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -81 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP5.45x5.45mm_ThermalVias -QFN, 64 Pin (https://www.infineon.com/dgdl/Infineon-MA12040-DS-v01_00-EN.pdf?fileId=5546d46264a8de7e0164b7467a3d617c#page=81), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -107 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm -QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/tusb8041.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -81 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm_ThermalVias -QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/tusb8041.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -107 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.3x7.3mm -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00002304A.pdf (page 43)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -90 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.3x7.3mm_ThermalVias -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00002304A.pdf (page 43)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -127 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.5x7.5mm -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc7593.pdf (page 432)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -101 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.5x7.5mm_ThermalVias -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc7593.pdf (page 432)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -151 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.15x7.15mm -QFN, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/229321fa.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -90 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.15x7.15mm_ThermalVias -QFN, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/229321fa.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -127 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.25x7.25mm -64-Lead Plastic Quad Flat No-Lead Package, 9x9mm Body (see Atmel Appnote 8826) -QFN 0.5 -0 -90 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.35x7.35mm -64-Lead Plastic Quad Flat, No Lead Package (MR) - 9x9x0.9 mm Body [QFN]; (see Microchip Packaging Specification 00000049BS.pdf) -QFN 0.5 -0 -90 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.65x7.65mm -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2549-8-bit-AVR-Microcontroller-ATmega640-1280-1281-2560-2561_datasheet.pdf (page 415)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -101 -65 -Package_DFN_QFN -QFN-64-1EP_9x9mm_P0.5mm_EP7.65x7.65mm_ThermalVias -QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2549-8-bit-AVR-Microcontroller-ATmega640-1280-1281-2560-2561_datasheet.pdf (page 415)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -151 -65 -Package_DFN_QFN -QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm -QFN, 68 Pin (https://cdn.microsemi.com/documents/1bf6886f-5919-4508-a50b-b1dbf3fdf0f4/download/#page=98), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -85 -69 -Package_DFN_QFN -QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm_ThermalVias -QFN, 68 Pin (https://cdn.microsemi.com/documents/1bf6886f-5919-4508-a50b-b1dbf3fdf0f4/download/#page=98), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -111 -69 -Package_DFN_QFN -QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm -QFN, 72 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001682C.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -82 -73 -Package_DFN_QFN -QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm_ThermalVias -QFN, 72 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001682C.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -135 -73 -Package_DFN_QFN -QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm -QFN, 76 Pin (https://www.marvell.com/documents/bqcwxsoiqfjkcjdjhkvc/#page=19), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -86 -77 -Package_DFN_QFN -QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm_ThermalVias -QFN, 76 Pin (https://www.marvell.com/documents/bqcwxsoiqfjkcjdjhkvc/#page=19), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -QFN DFN_QFN -0 -103 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(http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40) -QFN NoLead -0 -29 -25 -Package_DFN_QFN -Texas_RGY_R-PVQFN-N24_EP2.05x3.1mm_ThermalVias -QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40) -QFN NoLead -0 -36 -25 -Package_DFN_QFN -Texas_RNN0018A -Texas Instruments, VQFN-HR RNN0018A (http://www.ti.com/lit/ds/symlink/tps568215.pdf) -ti vqfn-hr rnn0018a -0 -26 -18 -Package_DFN_QFN -Texas_RUM0016A_EP2.6x2.6mm -QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -21 -17 -Package_DFN_QFN -Texas_RUM0016A_EP2.6x2.6mm_ThermalVias -QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -31 -17 -Package_DFN_QFN -Texas_RWH0032A -Texas Instruments, RWH0032A, 8x8x0.9mm (http://www.ti.com/lit/ds/snosd10c/snosd10c.pdf) -ti rwh0032a -0 -71 -33 -Package_DFN_QFN -Texas_RWH0032A_ThermalVias -Texas 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ipc_noLead_generator.py -QFN NoLead -0 -25 -21 -Package_DFN_QFN -Texas_S-PVQFN-N20_EP2.7x2.7mm_ThermalVias -QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/drv8662.pdf#page=23), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -35 -21 -Package_DFN_QFN -Texas_S-PVQFN-N20_EP3.15x3.15mm -QFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -25 -21 -Package_DFN_QFN -Texas_S-PVQFN-N20_EP3.15x3.15mm_ThermalVias -QFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -47 -21 -Package_DFN_QFN -Texas_S-PVQFN-N24_EP2.1x2.1mm -QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5720.pdf#page=111), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -29 -25 -Package_DFN_QFN -Texas_S-PVQFN-N24_EP2.1x2.1mm_ThermalVias -QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5720.pdf#page=111), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -39 -25 -Package_DFN_QFN -Texas_S-PVQFN-N32_EP3.45x3.45mm -QFN, 32 Pin (http://www.ti.com/lit/ds/symlink/msp430f1122.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -42 -33 -Package_DFN_QFN -Texas_S-PVQFN-N32_EP3.45x3.45mm_ThermalVias -QFN, 32 Pin (http://www.ti.com/lit/ds/symlink/msp430f1122.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -59 -33 -Package_DFN_QFN -Texas_S-PVQFN-N36_EP4.4x4.4mm -QFN, 36 Pin (http://www.ti.com/lit/ds/slvsba5d/slvsba5d.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -46 -37 -Package_DFN_QFN -Texas_S-PVQFN-N36_EP4.4x4.4mm_ThermalVias -QFN, 36 Pin (http://www.ti.com/lit/ds/slvsba5d/slvsba5d.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -79 -37 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP2.9x2.9mm -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5731.pdf#page=114), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -45 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP2.9x2.9mm_ThermalVias -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5731.pdf#page=114), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -55 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP3.52x2.62mm -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/drv8308.pdf#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -47 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP3.52x2.62mm_ThermalVias -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/drv8308.pdf#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -60 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP4.6x4.6mm -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/dac7750.pdf#page=55), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -50 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP4.6x4.6mm_ThermalVias -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/dac7750.pdf#page=55), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -83 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP4.15x4.15mm -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -50 -41 -Package_DFN_QFN -Texas_S-PVQFN-N40_EP4.15x4.15mm_ThermalVias -QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -83 -41 -Package_DFN_QFN -Texas_S-PVQFN-N48_EP5.15x5.15mm -QFN, 48 Pin (http://www.ti.com/lit/ds/symlink/msp430f5232.pdf#page=112), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -65 -49 -Package_DFN_QFN -Texas_S-PVQFN-N48_EP5.15x5.15mm_ThermalVias -QFN, 48 Pin (http://www.ti.com/lit/ds/symlink/msp430f5232.pdf#page=112), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -111 -49 -Package_DFN_QFN -Texas_S-PVQFN-N64_EP4.25x4.25mm -QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/msp430f5217.pdf#page=117), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -69 -65 -Package_DFN_QFN -Texas_S-PVQFN-N64_EP4.25x4.25mm_ThermalVias -QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/msp430f5217.pdf#page=117), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -127 -65 -Package_DFN_QFN -Texas_S-PWQFN-N16_EP2.1x2.1mm -QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -21 -17 -Package_DFN_QFN -Texas_S-PWQFN-N16_EP2.1x2.1mm_ThermalVias -QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -31 -17 -Package_DFN_QFN -Texas_S-PWQFN-N20 -20-Pin Plastic Quad Flatpack No-Lead Package, Body 3.0x3.0x0.8mm, Texas Instruments (http://www.ti.com/lit/ds/symlink/tps22993.pdf) -QFN 0.4 -0 -24 -20 -Package_DFN_QFN -Texas_S-PWQFN-N24_EP2.7x2.7mm -QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -29 -25 -Package_DFN_QFN -Texas_S-PWQFN-N24_EP2.7x2.7mm_ThermalVias -QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -39 -25 -Package_DFN_QFN -Texas_S-PWQFN-N32_EP2.8x2.8mm -QFN, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=91), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -37 -33 -Package_DFN_QFN -Texas_S-PWQFN-N32_EP2.8x2.8mm_ThermalVias -QFN, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=91), generated with kicad-footprint-generator ipc_noLead_generator.py -QFN NoLead -0 -47 -33 -Package_DFN_QFN -Texas_S-PWQFN-N100_EP5.5x5.5mm -http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/lit/ds/sllse76m/sllse76m.pdf -MultiRow QFN -0 -114 -105 -Package_DFN_QFN -Texas_S-PWQFN-N100_EP5.5x5.5mm_ThermalVias -http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/lit/ds/sllse76m/sllse76m.pdf -MultiRow QFN -0 -131 -105 -Package_DFN_QFN -Texas_S-PX2QFN-14 -Texas QFN, 14 Pin (http://www.ti.com/lit/ds/symlink/tlv9004.pdf#page=64), generated with kicad-footprint-generator ipc_noLead_generator.py -Texas QFN NoLead -0 -14 -14 -Package_DFN_QFN -Texas_VQFN-RHL-20 -http://www.ti.com/lit/ds/symlink/bq51050b.pdf -RHL0020A -0 -33 -21 -Package_DFN_QFN -Texas_VQFN-RHL-20_ThermalVias -http://www.ti.com/lit/ds/symlink/bq51050b.pdf -RHL0020A -0 -41 -21 -Package_DFN_QFN -Texas_VSON-HR-8_1.5x2mm_P0.5mm -Texas VSON-HR, 8 Pin (http://www.ti.com/lit/ds/symlink/tps62823.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py -Texas VSON-HR NoLead -0 -8 -8 -Package_DFN_QFN -Texas_WQFN-MR-100_3x3-DapStencil -http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=mpqf258&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=LPPD235&fileType=pdf -MultiRow QFN -0 -113 -105 -Package_DFN_QFN -Texas_WQFN-MR-100_ThermalVias_3x3-DapStencil -http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=mpqf258&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=LPPD235&fileType=pdf -MultiRow QFN -0 -126 -105 -Package_DFN_QFN -Texas_X2QFN-12_1.6x1.6mm_P0.4mm -Texas X2QFN, 12 Pin (http://www.ti.com/lit/ml/mpqf391c/mpqf391c.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -Texas X2QFN DFN_QFN -0 -12 -12 -Package_DFN_QFN -UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm -UDFN-4_1x1mm_P0.65mm, http://ww1.microchip.com/downloads/en/DeviceDoc/MIC550x-300mA-Single-Output-LDO-in-Small-Packages-DS20006006A.pdf -UDFN-4_1x1mm_P0.65mm -0 -5 -5 -Package_DFN_QFN -UDFN-9_1.0x3.8mm_P0.5mm -9-pin UDFN package, 1.0x3.8mm, (Ref: https://katalog.we-online.de/pbs/datasheet/824014881.pdf) -UDFN SMD -0 -9 -9 -Package_DFN_QFN -UDFN-10_1.35x2.6mm_P0.5mm -http://www.st.com/content/ccc/resource/technical/document/datasheet/f2/11/8a/ed/40/31/40/56/DM00088292.pdf/files/DM00088292.pdf/jcr:content/translations/en.DM00088292.pdf -UDFN 0.5 uQFN -0 -10 -10 -Package_DFN_QFN -UQFN-10_1.3x1.8mm_P0.4mm -UQFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 9)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -UQFN DFN_QFN -0 -10 -10 -Package_DFN_QFN -UQFN-10_1.4x1.8mm_P0.4mm -UQFN 10pin, https://www.onsemi.com/pub/Collateral/488AT.PDF -UQFN-10_1.4x1.8mm_P0.4mm -0 -10 -10 -Package_DFN_QFN -UQFN-10_1.6x2.1mm_P0.5mm -UQFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 12)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -UQFN DFN_QFN -0 -10 -10 -Package_DFN_QFN -UQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm -16-Lead Ultra Thin Quad Flat, No Lead Package (UC) - 3x3x0.5 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf) -QFN 0.5 -0 -21 -17 -Package_DFN_QFN -UQFN-16-1EP_4x4mm_P0.65mm_EP2.6x2.6mm -UQFN, 16 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/16L_UQFN_4x4x0_5mm_JQ_C04257A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -UQFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -UQFN-16-1EP_4x4mm_P0.65mm_EP2.6x2.6mm_ThermalVias -UQFN, 16 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/16L_UQFN_4x4x0_5mm_JQ_C04257A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -UQFN DFN_QFN -0 -31 -17 -Package_DFN_QFN -UQFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm -16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf) -QFN 0.65 -0 -21 -17 -Package_DFN_QFN -UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm -UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=332), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -25 -21 -Package_DFN_QFN -UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm_ThermalVias -UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=332), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -30 -21 -Package_DFN_QFN -UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm -UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -25 -21 -Package_DFN_QFN -UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_ThermalVias -UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -35 -21 -Package_DFN_QFN -UQFN-28-1EP_4x4mm_P0.4mm_EP2.35x2.35mm -UQFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=338), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -33 -29 -Package_DFN_QFN -UQFN-28-1EP_4x4mm_P0.4mm_EP2.35x2.35mm_ThermalVias -UQFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=338), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -43 -29 -Package_DFN_QFN -UQFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm -UQFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=345), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -50 -41 -Package_DFN_QFN -UQFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm_ThermalVias -UQFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=345), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -67 -41 -Package_DFN_QFN -UQFN-48-1EP_6x6mm_P0.4mm_EP4.45x4.45mm -UQFN, 48 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=347), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -58 -49 -Package_DFN_QFN -UQFN-48-1EP_6x6mm_P0.4mm_EP4.45x4.45mm_ThermalVias -UQFN, 48 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=347), generated with kicad-footprint-generator ipc_noLead_generator.py -UQFN NoLead -0 -75 -49 -Package_DFN_QFN -UQFN-48-1EP_6x6mm_P0.4mm_EP4.62x4.62mm -UQFN, 48 Pin (https://github.com/KiCad/kicad-symbols/pull/1189#issuecomment-449506354), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -UQFN DFN_QFN -0 -53 -49 -Package_DFN_QFN -UQFN-48-1EP_6x6mm_P0.4mm_EP4.62x4.62mm_ThermalVias -UQFN, 48 Pin (https://github.com/KiCad/kicad-symbols/pull/1189#issuecomment-449506354), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -UQFN DFN_QFN -0 -75 -49 -Package_DFN_QFN -VDFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.7mm -8-Lead Very Thin Dual Flatpack No-Lead (LZ) - 2x3x0.9 mm Body [VDFN] (see Microchip Packaging Specification 00000049BS.pdf) -DFN 0.5 -0 -11 -9 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm -VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/cdclvp1102.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -21 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias -VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/cdclvp1102.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -26 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm -VQFN, 16 Pin (https://www.st.com/resource/en/datasheet/stspin220.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm_ThermalVias -VQFN, 16 Pin (https://www.st.com/resource/en/datasheet/stspin220.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -26 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm -VQFN, 16 Pin (http://www.ti.com/lit/ds/sbos354a/sbos354a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm_ThermalVias -VQFN, 16 Pin (http://www.ti.com/lit/ds/sbos354a/sbos354a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -26 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.68x1.68mm -VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/tlv62095.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -21 -17 -Package_DFN_QFN -VQFN-16-1EP_3x3mm_P0.5mm_EP1.68x1.68mm_ThermalVias -VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/tlv62095.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -26 -17 -Package_DFN_QFN -VQFN-20-1EP_3x3mm_P0.4mm_EP1.7x1.7mm -VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -25 -21 -Package_DFN_QFN -VQFN-20-1EP_3x3mm_P0.4mm_EP1.7x1.7mm_ThermalVias -VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -30 -21 -Package_DFN_QFN -VQFN-20-1EP_3x3mm_P0.45mm_EP1.55x1.55mm -VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=264), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -25 -21 -Package_DFN_QFN -VQFN-20-1EP_3x3mm_P0.45mm_EP1.55x1.55mm_ThermalVias -VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=264), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -30 -21 -Package_DFN_QFN -VQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm -VQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430f1101a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -34 -25 -Package_DFN_QFN -VQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias -VQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430f1101a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -39 -25 -Package_DFN_QFN -VQFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm -VQFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-9505-AT42-QTouch-BSW-AT42QT1060_Datasheet.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -33 -29 -Package_DFN_QFN -VQFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm_ThermalVias -VQFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-9505-AT42-QTouch-BSW-AT42QT1060_Datasheet.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -43 -29 -Package_DFN_QFN -VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm -VQFN, 28 Pin (http://www.ti.com/lit/ds/symlink/lm5175.pdf#page=37), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -35 -29 -Package_DFN_QFN -VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm_ThermalVias -VQFN, 28 Pin (http://www.ti.com/lit/ds/symlink/lm5175.pdf#page=37), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py -VQFN DFN_QFN -0 -48 -29 -Package_DFN_QFN -VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm -VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/devicedoc/atmel-9520-at42-qtouch-bsw-at42qt1110_datasheet.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -37 -33 -Package_DFN_QFN -VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias -VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/devicedoc/atmel-9520-at42-qtouch-bsw-at42qt1110_datasheet.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -47 -33 -Package_DFN_QFN -VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm -VQFN, 32 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf#page=40), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -37 -33 -Package_DFN_QFN -VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm_ThermalVias -VQFN, 32 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf#page=40), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -47 -33 -Package_DFN_QFN -VQFN-46-1EP_5x6mm_P0.4mm_EP2.8x3.8mm -VQFN, 46 Pin (http://www.ti.com/lit/ds/symlink/lp5036.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -53 -47 -Package_DFN_QFN -VQFN-46-1EP_5x6mm_P0.4mm_EP2.8x3.8mm_ThermalVias -VQFN, 46 Pin (http://www.ti.com/lit/ds/symlink/lp5036.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -66 -47 -Package_DFN_QFN -VQFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm -VQFN, 48 Pin (http://www.ti.com/lit/ds/symlink/cc1312r.pdf#page=48), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -53 -49 -Package_DFN_QFN -VQFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias -VQFN, 48 Pin (http://www.ti.com/lit/ds/symlink/cc1312r.pdf#page=48), generated with kicad-footprint-generator ipc_noLead_generator.py -VQFN NoLead -0 -79 -49 -Package_DFN_QFN -WDFN-8-1EP_2x2.2mm_P0.5mm_EP0.80x0.54 -https://www.onsemi.com/pub/Collateral/511BN.PDF -WDFN-8 1EP 2.2X2.0 0.5P -0 -9 -9 -Package_DFN_QFN -WDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm -WDFN, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MNY_C04-0129E-MNY.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -WDFN NoLead -0 -13 -9 -Package_DFN_QFN -WDFN-8_2x2mm_P0.5mm -DFN8 2x2, 0.5P; No exposed pad (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF) -DFN 0.5 -0 -8 -8 -Package_DFN_QFN -WDFN-12-1EP_3x3mm_P0.45mm_EP1.7x2.5mm -WDFN, 12 Pin (https://www.diodes.com/assets/Datasheets/PAM2306.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py -WDFN NoLead -0 -17 -13 -Package_DFN_QFN -WQFN-14-1EP_2.5x2.5mm_P0.5mm_EP1.45x1.45mm -WQFN, 14 Pin (https://www.onsemi.com/pub/Collateral/FUSB302B-D.PDF#page=32), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -19 -15 -Package_DFN_QFN -WQFN-14-1EP_2.5x2.5mm_P0.5mm_EP1.45x1.45mm_ThermalVias -WQFN, 14 Pin (https://www.onsemi.com/pub/Collateral/FUSB302B-D.PDF#page=32), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -24 -15 -Package_DFN_QFN -WQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm -WQFN, 16 Pin (https://www.onsemi.com/pub/Collateral/FUSB307B-D.PDF#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -21 -17 -Package_DFN_QFN -WQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm_ThermalVias -WQFN, 16 Pin (https://www.onsemi.com/pub/Collateral/FUSB307B-D.PDF#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -26 -17 -Package_DFN_QFN -WQFN-16-1EP_4x4mm_P0.5mm_EP2.6x2.6mm -WQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -21 -17 -Package_DFN_QFN -WQFN-16-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias -WQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -31 -17 -Package_DFN_QFN -WQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x2.9mm -http://www.onsemi.com/pub/Collateral/510CD.PDF -WQFN-20 4.5mm 2.5mm 0.5mm -0 -24 -21 -Package_DFN_QFN -WQFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm -WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/lm26480.pdf#page=39), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -29 -25 -Package_DFN_QFN -WQFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias -WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/lm26480.pdf#page=39), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -39 -25 -Package_DFN_QFN -WQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm -WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/ts3a27518e.pdf#page=33), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -29 -25 -Package_DFN_QFN -WQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias -WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/ts3a27518e.pdf#page=33), generated with kicad-footprint-generator ipc_noLead_generator.py -WQFN NoLead -0 -39 -25 -Package_DFN_QFN -WQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm -QFN, 32-Leads, Body 5x5x0.8mm, Pitch 0.5mm, Thermal Pad 3.1x3.1mm; (see Texas Instruments LM25119 http://www.ti.com/lit/ds/symlink/lm25119.pdf) -WQFN 0.5 -0 -37 -33 -Package_DIP -DIP-4_W7.62mm -4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -4 -4 -Package_DIP -DIP-4_W7.62mm_LongPads -4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -4 -4 -Package_DIP -DIP-4_W7.62mm_SMDSocket_SmallPads -4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -4 -4 -Package_DIP -DIP-4_W7.62mm_Socket -4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -4 -4 -Package_DIP -DIP-4_W7.62mm_Socket_LongPads -4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -4 -4 -Package_DIP -DIP-4_W8.89mm_SMDSocket_LongPads -4-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -4 -4 -Package_DIP -DIP-4_W10.16mm -4-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -4 -4 -Package_DIP -DIP-4_W10.16mm_LongPads -4-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -4 -4 -Package_DIP -DIP-5-6_W7.62mm -5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -5 -5 -Package_DIP -DIP-5-6_W7.62mm_LongPads -5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -5 -5 -Package_DIP -DIP-5-6_W7.62mm_SMDSocket_SmallPads -5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -5 -5 -Package_DIP -DIP-5-6_W7.62mm_Socket -5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -5 -5 -Package_DIP -DIP-5-6_W7.62mm_Socket_LongPads -5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -5 -5 -Package_DIP -DIP-5-6_W8.89mm_SMDSocket_LongPads -5-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -5 -5 -Package_DIP -DIP-5-6_W10.16mm -5-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -5 -5 -Package_DIP -DIP-5-6_W10.16mm_LongPads -5-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -5 -5 -Package_DIP -DIP-6_W7.62mm -6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -6 -6 -Package_DIP -DIP-6_W7.62mm_LongPads -6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -6 -6 -Package_DIP -DIP-6_W7.62mm_SMDSocket_SmallPads -6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -6 -6 -Package_DIP -DIP-6_W7.62mm_Socket -6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -6 -6 -Package_DIP -DIP-6_W7.62mm_Socket_LongPads -6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -6 -6 -Package_DIP -DIP-6_W8.89mm_SMDSocket_LongPads -6-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -6 -6 -Package_DIP -DIP-6_W10.16mm -6-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -6 -6 -Package_DIP -DIP-6_W10.16mm_LongPads -6-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -6 -6 -Package_DIP -DIP-8-16_W7.62mm -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -8 -8 -Package_DIP -DIP-8-16_W7.62mm_Socket -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -8 -8 -Package_DIP -DIP-8-16_W7.62mm_Socket_LongPads -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -8 -8 -Package_DIP -DIP-8-N6_W7.62mm -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 6 -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -7 -7 -Package_DIP -DIP-8-N7_W7.62mm -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 7 -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -7 -7 -Package_DIP -DIP-8_W7.62mm -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -8 -8 -Package_DIP -DIP-8_W7.62mm_LongPads -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -8 -8 -Package_DIP -DIP-8_W7.62mm_SMDSocket_SmallPads -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -8 -8 -Package_DIP -DIP-8_W7.62mm_Socket -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -8 -8 -Package_DIP -DIP-8_W7.62mm_Socket_LongPads -8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -8 -8 -Package_DIP -DIP-8_W8.89mm_SMDSocket_LongPads -8-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -8 -8 -Package_DIP -DIP-8_W10.16mm -8-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -8 -8 -Package_DIP -DIP-8_W10.16mm_LongPads -8-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -8 -8 -Package_DIP -DIP-10_W7.62mm -10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -10 -10 -Package_DIP -DIP-10_W7.62mm_LongPads -10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -10 -10 -Package_DIP -DIP-10_W7.62mm_SMDSocket_SmallPads -10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -10 -10 -Package_DIP -DIP-10_W7.62mm_Socket -10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -10 -10 -Package_DIP -DIP-10_W7.62mm_Socket_LongPads -10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -10 -10 -Package_DIP -DIP-10_W8.89mm_SMDSocket_LongPads -10-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -10 -10 -Package_DIP -DIP-10_W10.16mm -10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -10 -10 -Package_DIP -DIP-10_W10.16mm_LongPads -10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -10 -10 -Package_DIP -DIP-12_W7.62mm -12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -12 -12 -Package_DIP -DIP-12_W7.62mm_LongPads -12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -12 -12 -Package_DIP -DIP-12_W7.62mm_SMDSocket_SmallPads -12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -12 -12 -Package_DIP -DIP-12_W7.62mm_Socket -12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -12 -12 -Package_DIP -DIP-12_W7.62mm_Socket_LongPads -12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -12 -12 -Package_DIP -DIP-12_W8.89mm_SMDSocket_LongPads -12-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -12 -12 -Package_DIP -DIP-12_W10.16mm -12-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -12 -12 -Package_DIP -DIP-12_W10.16mm_LongPads -12-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -12 -12 -Package_DIP -DIP-14_W7.62mm -14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -14 -14 -Package_DIP -DIP-14_W7.62mm_LongPads -14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -14 -14 -Package_DIP -DIP-14_W7.62mm_SMDSocket_SmallPads -14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -14 -14 -Package_DIP -DIP-14_W7.62mm_Socket -14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -14 -14 -Package_DIP -DIP-14_W7.62mm_Socket_LongPads -14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -14 -14 -Package_DIP -DIP-14_W8.89mm_SMDSocket_LongPads -14-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -14 -14 -Package_DIP -DIP-14_W10.16mm -14-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -14 -14 -Package_DIP -DIP-14_W10.16mm_LongPads -14-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -14 -14 -Package_DIP -DIP-16_W7.62mm -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -16 -16 -Package_DIP -DIP-16_W7.62mm_LongPads -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -16 -16 -Package_DIP -DIP-16_W7.62mm_SMDSocket_SmallPads -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -16 -16 -Package_DIP -DIP-16_W7.62mm_Socket -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -16 -16 -Package_DIP -DIP-16_W7.62mm_Socket_LongPads -16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -16 -16 -Package_DIP -DIP-16_W8.89mm_SMDSocket_LongPads -16-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -16 -16 -Package_DIP -DIP-16_W10.16mm -16-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -16 -16 -Package_DIP -DIP-16_W10.16mm_LongPads -16-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -16 -16 -Package_DIP -DIP-18_W7.62mm -18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -18 -18 -Package_DIP -DIP-18_W7.62mm_LongPads -18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -18 -18 -Package_DIP -DIP-18_W7.62mm_SMDSocket_SmallPads -18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -18 -18 -Package_DIP -DIP-18_W7.62mm_Socket -18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -18 -18 -Package_DIP -DIP-18_W7.62mm_Socket_LongPads -18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -18 -18 -Package_DIP -DIP-18_W8.89mm_SMDSocket_LongPads -18-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -18 -18 -Package_DIP -DIP-20_W7.62mm -20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -20 -20 -Package_DIP -DIP-20_W7.62mm_LongPads -20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -20 -20 -Package_DIP -DIP-20_W7.62mm_SMDSocket_SmallPads -20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -20 -20 -Package_DIP -DIP-20_W7.62mm_Socket -20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -20 -20 -Package_DIP -DIP-20_W7.62mm_Socket_LongPads -20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -20 -20 -Package_DIP -DIP-20_W8.89mm_SMDSocket_LongPads -20-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -20 -20 -Package_DIP -DIP-22_W7.62mm -22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -22 -22 -Package_DIP -DIP-22_W7.62mm_LongPads -22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -22 -22 -Package_DIP -DIP-22_W7.62mm_SMDSocket_SmallPads -22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -22 -22 -Package_DIP -DIP-22_W7.62mm_Socket -22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -22 -22 -Package_DIP -DIP-22_W7.62mm_Socket_LongPads -22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -22 -22 -Package_DIP -DIP-22_W8.89mm_SMDSocket_LongPads -22-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -22 -22 -Package_DIP -DIP-22_W10.16mm -22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -22 -22 -Package_DIP -DIP-22_W10.16mm_LongPads -22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -22 -22 -Package_DIP -DIP-22_W10.16mm_SMDSocket_SmallPads -22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil SMDSocket SmallPads -0 -22 -22 -Package_DIP -DIP-22_W10.16mm_Socket -22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket -THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket -0 -22 -22 -Package_DIP -DIP-22_W10.16mm_Socket_LongPads -22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket LongPads -0 -22 -22 -Package_DIP -DIP-22_W11.43mm_SMDSocket_LongPads -22-lead though-hole mounted DIP package, row spacing 11.43 mm (450 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 11.43mm 450mil SMDSocket LongPads -0 -22 -22 -Package_DIP -DIP-24_W7.62mm -24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -24 -24 -Package_DIP -DIP-24_W7.62mm_LongPads -24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -24 -24 -Package_DIP -DIP-24_W7.62mm_SMDSocket_SmallPads -24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -24 -24 -Package_DIP -DIP-24_W7.62mm_Socket -24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -24 -24 -Package_DIP -DIP-24_W7.62mm_Socket_LongPads -24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -24 -24 -Package_DIP -DIP-24_W8.89mm_SMDSocket_LongPads -24-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -24 -24 -Package_DIP -DIP-24_W10.16mm -24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) -THT DIP DIL PDIP 2.54mm 10.16mm 400mil -0 -24 -24 -Package_DIP -DIP-24_W10.16mm_LongPads -24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads -0 -24 -24 -Package_DIP -DIP-24_W10.16mm_SMDSocket_SmallPads -24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil SMDSocket SmallPads -0 -24 -24 -Package_DIP -DIP-24_W10.16mm_Socket -24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket -THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket -0 -24 -24 -Package_DIP -DIP-24_W10.16mm_Socket_LongPads -24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket LongPads -0 -24 -24 -Package_DIP -DIP-24_W11.43mm_SMDSocket_LongPads -24-lead though-hole mounted DIP package, row spacing 11.43 mm (450 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 11.43mm 450mil SMDSocket LongPads -0 -24 -24 -Package_DIP -DIP-24_W15.24mm -24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -24 -24 -Package_DIP -DIP-24_W15.24mm_LongPads -24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -24 -24 -Package_DIP -DIP-24_W15.24mm_SMDSocket_SmallPads -24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -24 -24 -Package_DIP -DIP-24_W15.24mm_Socket -24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -24 -24 -Package_DIP -DIP-24_W15.24mm_Socket_LongPads -24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -24 -24 -Package_DIP -DIP-24_W16.51mm_SMDSocket_LongPads -24-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -24 -24 -Package_DIP -DIP-28_W7.62mm -28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -28 -28 -Package_DIP -DIP-28_W7.62mm_LongPads -28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -28 -28 -Package_DIP -DIP-28_W7.62mm_SMDSocket_SmallPads -28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads -0 -28 -28 -Package_DIP -DIP-28_W7.62mm_Socket -28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket -0 -28 -28 -Package_DIP -DIP-28_W7.62mm_Socket_LongPads -28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads -0 -28 -28 -Package_DIP -DIP-28_W8.89mm_SMDSocket_LongPads -28-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads -0 -28 -28 -Package_DIP -DIP-28_W15.24mm -28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -28 -28 -Package_DIP -DIP-28_W15.24mm_LongPads -28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -28 -28 -Package_DIP -DIP-28_W15.24mm_SMDSocket_SmallPads -28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -28 -28 -Package_DIP -DIP-28_W15.24mm_Socket -28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -28 -28 -Package_DIP -DIP-28_W15.24mm_Socket_LongPads -28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -28 -28 -Package_DIP -DIP-28_W16.51mm_SMDSocket_LongPads -28-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -28 -28 -Package_DIP -DIP-32_W7.62mm -32-lead dip package, row spacing 7.62 mm (300 mils) -DIL DIP PDIP 2.54mm 7.62mm 300mil -0 -32 -32 -Package_DIP -DIP-32_W15.24mm -32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -32 -32 -Package_DIP -DIP-32_W15.24mm_LongPads -32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -32 -32 -Package_DIP -DIP-32_W15.24mm_SMDSocket_SmallPads -32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -32 -32 -Package_DIP -DIP-32_W15.24mm_Socket -32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -32 -32 -Package_DIP -DIP-32_W15.24mm_Socket_LongPads -32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -32 -32 -Package_DIP -DIP-32_W16.51mm_SMDSocket_LongPads -32-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -32 -32 -Package_DIP -DIP-40_W15.24mm -40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -40 -40 -Package_DIP -DIP-40_W15.24mm_LongPads -40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -40 -40 -Package_DIP -DIP-40_W15.24mm_SMDSocket_SmallPads -40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -40 -40 -Package_DIP -DIP-40_W15.24mm_Socket -40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -40 -40 -Package_DIP -DIP-40_W15.24mm_Socket_LongPads -40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -40 -40 -Package_DIP -DIP-40_W16.51mm_SMDSocket_LongPads -40-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -40 -40 -Package_DIP -DIP-40_W25.4mm -40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils) -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil -0 -40 -40 -Package_DIP -DIP-40_W25.4mm_LongPads -40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), LongPads -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil LongPads -0 -40 -40 -Package_DIP -DIP-40_W25.4mm_SMDSocket_SmallPads -40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil SMDSocket SmallPads -0 -40 -40 -Package_DIP -DIP-40_W25.4mm_Socket -40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket -0 -40 -40 -Package_DIP -DIP-40_W25.4mm_Socket_LongPads -40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket LongPads -0 -40 -40 -Package_DIP -DIP-40_W26.67mm_SMDSocket_LongPads -40-lead though-hole mounted DIP package, row spacing 26.67 mm (1050 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 26.669999999999998mm 1050mil SMDSocket LongPads -0 -40 -40 -Package_DIP -DIP-42_W15.24mm -42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -42 -42 -Package_DIP -DIP-42_W15.24mm_LongPads -42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -42 -42 -Package_DIP -DIP-42_W15.24mm_SMDSocket_SmallPads -42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -42 -42 -Package_DIP -DIP-42_W15.24mm_Socket -42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -42 -42 -Package_DIP -DIP-42_W15.24mm_Socket_LongPads -42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -42 -42 -Package_DIP -DIP-42_W16.51mm_SMDSocket_LongPads -42-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -42 -42 -Package_DIP -DIP-48_W15.24mm -48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -48 -48 -Package_DIP -DIP-48_W15.24mm_LongPads -48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -48 -48 -Package_DIP -DIP-48_W15.24mm_SMDSocket_SmallPads -48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -48 -48 -Package_DIP -DIP-48_W15.24mm_Socket -48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -48 -48 -Package_DIP -DIP-48_W15.24mm_Socket_LongPads -48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -48 -48 -Package_DIP -DIP-48_W16.51mm_SMDSocket_LongPads -48-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -48 -48 -Package_DIP -DIP-64_W15.24mm -64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) -THT DIP DIL PDIP 2.54mm 15.24mm 600mil -0 -64 -64 -Package_DIP -DIP-64_W15.24mm_LongPads -64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads -0 -64 -64 -Package_DIP -DIP-64_W15.24mm_SMDSocket_SmallPads -64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads -0 -64 -64 -Package_DIP -DIP-64_W15.24mm_Socket -64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket -0 -64 -64 -Package_DIP -DIP-64_W15.24mm_Socket_LongPads -64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads -0 -64 -64 -Package_DIP -DIP-64_W16.51mm_SMDSocket_LongPads -64-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads -0 -64 -64 -Package_DIP -DIP-64_W22.86mm -64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils) -THT DIP DIL PDIP 2.54mm 22.86mm 900mil -0 -64 -64 -Package_DIP -DIP-64_W22.86mm_LongPads -64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), LongPads -THT DIP DIL PDIP 2.54mm 22.86mm 900mil LongPads -0 -64 -64 -Package_DIP -DIP-64_W22.86mm_SMDSocket_SmallPads -64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 22.86mm 900mil SMDSocket SmallPads -0 -64 -64 -Package_DIP -DIP-64_W22.86mm_Socket -64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), Socket -THT DIP DIL PDIP 2.54mm 22.86mm 900mil Socket -0 -64 -64 -Package_DIP -DIP-64_W22.86mm_Socket_LongPads -64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 22.86mm 900mil Socket LongPads -0 -64 -64 -Package_DIP -DIP-64_W24.13mm_SMDSocket_LongPads -64-lead though-hole mounted DIP package, row spacing 24.13 mm (950 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 24.13mm 950mil SMDSocket LongPads -0 -64 -64 -Package_DIP -DIP-64_W25.4mm -64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils) -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil -0 -64 -64 -Package_DIP -DIP-64_W25.4mm_LongPads -64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), LongPads -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil LongPads -0 -64 -64 -Package_DIP -DIP-64_W25.4mm_SMDSocket_SmallPads -64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), SMDSocket, SmallPads -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil SMDSocket SmallPads -0 -64 -64 -Package_DIP -DIP-64_W25.4mm_Socket -64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket -0 -64 -64 -Package_DIP -DIP-64_W25.4mm_Socket_LongPads -64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket, LongPads -THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket LongPads -0 -64 -64 -Package_DIP -DIP-64_W26.67mm_SMDSocket_LongPads -64-lead though-hole mounted DIP package, row spacing 26.67 mm (1050 mils), SMDSocket, LongPads -THT DIP DIL PDIP 2.54mm 26.669999999999998mm 1050mil SMDSocket LongPads -0 -64 -64 -Package_DIP -Fairchild_LSOP-8 -8-Lead, 300\" Wide, Surface Mount Package (https://www.fairchildsemi.com/package-drawings/ML/MLSOP08A.pdf) -LSOP 2.54mm 300mil -0 -8 -8 -Package_DIP -PowerIntegrations_PDIP-8B -Power Integrations variant of 8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://www.power.com/sites/default/files/product-docs/lnk520.pdf -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -7 -7 -Package_DIP -PowerIntegrations_PDIP-8C -Power Integrations variant of 8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-iii_family_datasheet.pdf -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -7 -7 -Package_DIP -PowerIntegrations_SDIP-10C -PowerIntegrations variant of 10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://www.power.com/sites/default/files/product-docs/tophx_family_datasheet.pdf -THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads -0 -9 -9 -Package_DIP -PowerIntegrations_SMD-8 -PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://www.power.com/sites/default/files/product-docs/lnk520.pdf -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -8 -8 -Package_DIP -PowerIntegrations_SMD-8B -PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://www.power.com/sites/default/files/product-docs/lnk520.pdf -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -7 -7 -Package_DIP -PowerIntegrations_SMD-8C -PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-iii_family_datasheet.pdf -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -7 -7 -Package_DIP -PowerIntegrations_eDIP-12B -Power Integrations eDIP-12B, see https://www.power.com/sites/default/files/product-docs/linkswitch-pl_family_datasheet.pdf -THT DIP DIL PDIP 2.54mm 7.62mm 300mil -0 -11 -11 -Package_DIP -SMDIP-4_W7.62mm -4-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -4 -4 -Package_DIP -SMDIP-4_W9.53mm -4-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -4 -4 -Package_DIP -SMDIP-4_W9.53mm_Clearance8mm -4-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -4 -4 -Package_DIP -SMDIP-4_W11.48mm -4-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -4 -4 -Package_DIP -SMDIP-6_W7.62mm -6-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -6 -6 -Package_DIP -SMDIP-6_W9.53mm -6-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -6 -6 -Package_DIP -SMDIP-6_W9.53mm_Clearance8mm -6-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -6 -6 -Package_DIP -SMDIP-6_W11.48mm -6-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -6 -6 -Package_DIP -SMDIP-8_W7.62mm -8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -8 -8 -Package_DIP -SMDIP-8_W9.53mm -8-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -8 -8 -Package_DIP -SMDIP-8_W9.53mm_Clearance8mm -8-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -8 -8 -Package_DIP -SMDIP-8_W11.48mm -8-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -8 -8 -Package_DIP -SMDIP-10_W7.62mm -10-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -10 -10 -Package_DIP -SMDIP-10_W9.53mm -10-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -10 -10 -Package_DIP -SMDIP-10_W9.53mm_Clearance8mm -10-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -10 -10 -Package_DIP -SMDIP-10_W11.48mm -10-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -10 -10 -Package_DIP -SMDIP-12_W7.62mm -12-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -12 -12 -Package_DIP -SMDIP-12_W9.53mm -12-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -12 -12 -Package_DIP -SMDIP-12_W9.53mm_Clearance8mm -12-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -12 -12 -Package_DIP -SMDIP-12_W11.48mm -12-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -12 -12 -Package_DIP -SMDIP-14_W7.62mm -14-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -14 -14 -Package_DIP -SMDIP-14_W9.53mm -14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -14 -14 -Package_DIP -SMDIP-14_W9.53mm_Clearance8mm -14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -14 -14 -Package_DIP -SMDIP-14_W11.48mm -14-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -14 -14 -Package_DIP -SMDIP-16_W7.62mm -16-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -16 -16 -Package_DIP -SMDIP-16_W9.53mm -16-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -16 -16 -Package_DIP -SMDIP-16_W9.53mm_Clearance8mm -16-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -16 -16 -Package_DIP -SMDIP-16_W11.48mm -16-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -16 -16 -Package_DIP -SMDIP-18_W7.62mm -18-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -18 -18 -Package_DIP -SMDIP-18_W9.53mm -18-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -18 -18 -Package_DIP -SMDIP-18_W9.53mm_Clearance8mm -18-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -18 -18 -Package_DIP -SMDIP-18_W11.48mm -18-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -18 -18 -Package_DIP -SMDIP-20_W7.62mm -20-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -20 -20 -Package_DIP -SMDIP-20_W9.53mm -20-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -20 -20 -Package_DIP -SMDIP-20_W9.53mm_Clearance8mm -20-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -20 -20 -Package_DIP -SMDIP-20_W11.48mm -20-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -20 -20 -Package_DIP -SMDIP-22_W7.62mm -22-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -22 -22 -Package_DIP -SMDIP-22_W9.53mm -22-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -22 -22 -Package_DIP -SMDIP-22_W9.53mm_Clearance8mm -22-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm -0 -22 -22 -Package_DIP -SMDIP-22_W11.48mm -22-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -22 -22 -Package_DIP -SMDIP-24_W7.62mm -24-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -24 -24 -Package_DIP -SMDIP-24_W9.53mm -24-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -24 -24 -Package_DIP -SMDIP-24_W11.48mm -24-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -24 -24 -Package_DIP -SMDIP-24_W15.24mm -24-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -24 -24 -Package_DIP -SMDIP-28_W15.24mm -28-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -28 -28 -Package_DIP -SMDIP-32_W7.62mm -32-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil -0 -32 -32 -Package_DIP -SMDIP-32_W9.53mm -32-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil -0 -32 -32 -Package_DIP -SMDIP-32_W11.48mm -32-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil -0 -32 -32 -Package_DIP -SMDIP-32_W15.24mm -32-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -32 -32 -Package_DIP -SMDIP-40_W15.24mm -40-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -40 -40 -Package_DIP -SMDIP-40_W25.24mm -40-lead surface-mounted (SMD) DIP package, row spacing 25.24 mm (993 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 25.24mm 993mil -0 -40 -40 -Package_DIP -SMDIP-42_W15.24mm -42-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -42 -42 -Package_DIP -SMDIP-48_W15.24mm -48-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -48 -48 -Package_DIP -SMDIP-64_W15.24mm -64-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) -SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil -0 -64 -64 -Package_DIP -Toshiba_11-7A9 -Toshiba 11-7A9 package, like 6-lead dip package with missing pin 5, row spacing 7.62 mm (300 mils), https://toshiba.semicon-storage.com/info/docget.jsp?did=1421&prodName=TLP3021(S) -Toshiba 11-7A9 DIL DIP PDIP 2.54mm 7.62mm 300mil -0 -5 -5 -Package_DIP -Vishay_HVM-DIP-3_W7.62mm -3-lead though-hole mounted high-volatge DIP package (based on standard DIP-4), row spacing 7.62 mm (300 mils), see https://www.vishay.com/docs/91361/hexdip.pdf -THT DIP DIL PDIP 2.54mm 7.62mm 300mil Vishay HVMDIP HEXDIP -0 -4 -3 -Package_DirectFET -DirectFET_L4 -DirectFET L4 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=41 -DirectFET L4 MOSFET Infineon -0 -11 -3 -Package_DirectFET -DirectFET_L6 -DirectFET L6 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=42 -DirectFET L6 MOSFET Infineon -0 -13 -3 -Package_DirectFET -DirectFET_L8 -DirectFET L8 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=43 -DirectFET L8 MOSFET Infineon -0 -15 -3 -Package_DirectFET -DirectFET_LA -DirectFET LA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=44 -DirectFET LA MOSFET Infineon -0 -15 -3 -Package_DirectFET -DirectFET_M2 -DirectFET M2 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=33 -DirectFET M2 MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_M4 -DirectFET M4 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=34 -DirectFET M4 MOSFET Infineon -0 -9 -3 -Package_DirectFET -DirectFET_MA -DirectFET MA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=35 -DirectFET MA MOSFET Infineon -0 -8 -3 -Package_DirectFET -DirectFET_MB -DirectFET MB https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=36 -DirectFET MB MOSFET Infineon -0 -8 -3 -Package_DirectFET -DirectFET_MC -DirectFET MC https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=37 -DirectFET MC MOSFET Infineon -0 -10 -3 -Package_DirectFET -DirectFET_MD -DirectFET MD https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=38 -DirectFET MD MOSFET Infineon -0 -8 -3 -Package_DirectFET -DirectFET_ME -DirectFET ME https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=39 -DirectFET ME MOSFET Infineon -0 -10 -3 -Package_DirectFET -DirectFET_MF -DirectFET MF https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=40 -DirectFET MF MOSFET Infineon -0 -8 -3 -Package_DirectFET -DirectFET_MN -DirectFET MN https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=30 -DirectFET MN MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_MP -DirectFET MP https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=28 -DirectFET MP MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_MQ -DirectFET MQ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=29 -DirectFET MQ MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_MT -DirectFET MT https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=26 -DirectFET MT MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_MU -DirectFET MU https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=32 -DirectFET MU MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_MX -DirectFET MX https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=27 -DirectFET MX MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_MZ -DirectFET MZ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=31 -DirectFET MZ MOSFET Infineon -0 -7 -3 -Package_DirectFET -DirectFET_S1 -DirectFET S1 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=20 -DirectFET S1 MOSFET Infineon -0 -6 -3 -Package_DirectFET -DirectFET_S2 -DirectFET S2 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(http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=425), generated with kicad-footprint-generator ipc_gullwing_generator.py -LQFP QFP -0 -144 -144 -Package_QFP -LQFP-160_24x24mm_P0.5mm -LQFP, 160 Pin (https://www.nxp.com/docs/en/package-information/SOT435-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -LQFP QFP -0 -160 -160 -Package_QFP -LQFP-176_20x20mm_P0.4mm -LQFP, 176 Pin (https://www.onsemi.com/pub/Collateral/566DB.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py -LQFP QFP -0 -176 -176 -Package_QFP -LQFP-176_24x24mm_P0.5mm -LQFP, 176 Pin (https://www.st.com/resource/en/datasheet/stm32f207vg.pdf#page=163), generated with kicad-footprint-generator ipc_gullwing_generator.py -LQFP QFP -0 -176 -176 -Package_QFP -LQFP-208_28x28mm_P0.5mm -LQFP, 208 Pin (https://www.nxp.com/docs/en/package-information/SOT459-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -LQFP QFP -0 -208 -208 -Package_QFP -LQFP-216_24x24mm_P0.4mm -LQFP, 216 Pin (https://www.onsemi.com/pub/Collateral/561BE.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py -LQFP QFP -0 -216 -216 -Package_QFP -MQFP-44_10x10mm_P0.8mm -MQFP, 44 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ad7722.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -MQFP QFP -0 -44 -44 -Package_QFP -PQFP-44_10x10mm_P0.8mm -44-Lead Plastic Quad Flatpack - 10x10x2.5mm Body (http://www.onsemi.com/pub/Collateral/122BK.PDF) -PQFP 0.8 -0 -44 -44 -Package_QFP -PQFP-80_14x20mm_P0.8mm -PQFP80 14x20 / QIP80E CASE 122BS (see ON Semiconductor 122BS.PDF) -QFP 0.8 -0 -80 -80 -Package_QFP -PQFP-100_14x20mm_P0.65mm -PQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -PQFP QFP -0 -100 -100 -Package_QFP -PQFP-112_20x20mm_P0.65mm -PQFP, 112 pins, 20mm sq body, 0.65mm pitch (http://cache.freescale.com/files/shared/doc/package_info/98ASS23330W.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf) -PQFP 112 -0 -112 -112 -Package_QFP -PQFP-132_24x24mm_P0.635mm -PQFP, 132 pins, 24mm sq body, 0.635mm pitch (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf) -PQFP 132 -0 -132 -132 -Package_QFP -PQFP-132_24x24mm_P0.635mm_i386 -PQFP, 132 pins, 24mm sq body, 0.635mm pitch, Intel 386EX (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf) -PQFP 132 Intel 386EX -0 -132 -132 -Package_QFP -PQFP-144_28x28mm_P0.65mm -PQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -PQFP QFP -0 -144 -144 -Package_QFP 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-Package_QFP -TQFP-44-1EP_10x10mm_P0.8mm_EP4.5x4.5mm -44-Lead Plastic Thin Quad Flatpack (MW) - 10x10x1.0 mm Body [TQFP] With 4.5x4.5 mm Exposed Pad (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.8 -0 -54 -45 -Package_QFP -TQFP-44_10x10mm_P0.8mm -44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.8 -0 -44 -44 -Package_QFP -TQFP-48-1EP_7x7mm_P0.5mm_EP3.5x3.5mm -48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.5 -0 -53 -49 -Package_QFP -TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm -TQFP, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 45)), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -65 -49 -Package_QFP -TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm_ThermalVias -TQFP, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 45)), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -91 -49 -Package_QFP -TQFP-48_7x7mm_P0.5mm -48 LEAD TQFP 7x7mm (see MICREL TQFP7x7-48LD-PL-1.pdf) -QFP 0.5 -0 -48 -48 -Package_QFP -TQFP-52-1EP_10x10mm_P0.65mm_EP6.5x6.5mm -TQFP, 52 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_52_1.pdf), generated with kicad-footprint-generator ipc_qfp_generator.py -TQFP QFP -0 -78 -53 -Package_QFP -TQFP-52-1EP_10x10mm_P0.65mm_EP6.5x6.5mm_ThermalVias -TQFP, 52 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_52_1.pdf), generated with kicad-footprint-generator ipc_qfp_generator.py -TQFP QFP -0 -79 -53 -Package_QFP -TQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm -64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP] thermal pad -QFP 0.5 -0 -90 -65 -Package_QFP -TQFP-64_7x7mm_P0.4mm -TQFP64 7x7, 0.4P CASE 932BH (see ON Semiconductor 932BH.PDF) -QFP 0.4 -0 -64 -64 -Package_QFP -TQFP-64_10x10mm_P0.5mm -TQFP, 64 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -64 -64 -Package_QFP -TQFP-64_14x14mm_P0.8mm -64-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.8 -0 -64 -64 -Package_QFP -TQFP-80-1EP_14x14mm_P0.65mm_EP9.5x9.5mm -80-Lead Plastic Thin Quad Flatpack (PF) - 14x14mm body, 9.5mm sq thermal pad (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9852.pdf) -QFP 0.65 -0 -85 -81 -Package_QFP -TQFP-80_12x12mm_P0.5mm -80-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.5 -0 -80 -80 -Package_QFP -TQFP-80_14x14mm_P0.65mm -80-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.65 -0 -80 -80 -Package_QFP -TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm -TQFP, 100 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_100_4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -117 -101 -Package_QFP -TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm_ThermalVias -TQFP, 100 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_100_4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -143 -101 -Package_QFP -TQFP-100_12x12mm_P0.4mm -100-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.4 -0 -100 -100 -Package_QFP -TQFP-100_14x14mm_P0.5mm -TQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -100 -100 -Package_QFP -TQFP-120_14x14mm_P0.4mm -TQFP120 14x14 / TQFP120 CASE 932AZ (see ON Semiconductor 932AZ.PDF) -QFP 0.4 -0 -120 -120 -Package_QFP -TQFP-128_14x14mm_P0.4mm -TQFP128 14x14 / TQFP128 CASE 932BB (see ON Semiconductor 932BB.PDF) -QFP 0.4 -0 -128 -128 -Package_QFP -TQFP-144_16x16mm_P0.4mm -144-Lead Plastic Thin Quad Flatpack (PH) - 16x16x1 mm Body, 2.00 mm Footprint [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) -QFP 0.4 -0 -144 -144 -Package_QFP -TQFP-144_20x20mm_P0.5mm -TQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -144 -144 -Package_QFP -TQFP-176_24x24mm_P0.5mm -TQFP, 176 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -TQFP QFP -0 -176 -176 -Package_QFP -VQFP-80_14x14mm_P0.65mm -VQFP, 80 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -VQFP QFP -0 -80 -80 -Package_QFP -VQFP-100_14x14mm_P0.5mm -VQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -VQFP QFP -0 -100 -100 -Package_QFP -VQFP-128_14x14mm_P0.4mm -VQFP, 128 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -VQFP QFP -0 -128 -128 -Package_QFP -VQFP-176_20x20mm_P0.4mm -VQFP, 176 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py -VQFP QFP -0 -176 -176 -Package_SIP -PowerIntegrations_eSIP-7C -eSIP-7C Vertical Flat Package with Heatsink Tab, https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf -Power Integrations E Package -0 -6 -6 -Package_SIP -PowerIntegrations_eSIP-7F -eSIP-7F Flat Package with Heatsink Tab https://ac-dc.power.com/sites/default/files/product-docs/linkswitch-ph_family_datasheet.pdf -Power Integrations L Package -0 -6 -6 -Package_SIP -SIP-8_19x3mm_P2.54mm -SIP 8-pin (http://www.njr.com/semicon/PDF/package/SIP8_E.pdf) -SIP8 -0 -8 -8 -Package_SIP -SIP-9_21.54x3mm_P2.54mm -SIP 9-pin () -SIP8 -0 -9 -9 -Package_SIP -SIP3_11.6x8.5mm -RECOM,R78EXX,https://www.recom-power.com/pdf/Innoline/R-78Exx-0.5.pdf -SIP3 Regulator Module -0 -3 -3 -Package_SIP -SIP4_Sharp-SSR_P7.62mm_Angled -SIP4 Footprint for SSR made by Sharp -Solid State relais SSR Sharp -0 -4 -4 -Package_SIP -SIP4_Sharp-SSR_P7.62mm_Angled_NoHole -SIP4 Footprint for SSR made by Sharp -Solid State relais SSR Sharp -0 -4 -4 -Package_SIP -SIP4_Sharp-SSR_P7.62mm_Straight -SIP4 Footprint for SSR made by Sharp -Solid State relais SSR Sharp -0 -4 -4 -Package_SIP -SIP9_Housing -SIP9 -SIP9 -0 -9 -9 -Package_SIP -SIP9_Housing_BigPads -SIP9, large pads -SIP9 -0 -9 -9 -Package_SIP -SLA704XM -SIP SLA704XM (http://www.sumzi.com/upload/files/2007/07/2007073114282034189.PDF) -SIP -0 -18 -18 -Package_SIP -STK672-040-E -SIP-22 (http://www.onsemi.com/pub_link/Collateral/EN5227-D.PDF) -SIP-22 -0 -22 -22 -Package_SIP -STK672-080-E -SIP-15 (http://www.onsemi.com/pub_link/Collateral/EN6507-D.PDF) -SIP-15 -0 -15 -15 -Package_SIP -Sanyo_STK4xx-15_59.2x8.0mm_P2.54mm -Sanyo SIP-15, 59.2mm x 8.0mm bosy size, STK-433E STK-435E STK-436E (http://datasheet.octopart.com/STK430-Sanyo-datasheet-107060.pdf) -Sanyo SIP-15 -0 -15 -15 -Package_SIP -Sanyo_STK4xx-15_78.0x8.0mm_P2.54mm -Sanyo SIP-15, 78.0mm x 8.0mm bosy size, STK-437E STK-439E STK-441E STK-443E (http://datasheet.octopart.com/STK430-Sanyo-datasheet-107060.pdf) -Sanyo SIP-15 -0 -15 -15 -Package_SO -Diodes_PSOP-8 -8-Lead Plastic PSOP, Exposed Die Pad (see https://www.diodes.com/assets/Datasheets/AP2204.pdf) -SSOP 0.50 exposed pad -0 -12 -9 -Package_SO -Diodes_SO-8EP -8-Lead Plastic SO, Exposed Die Pad (see https://www.diodes.com/assets/Package-Files/SO-8EP.pdf) -SO exposed pad -0 -9 -9 -Package_SO -ETSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3x4.2mm -20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body with Exposed Pad [eTSSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -27 -21 -Package_SO -HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm -HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HSOP SO -0 -13 -9 -Package_SO -HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm_ThermalVias -HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HSOP SO -0 -20 -9 -Package_SO -HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugDown -HSOP 11.0x15.9mm Pitch 1.27mm Slug Down (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf) -HSOP 11.0 x 15.9mm Pitch 1.27mm -0 -23 -21 -Package_SO -HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugDown_ThermalVias -HSOP 11.0x15.9mm Pitch 1.27mm Slug Down Thermal Vias (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf) -HSOP 11.0 x 15.9mm Pitch 1.27mm -0 -45 -21 -Package_SO -HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugUp -HSOP 11.0x15.9mm Pitch 1.27mm Slug Up (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf) -HSOP 11.0 x 15.9mm Pitch 1.27mm -0 -20 -20 -Package_SO -HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugDown -HSOP 11.0x15.9mm Pitch 0.65mm Slug Down (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf) -HSOP 11.0 x 15.9mm Pitch 0.65mm -0 -39 -37 -Package_SO -HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugDown_ThermalVias -HSOP 11.0x15.9mm Pitch 0.65mm Slug Down Thermal Vias (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf) -HSOP 11.0 x 15.9mm Pitch 0.65mm -0 -61 -37 -Package_SO -HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugUp -HSOP 11.0x15.9mm Pitch 0.65mm Slug Up (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf) -HSOP 11.0 x 15.9mm Pitch 0.65mm -0 -36 -36 -Package_SO -HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm -HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSOP SO -0 -13 -9 -Package_SO -HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm_ThermalVias -HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSOP SO -0 -20 -9 -Package_SO -HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm -16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad; (http://www.ti.com/lit/ds/symlink/drv8833.pdf) -SSOP 0.65 -0 -29 -17 -Package_SO -HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask2.46x2.31mm_ThermalVias -16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8833.pdf) -SSOP 0.65 -0 -27 -17 -Package_SO -HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3x3mm_ThermalVias -16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf) -SSOP 0.65 -0 -46 -17 -Package_SO -HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3x3mm -HTSSOP, 16 Pin (https://www.st.com/resource/en/datasheet/stp08cp05.pdf#page=20), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -21 -17 -Package_SO -HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm -20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [HTSSOP], with thermal pad with vias -HTSSOP 0.65 -0 -29 -21 -Package_SO -HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.4x3.7mm -HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/bq24006.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -24 -21 -Package_SO -HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm -HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -26 -21 -Package_SO -HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias -HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -42 -21 -Package_SO -HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias_HandSolder -HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -42 -21 -Package_SO -HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_ThermalVias -20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [HTSSOP], with thermal pad with vias -HTSSOP 0.65 -0 -45 -21 -Package_SO -HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.2x5mm -HTSSOP, 24 Pin (https://www.st.com/resource/en/datasheet/stp16cp05.pdf#page=25), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -31 -25 -Package_SO -HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm -HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -28 -25 -Package_SO -HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm_ThermalVias -HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -47 -25 -Package_SO -HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm -HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -30 -29 -Package_SO -HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm_ThermalVias -HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -41 -29 -Package_SO -HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm -HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad -TSSOP HTSSOP 0.65 thermal pad -0 -39 -29 -Package_SO -HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm -HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad -TSSOP HTSSOP 0.65 thermal pad -0 -40 -29 -Package_SO -HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm_ThermalVias -HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad -TSSOP HTSSOP 0.65 thermal pad -0 -55 -29 -Package_SO -HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_ThermalVias -HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad -TSSOP HTSSOP 0.65 thermal pad -0 -58 -29 -Package_SO -HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm -HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf) -SSOP 0.65 PowerPAD -0 -43 -33 -Package_SO -HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm_ThermalVias -HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf) -SSOP 0.65 PowerPAD -0 -83 -33 -Package_SO -HTSSOP-38-1EP_6.1x12.5mm_P0.65mm_EP5.2x12.5mm_Mask3.39x6.35mm -HTSSOP, 38 Pin (http://www.ti.com/lit/ds/symlink/tlc5951.pdf#page=47&zoom=140,-67,15), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -46 -39 -Package_SO -HTSSOP-38-1EP_6.1x12.5mm_P0.65mm_EP5.2x12.5mm_Mask3.39x6.35mm_ThermalVias -HTSSOP, 38 Pin (http://www.ti.com/lit/ds/symlink/tlc5951.pdf#page=47&zoom=140,-67,15), generated with kicad-footprint-generator ipc_gullwing_generator.py -HTSSOP SO -0 -87 -39 -Package_SO -HTSSOP-56-1EP_6.1x14mm_P0.5mm_EP3.61x6.35mm -HTSSOP56: plastic thin shrink small outline package http://www.ti.com/lit/ds/symlink/drv8301.pdf -HTSSOP 0.5 -0 -72 -57 -Package_SO -Infineon_PG-DSO-8-27_3.9x4.9mm_EP2.65x3mm -Infineon PG-DSO, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator ipc_gullwing_generator.py -Infineon PG-DSO SO -0 -13 -9 -Package_SO -Infineon_PG-DSO-8-27_3.9x4.9mm_EP2.65x3mm_ThermalVias -Infineon PG-DSO, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator ipc_gullwing_generator.py -Infineon PG-DSO SO -0 -23 -9 -Package_SO -Infineon_PG-DSO-8-43 -Infineon_PG-DSO-8-43 -DSO DSO-8 SOIC SOIC-8 -0 -12 -9 -Package_SO -Infineon_PG-DSO-12-9 -Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/) -PG-DSO -0 -23 -13 -Package_SO -Infineon_PG-DSO-12-9_ThermalVias -Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/) -PG-DSO -0 -42 -13 -Package_SO -Infineon_PG-DSO-12-11 -Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/) -PG-DSO -0 -23 -13 -Package_SO -Infineon_PG-DSO-12-11_ThermalVias -Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/) -PG-DSO -0 -42 -13 -Package_SO -Infineon_PG-DSO-20-30 -Infineon SO package 20pin, exposed pad 4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/) -DSO-20 -0 -31 -21 -Package_SO -Infineon_PG-DSO-20-30_ThermalVias -Infineon SO package 20pin, exposed pad 4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/) -DSO-20 -0 -45 -21 -Package_SO -Infineon_PG-DSO-20-32 -Infineon SO package 20pin without exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-32/) -DSO-20 -0 -20 -20 -Package_SO -Infineon_PG-TSDSO-14-22 -Infineon_PG-TSDSO-14-22 -Infineon TSDSO 14-22 -0 -17 -15 -Package_SO -Linear_MSOP-12-16-1EP_3x4mm_P0.5mm -12-Lead Plastic Micro Small Outline Package (MS) [MSOP], variant of MSOP-16 (see http://cds.linear.com/docs/en/datasheet/3630fd.pdf) -SSOP 0.5 -0 -15 -13 -Package_SO -Linear_MSOP-12-16_3x4mm_P0.5mm -12-Lead Plastic Micro Small Outline Package (MS) [MSOP], variant of MSOP-16 (see https://www.analog.com/media/en/technical-documentation/data-sheets/3748fb.pdf) -SSOP 0.5 -0 -12 -12 -Package_SO -MFSOP6-4_4.4x3.6mm_P1.27mm -https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.4pin%20MFSOP6.html -MFSOP 4 pin SMD -0 -4 -4 -Package_SO -MFSOP6-5_4.4x3.6mm_P1.27mm -https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.5pin%20MFSOP6.html -MFSOP 4 pin SMD -0 -5 -5 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm -MS8E Package; 8-Lead Plastic MSOP, Exposed Die Pad (see Linear Technology 05081662_K_MS8E.pdf) -SSOP 0.65 -0 -13 -9 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP1.73x1.85mm -MSOP, 8 Pin (http://www.ti.com/lit/ds/symlink/lm25085.pdf#page=32), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -13 -9 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP1.73x1.85mm_ThermalVias -MSOP, 8 Pin (http://www.ti.com/lit/ds/symlink/lm25085.pdf#page=32), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -18 -9 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm -MSOP, 8 Pin (http://www.st.com/resource/en/datasheet/pm8834.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -13 -9 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm_ThermalVias -MSOP, 8 Pin (http://www.st.com/resource/en/datasheet/pm8834.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -18 -9 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP2.5x3mm_Mask1.73x2.36mm -MSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf#page=15), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -14 -9 -Package_SO -MSOP-8-1EP_3x3mm_P0.65mm_EP2.5x3mm_Mask1.73x2.36mm_ThermalVias -MSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf#page=15), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -19 -9 -Package_SO -MSOP-8_3x3mm_P0.65mm -MSOP, 8 Pin (https://www.jedec.org/system/files/docs/mo-187F.pdf variant AA), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -8 -8 -Package_SO -MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm -MSOP, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3805fg.pdf#page=18), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -15 -11 -Package_SO -MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm_ThermalVias -MSOP, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3805fg.pdf#page=18), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -20 -11 -Package_SO -MSOP-10-1EP_3x3mm_P0.5mm_EP1.73x1.98mm -MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -15 -11 -Package_SO -MSOP-10-1EP_3x3mm_P0.5mm_EP1.73x1.98mm_ThermalVias -MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -20 -11 -Package_SO -MSOP-10_3x3mm_P0.5mm -10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.5 -0 -10 -10 -Package_SO -MSOP-12-1EP_3x4mm_P0.65mm_EP1.65x2.85mm -MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3652fe.pdf#page=24), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -17 -13 -Package_SO -MSOP-12-1EP_3x4mm_P0.65mm_EP1.65x2.85mm_ThermalVias -MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3652fe.pdf#page=24), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -24 -13 -Package_SO -MSOP-12-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm -10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.5 -0 -19 -13 -Package_SO -MSOP-12-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm_ThermalVias -10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.5 -0 -25 -13 -Package_SO -MSOP-12-16_3x4mm_P0.5mm -10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.5 -0 -12 -12 -Package_SO -MSOP-12_3x4mm_P0.65mm -MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/6957fb.pdf#page=36), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -12 -12 -Package_SO -MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm -MSOP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081667_F_MSE16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -21 -17 -Package_SO -MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm_ThermalVias -MSOP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081667_F_MSE16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -28 -17 -Package_SO -MSOP-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm -MSOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -21 -17 -Package_SO -MSOP-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm_ThermalVias -MSOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -28 -17 -Package_SO -MSOP-16_3x4.039mm_P0.5mm -MSOP, 16 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081669_A_MS16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -16 -16 -Package_SO -MSOP-16_3x4mm_P0.5mm -MSOP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/436412f.pdf#page=22), generated with kicad-footprint-generator ipc_gullwing_generator.py -MSOP SO -0 -16 -16 -Package_SO -OnSemi_Micro8 -ON Semiconductor Micro8 (Case846A-02): https://www.onsemi.com/pub/Collateral/846A-02.PDF -micro8 -0 -8 -8 -Package_SO -PSOP-44_16.9x27.17mm_P1.27mm -PSOP44: plastic thin shrink small outline package; 44 leads; body width 16.90 mm -PSOP 1.27 -0 -44 -44 -Package_SO -PowerIntegrations_SO-8 -Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://ac-dc.power.com/sites/default/files/product-docs/senzero_family_datasheet.pdf -SOIC 1.27 -0 -8 -8 -Package_SO -PowerIntegrations_SO-8B -Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf -SOIC 1.27 -0 -7 -7 -Package_SO -PowerIntegrations_SO-8C -Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf -SOIC 1.27 -0 -7 -7 -Package_SO -PowerIntegrations_eSOP-12B -eSOP-12B SMT Flat Package with Heatsink Tab, see https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf -Power Integrations K Package -0 -12 -12 -Package_SO -PowerPAK_SO-8_Dual -PowerPAK SO-8 Dual (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72600/72600.pdf) -PowerPAK SO-8 Dual -0 -10 -6 -Package_SO -PowerPAK_SO-8_Single -PowerPAK SO-8 Single (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72599/72599.pdf) -PowerPAK SO-8 Single -0 -9 -5 -Package_SO -QSOP-16_3.9x4.9mm_P0.635mm -16-Lead Plastic Shrink Small Outline Narrow Body (QR)-.150" Body [QSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.635 -0 -16 -16 -Package_SO -QSOP-20_3.9x8.7mm_P0.635mm -20-Lead Plastic Shrink Small Outline Narrow Body (http://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7640_7641_7642_7643.pdf) -QSOP 0.635 -0 -20 -20 -Package_SO -QSOP-24_3.9x8.7mm_P0.635mm -24-Lead Plastic Shrink Small Outline Narrow Body (QR)-.150" Body [QSOP] (see Microchip Packaging Specification 00000049CH.pdf) -QSOP 0.635 -0 -24 -24 -Package_SO -SC-74-6_1.5x2.9mm_P0.95mm -SC-74, 6 Pin (https://www.nxp.com/docs/en/package-information/SOT457.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SC-74 SO -0 -6 -6 -Package_SO -SO-4_4.4x2.3mm_P1.27mm -4-Lead Plastic Small Outline (SO), see http://datasheet.octopart.com/OPIA403BTRE-Optek-datasheet-5328560.pdf -SO SOIC 1.27 -0 -4 -4 -Package_SO -SO-4_4.4x3.6mm_P2.54mm -4-Lead Plastic Small Outline (SO), see https://www.elpro.org/de/index.php?controller=attachment&id_attachment=339 -SO SOIC 2.54 -0 -4 -4 -Package_SO -SO-4_4.4x3.9mm_P2.54mm -SO, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=10047&prodName=TLP3123), generated with kicad-footprint-generator ipc_gullwing_generator.py -SO SO -0 -4 -4 -Package_SO -SO-4_4.4x4.3mm_P2.54mm -4-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/docs/AV02-0173EN -SO SOIC 2.54 -0 -4 -4 -Package_SO -SO-4_7.6x3.6mm_P2.54mm -4-Lead Plastic Small Outline (SO) (http://www.everlight.com/file/ProductFile/201407061745083848.pdf) -SO SOIC 2.54 -0 -4 -4 -Package_SO -SO-5_4.4x3.6mm_P1.27mm -5-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SO SOIC 1.27 -0 -5 -5 -Package_SO -SO-6L_10x3.84mm_P1.27mm -6-pin plasic small outline 7,5mm long https://toshiba.semicon-storage.com/info/docget.jsp?did=53548&prodName=TLP2770 -SO-6L -0 -6 -6 -Package_SO -SO-6_4.4x3.6mm_P1.27mm -6-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SO SOIC 1.27 -0 -6 -6 -Package_SO -SO-8_3.9x4.9mm_P1.27mm -SO, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SO SO -0 -8 -8 -Package_SO -SO-8_5.3x6.2mm_P1.27mm -8-Lead Plastic Small Outline, 5.3x6.2mm Body (http://www.ti.com.cn/cn/lit/ds/symlink/tl7705a.pdf) -SOIC 1.27 -0 -8 -8 -Package_SO -SO-20_12.8x7.5mm_P1.27mm -SO-20, 12.8x7.5mm, https://www.nxp.com/docs/en/data-sheet/SA605.pdf -S0-20 -0 -20 -20 -Package_SO -SOIC-4_4.55x2.6mm_P1.27mm -SOIC, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12884&prodName=TLP291), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -4 -4 -Package_SO -SOIC-4_4.55x3.7mm_P2.54mm -SOIC, 6 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=11791&prodName=TLP185), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -4 -4 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -13 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias -SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -20 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -13 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm_ThermalVias -SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -20 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm -SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -13 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm_ThermalVias -SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -20 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm -SOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lm5017.pdf#page=31), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -14 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm_ThermalVias -SOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lm5017.pdf#page=31), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -23 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm -SOIC, 8 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/hip2100.pdf#page=13), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -13 -9 -Package_SO -SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm_ThermalVias -SOIC, 8 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/hip2100.pdf#page=13), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -20 -9 -Package_SO -SOIC-8-N7_3.9x4.9mm_P1.27mm -8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], pin 7 removed (Microchip Packaging Specification 00000049BS.pdf, http://www.onsemi.com/pub/Collateral/NCP1207B.PDF) -SOIC 1.27 -0 -7 -7 -Package_SO -SOIC-8_3.9x4.9mm_P1.27mm -SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -8 -8 -Package_SO -SOIC-8_5.23x5.23mm_P1.27mm -SOIC, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf#page=68), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -8 -8 -Package_SO -SOIC-8_5.275x5.275mm_P1.27mm -SOIC, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20005045C.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -8 -8 -Package_SO -SOIC-8_7.5x5.85mm_P1.27mm -SOIC, 8 Pin (http://www.ti.com/lit/ml/mpds382b/mpds382b.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -8 -8 -Package_SO -SOIC-14W_7.5x9mm_P1.27mm -SOIC, 14 Pin (JEDEC MS-013AF, https://www.analog.com/media/en/package-pcb-resources/package/54614177245586rw_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -14 -14 -Package_SO -SOIC-14_3.9x8.7mm_P1.27mm -SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -14 -14 -Package_SO -SOIC-16W-12_7.5x10.3mm_P1.27mm -SOIC-16 With 12 Pin Placed - Wide, 7.50 mm Body [SOIC] (https://docs.broadcom.com/docs/AV02-0169EN) -SOIC 1.27 16 12 Wide -0 -12 -12 -Package_SO -SOIC-16W_5.3x10.2mm_P1.27mm -16-Lead Plastic Small Outline (SO) - Wide, 5.3 mm Body (http://www.ti.com/lit/ml/msop002a/msop002a.pdf) -SOIC 1.27 -0 -16 -16 -Package_SO -SOIC-16W_7.5x10.3mm_P1.27mm -SOIC, 16 Pin (JEDEC MS-013AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/rw_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -16 -16 -Package_SO -SOIC-16W_7.5x12.8mm_P1.27mm -SOIC, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ri_soic_ic/ri_16_1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -16 -16 -Package_SO -SOIC-16_3.9x9.9mm_P1.27mm -SOIC, 16 Pin (JEDEC MS-012AC, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -16 -16 -Package_SO -SOIC-16_4.55x10.3mm_P1.27mm -SOIC, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12858&prodName=TLP291-4), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -16 -16 -Package_SO -SOIC-18W_7.5x11.6mm_P1.27mm -SOIC, 18 Pin (JEDEC MS-013AB, https://www.analog.com/media/en/package-pcb-resources/package/33254132129439rw_18.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -18 -18 -Package_SO -SOIC-20W_7.5x12.8mm_P1.27mm -SOIC, 20 Pin (JEDEC MS-013AC, https://www.analog.com/media/en/package-pcb-resources/package/233848rw_20.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -20 -20 -Package_SO -SOIC-24W_7.5x15.4mm_P1.27mm -SOIC, 24 Pin (JEDEC MS-013AD, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/RW_24.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -24 -24 -Package_SO -SOIC-28W_7.5x17.9mm_P1.27mm -SOIC, 28 Pin (JEDEC MS-013AE, https://www.analog.com/media/en/package-pcb-resources/package/35833120341221rw_28.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -28 -28 -Package_SO -SOIC-28W_7.5x18.7mm_P1.27mm -SOIC, 28 Pin (https://www.akm.com/akm/en/file/datasheet/AK5394AVS.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOIC SO -0 -28 -28 -Package_SO -SOIJ-8_5.3x5.3mm_P1.27mm -8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf) -SOIC 1.27 -0 -8 -8 -Package_SO -SOJ-36_10.16x23.49mm_P1.27mm -SOJ, 36 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOJ SO -0 -36 -36 -Package_SO -SOP-4_3.8x4.1mm_P2.54mm -SOP, 4 Pin (http://www.ixysic.com/home/pdfs.nsf/www/CPC1017N.pdf/$file/CPC1017N.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -4 -4 -Package_SO -SOP-4_4.4x2.6mm_P1.27mm -SOP, 4 Pin (http://www.vishay.com/docs/83510/tcmt1100.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -4 -4 -Package_SO -SOP-8-1EP_4.57x4.57mm_P1.27mm_EP4.57x4.45mm -SOP, 8 Pin (Mini-Circuits XX112 housing; https://ww2.minicircuits.com/case_style/XX112.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -13 -9 -Package_SO -SOP-8-1EP_4.57x4.57mm_P1.27mm_EP4.57x4.45mm_ThermalVias -SOP, 8 Pin (Mini-Circuits XX112 housing; https://ww2.minicircuits.com/case_style/XX112.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -20 -9 -Package_SO -SOP-8_3.9x4.9mm_P1.27mm -SOP, 8 Pin (http://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf#page=79), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -8 -8 -Package_SO -SOP-8_3.76x4.96mm_P1.27mm -SOP, 8 Pin (https://ww2.minicircuits.com/case_style/XX211.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -8 -8 -Package_SO -SOP-8_5.28x5.23mm_P1.27mm -SOP, 8 Pin (http://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf#page=80), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -8 -8 -Package_SO -SOP-8_6.62x9.15mm_P2.54mm -SOP, 8 Pin (http://www.ti.com/lit/ds/symlink/iso1050.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -8 -8 -Package_SO -SOP-16_4.4x10.4mm_P1.27mm -16-Lead Plastic Small Outline http://www.vishay.com/docs/49633/sg2098.pdf -SOP 1.27 -0 -16 -16 -Package_SO -SOP-16_4.55x10.3mm_P1.27mm -SOP, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12855&prodName=TLP290-4), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -16 -16 -Package_SO -SOP-18_7x12.5mm_P1.27mm -SOP, 18 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=30523), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -18 -18 -Package_SO -SOP-24_7.5x15.4mm_P1.27mm -SOP, 24 Pin (http://www.issi.com/WW/pdf/31FL3218.pdf#page=14), generated with kicad-footprint-generator ipc_gullwing_generator.py -SOP SO -0 -24 -24 -Package_SO -SSO-4_6.7x5.1mm_P2.54mm_Clearance8mm -4-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/84299/vor1142b4.pdf -SSO Stretched SO SOIC 2.54 -0 -4 -4 -Package_SO -SSO-6_6.8x4.6mm_P1.27mm_Clearance7mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SSO Stretched SO SOIC 1.27 -0 -6 -6 -Package_SO -SSO-6_6.8x4.6mm_P1.27mm_Clearance8mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SSO Stretched SO SOIC 1.27 -0 -6 -6 -Package_SO -SSO-8_6.7x9.8mm_P2.54mm_Clearance8mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/83831/lh1533ab.pdf -SSO Stretched SO SOIC Pitch 2.54 -0 -8 -8 -Package_SO -SSO-8_6.8x5.9mm_P1.27mm_Clearance7mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SSO Stretched SO SOIC Pitch 1.27 -0 -8 -8 -Package_SO -SSO-8_6.8x5.9mm_P1.27mm_Clearance8mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SSO Stretched SO SOIC Pitch 1.27 -0 -8 -8 -Package_SO -SSO-8_9.6x6.3mm_P1.27mm_Clearance10.5mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SSO Stretched SO SOIC Pitch 1.27 -0 -8 -8 -Package_SO -SSO-8_13.6x6.3mm_P1.27mm_Clearance14.2mm -8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true -SSO Stretched SO SOIC Pitch 1.27 -0 -8 -8 -Package_SO -SSOP-8_2.95x2.8mm_P0.65mm -SSOP-8 2.9 x2.8mm Pitch 0.65mm -SSOP-8 2.95x2.8mm Pitch 0.65mm -0 -8 -8 -Package_SO -SSOP-8_3.9x5.05mm_P1.27mm -SSOP, 8 Pin (http://www.fujitsu.com/downloads/MICRO/fsa/pdf/products/memory/fram/MB85RS16-DS501-00014-6v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SSOP SO -0 -8 -8 -Package_SO -SSOP-8_3.95x5.21x3.27mm_P1.27mm -SSOP-8 3.95x5.21x3.27mm Pitch 1.27mm -SSOP-8 3.95x5.21x3.27mm 1.27mm -0 -8 -8 -Package_SO -SSOP-8_5.25x5.24mm_P1.27mm -SSOP, 8 Pin (http://www.fujitsu.com/ca/en/Images/MB85RS2MT-DS501-00023-1v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SSOP SO -0 -8 -8 -Package_SO -SSOP-10_3.9x4.9mm_P1.00mm -10-Lead SSOP, 3.9 x 4.9mm body, 1.00mm pitch (http://www.st.com/resource/en/datasheet/viper01.pdf) -SSOP 3.9 4.9 1.00 -0 -10 -10 -Package_SO -SSOP-14_5.3x6.2mm_P0.65mm -SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot337-1_po.pdf) -SSOP 0.65 -0 -14 -14 -Package_SO -SSOP-16_3.9x4.9mm_P0.635mm -SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot519-1_po.pdf) -SSOP 0.635 -0 -16 -16 -Package_SO -SSOP-16_4.4x5.2mm_P0.65mm -SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot369-1_po.pdf) -SSOP 0.65 -0 -16 -16 -Package_SO -SSOP-16_5.3x6.2mm_P0.65mm -SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot338-1_po.pdf) -SSOP 0.65 -0 -16 -16 -Package_SO -SSOP-18_4.4x6.5mm_P0.65mm -SSOP18: plastic shrink small outline package; 18 leads; body width 4.4 mm (http://toshiba.semicon-storage.com/info/docget.jsp?did=30523&prodName=TBD62783APG) -SSOP 0.65 -0 -18 -18 -Package_SO -SSOP-20_3.9x8.7mm_P0.635mm -SSOP20: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT231X.pdf) -SSOP 0.635 -0 -20 -20 -Package_SO -SSOP-20_4.4x6.5mm_P0.65mm -SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot266-1_po.pdf) -SSOP 0.65 -0 -20 -20 -Package_SO -SSOP-20_5.3x7.2mm_P0.65mm -SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SSOP SO -0 -20 -20 -Package_SO -SSOP-24_3.9x8.7mm_P0.635mm -SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot556-1_po.pdf) -SSOP 0.635 -0 -24 -24 -Package_SO -SSOP-24_5.3x8.2mm_P0.65mm -24-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -24 -24 -Package_SO -SSOP-28_3.9x9.9mm_P0.635mm -SSOP28: plastic shrink small outline package; 28 leads; body width 3.9 mm; lead pitch 0.635; (see http://cds.linear.com/docs/en/datasheet/38901fb.pdf) -SSOP 0.635 -0 -28 -28 -Package_SO -SSOP-28_5.3x10.2mm_P0.65mm -28-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -28 -28 -Package_SO -SSOP-32_11.305x20.495mm_P1.27mm -SSOP, 32 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -SSOP SO -0 -32 -32 -Package_SO -SSOP-44_5.3x12.8mm_P0.5mm -44-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (http://cds.linear.com/docs/en/datasheet/680313fa.pdf) -SSOP 0.5 -0 -44 -44 -Package_SO -SSOP-48_7.5x15.9mm_P0.635mm -SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot370-1_po.pdf) -SSOP 0.635 -0 -48 -48 -Package_SO -SSOP-56_7.5x18.5mm_P0.635mm -SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot371-1_po.pdf) -SSOP 0.635 -0 -56 -56 -Package_SO -STC_SOP-16_3.9x9.9mm_P1.27mm -STC SOP, 16 Pin (https://www.stcmicro.com/datasheet/STC15F2K60S2-en.pdf#page=156), generated with kicad-footprint-generator ipc_gullwing_generator.py -STC SOP SO -0 -16 -16 -Package_SO -ST_MultiPowerSO-30 -MultiPowerSO-30 3EP 16.0x17.2mm Pitch 1mm (http://www.st.com/resource/en/datasheet/vnh2sp30-e.pdf) -MultiPowerSO-30 3EP 16.0x17.2mm Pitch 1mm -0 -33 -33 -Package_SO -ST_PowerSSO-24_SlugDown -ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) -ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm -0 -25 -25 -Package_SO -ST_PowerSSO-24_SlugDown_ThermalVias -ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) -ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm -0 -38 -25 -Package_SO -ST_PowerSSO-24_SlugUp -ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) -ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm -0 -24 -24 -Package_SO -ST_PowerSSO-36_SlugDown -ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) -ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm -0 -37 -37 -Package_SO -ST_PowerSSO-36_SlugDown_ThermalVias -ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) -ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm -0 -50 -37 -Package_SO -ST_PowerSSO-36_SlugUp -ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) -ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm -0 -36 -36 -Package_SO -TI_SO-PowerPAD-8 -8-Lead Plastic PSOP, Exposed Die Pad (TI DDA0008B, see http://www.ti.com/lit/ds/symlink/lm3404.pdf) -SSOP 0.50 exposed pad -0 -12 -9 -Package_SO -TI_SO-PowerPAD-8_ThermalVias -8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf -HTSOP 1.27 -0 -19 -9 -Package_SO -TSOP-5_1.65x3.05mm_P0.95mm -TSOP-5 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf -Jedec MO-193C TSOP-5L -0 -5 -5 -Package_SO -TSOP-6_1.65x3.05mm_P0.95mm -TSOP-6 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf -Jedec MO-193C TSOP-6L -0 -6 -6 -Package_SO -TSOP-I-28_11.8x8mm_P0.55mm -TSOP I, 28 pins, 18.8x8mm body, 0.55mm pitch, IPC-calculated pads (http://ww1.microchip.com/downloads/en/devicedoc/doc0807.pdf) -TSOP I 28 pins -0 -28 -28 -Package_SO -TSOP-I-32_11.8x8mm_P0.5mm -TSOP-I, 32 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -TSOP-I SO -0 -32 -32 -Package_SO -TSOP-I-32_18.4x8mm_P0.5mm -TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf, http://www.fujitsu.com/downloads/MICRO/fma/pdfmcu/f32pm25.pdf) -TSOP I 32 -0 -32 -32 -Package_SO -TSOP-I-32_18.4x8mm_P0.5mm_Reverse -TSOP I, 32 pins, 18.4x8mm body (http://www.futurlec.com/Datasheet/Memory/628128.pdf), reverse mount -TSOP I 32 reverse -0 -32 -32 -Package_SO -TSOP-I-48_18.4x12mm_P0.5mm -TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf) -TSOP I 32 -0 -48 -48 -Package_SO -TSOP-I-56_18.4x14mm_P0.5mm -TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf) -TSOP I 32 -0 -56 -56 -Package_SO -TSOP-II-32_21.0x10.2mm_P1.27mm -32-lead plastic TSOP; Type II -TSOP-II 32 -0 -32 -32 -Package_SO -TSOP-II-44_10.16x18.41mm_P0.8mm -TSOP-II, 44 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -TSOP-II SO -0 -44 -44 -Package_SO -TSOP-II-54_22.2x10.16mm_P0.8mm -54-lead TSOP typ II package -TSOPII TSOP2 -0 -54 -54 -Package_SO -TSSOP-8_3x3mm_P0.65mm -TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot505-1_po.pdf) -SSOP 0.65 -0 -8 -8 -Package_SO -TSSOP-8_4.4x3mm_P0.65mm -8-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -8 -8 -Package_SO -TSSOP-10_3x3mm_P0.5mm -TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot552-1_po.pdf) -SSOP 0.5 -0 -10 -10 -Package_SO -TSSOP-14-1EP_4.4x5mm_P0.65mm -14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] with exposed pad (http://cds.linear.com/docs/en/datasheet/34301fa.pdf) -SSOP 0.65 exposed pad -0 -18 -15 -Package_SO -TSSOP-14_4.4x5mm_P0.65mm -14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -14 -14 -Package_SO -TSSOP-16-1EP_4.4x5mm_P0.65mm -FE Package; 16-Lead Plastic TSSOP (4.4mm); Exposed Pad Variation BB; (see Linear Technology 1956f.pdf) -SSOP 0.65 -0 -24 -17 -Package_SO -TSSOP-16_4.4x5mm_P0.65mm -16-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -16 -16 -Package_SO -TSSOP-20_4.4x6.5mm_P0.65mm -20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) -SSOP 0.65 -0 -20 -20 -Package_SO -TSSOP-24_4.4x7.8mm_P0.65mm -TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot355-1_po.pdf) -SSOP 0.65 -0 -24 -24 -Package_SO -TSSOP-28-1EP_4.4x9.7mm_P0.65mm -TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; Exposed Pad Variation; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot361-1_po.pdf) -SSOP 0.65 -0 -36 -29 -Package_SO -TSSOP-28_4.4x9.7mm_P0.65mm -TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot361-1_po.pdf) -SSOP 0.65 -0 -28 -28 -Package_SO -TSSOP-30_4.4x7.8mm_P0.5mm -TSSOP30: plastic thin shrink small outline package; 30 leads; body width 4.4 mm (http://www.ti.com/lit/ds/symlink/bq78350.pdf) -SSOP 0.5 -0 -30 -30 -Package_SO -TSSOP-32_6.1x11mm_P0.65mm -TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf) -SSOP 0.65 -0 -32 -32 -Package_SO -TSSOP-38_4.4x9.7mm_P0.5mm -TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot510-1_po.pdf) -SSOP 0.5 -0 -38 -38 -Package_SO -TSSOP-38_6.1x12.5mm_P0.65mm -TSSOP38: plastic thin shrink small outline package; 38 leads; body width 6.1 mm (http://www.ti.com/lit/ds/symlink/msp430g2744.pdf) -SSOP 0.65 -0 -38 -38 -Package_SO -TSSOP-44_4.4x11.2mm_P0.5mm -TSSOP44: plastic thin shrink small outline package; 44 leads; body width 4.4 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot510-1_po.pdf) -SSOP 0.5 -0 -44 -44 -Package_SO -TSSOP-48_6.1x12.5mm_P0.5mm -TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot362-1_po.pdf) -SSOP 0.5 -0 -48 -48 -Package_SO -TSSOP-56_6.1x14mm_P0.5mm -TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot364-1_po.pdf) -SSOP 0.5 -0 -56 -56 -Package_SO -Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm -Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf) -HSOP 1.27 -0 -11 -9 -Package_SO -Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm_ThermalVias -Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf) -HSOP 1.27 -0 -20 -9 -Package_SO -Texas_HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias -8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf -HTSOP 1.27 -0 -18 -9 -Package_SO -Texas_PWP0020A -20-Pin Thermally Enhanced Thin Shrink Small-Outline Package, Body 4.4x6.5x1.1mm, Pad 3.0x4.2mm, Texas Instruments (see http://www.ti.com/lit/ds/symlink/lm5118.pdf) -PWP HTSSOP 0.65mm -0 -25 -21 -Package_SO -Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm -HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HSOIC SO -0 -16 -9 -Package_SO -Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias -HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -HSOIC SO -0 -23 -9 -Package_SO -Texas_R-PDSO-N5 -Plastic Small outline http://www.ti.com/lit/ml/mpds158c/mpds158c.pdf -SOT23 R-PDSO-N5 -0 -5 -5 -Package_SO -VSO-40_7.6x15.4mm_P0.762mm -VSO40: plastic very small outline package; 40 leads (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot158-1_po.pdf) -SSOP 0.762 -0 -40 -40 -Package_SO -VSO-56_11.1x21.5mm_P0.75mm -VSO56: plastic very small outline package; 56 leads (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot190-1_po.pdf) -SSOP 0.75 -0 -56 -56 -Package_SO -VSSOP-8_2.3x2mm_P0.5mm -VSSOP-8 2.3x2mm Pitch 0.5mm -VSSOP-8 2.3x2mm Pitch 0.5mm -0 -8 -8 -Package_SO -VSSOP-8_2.4x2.1mm_P0.5mm -http://www.ti.com/lit/ml/mpds050d/mpds050d.pdf -VSSOP DCU R-PDSO-G8 Pitch0.5mm -0 -8 -8 -Package_SO -VSSOP-8_3.0x3.0mm_P0.65mm -VSSOP-8 3.0 x 3.0, http://www.ti.com/lit/ds/symlink/lm75b.pdf -VSSOP-8 3.0 x 3.0 -0 -8 -8 -Package_SO -VSSOP-10_3x3mm_P0.5mm -VSSOP, 10 Pin (http://www.ti.com/lit/ds/symlink/ads1115.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py -VSSOP SO -0 -10 -10 -Package_SO -Vishay_PowerPAK_1212-8_Dual -PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf) -Vishay_PowerPAK_1212-8_Dual -0 -6 -6 -Package_SO -Vishay_PowerPAK_1212-8_Single -PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf) -Vishay PowerPAK 1212-8 Single -0 -5 -5 -Package_SO -Zetex_SM8 -Zetex, SMD, 8 pin package (http://datasheet.octopart.com/ZDT6758TA-Zetex-datasheet-68057.pdf) -Zetex SM8 -0 -8 -8 -Package_SON -Diodes_PowerDI3333-8 -Diodes Incorporated PowerDI3333-8, Plastic Dual Flat No Lead Package, 3.3x3.3x0.8mm Body, https://www.diodes.com/assets/Package-Files/PowerDI3333-8.pdf -PowerDI 0.65 -0 -13 -5 -Package_SON -Fairchild_DualPower33-6_3x3mm -Fairchild Power33 MOSFET package, 3x3mm (see https://www.fairchildsemi.com/datasheets/FD/FDMC8032L.pdf) -mosfet -0 -18 -6 -Package_SON -Fairchild_MicroPak-6_1.0x1.45mm_P0.5mm -Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm https://www.nxp.com/docs/en/application-note/AN10343.pdff -Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm -0 -6 -6 -Package_SON -Fairchild_MicroPak2-6_1.0x1.0mm_P0.35mm -Fairchild-specific MicroPak2-6 1.0x1.0mm Pitch 0.35mm https://www.nxp.com/docs/en/application-note/AN10343.pdff -Fairchild-specific MicroPak2-6 1.0x1.0mm Pitch 0.35mm -0 -6 -6 -Package_SON -HUSON-3-1EP_2x2mm_P1.3mm_EP1.1x1.6mm -HUSON, 3 Pin, SOT1061 (Ref: https://assets.nexperia.com/documents/data-sheet/PMEG2020CPA.pdf) -huson nolead SOT1061 -0 -4 -3 -Package_SON -HVSON-8-1EP_4x4mm_P0.8mm_EP2.2x3.1mm -HVSON, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf (page 57)), generated with kicad-footprint-generator ipc_noLead_generator.py -HVSON NoLead -0 -13 -9 -Package_SON -Infineon_PG-TISON-8-2 -Infineon, PG-TISON-8-2, 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http://www.ti.com/lit/ds/symlink/tps63060.pdf -0.5 S-PWSON-N10 DSC -0 -47 -11 -Package_SON -Texas_X2SON-4_1x1mm_P0.65mm -X2SON 5 pin 1x1mm package (Reference Datasheet: http://www.ti.com/lit/ds/sbvs193d/sbvs193d.pdf Reference part: TPS383x) [StepUp generated footprint] -X2SON -0 -13 -5 -Package_SON -USON-10_2.5x1.0mm_P0.5mm -USON-10 2.5x1.0mm_ Pitch 0.5mm http://www.ti.com/lit/ds/symlink/tpd4e02b04.pdf -USON-10 2.5x1.0mm Pitch 0.5mm -0 -10 -10 -Package_SON -USON-20_2x4mm_P0.4mm -USON-20 2x4mm Pitch 0.4mm http://www.ti.com/lit/ds/symlink/txb0108.pdf -USON-20 2x4mm Pitch 0.4mm -0 -20 -20 -Package_SON -VSON-8_3.3x3.3mm_P0.65mm_NexFET -8-Lead Plastic Dual Flat, No Lead Package (MF) - 3.3x3.3x1 mm Body [VSON] http://www.ti.com/lit/ds/symlink/csd87334q3d.pdf -VSON 0.65 -0 -12 -5 -Package_SON -VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm -VSON, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_noLead_generator.py -VSON NoLead -0 -15 -11 -Package_SON -VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm_ThermalVias -VSON, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_noLead_generator.py -VSON NoLead -0 -18 -11 -Package_SON -VSON-10-1EP_3x3mm_P0.5mm_EP1.65x2.4mm -VSON 10 Thermal on 11 3x3mm Pitch 0.5mm http://chip.tomsk.ru/chip/chipdoc.nsf/Package/D8A64DD165C2AAD9472579400024FC41!OpenDocument -VSON 10 Thermal on 11 3x3mm Pitch 0.5mm -0 -21 -11 -Package_SON -VSON-10-1EP_3x3mm_P0.5mm_EP1.65x2.4mm_ThermalVias -VSON 10 Thermal on 11 3x3mm Pitch 0.5mm http://chip.tomsk.ru/chip/chipdoc.nsf/Package/D8A64DD165C2AAD9472579400024FC41!OpenDocument -VSON 10 Thermal on 11 3x3mm Pitch 0.5mm -0 -27 -11 -Package_SON -VSONP-8-1EP_5x6_P1.27mm -SON, 8-Leads, Body 5x6x1mm, Pitch 1.27mm; (see Texas Instruments CSD18531Q5A http://www.ti.com/lit/ds/symlink/csd18531q5a.pdf) -VSONP 1.27 -0 -13 -3 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http://www.ti.com/lit/ds/symlink/pca9306.pdf -X2SON-8 1.4x1mm Pitch0.35mm -0 -8 -8 -Package_SO_J-Lead -TSOC-6_3.76x3.94mm_P1.27mm -Maxim Integrated TSOC-6 D6+1,https://datasheets.maximintegrated.com/en/ds/DS2401.pdf, https://pdfserv.maximintegrated.com/land_patterns/90-0321.PDF -TSOC-6 -0 -6 -6 -Package_TO_SOT_SMD -ATPAK-2 -ATPAK SMD package, http://www.onsemi.com/pub/Collateral/ENA2192-D.PDF -ATPAK -0 -7 -3 -Package_TO_SOT_SMD -Analog_KS-4 -Analog Devices KS-4, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sc70ks/ks_4.pdf -Analog Devices KS-4 (like EIAJ SC-82) -0 -4 -4 -Package_TO_SOT_SMD -Diodes_SOT-553 -Diodes SOT-553, https://www.diodes.com/assets/Package-Files/SOT553.pdf -SOT-553 -0 -5 -5 -Package_TO_SOT_SMD -HVSOF5 -HVSOF5, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hvsof5_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/hall/bu52001gul-e.pdf -HVSOF5 -0 -5 -5 -Package_TO_SOT_SMD -HVSOF6 -HVSOF6, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hvsof6_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/audio_video/video_amplifier/bh76106hfv-e.pdf -HVSOF6 -0 -7 -7 -Package_TO_SOT_SMD -Infineon_PG-HDSOP-10-1 -Infineon PG-HDSOP-10-1 (DDPAK), 20.96x6.5x2.3mm, slug up (https://www.infineon.com/cms/en/product/packages/PG-HDSOP/PG-HDSOP-10-1/) -hdsop 10 ddpak -0 -10 -10 -Package_TO_SOT_SMD -Infineon_PG-HSOF-8-1 -Infineon HSOF-8-1 power mosfet http://www.infineon.com/cms/en/product/packages/PG-HSOF/PG-HSOF-8-1/ -mosfet hsof -0 -54 -3 -Package_TO_SOT_SMD -Infineon_PG-HSOF-8-1_ThermalVias -HSOF-8-1 power mosfet http://www.infineon.com/cms/en/product/packages/PG-HSOF/PG-HSOF-8-1/ -mosfet hsof thermal vias -0 -57 -3 -Package_TO_SOT_SMD -Infineon_PG-TO-220-7Lead_TabPin8 -Infineon PG-TO-220-7, Tab as Pin 8, see e.g. https://www.infineon.com/dgdl/Infineon-BTS50055-1TMC-DS-v01_00-EN.pdf?fileId=5546d4625a888733015aa9b0007235e9 -Infineon PG-TO-220-7 -0 -12 -8 -Package_TO_SOT_SMD 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http://rohmfs.rohm.com/en/products/databook/datasheet/ic/motor/dc/bd621x-e.pdf -Rohm HRP7 SMD -0 -69 -7 -Package_TO_SOT_SMD -SC-59 -SC-59, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg -SC-59 -0 -3 -3 -Package_TO_SOT_SMD -SC-59_Handsoldering -SC-59, hand-soldering varaint, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg -SC-59 hand-soldering -0 -3 -3 -Package_TO_SOT_SMD -SC-70-8 -SC70-8 -SC70-8 -0 -8 -8 -Package_TO_SOT_SMD -SC-70-8_Handsoldering -SC70-8, Handsoldering -SC70-8 Handsoldering -0 -8 -8 -Package_TO_SOT_SMD -SC-82AA -SC-82AA -SC-82AA -0 -4 -4 -Package_TO_SOT_SMD -SC-82AA_Handsoldering -SC-82AA -SC-82AA -0 -4 -4 -Package_TO_SOT_SMD -SC-82AB -SC-82AB -SC-82AB -0 -4 -4 -Package_TO_SOT_SMD -SC-82AB_Handsoldering -SC-82AB -SC-82AB -0 -4 -4 -Package_TO_SOT_SMD -SOT-23 -SOT-23, Standard -SOT-23 -0 -3 -3 -Package_TO_SOT_SMD -SOT-23-5 -5-pin SOT23 package -SOT-23-5 -0 -5 -5 -Package_TO_SOT_SMD -SOT-23-5_HandSoldering -5-pin SOT23 package -SOT-23-5 hand-soldering -0 -5 -5 -Package_TO_SOT_SMD -SOT-23-6 -6-pin SOT-23 package -SOT-23-6 -0 -6 -6 -Package_TO_SOT_SMD -SOT-23-6_Handsoldering -6-pin SOT-23 package, Handsoldering -SOT-23-6 Handsoldering -0 -6 -6 -Package_TO_SOT_SMD -SOT-23-8 -8-pin SOT-23 package, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sot-23rj/rj_8.pdf -SOT-23-8 -0 -8 -8 -Package_TO_SOT_SMD -SOT-23-8_Handsoldering -8-pin SOT-23 package, Handsoldering, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sot-23rj/rj_8.pdf -SOT-23-8 Handsoldering -0 -8 -8 -Package_TO_SOT_SMD -SOT-23W -SOT-23W http://www.allegromicro.com/~/media/Files/Datasheets/A112x-Datasheet.ashx?la=en&hash=7BC461E058CC246E0BAB62433B2F1ECA104CA9D3 -SOT-23W -0 -3 -3 -Package_TO_SOT_SMD -SOT-23W_Handsoldering -SOT-23W http://www.allegromicro.com/~/media/Files/Datasheets/A112x-Datasheet.ashx?la=en&hash=7BC461E058CC246E0BAB62433B2F1ECA104CA9D3 -SOT-23W for handsoldering -0 -3 -3 -Package_TO_SOT_SMD -SOT-23_Handsoldering -SOT-23, Handsoldering -SOT-23 -0 -3 -3 -Package_TO_SOT_SMD -SOT-89-3 -SOT-89-3 -SOT-89-3 -0 -6 -3 -Package_TO_SOT_SMD -SOT-89-3_Handsoldering -SOT-89-3 Handsoldering -SOT-89-3 Handsoldering -0 -5 -3 -Package_TO_SOT_SMD -SOT-89-5 -SOT-89-5, Housing,http://www.e-devices.ricoh.co.jp/en/products/product_power/pkg/sot-89-5.pdf -SOT-89-5 Housing -0 -9 -5 -Package_TO_SOT_SMD -SOT-89-5_Handsoldering -SOT89-5, Housing,http://www.e-devices.ricoh.co.jp/en/products/product_power/pkg/sot-89-5.pdf -SOT89-5 Housing -0 -9 -5 -Package_TO_SOT_SMD -SOT-143 -SOT-143 -SOT-143 -0 -4 -4 -Package_TO_SOT_SMD -SOT-143R_Reverse -SOT-143R Reverse -SOT-143R Reverse -0 -4 -4 -Package_TO_SOT_SMD -SOT-143R_Reverse_Handsoldering -SOT-143R Reverse Handsoldering -SOT-143 Reverse Handsoldering -0 -4 -4 -Package_TO_SOT_SMD -SOT-143_Handsoldering -SOT-143 Handsoldering -SOT-143 Handsoldering -0 -4 -4 -Package_TO_SOT_SMD -SOT-223 -module CMS SOT223 4 pins -CMS SOT -0 -4 -4 -Package_TO_SOT_SMD -SOT-223-3_TabPin2 -module CMS SOT223 4 pins -CMS SOT -0 -4 -3 -Package_TO_SOT_SMD -SOT-223-5 -module CMS SOT223 5 pins, http://ww1.microchip.com/downloads/en/DeviceDoc/51751a.pdf -CMS SOT -0 -5 -5 -Package_TO_SOT_SMD -SOT-223-6 -module CMS SOT223 6 pins, http://www.ti.com/lit/ds/symlink/tps737.pdf -CMS SOT -0 -6 -6 -Package_TO_SOT_SMD -SOT-223-6_TabPin3 -module CMS SOT223 6 pins, http://www.ti.com/lit/ds/symlink/tps737.pdf -CMS SOT -0 -6 -5 -Package_TO_SOT_SMD -SOT-223-8 -module CMS SOT223 8 pins, https://www.diodes.com/assets/Datasheets/ZXSBMR16PT8.pdf -CMS SOT -0 -8 -8 -Package_TO_SOT_SMD -SOT-323_SC-70 -SOT-323, SC-70 -SOT-323 SC-70 -0 -3 -3 -Package_TO_SOT_SMD -SOT-323_SC-70_Handsoldering -SOT-323, SC-70 Handsoldering -SOT-323 SC-70 Handsoldering -0 -3 -3 -Package_TO_SOT_SMD -SOT-343_SC-70-4 -SOT-343, SC-70-4 -SOT-343 SC-70-4 -0 -4 -4 -Package_TO_SOT_SMD -SOT-343_SC-70-4_Handsoldering -SOT-343, SC-70-4, Handsoldering -SOT-343 SC-70-4 Handsoldering -0 -4 -4 -Package_TO_SOT_SMD -SOT-353_SC-70-5 -SOT-353, SC-70-5 -SOT-353 SC-70-5 -0 -5 -5 -Package_TO_SOT_SMD -SOT-353_SC-70-5_Handsoldering -SOT-353, SC-70-5, Handsoldering -SOT-353 SC-70-5 Handsoldering -0 -5 -5 -Package_TO_SOT_SMD -SOT-363_SC-70-6 -SOT-363, SC-70-6 -SOT-363 SC-70-6 -0 -6 -6 -Package_TO_SOT_SMD -SOT-363_SC-70-6_Handsoldering -SOT-363, SC-70-6, Handsoldering -SOT-363 SC-70-6 Handsoldering -0 -6 -6 -Package_TO_SOT_SMD -SOT-383F -8-pin SOT-383F, http://www.mouser.com/ds/2/80/CPDVR085V0C-HF-RevB-10783.pdf -SOT-383F -0 -9 -9 -Package_TO_SOT_SMD -SOT-383FL -8-pin SOT-383FL package, http://www.onsemi.com/pub_link/Collateral/ENA2267-D.PDF -SOT-383FL -0 -8 -8 -Package_TO_SOT_SMD -SOT-416 -SOT-416, https://www.nxp.com/docs/en/package-information/SOT416.pdf -SOT-416 -0 -3 -3 -Package_TO_SOT_SMD -SOT-543 -SOT-543 4 lead surface package -SOT-543 SC-107A EMD4 -0 -4 -4 -Package_TO_SOT_SMD -SOT-553 -SOT553 -SOT-553 -0 -5 -5 -Package_TO_SOT_SMD -SOT-563 -SOT563 -SOT-563 -0 -6 -6 -Package_TO_SOT_SMD -SOT-665 -SOT665 -SOT-665 -0 -5 -5 -Package_TO_SOT_SMD -SOT-666 -SOT666 -SOT-666 -0 -6 -6 -Package_TO_SOT_SMD -SOT-723 -http://toshiba.semicon-storage.com/info/docget.jsp?did=5879&prodName=RN1104MFV -sot 723 -0 -3 -3 -Package_TO_SOT_SMD -SOT-883 -SOT-883, https://assets.nexperia.com/documents/outline-drawing/SOT883.pdf -SOT-883 -0 -3 -3 -Package_TO_SOT_SMD -SOT-886 -SOT-886 -SOT-886 -0 -6 -6 -Package_TO_SOT_SMD -SOT-963 -SOT 963 6 pins package 1x0.8mm pitch 0.35mm -SOT 963 6 pins package 1x0.8mm pitch 0.35mm -0 -6 -6 -Package_TO_SOT_SMD -SOT-1123 -SOT-1123 small outline transistor (see http://www.onsemi.com/pub/Collateral/NST3906F3-D.PDF) -SOT-1123 transistor -0 -3 -3 -Package_TO_SOT_SMD -SOT-1333-1 -SOT-1333-1 -SOT-1333-1 -0 -9 -9 -Package_TO_SOT_SMD -SOT-1334-1 -SOT-1334-1 -SOT-1334-1 -0 -14 -14 -Package_TO_SOT_SMD -SuperSOT-3 -3-pin SuperSOT package https://www.fairchildsemi.com/package-drawings/MA/MA03B.pdf -SuperSOT-3 SSOT-3 -0 -3 -3 -Package_TO_SOT_SMD -SuperSOT-6 -6-pin SuperSOT package http://www.mouser.com/ds/2/149/FMB5551-889214.pdf -SuperSOT-6 SSOT-6 -0 -6 -6 -Package_TO_SOT_SMD -SuperSOT-8 -8-pin SuperSOT package, http://www.icbank.com/icbank_data/semi_package/ssot8_dim.pdf -SuperSOT-8 SSOT-8 -0 -8 -8 -Package_TO_SOT_SMD -TDSON-8-1 -Power MOSFET package, TDSON-8-1, 5.15x5.9mm (https://www.infineon.com/cms/en/product/packages/PG-TDSON/PG-TDSON-8-1/) -tdson -0 -14 -5 -Package_TO_SOT_SMD -TO-50-3_LongPad-NoHole_Housing -TO-50-3 Macro T Package Style M236 -TO-50-3 Macro T Package Style M236 -0 -3 -3 -Package_TO_SOT_SMD -TO-50-3_LongPad-WithHole_Housing -TO-50-3 Macro T Package Style M236 -TO-50-3 Macro T Package Style M236 -0 -3 -3 -Package_TO_SOT_SMD -TO-50-3_ShortPad-NoHole_Housing -TO-50-3 Macro T Package Style M236 -TO-50-3 Macro T Package Style M236 -0 -3 -3 -Package_TO_SOT_SMD -TO-50-3_ShortPad-WithHole_Housing -TO-50-3 Macro T Package Style M236 -TO-50-3 Macro T Package Style M236 -0 -3 -3 -Package_TO_SOT_SMD -TO-50-4_LongPad-NoHole_Housing -TO-50-4 Macro X Package Style M238 -TO-50-4 Macro X Package Style M238 -0 -4 -4 -Package_TO_SOT_SMD -TO-50-4_LongPad-WithHole_Housing -TO-50-4 Macro X Package Style M238 -TO-50-4 Macro X Package Style M238 -0 -4 -4 -Package_TO_SOT_SMD -TO-50-4_ShortPad-NoHole_Housing -TO-50-4 Macro X Package Style M238 -TO-50-4 Macro X Package Style M238 -0 -4 -4 -Package_TO_SOT_SMD -TO-50-4_ShortPad-WithHole_Housing -TO-50-4 Macro X Package Style M238 -TO-50-4 Macro X Package Style M238 -0 -4 -4 -Package_TO_SOT_SMD -TO-252-2 -TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/ -DPAK TO-252 DPAK-3 TO-252-3 SOT-428 -0 -7 -3 -Package_TO_SOT_SMD -TO-252-2_TabPin1 -TO-252-2, tab to pin 1 https://www.wolfspeed.com/media/downloads/87/CSD01060.pdf -TO-252-2 diode -0 -7 -2 -Package_TO_SOT_SMD -TO-252-3_TabPin2 -TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/ -DPAK TO-252 DPAK-3 TO-252-3 SOT-428 -0 -8 -3 -Package_TO_SOT_SMD -TO-252-3_TabPin4 -TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/ -DPAK TO-252 DPAK-3 TO-252-3 SOT-428 -0 -8 -4 -Package_TO_SOT_SMD -TO-252-4 -TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/ -DPAK TO-252 DPAK-5 TO-252-5 -0 -9 -5 -Package_TO_SOT_SMD -TO-252-5_TabPin3 -TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/ -DPAK TO-252 DPAK-5 TO-252-5 -0 -10 -5 -Package_TO_SOT_SMD -TO-252-5_TabPin6 -TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/ -DPAK TO-252 DPAK-5 TO-252-5 -0 -10 -6 -Package_TO_SOT_SMD -TO-263-2 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/ -D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 -0 -7 -3 -Package_TO_SOT_SMD -TO-263-2_TabPin1 -TO-263 / D2PAK / DDPAK SMD package, tab to pin 1, https://www.wolfspeed.com/media/downloads/137/C3D06060G.pdf -D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 diode -0 -7 -2 -Package_TO_SOT_SMD -TO-263-3_TabPin2 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/ -D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 -0 -8 -3 -Package_TO_SOT_SMD -TO-263-3_TabPin4 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/ -D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 -0 -8 -4 -Package_TO_SOT_SMD -TO-263-4 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ -D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426 -0 -9 -5 -Package_TO_SOT_SMD -TO-263-5_TabPin3 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ -D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426 -0 -10 -5 -Package_TO_SOT_SMD -TO-263-5_TabPin6 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ -D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426 -0 -10 -6 -Package_TO_SOT_SMD -TO-263-6 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/ -D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 -0 -11 -7 -Package_TO_SOT_SMD -TO-263-7_TabPin4 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/ -D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 -0 -12 -7 -Package_TO_SOT_SMD -TO-263-7_TabPin8 -TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/ -D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 -0 -12 -8 -Package_TO_SOT_SMD -TO-263-9_TabPin5 -TO-263 / D2PAK / DDPAK SMD package, http://www.ti.com/lit/ds/symlink/lm4755.pdf -D2PAK DDPAK TO-263 D2PAK-9 TO-263-9 -0 -14 -9 -Package_TO_SOT_SMD -TO-263-9_TabPin10 -TO-263 / D2PAK / DDPAK SMD package, http://www.ti.com/lit/ds/symlink/lm4755.pdf -D2PAK DDPAK TO-263 D2PAK-9 TO-263-9 -0 -14 -10 -Package_TO_SOT_SMD -TO-268-2 -TO-268/D3PAK SMD package, http://www.icbank.com/icbank_data/semi_package/to268aa_dim.pdf -D3PAK TO-268 D3PAK-3 TO-268-3 -0 -7 -3 -Package_TO_SOT_SMD -TO-269AA -SMD package TO-269AA (e.g. diode bridge), see http://www.vishay.com/docs/88854/padlayouts.pdf -TO-269AA MBS diode bridge -0 -4 -4 -Package_TO_SOT_SMD -TO-277A -Thermal enhanced ultra thin SMD package; 3 leads; body: 4.3x6.1x0.43mm, https://www.vishay.com/docs/95570/to-277asmpc.pdf -TO-277A SMPC -0 -12 -3 -Package_TO_SOT_SMD -TO-277B -TO-227B https://media.digikey.com/pdf/Data%20Sheets/Littelfuse%20PDFs/DST2050S.pdf -TO-277B -0 -9 -3 -Package_TO_SOT_SMD -TSOT-23 -3-pin TSOT23 package, http://www.analog.com.tw/pdf/All_In_One.pdf -TSOT-23 -0 -3 -3 -Package_TO_SOT_SMD -TSOT-23-5 -5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf -TSOT-23-5 -0 -5 -5 -Package_TO_SOT_SMD -TSOT-23-5_HandSoldering -5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf -TSOT-23-5 Hand-soldering -0 -5 -5 -Package_TO_SOT_SMD -TSOT-23-6 -6-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_6_05-08-1636.pdf -TSOT-23-6 MK06A TSOT-6 -0 -6 -6 -Package_TO_SOT_SMD -TSOT-23-6_HandSoldering -6-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_6_05-08-1636.pdf -TSOT-23-6 MK06A TSOT-6 Hand-soldering -0 -6 -6 -Package_TO_SOT_SMD -TSOT-23-8 -8-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf -TSOT-23-8 -0 -8 -8 -Package_TO_SOT_SMD -TSOT-23-8_HandSoldering -8-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf -TSOT-23-8 Hand-soldering -0 -8 -8 -Package_TO_SOT_SMD -TSOT-23_HandSoldering -5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf -TSOT-23 Hand-soldering -0 -3 -3 -Package_TO_SOT_SMD -Texas_DRT-3 -Texas Instrument DRT-3 1x0.8mm Pitch 0.7mm http://www.ti.com/lit/ds/symlink/tpd2eusb30.pdf -DRT-3 1x0.8mm Pitch 0.7mm -0 -3 -3 -Package_TO_SOT_SMD -Texas_NDY0011A -TO-PMOD-11 11-pin switching regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf -Texas TO-PMOD NDY00011A -0 -12 -12 -Package_TO_SOT_SMD -Texas_R-PDSO-G6 -R-PDSO-G6, http://www.ti.com/lit/ds/slis144b/slis144b.pdf -R-PDSO-G6 SC-70-6 -0 -6 -6 -Package_TO_SOT_SMD -VSOF5 -VSOF5 -VSOF5 -0 -5 -5 -Package_TO_SOT_SMD -Vishay_PowerPAK_SC70-6L_Dual -Vishay PowerPAK SC70 dual transistor package http://www.vishay.com/docs/70487/70487.pdf -powerpak sc70 sc-70 dual -0 -8 -6 -Package_TO_SOT_SMD -Vishay_PowerPAK_SC70-6L_Single -Vishay PowerPAK SC70 single transistor package http://www.vishay.com/docs/70486/70486.pdf -powerpak sc70 sc-70 -0 -6 -3 -Package_TO_SOT_THT -Fairchild_TO-220F-6L -Fairchild TO-220F-6L, http://www.mouser.com/ds/2/149/FSL136MRT-113334.pdf -Fairchild TO-220F-6L -0 -6 -6 -Package_TO_SOT_THT -Heraeus_TO-92-2 -TO-92 2-pin variant by Heraeus, drill 0.75mm (http://www.produktinfo.conrad.com/datenblaetter/175000-199999/181293-da-01-de-TO92_Temperatursensor_PT1000_32209225.pdf) -to-92 -0 -2 -2 -Package_TO_SOT_THT -NEC_Molded_7x4x9mm -Molded Japan Transistor Package 7x4x9mm^3, http://rtellason.com/transdata/2sb734.pdf -Japan transistor -0 -3 -3 -Package_TO_SOT_THT -PowerIntegrations_TO-220-7C -Non Isolated Modified TO-220 7pin Package, see http://www.farnell.com/datasheets/5793.pdf -Power Integration Y Package -0 -6 -6 -Package_TO_SOT_THT -SIPAK-1EP_Horizontal_TabDown -SIPAK, Horizontal, RM 2.286mm -SIPAK Horizontal RM 2.286mm -0 -4 -4 -Package_TO_SOT_THT -SIPAK_Vertical -SIPAK, Vertical, RM 2.286mm -SIPAK Vertical RM 2.286mm -0 -3 -3 -Package_TO_SOT_THT -SOD-70_P2.54mm -Plastic near cylindrical package Sod-70 see: https://www.nxp.com/docs/en/data-sheet/KTY81_SER.pdf [StepUp generated footprint] -Sod-70 -0 -2 -2 -Package_TO_SOT_THT -SOD-70_P5.08mm -Plastic near cylindrical package Sod-70 see: https://www.nxp.com/docs/en/data-sheet/KTY81_SER.pdf [StepUp generated footprint] -Sod-70 -0 -2 -2 -Package_TO_SOT_THT -SOT-227 -SOT-227 / SOT-227B / ISOTOP, M4 mounting screws (https://www.vishay.com/docs/95423/sot227g2.pdf, https://www.vishay.com/docs/95793/vs-fc420sa10.pdf) -sot 227 isotop -0 -8 -4 -Package_TO_SOT_THT -TO-3 -Transistor TO-3 -TR TO-3 TO3 TO-204 -0 -4 -3 -Package_TO_SOT_THT -TO-3P-3_Horizontal_TabDown -TO-3P-3, Horizontal, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html -TO-3P-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-3P-3_Horizontal_TabUp -TO-3P-3, Horizontal, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html -TO-3P-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-3P-3_Vertical -TO-3P-3, Vertical, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html -TO-3P-3 Vertical RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-3PB-3_Horizontal_TabDown -TO-3PB-3, Horizontal, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF -TO-3PB-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-3PB-3_Horizontal_TabUp -TO-3PB-3, Horizontal, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF -TO-3PB-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-3PB-3_Vertical -TO-3PB-3, Vertical, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF -TO-3PB-3 Vertical RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-5-2 -TO-5-2 -TO-5-2 -0 -2 -2 -Package_TO_SOT_THT -TO-5-2_Window -TO-5-2_Window, Window -TO-5-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-5-3 -TO-5-3 -TO-5-3 -0 -3 -3 -Package_TO_SOT_THT -TO-5-3_Window -TO-5-3_Window, Window -TO-5-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-5-4 -TO-5-4 -TO-5-4 -0 -4 -4 -Package_TO_SOT_THT -TO-5-4_Window -TO-5-4_Window, Window -TO-5-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-5-6 -TO-5-6 -TO-5-6 -0 -6 -6 -Package_TO_SOT_THT -TO-5-6_Window -TO-5-6_Window, Window -TO-5-6_Window Window -0 -6 -6 -Package_TO_SOT_THT -TO-5-8 -TO-5-8 -TO-5-8 -0 -8 -8 -Package_TO_SOT_THT -TO-5-8_PD5.08 -TO-5-8_PD5.08 -TO-5-8_PD5.08 -0 -8 -8 -Package_TO_SOT_THT -TO-5-8_PD5.08_Window -TO-5-8_PD5.08_Window, Window -TO-5-8_PD5.08_Window Window -0 -8 -8 -Package_TO_SOT_THT -TO-5-8_Window -TO-5-8_Window, Window -TO-5-8_Window Window -0 -8 -8 -Package_TO_SOT_THT -TO-5-10 -TO-5-10 -TO-5-10 -0 -10 -10 -Package_TO_SOT_THT -TO-5-10_Window -TO-5-10_Window, Window -TO-5-10_Window Window -0 -10 -10 -Package_TO_SOT_THT -TO-8-2 -TO-8-2 -TO-8-2 -0 -2 -2 -Package_TO_SOT_THT -TO-8-2_Window -TO-8-2_Window, Window -TO-8-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-8-3 -TO-8-3 -TO-8-3 -0 -3 -3 -Package_TO_SOT_THT -TO-8-3_Window -TO-8-3_Window, Window -TO-8-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-11-2 -TO-11-2 -TO-11-2 -0 -2 -2 -Package_TO_SOT_THT -TO-11-2_Window -TO-11-2_Window, Window -TO-11-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-11-3 -TO-11-3 -TO-11-3 -0 -3 -3 -Package_TO_SOT_THT -TO-11-3_Window -TO-11-3_Window, Window -TO-11-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-12-4 -TO-12-4 -TO-12-4 -0 -4 -4 -Package_TO_SOT_THT -TO-12-4_Window -TO-12-4_Window, Window -TO-12-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-17-4 -TO-17-4 -TO-17-4 -0 -4 -4 -Package_TO_SOT_THT -TO-17-4_Window -TO-17-4_Window, Window -TO-17-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-18-2 -TO-18-2 -TO-18-2 -0 -2 -2 -Package_TO_SOT_THT -TO-18-2_Lens -TO-18-2_Lens, Lens -TO-18-2_Lens Lens -0 -2 -2 -Package_TO_SOT_THT -TO-18-2_Window -TO-18-2_Window, Window -TO-18-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-18-3 -TO-18-3 -TO-18-3 -0 -3 -3 -Package_TO_SOT_THT -TO-18-3_Lens -TO-18-3_Lens, Lens -TO-18-3_Lens Lens -0 -3 -3 -Package_TO_SOT_THT -TO-18-3_Window -TO-18-3_Window, Window -TO-18-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-18-4 -TO-18-4 -TO-18-4 -0 -4 -4 -Package_TO_SOT_THT -TO-18-4_Lens -TO-18-4_Lens, Lens -TO-18-4_Lens Lens -0 -4 -4 -Package_TO_SOT_THT -TO-18-4_Window -TO-18-4_Window, Window -TO-18-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-33-4 -TO-33-4 -TO-33-4 -0 -4 -4 -Package_TO_SOT_THT -TO-33-4_Window -TO-33-4_Window, Window -TO-33-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-38-2 -TO-38-2 -TO-38-2 -0 -2 -2 -Package_TO_SOT_THT -TO-38-2_Window -TO-38-2_Window, Window -TO-38-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-38-3 -TO-38-3 -TO-38-3 -0 -3 -3 -Package_TO_SOT_THT -TO-38-3_Window -TO-38-3_Window, Window -TO-38-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-39-2 -TO-39-2 -TO-39-2 -0 -2 -2 -Package_TO_SOT_THT -TO-39-2_Window -TO-39-2_Window, Window -TO-39-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-39-3 -TO-39-3 -TO-39-3 -0 -3 -3 -Package_TO_SOT_THT -TO-39-3_Window -TO-39-3_Window, Window -TO-39-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-39-4 -TO-39-4 -TO-39-4 -0 -4 -4 -Package_TO_SOT_THT -TO-39-4_Window -TO-39-4_Window, Window -TO-39-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-39-6 -TO-39-6 -TO-39-6 -0 -6 -6 -Package_TO_SOT_THT -TO-39-6_Window -TO-39-6_Window, Window -TO-39-6_Window Window -0 -6 -6 -Package_TO_SOT_THT -TO-39-8 -TO-39-8 -TO-39-8 -0 -8 -8 -Package_TO_SOT_THT -TO-39-8_Window -TO-39-8_Window, Window -TO-39-8_Window Window -0 -8 -8 -Package_TO_SOT_THT -TO-39-10 -TO-39-10 -TO-39-10 -0 -10 -10 -Package_TO_SOT_THT -TO-39-10_Window -TO-39-10_Window, Window -TO-39-10_Window Window -0 -10 -10 -Package_TO_SOT_THT -TO-46-2 -TO-46-2 -TO-46-2 -0 -2 -2 -Package_TO_SOT_THT -TO-46-2_Pin2Center -TO-46-2, Pin2 at center of package, Thorlabs photodiodes -TO-46-2 Thorlabs -0 -2 -2 -Package_TO_SOT_THT -TO-46-2_Pin2Center_Window -TO-46-2, Pin2 at center of package, Thorlabs photodiodes -TO-46-2 Thorlabs -0 -2 -2 -Package_TO_SOT_THT -TO-46-2_Window -TO-46-2_Window, Window -TO-46-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-46-3 -TO-46-3 -TO-46-3 -0 -3 -3 -Package_TO_SOT_THT -TO-46-3_Pin2Center -TO-46-3, Pin2 at center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf -TO-46-3 Thorlabs -0 -3 -3 -Package_TO_SOT_THT -TO-46-3_Pin2Center_Window -TO-46-3, Pin2 at center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf -TO-46-3 Thorlabs -0 -3 -3 -Package_TO_SOT_THT -TO-46-3_Window -TO-46-3_Window, Window -TO-46-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-46-4 -TO-46-4 -TO-46-4 -0 -4 -4 -Package_TO_SOT_THT -TO-46-4_Window -TO-46-4_Window, Window -TO-46-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-52-2 -TO-52-2 -TO-52-2 -0 -2 -2 -Package_TO_SOT_THT -TO-52-2_Window -TO-52-2_Window, Window -TO-52-2_Window Window -0 -2 -2 -Package_TO_SOT_THT -TO-52-3 -TO-52-3 -TO-52-3 -0 -3 -3 -Package_TO_SOT_THT -TO-52-3_Window -TO-52-3_Window, Window -TO-52-3_Window Window -0 -3 -3 -Package_TO_SOT_THT -TO-72-4 -TO-72-4 -TO-72-4 -0 -4 -4 -Package_TO_SOT_THT -TO-72-4_Window -TO-72-4_Window, Window -TO-72-4_Window Window -0 -4 -4 -Package_TO_SOT_THT -TO-75-6 -TO-75-6 -TO-75-6 -0 -6 -6 -Package_TO_SOT_THT -TO-75-6_Window -TO-75-6_Window, Window -TO-75-6_Window Window -0 -6 -6 -Package_TO_SOT_THT -TO-78-6 -TO-78-6 -TO-78-6 -0 -6 -6 -Package_TO_SOT_THT -TO-78-6_Window -TO-78-6_Window, Window -TO-78-6_Window Window -0 -6 -6 -Package_TO_SOT_THT -TO-78-8 -TO-78-8 -TO-78-8 -0 -8 -8 -Package_TO_SOT_THT -TO-78-8_Window -TO-78-8_Window, Window -TO-78-8_Window Window -0 -8 -8 -Package_TO_SOT_THT -TO-78-10 -TO-78-10 -TO-78-10 -0 -10 -10 -Package_TO_SOT_THT -TO-78-10_Window -TO-78-10_Window, Window -TO-78-10_Window Window -0 -10 -10 -Package_TO_SOT_THT -TO-92 -TO-92 leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92-2 -TO-92 2-pin leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 diode SOD70 -0 -2 -2 -Package_TO_SOT_THT -TO-92-2_Horizontal1 -2-pin TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 temperature sensor diode -0 -2 -2 -Package_TO_SOT_THT -TO-92-2_Horizontal2 -2-pin TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 temperature sensor diode -0 -2 -2 -Package_TO_SOT_THT -TO-92-2_W4.0mm_Horizontal_FlatSideDown -TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -2 -2 -Package_TO_SOT_THT -TO-92-2_W4.0mm_Horizontal_FlatSideUp -TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -2 -2 -Package_TO_SOT_THT -TO-92-2_Wide -TO-92 2-pin leads in-line, wide, drill 0.75mm -to-92 sc-43 sc-43a sot54 PA33 diode SOD70 -0 -2 -2 -Package_TO_SOT_THT -TO-92Flat -TO-92Flat package, often used for hall sensors, drill 0.75mm (see e.g. http://www.ti.com/lit/ds/symlink/drv5023.pdf) -to-92Flat hall sensor -0 -3 -3 -Package_TO_SOT_THT -TO-92L -TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) -TO-92L Molded Narrow transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92L_HandSolder -TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm, hand-soldering variant with enlarged pads (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92L_Inline -TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) -TO-92L Inline Wide transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92L_Inline_Wide -TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) -TO-92L Inline Wide transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92L_Wide -TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) -TO-92L Molded Wide transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92Mini-2 -TO-92Mini package, drill 0.6mm (https://media.digikey.com/pdf/Data%20Sheets/Infineon%20PDFs/KT,KTY.pdf) -to-92Mini transistor -0 -2 -2 -Package_TO_SOT_THT -TO-92S -TO-92S package, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf) -to-92S transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92S-2 -TO-92S package, 2-pin, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf) -to-92S transistor -0 -2 -2 -Package_TO_SOT_THT -TO-92S_Wide -TO-92S_Wide package, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf) -TO-92S_Wide transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_HandSolder -TO-92 leads molded, narrow, drill 0.75mm, handsoldering variant with enlarged pads (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Horizontal1 -TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Horizontal2 -TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Inline -TO-92 leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Inline_Horizontal1 -TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Inline_Horizontal2 -TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Inline_W4.0mm_Horizontal_FlatSideDown -TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Inline_W4.0mm_Horizontal_FlatSideUp -TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Inline_Wide -TO-92 leads in-line, wide, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_W4.0mm_StaggerEven_Horizontal_FlatSideDown -TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_W4.0mm_StaggerEven_Horizontal_FlatSideUp -TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-92_Wide -TO-92 leads molded, wide, drill 0.75mm (see NXP sot054_po.pdf) -to-92 sc-43 sc-43a sot54 PA33 transistor -0 -3 -3 -Package_TO_SOT_THT -TO-99-6 -TO-99-6 -TO-99-6 -0 -6 -6 -Package_TO_SOT_THT -TO-99-6_Window -TO-99-6_Window, Window -TO-99-6_Window Window -0 -6 -6 -Package_TO_SOT_THT -TO-99-8 -TO-99-8 -TO-99-8 -0 -8 -8 -Package_TO_SOT_THT -TO-99-8_Window -TO-99-8_Window, Window -TO-99-8_Window Window -0 -8 -8 -Package_TO_SOT_THT -TO-100-10 -TO-100-10 -TO-100-10 -0 -10 -10 -Package_TO_SOT_THT -TO-100-10_Window -TO-100-10_Window, Window -TO-100-10_Window Window -0 -10 -10 -Package_TO_SOT_THT -TO-126-2_Horizontal_TabDown -TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf -TO-126-2 Horizontal RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-126-2_Horizontal_TabUp -TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf -TO-126-2 Horizontal RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-126-2_Vertical -TO-126-2, Vertical, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf -TO-126-2 Vertical RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-126-3_Horizontal_TabDown -TO-126-3, Horizontal, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf -TO-126-3 Horizontal RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-126-3_Horizontal_TabUp -TO-126-3, Horizontal, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf -TO-126-3 Horizontal RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-126-3_Vertical -TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf -TO-126-3 Vertical RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-218-2_Horizontal_TabDown -TO-218-2, Horizontal, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf -TO-218-2 Horizontal RM 10.95mm SOT-93 -0 -2 -2 -Package_TO_SOT_THT -TO-218-2_Horizontal_TabUp -TO-218-2, Horizontal, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf -TO-218-2 Horizontal RM 10.95mm SOT-93 -0 -2 -2 -Package_TO_SOT_THT -TO-218-2_Vertical -TO-218-2, Vertical, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf -TO-218-2 Vertical RM 10.95mm SOT-93 -0 -2 -2 -Package_TO_SOT_THT -TO-218-3_Horizontal_TabDown -TO-218-3, Horizontal, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf -TO-218-3 Horizontal RM 5.475mm SOT-93 -0 -3 -3 -Package_TO_SOT_THT -TO-218-3_Horizontal_TabUp -TO-218-3, Horizontal, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf -TO-218-3 Horizontal RM 5.475mm SOT-93 -0 -3 -3 -Package_TO_SOT_THT -TO-218-3_Vertical -TO-218-3, Vertical, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf -TO-218-3 Vertical RM 5.475mm SOT-93 -0 -3 -3 -Package_TO_SOT_THT -TO-220-2_Horizontal_TabDown -TO-220-2, Horizontal, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF -TO-220-2 Horizontal RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-220-2_Horizontal_TabUp -TO-220-2, Horizontal, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF -TO-220-2 Horizontal RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-220-2_Vertical -TO-220-2, Vertical, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF -TO-220-2 Vertical RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-220-3_Horizontal_TabDown -TO-220-3, Horizontal, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf -TO-220-3 Horizontal RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-220-3_Horizontal_TabUp -TO-220-3, Horizontal, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf -TO-220-3 Horizontal RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-220-3_Vertical -TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf -TO-220-3 Vertical RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-220-4_Horizontal_TabDown -TO-220-4, Horizontal, RM 2.54mm -TO-220-4 Horizontal RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-220-4_Horizontal_TabUp -TO-220-4, Horizontal, RM 2.54mm -TO-220-4 Horizontal RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-220-4_P5.08x2.54mm_StaggerEven_Lead3.8mm_Vertical -TO-220-4, Vertical, RM 2.54mm, staggered type-2 -TO-220-4 Vertical RM 2.54mm staggered type-2 -0 -4 -4 -Package_TO_SOT_THT -TO-220-4_P5.08x2.54mm_StaggerEven_Lead5.84mm_TabDown -TO-220-4, Horizontal, RM 2.54mm, staggered type-2 -TO-220-4 Horizontal RM 2.54mm staggered type-2 -0 -4 -4 -Package_TO_SOT_THT -TO-220-4_P5.08x2.54mm_StaggerOdd_Lead3.8mm_Vertical -TO-220-4, Vertical, RM 2.54mm, staggered type-1 -TO-220-4 Vertical RM 2.54mm staggered type-1 -0 -4 -4 -Package_TO_SOT_THT -TO-220-4_P5.08x2.54mm_StaggerOdd_Lead5.84mm_TabDown -TO-220-4, Horizontal, RM 2.54mm, staggered type-1 -TO-220-4 Horizontal RM 2.54mm staggered type-1 -0 -4 -4 -Package_TO_SOT_THT -TO-220-4_Vertical -TO-220-4, Vertical, RM 2.54mm -TO-220-4 Vertical RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-220-5_Horizontal_TabDown -TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf -TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 -0 -5 -5 -Package_TO_SOT_THT -TO-220-5_Horizontal_TabUp -TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf -TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 -0 -5 -5 -Package_TO_SOT_THT -TO-220-5_P3.4x3.7mm_StaggerEven_Lead3.8mm_Vertical -TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-2, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf -TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 staggered type-2 -0 -5 -5 -Package_TO_SOT_THT -TO-220-5_P3.4x3.7mm_StaggerOdd_Lead3.8mm_Vertical -TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-1, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf -TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 staggered type-1 -0 -5 -5 -Package_TO_SOT_THT -TO-220-5_P3.4x3.8mm_StaggerEven_Lead7.13mm_TabDown -TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-2, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf -TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered type-2 -0 -5 -5 -Package_TO_SOT_THT -TO-220-5_P3.4x3.8mm_StaggerOdd_Lead7.13mm_TabDown -TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-1, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf -TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered type-1 -0 -5 -5 -Package_TO_SOT_THT -TO-220-5_Vertical -TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf -TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 -0 -5 -5 -Package_TO_SOT_THT -TO-220-7_P2.54x3.7mm_StaggerEven_Lead3.8mm_Vertical -TO-220-7, Vertical, RM 1.27mm, Multiwatt-7, staggered type-2 -TO-220-7 Vertical RM 1.27mm Multiwatt-7 staggered type-2 -0 -7 -7 -Package_TO_SOT_THT -TO-220-7_P2.54x3.7mm_StaggerOdd_Lead3.8mm_Vertical -TO-220-7, Vertical, RM 1.27mm, Multiwatt-7, staggered type-1 -TO-220-7 Vertical RM 1.27mm Multiwatt-7 staggered type-1 -0 -7 -7 -Package_TO_SOT_THT -TO-220-7_P2.54x3.8mm_StaggerEven_Lead5.85mm_TabDown -TO-220-7, Horizontal, RM 1.27mm, Multiwatt-7, staggered type-2 -TO-220-7 Horizontal RM 1.27mm Multiwatt-7 staggered type-2 -0 -7 -7 -Package_TO_SOT_THT -TO-220-7_P2.54x3.8mm_StaggerOdd_Lead5.85mm_TabDown -TO-220-7, Horizontal, RM 1.27mm, Multiwatt-7, staggered type-1 -TO-220-7 Horizontal RM 1.27mm Multiwatt-7 staggered type-1 -0 -7 -7 -Package_TO_SOT_THT -TO-220-8_Vertical -TO-220-8 (Multiwatt8), Vertical, 2.54mm Pitch (http://www.st.com/resource/en/datasheet/tda7264.pdf) -TO-220-9 Vertical 2.54mm Pitch Multiwatt 8 -0 -8 -8 -Package_TO_SOT_THT -TO-220-9_P1.94x3.7mm_StaggerEven_Lead3.8mm_Vertical -TO-220-9, Vertical, RM 0.97mm, Multiwatt-9, staggered type-2 -TO-220-9 Vertical RM 0.97mm Multiwatt-9 staggered type-2 -0 -9 -9 -Package_TO_SOT_THT -TO-220-9_P1.94x3.7mm_StaggerOdd_Lead3.8mm_Vertical -TO-220-9, Vertical, RM 0.97mm, Multiwatt-9, staggered type-1 -TO-220-9 Vertical RM 0.97mm Multiwatt-9 staggered type-1 -0 -9 -9 -Package_TO_SOT_THT -TO-220-9_P1.94x3.8mm_StaggerEven_Lead5.85mm_TabDown -TO-220-9, Horizontal, RM 0.97mm, Multiwatt-9, staggered type-2 -TO-220-9 Horizontal RM 0.97mm Multiwatt-9 staggered type-2 -0 -9 -9 -Package_TO_SOT_THT -TO-220-9_P1.94x3.8mm_StaggerOdd_Lead5.85mm_TabDown -TO-220-9, Horizontal, RM 0.97mm, Multiwatt-9, staggered type-1 -TO-220-9 Horizontal RM 0.97mm Multiwatt-9 staggered type-1 -0 -9 -9 -Package_TO_SOT_THT -TO-220-11_P3.4x2.54mm_StaggerEven_Lead5.84mm_TabDown -TO-220-11, Horizontal, RM 1.7mm, staggered type-2, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf -TO-220-11 Horizontal RM 1.7mm staggered type-2 -0 -11 -11 -Package_TO_SOT_THT -TO-220-11_P3.4x2.54mm_StaggerOdd_Lead5.84mm_TabDown -TO-220-11, Horizontal, RM 1.7mm, staggered type-1, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf -TO-220-11 Horizontal RM 1.7mm staggered type-1 -0 -11 -11 -Package_TO_SOT_THT -TO-220-11_P3.4x5.08mm_StaggerEven_Lead4.58mm_Vertical -TO-220-11, Vertical, RM 1.7mm, staggered type-2, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf -TO-220-11 Vertical RM 1.7mm staggered type-2 -0 -11 -11 -Package_TO_SOT_THT -TO-220-11_P3.4x5.08mm_StaggerOdd_Lead4.85mm_Vertical -TO-220-11, Vertical, RM 1.7mm, staggered type-1, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf -TO-220-11 Vertical RM 1.7mm staggered type-1 -0 -11 -11 -Package_TO_SOT_THT -TO-220-11_P3.4x5.08mm_StaggerOdd_Lead8.45mm_TabDown -TO-220-11, Horizontal, RM 1.7mm, staggered type-1, see http://www.ti.com/lit/ds/symlink/lmd18200.pdf -TO-220-11 Horizontal RM 1.7mm staggered type-1 -0 -11 -11 -Package_TO_SOT_THT -TO-220-15_P2.54x2.54mm_StaggerEven_Lead4.58mm_Vertical -TO-220-15, Vertical, RM 1.27mm, staggered type-2, see http://www.st.com/resource/en/datasheet/l298.pdf -TO-220-15 Vertical RM 1.27mm staggered type-2 -0 -15 -15 -Package_TO_SOT_THT -TO-220-15_P2.54x2.54mm_StaggerEven_Lead5.84mm_TabDown -TO-220-15, Horizontal, RM 1.27mm, staggered type-2, see http://www.st.com/resource/en/datasheet/l298.pdf -TO-220-15 Horizontal RM 1.27mm staggered type-2 -0 -15 -15 -Package_TO_SOT_THT -TO-220-15_P2.54x2.54mm_StaggerOdd_Lead4.58mm_Vertical -TO-220-15, Vertical, RM 1.27mm, staggered type-1, see http://www.st.com/resource/en/datasheet/l298.pdf -TO-220-15 Vertical RM 1.27mm staggered type-1 -0 -15 -15 -Package_TO_SOT_THT -TO-220-15_P2.54x2.54mm_StaggerOdd_Lead5.84mm_TabDown -TO-220-15, Horizontal, RM 1.27mm, staggered type-1, see http://www.st.com/resource/en/datasheet/l298.pdf -TO-220-15 Horizontal RM 1.27mm staggered type-1 -0 -15 -15 -Package_TO_SOT_THT -TO-220F-2_Horizontal_TabDown -TO-220F-2, Horizontal, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf -TO-220F-2 Horizontal RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-220F-2_Horizontal_TabUp -TO-220F-2, Horizontal, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf -TO-220F-2 Horizontal RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-220F-2_Vertical -TO-220F-2, Vertical, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf -TO-220F-2 Vertical RM 5.08mm -0 -2 -2 -Package_TO_SOT_THT -TO-220F-3_Horizontal_TabDown -TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf -TO-220F-3 Horizontal RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-220F-3_Horizontal_TabUp -TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf -TO-220F-3 Horizontal RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-220F-3_Vertical -TO-220F-3, Vertical, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf -TO-220F-3 Vertical RM 2.54mm -0 -3 -3 -Package_TO_SOT_THT -TO-220F-4_Horizontal_TabDown -TO-220F-4, Horizontal, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Horizontal RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-220F-4_Horizontal_TabUp -TO-220F-4, Horizontal, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Horizontal RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-220F-4_P5.08x2.05mm_StaggerEven_Lead1.85mm_Vertical -TO-220F-4, Vertical, RM 2.54mm, staggered type-2, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Vertical RM 2.54mm staggered type-2 -0 -4 -4 -Package_TO_SOT_THT -TO-220F-4_P5.08x2.05mm_StaggerOdd_Lead1.85mm_Vertical -TO-220F-4, Vertical, RM 2.54mm, staggered type-1, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Vertical RM 2.54mm staggered type-1 -0 -4 -4 -Package_TO_SOT_THT -TO-220F-4_P5.08x3.7mm_StaggerEven_Lead3.5mm_Vertical -TO-220F-4, Vertical, RM 2.54mm, staggered type-2, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Vertical RM 2.54mm staggered type-2 -0 -4 -4 -Package_TO_SOT_THT -TO-220F-4_P5.08x3.7mm_StaggerOdd_Lead3.5mm_Vertical -TO-220F-4, Vertical, RM 2.54mm, staggered type-1, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Vertical RM 2.54mm staggered type-1 -0 -4 -4 -Package_TO_SOT_THT -TO-220F-4_Vertical -TO-220F-4, Vertical, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf -TO-220F-4 Vertical RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-220F-5_Horizontal_TabDown -TO-220F-5, Horizontal, RM 1.7mm, PentawattF-, MultiwattF-5 -TO-220F-5 Horizontal RM 1.7mm PentawattF- MultiwattF-5 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-5_Horizontal_TabUp -TO-220F-5, Horizontal, RM 1.7mm, PentawattF-, MultiwattF-5 -TO-220F-5 Horizontal RM 1.7mm PentawattF- MultiwattF-5 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-5_P3.4x2.06mm_StaggerEven_Lead1.86mm_Vertical -TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-2 -TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-2 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-5_P3.4x2.06mm_StaggerOdd_Lead1.86mm_Vertical -TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-1 -TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-1 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-5_P3.4x3.7mm_StaggerEven_Lead3.5mm_Vertical -TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-2 -TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-2 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-5_P3.4x3.7mm_StaggerOdd_Lead3.5mm_Vertical -TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-1 -TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-1 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-5_Vertical -TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5 -TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 -0 -5 -5 -Package_TO_SOT_THT -TO-220F-7_P2.54x3.7mm_StaggerEven_Lead3.5mm_Vertical -TO-220F-7, Vertical, RM 1.27mm, staggered type-2 -TO-220F-7 Vertical RM 1.27mm staggered type-2 -0 -7 -7 -Package_TO_SOT_THT -TO-220F-7_P2.54x3.7mm_StaggerOdd_Lead3.5mm_Vertical -TO-220F-7, Vertical, RM 1.27mm, staggered type-1 -TO-220F-7 Vertical RM 1.27mm staggered type-1 -0 -7 -7 -Package_TO_SOT_THT -TO-220F-9_P1.8x3.7mm_StaggerEven_Lead3.5mm_Vertical -TO-220F-9, Vertical, RM 0.9mm, staggered type-2 -TO-220F-9 Vertical RM 0.9mm staggered type-2 -0 -9 -9 -Package_TO_SOT_THT -TO-220F-9_P1.8x3.7mm_StaggerOdd_Lead3.5mm_Vertical -TO-220F-9, Vertical, RM 0.9mm, staggered type-1 -TO-220F-9 Vertical RM 0.9mm staggered type-1 -0 -9 -9 -Package_TO_SOT_THT -TO-220F-11_P3.4x5.08mm_StaggerEven_Lead5.08mm_Vertical -TO-220F-11, Vertical, RM 1.7mm, MultiwattF-11, staggered type-2, see http://www.ti.com/lit/ds/symlink/lm3886.pdf -TO-220F-11 Vertical RM 1.7mm MultiwattF-11 staggered type-2 -0 -11 -11 -Package_TO_SOT_THT -TO-220F-11_P3.4x5.08mm_StaggerOdd_Lead5.08mm_Vertical -TO-220F-11, Vertical, RM 1.7mm, MultiwattF-11, staggered type-1, see http://www.ti.com/lit/ds/symlink/lm3886.pdf -TO-220F-11 Vertical RM 1.7mm MultiwattF-11 staggered type-1 -0 -11 -11 -Package_TO_SOT_THT -TO-220F-15_P2.54x5.08mm_StaggerEven_Lead5.08mm_Vertical -TO-220F-15, Vertical, RM 1.27mm, MultiwattF-15, staggered type-2 -TO-220F-15 Vertical RM 1.27mm MultiwattF-15 staggered type-2 -0 -15 -15 -Package_TO_SOT_THT -TO-220F-15_P2.54x5.08mm_StaggerOdd_Lead5.08mm_Vertical -TO-220F-15, Vertical, RM 1.27mm, MultiwattF-15, staggered type-1 -TO-220F-15 Vertical RM 1.27mm MultiwattF-15 staggered type-1 -0 -15 -15 -Package_TO_SOT_THT -TO-247-2_Horizontal_TabDown -TO-247-2, Horizontal, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-2 Horizontal RM 10.9mm -0 -2 -2 -Package_TO_SOT_THT -TO-247-2_Horizontal_TabUp -TO-247-2, Horizontal, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-2 Horizontal RM 10.9mm -0 -2 -2 -Package_TO_SOT_THT -TO-247-2_Vertical -TO-247-2, Vertical, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-2 Vertical RM 10.9mm -0 -2 -2 -Package_TO_SOT_THT -TO-247-3_Horizontal_TabDown -TO-247-3, Horizontal, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-247-3_Horizontal_TabUp -TO-247-3, Horizontal, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-247-3_Vertical -TO-247-3, Vertical, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-3 Vertical RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-247-4_Horizontal_TabDown -TO-247-4, Horizontal, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-4 Horizontal RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-247-4_Horizontal_TabUp -TO-247-4, Horizontal, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-4 Horizontal RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-247-4_Vertical -TO-247-4, Vertical, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html -TO-247-4 Vertical RM 2.54mm -0 -4 -4 -Package_TO_SOT_THT -TO-247-5_Horizontal_TabDown -TO-247-5, Horizontal, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf -TO-247-5 Horizontal RM 2.54mm -0 -5 -5 -Package_TO_SOT_THT -TO-247-5_Horizontal_TabUp -TO-247-5, Horizontal, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf -TO-247-5 Horizontal RM 2.54mm -0 -5 -5 -Package_TO_SOT_THT -TO-247-5_Vertical -TO-247-5, Vertical, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf -TO-247-5 Vertical RM 2.54mm -0 -5 -5 -Package_TO_SOT_THT -TO-251-2-1EP_Horizontal_TabDown -TO-251-2, Horizontal, RM 4.58mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf -TO-251-2 Horizontal RM 4.58mm IPAK -0 -3 -3 -Package_TO_SOT_THT -TO-251-2_Vertical -TO-251-2, Vertical, RM 4.58mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf -TO-251-2 Vertical RM 4.58mm IPAK -0 -2 -2 -Package_TO_SOT_THT -TO-251-3-1EP_Horizontal_TabDown -TO-251-3, Horizontal, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf -TO-251-3 Horizontal RM 2.29mm IPAK -0 -4 -4 -Package_TO_SOT_THT -TO-251-3_Vertical -TO-251-3, Vertical, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf -TO-251-3 Vertical RM 2.29mm IPAK -0 -3 -3 -Package_TO_SOT_THT -TO-262-3-1EP_Horizontal_TabDown -TO-262-3, Horizontal, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF -TO-262-3 Horizontal RM 2.54mm IIPAK I2PAK -0 -4 -4 -Package_TO_SOT_THT -TO-262-3_Vertical -TO-262-3, Vertical, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF -TO-262-3 Vertical RM 2.54mm IIPAK I2PAK -0 -3 -3 -Package_TO_SOT_THT -TO-262-5-1EP_Horizontal_TabDown -TO-262-5, Horizontal, RM 1.7mm, IIPAK, I2PAK, see http://pdf.datasheetcatalog.com/datasheet/irf/iris4011.pdf -TO-262-5 Horizontal RM 1.7mm IIPAK I2PAK -0 -6 -6 -Package_TO_SOT_THT -TO-262-5_Vertical -TO-262-5, Vertical, RM 1.7mm, IIPAK, I2PAK, see http://pdf.datasheetcatalog.com/datasheet/irf/iris4011.pdf -TO-262-5 Vertical RM 1.7mm IIPAK I2PAK -0 -5 -5 -Package_TO_SOT_THT -TO-264-2_Horizontal_TabDown -TO-264-2, Horizontal, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf -TO-264-2 Horizontal RM 10.9mm -0 -2 -2 -Package_TO_SOT_THT -TO-264-2_Horizontal_TabUp -TO-264-2, Horizontal, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf -TO-264-2 Horizontal RM 10.9mm -0 -2 -2 -Package_TO_SOT_THT -TO-264-2_Vertical -TO-264-2, Vertical, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf -TO-264-2 Vertical RM 10.9mm -0 -2 -2 -Package_TO_SOT_THT -TO-264-3_Horizontal_TabDown -TO-264-3, Horizontal, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf -TO-264-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-264-3_Horizontal_TabUp -TO-264-3, Horizontal, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf -TO-264-3 Horizontal RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-264-3_Vertical -TO-264-3, Vertical, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf -TO-264-3 Vertical RM 5.45mm -0 -3 -3 -Package_TO_SOT_THT -TO-264-5_Horizontal_TabDown -TO-264-5, Horizontal, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF -TO-264-5 Horizontal RM 3.81mm -0 -5 -5 -Package_TO_SOT_THT -TO-264-5_Horizontal_TabUp -TO-264-5, Horizontal, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF -TO-264-5 Horizontal RM 3.81mm -0 -5 -5 -Package_TO_SOT_THT -TO-264-5_Vertical -TO-264-5, Vertical, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF -TO-264-5 Vertical RM 3.81mm -0 -5 -5 -Potentiometer_SMD -Potentiometer_ACP_CA6-VSMD_Vertical -Potentiometer, vertical, ACP CA6-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf -Potentiometer vertical ACP CA6-VSMD -0 -3 -3 -Potentiometer_SMD -Potentiometer_ACP_CA6-VSMD_Vertical_Hole -Potentiometer, vertical, shaft hole, ACP CA6-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf -Potentiometer vertical hole ACP CA6-VSMD -0 -3 -3 -Potentiometer_SMD -Potentiometer_ACP_CA9-VSMD_Vertical -Potentiometer, vertical, ACP CA9-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer vertical ACP CA9-VSMD -0 -3 -3 -Potentiometer_SMD -Potentiometer_ACP_CA9-VSMD_Vertical_Hole -Potentiometer, vertical, shaft hole, ACP CA9-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer vertical hole ACP CA9-VSMD -0 -3 -3 -Potentiometer_SMD -Potentiometer_ACP_CA14-VSMD_Vertical -Potentiometer, vertical, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer vertical ACP CA14-VSMD -0 -3 -3 -Potentiometer_SMD -Potentiometer_ACP_CA14-VSMD_Vertical_Hole -Potentiometer, vertical, shaft hole, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer vertical hole ACP CA14-VSMD -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3214G_Horizontal -Potentiometer, horizontal, Bourns 3214G, https://www.bourns.com/docs/Product-Datasheets/3214.pdf -Potentiometer horizontal Bourns 3214G -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3214J_Horizontal -Potentiometer, horizontal, Bourns 3214J, https://www.bourns.com/docs/Product-Datasheets/3214.pdf -Potentiometer horizontal Bourns 3214J -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3214W_Vertical -Potentiometer, vertical, Bourns 3214W, https://www.bourns.com/docs/Product-Datasheets/3214.pdf -Potentiometer vertical Bourns 3214W -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3214X_Vertical -Potentiometer, vertical, Bourns 3214X, https://www.bourns.com/docs/Product-Datasheets/3214.pdf -Potentiometer vertical Bourns 3214X -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3224G_Horizontal -Potentiometer, horizontal, Bourns 3224G, https://www.bourns.com/docs/Product-Datasheets/3224.pdf -Potentiometer horizontal Bourns 3224G -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3224J_Horizontal -Potentiometer, horizontal, Bourns 3224J, https://www.bourns.com/docs/Product-Datasheets/3224.pdf -Potentiometer horizontal Bourns 3224J -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3224W_Vertical -Potentiometer, vertical, Bourns 3224W, https://www.bourns.com/docs/Product-Datasheets/3224.pdf -Potentiometer vertical Bourns 3224W -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3224X_Vertical -Potentiometer, vertical, Bourns 3224X, https://www.bourns.com/docs/Product-Datasheets/3224.pdf -Potentiometer vertical Bourns 3224X -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3269P_Horizontal -Potentiometer, horizontal, Bourns 3269P, https://www.bourns.com/docs/Product-Datasheets/3269.pdf -Potentiometer horizontal Bourns 3269P -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3269W_Vertical -Potentiometer, vertical, Bourns 3269W, https://www.bourns.com/docs/Product-Datasheets/3269.pdf -Potentiometer vertical Bourns 3269W -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3269X_Horizontal -Potentiometer, horizontal, Bourns 3269X, https://www.bourns.com/docs/Product-Datasheets/3269.pdf -Potentiometer horizontal Bourns 3269X -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3314G_Vertical -Potentiometer, vertical, Bourns 3314G, http://www.bourns.com/docs/Product-Datasheets/3314.pdf -Potentiometer vertical Bourns 3314G -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3314J_Vertical -Potentiometer, vertical, Bourns 3314J, http://www.bourns.com/docs/Product-Datasheets/3314.pdf -Potentiometer vertical Bourns 3314J -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3314R-1_Vertical_Hole -Potentiometer, vertical, shaft hole, Bourns 3314R-1, http://www.bourns.com/docs/Product-Datasheets/3314.pdf -Potentiometer vertical hole Bourns 3314R-1 -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3314R-GM5_Vertical -Potentiometer, vertical, Bourns 3314R-GM5, http://www.bourns.com/docs/Product-Datasheets/3314.pdf -Potentiometer vertical Bourns 3314R-GM5 -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_3314S_Horizontal -Potentiometer, horizontal, Bourns 3314S, http://www.bourns.com/docs/Product-Datasheets/3314.pdf -Potentiometer horizontal Bourns 3314S -0 -3 -3 -Potentiometer_SMD -Potentiometer_Bourns_PRS11S_Vertical -Potentiometer, vertical, Bourns PRS11S, http://www.bourns.com/docs/Product-Datasheets/PRS11S.pdf -Potentiometer vertical Bourns PRS11S -0 -5 -5 -Potentiometer_SMD -Potentiometer_Bourns_TC33X_Vertical -Potentiometer, Bourns, TC33X, Vertical, https://www.bourns.com/pdfs/TC33.pdf -Potentiometer Bourns TC33X Vertical -0 -3 -3 -Potentiometer_SMD -Potentiometer_Vishay_TS53YJ_Vertical -Potentiometer, vertical, Vishay TS53YJ, https://www.vishay.com/docs/51008/ts53.pdf -Potentiometer vertical Vishay TS53YJ -0 -3 -3 -Potentiometer_SMD -Potentiometer_Vishay_TS53YL_Vertical -Potentiometer, vertical, Vishay TS53YL, https://www.vishay.com/docs/51008/ts53.pdf -Potentiometer vertical Vishay TS53YL -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA6-H2,5_Horizontal -Potentiometer, horizontal, ACP CA6-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf -Potentiometer horizontal ACP CA6-H2,5 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA9-H2,5_Horizontal -Potentiometer, horizontal, ACP CA9-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer horizontal ACP CA9-H2,5 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA9-H3,8_Horizontal -Potentiometer, horizontal, ACP CA9-H3,8, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer horizontal ACP CA9-H3,8 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA9-H5_Horizontal -Potentiometer, horizontal, ACP CA9-H5, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer horizontal ACP CA9-H5 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA9-V10_Vertical -Potentiometer, vertical, ACP CA9-V10, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer vertical ACP CA9-V10 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA9-V10_Vertical_Hole -Potentiometer, vertical, shaft hole, ACP CA9-V10, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf -Potentiometer vertical hole ACP CA9-V10 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA14-H2,5_Horizontal -Potentiometer, horizontal, ACP CA14-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer horizontal ACP CA14-H2,5 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA14-H4_Horizontal -Potentiometer, horizontal, ACP CA14-H4, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer horizontal ACP CA14-H4 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA14-H5_Horizontal -Potentiometer, horizontal, ACP CA14-H5, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer horizontal ACP CA14-H5 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA14V-15_Vertical -Potentiometer, vertical, ACP CA14V-15, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer vertical ACP CA14V-15 -0 -3 -3 -Potentiometer_THT -Potentiometer_ACP_CA14V-15_Vertical_Hole -Potentiometer, vertical, shaft hole, ACP CA14V-15, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf -Potentiometer vertical hole ACP CA14V-15 -0 -3 -3 -Potentiometer_THT -Potentiometer_Alpha_RD901F-40-00D_Single_Vertical -Potentiometer, vertical, 9mm, single, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 -potentiometer vertical 9mm single -0 -5 -3 -Potentiometer_THT -Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles -Potentiometer, vertical, 9mm, single, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 -potentiometer vertical 9mm single -0 -5 -3 -Potentiometer_THT -Potentiometer_Alpha_RD902F-40-00D_Dual_Vertical -Potentiometer, vertical, 9mm, dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 -potentiometer vertical 9mm dual -0 -8 -6 -Potentiometer_THT -Potentiometer_Alpha_RD902F-40-00D_Dual_Vertical_CircularHoles -Potentiometer, vertical, 9mm, dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 -potentiometer vertical 9mm dual -0 -8 -6 -Potentiometer_THT -Potentiometer_Alps_RK09K_Single_Horizontal -Potentiometer, horizontal, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html -Potentiometer horizontal Alps RK09K Single -0 -5 -3 -Potentiometer_THT -Potentiometer_Alps_RK09K_Single_Vertical -Potentiometer, vertical, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html -Potentiometer vertical Alps RK09K Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Alps_RK09L_Double_Horizontal -Potentiometer, horizontal, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html -Potentiometer horizontal Alps RK09L Double -0 -8 -6 -Potentiometer_THT -Potentiometer_Alps_RK09L_Double_Vertical -Potentiometer, vertical, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html -Potentiometer vertical Alps RK09L Double -0 -6 -6 -Potentiometer_THT -Potentiometer_Alps_RK09L_Single_Horizontal -Potentiometer, horizontal, Alps RK09L Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html -Potentiometer horizontal Alps RK09L Single -0 -5 -3 -Potentiometer_THT -Potentiometer_Alps_RK09L_Single_Vertical -Potentiometer, vertical, Alps RK09L Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html -Potentiometer vertical Alps RK09L Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Alps_RK09Y11_Single_Horizontal -Potentiometer, horizontal, Alps RK09Y11 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09Y11/RK09Y11_list.html -Potentiometer horizontal Alps RK09Y11 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Alps_RK097_Dual_Horizontal -Potentiometer, horizontal, Alps RK097 Dual, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK097/RK097_list.html -Potentiometer horizontal Alps RK097 Dual -0 -6 -6 -Potentiometer_THT -Potentiometer_Alps_RK097_Single_Horizontal -Potentiometer, horizontal, Alps RK097 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK097/RK097_list.html -Potentiometer horizontal Alps RK097 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Alps_RK163_Dual_Horizontal -Potentiometer, horizontal, Alps RK163 Dual, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK16/RK16_list.html -Potentiometer horizontal Alps RK163 Dual -0 -6 -6 -Potentiometer_THT -Potentiometer_Alps_RK163_Single_Horizontal -Potentiometer, horizontal, Alps RK163 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK16/RK16_list.html -Potentiometer horizontal Alps RK163 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3005_Horizontal -Potentiometer, horizontal, Bourns 3005, http://www.bourns.com/docs/Product-Datasheets/3005.pdf -Potentiometer horizontal Bourns 3005 -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3006P_Horizontal -Potentiometer, horizontal, Bourns 3006P, https://www.bourns.com/docs/Product-Datasheets/3006.pdf -Potentiometer horizontal Bourns 3006P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3006W_Horizontal -Potentiometer, horizontal, Bourns 3006W, https://www.bourns.com/docs/Product-Datasheets/3006.pdf -Potentiometer horizontal Bourns 3006W -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3006Y_Horizontal -Potentiometer, horizontal, Bourns 3006Y, https://www.bourns.com/docs/Product-Datasheets/3006.pdf -Potentiometer horizontal Bourns 3006Y -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3009P_Horizontal -Potentiometer, horizontal, Bourns 3009P, http://www.bourns.com/docs/Product-Datasheets/3009.pdf -Potentiometer horizontal Bourns 3009P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3009Y_Horizontal -Potentiometer, horizontal, Bourns 3009Y, http://www.bourns.com/docs/Product-Datasheets/3009.pdf -Potentiometer horizontal Bourns 3009Y -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3266P_Horizontal -Potentiometer, horizontal, Bourns 3266P, https://www.bourns.com/docs/Product-Datasheets/3266.pdf -Potentiometer horizontal Bourns 3266P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3266W_Vertical -Potentiometer, vertical, Bourns 3266W, https://www.bourns.com/docs/Product-Datasheets/3266.pdf -Potentiometer vertical Bourns 3266W -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3266X_Horizontal -Potentiometer, horizontal, Bourns 3266X, https://www.bourns.com/docs/Product-Datasheets/3266.pdf -Potentiometer horizontal Bourns 3266X -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3266Y_Vertical -Potentiometer, vertical, Bourns 3266Y, https://www.bourns.com/docs/Product-Datasheets/3266.pdf -Potentiometer vertical Bourns 3266Y -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3266Z_Horizontal -Potentiometer, horizontal, Bourns 3266Z, https://www.bourns.com/docs/Product-Datasheets/3266.pdf -Potentiometer horizontal Bourns 3266Z -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3296P_Horizontal -Potentiometer, horizontal, Bourns 3296P, https://www.bourns.com/pdfs/3296.pdf -Potentiometer horizontal Bourns 3296P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3296W_Vertical -Potentiometer, vertical, Bourns 3296W, https://www.bourns.com/pdfs/3296.pdf -Potentiometer vertical Bourns 3296W -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3296X_Horizontal -Potentiometer, horizontal, Bourns 3296X, https://www.bourns.com/pdfs/3296.pdf -Potentiometer horizontal Bourns 3296X -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3296Y_Vertical -Potentiometer, vertical, Bourns 3296Y, https://www.bourns.com/pdfs/3296.pdf -Potentiometer vertical Bourns 3296Y -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3296Z_Horizontal -Potentiometer, horizontal, Bourns 3296Z, https://www.bourns.com/pdfs/3296.pdf -Potentiometer horizontal Bourns 3296Z -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3299P_Horizontal -Potentiometer, horizontal, Bourns 3299P, https://www.bourns.com/pdfs/3299.pdf -Potentiometer horizontal Bourns 3299P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3299W_Vertical -Potentiometer, vertical, Bourns 3299W, https://www.bourns.com/pdfs/3299.pdf -Potentiometer vertical Bourns 3299W -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3299X_Horizontal -Potentiometer, horizontal, Bourns 3299X, https://www.bourns.com/pdfs/3299.pdf -Potentiometer horizontal Bourns 3299X -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3299Y_Vertical -Potentiometer, vertical, Bourns 3299Y, https://www.bourns.com/pdfs/3299.pdf -Potentiometer vertical Bourns 3299Y -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3299Z_Horizontal -Potentiometer, horizontal, Bourns 3299Z, https://www.bourns.com/pdfs/3299.pdf -Potentiometer horizontal Bourns 3299Z -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3339H_Vertical -Potentiometer, vertical, Bourns 3339H, http://www.bourns.com/docs/Product-Datasheets/3339.pdf -Potentiometer vertical Bourns 3339H -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3339P_Vertical -Potentiometer, vertical, Bourns 3339P, http://www.bourns.com/docs/Product-Datasheets/3339.pdf -Potentiometer vertical Bourns 3339P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3339P_Vertical_HandSoldering -Potentiometer, vertical, Bourns 3339P, hand-soldering, http://www.bourns.com/docs/Product-Datasheets/3339.pdf -Potentiometer vertical Bourns 3339P hand-soldering -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3339S_Horizontal -Potentiometer, horizontal, Bourns 3339S, http://www.bourns.com/docs/Product-Datasheets/3339.pdf -Potentiometer horizontal Bourns 3339S -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3339W_Horizontal -Potentiometer, horizontal, Bourns 3339W, http://www.bourns.com/docs/Product-Datasheets/3339.pdf -Potentiometer horizontal Bourns 3339W -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3386C_Horizontal -Potentiometer, horizontal, Bourns 3386C, https://www.bourns.com/pdfs/3386.pdf -Potentiometer horizontal Bourns 3386C -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3386F_Vertical -Potentiometer, vertical, Bourns 3386F, https://www.bourns.com/pdfs/3386.pdf -Potentiometer vertical Bourns 3386F -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3386P_Vertical -Potentiometer, vertical, Bourns 3386P, https://www.bourns.com/pdfs/3386.pdf -Potentiometer vertical Bourns 3386P -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_3386X_Horizontal -Potentiometer, horizontal, Bourns 3386X, https://www.bourns.com/pdfs/3386.pdf -Potentiometer horizontal Bourns 3386X -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_PTA1543_Single_Slide -Bourns single-gang slide potentiometer, 15.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf -Bourns single-gang slide potentiometer 15.0mm -0 -7 -4 -Potentiometer_THT -Potentiometer_Bourns_PTA2043_Single_Slide -Bourns single-gang slide potentiometer, 20.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf -Bourns single-gang slide potentiometer 20.0mm -0 -7 -4 -Potentiometer_THT -Potentiometer_Bourns_PTA3043_Single_Slide -Bourns single-gang slide potentiometer, 30.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf -Bourns single-gang slide potentiometer 30.0mm -0 -7 -4 -Potentiometer_THT -Potentiometer_Bourns_PTA4543_Single_Slide -Bourns single-gang slide potentiometer, 45.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf -Bourns single-gang slide potentiometer 45.0mm -0 -7 -4 -Potentiometer_THT -Potentiometer_Bourns_PTA6043_Single_Slide -Bourns single-gang slide potentiometer, 60.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf -Bourns single-gang slide potentiometer 60.0mm -0 -7 -4 -Potentiometer_THT -Potentiometer_Bourns_PTV09A-1_Single_Vertical -Potentiometer, vertical, Bourns PTV09A-1 Single, http://www.bourns.com/docs/Product-Datasheets/ptv09.pdf -Potentiometer vertical Bourns PTV09A-1 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Bourns_PTV09A-2_Single_Horizontal -Potentiometer, horizontal, Bourns PTV09A-2 Single, http://www.bourns.com/docs/Product-Datasheets/ptv09.pdf -Potentiometer horizontal Bourns PTV09A-2 Single -0 -5 -3 -Potentiometer_THT -Potentiometer_Omeg_PC16BU_Horizontal -Potentiometer, horizontal, Omeg PC16BU, http://www.omeg.co.uk/pc6bubrc.htm -Potentiometer horizontal Omeg PC16BU -0 -3 -3 -Potentiometer_THT -Potentiometer_Omeg_PC16BU_Vertical -Potentiometer, vertical, Omeg PC16BU, http://www.omeg.co.uk/pc6bubrc.htm -Potentiometer vertical Omeg PC16BU -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PC-16_Dual_Horizontal -Potentiometer, horizontal, Piher PC-16 Dual, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf -Potentiometer horizontal Piher PC-16 Dual -0 -6 -6 -Potentiometer_THT -Potentiometer_Piher_PC-16_Single_Horizontal -Potentiometer, horizontal, Piher PC-16 Single, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf -Potentiometer horizontal Piher PC-16 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PC-16_Single_Vertical -Potentiometer, vertical, Piher PC-16 Single, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf -Potentiometer vertical Piher PC-16 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PC-16_Triple_Horizontal -Potentiometer, horizontal, Piher PC-16 Triple, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf -Potentiometer horizontal Piher PC-16 Triple -0 -9 -9 -Potentiometer_THT -Potentiometer_Piher_PT-6-H_Horizontal -Potentiometer, horizontal, Piher PT-6-H, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf -Potentiometer horizontal Piher PT-6-H -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-6-V_Vertical -Potentiometer, vertical, Piher PT-6-V, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf -Potentiometer vertical Piher PT-6-V -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-6-V_Vertical_Hole -Potentiometer, vertical, shaft hole, Piher PT-6-V, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf -Potentiometer vertical hole Piher PT-6-V -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-10-H01_Horizontal -Potentiometer, horizontal, Piher PT-10-H01, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf -Potentiometer horizontal Piher PT-10-H01 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-10-H05_Horizontal -Potentiometer, horizontal, Piher PT-10-H05, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf -Potentiometer horizontal Piher PT-10-H05 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-10-V05_Vertical -Potentiometer, vertical, Piher PT-10-V05, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf -Potentiometer vertical Piher PT-10-V05 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-10-V10_Vertical -Potentiometer, vertical, Piher PT-10-V10, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf -Potentiometer vertical Piher PT-10-V10 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-10-V10_Vertical_Hole -Potentiometer, vertical, shaft hole, Piher PT-10-V10, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf -Potentiometer vertical hole Piher PT-10-V10 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-H01_Horizontal -Potentiometer, horizontal, Piher PT-15-H01, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer horizontal Piher PT-15-H01 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-H05_Horizontal -Potentiometer, horizontal, Piher PT-15-H05, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer horizontal Piher PT-15-H05 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-H06_Horizontal -Potentiometer, horizontal, Piher PT-15-H06, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer horizontal Piher PT-15-H06 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-H25_Horizontal -Potentiometer, horizontal, Piher PT-15-H25, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer horizontal Piher PT-15-H25 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-V02_Vertical -Potentiometer, vertical, Piher PT-15-V02, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer vertical Piher PT-15-V02 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-V02_Vertical_Hole -Potentiometer, vertical, shaft hole, Piher PT-15-V02, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer vertical hole Piher PT-15-V02 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-V15_Vertical -Potentiometer, vertical, Piher PT-15-V15, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer vertical Piher PT-15-V15 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_PT-15-V15_Vertical_Hole -Potentiometer, vertical, shaft hole, Piher PT-15-V15, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf -Potentiometer vertical hole Piher PT-15-V15 -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_T-16H_Double_Horizontal -Potentiometer, horizontal, Piher T-16H Double, http://www.piher-nacesa.com/pdf/22-T16v03.pdf -Potentiometer horizontal Piher T-16H Double -0 -6 -6 -Potentiometer_THT -Potentiometer_Piher_T-16H_Single_Horizontal -Potentiometer, horizontal, Piher T-16H Single, http://www.piher-nacesa.com/pdf/22-T16v03.pdf -Potentiometer horizontal Piher T-16H Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Piher_T-16L_Single_Vertical_Hole -Potentiometer, vertical, shaft hole, Piher T-16L Single, http://www.piher-nacesa.com/pdf/22-T16v03.pdf -Potentiometer vertical hole Piher T-16L Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Runtron_RM-063_Horizontal -Potentiometer, horizontal, Trimmer, RM-063 http://www.runtron.com/down/PDF%20Datasheet/Carbon%20Film%20Potentiometer/RM065%20RM063.pdf -Potentiometer Trimmer RM-063 -0 -3 -3 -Potentiometer_THT -Potentiometer_Runtron_RM-065_Vertical -Potentiometer, vertical, Trimmer, RM-065 http://www.runtron.com/down/PDF%20Datasheet/Carbon%20Film%20Potentiometer/RM065%20RM063.pdf -Potentiometer Trimmer RM-065 -0 -3 -3 -Potentiometer_THT -Potentiometer_TT_P0915N -http://www.ttelectronics.com/sites/default/files/download-files/Datasheet_PanelPot_P09xSeries.pdf -potentiometer vertical TT P0915N single -0 -5 -3 -Potentiometer_THT -Potentiometer_Vishay_43_Horizontal -Potentiometer, horizontal, Vishay 43, http://www.vishay.com/docs/57026/43.pdf -Potentiometer horizontal Vishay 43 -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_148-149_Dual_Horizontal -Potentiometer, horizontal, Vishay 148-149 Dual, http://www.vishay.com/docs/57040/148149.pdf -Potentiometer horizontal Vishay 148-149 Dual -0 -6 -6 -Potentiometer_THT -Potentiometer_Vishay_148-149_Single_Horizontal -Potentiometer, horizontal, Vishay 148-149 Single, http://www.vishay.com/docs/57040/148149.pdf -Potentiometer horizontal Vishay 148-149 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_148-149_Single_Vertical -Potentiometer, vertical, Vishay 148-149 Single, http://www.vishay.com/docs/57040/148149.pdf -Potentiometer vertical Vishay 148-149 Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_148E-149E_Dual_Horizontal -Potentiometer, horizontal, Vishay 148E-149E Dual, http://www.vishay.com/docs/57040/148149.pdf -Potentiometer horizontal Vishay 148E-149E Dual -0 -10 -6 -Potentiometer_THT -Potentiometer_Vishay_148E-149E_Single_Horizontal -Potentiometer, horizontal, Vishay 148E-149E Single, http://www.vishay.com/docs/57040/148149.pdf -Potentiometer horizontal Vishay 148E-149E Single -0 -7 -3 -Potentiometer_THT -Potentiometer_Vishay_248BH-249BH_Single_Horizontal -Potentiometer, horizontal, Vishay 248BH-249BH Single, http://www.vishay.com/docs/57054/248249.pdf -Potentiometer horizontal Vishay 248BH-249BH Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_248GJ-249GJ_Single_Horizontal -Potentiometer, horizontal, Vishay 248GJ-249GJ Single, http://www.vishay.com/docs/57054/248249.pdf -Potentiometer horizontal Vishay 248GJ-249GJ Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_248GJ-249GJ_Single_Vertical -Potentiometer, vertical, Vishay 248GJ-249GJ Single, http://www.vishay.com/docs/57054/248249.pdf -Potentiometer vertical Vishay 248GJ-249GJ Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_T7-YA_Single_Vertical -Potentiometer, vertical, Vishay T7-YA Single, http://www.vishay.com/docs/51015/t7.pdf -Potentiometer vertical Vishay T7-YA Single -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_T73XW_Horizontal -Potentiometer, horizontal, Vishay T73XW, http://www.vishay.com/docs/51016/t73.pdf -Potentiometer horizontal Vishay T73XW -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_T73XX_Horizontal -Potentiometer, horizontal, Vishay T73XX, http://www.vishay.com/docs/51016/t73.pdf -Potentiometer horizontal Vishay T73XX -0 -3 -3 -Potentiometer_THT -Potentiometer_Vishay_T73YP_Vertical -Potentiometer, vertical, Vishay T73YP, http://www.vishay.com/docs/51016/t73.pdf -Potentiometer vertical Vishay T73YP -0 -3 -3 -RF -Skyworks_SKY13575_639LF -http://www.skyworksinc.com/uploads/documents/SKY13575_639LF_203270D.pdf -Skyworks -0 -19 -15 -RF -Skyworks_SKY65404-31 -http://www.skyworksinc.com/uploads/documents/SKY65404_31_201512K.pdf -Skyworks -0 -7 -7 -RF_Antenna -Coilcraft_MA5532-AE_RFID -RFID Transponder Coil -antenna rfid coilcraft -0 -2 -2 -RF_Antenna -Pulse_W3011 -Pulse RF Antenna, 4mm Clearance -antenna rf -0 -3 -2 -RF_Antenna -Texas_SWRA117D_2.4GHz_Left -http://www.ti.com/lit/an/swra117d/swra117d.pdf -PCB antenna -0 -2 -2 -RF_Antenna -Texas_SWRA117D_2.4GHz_Right -http://www.ti.com/lit/an/swra117d/swra117d.pdf -PCB antenna -0 -2 -2 -RF_Antenna -Texas_SWRA416_868MHz_915MHz -http://www.ti.com/lit/an/swra416/swra416.pdf -PCB antenna -0 -20 -1 -RF_Converter -Anaren_0805_2012Metric-6 -https://cdn.anaren.com/product-documents/Xinger/DirectionalCouplers/DC4759J5020AHF/DC4759J5020AHF_DataSheet(Rev_E).pdf -coupler rf -0 -6 -6 -RF_Converter -Balun_Johanson_1.6x0.8mm -6-pin 1.6x0.8 mm balun footprint -Johanson balun filter -0 -6 -6 -RF_Converter -Balun_Johanson_5400BL15B050E -https://www.johansontechnology.com/datasheets/5400BL15B050/5400BL15B050.pdf -balun RF -0 -6 -6 -RF_Converter -RF_Attenuator_Susumu_PAT1220 -http://www.susumu-usa.com/pdf/Foot_Print_38.pdf, https://www.susumu.co.jp/common/pdf/n_catalog_partition16_en.pdf -2mm 1.2mm -0 -3 -3 -RF_GPS -Linx_RXM-GPS -GPS Module, Linx -gps linx -0 -22 -22 -RF_GPS -SIM28ML -https://simcom.ee/documents/SIM28ML/SIM28ML_Hardware%20Design_V1.01.pdf -SIM28ML GPS -0 -18 -18 -RF_GPS -Sierra_XA11X0 -QFN-24, Pitch 1.20 no EP, https://source.sierrawireless.com/resources/airprime/hardware_specs_user_guides/airprime_xm1100_product_technical_specification -QFN-24 P1.20 -0 -24 -24 -RF_GPS -Sierra_XM11X0 -QFN-20, Pitch 1.20 no EP, https://source.sierrawireless.com/resources/airprime/hardware_specs_user_guides/airprime_xm1100_product_technical_specification -QFN-20 P1.20 -0 -20 -20 -RF_GPS -ublox_LEA -ublox LEA 6/7/8, (https://www.u-blox.com/sites/default/files/LEA-M8S-M8T-FW3_HardwareIntegrationManual_%28UBX-15030060%29.pdf) -GPS ublox LEA 6/7/8 -0 -28 -28 -RF_GPS -ublox_MAX -ublox MAX 6/7/8, (https://www.u-blox.com/sites/default/files/MAX-8-M8-FW3_HardwareIntegrationManual_%28UBX-15030059%29.pdf) -GPS ublox MAX 6/7/8 -0 -18 -18 -RF_GPS -ublox_NEO -ublox NEO 6/7/8, (https://www.u-blox.com/sites/default/files/NEO-8Q-NEO-M8-FW3_HardwareIntegrationManual_%28UBX-15029985%29_0.pdf) -GPS ublox NEO 6/7/8 -0 -24 -24 -RF_GPS -ublox_SAM-M8Q -GPS Module, 15.5x15.5x6.3mm, https://www.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf -ublox SAM-M8Q -0 -100 -20 -RF_GPS -ublox_SAM-M8Q_HandSolder -GPS Module, 15.5x15.5x6.3mm, https://www.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf -ublox SAM-M8Q -0 -20 -20 -RF_GSM -Quectel_BC66 -GSM NB-IoT module, 15.8x17.7x2mm, https://www.quectel.com/UploadImage/Downlad/Quectel_BC66_Hardware_Design_V1.1.pdf -GSM NB-IoT Module BC66 M66 -0 -58 -58 -RF_GSM -SIMCom_SIM800C -Quad-Band GSM/GPRS module, 17.6x15.7x2.3mm, http://simcom.ee/documents/SIM800C/SIM800C_Hardware_Design_V1.05.pdf -GSM Module SIM800C -0 -42 -42 -RF_GSM -SIMCom_SIM900 -Quad-Band GSM/GPRS module, 24x24x3mm, http://simcom.ee/documents/SIM900/SIM900_Hardware%20Design_V2.05.pdf -GSM Module SIM900 -0 -68 -68 -RF_GSM -Telit_xL865 -Telit xL865 familly footprint, http://www.telit.com/fileadmin/user_upload/products/Downloads/3G/Telit_UL865_Hardware_User_Guide_r8.pdf -xL865 gsm umts -0 -52 -48 -RF_GSM -ublox_SARA-G3_LGA-96 -ublox Sara GSM/HSPA modem, https://www.u-blox.com/sites/default/files/SARA-G3-U2_SysIntegrManual_%28UBX-13000995%29.pdf, pag.162 -ublox SARA-G3 SARA-U2 GSM HSPA -0 -192 -96 -RF_Mini-Circuits -Mini-Circuits_BK377 -Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf) -Mini-circuits BK377 -0 -14 -14 -RF_Mini-Circuits -Mini-Circuits_BK377_LandPatternPL-005 -Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf) according to land-pattern PL-005, including GND vias (https://ww2.minicircuits.com/pcb/98-pl005.pdf) -Mini-circuits VCXO JTOS PL-005 -0 -50 -14 -RF_Mini-Circuits -Mini-Circuits_CD541_H2.08mm -https://ww2.minicircuits.com/case_style/CD541.pdf -RF Transformer -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_CD542_H2.84mm -https://ww2.minicircuits.com/case_style/CD542.pdf -RF Transformer -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_CD542_LandPatternPL-052 -Footprint for Mini-Circuits case CD542 (https://ww2.minicircuits.com/case_style/CD542.pdf) using land-pattern PL-052, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl052.pdf) -MiniCircuits PL-052 CD542 -0 -17 -6 -RF_Mini-Circuits -Mini-Circuits_CD542_LandPatternPL-094 -Footprint for mini circuit case CD542, Land pattern PL-094, pads 5 and 2 connected via insulated copper area below body, vias included (case drawing: https://ww2.minicircuits.com/case_style/CD542.pdf, land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl094.pdf) -mini-circuits CD542 pl-094 -0 -18 -6 -RF_Mini-Circuits -Mini-Circuits_CD636_H4.11mm -https://ww2.minicircuits.com/case_style/CD636.pdf -RF Transformer -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_CD636_LandPatternPL-035 -Footprint for Mini-Circuits case CD636 (https://ww2.minicircuits.com/case_style/CD636.pdf) following land pattern PL-035, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl035.pdf) -mini-circuits pl-035 CD636 -0 -13 -6 -RF_Mini-Circuits -Mini-Circuits_CD637_H5.23mm -https://ww2.minicircuits.com/case_style/CD637.pdf -RF Transformer -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_CK605 -Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf) -Mini-Circuits CK605 -0 -16 -16 -RF_Mini-Circuits -Mini-Circuits_CK605_LandPatternPL-012 -Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf) following land pattern PL-012, including GND vias (https://ww2.minicircuits.com/pcb/98-pl012.pdf) -Mini-Circuits PL-012 -0 -53 -16 -RF_Mini-Circuits -Mini-Circuits_DB1627 -Mini-Circuits top-hat case DB1627 (https://ww2.minicircuits.com/case_style/DB1627.pdf) -Mini-Circuits DB1627 -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_GP731 -Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) -Mini-Circuits GP731 -0 -8 -8 -RF_Mini-Circuits -Mini-Circuits_GP731_LandPatternPL-176 -Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf) -mini-circuits PL-176 -0 -21 -8 -RF_Mini-Circuits -Mini-Circuits_GP1212 -Footprint for Mini-Circuits case GP1212 (https://ww2.minicircuits.com/case_style/GP731.pdf) -mini-circuits GP1212 -0 -8 -8 -RF_Mini-Circuits -Mini-Circuits_GP1212_LandPatternPL-176 -Footprint for Mini-Circuits case GP1212 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf) -mini-circuits PL-176 -0 -21 -8 -RF_Mini-Circuits -Mini-Circuits_HF1139 -Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf) -Mini-Circuits HF1139 -0 -8 -8 -RF_Mini-Circuits -Mini-Circuits_HF1139_LandPatternPL-230 -Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf) following land pattern PL-230, including GND vias (https://ww2.minicircuits.com/pcb/98-pl230.pdf) -Mini-Circuits PL-230 -0 -37 -8 -RF_Mini-Circuits -Mini-Circuits_HZ1198 -Footprint for Mini-Circuits case HZ1198 (https://ww2.minicircuits.com/case_style/HZ1198.pdf) -Mini-Circuits HZ1198 -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_HZ1198_LandPatternPL-247 -Footprint for Mini-Circuits cas HZ1198 (https://ww2.minicircuits.com/case_style/HZ1198.pdf) following land pattern PL-247, including GND-vias (https://www.minicircuits.com/pcb/98-pl247.pdf) -Mini-Circuits PL-247 HZ1198 -0 -40 -6 -RF_Mini-Circuits -Mini-Circuits_MMM168 -Footprint for Mini-Circuits case MMM168 (https://ww2.minicircuits.com/case_style/MMM168.pdf) -Mini-Circuits MMM168 -0 -4 -4 -RF_Mini-Circuits -Mini-Circuits_MMM168_LandPatternPL-225 -Footprint for Mini-Circuits case MMM168, Land pattern PL-225, vias included, (case drawing: https://ww2.minicircuits.com/case_style/MMM168.pdf, land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl225.pdf) -pl-225 -0 -10 -4 -RF_Mini-Circuits -Mini-Circuits_QQQ130_ClockwisePinNumbering -Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf) -Mini-Circuits QQQ130 -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_QQQ130_LandPattern_PL-236_ClockwisePinNumbering -Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf) following land pattern PL-236, including GND vias (https://ww2.minicircuits.com/pcb/98-pl236.pdf) -Mini-Circuits PL-236 -0 -14 -6 -RF_Mini-Circuits -Mini-Circuits_TT1224_ClockwisePinNumbering -Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl258.pdf) -Mini-Circuits TT1224 -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_TT1224_LandPatternPL-258_ClockwisePinNumbering -Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl258.pdf) -PL-258 Mini-Circuits -0 -26 -6 -RF_Mini-Circuits -Mini-Circuits_TTT167 -Footprint for Mini-Circuits case TTT167 (https://ww2.minicircuits.com/case_style/TTT167.pdf) -Mini-Circuits TTT167 -0 -6 -6 -RF_Mini-Circuits -Mini-Circuits_TTT167_LandPatternPL-079 -Footprint for Mini-Circuits case TTT167 (Mini-Circuits_TTT167_LandPatternPL-079) following land pattern PL-079, including GND vias (https://ww2.minicircuits.com/pcb/98-pl079.pdf) -Mini-Circuits PL-079 -0 -36 -6 -RF_Mini-Circuits -Mini-Circuits_YY161 -Footprint for Mini-Circuits case YY161 (https://ww2.minicircuits.com/case_style/YY161.pdf) -Mini-Circuits YY161 -0 -8 -8 -RF_Mini-Circuits -Mini-Circuits_YY161_LandPatternPL-049 -Footprint for Mini-Circuits case YY161 (https://ww2.minicircuits.com/case_style/YY161.pdf) using land-pattern PL-049, including GND-connections and vias (https://ww2.minicircuits.com/pcb/98-pl049.pdf) -mini-circuits pl-049 -0 -36 -8 -RF_Module -Ai-Thinker-Ra-01-LoRa -Ai Thinker Ra-01 LoRa -LoRa Ra-01 -0 -16 -16 -RF_Module -Atmel_ATSAMR21G18-MR210UA_NoRFPads -http://ww1.microchip.com/downloads/en/devicedoc/atmel-42475-atsamr21g18-mr210ua_datasheet.pdf -module wireless zigbee 802.15.4 flash crypto ATSAMR21G18 AT45DB041E TECC508A U.Fi -0 -42 -42 -RF_Module -BLE112-A -Class 4 Bluetooth Module with on-board antenna -Bluetooth Module -0 -30 -30 -RF_Module -CMWX1ZZABZ -https://wireless.murata.com/RFM/data/type_abz.pdf -iot lora sigfox -0 -57 -57 -RF_Module -CYBLE-21Pin-10x10mm -Cypress EZ-BLE PRoC Module (Bluetooth Smart) 21 Pin Module -Cypress BT Bluetooth -0 -21 -21 -RF_Module -DWM1000 -IEEE802.15.4-2011 UWB -UWB Module -0 -24 -24 -RF_Module -DecaWave_DWM1001 -https://www.decawave.com/sites/default/files/dwm1001_datasheet.pdf -UWB module -0 -34 -34 -RF_Module -Digi_XBee_SMT -http://www.digi.com/resources/documentation/digidocs/pdfs/90002126.pdf http://ftp1.digi.com/support/documentation/90001020_F.pdf -Digi XBee SMT RF -0 -37 -37 -RF_Module -E18-MS1-PCB -http://www.cdebyte.com/en/downpdf.aspx?id=122 -Zigbee -0 -24 -24 -RF_Module -E73-2G4M04S -http://www.cdebyte.com/en/downpdf.aspx?id=243 -BLE BLE5 nRF52832 -0 -44 -44 -RF_Module -ESP-07 -Wi-Fi Module, http://wiki.ai-thinker.com/_media/esp8266/docs/a007ps01a2_esp-07_product_specification_v1.2.pdf -Wi-Fi Module -0 -16 -16 -RF_Module -ESP-12E -Wi-Fi Module, http://wiki.ai-thinker.com/_media/esp8266/docs/aithinker_esp_12f_datasheet_en.pdf -Wi-Fi Module -0 -22 -22 -RF_Module -ESP-WROOM-02 -http://espressif.com/sites/default/files/documentation/0c-esp-wroom-02_datasheet_en.pdf -ESP WROOM-02 espressif esp8266ex -0 -19 -19 -RF_Module -ESP32-WROOM-32 -Single 2.4 GHz Wi-Fi and Bluetooth combo chip https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32_datasheet_en.pdf -Single 2.4 GHz Wi-Fi and Bluetooth combo chip -0 -39 -39 -RF_Module -ESP32-WROOM-32U -Single 2.4 GHz Wi-Fi and Bluetooth combo chip with U.FL connector, https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32d_esp32-wroom-32u_datasheet_en.pdf -Single 2.4 GHz Wi-Fi and Bluetooth combo chip -0 -39 -39 -RF_Module -Garmin_M8-35_9.8x14.0mm_Layout6x6_P1.5mm -D52M ANT SoC Module https://www.thisisant.com/assets/resources/D00001687_D52_Module_Datasheet.v.2.3_(Garmin).pdf -RF SoC Radio ANT Bluetooth BLE D52 nRF52 Garmin Canada Dynastream Nordic -0 -35 -35 -RF_Module -HOPERF_RFM9XW_SMD -Low Power Long Range Transceiver Module SMD-16 (https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf) -LoRa Low Power Long Range Transceiver Module -0 -16 -16 -RF_Module -HOPERF_RFM9XW_THT -Low Power Long Range Transceiver Module THT-16 (https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf) -Low Power Long Range Transceiver Module LoRa -0 -16 -16 -RF_Module -HOPERF_RFM69HW -Radio, RF, Module, http://www.hoperf.com/upload/rf/RFM69HW-V1.3.pdf -Radio RF Module -0 -16 -16 -RF_Module -IQRF_TRx2DA_KON-SIM-01 -8 pin SIM connector for IQRF TR-x2DA(T) modules, http://iqrf.org/weben/downloads.php?id=104 -IQRF_KON-SIM-01 IQRF_TRx2DA -0 -10 -8 -RF_Module -IQRF_TRx2D_KON-SIM-01 -8 pin SIM connector for IQRF TR-x2D(C)(T) modules, http://iqrf.org/weben/downloads.php?id=104 -IQRF_KON-SIM-01 IQRF_TRx2D IQRF_TRx2DC -0 -10 -8 -RF_Module -Laird_BL652 -Bluetooth v4.2 + NFC module -Bluetooth BLE NFC -0 -39 -39 -RF_Module -MOD-nRF8001 -BLE module, https://www.olimex.com/Products/Modules/RF/MOD-nRF8001/ -BLE module -0 -11 -11 -RF_Module -Microchip_RN4871 -Microchip RN4871 footprint -RN4871 BLE -0 -16 -16 -RF_Module -Modtronix_inAir9 -Modtronix Wireless SX1276 LoRa Module (http://modtronix.com/img/prod/imod/inair9/inair_dimensions.gif) -Modtronix LoRa inAir inAir9 SX1276 RF 915MHz 868MHz Wireless -0 -14 -14 -RF_Module -MonoWireless_TWE-L-WX -https://www.mono-wireless.com/jp/products/TWE-LITE/MW-PDS-TWELITE-JP.pdf -TWE-L-WX -0 -32 -32 -RF_Module -Particle_P1 -https://docs.particle.io/datasheets/p1-datasheet/ -Particle P1 -0 -75 -75 -RF_Module -RFDigital_RFD77101 -RFDigital RFD77101 Simblee -RFDigital RFD77101 Simblee -0 -48 -45 -RF_Module -RN42 -Class 2 Bluetooth Module with on-board antenna -Bluetooth Module -0 -36 -33 -RF_Module -RN42N -Class 2 Bluetooth Module without antenna -Bluetooth Module -0 -39 -36 -RF_Module -RN2483 -Low-Power Long Range LoRa Transceiver Module -rf module lora lorawan -0 -47 -47 -RF_Module -ST_SPBTLE -Bluetooth Low Energy Module -ble module st bluetooth -0 -11 -11 -RF_Module -TD1205 -https://github.com/Telecom-Design/Documentation_TD_RF_Module/blob/master/TD1205%20Datasheet.pdf -SIGFOX Module -0 -9 -9 -RF_Module -TD1208 -https://github.com/Telecom-Design/Documentation_TD_RF_Module/blob/master/TD1208%20Datasheet.pdf -SIGFOX Module -0 -25 -25 -RF_Module -Taiyo-Yuden_EYSGJNZWY -Taiyo Yuden NRF51822 Module Bluetooth https://www.yuden.co.jp/wireless_module/document/datareport2/en/TY_BLE_EYSGJNZ_DataReport_V1_9_20180530E.pdf -Taiyo Yuden NRF51822 Module Bluetooth -0 -30 -28 -RF_Module -ZETA-433-SO_SMD -RF transceiver SMD style https://www.rfsolutions.co.uk/downloads/1456219226DS-ZETA.pdf -RF transceiver SMD style -0 -12 -12 -RF_Module -ZETA-433-SO_THT -RF transceiver THT style https://www.rfsolutions.co.uk/downloads/1456219226DS-ZETA.pdf -RF transceiver SMD style -0 -12 -12 -RF_Module -nRF24L01_Breakout -nRF24L01 breakout board -nRF24L01 adapter breakout -0 -8 -8 -RF_Shielding -Laird_Technologies_97-2002_25.40x25.40mm -Laird Technologies 97-2002 EZ PEEL Shielding Cabinet One Piece SMD 25.40x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -8 -1 -RF_Shielding -Laird_Technologies_97-2003_12.70x13.37mm -Laird Technologies 97-2003 EZ PEEL Shielding Cabinet One Piece SMD 12.70x13.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -8 -1 -RF_Shielding -Laird_Technologies_BMI-S-101_13.66x12.70mm -Laird Technologies BMI-S-101 Shielding Cabinet One Piece SMD 13.66x12.70mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -16 -1 -RF_Shielding -Laird_Technologies_BMI-S-102_16.50x16.50mm -Laird Technologies BMI-S-102 Shielding Cabinet One Piece SMD 16.50x16.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -16 -1 -RF_Shielding -Laird_Technologies_BMI-S-103_26.21x26.21mm -Laird Technologies BMI-S-103 Shielding Cabinet One Piece SMD 26.21x26.21mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -24 -1 -RF_Shielding -Laird_Technologies_BMI-S-104_32.00x32.00mm -Laird Technologies BMI-S-104 Shielding Cabinet One Piece SMD 32.00x32.00mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -28 -1 -RF_Shielding -Laird_Technologies_BMI-S-105_38.10x25.40mm -Laird Technologies BMI-S-105 Shielding Cabinet One Piece SMD 38.10x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -28 -1 -RF_Shielding -Laird_Technologies_BMI-S-106_36.83x33.68mm -Laird Technologies BMI-S-106 Shielding Cabinet One Piece SMD 36.83x33.68mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -28 -1 -RF_Shielding -Laird_Technologies_BMI-S-107_44.37x44.37mm -Laird Technologies BMI-S-107 Shielding Cabinet One Piece SMD 44.37x44.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -36 -1 -RF_Shielding -Laird_Technologies_BMI-S-201-F_13.66x12.70mm -Laird Technologies BMI-S-201-F Shielding Cabinet Two Piece SMD 13.66x12.70mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -16 -1 -RF_Shielding -Laird_Technologies_BMI-S-202-F_16.50x16.50mm -Laird Technologies BMI-S-202-F Shielding Cabinet Two Piece SMD 16.50x16.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -16 -1 -RF_Shielding -Laird_Technologies_BMI-S-203-F_26.21x26.21mm -Laird Technologies BMI-S-203-F Shielding Cabinet Two Piece SMD 26.21x26.21mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -24 -1 -RF_Shielding -Laird_Technologies_BMI-S-204-F_32.00x32.00mm -Laird Technologies BMI-S-204-F Shielding Cabinet Two Piece SMD 32.00x32.00mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -28 -1 -RF_Shielding -Laird_Technologies_BMI-S-205-F_38.10x25.40mm -Laird Technologies BMI-S-205-F Shielding Cabinet Two Piece SMD 38.10x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -28 -1 -RF_Shielding -Laird_Technologies_BMI-S-206-F_36.83x33.68mm -Laird Technologies BMI-S-206-F Shielding Cabinet Two Piece SMD 36.83x33.68mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -28 -1 -RF_Shielding -Laird_Technologies_BMI-S-207-F_44.37x44.37mm -Laird Technologies BMI-S-207-F Shielding Cabinet Two Piece SMD 44.37x44.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -36 -1 -RF_Shielding -Laird_Technologies_BMI-S-208-F_39.60x39.60mm -Laird Technologies BMI-S-208-F Shielding Cabinet Two Piece SMD 39.60x39.60mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -32 -1 -RF_Shielding -Laird_Technologies_BMI-S-209-F_29.36x18.50mm -Laird Technologies BMI-S-209-F Shielding Cabinet Two Piece SMD 29.36x18.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -20 -1 -RF_Shielding -Laird_Technologies_BMI-S-210-F_44.00x30.50mm -Laird Technologies BMI-S-210-F Shielding Cabinet Two Piece SMD 44.00x30.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) -Shielding Cabinet -0 -32 -1 -RF_Shielding -Laird_Technologies_BMI-S-230-F_50.8x38.1mm -Laird Technologies BMI-S-230-F Shielding Cabinet Two Piece SMD 50.8x38.1mm -Shielding Cabinet -0 -36 -1 -RF_Shielding -Wuerth_36103205_20x20mm -WE-SHC Shielding Cabinet SMD 20x20mm -Shielding Cabinet -0 -20 -1 -RF_Shielding -Wuerth_36103255_25x25mm -WE-SHC Shielding Cabinet SMD 25x25mm -Shielding Cabinet -0 -24 -1 -RF_Shielding -Wuerth_36103305_30x30mm -WE-SHC Shielding Cabinet SMD 30x30mm -Shielding Cabinet -0 -28 -1 -RF_Shielding -Wuerth_36103505_50x50mm -WE-SHC Shielding Cabinet SMD 50x50mm -Shielding Cabinet -0 -44 -1 -RF_Shielding -Wuerth_36103605_60x60mm -WE-SHC Shielding Cabinet SMD 60x60mm -Shielding Cabinet -0 -52 -1 -RF_Shielding -Wuerth_36503205_20x20mm -WE-SHC Shielding Cabinet THT 21x21mm -Shielding Cabinet -0 -16 -1 -RF_Shielding -Wuerth_36503255_25x25mm -WE-SHC Shielding Cabinet THT 26x26mm -Shielding Cabinet -0 -20 -1 -RF_Shielding -Wuerth_36503305_30x30mm -WE-SHC Shielding Cabinet THT 31x31mm -Shielding Cabinet -0 -24 -1 -RF_Shielding -Wuerth_36503505_50x50mm -WE-SHC Shielding Cabinet THT 51x51mm -Shielding Cabinet -0 -40 -1 -RF_Shielding -Wuerth_36503605_60x60mm -WE-SHC Shielding Cabinet THT 61x61mm -Shielding Cabinet -0 -48 -1 -RF_WiFi -USR-C322 -https://www.usriot.com/download/WIFI/USR-C322-Hardware-Manual_V1.2.01.pdf -WiFi IEEE802.11 b/g/n -0 -44 -44 -Relay_SMD -Relay_DPDT_AXICOM_IMSeries_JLeg -http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Specification+Or+Standard%7F108-98001%7FW5%7Fpdf%7FEnglish%7FENG_SS_108-98001_W5.pdf -AXICOM IM-Series Relay J JLeg -0 -8 -8 -Relay_SMD -Relay_DPDT_FRT5_SMD -IM Signal Relay DPDT FRT5 narrow footprint, SMD version of package -Relay DPDT IM-relay FRT5 -0 -10 -10 -Relay_SMD -Relay_DPDT_Omron_G6H-2F -package for Omron G6H-2F relais, see http://cdn-reichelt.de/documents/datenblatt/C300/G6H%23OMR.pdf -Omron G6H-2F relais -0 -10 -10 -Relay_SMD -Relay_DPDT_Omron_G6K-2F -Omron G6K-2F relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf -Omron G6K-2F relay -0 -8 -8 -Relay_SMD -Relay_DPDT_Omron_G6K-2F-Y -Omron G6K-2F-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf -Omron G6K-2F-Y relay -0 -8 -8 -Relay_SMD -Relay_DPDT_Omron_G6K-2G -Omron G6K-2G relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf -Omron G6K-2G relay -0 -8 -8 -Relay_SMD -Relay_DPDT_Omron_G6K-2G-Y -Omron G6K-2G-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf -Omron G6K-2G-Y relay -0 -8 -8 -Relay_SMD -Relay_DPDT_Omron_G6S-2F -Relay Omron G6S-2F, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf -Relay Omron G6S-2F -0 -8 -8 -Relay_SMD -Relay_DPDT_Omron_G6S-2G -Relay Omron G6S-2G, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf -Relay Omron G6S-2G -0 -8 -8 -Relay_SMD -Relay_DPDT_Omron_G6SK-2F -Relay Omron G6SK-2F, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf -Relay Omron G6SK-2F -0 -10 -10 -Relay_SMD -Relay_DPDT_Omron_G6SK-2G -Relay Omron G6SK-2G, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf -Relay Omron G6SK-2G -0 -10 -10 -Relay_SMD -Relay_SPDT_AXICOM_HF3Series_50ohms_Pitch1.27mm -hiqsdr.com/images/3/3e/Axicom-HF3.pdf -AXICOM HF3-Series Relay Pitch 1.27mm 50ohms -0 -16 -16 -Relay_SMD -Relay_SPDT_AXICOM_HF3Series_75ohms_Pitch1.27mm -hiqsdr.com/images/3/3e/Axicom-HF3.pdf -AXICOM HF3-Series Relay Pitch 1.27mm 75ohm -0 -16 -16 -Relay_THT -Relay_1-Form-A_Schrack-RYII_RM5mm -Relay, 1-Form-A, Schrack-RYII, RM5mm, SPST-NO -Relay 1-Form-A Schrack-RYII RM5mm SPST-NO -0 -4 -4 -Relay_THT -Relay_1-Form-B_Schrack-RYII_RM5mm -Relay, 1-Form-B, Schrack-RYII, RM5mm, SPST-NC -Relay 1-Form-B Schrack-RYII RM5mm SPST-NC -0 -4 -4 -Relay_THT -Relay_1-Form-C_Schrack-RYII_RM3.2mm -Relay, 1-Form-C, Schrack-RYII, RM3.2mm, SPDT -Relay 1-Form-C Schrack-RYII RM3.2mm SPDT -0 -5 -5 -Relay_THT -Relay_DPDT_AXICOM_IMSeries_Pitch3.2mm -AXICOM IM-Series Relays, DPDR, Pitch 3.2mm, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Specification+Or+Standard%7F108-98001%7FV%7Fpdf%7FEnglish%7FENG_SS_108-98001_V_IM_0614_v1.pdf%7F4-1462039-1 -AXICOM IM-Series Relay DPDR Pitch 3.2mm -0 -8 -8 -Relay_THT -Relay_DPDT_AXICOM_IMSeries_Pitch5.08mm -AXICOM IM-Series Relays, DPDR, Pitch 5.08 -AXICOM IM-Series Relay DPDR Pitch 5.08 -0 -8 -8 -Relay_THT -Relay_DPDT_FRT5 -IM Signal Relay DPDT FRT5 narrow footprint -Relay DPDT IM-relay FRT5 -0 -10 -10 -Relay_THT -Relay_DPDT_Finder_30.22 -Finder 32.21-x000 Relay, DPDT, https://gfinder.findernet.com/public/attachments/30/EN/S30EN.pdf -AXICOM IM-Series Relay SPDT -0 -8 -8 -Relay_THT -Relay_DPDT_Finder_40.52 -Relay DPDT Finder 40.52, Pitch 5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf -Relay DPDT Finder 40.52 Pitch 5mm -0 -8 -8 -Relay_THT -Relay_DPDT_Fujitsu_FTR-F1C -https://www.fujitsu.com/downloads/MICRO/fcai/relays/ftr-f1.pdf -relay dpdt fujitsu tht -0 -8 -8 -Relay_THT -Relay_DPDT_Omron_G5V-2 -http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5v2.pdf -Omron G5V-2 Relay DPDT -0 -8 -8 -Relay_THT -Relay_DPDT_Omron_G6H-2 -Omron relay G6H-2, see http://cdn-reichelt.de/documents/datenblatt/C300/G6H%23OMR.pdf -Omron relay G6H-2 -0 -10 -10 -Relay_THT -Relay_DPDT_Omron_G6K-2P -Omron G6K-2P relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf -Omron G6K-2P relay -0 -8 -8 -Relay_THT -Relay_DPDT_Omron_G6K-2P-Y -Omron G6K-2P-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf -Omron G6K-2P-Y relay -0 -8 -8 -Relay_THT -Relay_DPDT_Omron_G6S-2 -Relay Omron G6S-2, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf -Relay Omron G6S-2 -0 -8 -8 -Relay_THT -Relay_DPDT_Omron_G6SK-2 -Relay Omron G6SK-2, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf -Relay Omron G6SK-2 -0 -10 -10 -Relay_THT -Relay_DPDT_Panasonic_JW2 -Panasonic Relay DPDT, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok -Panasonic Relay DPDT -0 -8 -8 -Relay_THT -Relay_DPDT_Schrack-RT2-FormC-Dual-Coil_RM5mm -Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7FRT2_bistable%7F1116%7Fpdf%7FEnglish%7FENG_DS_RT2_bistable_1116.pdf%7F1-1415537-8 -Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Relay -0 -9 -9 -Relay_THT -Relay_DPDT_Schrack-RT2-FormC_RM5mm -Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN -Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Relay -0 -8 -8 -Relay_THT -Relay_DPST_Fujitsu_FTR-F1A -https://www.fujitsu.com/downloads/MICRO/fcai/relays/ftr-f1.pdf -relay dpst fujitsu tht -0 -6 -6 -Relay_THT -Relay_DPST_Schrack-RT2-FormA_RM5mm -Relay DPST Schrack-RT2 RM5mm 16A 250V AC Form A http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN -Relay DPST Schrack-RT2 RM5mm 16A 250V AC Relay -0 -6 -6 -Relay_THT -Relay_SPDT_Finder_32.21-x000 -Finder 32.21-x000 Relay, SPDT, https://gfinder.findernet.com/assets/Series/355/S32EN.pdf -AXICOM IM-Series Relay SPDT -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_34.51_Horizontal -Relay SPDT, Finder Type34.51, horizontal form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf -Relay SPDT Finder -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_34.51_Vertical -Relay SPDT, Finder Type34.51, vertical/standing form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf -Relay SPDT Finder -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_36.11 -FINDER 36.11, SPDT relay, 10A, https://gfinder.findernet.com/public/attachments/36/EN/S36EN.pdf -spdt relay -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_40.11 -Relay SPDT Finder 40.11, https://www.finder-relais.net/de/finder-relais-serie-40.pdf -Relay SPDT Finder 40.11 -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_40.31 -Relay DPDT Finder 40.31, Pitch 3.5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf -Relay DPDT Finder 40.31 Pitch 3.5mm -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_40.41 -Relay DPDT Finder 40.41, Pitch 3.5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf -Relay DPDT Finder 40.41 Pitch 3.5mm -0 -5 -5 -Relay_THT -Relay_SPDT_Finder_40.51 -Relay DPDT Finder 40.51, Pitch 5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf -Relay DPDT Finder 40.51 Pitch 5mm -0 -5 -5 -Relay_THT -Relay_SPDT_HJR-4102 -IM Signal Relay SPDT HJR-4102 -Relay SPDT IM-relay HJR-4102 -0 -6 -6 -Relay_THT -Relay_SPDT_HsinDa_Y14 -http://www.hsinda.com.cn/en/ProductShow.asp?ID=208 -Relay Y14 -0 -6 -6 -Relay_THT -Relay_SPDT_Omron-G5LE-1 -Omron Relay SPDT, http://www.omron.com/ecb/products/pdf/en-g5le.pdf -Omron Relay SPDT -0 -5 -5 -Relay_THT -Relay_SPDT_Omron-G5Q-1 -Relay SPDT Omron Serie G5Q, http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5q.pdf -Relay SPDT Omron Serie G5Q -0 -5 -5 -Relay_THT -Relay_SPDT_Omron_G5V-1 -Relay Omron G5V-1, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5v_1.pdf -Relay Omron G5V-1 -0 -6 -6 -Relay_THT -Relay_SPDT_Omron_G6E -Relay SPDT Omron Serie G6E -Relay SPDT Omron Serie G6E 1x um -0 -5 -5 -Relay_THT -Relay_SPDT_Omron_G6EK -Relay SPDT Omron Serie G6EK, see http://www.logosfoundation.org/instrum_gwr/pi/Omron_G6E_134P.pdf -Relay SPDT Omron Serie G6EK -0 -6 -6 -Relay_THT -Relay_SPDT_Panasonic_JW1_FormC -Panasonic Relay SPDT, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok -Panasonic Relay SPDT -0 -5 -5 -Relay_THT -Relay_SPDT_PotterBrumfield_T9AP5D52_12V30A -Relay SPDT Potter&Brumfield T9AP5D52 12V 30A 1xUn Connector Fast ON Only Dummy for Space NO Pads -Relay SPDT Potter&Brumfield T9AP5D52 12V 30A 1xUm Connector Fast ON Flachsteckeranschluss Only Dummy for Space NO Pads -0 -0 -0 -Relay_THT -Relay_SPDT_RAYEX-L90 -https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf -Relay RAYEX L90 SPDT -0 -6 -6 -Relay_THT -Relay_SPDT_RAYEX-L90S -https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf -Relay RAYEX L90S SPDT -0 -5 -5 -Relay_THT -Relay_SPDT_SANYOU_SRD_Series_Form_C -relay Sanyou SRD series Form C http://www.sanyourelay.ca/public/products/pdf/SRD.pdf -relay Sanyu SRD form C -0 -5 -5 -Relay_THT -Relay_SPDT_Schrack-RP-II-1-16A-FormC_RM5mm -Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf -Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Relay -0 -8 -5 -Relay_THT -Relay_SPDT_Schrack-RP-II-1-FormC_RM3.5mm -Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf -Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Relay -0 -5 -5 -Relay_THT -Relay_SPDT_Schrack-RP-II-1-FormC_RM5mm -Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf -Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Relay -0 -5 -5 -Relay_THT -Relay_SPDT_Schrack-RT1-16A-FormC_RM5mm -Relay SPST Schrack-RT1 RM5mm 16A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf -Relay SPST Schrack-RT1 RM5mm 16A 250V AC Relay -0 -8 -5 -Relay_THT -Relay_SPDT_Schrack-RT1-FormC_RM3.5mm -Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf -Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Relay -0 -5 -5 -Relay_THT -Relay_SPDT_Schrack-RT1-FormC_RM5mm -Relay SPST Schrack-RT1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf -Relay SPST Schrack-RT1 RM5mm 8A 250V AC Relay -0 -5 -5 -Relay_THT -Relay_SPDT_StandexMeder_SIL_Form1C -Standex-Meder SIL-relais, Form 1C, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf -Standex Meder SIL reed relais -0 -5 -5 -Relay_THT -Relay_SPST_Finder_32.21-x300 -Finder 32.21-x300 Relay, SPST, https://gfinder.findernet.com/assets/Series/355/S32EN.pdf -Finder 32.21-x300 Relay SPST -0 -4 -4 -Relay_THT -Relay_SPST_Omron-G5Q-1A -Relay SPST-NO Omron Serie G5Q, http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5q.pdf -Relay SPST-NO Omron Serie G5Q -0 -4 -4 -Relay_THT -Relay_SPST_Panasonic_JW1_FormA -Panasonic Relay SPST, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok -Panasonic Relay SPST -0 -4 -4 -Relay_THT -Relay_SPST_PotterBrumfield_T9AP1D52_12V30A -Relay SPST Potter&Brumfield T9AP1D52 12V 30A 1xEin Connector Fast ON Only Dummy for Space NO Pads -Relau SPST Potter&Brumfield T9AP1D52 12V 30A 1xEin Connector Fast ON Flachsteckeranschluss Only Dummy for Space NO Pads -0 -0 -0 -Relay_THT -Relay_SPST_RAYEX-L90A -https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf -Relay RAYEX L90A SPST NO -0 -5 -5 -Relay_THT -Relay_SPST_RAYEX-L90AS -https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf -Relay RAYEX L90AS SPST NO -0 -4 -4 -Relay_THT -Relay_SPST_RAYEX-L90B -https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf -Relay RAYEX L90B SPST NC -0 -5 -5 -Relay_THT -Relay_SPST_RAYEX-L90BS -https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf -Relay RAYEX L90BS SPST NC -0 -4 -4 -Relay_THT -Relay_SPST_SANYOU_SRD_Series_Form_A -relay Sanyou SRD series Form A http://www.sanyourelay.ca/public/products/pdf/SRD.pdf -relay Sanyu SRD form A -0 -4 -4 -Relay_THT -Relay_SPST_SANYOU_SRD_Series_Form_B -relay Sanyou SRD series Form B opener http://www.sanyourelay.ca/public/products/pdf/SRD.pdf -relay Sanyu SRD form B opener -0 -4 -4 -Relay_THT -Relay_SPST_Schrack-RP-II-1-16A-FormA_RM5mm -Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Form A http://image.schrack.com/datenblaetter/h_rp810012-b.pdf -Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Relay -0 -6 -4 -Relay_THT -Relay_SPST_Schrack-RP-II-1-FormA_RM3.5mm -Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Form A -Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Relay -0 -4 -4 -Relay_THT -Relay_SPST_Schrack-RP-II-1-FormA_RM5mm -Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Form A http://image.schrack.com/datenblaetter/h_rp810012-b.pdf -Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Relay -0 -4 -4 -Relay_THT -Relay_SPST_Schrack-RP3SL-1coil_RM5mm -Relay SPST Schrack-RP3SL, 1-coil-version, RM5mm 16A 250V AC Form A http://www.alliedelec.com/m/d/543c6bed18bf23a83ae5238947033ee0.pdf -Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Relay -0 -6 -4 -Relay_THT -Relay_SPST_Schrack-RP3SL_RM5mm -Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Form A http://www.alliedelec.com/m/d/543c6bed18bf23a83ae5238947033ee0.pdf -Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Relay -0 -7 -5 -Relay_THT -Relay_SPST_Schrack-RT1-16A-FormA_RM5mm -Relay SPST Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN -Relay SPST Schrack-RT2 RM5mm 16A 250V AC Relay -0 -6 -4 -Relay_THT -Relay_SPST_Schrack-RT1-FormA_RM3.5mm -Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Form A -Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Relay -0 -4 -4 -Relay_THT -Relay_SPST_Schrack-RT1-FormA_RM5mm -Relay SPST Schrack-RT1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf -Relay SPST Schrack-RT1 RM5mm 8A 250V AC Relay -0 -4 -4 -Relay_THT -Relay_SPST_StandexMeder_MS_Form1AB -Standex-Meder MS SIL-relais, Form 1A/1B, see https://standexelectronics.com/de/produkte/ms-reed-relais/ -Standex Meder MS SIL reed relais -0 -4 -4 -Relay_THT -Relay_SPST_StandexMeder_SIL_Form1A -Standex-Meder SIL-relais, Form 1A, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf -Standex Meder SIL reed relais -0 -4 -4 -Relay_THT -Relay_SPST_StandexMeder_SIL_Form1B -Standex-Meder SIL-relais, Form 1B, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf -Standex Meder SIL reed relais -0 -4 -4 -Relay_THT -Relay_SPST_TE_PCH-1xxx2M -Miniature PCB Relay, PCH Series, 1 Form A (NO), SPST http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7FPCH_series_relay_data_sheet_E%7F1215%7Fpdf%7FEnglish%7FENG_DS_PCH_series_relay_data_sheet_E_1215.pdf -Relay SPST NO -0 -4 -4 -Relay_THT -Relay_SPST_TE_PCN-1xxD3MHZ -https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1461491%7FG2%7Fpdf%7FEnglish%7FENG_CD_1461491_G2.pdf%7F3-1461491-0 -SPST relay slim -0 -4 -4 -Relay_THT -Relay_Socket_DPDT_Finder_96.12 -https://gfinder.findernet.com/public/attachments/56/DE/S56DE.pdf -Relay socket DPDT Finder 96.12 56.32 -0 -8 -8 -Relay_THT -Relay_StandexMeder_DIP_HighProfile -package for Standex Meder DIP reed relay series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf -DIL DIP PDIP 2.54mm 7.62mm 300mil reed relay -0 -8 -8 -Relay_THT -Relay_StandexMeder_DIP_LowProfile -package for Standex Meder DIP reed relay series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf -DIL DIP PDIP 2.54mm 7.62mm 300mil reed relay -0 -8 -8 -Relay_THT -Relay_StandexMeder_UMS -Standex-Meder SIL-relais, UMS, see http://cdn-reichelt.de/documents/datenblatt/C300/UMS05_1A80_75L_DB.pdf -Standex Meder SIL reed relais -0 -4 -4 -Resistor_SMD -R_0201_0603Metric -Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator -resistor -0 -4 -2 -Resistor_SMD -R_0402_1005Metric -Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_0603_1608Metric -Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_0603_1608Metric_Pad1.05x0.95mm_HandSolder -Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_0612_1632Metric -Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_0612_1632Metric_Pad1.18x3.40mm_HandSolder -Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_0805_2012Metric -Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_0805_2012Metric_Pad1.15x1.40mm_HandSolder -Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_0815_2038Metric -Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.yageo.com/documents/recent/PYu-PRPFPH_521_RoHS_L_0.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_0815_2038Metric_Pad1.53x4.00mm_HandSolder -Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.yageo.com/documents/recent/PYu-PRPFPH_521_RoHS_L_0.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_01005_0402Metric -Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator -resistor -0 -4 -2 -Resistor_SMD -R_1020_2550Metric -Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_1020_2550Metric_Pad1.33x5.20mm_HandSolder -Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_1206_3216Metric -Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_1206_3216Metric_Pad1.42x1.75mm_HandSolder -Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_1210_3225Metric -Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_1210_3225Metric_Pad1.42x2.65mm_HandSolder -Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_1218_3246Metric -Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_1218_3246Metric_Pad1.22x4.75mm_HandSolder -Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_1806_4516Metric -Resistor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_1806_4516Metric_Pad1.57x1.80mm_HandSolder -Resistor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_1812_4532Metric -Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_1812_4532Metric_Pad1.30x3.40mm_HandSolder -Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_2010_5025Metric -Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_2010_5025Metric_Pad1.52x2.65mm_HandSolder -Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_2512_6332Metric -Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_2512_6332Metric_Pad1.52x3.35mm_HandSolder -Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_2816_7142Metric -Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_2816_7142Metric_Pad3.20x4.45mm_HandSolder -Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_4020_10251Metric -Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator -resistor -0 -2 -2 -Resistor_SMD -R_4020_10251Metric_Pad1.65x5.30mm_HandSolder -Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator -resistor handsolder -0 -2 -2 -Resistor_SMD -R_Array_Concave_2x0603 -Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf) -resistor array -0 -4 -4 -Resistor_SMD -R_Array_Concave_4x0402 -Thick Film Chip Resistor Array, Wave soldering, Vishay CRA04P (see cra04p.pdf) -resistor array -0 -8 -8 -Resistor_SMD -R_Array_Concave_4x0603 -Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf) -resistor array -0 -8 -8 -Resistor_SMD -R_Array_Convex_2x0402 -Chip Resistor Network, ROHM MNR02 (see mnr_g.pdf) -resistor array -0 -4 -4 -Resistor_SMD -R_Array_Convex_2x0603 -Chip Resistor Network, ROHM MNR12 (see mnr_g.pdf) -resistor array -0 -4 -4 -Resistor_SMD -R_Array_Convex_2x0606 -Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf) -resistor array -0 -4 -4 -Resistor_SMD -R_Array_Convex_2x1206 -Chip Resistor Network, ROHM MNR32 (see mnr_g.pdf) -resistor array -0 -4 -4 -Resistor_SMD -R_Array_Convex_4x0402 -Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf) -resistor array -0 -8 -8 -Resistor_SMD -R_Array_Convex_4x0603 -Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf) -resistor array -0 -8 -8 -Resistor_SMD -R_Array_Convex_4x0612 -Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf) -resistor array -0 -8 -8 -Resistor_SMD -R_Array_Convex_4x1206 -Chip Resistor Network, ROHM MNR34 (see mnr_g.pdf) -resistor array -0 -8 -8 -Resistor_SMD -R_Array_Convex_5x0603 -Chip Resistor Network, ROHM MNR15 (see mnr_g.pdf) -resistor array -0 -10 -10 -Resistor_SMD -R_Array_Convex_5x1206 -Chip Resistor Network, ROHM MNR35 (see mnr_g.pdf) -resistor array -0 -10 -10 -Resistor_SMD -R_Array_Convex_8x0602 -Chip Resistor Network, ROHM MNR18 (see mnr_g.pdf) -resistor array -0 -16 -16 -Resistor_SMD -R_Cat16-2 -SMT resistor net, Bourns CAT16 series, 2 way -SMT resistor net Bourns CAT16 series 2 way -0 -4 -4 -Resistor_SMD -R_Cat16-4 -SMT resistor net, Bourns CAT16 series, 4 way -SMT resistor net Bourns CAT16 series 4 way -0 -8 -8 -Resistor_SMD -R_Cat16-8 -SMT resistor net, Bourns CAT16 series, 8 way -SMT resistor net Bourns CAT16 series 8 way -0 -16 -16 -Resistor_SMD -R_MELF_MMB-0207 -Resistor, MELF, MMB-0207, http://www.vishay.com/docs/28713/melfprof.pdf -MELF Resistor -0 -2 -2 -Resistor_SMD -R_MicroMELF_MMU-0102 -Resistor, MicroMELF, MMU-0102, http://www.vishay.com/docs/28713/melfprof.pdf -MicroMELF Resistor -0 -2 -2 -Resistor_SMD -R_MiniMELF_MMA-0204 -Resistor, MiniMELF, MMA-0204, http://www.vishay.com/docs/28713/melfprof.pdf -MiniMELF Resistor -0 -2 -2 -Resistor_SMD -R_Shunt_Ohmite_LVK12 -4 contact shunt resistor -shunt resistor 4 contacts -0 -4 -4 -Resistor_SMD -R_Shunt_Ohmite_LVK20 -4 contacts shunt resistor, https://www.ohmite.com/assets/docs/res_lvk.pdf -4 contacts resistor smd -0 -4 -4 -Resistor_SMD -R_Shunt_Ohmite_LVK24 -4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf -4 contacts resistor smd -0 -4 -4 -Resistor_SMD -R_Shunt_Ohmite_LVK25 -4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf -4 contacts resistor smd -0 -4 -4 -Resistor_SMD -R_Shunt_Vishay_WSK2512_6332Metric_T1.19mm -Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 1.19mm, 5 to 200 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf) -resistor shunt WSK2512 -0 -4 -4 -Resistor_SMD -R_Shunt_Vishay_WSK2512_6332Metric_T2.21mm -Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.21mm, 1 to 4.9 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf) -resistor shunt WSK2512 -0 -4 -4 -Resistor_SMD -R_Shunt_Vishay_WSK2512_6332Metric_T2.66mm -Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.66mm, 0.5 to 0.99 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf) -resistor shunt WSK2512 -0 -4 -4 -Resistor_SMD -R_Shunt_Vishay_WSKW0612 -https://www.vishay.com/docs/30332/wskw0612.pdf -4-Terminal SMD Shunt -0 -4 -4 -Resistor_SMD -R_Shunt_Vishay_WSR2_WSR3 -Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf -SMD Shunt Resistor -0 -2 -2 -Resistor_SMD -R_Shunt_Vishay_WSR2_WSR3_KelvinConnection -Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf -SMD Shunt Resistor -0 -4 -2 -Resistor_THT -R_Array_SIP4 -4-pin Resistor SIP pack -R -0 -4 -4 -Resistor_THT -R_Array_SIP5 -5-pin Resistor SIP pack -R -0 -5 -5 -Resistor_THT -R_Array_SIP6 -6-pin Resistor SIP pack -R -0 -6 -6 -Resistor_THT -R_Array_SIP7 -7-pin Resistor SIP pack -R -0 -7 -7 -Resistor_THT -R_Array_SIP8 -8-pin Resistor SIP pack -R -0 -8 -8 -Resistor_THT -R_Array_SIP9 -9-pin Resistor SIP pack -R -0 -9 -9 -Resistor_THT -R_Array_SIP10 -10-pin Resistor SIP pack -R -0 -10 -10 -Resistor_THT -R_Array_SIP11 -11-pin Resistor SIP pack -R -0 -11 -11 -Resistor_THT -R_Array_SIP12 -12-pin Resistor SIP pack -R -0 -12 -12 -Resistor_THT -R_Array_SIP13 -13-pin Resistor SIP pack -R -0 -13 -13 -Resistor_THT -R_Array_SIP14 -14-pin Resistor SIP pack -R -0 -14 -14 -Resistor_THT -R_Axial_DIN0204_L3.6mm_D1.6mm_P1.90mm_Vertical -Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=1.9mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0204 series Axial Vertical pin pitch 1.9mm 0.167W length 3.6mm diameter 1.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0204_L3.6mm_D1.6mm_P2.54mm_Vertical -Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=2.54mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0204 series Axial Vertical pin pitch 2.54mm 0.167W length 3.6mm diameter 1.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal -Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0204 series Axial Horizontal pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Vertical -Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0204 series Axial Vertical pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal -Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=7.62mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0204 series Axial Horizontal pin pitch 7.62mm 0.167W length 3.6mm diameter 1.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical -Resistor, Axial_DIN0207 series, Axial, Vertical, pin pitch=2.54mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0207 series Axial Vertical pin pitch 2.54mm 0.25W = 1/4W length 6.3mm diameter 2.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0207_L6.3mm_D2.5mm_P5.08mm_Vertical -Resistor, Axial_DIN0207 series, Axial, Vertical, pin pitch=5.08mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0207 series Axial Vertical pin pitch 5.08mm 0.25W = 1/4W length 6.3mm diameter 2.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal -Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=7.62mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0207 series Axial Horizontal pin pitch 7.62mm 0.25W = 1/4W length 6.3mm diameter 2.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal -Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0207_L6.3mm_D2.5mm_P15.24mm_Horizontal -Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=15.24mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0207 series Axial Horizontal pin pitch 15.24mm 0.25W = 1/4W length 6.3mm diameter 2.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0309_L9.0mm_D3.2mm_P2.54mm_Vertical -Resistor, Axial_DIN0309 series, Axial, Vertical, pin pitch=2.54mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0309 series Axial Vertical pin pitch 2.54mm 0.5W = 1/2W length 9mm diameter 3.2mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0309_L9.0mm_D3.2mm_P5.08mm_Vertical -Resistor, Axial_DIN0309 series, Axial, Vertical, pin pitch=5.08mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0309 series Axial Vertical pin pitch 5.08mm 0.5W = 1/2W length 9mm diameter 3.2mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal -Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=12.7mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0309 series Axial Horizontal pin pitch 12.7mm 0.5W = 1/2W length 9mm diameter 3.2mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0309_L9.0mm_D3.2mm_P15.24mm_Horizontal -Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=15.24mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0309 series Axial Horizontal pin pitch 15.24mm 0.5W = 1/2W length 9mm diameter 3.2mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0309_L9.0mm_D3.2mm_P20.32mm_Horizontal -Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=20.32mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0309 series Axial Horizontal pin pitch 20.32mm 0.5W = 1/2W length 9mm diameter 3.2mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0309_L9.0mm_D3.2mm_P25.40mm_Horizontal -Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=25.4mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0309 series Axial Horizontal pin pitch 25.4mm 0.5W = 1/2W length 9mm diameter 3.2mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0411_L9.9mm_D3.6mm_P5.08mm_Vertical -Resistor, Axial_DIN0411 series, Axial, Vertical, pin pitch=5.08mm, 1W, length*diameter=9.9*3.6mm^2 -Resistor Axial_DIN0411 series Axial Vertical pin pitch 5.08mm 1W length 9.9mm diameter 3.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0411_L9.9mm_D3.6mm_P7.62mm_Vertical -Resistor, Axial_DIN0411 series, Axial, Vertical, pin pitch=7.62mm, 1W, length*diameter=9.9*3.6mm^2 -Resistor Axial_DIN0411 series Axial Vertical pin pitch 7.62mm 1W length 9.9mm diameter 3.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0411_L9.9mm_D3.6mm_P12.70mm_Horizontal -Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=12.7mm, 1W, length*diameter=9.9*3.6mm^2 -Resistor Axial_DIN0411 series Axial Horizontal pin pitch 12.7mm 1W length 9.9mm diameter 3.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0411_L9.9mm_D3.6mm_P15.24mm_Horizontal -Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=15.24mm, 1W, length*diameter=9.9*3.6mm^2 -Resistor Axial_DIN0411 series Axial Horizontal pin pitch 15.24mm 1W length 9.9mm diameter 3.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0411_L9.9mm_D3.6mm_P20.32mm_Horizontal -Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=20.32mm, 1W, length*diameter=9.9*3.6mm^2 -Resistor Axial_DIN0411 series Axial Horizontal pin pitch 20.32mm 1W length 9.9mm diameter 3.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0411_L9.9mm_D3.6mm_P25.40mm_Horizontal -Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=25.4mm, 1W, length*diameter=9.9*3.6mm^2 -Resistor Axial_DIN0411 series Axial Horizontal pin pitch 25.4mm 1W length 9.9mm diameter 3.6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0414_L11.9mm_D4.5mm_P5.08mm_Vertical -Resistor, Axial_DIN0414 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0414 series Axial Vertical pin pitch 5.08mm 2W length 11.9mm diameter 4.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0414_L11.9mm_D4.5mm_P7.62mm_Vertical -Resistor, Axial_DIN0414 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0414 series Axial Vertical pin pitch 7.62mm 2W length 11.9mm diameter 4.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0414_L11.9mm_D4.5mm_P15.24mm_Horizontal -Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=15.24mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0414 series Axial Horizontal pin pitch 15.24mm 2W length 11.9mm diameter 4.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0414_L11.9mm_D4.5mm_P20.32mm_Horizontal -Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0414 series Axial Horizontal pin pitch 20.32mm 2W length 11.9mm diameter 4.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0414_L11.9mm_D4.5mm_P25.40mm_Horizontal -Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0414 series Axial Horizontal pin pitch 25.4mm 2W length 11.9mm diameter 4.5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0516_L15.5mm_D5.0mm_P5.08mm_Vertical -Resistor, Axial_DIN0516 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0516 series Axial Vertical pin pitch 5.08mm 2W length 15.5mm diameter 5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0516_L15.5mm_D5.0mm_P7.62mm_Vertical -Resistor, Axial_DIN0516 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0516 series Axial Vertical pin pitch 7.62mm 2W length 15.5mm diameter 5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0516_L15.5mm_D5.0mm_P20.32mm_Horizontal -Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0516 series Axial Horizontal pin pitch 20.32mm 2W length 15.5mm diameter 5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0516_L15.5mm_D5.0mm_P25.40mm_Horizontal -Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0516 series Axial Horizontal pin pitch 25.4mm 2W length 15.5mm diameter 5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0516_L15.5mm_D5.0mm_P30.48mm_Horizontal -Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=30.48mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf -Resistor Axial_DIN0516 series Axial Horizontal pin pitch 30.48mm 2W length 15.5mm diameter 5mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0614_L14.3mm_D5.7mm_P5.08mm_Vertical -Resistor, Axial_DIN0614 series, Axial, Vertical, pin pitch=5.08mm, 1.5W, length*diameter=14.3*5.7mm^2 -Resistor Axial_DIN0614 series Axial Vertical pin pitch 5.08mm 1.5W length 14.3mm diameter 5.7mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0614_L14.3mm_D5.7mm_P7.62mm_Vertical -Resistor, Axial_DIN0614 series, Axial, Vertical, pin pitch=7.62mm, 1.5W, length*diameter=14.3*5.7mm^2 -Resistor Axial_DIN0614 series Axial Vertical pin pitch 7.62mm 1.5W length 14.3mm diameter 5.7mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0614_L14.3mm_D5.7mm_P15.24mm_Horizontal -Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=15.24mm, 1.5W, length*diameter=14.3*5.7mm^2 -Resistor Axial_DIN0614 series Axial Horizontal pin pitch 15.24mm 1.5W length 14.3mm diameter 5.7mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0614_L14.3mm_D5.7mm_P20.32mm_Horizontal -Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=20.32mm, 1.5W, length*diameter=14.3*5.7mm^2 -Resistor Axial_DIN0614 series Axial Horizontal pin pitch 20.32mm 1.5W length 14.3mm diameter 5.7mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0614_L14.3mm_D5.7mm_P25.40mm_Horizontal -Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=25.4mm, 1.5W, length*diameter=14.3*5.7mm^2 -Resistor Axial_DIN0614 series Axial Horizontal pin pitch 25.4mm 1.5W length 14.3mm diameter 5.7mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0617_L17.0mm_D6.0mm_P5.08mm_Vertical -Resistor, Axial_DIN0617 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0617 series Axial Vertical pin pitch 5.08mm 2W length 17mm diameter 6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0617_L17.0mm_D6.0mm_P7.62mm_Vertical -Resistor, Axial_DIN0617 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0617 series Axial Vertical pin pitch 7.62mm 2W length 17mm diameter 6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal -Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0617 series Axial Horizontal pin pitch 20.32mm 2W length 17mm diameter 6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0617_L17.0mm_D6.0mm_P25.40mm_Horizontal -Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0617 series Axial Horizontal pin pitch 25.4mm 2W length 17mm diameter 6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0617_L17.0mm_D6.0mm_P30.48mm_Horizontal -Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=30.48mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0617 series Axial Horizontal pin pitch 30.48mm 2W length 17mm diameter 6mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0918_L18.0mm_D9.0mm_P7.62mm_Vertical -Resistor, Axial_DIN0918 series, Axial, Vertical, pin pitch=7.62mm, 4W, length*diameter=18*9mm^2 -Resistor Axial_DIN0918 series Axial Vertical pin pitch 7.62mm 4W length 18mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0918_L18.0mm_D9.0mm_P22.86mm_Horizontal -Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=22.86mm, 4W, length*diameter=18*9mm^2 -Resistor Axial_DIN0918 series Axial Horizontal pin pitch 22.86mm 4W length 18mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0918_L18.0mm_D9.0mm_P25.40mm_Horizontal -Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=25.4mm, 4W, length*diameter=18*9mm^2 -Resistor Axial_DIN0918 series Axial Horizontal pin pitch 25.4mm 4W length 18mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0918_L18.0mm_D9.0mm_P30.48mm_Horizontal -Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=30.48mm, 4W, length*diameter=18*9mm^2 -Resistor Axial_DIN0918 series Axial Horizontal pin pitch 30.48mm 4W length 18mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0922_L20.0mm_D9.0mm_P7.62mm_Vertical -Resistor, Axial_DIN0922 series, Axial, Vertical, pin pitch=7.62mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0922 series Axial Vertical pin pitch 7.62mm 5W length 20mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0922_L20.0mm_D9.0mm_P25.40mm_Horizontal -Resistor, Axial_DIN0922 series, Axial, Horizontal, pin pitch=25.4mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0922 series Axial Horizontal pin pitch 25.4mm 5W length 20mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_DIN0922_L20.0mm_D9.0mm_P30.48mm_Horizontal -Resistor, Axial_DIN0922 series, Axial, Horizontal, pin pitch=30.48mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf -Resistor Axial_DIN0922 series Axial Horizontal pin pitch 30.48mm 5W length 20mm diameter 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L20.0mm_W6.4mm_P5.08mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=5.08mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 5.08mm 4W length 20mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L20.0mm_W6.4mm_P7.62mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 4W length 20mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L20.0mm_W6.4mm_P22.40mm -Resistor, Axial_Power series, Box, pin pitch=22.4mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 22.4mm 4W length 20mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L20.0mm_W6.4mm_P25.40mm -Resistor, Axial_Power series, Box, pin pitch=25.4mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 25.4mm 4W length 20mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L20.0mm_W6.4mm_P30.48mm -Resistor, Axial_Power series, Box, pin pitch=30.48mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 30.48mm 4W length 20mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L25.0mm_W6.4mm_P27.94mm -Resistor, Axial_Power series, Box, pin pitch=27.94mm, 5W, length*width*height=25*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 27.94mm 5W length 25mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L25.0mm_W6.4mm_P30.48mm -Resistor, Axial_Power series, Box, pin pitch=30.48mm, 5W, length*width*height=25*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 30.48mm 5W length 25mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L25.0mm_W9.0mm_P7.62mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 7W length 25mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L25.0mm_W9.0mm_P10.16mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 7W length 25mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L25.0mm_W9.0mm_P27.94mm -Resistor, Axial_Power series, Box, pin pitch=27.94mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 27.94mm 7W length 25mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L25.0mm_W9.0mm_P30.48mm -Resistor, Axial_Power series, Box, pin pitch=30.48mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 30.48mm 7W length 25mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L38.0mm_W6.4mm_P40.64mm -Resistor, Axial_Power series, Box, pin pitch=40.64mm, 7W, length*width*height=38*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 40.64mm 7W length 38mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L38.0mm_W6.4mm_P45.72mm -Resistor, Axial_Power series, Box, pin pitch=45.72mm, 7W, length*width*height=38*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 45.72mm 7W length 38mm width 6.4mm height 6.4mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L38.0mm_W9.0mm_P40.64mm -Resistor, Axial_Power series, Box, pin pitch=40.64mm, 9W, length*width*height=38*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 40.64mm 9W length 38mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L38.0mm_W9.0mm_P45.72mm -Resistor, Axial_Power series, Box, pin pitch=45.72mm, 9W, length*width*height=38*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 45.72mm 9W length 38mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L48.0mm_W12.5mm_P7.62mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 15W length 48mm width 12.5mm height 12.5mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L48.0mm_W12.5mm_P10.16mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 15W length 48mm width 12.5mm height 12.5mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L48.0mm_W12.5mm_P55.88mm -Resistor, Axial_Power series, Box, pin pitch=55.88mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 55.88mm 15W length 48mm width 12.5mm height 12.5mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L48.0mm_W12.5mm_P60.96mm -Resistor, Axial_Power series, Box, pin pitch=60.96mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 60.96mm 15W length 48mm width 12.5mm height 12.5mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L50.0mm_W9.0mm_P55.88mm -Resistor, Axial_Power series, Box, pin pitch=55.88mm, 11W, length*width*height=50*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 55.88mm 11W length 50mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L50.0mm_W9.0mm_P60.96mm -Resistor, Axial_Power series, Box, pin pitch=60.96mm, 11W, length*width*height=50*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 60.96mm 11W length 50mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L60.0mm_W14.0mm_P10.16mm_Vertical -Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 25W length 60mm width 14mm height 14mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L60.0mm_W14.0mm_P66.04mm -Resistor, Axial_Power series, Box, pin pitch=66.04mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 66.04mm 25W length 60mm width 14mm height 14mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L60.0mm_W14.0mm_P71.12mm -Resistor, Axial_Power series, Box, pin pitch=71.12mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 71.12mm 25W length 60mm width 14mm height 14mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L75.0mm_W9.0mm_P81.28mm -Resistor, Axial_Power series, Box, pin pitch=81.28mm, 17W, length*width*height=75*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 81.28mm 17W length 75mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Power_L75.0mm_W9.0mm_P86.36mm -Resistor, Axial_Power series, Box, pin pitch=86.36mm, 17W, length*width*height=75*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf -Resistor Axial_Power series Box pin pitch 86.36mm 17W length 75mm width 9mm height 9mm -0 -2 -2 -Resistor_THT -R_Axial_Shunt_L22.2mm_W8.0mm_PS14.30mm_P25.40mm -Resistor, Axial_Shunt series, Box, pin pitch=25.4mm, 3W, length*width*height=22.2*8*8mm^3, shunt pin pitch = 14.30mm, http://www.vishay.com/docs/30217/cpsl.pdf -Resistor Axial_Shunt series Box pin pitch 25.4mm 3W length 22.2mm width 8mm height 8mm shunt pin pitch 14.30mm -0 -4 -4 -Resistor_THT -R_Axial_Shunt_L22.2mm_W9.5mm_PS14.30mm_P25.40mm -Resistor, Axial_Shunt series, Box, pin pitch=25.4mm, 5W, length*width*height=22.2*9.5*9.5mm^3, shunt pin pitch = 14.30mm, http://www.vishay.com/docs/30217/cpsl.pdf -Resistor Axial_Shunt series Box pin pitch 25.4mm 5W length 22.2mm width 9.5mm height 9.5mm shunt pin pitch 14.30mm -0 -4 -4 -Resistor_THT -R_Axial_Shunt_L35.3mm_W9.5mm_PS25.40mm_P38.10mm -Resistor, Axial_Shunt series, Box, pin pitch=38.1mm, 7W, length*width*height=35.3*9.5*9.5mm^3, shunt pin pitch = 25.40mm, http://www.vishay.com/docs/30217/cpsl.pdf -Resistor Axial_Shunt series Box pin pitch 38.1mm 7W length 35.3mm width 9.5mm height 9.5mm shunt pin pitch 25.40mm -0 -4 -4 -Resistor_THT -R_Axial_Shunt_L47.6mm_W9.5mm_PS34.93mm_P50.80mm -Resistor, Axial_Shunt series, Box, pin pitch=50.8mm, 10W, length*width*height=47.6*9.5*9.5mm^3, shunt pin pitch = 34.93mm, http://www.vishay.com/docs/30217/cpsl.pdf -Resistor Axial_Shunt series Box pin pitch 50.8mm 10W length 47.6mm width 9.5mm height 9.5mm shunt pin pitch 34.93mm -0 -4 -4 -Resistor_THT -R_Axial_Shunt_L47.6mm_W12.7mm_PS34.93mm_P50.80mm -Resistor, Axial_Shunt series, Box, pin pitch=50.8mm, 15W, length*width*height=47.6*12.7*12.7mm^3, shunt pin pitch = 34.93mm, http://www.vishay.com/docs/30217/cpsl.pdf -Resistor Axial_Shunt series Box pin pitch 50.8mm 15W length 47.6mm width 12.7mm height 12.7mm shunt pin pitch 34.93mm -0 -4 -4 -Resistor_THT -R_Bare_Metal_Element_L12.4mm_W4.8mm_P11.40mm -Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=11.4mm, 1W, length*width=12.4*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf -Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 11.4mm 1W length 12.4mm width 4.8mm -0 -2 -2 -Resistor_THT -R_Bare_Metal_Element_L16.3mm_W4.8mm_P15.30mm -Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=15.3mm, 3W, length*width=16.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf -Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 15.3mm 3W length 16.3mm width 4.8mm -0 -2 -2 -Resistor_THT -R_Bare_Metal_Element_L21.3mm_W4.8mm_P20.30mm -Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=20.3mm, 5W, length*width=21.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf -Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 20.3mm 5W length 21.3mm width 4.8mm -0 -2 -2 -Resistor_THT -R_Box_L8.4mm_W2.5mm_P5.08mm -Resistor, Box series, Radial, pin pitch=5.08mm, 0.5W = 1/2W, length*width=8.38*2.54mm^2, http://www.vishay.com/docs/60051/cns020.pdf -Resistor Box series Radial pin pitch 5.08mm 0.5W = 1/2W length 8.38mm width 2.54mm -0 -2 -2 -Resistor_THT -R_Box_L13.0mm_W4.0mm_P9.00mm -Resistor, Box series, Radial, pin pitch=9.00mm, 2W, length*width=13.0*4.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf -Resistor Box series Radial pin pitch 9.00mm 2W length 13.0mm width 4.0mm -0 -2 -2 -Resistor_THT -R_Box_L14.0mm_W5.0mm_P9.00mm -Resistor, Box series, Radial, pin pitch=9.00mm, 5W, length*width=14.0*5.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf -Resistor Box series Radial pin pitch 9.00mm 5W length 14.0mm width 5.0mm -0 -2 -2 -Resistor_THT -R_Box_L26.0mm_W5.0mm_P20.00mm -Resistor, Box series, Radial, pin pitch=20.00mm, 10W, length*width=26.0*5.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf -Resistor Box series Radial pin pitch 20.00mm 10W length 26.0mm width 5.0mm -0 -2 -2 -Resistor_THT -R_Radial_Power_L7.0mm_W8.0mm_Px2.40mm_Py2.30mm -Resistor, Radial_Power series, Radial, pin pitch=2.40*2.30mm^2, 7W, length*width=7*8mm^2, http://www.vitrohm.com/content/files/vitrohm_series_kv_-_201601.pdf -Resistor Radial_Power series Radial pin pitch 2.40*2.30mm^2 7W length 7mm width 8mm -0 -2 -2 -Resistor_THT -R_Radial_Power_L9.0mm_W10.0mm_Px2.70mm_Py2.30mm -Resistor, Radial_Power series, Radial, pin pitch=2.70*2.30mm^2, 17W, length*width=9*10mm^2, http://www.vitrohm.com/content/files/vitrohm_series_kv_-_201601.pdf -Resistor Radial_Power series Radial pin pitch 2.70*2.30mm^2 17W length 9mm width 10mm -0 -2 -2 -Resistor_THT -R_Radial_Power_L11.0mm_W7.0mm_P5.00mm -Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 2W, length*width=11.0*7.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf -Resistor Radial_Power series Radial pin pitch 5.00mm 2W length 11.0mm width 7.0mm -0 -2 -2 -Resistor_THT -R_Radial_Power_L12.0mm_W8.0mm_P5.00mm -Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 3W, length*width=12.0*8.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf -Resistor Radial_Power series Radial pin pitch 5.00mm 3W length 12.0mm width 8.0mm -0 -2 -2 -Resistor_THT -R_Radial_Power_L13.0mm_W9.0mm_P5.00mm -Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 7W, length*width=13.0*9.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf -Resistor Radial_Power series Radial pin pitch 5.00mm 7W length 13.0mm width 9.0mm -0 -2 -2 -Resistor_THT -R_Radial_Power_L16.1mm_W9.0mm_P7.37mm -Resistor, Radial_Power series, Radial, pin pitch=7.37mm, 10W, length*width=16.1*9mm^2, http://www.vishay.com/docs/30218/cpcx.pdf -Resistor Radial_Power series Radial pin pitch 7.37mm 10W length 16.1mm width 9mm -0 -2 -2 -Rotary_Encoder -RotaryEncoder_Alps_EC11E-Switch_Vertical_H20mm -Alps rotary encoder, EC12E... with switch, vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html -rotary encoder -0 -7 -6 -Rotary_Encoder -RotaryEncoder_Alps_EC11E-Switch_Vertical_H20mm_CircularMountingHoles -Alps rotary encoder, EC12E... with switch, vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html -rotary encoder -0 -7 -6 -Rotary_Encoder -RotaryEncoder_Alps_EC11E_Vertical_H20mm -Alps rotary encoder, EC12E... without switch (pins are dummy), vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html -rotary encoder -0 -7 -4 -Rotary_Encoder -RotaryEncoder_Alps_EC11E_Vertical_H20mm_CircularMountingHoles -Alps rotary encoder, EC12E... without switch (pins are dummy), vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html -rotary encoder -0 -7 -4 -Rotary_Encoder -RotaryEncoder_Alps_EC12E-Switch_Vertical_H20mm -Alps rotary encoder, EC12E... with switch, vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html & http://cdn-reichelt.de/documents/datenblatt/F100/402097STEC12E08.PDF -rotary encoder -0 -7 -6 -Rotary_Encoder -RotaryEncoder_Alps_EC12E-Switch_Vertical_H20mm_CircularMountingHoles -Alps rotary encoder, EC12E... with switch, vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html & http://cdn-reichelt.de/documents/datenblatt/F100/402097STEC12E08.PDF -rotary encoder -0 -7 -6 -Rotary_Encoder -RotaryEncoder_Alps_EC12E_Vertical_H20mm -Alps rotary encoder, EC12E..., vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html -rotary encoder -0 -5 -4 -Rotary_Encoder -RotaryEncoder_Alps_EC12E_Vertical_H20mm_CircularMountingHoles -Alps rotary encoder, EC12E..., vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html -rotary encoder -0 -5 -4 -Sensor -Aosong_DHT11_5.5x12.0_P2.54mm -Temperature and humidity module, http://akizukidenshi.com/download/ds/aosong/DHT11.pdf -Temperature and humidity module -0 -4 -4 -Sensor -MQ-6 -Gas Sensor, 6 pin, https://www.winsen-sensor.com/d/files/semiconductor/mq-6.pdf -gas sensor -0 -6 -6 -Sensor -SHT1x -SHT1x -SHT1x -0 -8 -8 -Sensor_Audio -Infineon_PG-LLGA-5-1 -Infineon_PG-LLGA-5-1 StepUp generated footprint, https://www.infineon.com/cms/en/product/packages/PG-LLGA/PG-LLGA-5-1/ -infineon mems microphone -0 -15 -5 -Sensor_Audio -ST_HLGA-6_3.76x4.72mm_P1.65mm -http://www.st.com/content/ccc/resource/technical/document/datasheet/group3/27/62/48/98/44/54/4d/36/DM00303211/files/DM00303211.pdf/jcr:content/translations/en.DM00303211.pdf -HLGA Sensor Audio -0 -6 -6 -Sensor_Current -AKM_CQ_7 -AKM Current Sensor, 7 pin, THT (http://www.akm.com/akm/en/file/datasheet/CQ-236B.pdf) -akm current sensor tht -0 -39 -7 -Sensor_Current -AKM_CQ_7S -AKM Current Sensor, 7 pin, SMD (http://www.akm.com/akm/en/file/datasheet/CQ-236B.pdf) -akm current sensor smd -0 -19 -7 -Sensor_Current -AKM_CQ_VSOP-24_5.6x7.9mm_P0.65mm -AKM VSOP-24 current sensor, 5.6x7.9mm body, 0.65mm pitch (http://www.akm.com/akm/en/file/datasheet/CQ-330J.pdf) -akm vsop 24 -0 -10 -10 -Sensor_Current -AKM_CZ_SSOP-10_6.5x8.1mm_P0.95mm -AKM CZ-381x current sensor, 6.5x8.1mm body, 0.95mm pitch (http://www.akm.com/akm/en/product/detail/0009/) -akm cz-381x 10 -0 -10 -10 -Sensor_Current -Allegro_CB_PFF -Allegro MicroSystems, CB-PFF Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) !PADS 4-5 DO NOT MATCH DATASHEET! -Allegro CB-PFF -0 -37 -5 -Sensor_Current -Allegro_CB_PSF -Allegro MicroSystems, CB-PSF Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) -Allegro CB-PSF -0 -5 -5 -Sensor_Current -Allegro_CB_PSS -Allegro MicroSystems, CB-PSS Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) -Allegro CB-PSS -0 -5 -5 -Sensor_Current -Allegro_PSOF-7_4.8x6.4mm_P1.60mm -Allegro Microsystems PSOF-7, 4.8x6.4mm Body, 1.60mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS780-Datasheet.ashx) -Allegro PSOF-7 -0 -7 -7 -Sensor_Current -Allegro_QFN-12-10-1EP_3x3mm_P0.5mm -Allegro Microsystems 12-Lead (10-Lead Populated) Quad Flat Pack, 3x3mm Body, 0.5mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS711-Datasheet.ashx) -Allegro QFN 0.5 -0 -14 -10 -Sensor_Current -Allegro_QSOP-24_3.9x8.7mm_P0.635mm -Allegro Microsystems 24-Lead Plastic Shrink Small Outline Narrow Body Body [QSOP] (http://www.allegromicro.com/~/media/Files/Datasheets/ACS726-Datasheet.ashx?la=en) -Allegro QSOP 0.635 -0 -24 -24 -Sensor_Current -Allegro_SIP-3 -Allegro Microsystems SIP-3, 1.27mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/A1369-Datasheet.ashx) -Allegro SIP-3 -0 -3 -3 -Sensor_Current -Allegro_SIP-4 -Allegro Microsystems SIP-4, 1.27mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/A1363-Datasheet.ashx) -Allegro SIP-4 -0 -4 -4 -Sensor_Current -Diodes_SIP-3_4.1x1.5mm_P1.27mm -Diodes SIP-3 Bulk Pack, 1.27mm Pitch (https://www.diodes.com/assets/Package-Files/SIP-3-Bulk-Pack.pdf) -Diodes SIP-3 Bulk Pack -0 -3 -3 -Sensor_Current -Diodes_SIP-3_4.1x1.5mm_P2.65mm -Diodes SIP-3 Ammo Pack, 2.65mm Pitch (https://www.diodes.com/assets/Package-Files/SIP-3-Ammo-Pack.pdf) -Diodes SIP-3 Ammo Pack -0 -3 -3 -Sensor_Current -Honeywell_CSLW -https://sensing.honeywell.com/honeywell-sensing-cslw-series-product-sheet-005861-1-en.pdf -Miniature Wired Open-Loop Current Sensor -0 -5 -5 -Sensor_Current -LEM_HO8-NP -LEM HO 8/15/25-NP Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-np-0000_series.pdf) -current transducer -0 -13 -13 -Sensor_Current -LEM_HO8-NSM -LEM HO 8/15/25-NSM Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-nsm-0000_series.pdf) -current transducer -0 -13 -13 -Sensor_Current -LEM_HO40-NP -LEM HO 40/60/120/150-NP Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-np_0100__1100_series.pdf) -current transducer -0 -13 -13 -Sensor_Current -LEM_HTFS -LEM HTFS x00-P current transducer (https://www.lem.com/sites/default/files/products_datasheets/htfs_200_800-p.pdf) -HTFS current transducer -0 -4 -4 -Sensor_Current -LEM_HX02-P -LEM HX02-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX03-P-SP2 -LEM HX03-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX04-P -LEM HX04-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX05-NP -LEM HX05-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf) -hall current -0 -8 -8 -Sensor_Current -LEM_HX05-P-SP2 -LEM HX05-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX06-P -LEM HX06-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX10-NP -LEM HX10-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf) -hall current -0 -8 -8 -Sensor_Current -LEM_HX10-P-SP2 -LEM HX10-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX15-NP -LEM HX15-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf) -hall current -0 -8 -8 -Sensor_Current -LEM_HX15-P-SP2 -LEM HX15-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX20-P-SP2 -LEM HX20-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX25-P-SP2 -LEM HX25-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_HX50-P-SP2 -LEM HX50-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) -hall current -0 -6 -6 -Sensor_Current -LEM_LA25-P -LEM Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/la_25-p.pdf) -current transducer -0 -3 -3 -Sensor_Current -LEM_LTSR-NP -LEM current transducer LEM_LTSR-NP 5V supply voltage series https://www.lem.com/sites/default/files/products_datasheets/ltsr_6-np.pdf -Current transducer -0 -10 -10 -Sensor_Motion -InvenSense_QFN-24_3x3mm_P0.4mm -24-Lead Plastic QFN (3mm x 3mm); Pitch 0.4mm; EP 1.7x1.54mm; for InvenSense motion sensors; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU9250REV1.0.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) -QFN 0.4 -0 -24 -24 -Sensor_Motion -InvenSense_QFN-24_3x3mm_P0.4mm_NoMask -24-Lead Plastic QFN (3mm x 3mm); Pitch 0.4mm; EP 1.7x1.54mm; for InvenSense motion sensors; Mask removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU9250REV1.0.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) -QFN 0.4 -0 -25 -24 -Sensor_Motion -InvenSense_QFN-24_4x4mm_P0.5mm -24-Lead Plastic QFN (4mm x 4mm); Pitch 0.5mm; EP 2.7x2.6mm; for InvenSense motion sensors; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) -QFN 0.5 -0 -24 -24 -Sensor_Motion -InvenSense_QFN-24_4x4mm_P0.5mm_NoMask -24-Lead Plastic QFN (4mm x 4mm); Pitch 0.5mm; EP 2.7x2.6mm; for InvenSense motion sensors; Mask removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) -QFN 0.5 -0 -25 -24 -Sensor_Pressure -Freescale_98ARH99066A -https://www.nxp.com/docs/en/data-sheet/MPXH6250A.pdf -sensor pressure ssop 98ARH99066A -0 -8 -8 -Sensor_Pressure -Freescale_98ARH99089A -https://www.nxp.com/docs/en/data-sheet/MPXH6250A.pdf -sensor pressure ssop 98ARH99089A -0 -8 -8 -Sensor_Pressure -Honeywell_40PCxxxG1A -https://www.honeywellscportal.com/index.php?ci_id=138832 -pressure sensor automotive honeywell -0 -3 -3 -Sensor_Voltage -LEM_LV25-P -LEM LV25-P Voltage transducer, https://www.lem.com/sites/default/files/products_datasheets/lv_25-p.pdf -LEM Hall Effect Voltage transducer -0 -5 -5 -Socket -3M_Textool_240-1288-00-0602J_2x20_P2.54mm -3M 40-pin zero insertion force socket, though-hole, row spacing 25.4 mm (1000 mils) -THT DIP DIL ZIF 25.4mm 1000mil Socket -0 -40 -40 -Socket -DIP_Socket-14_W4.3_W5.08_W7.62_W10.16_W10.9_3M_214-3339-00-0602J -3M 14-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 7.62mm 300mil Socket -0 -14 -14 -Socket -DIP_Socket-16_W4.3_W5.08_W7.62_W10.16_W10.9_3M_216-3340-00-0602J -3M 16-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 7.62mm 300mil Socket -0 -16 -16 -Socket -DIP_Socket-18_W4.3_W5.08_W7.62_W10.16_W10.9_3M_218-3341-00-0602J -3M 18-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 7.62mm 300mil Socket -0 -18 -18 -Socket -DIP_Socket-20_W4.3_W5.08_W7.62_W10.16_W10.9_3M_220-3342-00-0602J -3M 20-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 7.62mm 300mil Socket -0 -20 -20 -Socket -DIP_Socket-22_W6.9_W7.62_W10.16_W12.7_W13.5_3M_222-3343-00-0602J -3M 22-pin zero insertion force socket, through-hole, row spacing 10.16 mm (400 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 10.16mm 400mil Socket -0 -22 -22 -Socket -DIP_Socket-24_W4.3_W5.08_W7.62_W10.16_W10.9_3M_224-5248-00-0602J -3M 24-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 7.62mm 300mil Socket -0 -24 -24 -Socket -DIP_Socket-24_W11.9_W12.7_W15.24_W17.78_W18.5_3M_224-1275-00-0602J -3M 24-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 15.24mm 600mil Socket -0 -24 -24 -Socket -DIP_Socket-28_W6.9_W7.62_W10.16_W12.7_W13.5_3M_228-4817-00-0602J -3M 28-pin zero insertion force socket, through-hole, row spacing 10.16 mm (400 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 10.16mm 400mil Socket -0 -28 -28 -Socket -DIP_Socket-28_W11.9_W12.7_W15.24_W17.78_W18.5_3M_228-1277-00-0602J -3M 28-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 15.24mm 600mil Socket -0 -28 -28 -Socket -DIP_Socket-32_W11.9_W12.7_W15.24_W17.78_W18.5_3M_232-1285-00-0602J -3M 32-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 15.24mm 600mil Socket -0 -32 -32 -Socket -DIP_Socket-40_W11.9_W12.7_W15.24_W17.78_W18.5_3M_240-1280-00-0602J -3M 40-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 15.24mm 600mil Socket -0 -40 -40 -Socket -DIP_Socket-40_W22.1_W22.86_W25.4_W27.94_W28.7_3M_240-3639-00-0602J -3M 40-pin zero insertion force socket, through-hole, row spacing 25.4 mm (1000 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 25.4mm 1000mil Socket -0 -40 -40 -Socket -DIP_Socket-42_W11.9_W12.7_W15.24_W17.78_W18.5_3M_242-1281-00-0602J -3M 42-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf -THT DIP DIL ZIF 15.24mm 600mil Socket -0 -42 -42 -Socket -Wells_648-0482211SA01 -https://www.farnell.com/cad/316865.pdf?_ga=2.37208032.177107060.1530611323-249019997.1498114824 -48pin TSOP Socket -0 -48 -48 -Symbol -CE-Logo_8.5x6mm_SilkScreen -CE marking -Logo CE certification -0 -0 -0 -Symbol -CE-Logo_11.2x8mm_SilkScreen -CE marking -Logo CE certification -0 -0 -0 -Symbol -CE-Logo_16.8x12mm_SilkScreen -CE marking -Logo CE certification -0 -0 -0 -Symbol -CE-Logo_28x20mm_SilkScreen -CE marking -Logo CE certification -0 -0 -0 -Symbol -CE-Logo_42x30mm_SilkScreen -CE marking -Logo CE certification -0 -0 -0 -Symbol -CE-Logo_56.1x40mm_SilkScreen -CE marking -Logo CE certification -0 -0 -0 -Symbol -ESD-Logo_6.6x6mm_SilkScreen -Electrostatic discharge Logo -Logo ESD -0 -0 -0 -Symbol -ESD-Logo_8.9x8mm_SilkScreen -Electrostatic discharge Logo -Logo ESD -0 -0 -0 -Symbol -ESD-Logo_13.2x12mm_SilkScreen -Electrostatic discharge Logo -Logo ESD -0 -0 -0 -Symbol -ESD-Logo_22x20mm_SilkScreen -Electrostatic discharge Logo -Logo ESD -0 -0 -0 -Symbol -ESD-Logo_33x30mm_SilkScreen -Electrostatic discharge Logo -Logo ESD -0 -0 -0 -Symbol -ESD-Logo_44.1x40mm_SilkScreen -Electrostatic discharge Logo -Logo ESD -0 -0 -0 -Symbol -FCC-Logo_7.3x6mm_SilkScreen -FCC marking -Logo FCC certification -0 -0 -0 -Symbol -FCC-Logo_9.6x8mm_SilkScreen -FCC marking -Logo FCC certification -0 -0 -0 -Symbol -FCC-Logo_14.6x12mm_SilkScreen -FCC marking -Logo FCC certification -0 -0 -0 -Symbol -FCC-Logo_24.2x20mm_SilkScreen -FCC marking -Logo FCC certification -0 -0 -0 -Symbol -FCC-Logo_36.3x30mm_SilkScreen -FCC marking -Logo FCC certification -0 -0 -0 -Symbol -FCC-Logo_48.3x40mm_SilkScreen -FCC marking -Logo FCC certification -0 -0 -0 -Symbol -KiCad-Logo2_5mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_5mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_6mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_6mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_8mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_8mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_12mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_12mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_20mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_20mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_30mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_30mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_40mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo2_40mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_5mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_5mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_6mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_6mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_8mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_8mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_12mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_12mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_20mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_20mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_30mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_30mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_40mm_Copper -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -KiCad-Logo_40mm_SilkScreen -KiCad Logo -Logo KiCad -0 -0 -0 -Symbol -OSHW-Logo2_7.3x6mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_7.3x6mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_9.8x8mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_9.8x8mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_14.6x12mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_14.6x12mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_24.3x20mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_24.3x20mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_36.5x30mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_36.5x30mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_48.7x40mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo2_48.7x40mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Logo_5.7x6mm_Copper -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_5.7x6mm_SilkScreen -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_7.5x8mm_Copper -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_7.5x8mm_SilkScreen -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_11.4x12mm_Copper -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_11.4x12mm_SilkScreen -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_19x20mm_Copper -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_19x20mm_SilkScreen -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_28.5x30mm_Copper -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_28.5x30mm_SilkScreen -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_38.1x40mm_Copper -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Logo_38.1x40mm_SilkScreen -Open Source Hardware Logo -Logo OSHW -0 -0 -0 -Symbol -OSHW-Symbol_6.7x6mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_6.7x6mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_8.9x8mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_8.9x8mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_13.4x12mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_13.4x12mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_22.3x20mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_22.3x20mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_33.5x30mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_33.5x30mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_44.5x40mm_Copper -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -OSHW-Symbol_44.5x40mm_SilkScreen -Open Source Hardware Symbol -Logo Symbol OSHW -0 -0 -0 -Symbol -Polarity_Center_Negative_6mm_SilkScreen -Polarity Logo, Center Negative -Logo Polarity Center Negative -0 -0 -0 -Symbol -Polarity_Center_Negative_8mm_SilkScreen -Polarity Logo, Center Negative -Logo Polarity Center Negative -0 -0 -0 -Symbol -Polarity_Center_Negative_12mm_SilkScreen -Polarity Logo, Center Negative -Logo Polarity Center Negative -0 -0 -0 -Symbol -Polarity_Center_Negative_20mm_SilkScreen -Polarity Logo, Center Negative -Logo Polarity Center Negative -0 -0 -0 -Symbol -Polarity_Center_Negative_30mm_SilkScreen -Polarity Logo, Center Negative -Logo Polarity Center Negative -0 -0 -0 -Symbol -Polarity_Center_Negative_40mm_SilkScreen -Polarity Logo, Center Negative -Logo Polarity Center Negative -0 -0 -0 -Symbol -Polarity_Center_Positive_6mm_SilkScreen -Polarity Logo, Center Positive -Logo Polarity Center Positive -0 -0 -0 -Symbol -Polarity_Center_Positive_8mm_SilkScreen -Polarity Logo, Center Positive -Logo Polarity Center Positive -0 -0 -0 -Symbol -Polarity_Center_Positive_12mm_SilkScreen -Polarity Logo, Center Positive -Logo Polarity Center Positive -0 -0 -0 -Symbol -Polarity_Center_Positive_20mm_SilkScreen -Polarity Logo, Center Positive -Logo Polarity Center Positive -0 -0 -0 -Symbol -Polarity_Center_Positive_30mm_SilkScreen -Polarity Logo, Center Positive -Logo Polarity Center Positive -0 -0 -0 -Symbol -Polarity_Center_Positive_40mm_SilkScreen -Polarity Logo, Center Positive -Logo Polarity Center Positive -0 -0 -0 -Symbol -RoHS-Logo_6mm_SilkScreen -Restriction of Hazardous Substances Directive Logo -Logo RoHS -0 -0 -0 -Symbol -RoHS-Logo_8mm_SilkScreen -Restriction of Hazardous Substances Directive Logo -Logo RoHS -0 -0 -0 -Symbol -RoHS-Logo_12mm_SilkScreen -Restriction of Hazardous Substances Directive Logo -Logo RoHS -0 -0 -0 -Symbol -RoHS-Logo_20mm_SilkScreen -Restriction of Hazardous Substances Directive Logo -Logo RoHS -0 -0 -0 -Symbol -RoHS-Logo_30mm_SilkScreen -Restriction of Hazardous Substances Directive Logo -Logo RoHS -0 -0 -0 -Symbol -RoHS-Logo_40mm_SilkScreen -Restriction of Hazardous Substances Directive Logo -Logo RoHS -0 -0 -0 -Symbol -Symbol_Attention_CopperTop_Big -Symbol, Attention, Copper Top, Big, -Symbol, Attention, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_Attention_CopperTop_Small -Symbol, Attention, Copper Top, Small, -Symbol, Attention, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_Barrel_Polarity -Barrel connector polarity indicator -barrel polarity -0 -0 -0 -Symbol -Symbol_CC-Attribution_CopperTop_Big -Symbol, CC-Attribution, Copper Top, Big, -Symbol, CC-Attribution, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_CC-Attribution_CopperTop_Small -Symbol, CC-Share Alike, Copper Top, Small, -Symbol, CC-Share Alike, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_CC-Noncommercial_CopperTop_Big -Symbol, CC-Noncommercial, Copper Top, Big, -Symbol, CC-Noncommercial, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_CC-Noncommercial_CopperTop_Small -Symbol, CC-Noncommercial Alike, Copper Top, Small, -Symbol, CC-Noncommercial Alike, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_CC-PublicDomain_CopperTop_Big -Symbol, CC-PublicDomain, Copper Top, Big, -Symbol, CC-PublicDomain, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_CC-PublicDomain_CopperTop_Small -Symbol, CC-Public Domain, Copper Top, Small, -Symbol, CC-Public Domain, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_CC-PublicDomain_SilkScreenTop_Big -Symbol, CC-PublicDomain, SilkScreen Top, Big, -Symbol, CC-PublicDomain, SilkScreen Top, Big, -0 -0 -0 -Symbol -Symbol_CC-ShareAlike_CopperTop_Big -Symbol, CC-Share Alike, Copper Top, Big, -Symbol, CC-Share Alike, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_CC-ShareAlike_CopperTop_Small -Symbol, CC-Share Alike, Copper Top, Small, -Symbol, CC-Share Alike, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_CreativeCommonsPublicDomain_CopperTop_Small -Symbol, Creative Commons Public Domain, CopperTop, Small, -Symbol, Creative Commons Public Domain, CopperTop, Small, -0 -0 -0 -Symbol -Symbol_CreativeCommonsPublicDomain_SilkScreenTop_Small -Symbol, Creative Commons Public Domain, SilkScreenTop, Small, -Symbol, Creative Commons Public Domain, SilkScreen Top, Small, -0 -0 -0 -Symbol -Symbol_CreativeCommons_CopperTop_Type1_Big -Symbol, Creative Commons, CopperTop, Type 1, Big, -Symbol, Creative Commons, CopperTop, Type 1, Big, -0 -0 -0 -Symbol -Symbol_CreativeCommons_CopperTop_Type2_Big -Symbol, Creative Commons, CopperTop, Type 2, Big, -Symbol, Creative Commons, CopperTop, Type 2, Big, -0 -0 -0 -Symbol -Symbol_CreativeCommons_CopperTop_Type2_Small -Symbol, Creative Commons, CopperTop, Type 2, Small, -Symbol, Creative Commons, CopperTop, Type 2, Small, -0 -0 -0 -Symbol -Symbol_CreativeCommons_SilkScreenTop_Type2_Big -Symbol, Creative Commons, SilkScreen Top, Type 2, Big, -Symbol, Creative Commons, SilkScreen Top, Type 2, Big, -0 -0 -0 -Symbol -Symbol_Danger_CopperTop_Big -Symbol, Danger, CopperTop, Big, -Symbol, Danger, CopperTop, Big, -0 -0 -0 -Symbol -Symbol_Danger_CopperTop_Small -Symbol, Danger, Copper Top, Small, -Symbol, Danger, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_ESD-Logo-Text_CopperTop - - -0 -0 -0 -Symbol -Symbol_ESD-Logo_CopperTop -ESD-Logo, similar JEDEC-14, without text, ohne Text, Copper Top, -ESD-Logo, similar JEDEC-14, without text, ohne Text, Copper Top, -0 -0 -0 -Symbol -Symbol_GNU-GPL_CopperTop_Big -Symbol, GNU-GPL, Copper Top, Big, -Symbol, GNU-GPL, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_GNU-GPL_CopperTop_Small -Symbol, GNU-GPL, Copper Top, Small, -Symbol, GNU-GPL, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_GNU-Logo_CopperTop -GNU-Logo, GNU-Head, GNU-Kopf, Copper Top, -GNU-Logo, GNU-Head, GNU-Kopf, Copper Top, -0 -0 -0 -Symbol -Symbol_GNU-Logo_SilkscreenTop -GNU-Logo, GNU-Head, GNU-Kopf, Silkscreen, -GNU-Logo, GNU-Head, GNU-Kopf, Silkscreen, -0 -0 -0 -Symbol -Symbol_HighVoltage_Type1_CopperTop_Big -Symbol, HighVoltage, Type1, Copper Top, Big, -Symbol, HighVoltage, Type1, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_HighVoltage_Type2_CopperTop_Big -Symbol, HighVoltage, Type2, Copper Top, Big, -Symbol, HighVoltage, Type2, Copper Top, Big, -0 -0 -0 -Symbol -Symbol_HighVoltage_Type2_CopperTop_VerySmall -Symbol, High Voltage, Type 2, Copper Top, Very Small, -Symbol, High Voltage, Type 2, Copper Top, Very Small, -0 -0 -0 -Symbol -Symbol_Highvoltage_Type1_CopperTop_Small -Symbol, Highvoltage, Type 1, Copper Top, Small, -Symbol, Highvoltage, Type 1, Copper Top, Small, -0 -0 -0 -Symbol -Symbol_Highvoltage_Type2_CopperTop_Small -Symbol, Highvoltage, Type 2, Copper Top, Small, -Symbol, Highvoltage, Type 2, Copper Top, Small, -0 -0 -0 -Symbol -WEEE-Logo_4.2x6mm_SilkScreen -Waste Electrical and Electronic Equipment Directive -Logo WEEE -0 -0 -0 -Symbol -WEEE-Logo_5.6x8mm_SilkScreen -Waste Electrical and Electronic Equipment Directive -Logo WEEE -0 -0 -0 -Symbol -WEEE-Logo_8.4x12mm_SilkScreen -Waste Electrical and Electronic Equipment Directive -Logo WEEE -0 -0 -0 -Symbol -WEEE-Logo_14x20mm_SilkScreen -Waste Electrical and Electronic Equipment Directive -Logo WEEE -0 -0 -0 -Symbol -WEEE-Logo_21x30mm_SilkScreen -Waste Electrical and Electronic Equipment Directive -Logo WEEE -0 -0 -0 -Symbol -WEEE-Logo_28.1x40mm_SilkScreen -Waste Electrical and Electronic Equipment Directive -Logo WEEE -0 -0 -0 -TerminalBlock -TerminalBlock_Altech_AK300-2_P5.00mm -Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf -Altech AK300 terminal block pitch 5.0mm -0 -2 -2 -TerminalBlock -TerminalBlock_Altech_AK300-3_P5.00mm -Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf -Altech AK300 terminal block pitch 5.0mm -0 -3 -3 -TerminalBlock -TerminalBlock_Altech_AK300-4_P5.00mm -Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf -Altech AK300 terminal block pitch 5.0mm -0 -4 -4 -TerminalBlock -TerminalBlock_Wuerth_691311400102_P7.62mm -https://katalog.we-online.de/em/datasheet/6913114001xx.pdf -Wuerth WR-TBL Series 3114 terminal block pitch 7.62mm -0 -2 -2 -TerminalBlock -TerminalBlock_bornier-2_P5.08mm -simple 2-pin terminal block, pitch 5.08mm, revamped version of bornier2 -terminal block bornier2 -0 -2 -2 -TerminalBlock -TerminalBlock_bornier-3_P5.08mm -simple 3-pin terminal block, pitch 5.08mm, revamped version of bornier3 -terminal block bornier3 -0 -3 -3 -TerminalBlock -TerminalBlock_bornier-4_P5.08mm -simple 4-pin terminal block, pitch 5.08mm, revamped version of bornier4 -terminal block bornier4 -0 -4 -4 -TerminalBlock -TerminalBlock_bornier-5_P5.08mm -simple 5-pin terminal block, pitch 5.08mm, revamped version of bornier5 -terminal block bornier5 -0 -5 -5 -TerminalBlock -TerminalBlock_bornier-6_P5.08mm -simple 6pin terminal block, pitch 5.08mm, revamped version of bornier6 -terminal block bornier6 -0 -6 -6 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x02_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 19963, 2 pins, pitch 3.5mm, size 7.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19963.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 19963 pitch 3.5mm size 7.7x7mm^2 drill 1.2mm pad 2.4mm -0 -2 -2 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x02_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10693, vertical (cable from top), 2 pins, pitch 3.5mm, size 8x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10693.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10693 vertical pitch 3.5mm size 8x8.3mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x03_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 20193, 3 pins, pitch 3.5mm, size 11.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20193.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 20193 pitch 3.5mm size 11.2x7mm^2 drill 1.2mm pad 2.4mm -0 -3 -3 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x03_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10694, vertical (cable from top), 3 pins, pitch 3.5mm, size 11.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10694.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10694 vertical pitch 3.5mm size 11.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x04_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 20001, 4 pins, pitch 3.5mm, size 14.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20001.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 20001 pitch 3.5mm size 14.7x7mm^2 drill 1.2mm pad 2.4mm -0 -4 -4 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x04_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10695, vertical (cable from top), 4 pins, pitch 3.5mm, size 15x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10695.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10695 vertical pitch 3.5mm size 15x8.3mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x05_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 20223, 5 pins, pitch 3.5mm, size 18.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20223.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 20223 pitch 3.5mm size 18.2x7mm^2 drill 1.2mm pad 2.4mm -0 -5 -5 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x05_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10696, vertical (cable from top), 5 pins, pitch 3.5mm, size 18.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10696.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10696 vertical pitch 3.5mm size 18.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x06_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 19964, 6 pins, pitch 3.5mm, size 21.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19964.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 19964 pitch 3.5mm size 21.7x7mm^2 drill 1.2mm pad 2.4mm -0 -6 -6 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x06_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10697, vertical (cable from top), 6 pins, pitch 3.5mm, size 22x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10697.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10697 vertical pitch 3.5mm size 22x8.3mm^2 drill 1.3mm pad 2.6mm -0 -6 -6 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x07_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10684, 7 pins, pitch 3.5mm, size 25.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10684.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10684 pitch 3.5mm size 25.2x7mm^2 drill 1.2mm pad 2.4mm -0 -7 -7 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x07_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10698, vertical (cable from top), 7 pins, pitch 3.5mm, size 25.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10698.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10698 vertical pitch 3.5mm size 25.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -7 -7 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x08_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 19965, 8 pins, pitch 3.5mm, size 28.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19965.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 19965 pitch 3.5mm size 28.7x7mm^2 drill 1.2mm pad 2.4mm -0 -8 -8 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x08_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10699, vertical (cable from top), 8 pins, pitch 3.5mm, size 29x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10699.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10699 vertical pitch 3.5mm size 29x8.3mm^2 drill 1.3mm pad 2.6mm -0 -8 -8 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x09_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10686, 9 pins, pitch 3.5mm, size 32.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10686.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10686 pitch 3.5mm size 32.2x7mm^2 drill 1.2mm pad 2.4mm -0 -9 -9 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x09_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10700, vertical (cable from top), 9 pins, pitch 3.5mm, size 32.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10700.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10700 vertical pitch 3.5mm size 32.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -9 -9 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x10_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10687, 10 pins, pitch 3.5mm, size 35.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10687.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10687 pitch 3.5mm size 35.7x7mm^2 drill 1.2mm pad 2.4mm -0 -10 -10 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x10_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10701, vertical (cable from top), 10 pins, pitch 3.5mm, size 36x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10701.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10701 vertical pitch 3.5mm size 36x8.3mm^2 drill 1.3mm pad 2.6mm -0 -10 -10 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x11_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10688, 11 pins, pitch 3.5mm, size 39.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10688.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10688 pitch 3.5mm size 39.2x7mm^2 drill 1.2mm pad 2.4mm -0 -11 -11 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x11_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10702, vertical (cable from top), 11 pins, pitch 3.5mm, size 39.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10702.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10702 vertical pitch 3.5mm size 39.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -11 -11 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x12_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10689, 12 pins, pitch 3.5mm, size 42.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10689.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10689 pitch 3.5mm size 42.7x7mm^2 drill 1.2mm pad 2.4mm -0 -12 -12 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x12_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10703, vertical (cable from top), 12 pins, pitch 3.5mm, size 43x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10703.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10703 vertical pitch 3.5mm size 43x8.3mm^2 drill 1.3mm pad 2.6mm -0 -12 -12 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x13_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10690, 13 pins, pitch 3.5mm, size 46.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10690.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10690 pitch 3.5mm size 46.2x7mm^2 drill 1.2mm pad 2.4mm -0 -13 -13 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x13_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10704, vertical (cable from top), 13 pins, pitch 3.5mm, size 46.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10704.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10704 vertical pitch 3.5mm size 46.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -13 -13 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x14_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10691, 14 pins, pitch 3.5mm, size 49.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10691.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10691 pitch 3.5mm size 49.7x7mm^2 drill 1.2mm pad 2.4mm -0 -14 -14 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x14_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10705, vertical (cable from top), 14 pins, pitch 3.5mm, size 50x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10705.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10705 vertical pitch 3.5mm size 50x8.3mm^2 drill 1.3mm pad 2.6mm -0 -14 -14 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x15_P3.50mm_Horizontal -Terminal Block 4Ucon ItemNo. 10692, 15 pins, pitch 3.5mm, size 53.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10692.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10692 pitch 3.5mm size 53.2x7mm^2 drill 1.2mm pad 2.4mm -0 -15 -15 -TerminalBlock_4Ucon -TerminalBlock_4Ucon_1x15_P3.50mm_Vertical -Terminal Block 4Ucon ItemNo. 10706, vertical (cable from top), 15 pins, pitch 3.5mm, size 53.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10706.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon -THT Terminal Block 4Ucon ItemNo. 10706 vertical pitch 3.5mm size 53.5x8.3mm^2 drill 1.3mm pad 2.6mm -0 -15 -15 -TerminalBlock_Altech -Altech_AK300_1x02_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -2 -2 -TerminalBlock_Altech -Altech_AK300_1x03_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -3 -3 -TerminalBlock_Altech -Altech_AK300_1x04_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -4 -4 -TerminalBlock_Altech -Altech_AK300_1x05_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -5 -5 -TerminalBlock_Altech -Altech_AK300_1x06_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -6 -6 -TerminalBlock_Altech -Altech_AK300_1x07_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -7 -7 -TerminalBlock_Altech -Altech_AK300_1x08_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -8 -8 -TerminalBlock_Altech -Altech_AK300_1x09_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -9 -9 -TerminalBlock_Altech -Altech_AK300_1x10_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -10 -10 -TerminalBlock_Altech -Altech_AK300_1x11_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -11 -11 -TerminalBlock_Altech -Altech_AK300_1x12_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -12 -12 -TerminalBlock_Altech -Altech_AK300_1x13_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -13 -13 -TerminalBlock_Altech -Altech_AK300_1x14_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -14 -14 -TerminalBlock_Altech -Altech_AK300_1x15_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -15 -15 -TerminalBlock_Altech -Altech_AK300_1x16_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -16 -16 -TerminalBlock_Altech -Altech_AK300_1x17_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -17 -17 -TerminalBlock_Altech -Altech_AK300_1x18_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -18 -18 -TerminalBlock_Altech -Altech_AK300_1x19_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -19 -19 -TerminalBlock_Altech -Altech_AK300_1x20_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -20 -20 -TerminalBlock_Altech -Altech_AK300_1x21_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -21 -21 -TerminalBlock_Altech -Altech_AK300_1x22_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -22 -22 -TerminalBlock_Altech -Altech_AK300_1x23_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -23 -23 -TerminalBlock_Altech -Altech_AK300_1x24_P5.00mm_45-Degree -Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) -Altech AK300 serie connector -0 -24 -24 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-02_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -2 -2 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-03_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -3 -3 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-04_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -4 -4 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-05_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -5 -5 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-06_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -6 -6 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-07_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -7 -7 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-08_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -8 -8 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-09_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -9 -9 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-10_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -10 -10 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-11_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -11 -11 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-12_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -12 -12 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-13_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -13 -13 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-14_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -14 -14 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-15_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -15 -15 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-16_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -16 -16 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-17_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -17 -17 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-18_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -18 -18 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-19_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -19 -19 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-20_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -20 -20 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-21_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -21 -21 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-22_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -22 -22 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-23_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -23 -23 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-24_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -24 -24 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-25_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -25 -25 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-26_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -26 -26 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-27_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -27 -27 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-28_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -28 -28 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-29_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -29 -29 -TerminalBlock_Dinkle -TerminalBlock_Dinkle_DT-55-B01X-30_P10.00mm -Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX -Dinkle DT-55-B01X Terminal Block pitch 10.00mm -0 -30 -30 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360271_1x01_Horizontal_ScrewM3.0_Boxed -single screw terminal block Metz Connect 360271, block size 9x7.3mm^2, drill diamater 1.5mm, 1 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 134, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360271 size 9x7.3mm^2 drill 1.5mm pad 3mm -0 -1 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360272_1x01_Horizontal_ScrewM2.6 -single screw terminal block Metz Connect 360272, block size 4x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 131, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360272 size 4x4mm^2 drill 1.5mm pad 3mm -0 -2 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360273_1x01_Horizontal_ScrewM2.6_WireProtection -single screw terminal block Metz Connect 360273, block size 5x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 131, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360273 size 5x4mm^2 drill 1.5mm pad 3mm -0 -2 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360291_1x01_Horizontal_ScrewM3.0_Boxed -single screw terminal block Metz Connect 360291, block size 9x7.3mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360291 size 9x7.3mm^2 drill 1.5mm pad 3mm -0 -2 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360322_1x01_Horizontal_ScrewM3.0_WireProtection -single screw terminal block Metz Connect 360322, block size 6x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360322 size 6x4mm^2 drill 1.5mm pad 3mm -0 -2 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360381_1x01_Horizontal_ScrewM3.0 -single screw terminal block Metz Connect 360381, block size 5x5mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360381 size 5x5mm^2 drill 1.5mm pad 3mm -0 -2 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360410_1x01_Horizontal_ScrewM3.0 -single screw terminal block Metz Connect 360410, block size 5x5mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 132, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360410 size 5x5mm^2 drill 1.5mm pad 3mm -0 -2 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_360425_1x01_Horizontal_ScrewM4.0_Boxed -single screw terminal block Metz Connect 360425, block size 9x9mm^2, drill diamater 1.6mm, 4 pads, pad diameter 3.2mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 134, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT single screw terminal block Metz Connect 360425 size 9x9mm^2 drill 1.6mm pad 3.2mm -0 -4 -1 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type011_RT05502HBWC_1x02_P5.00mm_Horizontal -terminal block Metz Connect Type011_RT05502HBWC, 2 pins, pitch 5mm, size 10x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type011_RT05502HBWC pitch 5mm size 10x10.5mm^2 drill 1.4mm pad 2.8mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type011_RT05503HBWC_1x03_P5.00mm_Horizontal -terminal block Metz Connect Type011_RT05503HBWC, 3 pins, pitch 5mm, size 15x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type011_RT05503HBWC pitch 5mm size 15x10.5mm^2 drill 1.4mm pad 2.8mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type011_RT05504HBWC_1x04_P5.00mm_Horizontal -terminal block Metz Connect Type011_RT05504HBWC, 4 pins, pitch 5mm, size 20x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type011_RT05504HBWC pitch 5mm size 20x10.5mm^2 drill 1.4mm pad 2.8mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type011_RT05505HBWC_1x05_P5.00mm_Horizontal -terminal block Metz Connect Type011_RT05505HBWC, 5 pins, pitch 5mm, size 25x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type011_RT05505HBWC pitch 5mm size 25x10.5mm^2 drill 1.4mm pad 2.8mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type011_RT05506HBWC_1x06_P5.00mm_Horizontal -terminal block Metz Connect Type011_RT05506HBWC, 6 pins, pitch 5mm, size 30x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type011_RT05506HBWC pitch 5mm size 30x10.5mm^2 drill 1.4mm pad 2.8mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type055_RT01502HDWU_1x02_P5.00mm_Horizontal -terminal block Metz Connect Type055_RT01502HDWU, 2 pins, pitch 5mm, size 10x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type055_RT01502HDWU pitch 5mm size 10x8mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type055_RT01503HDWU_1x03_P5.00mm_Horizontal -terminal block Metz Connect Type055_RT01503HDWU, 3 pins, pitch 5mm, size 15x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type055_RT01503HDWU pitch 5mm size 15x8mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type055_RT01504HDWU_1x04_P5.00mm_Horizontal -terminal block Metz Connect Type055_RT01504HDWU, 4 pins, pitch 5mm, size 20x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type055_RT01504HDWU pitch 5mm size 20x8mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type059_RT06302HBWC_1x02_P3.50mm_Horizontal -terminal block Metz Connect Type059_RT06302HBWC, 2 pins, pitch 3.5mm, size 7x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type059_RT06302HBWC pitch 3.5mm size 7x6.5mm^2 drill 1.2mm pad 2.3mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type059_RT06303HBWC_1x03_P3.50mm_Horizontal -terminal block Metz Connect Type059_RT06303HBWC, 3 pins, pitch 3.5mm, size 10.5x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type059_RT06303HBWC pitch 3.5mm size 10.5x6.5mm^2 drill 1.2mm pad 2.3mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type059_RT06304HBWC_1x04_P3.50mm_Horizontal -terminal block Metz Connect Type059_RT06304HBWC, 4 pins, pitch 3.5mm, size 14x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type059_RT06304HBWC pitch 3.5mm size 14x6.5mm^2 drill 1.2mm pad 2.3mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type059_RT06305HBWC_1x05_P3.50mm_Horizontal -terminal block Metz Connect Type059_RT06305HBWC, 5 pins, pitch 3.5mm, size 17.5x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type059_RT06305HBWC pitch 3.5mm size 17.5x6.5mm^2 drill 1.2mm pad 2.3mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type059_RT06306HBWC_1x06_P3.50mm_Horizontal -terminal block Metz Connect Type059_RT06306HBWC, 6 pins, pitch 3.5mm, size 21x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type059_RT06306HBWC pitch 3.5mm size 21x6.5mm^2 drill 1.2mm pad 2.3mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type067_RT01902HDWC_1x02_P10.00mm_Horizontal -terminal block Metz Connect Type067_RT01902HDWC, 2 pins, pitch 10mm, size 15.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type067_RT01902HDWC pitch 10mm size 15.8x8.2mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type067_RT01903HDWC_1x03_P10.00mm_Horizontal -terminal block Metz Connect Type067_RT01903HDWC, 3 pins, pitch 10mm, size 25.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type067_RT01903HDWC pitch 10mm size 25.8x8.2mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type067_RT01904HDWC_1x04_P10.00mm_Horizontal -terminal block Metz Connect Type067_RT01904HDWC, 4 pins, pitch 10mm, size 35.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type067_RT01904HDWC pitch 10mm size 35.8x8.2mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type067_RT01905HDWC_1x05_P10.00mm_Horizontal -terminal block Metz Connect Type067_RT01905HDWC, 5 pins, pitch 10mm, size 45.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type067_RT01905HDWC pitch 10mm size 45.8x8.2mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type073_RT02602HBLU_1x02_P5.08mm_Horizontal -terminal block Metz Connect Type073_RT02602HBLU, 2 pins, pitch 5.08mm, size 10.2x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310731_RT026xxHBLU_OFF-022792U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type073_RT02602HBLU pitch 5.08mm size 10.2x11mm^2 drill 1.4mm pad 2.6mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type073_RT02603HBLU_1x03_P5.08mm_Horizontal -terminal block Metz Connect Type073_RT02603HBLU, 3 pins, pitch 5.08mm, size 15.2x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310731_RT026xxHBLU_OFF-022792U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type073_RT02603HBLU pitch 5.08mm size 15.2x11mm^2 drill 1.4mm pad 2.6mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type086_RT03402HBLC_1x02_P3.81mm_Horizontal -terminal block Metz Connect Type086_RT03402HBLC, 2 pins, pitch 3.81mm, size 7.51x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type086_RT03402HBLC pitch 3.81mm size 7.51x7.3mm^2 drill 0.7mm pad 1.4mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type086_RT03403HBLC_1x03_P3.81mm_Horizontal -terminal block Metz Connect Type086_RT03403HBLC, 3 pins, pitch 3.81mm, size 11.3x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type086_RT03403HBLC pitch 3.81mm size 11.3x7.3mm^2 drill 0.7mm pad 1.4mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type086_RT03404HBLC_1x04_P3.81mm_Horizontal -terminal block Metz Connect Type086_RT03404HBLC, 4 pins, pitch 3.81mm, size 15.1x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type086_RT03404HBLC pitch 3.81mm size 15.1x7.3mm^2 drill 0.7mm pad 1.4mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type086_RT03405HBLC_1x05_P3.81mm_Horizontal -terminal block Metz Connect Type086_RT03405HBLC, 5 pins, pitch 3.81mm, size 18.9x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type086_RT03405HBLC pitch 3.81mm size 18.9x7.3mm^2 drill 0.7mm pad 1.4mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type086_RT03406HBLC_1x06_P3.81mm_Horizontal -terminal block Metz Connect Type086_RT03406HBLC, 6 pins, pitch 3.81mm, size 22.8x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type086_RT03406HBLC pitch 3.81mm size 22.8x7.3mm^2 drill 0.7mm pad 1.4mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type094_RT03502HBLU_1x02_P5.00mm_Horizontal -terminal block Metz Connect Type094_RT03502HBLU, 2 pins, pitch 5mm, size 10x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type094_RT03502HBLU pitch 5mm size 10x8.3mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type094_RT03503HBLU_1x03_P5.00mm_Horizontal -terminal block Metz Connect Type094_RT03503HBLU, 3 pins, pitch 5mm, size 15x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type094_RT03503HBLU pitch 5mm size 15x8.3mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type094_RT03504HBLU_1x04_P5.00mm_Horizontal -terminal block Metz Connect Type094_RT03504HBLU, 4 pins, pitch 5mm, size 20x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type094_RT03504HBLU pitch 5mm size 20x8.3mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type094_RT03505HBLU_1x05_P5.00mm_Horizontal -terminal block Metz Connect Type094_RT03505HBLU, 5 pins, pitch 5mm, size 25x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type094_RT03505HBLU pitch 5mm size 25x8.3mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type094_RT03506HBLU_1x06_P5.00mm_Horizontal -terminal block Metz Connect Type094_RT03506HBLU, 6 pins, pitch 5mm, size 30x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type094_RT03506HBLU pitch 5mm size 30x8.3mm^2 drill 1.3mm pad 2.6mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type101_RT01602HBWC_1x02_P5.08mm_Horizontal -terminal block Metz Connect Type101_RT01602HBWC, 2 pins, pitch 5.08mm, size 10.2x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type101_RT01602HBWC pitch 5.08mm size 10.2x8mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type101_RT01603HBWC_1x03_P5.08mm_Horizontal -terminal block Metz Connect Type101_RT01603HBWC, 3 pins, pitch 5.08mm, size 15.2x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type101_RT01603HBWC pitch 5.08mm size 15.2x8mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type101_RT01604HBWC_1x04_P5.08mm_Horizontal -terminal block Metz Connect Type101_RT01604HBWC, 4 pins, pitch 5.08mm, size 20.3x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type101_RT01604HBWC pitch 5.08mm size 20.3x8mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type101_RT01605HBWC_1x05_P5.08mm_Horizontal -terminal block Metz Connect Type101_RT01605HBWC, 5 pins, pitch 5.08mm, size 25.4x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type101_RT01605HBWC pitch 5.08mm size 25.4x8mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type101_RT01606HBWC_1x06_P5.08mm_Horizontal -terminal block Metz Connect Type101_RT01606HBWC, 6 pins, pitch 5.08mm, size 30.5x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type101_RT01606HBWC pitch 5.08mm size 30.5x8mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type171_RT13702HBWC_1x02_P7.50mm_Horizontal -terminal block Metz Connect Type171_RT13702HBWC, 2 pins, pitch 7.5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type171_RT13702HBWC pitch 7.5mm size 15x9mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type171_RT13703HBWC_1x03_P7.50mm_Horizontal -terminal block Metz Connect Type171_RT13703HBWC, 3 pins, pitch 7.5mm, size 22.5x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type171_RT13703HBWC pitch 7.5mm size 22.5x9mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type171_RT13704HBWC_1x04_P7.50mm_Horizontal -terminal block Metz Connect Type171_RT13704HBWC, 4 pins, pitch 7.5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type171_RT13704HBWC pitch 7.5mm size 30x9mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type171_RT13705HBWC_1x05_P7.50mm_Horizontal -terminal block Metz Connect Type171_RT13705HBWC, 5 pins, pitch 7.5mm, size 37.5x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type171_RT13705HBWC pitch 7.5mm size 37.5x9mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type171_RT13706HBWC_1x06_P7.50mm_Horizontal -terminal block Metz Connect Type171_RT13706HBWC, 6 pins, pitch 7.5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type171_RT13706HBWC pitch 7.5mm size 45x9mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type175_RT02702HBLC_1x02_P7.50mm_Horizontal -terminal block Metz Connect Type175_RT02702HBLC, 2 pins, pitch 7.5mm, size 15x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type175_RT02702HBLC pitch 7.5mm size 15x11mm^2 drill 1.4mm pad 2.6mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type175_RT02703HBLC_1x03_P7.50mm_Horizontal -terminal block Metz Connect Type175_RT02703HBLC, 3 pins, pitch 7.5mm, size 22.5x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type175_RT02703HBLC pitch 7.5mm size 22.5x11mm^2 drill 1.4mm pad 2.6mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type175_RT02704HBLC_1x04_P7.50mm_Horizontal -terminal block Metz Connect Type175_RT02704HBLC, 4 pins, pitch 7.5mm, size 30x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type175_RT02704HBLC pitch 7.5mm size 30x11mm^2 drill 1.4mm pad 2.6mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type175_RT02705HBLC_1x05_P7.50mm_Horizontal -terminal block Metz Connect Type175_RT02705HBLC, 5 pins, pitch 7.5mm, size 37.5x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type175_RT02705HBLC pitch 7.5mm size 37.5x11mm^2 drill 1.4mm pad 2.6mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type175_RT02706HBLC_1x06_P7.50mm_Horizontal -terminal block Metz Connect Type175_RT02706HBLC, 6 pins, pitch 7.5mm, size 45x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type175_RT02706HBLC pitch 7.5mm size 45x11mm^2 drill 1.4mm pad 2.6mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type205_RT04502UBLC_1x02_P5.00mm_45Degree -terminal block Metz Connect Type205_RT04502UBLC, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 10x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type205_RT04502UBLC 45Degree pitch 5mm size 10x12.5mm^2 drill 1.4mm pad 2.7mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type205_RT04503UBLC_1x03_P5.00mm_45Degree -terminal block Metz Connect Type205_RT04503UBLC, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 15x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type205_RT04503UBLC 45Degree pitch 5mm size 15x12.5mm^2 drill 1.4mm pad 2.7mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type205_RT04504UBLC_1x04_P5.00mm_45Degree -terminal block Metz Connect Type205_RT04504UBLC, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 20x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type205_RT04504UBLC 45Degree pitch 5mm size 20x12.5mm^2 drill 1.4mm pad 2.7mm -0 -4 -4 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type205_RT04505UBLC_1x05_P5.00mm_45Degree -terminal block Metz Connect Type205_RT04505UBLC, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 25x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type205_RT04505UBLC 45Degree pitch 5mm size 25x12.5mm^2 drill 1.4mm pad 2.7mm -0 -5 -5 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type205_RT04506UBLC_1x06_P5.00mm_45Degree -terminal block Metz Connect Type205_RT04506UBLC, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 30x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type205_RT04506UBLC 45Degree pitch 5mm size 30x12.5mm^2 drill 1.4mm pad 2.7mm -0 -6 -6 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type701_RT11L02HGLU_1x02_P6.35mm_Horizontal -terminal block Metz Connect Type701_RT11L02HGLU, 2 pins, pitch 6.35mm, size 12.7x12.5mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317011_RT11LxxHGLU_OFF-022798U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type701_RT11L02HGLU pitch 6.35mm size 12.7x12.5mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type701_RT11L03HGLU_1x03_P6.35mm_Horizontal -terminal block Metz Connect Type701_RT11L03HGLU, 3 pins, pitch 6.35mm, size 19x12.5mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317011_RT11LxxHGLU_OFF-022798U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type701_RT11L03HGLU pitch 6.35mm size 19x12.5mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type703_RT10N02HGLU_1x02_P9.52mm_Horizontal -terminal block Metz Connect Type703_RT10N02HGLU, 2 pins, pitch 9.52mm, size 19x12.5mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317031_RT10NxxHGLU_OFF-022897S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type703_RT10N02HGLU pitch 9.52mm size 19x12.5mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_MetzConnect -TerminalBlock_MetzConnect_Type703_RT10N03HGLU_1x03_P9.52mm_Horizontal -terminal block Metz Connect Type703_RT10N03HGLU, 3 pins, pitch 9.52mm, size 28.6x12.5mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317031_RT10NxxHGLU_OFF-022897S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect -THT terminal block Metz Connect Type703_RT10N03HGLU pitch 9.52mm size 28.6x12.5mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_Philmore -TerminalBlock_Philmore_TB132_1x02_P5.00mm_Horizontal -Terminal Block Philmore , 2 pins, pitch 5mm, size 10x10.2mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Philmore -THT Terminal Block Philmore pitch 5mm size 10x10.2mm^2 drill 1.2mm pad 2.4mm -0 -2 -2 -TerminalBlock_Philmore -TerminalBlock_Philmore_TB133_1x03_P5.00mm_Horizontal -Terminal Block Philmore , 3 pins, pitch 5mm, size 15x10.2mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Philmore -THT Terminal Block Philmore pitch 5mm size 15x10.2mm^2 drill 1.2mm pad 2.4mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-2-5.08, 2 pins, pitch 5.08mm, size 10.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-2-5.08 pitch 5.08mm size 10.2x9.8mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-2, 2 pins, pitch 5mm, size 10x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-2 pitch 5mm size 10x9.8mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-3-5.08_1x03_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-3-5.08, 3 pins, pitch 5.08mm, size 15.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-3-5.08 pitch 5.08mm size 15.2x9.8mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-3_1x03_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-3, 3 pins, pitch 5mm, size 15x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-3 pitch 5mm size 15x9.8mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-4-5.08_1x04_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-4-5.08, 4 pins, pitch 5.08mm, size 20.3x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-4-5.08 pitch 5.08mm size 20.3x9.8mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-4_1x04_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-4, 4 pins, pitch 5mm, size 20x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-4 pitch 5mm size 20x9.8mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-5-5.08_1x05_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-5-5.08, 5 pins, pitch 5.08mm, size 25.4x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-5-5.08 pitch 5.08mm size 25.4x9.8mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-5, 5 pins, pitch 5mm, size 25x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-5 pitch 5mm size 25x9.8mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-6-5.08_1x06_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-6-5.08, 6 pins, pitch 5.08mm, size 30.5x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-6-5.08 pitch 5.08mm size 30.5x9.8mm^2 drill 1.3mm pad 2.6mm -0 -6 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-6_1x06_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-6, 6 pins, pitch 5mm, size 30x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-6 pitch 5mm size 30x9.8mm^2 drill 1.3mm pad 2.6mm -0 -6 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-7-5.08_1x07_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-7-5.08, 7 pins, pitch 5.08mm, size 35.6x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-7-5.08 pitch 5.08mm size 35.6x9.8mm^2 drill 1.3mm pad 2.6mm -0 -7 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-7_1x07_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-7, 7 pins, pitch 5mm, size 35x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-7 pitch 5mm size 35x9.8mm^2 drill 1.3mm pad 2.6mm -0 -7 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-8-5.08_1x08_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-8-5.08, 8 pins, pitch 5.08mm, size 40.6x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-8-5.08 pitch 5.08mm size 40.6x9.8mm^2 drill 1.3mm pad 2.6mm -0 -8 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-8_1x08_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-8, 8 pins, pitch 5mm, size 40x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-8 pitch 5mm size 40x9.8mm^2 drill 1.3mm pad 2.6mm -0 -8 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-9-5.08_1x09_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-9-5.08, 9 pins, pitch 5.08mm, size 45.7x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-9-5.08 pitch 5.08mm size 45.7x9.8mm^2 drill 1.3mm pad 2.6mm -0 -9 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-9_1x09_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-9, 9 pins, pitch 5mm, size 45x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-9 pitch 5mm size 45x9.8mm^2 drill 1.3mm pad 2.6mm -0 -9 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-10-5.08_1x10_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-10-5.08, 10 pins, pitch 5.08mm, size 50.8x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-10-5.08 pitch 5.08mm size 50.8x9.8mm^2 drill 1.3mm pad 2.6mm -0 -10 -10 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-10_1x10_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-10, 10 pins, pitch 5mm, size 50x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-10 pitch 5mm size 50x9.8mm^2 drill 1.3mm pad 2.6mm -0 -10 -10 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-11-5.08_1x11_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-11-5.08, 11 pins, pitch 5.08mm, size 55.9x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-11-5.08 pitch 5.08mm size 55.9x9.8mm^2 drill 1.3mm pad 2.6mm -0 -11 -11 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-11_1x11_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-11, 11 pins, pitch 5mm, size 55x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-11 pitch 5mm size 55x9.8mm^2 drill 1.3mm pad 2.6mm -0 -11 -11 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-12-5.08_1x12_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-12-5.08, 12 pins, pitch 5.08mm, size 61x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-12-5.08 pitch 5.08mm size 61x9.8mm^2 drill 1.3mm pad 2.6mm -0 -12 -12 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-12_1x12_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-12, 12 pins, pitch 5mm, size 60x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-12 pitch 5mm size 60x9.8mm^2 drill 1.3mm pad 2.6mm -0 -12 -12 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-13-5.08_1x13_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-13-5.08, 13 pins, pitch 5.08mm, size 66x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-13-5.08 pitch 5.08mm size 66x9.8mm^2 drill 1.3mm pad 2.6mm -0 -13 -13 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-13_1x13_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-13, 13 pins, pitch 5mm, size 65x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-13 pitch 5mm size 65x9.8mm^2 drill 1.3mm pad 2.6mm -0 -13 -13 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-14-5.08_1x14_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-14-5.08, 14 pins, pitch 5.08mm, size 71.1x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-14-5.08 pitch 5.08mm size 71.1x9.8mm^2 drill 1.3mm pad 2.6mm -0 -14 -14 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-14_1x14_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-14, 14 pins, pitch 5mm, size 70x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-14 pitch 5mm size 70x9.8mm^2 drill 1.3mm pad 2.6mm -0 -14 -14 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-15-5.08_1x15_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-15-5.08, 15 pins, pitch 5.08mm, size 76.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-15-5.08 pitch 5.08mm size 76.2x9.8mm^2 drill 1.3mm pad 2.6mm -0 -15 -15 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-15_1x15_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-15, 15 pins, pitch 5mm, size 75x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-15 pitch 5mm size 75x9.8mm^2 drill 1.3mm pad 2.6mm -0 -15 -15 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-16-5.08_1x16_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-1,5-16-5.08, 16 pins, pitch 5.08mm, size 81.3x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-16-5.08 pitch 5.08mm size 81.3x9.8mm^2 drill 1.3mm pad 2.6mm -0 -16 -16 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-1,5-16_1x16_P5.00mm_Horizontal -Terminal Block Phoenix MKDS-1,5-16, 16 pins, pitch 5mm, size 80x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-1,5-16 pitch 5mm size 80x9.8mm^2 drill 1.3mm pad 2.6mm -0 -16 -16 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-2-5.08_1x02_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-2-5.08, 2 pins, pitch 5.08mm, size 10.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-2-5.08 pitch 5.08mm size 10.2x11.2mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-3-5.08_1x03_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-3-5.08, 3 pins, pitch 5.08mm, size 15.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-3-5.08 pitch 5.08mm size 15.2x11.2mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-4-5.08_1x04_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-4-5.08, 4 pins, pitch 5.08mm, size 20.3x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-4-5.08 pitch 5.08mm size 20.3x11.2mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-5-5.08_1x05_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-5-5.08, 5 pins, pitch 5.08mm, size 25.4x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-5-5.08 pitch 5.08mm size 25.4x11.2mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-6-5.08_1x06_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-6-5.08, 6 pins, pitch 5.08mm, size 30.5x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-6-5.08 pitch 5.08mm size 30.5x11.2mm^2 drill 1.3mm pad 2.6mm -0 -6 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-7-5.08_1x07_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-7-5.08, 7 pins, pitch 5.08mm, size 35.6x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-7-5.08 pitch 5.08mm size 35.6x11.2mm^2 drill 1.3mm pad 2.6mm -0 -7 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-8-5.08_1x08_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-8-5.08, 8 pins, pitch 5.08mm, size 40.6x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-8-5.08 pitch 5.08mm size 40.6x11.2mm^2 drill 1.3mm pad 2.6mm -0 -8 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-9-5.08_1x09_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-9-5.08, 9 pins, pitch 5.08mm, size 45.7x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-9-5.08 pitch 5.08mm size 45.7x11.2mm^2 drill 1.3mm pad 2.6mm -0 -9 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-10-5.08_1x10_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-10-5.08, 10 pins, pitch 5.08mm, size 50.8x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-10-5.08 pitch 5.08mm size 50.8x11.2mm^2 drill 1.3mm pad 2.6mm -0 -10 -10 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-11-5.08_1x11_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-11-5.08, 11 pins, pitch 5.08mm, size 55.9x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-11-5.08 pitch 5.08mm size 55.9x11.2mm^2 drill 1.3mm pad 2.6mm -0 -11 -11 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-12-5.08_1x12_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-12-5.08, 12 pins, pitch 5.08mm, size 61x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-12-5.08 pitch 5.08mm size 61x11.2mm^2 drill 1.3mm pad 2.6mm -0 -12 -12 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-13-5.08_1x13_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-13-5.08, 13 pins, pitch 5.08mm, size 66x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-13-5.08 pitch 5.08mm size 66x11.2mm^2 drill 1.3mm pad 2.6mm -0 -13 -13 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-14-5.08_1x14_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-14-5.08, 14 pins, pitch 5.08mm, size 71.1x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-14-5.08 pitch 5.08mm size 71.1x11.2mm^2 drill 1.3mm pad 2.6mm -0 -14 -14 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-15-5.08_1x15_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-15-5.08, 15 pins, pitch 5.08mm, size 76.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-15-5.08 pitch 5.08mm size 76.2x11.2mm^2 drill 1.3mm pad 2.6mm -0 -15 -15 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MKDS-3-16-5.08_1x16_P5.08mm_Horizontal -Terminal Block Phoenix MKDS-3-16-5.08, 16 pins, pitch 5.08mm, size 81.3x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MKDS-3-16-5.08 pitch 5.08mm size 81.3x11.2mm^2 drill 1.3mm pad 2.6mm -0 -16 -16 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-2-2.54_1x02_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-2-2.54, 2 pins, pitch 2.54mm, size 5.54x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725656-920552.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-2-2.54 pitch 2.54mm size 5.54x6.2mm^2 drill 1.1mm pad 2.2mm -0 -2 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-3-2.54_1x03_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-3-2.54, 3 pins, pitch 2.54mm, size 8.08x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725656-920552.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-3-2.54 pitch 2.54mm size 8.08x6.2mm^2 drill 1.1mm pad 2.2mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-4-2.54_1x04_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-4-2.54, 4 pins, pitch 2.54mm, size 10.6x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-4-2.54 pitch 2.54mm size 10.6x6.2mm^2 drill 1.1mm pad 2.2mm -0 -4 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-5-2.54_1x05_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-5-2.54, 5 pins, pitch 2.54mm, size 13.2x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-5-2.54 pitch 2.54mm size 13.2x6.2mm^2 drill 1.1mm pad 2.2mm -0 -5 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-6-2.54_1x06_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-6-2.54, 6 pins, pitch 2.54mm, size 15.7x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-6-2.54 pitch 2.54mm size 15.7x6.2mm^2 drill 1.1mm pad 2.2mm -0 -6 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-7-2.54_1x07_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-7-2.54, 7 pins, pitch 2.54mm, size 18.2x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-7-2.54 pitch 2.54mm size 18.2x6.2mm^2 drill 1.1mm pad 2.2mm -0 -7 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-8-2.54_1x08_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-8-2.54, 8 pins, pitch 2.54mm, size 20.8x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-8-2.54 pitch 2.54mm size 20.8x6.2mm^2 drill 1.1mm pad 2.2mm -0 -8 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-9-2.54_1x09_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-9-2.54, 9 pins, pitch 2.54mm, size 23.3x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-9-2.54 pitch 2.54mm size 23.3x6.2mm^2 drill 1.1mm pad 2.2mm -0 -9 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-10-2.54_1x10_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-10-2.54, 10 pins, pitch 2.54mm, size 25.9x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-10-2.54 pitch 2.54mm size 25.9x6.2mm^2 drill 1.1mm pad 2.2mm -0 -10 -10 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-11-2.54_1x11_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-11-2.54, 11 pins, pitch 2.54mm, size 28.4x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-11-2.54 pitch 2.54mm size 28.4x6.2mm^2 drill 1.1mm pad 2.2mm -0 -11 -11 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_MPT-0,5-12-2.54_1x12_P2.54mm_Horizontal -Terminal Block Phoenix MPT-0,5-12-2.54, 12 pins, pitch 2.54mm, size 30.9x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix MPT-0,5-12-2.54 pitch 2.54mm size 30.9x6.2mm^2 drill 1.1mm pad 2.2mm -0 -12 -12 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-2-3.5-H_1x02_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-2-3.5-H, 2 pins, pitch 3.5mm, size 7x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-2-3.5-H pitch 3.5mm size 7x7.6mm^2 drill 1.2mm pad 2.4mm -0 -2 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-2-5.0-H_1x02_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-2-5.0-H, 2 pins, pitch 5mm, size 10x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-2-5.0-H pitch 5mm size 10x9mm^2 drill 1.3mm pad 2.6mm -0 -2 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-3-3.5-H_1x03_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-3-3.5-H, 3 pins, pitch 3.5mm, size 10.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-3-3.5-H pitch 3.5mm size 10.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-3-5.0-H_1x03_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-3-5.0-H, 3 pins, pitch 5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-3-5.0-H pitch 5mm size 15x9mm^2 drill 1.3mm pad 2.6mm -0 -3 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-4-3.5-H_1x04_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-4-3.5-H, 4 pins, pitch 3.5mm, size 14x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-4-3.5-H pitch 3.5mm size 14x7.6mm^2 drill 1.2mm pad 2.4mm -0 -4 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-4-5.0-H_1x04_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-4-5.0-H, 4 pins, pitch 5mm, size 20x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-4-5.0-H pitch 5mm size 20x9mm^2 drill 1.3mm pad 2.6mm -0 -4 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-5-3.5-H_1x05_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-5-3.5-H, 5 pins, pitch 3.5mm, size 17.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-5-3.5-H pitch 3.5mm size 17.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -5 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-5-5.0-H_1x05_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-5-5.0-H, 5 pins, pitch 5mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-5-5.0-H pitch 5mm size 25x9mm^2 drill 1.3mm pad 2.6mm -0 -5 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-6-3.5-H_1x06_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-6-3.5-H, 6 pins, pitch 3.5mm, size 21x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-6-3.5-H pitch 3.5mm size 21x7.6mm^2 drill 1.2mm pad 2.4mm -0 -6 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-6-5.0-H_1x06_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-6-5.0-H, 6 pins, pitch 5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-6-5.0-H pitch 5mm size 30x9mm^2 drill 1.3mm pad 2.6mm -0 -6 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-7-3.5-H_1x07_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-7-3.5-H, 7 pins, pitch 3.5mm, size 24.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-7-3.5-H pitch 3.5mm size 24.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -7 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-7-5.0-H_1x07_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-7-5.0-H, 7 pins, pitch 5mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-7-5.0-H pitch 5mm size 35x9mm^2 drill 1.3mm pad 2.6mm -0 -7 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-8-3.5-H_1x08_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-8-3.5-H, 8 pins, pitch 3.5mm, size 28x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-8-3.5-H pitch 3.5mm size 28x7.6mm^2 drill 1.2mm pad 2.4mm -0 -8 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-8-5.0-H_1x08_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-8-5.0-H, 8 pins, pitch 5mm, size 40x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-8-5.0-H pitch 5mm size 40x9mm^2 drill 1.3mm pad 2.6mm -0 -8 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-9-3.5-H_1x09_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-9-3.5-H, 9 pins, pitch 3.5mm, size 31.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-9-3.5-H pitch 3.5mm size 31.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -9 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-9-5.0-H_1x09_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-9-5.0-H, 9 pins, pitch 5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-9-5.0-H pitch 5mm size 45x9mm^2 drill 1.3mm pad 2.6mm -0 -9 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-10-3.5-H_1x10_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-10-3.5-H, 10 pins, pitch 3.5mm, size 35x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-10-3.5-H pitch 3.5mm size 35x7.6mm^2 drill 1.2mm pad 2.4mm -0 -10 -10 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-10-5.0-H_1x10_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-10-5.0-H, 10 pins, pitch 5mm, size 50x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-10-5.0-H pitch 5mm size 50x9mm^2 drill 1.3mm pad 2.6mm -0 -10 -10 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-11-3.5-H_1x11_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-11-3.5-H, 11 pins, pitch 3.5mm, size 38.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-11-3.5-H pitch 3.5mm size 38.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -11 -11 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-11-5.0-H_1x11_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-11-5.0-H, 11 pins, pitch 5mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-11-5.0-H pitch 5mm size 55x9mm^2 drill 1.3mm pad 2.6mm -0 -11 -11 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-12-3.5-H_1x12_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-12-3.5-H, 12 pins, pitch 3.5mm, size 42x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-12-3.5-H pitch 3.5mm size 42x7.6mm^2 drill 1.2mm pad 2.4mm -0 -12 -12 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-12-5.0-H_1x12_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-12-5.0-H, 12 pins, pitch 5mm, size 60x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-12-5.0-H pitch 5mm size 60x9mm^2 drill 1.3mm pad 2.6mm -0 -12 -12 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-13-3.5-H_1x13_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-13-3.5-H, 13 pins, pitch 3.5mm, size 45.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-13-3.5-H pitch 3.5mm size 45.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -13 -13 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-13-5.0-H_1x13_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-13-5.0-H, 13 pins, pitch 5mm, size 65x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-13-5.0-H pitch 5mm size 65x9mm^2 drill 1.3mm pad 2.6mm -0 -13 -13 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-14-3.5-H_1x14_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-14-3.5-H, 14 pins, pitch 3.5mm, size 49x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-14-3.5-H pitch 3.5mm size 49x7.6mm^2 drill 1.2mm pad 2.4mm -0 -14 -14 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-14-5.0-H_1x14_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-14-5.0-H, 14 pins, pitch 5mm, size 70x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-14-5.0-H pitch 5mm size 70x9mm^2 drill 1.3mm pad 2.6mm -0 -14 -14 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-15-3.5-H_1x15_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-15-3.5-H, 15 pins, pitch 3.5mm, size 52.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-15-3.5-H pitch 3.5mm size 52.5x7.6mm^2 drill 1.2mm pad 2.4mm -0 -15 -15 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-15-5.0-H_1x15_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-15-5.0-H, 15 pins, pitch 5mm, size 75x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-15-5.0-H pitch 5mm size 75x9mm^2 drill 1.3mm pad 2.6mm -0 -15 -15 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-16-3.5-H_1x16_P3.50mm_Horizontal -Terminal Block Phoenix PT-1,5-16-3.5-H, 16 pins, pitch 3.5mm, size 56x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-16-3.5-H pitch 3.5mm size 56x7.6mm^2 drill 1.2mm pad 2.4mm -0 -16 -16 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PT-1,5-16-5.0-H_1x16_P5.00mm_Horizontal -Terminal Block Phoenix PT-1,5-16-5.0-H, 16 pins, pitch 5mm, size 80x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PT-1,5-16-5.0-H pitch 5mm size 80x9mm^2 drill 1.3mm pad 2.6mm -0 -16 -16 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-2-2,5-V-SMD_1x02-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 2 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814702/pdf -PhoenixContact PTSM0.5 2 2.5mm vertical SMD spring clamp terminal block connector -0 -4 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-2-2.5-H-THR_1x02_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR, 2 pins, pitch 2.5mm, size 7.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR pitch 2.5mm size 7.2x10mm^2 drill 1.2mm pad 3mm -0 -4 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-2-2.5-V-THR_1x02_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-2-2.5-V-THR, vertical (cable from top), 2 pins, pitch 2.5mm, size 5.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-2-2.5-V-THR vertical pitch 2.5mm size 5.5x5mm^2 drill 1.2mm pad 2mm -0 -4 -2 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-2-HV-2.5-SMD_1x02-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 2 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778696/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -4 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-3-2,5-V-SMD_1x03-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 3 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814715/pdf -PhoenixContact PTSM0.5 3 2.5mm vertical SMD spring clamp terminal block connector -0 -5 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR, 3 pins, pitch 2.5mm, size 9.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR pitch 2.5mm size 9.7x10mm^2 drill 1.2mm pad 3mm -0 -6 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-3-2.5-V-THR_1x03_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-3-2.5-V-THR, vertical (cable from top), 3 pins, pitch 2.5mm, size 8x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-3-2.5-V-THR vertical pitch 2.5mm size 8x5mm^2 drill 1.2mm pad 2mm -0 -6 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-3-HV-2.5-SMD_1x03-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 3 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778706/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -5 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-4-2,5-V-SMD_1x04-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 4 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814728/pdf -PhoenixContact PTSM0.5 4 2.5mm vertical SMD spring clamp terminal block connector -0 -6 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR, 4 pins, pitch 2.5mm, size 12.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR pitch 2.5mm size 12.2x10mm^2 drill 1.2mm pad 3mm -0 -8 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-4-2.5-V-THR_1x04_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-4-2.5-V-THR, vertical (cable from top), 4 pins, pitch 2.5mm, size 10.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-4-2.5-V-THR vertical pitch 2.5mm size 10.5x5mm^2 drill 1.2mm pad 2mm -0 -8 -4 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-4-HV-2.5-SMD_1x04-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 4 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778719/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -4 -3 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-5-2,5-V-SMD_1x05-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 5 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814731/pdf -PhoenixContact PTSM0.5 5 2.5mm vertical SMD spring clamp terminal block connector -0 -7 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-5-2.5-H-THR_1x05_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-5-2.5-H-THR, 5 pins, pitch 2.5mm, size 14.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-5-2.5-H-THR pitch 2.5mm size 14.7x10mm^2 drill 1.2mm pad 3mm -0 -10 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-5-2.5-V-THR_1x05_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-5-2.5-V-THR, vertical (cable from top), 5 pins, pitch 2.5mm, size 13x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-5-2.5-V-THR vertical pitch 2.5mm size 13x5mm^2 drill 1.2mm pad 2mm -0 -10 -5 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-5-HV-2.5-SMD_1x05-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 5 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778722/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -7 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-6-2,5-V-SMD_1x06-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 6 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814744/pdf -PhoenixContact PTSM0.5 6 2.5mm vertical SMD spring clamp terminal block connector -0 -8 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-6-2.5-H-THR_1x06_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-6-2.5-H-THR, 6 pins, pitch 2.5mm, size 17.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-6-2.5-H-THR pitch 2.5mm size 17.2x10mm^2 drill 1.2mm pad 3mm -0 -12 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-6-2.5-V-THR_1x06_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-6-2.5-V-THR, vertical (cable from top), 6 pins, pitch 2.5mm, size 15.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-6-2.5-V-THR vertical pitch 2.5mm size 15.5x5mm^2 drill 1.2mm pad 2mm -0 -12 -6 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-6-HV-2.5-SMD_1x06-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 6 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778735/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -8 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-7-2,5-V-SMD_1x07-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 7 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814757/pdf -PhoenixContact PTSM0.5 7 2.5mm vertical SMD spring clamp terminal block connector -0 -9 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-7-2.5-H-THR_1x07_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-7-2.5-H-THR, 7 pins, pitch 2.5mm, size 19.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-7-2.5-H-THR pitch 2.5mm size 19.7x10mm^2 drill 1.2mm pad 3mm -0 -14 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-7-2.5-V-THR_1x07_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-7-2.5-V-THR, vertical (cable from top), 7 pins, pitch 2.5mm, size 18x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-7-2.5-V-THR vertical pitch 2.5mm size 18x5mm^2 drill 1.2mm pad 2mm -0 -14 -7 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-7-HV-2.5-SMD_1x07-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 7 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778748/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -9 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-8-2,5-V-SMD_1x08-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 8 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814760/pdf -PhoenixContact PTSM0.5 8 2.5mm vertical SMD spring clamp terminal block connector -0 -10 -9 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-8-2.5-H-THR_1x08_P2.50mm_Horizontal -Terminal Block Phoenix PTSM-0,5-8-2.5-H-THR, 8 pins, pitch 2.5mm, size 22.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-8-2.5-H-THR pitch 2.5mm size 22.2x10mm^2 drill 1.2mm pad 3mm -0 -16 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-8-2.5-V-THR_1x08_P2.50mm_Vertical -Terminal Block Phoenix PTSM-0,5-8-2.5-V-THR, vertical (cable from top), 8 pins, pitch 2.5mm, size 20.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix -THT Terminal Block Phoenix PTSM-0,5-8-2.5-V-THR vertical pitch 2.5mm size 20.5x5mm^2 drill 1.2mm pad 2mm -0 -16 -8 -TerminalBlock_Phoenix -TerminalBlock_Phoenix_PTSM-0,5-8-HV-2.5-SMD_1x08-1MP_P2.50mm_Vertical -PhoenixContact PTSM0,5 8 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778751/pdf -2.5mm vertical SMD spring clamp terminal block connector -0 -10 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00001_1x02_P5.00mm_Horizontal -terminal block RND 205-00001, 2 pins, pitch 5mm, size 10x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00001 pitch 5mm size 10x9mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00002_1x03_P5.00mm_Horizontal -terminal block RND 205-00002, 3 pins, pitch 5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00002 pitch 5mm size 15x9mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00003_1x04_P5.00mm_Horizontal -terminal block RND 205-00003, 4 pins, pitch 5mm, size 20x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00003 pitch 5mm size 20x9mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00004_1x05_P5.00mm_Horizontal -terminal block RND 205-00004, 5 pins, pitch 5mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00004 pitch 5mm size 25x9mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00005_1x06_P5.00mm_Horizontal -terminal block RND 205-00005, 6 pins, pitch 5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00005 pitch 5mm size 30x9mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00006_1x07_P5.00mm_Horizontal -terminal block RND 205-00006, 7 pins, pitch 5mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00006 pitch 5mm size 35x9mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00007_1x08_P5.00mm_Horizontal -terminal block RND 205-00007, 8 pins, pitch 5mm, size 40x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00007 pitch 5mm size 40x9mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00008_1x09_P5.00mm_Horizontal -terminal block RND 205-00008, 9 pins, pitch 5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00008 pitch 5mm size 45x9mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00009_1x10_P5.00mm_Horizontal -terminal block RND 205-00009, 10 pins, pitch 5mm, size 50x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00009 pitch 5mm size 50x9mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00010_1x11_P5.00mm_Horizontal -terminal block RND 205-00010, 11 pins, pitch 5mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00010 pitch 5mm size 55x9mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00011_1x12_P5.00mm_Horizontal -terminal block RND 205-00011, 12 pins, pitch 5mm, size 60x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00011 pitch 5mm size 60x9mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00012_1x02_P5.00mm_Horizontal -terminal block RND 205-00012, 2 pins, pitch 5mm, size 10x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00012 pitch 5mm size 10x7.6mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00013_1x03_P5.00mm_Horizontal -terminal block RND 205-00013, 3 pins, pitch 5mm, size 15x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00013 pitch 5mm size 15x7.6mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00014_1x04_P5.00mm_Horizontal -terminal block RND 205-00014, 4 pins, pitch 5mm, size 20x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00014 pitch 5mm size 20x7.6mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00015_1x05_P5.00mm_Horizontal -terminal block RND 205-00015, 5 pins, pitch 5mm, size 25x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00015 pitch 5mm size 25x7.6mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00016_1x06_P5.00mm_Horizontal -terminal block RND 205-00016, 6 pins, pitch 5mm, size 30x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00016 pitch 5mm size 30x7.6mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00017_1x07_P5.00mm_Horizontal -terminal block RND 205-00017, 7 pins, pitch 5mm, size 35x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00017 pitch 5mm size 35x7.6mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00018_1x08_P5.00mm_Horizontal -terminal block RND 205-00018, 8 pins, pitch 5mm, size 40x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00018 pitch 5mm size 40x7.6mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00019_1x09_P5.00mm_Horizontal -terminal block RND 205-00019, 9 pins, pitch 5mm, size 45x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00019 pitch 5mm size 45x7.6mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00020_1x10_P5.00mm_Horizontal -terminal block RND 205-00020, 10 pins, pitch 5mm, size 50x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00020 pitch 5mm size 50x7.6mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00021_1x11_P5.00mm_Horizontal -terminal block RND 205-00021, 11 pins, pitch 5mm, size 55x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00021 pitch 5mm size 55x7.6mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00022_1x12_P5.00mm_Horizontal -terminal block RND 205-00022, 12 pins, pitch 5mm, size 60x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00022 pitch 5mm size 60x7.6mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00023_1x02_P10.00mm_Horizontal -terminal block RND 205-00023, 2 pins, pitch 10mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00023 pitch 10mm size 15x9mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00024_1x03_P10.00mm_Horizontal -terminal block RND 205-00024, 3 pins, pitch 10mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00024 pitch 10mm size 25x9mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00025_1x04_P10.00mm_Horizontal -terminal block RND 205-00025, 4 pins, pitch 10mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00025 pitch 10mm size 35x9mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00026_1x05_P10.00mm_Horizontal -terminal block RND 205-00026, 5 pins, pitch 10mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00026 pitch 10mm size 45x9mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00027_1x06_P10.00mm_Horizontal -terminal block RND 205-00027, 6 pins, pitch 10mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00027 pitch 10mm size 55x9mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00028_1x07_P10.00mm_Horizontal -terminal block RND 205-00028, 7 pins, pitch 10mm, size 65x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00028 pitch 10mm size 65x9mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00029_1x08_P10.00mm_Horizontal -terminal block RND 205-00029, 8 pins, pitch 10mm, size 75x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00029 pitch 10mm size 75x9mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00030_1x09_P10.00mm_Horizontal -terminal block RND 205-00030, 9 pins, pitch 10mm, size 85x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00030 pitch 10mm size 85x9mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00031_1x10_P10.00mm_Horizontal -terminal block RND 205-00031, 10 pins, pitch 10mm, size 95x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00031 pitch 10mm size 95x9mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00032_1x11_P10.00mm_Horizontal -terminal block RND 205-00032, 11 pins, pitch 10mm, size 105x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00032 pitch 10mm size 105x9mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00033_1x12_P10.00mm_Horizontal -terminal block RND 205-00033, 12 pins, pitch 10mm, size 115x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00033 pitch 10mm size 115x9mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00045_1x02_P5.00mm_Horizontal -terminal block RND 205-00045, 2 pins, pitch 5mm, size 10x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00045 pitch 5mm size 10x8.1mm^2 drill 1.1mm pad 2.1mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00046_1x03_P5.00mm_Horizontal -terminal block RND 205-00046, 3 pins, pitch 5mm, size 15x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00046 pitch 5mm size 15x8.1mm^2 drill 1.1mm pad 2.1mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00047_1x04_P5.00mm_Horizontal -terminal block RND 205-00047, 4 pins, pitch 5mm, size 20x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00047 pitch 5mm size 20x8.1mm^2 drill 1.1mm pad 2.1mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00048_1x05_P5.00mm_Horizontal -terminal block RND 205-00048, 5 pins, pitch 5mm, size 25x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00048 pitch 5mm size 25x8.1mm^2 drill 1.1mm pad 2.1mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00049_1x06_P5.00mm_Horizontal -terminal block RND 205-00049, 6 pins, pitch 5mm, size 30x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00049 pitch 5mm size 30x8.1mm^2 drill 1.1mm pad 2.1mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00050_1x07_P5.00mm_Horizontal -terminal block RND 205-00050, 7 pins, pitch 5mm, size 35x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00050 pitch 5mm size 35x8.1mm^2 drill 1.1mm pad 2.1mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00051_1x08_P5.00mm_Horizontal -terminal block RND 205-00051, 8 pins, pitch 5mm, size 40x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00051 pitch 5mm size 40x8.1mm^2 drill 1.1mm pad 2.1mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00052_1x09_P5.00mm_Horizontal -terminal block RND 205-00052, 9 pins, pitch 5mm, size 45x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00052 pitch 5mm size 45x8.1mm^2 drill 1.1mm pad 2.1mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00053_1x10_P5.00mm_Horizontal -terminal block RND 205-00053, 10 pins, pitch 5mm, size 50x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00053 pitch 5mm size 50x8.1mm^2 drill 1.1mm pad 2.1mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00054_1x11_P5.00mm_Horizontal -terminal block RND 205-00054, 11 pins, pitch 5mm, size 55x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00054 pitch 5mm size 55x8.1mm^2 drill 1.1mm pad 2.1mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00055_1x12_P5.00mm_Horizontal -terminal block RND 205-00055, 12 pins, pitch 5mm, size 60x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00055 pitch 5mm size 60x8.1mm^2 drill 1.1mm pad 2.1mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00056_1x02_P5.00mm_45Degree -terminal block RND 205-00056, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 10x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00056 45Degree pitch 5mm size 10x12.6mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00057_1x03_P5.00mm_45Degree -terminal block RND 205-00057, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 15x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00057 45Degree pitch 5mm size 15x12.6mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00058_1x04_P5.00mm_45Degree -terminal block RND 205-00058, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 20x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00058 45Degree pitch 5mm size 20x12.6mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00059_1x05_P5.00mm_45Degree -terminal block RND 205-00059, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 25x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00059 45Degree pitch 5mm size 25x12.6mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00060_1x06_P5.00mm_45Degree -terminal block RND 205-00060, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 30x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00060 45Degree pitch 5mm size 30x12.6mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00061_1x07_P5.00mm_45Degree -terminal block RND 205-00061, 45Degree (cable under 45degree), 7 pins, pitch 5mm, size 35x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00061 45Degree pitch 5mm size 35x12.6mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00062_1x08_P5.00mm_45Degree -terminal block RND 205-00062, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 40x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00062 45Degree pitch 5mm size 40x12.6mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00063_1x09_P5.00mm_45Degree -terminal block RND 205-00063, 45Degree (cable under 45degree), 9 pins, pitch 5mm, size 45x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00063 45Degree pitch 5mm size 45x12.6mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00064_1x10_P5.00mm_45Degree -terminal block RND 205-00064, 45Degree (cable under 45degree), 10 pins, pitch 5mm, size 50x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00064 45Degree pitch 5mm size 50x12.6mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00065_1x11_P5.00mm_45Degree -terminal block RND 205-00065, 45Degree (cable under 45degree), 11 pins, pitch 5mm, size 55x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00065 45Degree pitch 5mm size 55x12.6mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00066_1x12_P5.00mm_45Degree -terminal block RND 205-00066, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 60x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00066 45Degree pitch 5mm size 60x12.6mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00067_1x02_P7.50mm_Horizontal -terminal block RND 205-00067, 2 pins, pitch 7.5mm, size 15x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00067 pitch 7.5mm size 15x10.3mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00068_1x03_P7.50mm_Horizontal -terminal block RND 205-00068, 3 pins, pitch 7.5mm, size 22.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00068 pitch 7.5mm size 22.5x10.3mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00069_1x04_P7.50mm_Horizontal -terminal block RND 205-00069, 4 pins, pitch 7.5mm, size 30x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00069 pitch 7.5mm size 30x10.3mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00070_1x05_P7.50mm_Horizontal -terminal block RND 205-00070, 5 pins, pitch 7.5mm, size 37.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00070 pitch 7.5mm size 37.5x10.3mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00071_1x06_P7.50mm_Horizontal -terminal block RND 205-00071, 6 pins, pitch 7.5mm, size 45x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00071 pitch 7.5mm size 45x10.3mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00072_1x07_P7.50mm_Horizontal -terminal block RND 205-00072, 7 pins, pitch 7.5mm, size 52.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00072 pitch 7.5mm size 52.5x10.3mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00073_1x08_P7.50mm_Horizontal -terminal block RND 205-00073, 8 pins, pitch 7.5mm, size 60x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00073 pitch 7.5mm size 60x10.3mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00074_1x09_P7.50mm_Horizontal -terminal block RND 205-00074, 9 pins, pitch 7.5mm, size 67.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00074 pitch 7.5mm size 67.5x10.3mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00075_1x10_P7.50mm_Horizontal -terminal block RND 205-00075, 10 pins, pitch 7.5mm, size 75x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00075 pitch 7.5mm size 75x10.3mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00076_1x11_P7.50mm_Horizontal -terminal block RND 205-00076, 11 pins, pitch 7.5mm, size 82.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00076 pitch 7.5mm size 82.5x10.3mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00077_1x12_P7.50mm_Horizontal -terminal block RND 205-00077, 12 pins, pitch 7.5mm, size 90x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00077 pitch 7.5mm size 90x10.3mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00078_1x02_P10.00mm_Horizontal -terminal block RND 205-00078, 2 pins, pitch 10mm, size 15x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00078 pitch 10mm size 15x10.3mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00079_1x03_P10.00mm_Horizontal -terminal block RND 205-00079, 3 pins, pitch 10mm, size 25x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00079 pitch 10mm size 25x10.3mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00080_1x04_P10.00mm_Horizontal -terminal block RND 205-00080, 4 pins, pitch 10mm, size 35x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00080 pitch 10mm size 35x10.3mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00081_1x05_P10.00mm_Horizontal -terminal block RND 205-00081, 5 pins, pitch 10mm, size 45x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00081 pitch 10mm size 45x10.3mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00082_1x06_P10.00mm_Horizontal -terminal block RND 205-00082, 6 pins, pitch 10mm, size 55x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00082 pitch 10mm size 55x10.3mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00083_1x07_P10.00mm_Horizontal -terminal block RND 205-00083, 7 pins, pitch 10mm, size 65x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00083 pitch 10mm size 65x10.3mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00084_1x08_P10.00mm_Horizontal -terminal block RND 205-00084, 8 pins, pitch 10mm, size 75x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00084 pitch 10mm size 75x10.3mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00085_1x09_P10.00mm_Horizontal -terminal block RND 205-00085, 9 pins, pitch 10mm, size 85x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00085 pitch 10mm size 85x10.3mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00086_1x10_P10.00mm_Horizontal -terminal block RND 205-00086, 10 pins, pitch 10mm, size 95x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00086 pitch 10mm size 95x10.3mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00087_1x11_P10.00mm_Horizontal -terminal block RND 205-00087, 11 pins, pitch 10mm, size 105x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00087 pitch 10mm size 105x10.3mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00088_1x12_P10.00mm_Horizontal -terminal block RND 205-00088, 12 pins, pitch 10mm, size 115x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00088 pitch 10mm size 115x10.3mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00232_1x02_P5.08mm_Horizontal -terminal block RND 205-00232, 2 pins, pitch 5.08mm, size 10.2x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00232 pitch 5.08mm size 10.2x8.45mm^2 drill 1.1mm pad 2.1mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00233_1x03_P5.08mm_Horizontal -terminal block RND 205-00233, 3 pins, pitch 5.08mm, size 15.2x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00233 pitch 5.08mm size 15.2x8.45mm^2 drill 1.1mm pad 2.1mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00234_1x04_P5.08mm_Horizontal -terminal block RND 205-00234, 4 pins, pitch 5.08mm, size 20.3x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00234 pitch 5.08mm size 20.3x8.45mm^2 drill 1.1mm pad 2.1mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00235_1x05_P5.08mm_Horizontal -terminal block RND 205-00235, 5 pins, pitch 5.08mm, size 25.4x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00235 pitch 5.08mm size 25.4x8.45mm^2 drill 1.1mm pad 2.1mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00236_1x06_P5.08mm_Horizontal -terminal block RND 205-00236, 6 pins, pitch 5.08mm, size 30.5x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00236 pitch 5.08mm size 30.5x8.45mm^2 drill 1.1mm pad 2.1mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00237_1x07_P5.08mm_Horizontal -terminal block RND 205-00237, 7 pins, pitch 5.08mm, size 35.6x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00237 pitch 5.08mm size 35.6x8.45mm^2 drill 1.1mm pad 2.1mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00238_1x08_P5.08mm_Horizontal -terminal block RND 205-00238, 8 pins, pitch 5.08mm, size 40.6x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00238 pitch 5.08mm size 40.6x8.45mm^2 drill 1.1mm pad 2.1mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00239_1x09_P5.08mm_Horizontal -terminal block RND 205-00239, 9 pins, pitch 5.08mm, size 45.7x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00239 pitch 5.08mm size 45.7x8.45mm^2 drill 1.1mm pad 2.1mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00240_1x10_P5.08mm_Horizontal -terminal block RND 205-00240, 10 pins, pitch 5.08mm, size 50.8x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00240 pitch 5.08mm size 50.8x8.45mm^2 drill 1.1mm pad 2.1mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00241_1x02_P10.16mm_Horizontal -terminal block RND 205-00241, 2 pins, pitch 10.2mm, size 15.2x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00241 pitch 10.2mm size 15.2x8.3mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00242_1x03_P10.16mm_Horizontal -terminal block RND 205-00242, 3 pins, pitch 10.2mm, size 25.4x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00242 pitch 10.2mm size 25.4x8.3mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00243_1x04_P10.16mm_Horizontal -terminal block RND 205-00243, 4 pins, pitch 10.2mm, size 35.6x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00243 pitch 10.2mm size 35.6x8.3mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00244_1x05_P10.16mm_Horizontal -terminal block RND 205-00244, 5 pins, pitch 10.2mm, size 45.7x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00244 pitch 10.2mm size 45.7x8.3mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00245_1x06_P10.16mm_Horizontal -terminal block RND 205-00245, 6 pins, pitch 10.2mm, size 55.9x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00245 pitch 10.2mm size 55.9x8.3mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00246_1x07_P10.16mm_Horizontal -terminal block RND 205-00246, 7 pins, pitch 10.2mm, size 66x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00246 pitch 10.2mm size 66x8.3mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00247_1x08_P10.16mm_Horizontal -terminal block RND 205-00247, 8 pins, pitch 10.2mm, size 76.2x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00247 pitch 10.2mm size 76.2x8.3mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00248_1x09_P10.16mm_Horizontal -terminal block RND 205-00248, 9 pins, pitch 10.2mm, size 86.4x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00248 pitch 10.2mm size 86.4x8.3mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00249_1x10_P10.16mm_Horizontal -terminal block RND 205-00249, 10 pins, pitch 10.2mm, size 96.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00249 pitch 10.2mm size 96.5x8.3mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00250_1x11_P10.16mm_Horizontal -terminal block RND 205-00250, 11 pins, pitch 10.2mm, size 107x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00250 pitch 10.2mm size 107x8.3mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00251_1x12_P10.16mm_Horizontal -terminal block RND 205-00251, 12 pins, pitch 10.2mm, size 117x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00251 pitch 10.2mm size 117x8.3mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00276_1x02_P5.00mm_Vertical -terminal block RND 205-00078, vertical (cable from top), 2 pins, pitch 5mm, size 10x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00078 vertical pitch 5mm size 10x10mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00277_1x03_P5.00mm_Vertical -terminal block RND 205-00079, vertical (cable from top), 3 pins, pitch 5mm, size 15x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00079 vertical pitch 5mm size 15x10mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00278_1x04_P5.00mm_Vertical -terminal block RND 205-00080, vertical (cable from top), 4 pins, pitch 5mm, size 20x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00080 vertical pitch 5mm size 20x10mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00279_1x05_P5.00mm_Vertical -terminal block RND 205-00081, vertical (cable from top), 5 pins, pitch 5mm, size 25x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00081 vertical pitch 5mm size 25x10mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00280_1x06_P5.00mm_Vertical -terminal block RND 205-00082, vertical (cable from top), 6 pins, pitch 5mm, size 30x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00082 vertical pitch 5mm size 30x10mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00281_1x07_P5.00mm_Vertical -terminal block RND 205-00083, vertical (cable from top), 7 pins, pitch 5mm, size 35x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00083 vertical pitch 5mm size 35x10mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00282_1x08_P5.00mm_Vertical -terminal block RND 205-00084, vertical (cable from top), 8 pins, pitch 5mm, size 40x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00084 vertical pitch 5mm size 40x10mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00283_1x09_P5.00mm_Vertical -terminal block RND 205-00085, vertical (cable from top), 9 pins, pitch 5mm, size 45x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00085 vertical pitch 5mm size 45x10mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00284_1x10_P5.00mm_Vertical -terminal block RND 205-00086, vertical (cable from top), 10 pins, pitch 5mm, size 50x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00086 vertical pitch 5mm size 50x10mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00285_1x11_P5.00mm_Vertical -terminal block RND 205-00087, vertical (cable from top), 11 pins, pitch 5mm, size 55x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00087 vertical pitch 5mm size 55x10mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00286_1x12_P5.00mm_Vertical -terminal block RND 205-00088, vertical (cable from top), 12 pins, pitch 5mm, size 60x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00088 vertical pitch 5mm size 60x10mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00287_1x02_P5.08mm_Horizontal -terminal block RND 205-00287, 2 pins, pitch 5.08mm, size 10.2x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00287 pitch 5.08mm size 10.2x10.6mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00288_1x03_P5.08mm_Horizontal -terminal block RND 205-00288, 3 pins, pitch 5.08mm, size 15.2x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00288 pitch 5.08mm size 15.2x10.6mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00289_1x04_P5.08mm_Horizontal -terminal block RND 205-00289, 4 pins, pitch 5.08mm, size 20.3x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00289 pitch 5.08mm size 20.3x10.6mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00290_1x05_P5.08mm_Horizontal -terminal block RND 205-00290, 5 pins, pitch 5.08mm, size 25.4x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00290 pitch 5.08mm size 25.4x10.6mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00291_1x06_P5.08mm_Horizontal -terminal block RND 205-00291, 6 pins, pitch 5.08mm, size 30.5x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00291 pitch 5.08mm size 30.5x10.6mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00292_1x07_P5.08mm_Horizontal -terminal block RND 205-00292, 7 pins, pitch 5.08mm, size 35.6x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00292 pitch 5.08mm size 35.6x10.6mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00293_1x08_P5.08mm_Horizontal -terminal block RND 205-00293, 8 pins, pitch 5.08mm, size 40.6x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00293 pitch 5.08mm size 40.6x10.6mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00294_1x09_P5.08mm_Horizontal -terminal block RND 205-00294, 9 pins, pitch 5.08mm, size 45.7x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00294 pitch 5.08mm size 45.7x10.6mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00295_1x10_P5.08mm_Horizontal -terminal block RND 205-00295, 10 pins, pitch 5.08mm, size 50.8x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00295 pitch 5.08mm size 50.8x10.6mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00296_1x11_P5.08mm_Horizontal -terminal block RND 205-00296, 11 pins, pitch 5.08mm, size 55.9x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00296 pitch 5.08mm size 55.9x10.6mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00297_1x12_P5.08mm_Horizontal -terminal block RND 205-00297, 12 pins, pitch 5.08mm, size 61x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00297 pitch 5.08mm size 61x10.6mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_RND -TerminalBlock_RND_205-00298_1x02_P10.00mm_Horizontal -terminal block RND 205-00298, 2 pins, pitch 10mm, size 15x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00298 pitch 10mm size 15x8.1mm^2 drill 1.3mm pad 2.5mm -0 -2 -2 -TerminalBlock_RND -TerminalBlock_RND_205-00299_1x03_P10.00mm_Horizontal -terminal block RND 205-00299, 3 pins, pitch 10mm, size 25x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00299 pitch 10mm size 25x8.1mm^2 drill 1.3mm pad 2.5mm -0 -3 -3 -TerminalBlock_RND -TerminalBlock_RND_205-00300_1x04_P10.00mm_Horizontal -terminal block RND 205-00300, 4 pins, pitch 10mm, size 35x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00300 pitch 10mm size 35x8.1mm^2 drill 1.3mm pad 2.5mm -0 -4 -4 -TerminalBlock_RND -TerminalBlock_RND_205-00301_1x05_P10.00mm_Horizontal -terminal block RND 205-00301, 5 pins, pitch 10mm, size 45x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00301 pitch 10mm size 45x8.1mm^2 drill 1.3mm pad 2.5mm -0 -5 -5 -TerminalBlock_RND -TerminalBlock_RND_205-00302_1x06_P10.00mm_Horizontal -terminal block RND 205-00302, 6 pins, pitch 10mm, size 55x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00302 pitch 10mm size 55x8.1mm^2 drill 1.3mm pad 2.5mm -0 -6 -6 -TerminalBlock_RND -TerminalBlock_RND_205-00303_1x07_P10.00mm_Horizontal -terminal block RND 205-00303, 7 pins, pitch 10mm, size 65x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00303 pitch 10mm size 65x8.1mm^2 drill 1.3mm pad 2.5mm -0 -7 -7 -TerminalBlock_RND -TerminalBlock_RND_205-00304_1x08_P10.00mm_Horizontal -terminal block RND 205-00304, 8 pins, pitch 10mm, size 75x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00304 pitch 10mm size 75x8.1mm^2 drill 1.3mm pad 2.5mm -0 -8 -8 -TerminalBlock_RND -TerminalBlock_RND_205-00305_1x09_P10.00mm_Horizontal -terminal block RND 205-00305, 9 pins, pitch 10mm, size 85x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00305 pitch 10mm size 85x8.1mm^2 drill 1.3mm pad 2.5mm -0 -9 -9 -TerminalBlock_RND -TerminalBlock_RND_205-00306_1x10_P10.00mm_Horizontal -terminal block RND 205-00306, 10 pins, pitch 10mm, size 95x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00306 pitch 10mm size 95x8.1mm^2 drill 1.3mm pad 2.5mm -0 -10 -10 -TerminalBlock_RND -TerminalBlock_RND_205-00307_1x11_P10.00mm_Horizontal -terminal block RND 205-00307, 11 pins, pitch 10mm, size 105x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00307 pitch 10mm size 105x8.1mm^2 drill 1.3mm pad 2.5mm -0 -11 -11 -TerminalBlock_RND -TerminalBlock_RND_205-00308_1x12_P10.00mm_Horizontal -terminal block RND 205-00308, 12 pins, pitch 10mm, size 115x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND -THT terminal block RND 205-00308 pitch 10mm size 115x8.1mm^2 drill 1.3mm pad 2.5mm -0 -12 -12 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_1-282834-0_1x10_P2.54mm_Horizontal -Terminal Block TE 1-282834-0, 10 pins, pitch 2.54mm, size 25.86x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 1-282834-0 pitch 2.54mm size 25.86x6.5mm^2 drill 1.1mm pad 2.1mm -0 -10 -10 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_1-282834-1_1x11_P2.54mm_Horizontal -Terminal Block TE 1-282834-1, 11 pins, pitch 2.54mm, size 28.4x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 1-282834-1 pitch 2.54mm size 28.4x6.5mm^2 drill 1.1mm pad 2.1mm -0 -11 -11 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal -Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm -0 -12 -12 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-2_1x02_P2.54mm_Horizontal -Terminal Block TE 282834-2, 2 pins, pitch 2.54mm, size 5.54x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-2 pitch 2.54mm size 5.54x6.5mm^2 drill 1.1mm pad 2.1mm -0 -2 -2 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-3_1x03_P2.54mm_Horizontal -Terminal Block TE 282834-3, 3 pins, pitch 2.54mm, size 8.08x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-3 pitch 2.54mm size 8.08x6.5mm^2 drill 1.1mm pad 2.1mm -0 -3 -3 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-4_1x04_P2.54mm_Horizontal -Terminal Block TE 282834-4, 4 pins, pitch 2.54mm, size 10.620000000000001x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-4 pitch 2.54mm size 10.620000000000001x6.5mm^2 drill 1.1mm pad 2.1mm -0 -4 -4 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-5_1x05_P2.54mm_Horizontal -Terminal Block TE 282834-5, 5 pins, pitch 2.54mm, size 13.16x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-5 pitch 2.54mm size 13.16x6.5mm^2 drill 1.1mm pad 2.1mm -0 -5 -5 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-6_1x06_P2.54mm_Horizontal -Terminal Block TE 282834-6, 6 pins, pitch 2.54mm, size 15.7x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-6 pitch 2.54mm size 15.7x6.5mm^2 drill 1.1mm pad 2.1mm -0 -6 -6 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-7_1x07_P2.54mm_Horizontal -Terminal Block TE 282834-7, 7 pins, pitch 2.54mm, size 18.240000000000002x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-7 pitch 2.54mm size 18.240000000000002x6.5mm^2 drill 1.1mm pad 2.1mm -0 -7 -7 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-8_1x08_P2.54mm_Horizontal -Terminal Block TE 282834-8, 8 pins, pitch 2.54mm, size 20.78x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-8 pitch 2.54mm size 20.78x6.5mm^2 drill 1.1mm pad 2.1mm -0 -8 -8 -TerminalBlock_TE-Connectivity -TerminalBlock_TE_282834-9_1x09_P2.54mm_Horizontal -Terminal Block TE 282834-9, 9 pins, pitch 2.54mm, size 23.32x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity -THT Terminal Block TE 282834-9 pitch 2.54mm size 23.32x6.5mm^2 drill 1.1mm pad 2.1mm -0 -9 -9 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-101_1x01_P5.00mm_45Degree -Terminal Block WAGO 236-101, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 7.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-101 45Degree pitch 5mm size 7.3x14mm^2 drill 1.15mm pad 3mm -0 -1 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-102_1x02_P5.00mm_45Degree -Terminal Block WAGO 236-102, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-102 45Degree pitch 5mm size 12.3x14mm^2 drill 1.15mm pad 3mm -0 -2 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-103_1x03_P5.00mm_45Degree -Terminal Block WAGO 236-103, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-103 45Degree pitch 5mm size 17.3x14mm^2 drill 1.15mm pad 3mm -0 -3 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-104_1x04_P5.00mm_45Degree -Terminal Block WAGO 236-104, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-104 45Degree pitch 5mm size 22.3x14mm^2 drill 1.15mm pad 3mm -0 -4 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-106_1x06_P5.00mm_45Degree -Terminal Block WAGO 236-106, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-106 45Degree pitch 5mm size 32.3x14mm^2 drill 1.15mm pad 3mm -0 -6 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-108_1x08_P5.00mm_45Degree -Terminal Block WAGO 236-108, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-108 45Degree pitch 5mm size 42.3x14mm^2 drill 1.15mm pad 3mm -0 -8 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-112_1x12_P5.00mm_45Degree -Terminal Block WAGO 236-112, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-112 45Degree pitch 5mm size 62.3x14mm^2 drill 1.15mm pad 3mm -0 -12 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-116_1x16_P5.00mm_45Degree -Terminal Block WAGO 236-116, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-116 45Degree pitch 5mm size 82.3x14mm^2 drill 1.15mm pad 3mm -0 -16 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-124_1x24_P5.00mm_45Degree -Terminal Block WAGO 236-124, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-124 45Degree pitch 5mm size 122x14mm^2 drill 1.15mm pad 3mm -0 -24 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-136_1x36_P5.00mm_45Degree -Terminal Block WAGO 236-136, 45Degree (cable under 45degree), 36 pins, pitch 5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-136 45Degree pitch 5mm size 182x14mm^2 drill 1.15mm pad 3mm -0 -36 -36 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-148_1x48_P5.00mm_45Degree -Terminal Block WAGO 236-148, 45Degree (cable under 45degree), 48 pins, pitch 5mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-148 45Degree pitch 5mm size 242x14mm^2 drill 1.15mm pad 3mm -0 -48 -48 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-201_1x01_P7.50mm_45Degree -Terminal Block WAGO 236-201, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 9.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-201 45Degree pitch 7.5mm size 9.8x14mm^2 drill 1.15mm pad 3mm -0 -1 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-202_1x02_P7.50mm_45Degree -Terminal Block WAGO 236-202, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-202 45Degree pitch 7.5mm size 17.3x14mm^2 drill 1.15mm pad 3mm -0 -2 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-203_1x03_P7.50mm_45Degree -Terminal Block WAGO 236-203, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 24.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-203 45Degree pitch 7.5mm size 24.8x14mm^2 drill 1.15mm pad 3mm -0 -3 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-204_1x04_P7.50mm_45Degree -Terminal Block WAGO 236-204, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-204 45Degree pitch 7.5mm size 32.3x14mm^2 drill 1.15mm pad 3mm -0 -4 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-206_1x06_P7.50mm_45Degree -Terminal Block WAGO 236-206, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 47.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-206 45Degree pitch 7.5mm size 47.3x14mm^2 drill 1.15mm pad 3mm -0 -6 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-208_1x08_P7.50mm_45Degree -Terminal Block WAGO 236-208, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-208 45Degree pitch 7.5mm size 62.3x14mm^2 drill 1.15mm pad 3mm -0 -8 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-212_1x12_P7.50mm_45Degree -Terminal Block WAGO 236-212, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 92.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-212 45Degree pitch 7.5mm size 92.3x14mm^2 drill 1.15mm pad 3mm -0 -12 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-216_1x16_P7.50mm_45Degree -Terminal Block WAGO 236-216, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-216 45Degree pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm -0 -16 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-224_1x24_P7.50mm_45Degree -Terminal Block WAGO 236-224, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-224 45Degree pitch 7.5mm size 182x14mm^2 drill 1.15mm pad 3mm -0 -24 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-301_1x01_P10.00mm_45Degree -Terminal Block WAGO 236-301, 45Degree (cable under 45degree), 1 pins, pitch 10mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-301 45Degree pitch 10mm size 12.3x14mm^2 drill 1.15mm pad 3mm -0 -1 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-302_1x02_P10.00mm_45Degree -Terminal Block WAGO 236-302, 45Degree (cable under 45degree), 2 pins, pitch 10mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-302 45Degree pitch 10mm size 22.3x14mm^2 drill 1.15mm pad 3mm -0 -2 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-303_1x03_P10.00mm_45Degree -Terminal Block WAGO 236-303, 45Degree (cable under 45degree), 3 pins, pitch 10mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-303 45Degree pitch 10mm size 32.3x14mm^2 drill 1.15mm pad 3mm -0 -3 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-304_1x04_P10.00mm_45Degree -Terminal Block WAGO 236-304, 45Degree (cable under 45degree), 4 pins, pitch 10mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-304 45Degree pitch 10mm size 42.3x14mm^2 drill 1.15mm pad 3mm -0 -4 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-306_1x06_P10.00mm_45Degree -Terminal Block WAGO 236-306, 45Degree (cable under 45degree), 6 pins, pitch 10mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-306 45Degree pitch 10mm size 62.3x14mm^2 drill 1.15mm pad 3mm -0 -6 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-308_1x08_P10.00mm_45Degree -Terminal Block WAGO 236-308, 45Degree (cable under 45degree), 8 pins, pitch 10mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-308 45Degree pitch 10mm size 82.3x14mm^2 drill 1.15mm pad 3mm -0 -8 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-312_1x12_P10.00mm_45Degree -Terminal Block WAGO 236-312, 45Degree (cable under 45degree), 12 pins, pitch 10mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-312 45Degree pitch 10mm size 122x14mm^2 drill 1.15mm pad 3mm -0 -12 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-316_1x16_P10.00mm_45Degree -Terminal Block WAGO 236-316, 45Degree (cable under 45degree), 16 pins, pitch 10mm, size 162x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-316 45Degree pitch 10mm size 162x14mm^2 drill 1.15mm pad 3mm -0 -16 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-324_1x24_P10.00mm_45Degree -Terminal Block WAGO 236-324, 45Degree (cable under 45degree), 24 pins, pitch 10mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-324 45Degree pitch 10mm size 242x14mm^2 drill 1.15mm pad 3mm -0 -24 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-401_1x01_P5.00mm_45Degree -Terminal Block WAGO 236-401, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 7.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-401 45Degree pitch 5mm size 7.3x14mm^2 drill 1.15mm pad 3mm -0 -2 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-402_1x02_P5.00mm_45Degree -Terminal Block WAGO 236-402, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-402 45Degree pitch 5mm size 12.3x14mm^2 drill 1.15mm pad 3mm -0 -4 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-403_1x03_P5.00mm_45Degree -Terminal Block WAGO 236-403, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-403 45Degree pitch 5mm size 17.3x14mm^2 drill 1.15mm pad 3mm -0 -6 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-404_1x04_P5.00mm_45Degree -Terminal Block WAGO 236-404, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-404 45Degree pitch 5mm size 22.3x14mm^2 drill 1.15mm pad 3mm -0 -8 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-406_1x06_P5.00mm_45Degree -Terminal Block WAGO 236-406, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-406 45Degree pitch 5mm size 32.3x14mm^2 drill 1.15mm pad 3mm -0 -12 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-408_1x08_P5.00mm_45Degree -Terminal Block WAGO 236-408, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-408 45Degree pitch 5mm size 42.3x14mm^2 drill 1.15mm pad 3mm -0 -16 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-412_1x12_P5.00mm_45Degree -Terminal Block WAGO 236-412, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-412 45Degree pitch 5mm size 62.3x14mm^2 drill 1.15mm pad 3mm -0 -24 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-416_1x16_P5.00mm_45Degree -Terminal Block WAGO 236-416, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-416 45Degree pitch 5mm size 82.3x14mm^2 drill 1.15mm pad 3mm -0 -32 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-424_1x24_P5.00mm_45Degree -Terminal Block WAGO 236-424, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-424 45Degree pitch 5mm size 122x14mm^2 drill 1.15mm pad 3mm -0 -48 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-436_1x36_P5.00mm_45Degree -Terminal Block WAGO 236-436, 45Degree (cable under 45degree), 36 pins, pitch 5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-436 45Degree pitch 5mm size 182x14mm^2 drill 1.15mm pad 3mm -0 -72 -36 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-448_1x48_P5.00mm_45Degree -Terminal Block WAGO 236-448, 45Degree (cable under 45degree), 48 pins, pitch 5mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-448 45Degree pitch 5mm size 242x14mm^2 drill 1.15mm pad 3mm -0 -96 -48 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-501_1x01_P7.50mm_45Degree -Terminal Block WAGO 236-501, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 9.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-501 45Degree pitch 7.5mm size 9.8x14mm^2 drill 1.15mm pad 3mm -0 -2 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-502_1x02_P7.50mm_45Degree -Terminal Block WAGO 236-502, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-502 45Degree pitch 7.5mm size 17.3x14mm^2 drill 1.15mm pad 3mm -0 -4 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-503_1x03_P7.50mm_45Degree -Terminal Block WAGO 236-503, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 24.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-503 45Degree pitch 7.5mm size 24.8x14mm^2 drill 1.15mm pad 3mm -0 -6 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-504_1x04_P7.50mm_45Degree -Terminal Block WAGO 236-504, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-504 45Degree pitch 7.5mm size 32.3x14mm^2 drill 1.15mm pad 3mm -0 -8 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-506_1x06_P7.50mm_45Degree -Terminal Block WAGO 236-506, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 47.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-506 45Degree pitch 7.5mm size 47.3x14mm^2 drill 1.15mm pad 3mm -0 -12 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-508_1x08_P7.50mm_45Degree -Terminal Block WAGO 236-508, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-508 45Degree pitch 7.5mm size 62.3x14mm^2 drill 1.15mm pad 3mm -0 -16 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-512_1x12_P7.50mm_45Degree -Terminal Block WAGO 236-512, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 92.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-512 45Degree pitch 7.5mm size 92.3x14mm^2 drill 1.15mm pad 3mm -0 -24 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-516_1x16_P7.50mm_45Degree -Terminal Block WAGO 236-516, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-516 45Degree pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm -0 -32 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-524_1x24_P7.50mm_45Degree -Terminal Block WAGO 236-524, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-524 45Degree pitch 7.5mm size 182x14mm^2 drill 1.15mm pad 3mm -0 -48 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-601_1x01_P10.00mm_45Degree -Terminal Block WAGO 236-601, 45Degree (cable under 45degree), 1 pins, pitch 10mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-601 45Degree pitch 10mm size 12.3x14mm^2 drill 1.15mm pad 3mm -0 -2 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-602_1x02_P10.00mm_45Degree -Terminal Block WAGO 236-602, 45Degree (cable under 45degree), 2 pins, pitch 10mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-602 45Degree pitch 10mm size 22.3x14mm^2 drill 1.15mm pad 3mm -0 -4 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-603_1x03_P10.00mm_45Degree -Terminal Block WAGO 236-603, 45Degree (cable under 45degree), 3 pins, pitch 10mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-603 45Degree pitch 10mm size 32.3x14mm^2 drill 1.15mm pad 3mm -0 -6 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-604_1x04_P10.00mm_45Degree -Terminal Block WAGO 236-604, 45Degree (cable under 45degree), 4 pins, pitch 10mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-604 45Degree pitch 10mm size 42.3x14mm^2 drill 1.15mm pad 3mm -0 -8 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-606_1x06_P10.00mm_45Degree -Terminal Block WAGO 236-606, 45Degree (cable under 45degree), 6 pins, pitch 10mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-606 45Degree pitch 10mm size 62.3x14mm^2 drill 1.15mm pad 3mm -0 -12 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-608_1x08_P10.00mm_45Degree -Terminal Block WAGO 236-608, 45Degree (cable under 45degree), 8 pins, pitch 10mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-608 45Degree pitch 10mm size 82.3x14mm^2 drill 1.15mm pad 3mm -0 -16 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-612_1x12_P10.00mm_45Degree -Terminal Block WAGO 236-612, 45Degree (cable under 45degree), 12 pins, pitch 10mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-612 45Degree pitch 10mm size 122x14mm^2 drill 1.15mm pad 3mm -0 -24 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-616_1x16_P10.00mm_45Degree -Terminal Block WAGO 236-616, 45Degree (cable under 45degree), 16 pins, pitch 10mm, size 162x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-616 45Degree pitch 10mm size 162x14mm^2 drill 1.15mm pad 3mm -0 -32 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_236-624_1x24_P10.00mm_45Degree -Terminal Block WAGO 236-624, 45Degree (cable under 45degree), 24 pins, pitch 10mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 236-624 45Degree pitch 10mm size 242x14mm^2 drill 1.15mm pad 3mm -0 -48 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-101_1x01_P5.00mm_45Degree -Terminal Block WAGO 804-101, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 6.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-101 45Degree pitch 5mm size 6.5x15mm^2 drill 1.2mm pad 3mm -0 -2 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-102_1x02_P5.00mm_45Degree -Terminal Block WAGO 804-102, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 11.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-102 45Degree pitch 5mm size 11.5x15mm^2 drill 1.2mm pad 3mm -0 -4 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-103_1x03_P5.00mm_45Degree -Terminal Block WAGO 804-103, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 16.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-103 45Degree pitch 5mm size 16.5x15mm^2 drill 1.2mm pad 3mm -0 -6 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-104_1x04_P5.00mm_45Degree -Terminal Block WAGO 804-104, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 21.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-104 45Degree pitch 5mm size 21.5x15mm^2 drill 1.2mm pad 3mm -0 -8 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-105_1x05_P5.00mm_45Degree -Terminal Block WAGO 804-105, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 26.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-105 45Degree pitch 5mm size 26.5x15mm^2 drill 1.2mm pad 3mm -0 -10 -5 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-106_1x06_P5.00mm_45Degree -Terminal Block WAGO 804-106, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 31.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-106 45Degree pitch 5mm size 31.5x15mm^2 drill 1.2mm pad 3mm -0 -12 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-107_1x07_P5.00mm_45Degree -Terminal Block WAGO 804-107, 45Degree (cable under 45degree), 7 pins, pitch 5mm, size 36.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-107 45Degree pitch 5mm size 36.5x15mm^2 drill 1.2mm pad 3mm -0 -14 -7 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-108_1x08_P5.00mm_45Degree -Terminal Block WAGO 804-108, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 41.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-108 45Degree pitch 5mm size 41.5x15mm^2 drill 1.2mm pad 3mm -0 -16 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-109_1x09_P5.00mm_45Degree -Terminal Block WAGO 804-109, 45Degree (cable under 45degree), 9 pins, pitch 5mm, size 46.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-109 45Degree pitch 5mm size 46.5x15mm^2 drill 1.2mm pad 3mm -0 -18 -9 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-110_1x10_P5.00mm_45Degree -Terminal Block WAGO 804-110, 45Degree (cable under 45degree), 10 pins, pitch 5mm, size 51.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-110 45Degree pitch 5mm size 51.5x15mm^2 drill 1.2mm pad 3mm -0 -20 -10 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-112_1x12_P5.00mm_45Degree -Terminal Block WAGO 804-112, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 61.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-112 45Degree pitch 5mm size 61.5x15mm^2 drill 1.2mm pad 3mm -0 -24 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-116_1x16_P5.00mm_45Degree -Terminal Block WAGO 804-116, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 81.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-116 45Degree pitch 5mm size 81.5x15mm^2 drill 1.2mm pad 3mm -0 -32 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-124_1x24_P5.00mm_45Degree -Terminal Block WAGO 804-124, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-124 45Degree pitch 5mm size 122x15mm^2 drill 1.2mm pad 3mm -0 -48 -24 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-301_1x01_P7.50mm_45Degree -Terminal Block WAGO 804-301, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 6.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-301 45Degree pitch 7.5mm size 6.5x15mm^2 drill 1.2mm pad 3mm -0 -2 -1 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-302_1x02_P7.50mm_45Degree -Terminal Block WAGO 804-302, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 14x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-302 45Degree pitch 7.5mm size 14x15mm^2 drill 1.2mm pad 3mm -0 -4 -2 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-303_1x03_P7.50mm_45Degree -Terminal Block WAGO 804-303, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 21.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-303 45Degree pitch 7.5mm size 21.5x15mm^2 drill 1.2mm pad 3mm -0 -6 -3 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-304_1x04_P7.50mm_45Degree -Terminal Block WAGO 804-304, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 29x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-304 45Degree pitch 7.5mm size 29x15mm^2 drill 1.2mm pad 3mm -0 -8 -4 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-305_1x05_P7.50mm_45Degree -Terminal Block WAGO 804-305, 45Degree (cable under 45degree), 5 pins, pitch 7.5mm, size 36.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-305 45Degree pitch 7.5mm size 36.5x15mm^2 drill 1.2mm pad 3mm -0 -10 -5 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-306_1x06_P7.50mm_45Degree -Terminal Block WAGO 804-306, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 44x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-306 45Degree pitch 7.5mm size 44x15mm^2 drill 1.2mm pad 3mm -0 -12 -6 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-307_1x07_P7.50mm_45Degree -Terminal Block WAGO 804-307, 45Degree (cable under 45degree), 7 pins, pitch 7.5mm, size 51.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-307 45Degree pitch 7.5mm size 51.5x15mm^2 drill 1.2mm pad 3mm -0 -14 -7 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-308_1x08_P7.50mm_45Degree -Terminal Block WAGO 804-308, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 59x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-308 45Degree pitch 7.5mm size 59x15mm^2 drill 1.2mm pad 3mm -0 -16 -8 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-309_1x09_P7.50mm_45Degree -Terminal Block WAGO 804-309, 45Degree (cable under 45degree), 9 pins, pitch 7.5mm, size 66.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-309 45Degree pitch 7.5mm size 66.5x15mm^2 drill 1.2mm pad 3mm -0 -18 -9 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-310_1x10_P7.50mm_45Degree -Terminal Block WAGO 804-310, 45Degree (cable under 45degree), 10 pins, pitch 7.5mm, size 74x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-310 45Degree pitch 7.5mm size 74x15mm^2 drill 1.2mm pad 3mm -0 -20 -10 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-312_1x12_P7.50mm_45Degree -Terminal Block WAGO 804-312, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 89x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-312 45Degree pitch 7.5mm size 89x15mm^2 drill 1.2mm pad 3mm -0 -24 -12 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-316_1x16_P7.50mm_45Degree -Terminal Block WAGO 804-316, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 119x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-316 45Degree pitch 7.5mm size 119x15mm^2 drill 1.2mm pad 3mm -0 -32 -16 -TerminalBlock_WAGO -TerminalBlock_WAGO_804-324_1x24_P7.50mm_45Degree -Terminal Block WAGO 804-324, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 179x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO -THT Terminal Block WAGO 804-324 45Degree pitch 7.5mm size 179x15mm^2 drill 1.2mm pad 3mm -0 -48 -24 -TestPoint -TestPoint_2Pads_Pitch2.54mm_Drill0.8mm -Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm -CONN DEV -0 -2 -2 -TestPoint -TestPoint_2Pads_Pitch5.08mm_Drill1.3mm -Test point with 2 pads, pitch 5.08mm, hole diameter 1.3mm, wire diameter 1.0mm -CONN DEV -0 -2 -2 -TestPoint -TestPoint_Bridge_Pitch2.0mm_Drill0.7mm -wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch2.54mm_Drill0.7mm -wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch2.54mm_Drill1.0mm -wire loop as test point, pitch 2.54mm, hole diameter 1.0mm, wire diameter 0.8mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch2.54mm_Drill1.3mm -wire loop as test point, pitch 2.54mm, hole diameter 1.3mm, wire diameter 1.0mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch3.81mm_Drill1.3mm -wire loop as test point, pitch 3.81mm, hole diameter 1.3mm, wire diameter 1.0mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch5.08mm_Drill0.7mm -wire loop as test point, pitch 5.08mm, hole diameter 0.7mm, wire diameter 1.0mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch5.08mm_Drill1.3mm -wire loop as test point, pitch 5.08mm, hole diameter 1.3mm, wire diameter 1.0mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch6.35mm_Drill1.3mm -wire loop as test point, pitch 6.35mm, hole diameter 1.3mm, wire diameter 1.0mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Bridge_Pitch7.62mm_Drill1.3mm -wire loop as test point, pitch 7.62mm, hole diameter 1.3mm, wire diameter 1.0mm -test point wire loop -0 -2 -1 -TestPoint -TestPoint_Keystone_5000-5004_Miniature -Keystone Miniature THM Test Point 5000-5004, http://www.keyelco.com/product-pdf.cfm?p=1309 -Through Hole Mount Test Points -0 -1 -1 -TestPoint -TestPoint_Keystone_5005-5009_Compact -Keystone Miniature THM Test Point 5005-5009, http://www.keyelco.com/product-pdf.cfm?p=1314 -Through Hole Mount Test Points -0 -1 -1 -TestPoint -TestPoint_Keystone_5010-5014_Multipurpose -Keystone Miniature THM Test Point 5010-5014, http://www.keyelco.com/product-pdf.cfm?p=1319 -Through Hole Mount Test Points -0 -1 -1 -TestPoint -TestPoint_Keystone_5015_Micro-Minature -SMT Test Point- Micro Miniature 5015, http://www.keyelco.com/product-pdf.cfm?p=1353 -Test Point -0 -1 -1 -TestPoint -TestPoint_Keystone_5019_Minature -SMT Test Point- Micro Miniature 5019, http://www.keyelco.com/product-pdf.cfm?p=1357 -Test Point -0 -1 -1 -TestPoint -TestPoint_Loop_D1.80mm_Drill1.0mm_Beaded -wire loop with bead as test point, loop diameter 1.8mm, hole diameter 1.0mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.50mm_Drill1.0mm -wire loop as test point, loop diameter 2.5mm, hole diameter 1.0mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.50mm_Drill1.0mm_LowProfile -low profile wire loop as test point, loop diameter 2.5mm, hole diameter 1.0mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.50mm_Drill1.85mm -wire loop as test point, loop diameter 2.5mm, hole diameter 1.85mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.54mm_Drill1.5mm_Beaded -wire loop with bead as test point, loop diameter2.548mm, hole diameter 1.5mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.60mm_Drill0.9mm_Beaded -wire loop with bead as test point, loop diameter2.6mm, hole diameter 0.9mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.60mm_Drill1.4mm_Beaded -wire loop with bead as test point, loop diameter2.6mm, hole diameter 1.4mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D2.60mm_Drill1.6mm_Beaded -wire loop with bead as test point, loop diameter2.6mm, hole diameter 1.6mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D3.50mm_Drill0.9mm_Beaded -wire loop with bead as test point, loop diameter2.6mm, hole diameter 0.9mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D3.50mm_Drill1.4mm_Beaded -wire loop with bead as test point, loop diameter 3.5mm, hole diameter 1.4mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D3.80mm_Drill2.0mm -wire loop as test point, loop diameter 3.8mm, hole diameter 2.0mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D3.80mm_Drill2.5mm -wire loop as test point, loop diameter 3.8mm, hole diameter 2.5mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Loop_D3.80mm_Drill2.8mm -wire loop as test point, loop diameter 3.8mm, hole diameter 2.8mm -test point wire loop bead -0 -1 -1 -TestPoint -TestPoint_Pad_1.0x1.0mm -SMD rectangular pad as test Point, square 1.0mm side length -test point SMD pad rectangle square -0 -1 -1 -TestPoint -TestPoint_Pad_1.5x1.5mm -SMD rectangular pad as test Point, square 1.5mm side length -test point SMD pad rectangle square -0 -1 -1 -TestPoint -TestPoint_Pad_2.0x2.0mm -SMD rectangular pad as test Point, square 2.0mm side length -test point SMD pad rectangle square -0 -1 -1 -TestPoint -TestPoint_Pad_2.5x2.5mm -SMD rectangular pad as test Point, square 2.5mm side length -test point SMD pad rectangle square -0 -1 -1 -TestPoint -TestPoint_Pad_3.0x3.0mm -SMD rectangular pad as test Point, square 3.0mm side length -test point SMD pad rectangle square -0 -1 -1 -TestPoint -TestPoint_Pad_4.0x4.0mm -SMD rectangular pad as test Point, square 4.0mm side length -test point SMD pad rectangle square -0 -1 -1 -TestPoint -TestPoint_Pad_D1.0mm -SMD pad as test Point, diameter 1.0mm -test point SMD pad -0 -1 -1 -TestPoint -TestPoint_Pad_D1.5mm -SMD pad as test Point, diameter 1.5mm -test point SMD pad -0 -1 -1 -TestPoint -TestPoint_Pad_D2.0mm -SMD pad as test Point, diameter 2.0mm -test point SMD pad -0 -1 -1 -TestPoint -TestPoint_Pad_D2.5mm -SMD pad as test Point, diameter 2.5mm -test point SMD pad -0 -1 -1 -TestPoint -TestPoint_Pad_D3.0mm -SMD pad as test Point, diameter 3.0mm -test point SMD pad -0 -1 -1 -TestPoint -TestPoint_Pad_D4.0mm -SMD pad as test Point, diameter 4.0mm -test point SMD pad -0 -1 -1 -TestPoint -TestPoint_Plated_Hole_D2.0mm -Plated Hole as test Point, diameter 2.0mm -test point plated hole -0 -1 -1 -TestPoint -TestPoint_Plated_Hole_D3.0mm -Plated Hole as test Point, diameter 3.0mm -test point plated hole -0 -1 -1 -TestPoint -TestPoint_Plated_Hole_D4.0mm -Plated Hole as test Point, diameter 4.0mm -test point plated hole -0 -1 -1 -TestPoint -TestPoint_Plated_Hole_D5.0mm -Plated Hole as test Point, diameter 5.0mm -test point plated hole -0 -1 -1 -TestPoint -TestPoint_THTPad_1.0x1.0mm_Drill0.5mm -THT rectangular pad as test Point, square 1.0mm side length, hole diameter 0.5mm -test point THT pad rectangle square -0 -1 -1 -TestPoint -TestPoint_THTPad_1.5x1.5mm_Drill0.7mm -THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm -test point THT pad rectangle square -0 -1 -1 -TestPoint -TestPoint_THTPad_2.0x2.0mm_Drill1.0mm -THT rectangular pad as test Point, square 2.0mm_Drill1.0mm side length, hole diameter 1.0mm -test point THT pad rectangle square -0 -1 -1 -TestPoint -TestPoint_THTPad_2.5x2.5mm_Drill1.2mm -THT rectangular pad as test Point, square 2.5mm side length, hole diameter 1.2mm -test point THT pad rectangle square -0 -1 -1 -TestPoint -TestPoint_THTPad_3.0x3.0mm_Drill1.5mm -THT rectangular pad as test Point, square 3.0mm side length, hole diameter 1.5mm -test point THT pad rectangle square -0 -1 -1 -TestPoint -TestPoint_THTPad_4.0x4.0mm_Drill2.0mm -THT rectangular pad as test Point, square 4.0mm side length, hole diameter 2.0mm -test point THT pad rectangle square -0 -1 -1 -TestPoint -TestPoint_THTPad_D1.0mm_Drill0.5mm -THT pad as test Point, diameter 1.0mm, hole diameter 0.5mm -test point THT pad -0 -1 -1 -TestPoint -TestPoint_THTPad_D1.5mm_Drill0.7mm -THT pad as test Point, diameter 1.5mm, hole diameter 0.7mm -test point THT pad -0 -1 -1 -TestPoint -TestPoint_THTPad_D2.0mm_Drill1.0mm -THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm -test point THT pad -0 -1 -1 -TestPoint -TestPoint_THTPad_D2.5mm_Drill1.2mm -THT pad as test Point, diameter 2.5mm, hole diameter 1.2mm -test point THT pad -0 -1 -1 -TestPoint -TestPoint_THTPad_D3.0mm_Drill1.5mm -THT pad as test Point, diameter 3.0mm, hole diameter 1.5mm -test point THT pad -0 -1 -1 -TestPoint -TestPoint_THTPad_D4.0mm_Drill2.0mm -THT pad as test Point, diameter 4.0mm, hole diameter 2.0mm -test point THT pad -0 -1 -1 -Transformer_SMD -Pulse_P0926NL -SMT Gate Drive Transformer, 1:1:1, 8.0x6.3x5.3mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) -pulse pa0926nl -0 -6 -6 -Transformer_SMD -Pulse_PA1323NL -SMT Gate Drive Transformer, 1:1, 9.5x7.1x5.3mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) -pulse pa1323nl -0 -6 -6 -Transformer_SMD -Pulse_PA2001NL -SMT Gate Drive Transformer, 1:1, 8.6x6.7x2.5mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) -pulse pa2001nl pe-68386nl -0 -4 -4 -Transformer_SMD -Pulse_PA2002NL-PA2008NL-PA2009NL -SMT Gate Drive Transformer, 1:1:1 or 2:1:1 or 2.5:1:1 or 1:1, 9.0x8.6x7.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) -pulse pa2002nl pa2008nl pa2009nl p0544nl pa0184nl pa0297nl pa0510nl -0 -6 -6 -Transformer_SMD -Pulse_PA2004NL -SMT Gate Drive Transformer, 1:1:1, 8.6x6.7x3.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) -pulse pa2004nl pa0264nl -0 -6 -6 -Transformer_SMD -Pulse_PA2005NL -SMT Gate Drive Transformer, 1:1:1, 11.8x8.8x4.0mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) -pulse pa2005nl pa0173nl -0 -6 -6 -Transformer_SMD -Pulse_PA2006NL -SMT Gate Drive Transformer, 1:1, 11.8x8.8x4.0mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) -pulse pa2006nl pa0186nl -0 -4 -4 -Transformer_SMD -Pulse_PA2007NL -SMT Gate Drive Transformer, 1:1, 9.0x8.6x7.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) -pulse pa2007nl -0 -4 -4 -Transformer_SMD -Pulse_PA2777NL -SMT Gate Drive Transformer, 1:1, 7.1x6.1x5.5mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) -pulse pa2777nl -0 -8 -8 -Transformer_SMD -Pulse_PA3493NL -SMT Gate Drive Transformer, 1.25:1, 10.9x9.7x2.7mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) -pulse pa3493nl -0 -4 -4 -Transformer_SMD -Transformer_Coilcraft_CST1 -Current sense transformer, SMD, 8.0x8.13x5.3mm (https://www.coilcraft.com/pdfs/cst.pdf) -Transformer current sense SMD -0 -8 -8 -Transformer_SMD -Transformer_Coilcraft_CST2 -Current sense transformer, SMD, 8.0x8.13x5.3mm (https://www.coilcraft.com/pdfs/cst.pdf) -Transformer current sense SMD -0 -8 -8 -Transformer_SMD -Transformer_Coilcraft_CST2010 -Current sense transformer, SMD, 14.55x19.91x10.50mm (https://www.coilcraft.com/pdfs/cst2010.pdf) -Transformer current sense SMD -0 -12 -12 -Transformer_SMD -Transformer_CurrentSense_8.4x7.2mm -Transformer current sense SMD 8.4x7.2mm -Transformer current sense SMD -0 -8 -8 -Transformer_SMD -Transformer_Ethernet_Bel_S558-5999-T7-F -Ethernet Transformer, Bel S558-5999-T7-F, https://www.belfuse.com/resources/ICMs/lan-/S558-5999-T7-F.pdf -Ethernet Transformer -0 -16 -16 -Transformer_SMD -Transformer_Ethernet_Bourns_PT61017PEL -https://www.bourns.com/docs/Product-Datasheets/PT61017PEL.pdf -Transformer Ethernet Single Center-Tap -0 -16 -16 -Transformer_SMD -Transformer_Ethernet_HALO_TG111-MSC13 -Transformer Ethernet SMD, https://www.haloelectronics.com/pdf/discrete-genesus.pdf -Transformer Ethernet SMD -0 -24 -24 -Transformer_SMD -Transformer_MACOM_SM-22 -https://cdn.macom.com/datasheets/ETC1-1-13.pdf -RF Transformer -0 -5 -5 -Transformer_SMD -Transformer_NF_ETAL_P2781 -NF-Transformer, ETAL, P2781, SMD, -NF-Transformer ETAL P2781 SMD -0 -8 -7 -Transformer_SMD -Transformer_NF_ETAL_P2781_HandSoldering -NF-Transformer, ETAL, P2781, SMD, Handsoldering -NF-Transformer ETAL P2781 SMD Handsoldering -0 -8 -7 -Transformer_SMD -Transformer_NF_ETAL_P3000 -NF-Reansformer, ETAL, P3000, SMD, -NF-Reansformer ETAL P3000 SMD -0 -15 -13 -Transformer_SMD -Transformer_NF_ETAL_P3000_HandSoldering -NF-Reansformer, ETAL, P3000, SMD, Handsoldering, -NF-Reansformer ETAL P3000 SMD Handsoldering -0 -15 -13 -Transformer_SMD -Transformer_NF_ETAL_P3181 -NF-Transformer, ETAL, P3181, SMD, -NF-Transformer ETAL P3181 SMD -0 -7 -6 -Transformer_SMD -Transformer_NF_ETAL_P3181_HandSoldering -NF-Transformer, ETAL, P3181, SMD, Hand Soldering, -NF-Transformer ETAL P3181 SMD Hand Soldering -0 -7 -6 -Transformer_SMD -Transformer_NF_ETAL_P3188 -NF-Transformer, ETAL, P3188, SMD, -NF-Transformer ETAL P3188 SMD -0 -8 -6 -Transformer_SMD -Transformer_NF_ETAL_P3188_HandSoldering -NF-Transformer, ETAL, P3188, SMD, Handsoldering, -NF-Transformer ETAL P3188 SMD Handsoldering -0 -8 -6 -Transformer_SMD -Transformer_NF_ETAL_P3191 -NF-Transformer, ETAL, P3191, SMD, -NF-Transformer ETAL P3191 SMD -0 -8 -6 -Transformer_SMD -Transformer_NF_ETAL_P3191_HandSoldering -NF-Transformer, ETAL, P3191, SMD, Handsoldering, -NF-Transformer ETAL P3191 SMD Handsoldering -0 -8 -6 -Transformer_SMD -Transformer_Pulse_H1100NL -For H1100NL, H1101NL, H1102NL, H1121NL, H1183NL, H1199NL, HX1188NL, HX1198NL and H1302NL. https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/H1102NL/doc_part/H1102NL.pdf -H1100NL H1101NL H1102NL H1121NL H1183NL H1199NL HX1188NL HX1198NL H1302N -0 -16 -16 -Transformer_THT -Autotransformer_Toroid_1Tap_Horizontal_D9.0mm_Amidon-T30 -Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 9mm, Amidon T30, -Autotransformer Toroid horizontal laying 1 Tap Diameter 9mm Amidon T30 -0 -3 -3 -Transformer_THT -Autotransformer_Toroid_1Tap_Horizontal_D10.5mm_Amidon-T37 -Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 10,5mm, Amidon T37, -Autotransformer Toroid horizontal laying 1 Tap Diameter 10 5mm Amidon T37 -0 -3 -3 -Transformer_THT -Autotransformer_Toroid_1Tap_Horizontal_D12.5mm_Amidon-T44 -Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 12,5mm, Amidon T44, -Autotransformer Toroid horizontal laying 1 Tap Diameter 12 5mm Amidon T44 -0 -3 -3 -Transformer_THT -Autotransformer_Toroid_1Tap_Horizontal_D14.0mm_Amidon-T50 -Choke, Inductance, Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 14mm, Amidon T50, -Choke Inductance Autotransformer Toroid horizontal laying 1 Tap Diameter 14mm Amidon T50 -0 -3 -3 -Transformer_THT -Autotransformer_ZS1052-AC -Ignition coil for xenon flash, http://www.excelitas.com/downloads/ZS1052ACH.pdf -ignition coil autotransformer -0 -3 -3 -Transformer_THT -Transformer_37x44 -transformer 37x44mm² -transformer 37x44mm² -0 -12 -4 -Transformer_THT -Transformer_Breve_TEZ-22x24 -http://www.breve.pl/pdf/ANG/TEZ_ang.pdf -TEZ PCB Transformer -0 -7 -7 -Transformer_THT -Transformer_Breve_TEZ-28x33 -http://www.breve.pl/pdf/ANG/TEZ_ang.pdf -TEZ PCB Transformer -0 -9 -9 -Transformer_THT -Transformer_Breve_TEZ-35x42 -http://www.breve.pl/pdf/ANG/TEZ_ang.pdf -TEZ PCB Transformer -0 -9 -9 -Transformer_THT -Transformer_Breve_TEZ-38x45 -http://www.breve.pl/pdf/ANG/TEZ_ang.pdf -TEZ PCB Transformer -0 -9 -9 -Transformer_THT -Transformer_Breve_TEZ-44x52 -http://www.breve.pl/pdf/ANG/TEZ_ang.pdf -TEZ PCB Transformer -0 -10 -10 -Transformer_THT -Transformer_Breve_TEZ-47x57 -http://www.breve.pl/pdf/ANG/TEZ_ang.pdf -TEZ PCB Transformer -0 -13 -13 -Transformer_THT -Transformer_CHK_EI30-2VA_1xSec -Trafo, Printtrafo, CHK, EI30, 2VA, 1x Sec,http://www.eratransformers.com/downloads/030-7585.0.pdf -Trafo Printtrafo CHK EI30 2VA 1x Sec -0 -10 -10 -Transformer_THT -Transformer_CHK_EI30-2VA_2xSec -Trafo, Printtrafo, CHK, EI30, 2VA, 2x Sec, -Trafo Printtrafo CHK EI30 2VA 2x Sec -0 -10 -10 -Transformer_THT -Transformer_CHK_EI30-2VA_Neutral -Trafo, Printtrafo, CHK, EI30, 2VA, neutral, -Trafo Printtrafo CHK EI30 2VA neutral -0 -10 -10 -Transformer_THT -Transformer_CHK_EI38-3VA_1xSec -Trafo, Printtrafo, CHK, EI38, 3VA, 1x Sec, http://www.eratransformers.com/product-detail/20 -Trafo Printtrafo CHK EI38 3VA 1x Sec -0 -10 -10 -Transformer_THT -Transformer_CHK_EI38-3VA_2xSec -Trafo, Printtrafo, CHK, EI38, 3VA, 2x Sec, http://www.eratransformers.com/product-detail/20 -Trafo Printtrafo CHK EI38 3VA 2x Sec -0 -10 -10 -Transformer_THT -Transformer_CHK_EI38-3VA_Neutral -Trafo, Printtrafo, CHK, EI38, 3VA, neutral, http://www.eratransformers.com/product-detail/20 -Trafo Printtrafo CHK EI42 3VA neutral -0 -10 -10 -Transformer_THT -Transformer_CHK_EI42-5VA_1xSec -Trafo, Printtrafo, CHK, EI42, 5VA, 1x Sec, -Trafo Printtrafo CHK EI42 5VA 1x Sec -0 -10 -10 -Transformer_THT -Transformer_CHK_EI42-5VA_2xSec -Trafo, Printtrafo, CHK, EI42, 5VA, 2x Sec, -Trafo Printtrafo CHK EI42 5VA 2x Sec -0 -10 -10 -Transformer_THT -Transformer_CHK_EI42-5VA_Neutral -Trafo, Printtrafo, CHK, EI42, 5VA, neutral, -Trafo Printtrafo CHK EI42 5VA neutral -0 -10 -10 -Transformer_THT -Transformer_CHK_EI48-8VA_1xSec -Trafo, Printtrafo, CHK, EI48, 8VA, 1x Sec, http://www.eratransformers.com/product-detail/18 -Trafo Printtrafo CHK EI48 8VA 1x Sec -0 -12 -12 -Transformer_THT -Transformer_CHK_EI48-8VA_2xSec -Trafo, Printtrafo, CHK, EI48, 8VA, 2x Sec, http://www.eratransformers.com/product-detail/18 -Trafo Printtrafo CHK EI48 8VA 2x Sec -0 -12 -12 -Transformer_THT -Transformer_CHK_EI48-8VA_Neutral -Trafo, Printtrafo, CHK, EI48, 8VA, neutral, http://www.eratransformers.com/product-detail/18 -Trafo Printtrafo CHK EI48 8VA neutral -0 -12 -12 -Transformer_THT -Transformer_CHK_EI48-10VA_1xSec -Trafo, Printtrafo, CHK, EI48, 10VA, 1x Sec, -Trafo Printtrafo CHK EI48 10VA 1x Sec -0 -12 -12 -Transformer_THT -Transformer_CHK_EI48-10VA_2xSec -Trafo, Printtrafo, CHK, EI48, 10VA, 2x Sec, http://www.eratransformers.com/product-detail/18 -Trafo Printtrafo CHK EI48 10VA 2x Sec -0 -12 -12 -Transformer_THT -Transformer_CHK_EI48-10VA_Neutral -Trafo, Printtrafo, CHK, EI48, 10VA, neutral, http://www.eratransformers.com/product-detail/18 -Trafo Printtrafo CHK EI48 10VA neutral -0 -12 -12 -Transformer_THT -Transformer_CHK_EI54-12VA_1xSec -Trafo, Printtrafo, CHK, EI54, 12VA, 1x Sec,http://www.eratransformers.com/product-detail/19 -Trafo Printtrafo CHK EI54 12VA 1x Sec -0 -14 -14 -Transformer_THT -Transformer_CHK_EI54-12VA_2xSec -Trafo, Printtrafo, CHK, EI54, 12VA, 2x Sec,http://www.eratransformers.com/product-detail/19 -Trafo Printtrafo CHK EI54 12VA 2x Sec -0 -14 -14 -Transformer_THT -Transformer_CHK_EI54-12VA_Neutral -Trafo, Printtrafo, CHK, EI54, 12VA, neutral,http://www.eratransformers.com/product-detail/19 -Trafo Printtrafo CHK EI54 12VA neutral -0 -14 -14 -Transformer_THT -Transformer_CHK_EI54-16VA_1xSec -Trafo, Printtrafo, CHK, EI54, 16VA, 1x Sec,http://www.eratransformers.com/product-detail/19 -Trafo Printtrafo CHK EI54 16VA 1x Sec -0 -14 -14 -Transformer_THT -Transformer_CHK_EI54-16VA_2xSec -Trafo, Printtrafo, CHK, EI54, 16VA, 2x Sec,http://www.eratransformers.com/product-detail/19 -Trafo Printtrafo CHK EI54 16VA 2x Sec -0 -14 -14 -Transformer_THT -Transformer_CHK_EI54-16VA_Neutral -Trafo, Printtrafo, CHK, EI54, 16VA, neutral,http://www.eratransformers.com/product-detail/19 -Trafo Printtrafo CHK EI54 16VA neutral -0 -14 -14 -Transformer_THT -Transformer_CHK_UI30-4VA_Flat -Trafo, Flattrafo, CHK, UI30, 4VA, -Trafo Flattrafo CHK UI30 4VA -0 -16 -16 -Transformer_THT -Transformer_CHK_UI39-10VA_Flat -Trafo, Flattrafo, CHK, UI39, 10VA, -Trafo Flattrafo CHK UI39 10VA -0 -20 -20 -Transformer_THT -Transformer_Coilcraft_Q4434-B_Rhombus-T1311 -Transformator, Transformer, Flyback, Coilcraft Q4434-B, Rgombus T1311, -Transformator Transformer Flyback Coilcraft Q4434-B Rgombus T1311 -0 -8 -8 -Transformer_THT -Transformer_EPCOS_B66359A1013T_Horizontal -Transformer, Transformator, ETD29, 13 Pin, Horizontal, EPCOS-B66359A1013T, -Transformer Transformator ETD29 13 Pin Horizontal EPCOS-B66359A1013T -0 -13 -13 -Transformer_THT -Transformer_EPCOS_B66359J1014T_Vertical -Transformer, Transformator, ETD29, 14 Pin, Vertical, EPCOS-B66359J1014T, -Transformer Transformator ETD29 14 Pin Vertical EPCOS-B66359J1014T -0 -14 -14 -Transformer_THT -Transformer_Microphone_Lundahl_LL1538 -AUDIO TRAFO LUNDAHL, https://www.lundahltransformers.com/wp-content/uploads/datasheets/1538_8xl.pdf -AUDIO TRAFO LUNDAHL -0 -7 -7 -Transformer_THT -Transformer_Microphone_Lundahl_LL1587 -AUDIO TRAFO LUNDAHL, https://www.lundahltransformers.com/wp-content/uploads/datasheets/1587.pdf -AUDIO TRAFO LUNDAHL -0 -7 -7 -Transformer_THT -Transformer_Myrra_74040_Horizontal -Transformer, Transformator, ETD29, 13 Pin, Horizontal, Myrra-74040, -Transformer Transformator ETD29 13 Pin Horizontal Myrra-74040 -0 -13 -13 -Transformer_THT -Transformer_Myrra_EF20_7408x -EF20 flyback transformer,http://myrra.com/wp-content/uploads/2017/09/Datasheet-74087-74088-74089-rev-A.pdf -transformer flyback SMPS -0 -9 -9 -Transformer_THT -Transformer_NF_ETAL_1-1_P1200 -NF-Transformer, 1:1, ETAL P1200,http://www.etalgroup.com/sites/default/files/products/P1200_April_2005.pdf -NF-Transformer 1to1 ETAL P1200 -0 -4 -4 -Transformer_THT -Transformer_NF_ETAL_P1165 -NF-Transformer, ETAL, P1165,http://www.etalgroup.com/sites/default/files/products/P1165_February_2006.pdf -NF-Transformer ETAL P1165 -0 -4 -4 -Transformer_THT -Transformer_NF_ETAL_P3324 -NF-Transformer, ETAL P3324,http://www.etalgroup.com/sites/default/files/products/P3324_April_2005.pdf -NF-Transformer ETAL P3324 -0 -4 -4 -Transformer_THT -Transformer_NF_ETAL_P3356 -NF-Transformer, ETAL P3356, http://www.etalgroup.com/sites/default/files/products/P3356_December_2005.pdf -NF-Transformer ETAL P3356 -0 -4 -4 -Transformer_THT -Transformer_Toroid_Horizontal_D9.0mm_Amidon-T30 -Transformer, Toroid, horizontal, laying, Diameter 9mm, Amidon, T30, -Transformer Toroid horizontal laying Diameter 9mm Amidon T30 -0 -4 -4 -Transformer_THT -Transformer_Toroid_Horizontal_D10.5mm_Amidon-T37 -Transformer, Toroid, horizontal, laying, Diameter 10,5mm, Amidon T37, -Transformer Toroid horizontal laying Diameter 10 5mm Amidon T37 -0 -4 -4 -Transformer_THT -Transformer_Toroid_Horizontal_D12.5mm_Amidon-T44 -Transformer, Toroid, horizontal, laying, Diameter 12,5mm, Amidon T44, -Transformer Toroid horizontal laying Diameter 12 5mm Amidon T44 -0 -4 -4 -Transformer_THT -Transformer_Toroid_Horizontal_D14.0mm_Amidon-T50 -Transformer, Toroid, horizontal, laying, Diameter 14mm, Amidon T50, -Transformer Toroid horizontal laying Diameter 14mm Amidon T50 -0 -4 -4 -Transformer_THT -Transformer_Toroid_Horizontal_D18.0mm -Transformer, Toroid, tapped, horizontal, laying, Diameter 18mm, -Transformer Toroid tapped horizontal laying Diameter 18mm -0 -5 -4 -Transformer_THT -Transformer_Toroid_Tapped_Horizontal_D9.0mm_Amidon-T30 -Transformer, Toroid, tapped, horizontal, laying, Diameter 9mm, Amidon, T30, -Transformer Toroid tapped horizontal laying Diameter 9mm Amidon T30 -0 -6 -6 -Transformer_THT -Transformer_Toroid_Tapped_Horizontal_D10.5mm_Amidon-T37 -Transformer, Toroid, tapped, horizontal, laying, Diameter 10,5mm, Amidon, T37, -Transformer Toroid tapped horizontal laying Diameter 10 5mm Amidon T37 -0 -6 -6 -Transformer_THT -Transformer_Toroid_Tapped_Horizontal_D12.5mm_Amidon-T44 -Transformer, Toroid, tapped, horizontal, laying, Diameter 12,5mm, Amidon, T44, -Transformer Toroid tapped horizontal laying Diameter 12 5mm Amidon T44 -0 -6 -6 -Transformer_THT -Transformer_Toroid_Tapped_Horizontal_D14.0mm_Amidon-T50 -Transformer, Toroid, tapped, horizontal, laying, Diameter 14mm, Amidon T50, -Transformer Toroid tapped horizontal laying Diameter 14mm Amidon T50 -0 -6 -6 -Transformer_THT -Transformer_Wuerth_750343373 -Transformer, horizontal core with bobbin, 10 pin, 3.81mm pitch, 15.24mm row spacing, 22x23x17.53mm (https://katalog.we-online.com/ctm/datasheet/750343373.pdf) -transformer flyback -0 -10 -10 -Valve -Valve_ECC-83-1 -Valve ECC-83-1 round pins -Valve ECC-83-1 round pins -0 -9 -9 -Valve -Valve_ECC-83-2 -Valve ECC-83-2 flat pins -Valve ECC-83-2 flat pins -0 -10 -9 -Valve -Valve_EURO -Valve Euro -Valve Euro -0 -7 -5 -Valve -Valve_Glimm -Valve Glimm -Valve Glimm -0 -2 -2 -Valve -Valve_Mini_G -Valve mini G -Valve mini G -0 -9 -7 -Valve -Valve_Mini_P -Valve mini P -Valve mini P -0 -7 -7 -Valve -Valve_Mini_Pentode_Linear -Mini-Pentode, 5-pin, e.g. JAN6418 -Valve Mini-Pentode 5-pin JAN6418 -0 -5 -5 -Valve -Valve_Noval_G -Valve NOVAL G -Valve NOVAL G -0 -11 -9 -Valve -Valve_Noval_P -Valve NOVAL P -Valve NOVAL P -0 -9 -9 -Valve -Valve_Octal -8-pin round valve -valve -0 -9 -8 -Varistor -RV_Disc_D7mm_W3.4mm_P5mm -Varistor, diameter 7mm, width 3.4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W3.5mm_P5mm -Varistor, diameter 7mm, width 3.5mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W3.6mm_P5mm -Varistor, diameter 7mm, width 3.6mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W3.7mm_P5mm -Varistor, diameter 7mm, width 3.7mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W3.8mm_P5mm -Varistor, diameter 7mm, width 3.8mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W3.9mm_P5mm -Varistor, diameter 7mm, width 3.9mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W4.2mm_P5mm -Varistor, diameter 7mm, width 4.2mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W4.3mm_P5mm -Varistor, diameter 7mm, width 4.3mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W4.5mm_P5mm -Varistor, diameter 7mm, width 4.5mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W4.8mm_P5mm -Varistor, diameter 7mm, width 4.8mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W4.9mm_P5mm -Varistor, diameter 7mm, width 4.9mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W4mm_P5mm -Varistor, diameter 7mm, width 4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W5.1mm_P5mm -Varistor, diameter 7mm, width 5.1mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W5.4mm_P5mm -Varistor, diameter 7mm, width 5.4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W5.5mm_P5mm -Varistor, diameter 7mm, width 5.5mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D7mm_W5.7mm_P5mm -Varistor, diameter 7mm, width 5.7mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.3mm_P5mm -Varistor, diameter 9mm, width 3.3mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.4mm_P5mm -Varistor, diameter 9mm, width 3.4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.5mm_P5mm -Varistor, diameter 9mm, width 3.5mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.6mm_P5mm -Varistor, diameter 9mm, width 3.6mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.7mm_P5mm -Varistor, diameter 9mm, width 3.7mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.8mm_P5mm -Varistor, diameter 9mm, width 3.8mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W3.9mm_P5mm -Varistor, diameter 9mm, width 3.9mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W4.1mm_P5mm -Varistor, diameter 9mm, width 4.1mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W4.2mm_P5mm -Varistor, diameter 9mm, width 4.2mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W4.4mm_P5mm -Varistor, diameter 9mm, width 4.4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W4.5mm_P5mm -Varistor, diameter 9mm, width 4.5mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W4.8mm_P5mm -Varistor, diameter 9mm, width 4.8mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W4mm_P5mm -Varistor, diameter 9mm, width 4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W5.2mm_P5mm -Varistor, diameter 9mm, width 5.2mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W5.4mm_P5mm -Varistor, diameter 9mm, width 5.4mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W5.5mm_P5mm -Varistor, diameter 9mm, width 5.5mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W5.7mm_P5mm -Varistor, diameter 9mm, width 5.7mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D9mm_W6.1mm_P5mm -Varistor, diameter 9mm, width 6.1mm, pitch 5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W3.9mm_P7.5mm -Varistor, diameter 12mm, width 3.9mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.2mm_P7.5mm -Varistor, diameter 12mm, width 4.2mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.3mm_P7.5mm -Varistor, diameter 12mm, width 4.3mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.4mm_P7.5mm -Varistor, diameter 12mm, width 4.4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.5mm_P7.5mm -Varistor, diameter 12mm, width 4.5mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.6mm_P7.5mm -Varistor, diameter 12mm, width 4.6mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.7mm_P7.5mm -Varistor, diameter 12mm, width 4.7mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4.8mm_P7.5mm -Varistor, diameter 12mm, width 4.8mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W4mm_P7.5mm -Varistor, diameter 12mm, width 4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W5.1mm_P7.5mm -Varistor, diameter 12mm, width 5.1mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W5.4mm_P7.5mm -Varistor, diameter 12mm, width 5.4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W5.8mm_P7.5mm -Varistor, diameter 12mm, width 5.8mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W5mm_P7.5mm -Varistor, diameter 12mm, width 5mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W6.1mm_P7.5mm -Varistor, diameter 12mm, width 6.1mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W6.2mm_P7.5mm -Varistor, diameter 12mm, width 6.2mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W6.3mm_P7.5mm -Varistor, diameter 12mm, width 6.3mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W6.7mm_P7.5mm -Varistor, diameter 12mm, width 6.7mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W7.1mm_P7.5mm -Varistor, diameter 12mm, width 7.1mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W7.5mm_P7.5mm -Varistor, diameter 12mm, width 7.5mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D12mm_W7.9mm_P7.5mm -Varistor, diameter 12mm, width 7.9mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W3.9mm_P7.5mm -Varistor, diameter 15.5mm, width 3.9mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.2mm_P7.5mm -Varistor, diameter 15.5mm, width 4.2mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.3mm_P7.5mm -Varistor, diameter 15.5mm, width 4.3mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.4mm_P7.5mm -Varistor, diameter 15.5mm, width 4.4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.5mm_P7.5mm -Varistor, diameter 15.5mm, width 4.5mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.6mm_P7.5mm -Varistor, diameter 15.5mm, width 4.6mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.7mm_P7.5mm -Varistor, diameter 15.5mm, width 4.7mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.8mm_P7.5mm -Varistor, diameter 15.5mm, width 4.8mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4.9mm_P7.5mm -Varistor, diameter 15.5mm, width 4.9mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W4mm_P7.5mm -Varistor, diameter 15.5mm, width 4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W5.2mm_P7.5mm -Varistor, diameter 15.5mm, width 5.2mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W5.4mm_P7.5mm -Varistor, diameter 15.5mm, width 5.4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W5.9mm_P7.5mm -Varistor, diameter 15.5mm, width 5.9mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W5mm_P7.5mm -Varistor, diameter 15.5mm, width 5mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W6.1mm_P7.5mm -Varistor, diameter 15.5mm, width 6.1mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W6.3mm_P7.5mm -Varistor, diameter 15.5mm, width 6.3mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W6.4mm_P7.5mm -Varistor, diameter 15.5mm, width 6.4mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W6.8mm_P7.5mm -Varistor, diameter 15.5mm, width 6.8mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W7.2mm_P7.5mm -Varistor, diameter 15.5mm, width 7.2mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W7.5mm_P7.5mm -Varistor, diameter 15.5mm, width 7.5mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W8mm_P7.5mm -Varistor, diameter 15.5mm, width 8mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D15.5mm_W11mm_P7.5mm -Varistor, diameter 15.5mm, width 11mm, pitch 7.5mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D16.5mm_W6.7mm_P7.5mm -Varistor, diameter 16.5mm, width 6.7mm, pitch 5mm, https://katalog.we-online.de/pbs/datasheet/820542711.pdf -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.3mm_P10mm -Varistor, diameter 21.5mm, width 4.3mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.4mm_P10mm -Varistor, diameter 21.5mm, width 4.4mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.5mm_P10mm -Varistor, diameter 21.5mm, width 4.5mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.6mm_P10mm -Varistor, diameter 21.5mm, width 4.6mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.7mm_P10mm -Varistor, diameter 21.5mm, width 4.7mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.8mm_P10mm -Varistor, diameter 21.5mm, width 4.8mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W4.9mm_P10mm -Varistor, diameter 21.5mm, width 4.9mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W5.1mm_P10mm -Varistor, diameter 21.5mm, width 5.1mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W5.3mm_P10mm -Varistor, diameter 21.5mm, width 5.3mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W5.4mm_P10mm -Varistor, diameter 21.5mm, width 5.4mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W5.6mm_P10mm -Varistor, diameter 21.5mm, width 5.6mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W5.8mm_P10mm -Varistor, diameter 21.5mm, width 5.8mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W5mm_P10mm -Varistor, diameter 21.5mm, width 5mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W6.1mm_P7.5mm -varistor -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W6.3mm_P10mm -Varistor, diameter 21.5mm, width 6.3mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W6.5mm_P10mm -Varistor, diameter 21.5mm, width 6.5mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W6.7mm_P10mm -Varistor, diameter 21.5mm, width 6.7mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W6.8mm_P10mm -Varistor, diameter 21.5mm, width 6.8mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W7.1mm_P10mm -Varistor, diameter 21.5mm, width 7.1mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W7.5mm_P10mm -Varistor, diameter 21.5mm, width 7.5mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W7.9mm_P10mm -Varistor, diameter 21.5mm, width 7.9mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W8.4mm_P10mm -Varistor, diameter 21.5mm, width 8.4mm, pitch 10mm -varistor SIOV -0 -2 -2 -Varistor -RV_Disc_D21.5mm_W11.4mm_P10mm -Varistor, diameter 21.5mm, width 11.4mm, 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-http://nimbelink.com/Documentation/Skywire/4G_LTE_Cat_1/30122_NL-SW-LTE-GELS3_Datasheet.pdf - -0 -20 -20 -digikey-footprints -Cellular_Modem_NL-SW-LTE-TSVG - - -0 -20 -20 -digikey-footprints -Coax_Conn_U.FL -https://media.digikey.com/pdf/Data%20Sheets/Hirose%20PDFs/UFL%20Series.pdf - -0 -3 -2 -digikey-footprints -DFN-6_3x3mm_EP1 - - -0 -7 -7 -digikey-footprints -DFN-10_2x2mm -https://media.digikey.com/pdf/Data%20Sheets/NXP%20PDFs/MMA8652FC.pdf - -0 -10 -10 -digikey-footprints -DFN-10_3x3mm -http://cache.freescale.com/files/sensors/doc/data_sheet/MMA7660FC.pdf - -0 -10 -10 -digikey-footprints -DFN-12-1EP_3x3mm -http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_166%20FTDI%20Example%20IC%20PCB%20Footprints.pdf - -0 -13 -13 -digikey-footprints -DIP-4_W7.62mm -http://optoelectronics.liteon.com/upload/download/DS70-2001-026/MOC306X%20series%20201606.pdf - -0 -4 -4 -digikey-footprints -DIP-6_W7.62mm -http://optoelectronics.liteon.com/upload/download/DS70-2001-026/MOC306X%20series%20201606.pdf - -0 -6 -6 -digikey-footprints -DIP-8_W7.62mm -http://media.digikey.com/pdf/Data%20Sheets/Lite-On%20PDFs/6N137%20Series.pdf - -0 -8 -8 -digikey-footprints -DIP-10_W10.16mm - - -0 -10 -10 -digikey-footprints -DIP-14_W3mm - - -0 -14 -14 -digikey-footprints -DIP-16_W7.62mm - - -0 -16 -16 -digikey-footprints -DIP-18_W7.62mm -http://www.ti.com/lit/ds/symlink/tpic6b595.pdf - -0 -18 -18 -digikey-footprints -DIP-20_W7.62mm -http://www.digikey.com/products/en?formaction=on&lang=en&site=us&KeyWords=296-1956-5-ND - -0 -20 -20 -digikey-footprints -DIP-28_W7.62mm -http://www.digikey.com/products/en?formaction=on&lang=en&site=us&KeyWords=296-1956-5-ND - -0 -28 -28 -digikey-footprints -DIP-40_W15.24mm -http://www.ti.com/lit/ds/symlink/tpic6b595.pdf - -0 -40 -40 -digikey-footprints -DO-35 - - -0 -2 -2 -digikey-footprints -DO-35_NK - - -0 -2 -2 -digikey-footprints -DO-41 - - -0 -2 -2 -digikey-footprints -DO-214AB - - -0 -2 -2 -digikey-footprints -DO-214AC - - -0 -2 -2 -digikey-footprints -DSBGA-8_1.6x1.6mm -http://www.ti.com/lit/ds/symlink/tmp006.pdf - -0 -9 -8 -digikey-footprints -DSUB-9_Jack_5747840-3 -http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=5747840&DocType=Customer+Drawing&DocLang=English - -0 -11 -10 -digikey-footprints -DSUB-9_Receptical_A-DF_09_A_KG-T2S -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_4888_CO.pdf - -0 -11 -10 -digikey-footprints -DVI_Female_74320-9004 - - -0 -26 -25 -digikey-footprints -DVI_Female_74320-9010 - - -0 -32 -30 -digikey-footprints -Diode_DO-35_P10mm - - -0 -2 -2 -digikey-footprints -DisplayPort_2040210-1 - - -0 -25 -21 -digikey-footprints -DisplayPort_Mini_2129320-3 - - -0 -24 -21 -digikey-footprints -ESP32-WROOM-32D - - -0 -39 -39 -digikey-footprints -Ethernet_Jack_54602-908LF -http://portal.fciconnect.com/Comergent//fci/drawing/c-bmj-0102.pdf - -0 -8 -8 -digikey-footprints -Ethernet_Jack_ARJC02-111008B -http://www.abracon.com/Magnetics/lan/Ethernet_Jack_ARJC02-111008B.PDF - -0 -12 -12 -digikey-footprints -Ethernet_Jack_RJLSE4208101T -https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJLSE4X0XX01X.pdf - -0 -10 -9 -digikey-footprints -FLIR_Lepton_Socket_1050281001 - - -0 -68 -33 -digikey-footprints -GPS_Module_CAM-M8C-0 - - -0 -31 -31 -digikey-footprints -GSM_Module_17.8x16.5mm_A2235-H - - -0 -30 -23 -digikey-footprints -Gas_Sensor_110-109 - - -0 -10 -10 -digikey-footprints -Gas_Sensor_110-202 -http://www.spec-sensors.com/wp-content/uploads/2016/02/3SP_Ethanol_1000-P-Package-Gas_Sensor_110-202.pdf - -0 -6 -6 -digikey-footprints -HDMI_A_Female_2000-1-2-41-00-BK -http://media.digikey.com/pdf/Data%20Sheets/CNC%20Tech%20PDFs/HDMI_A_Female_2000-1-2-41-00-BK_Dwg.pdf - -0 -25 -20 -digikey-footprints -HDMI_Female_DC3RX19JA3R1700 - - -0 -23 -20 -digikey-footprints -HDMI_Mini_Female_2001-1-2-21-00-BK - - -0 -23 -20 -digikey-footprints -HTQFP-100_14x14mm - - -0 -182 -101 -digikey-footprints -Hall_Sensor_SIP-3_A132_LUA-T -file:///C:/Users/chad_rosencrans/Downloads/A1324-5-6-Datasheet%20(1).pdf - -0 -3 -3 -digikey-footprints -HeaderPin_2x2_P4.2_Drill1.4mm -http://www.molex.com/pdm_docs/sd/039281043_sd.pdf - -0 -4 -4 -digikey-footprints -Headphone_Jack_2.5mm_SJ1-2503A -http://www.cui.com/product/resource/sj1-2503a.pdf - -0 -4 -4 -digikey-footprints -Headphone_Jack_3.5mm_SJ1-3523N -http://www.cui.com/product/resource/sj1-352xn-series.pdf - -0 -3 -3 -digikey-footprints -Headphone_Jack_6.35mm_RA49B14B - - -0 -5 -5 -digikey-footprints -Headphone_Jack_6.35mm_SN49B12B - - -0 -3 -3 -digikey-footprints -Humidity_HIH-4030 - - -0 -4 -4 -digikey-footprints -Humidity_HIH61xx - - -0 -8 -8 -digikey-footprints -Humidity_SHT15 -https://www.sensirion.com/fileadmin/user_upload/customers/sensirion/Dokumente/2_Humidity_Sensors/Sensirion_Humidity_Sensors_SHT1x_Datasheet_V5.pdf - -0 -8 -8 -digikey-footprints -ICL_THT_P7.8mm -https://www.ametherm.com/datasheetspdf/SL322R025.pdf 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-http://optoelectronics.liteon.com/upload/download/DS20-2000-343/1CHKxKNN.pdf - -0 -2 -2 -digikey-footprints -LED_7Seg_VAOS-C402S9-BW_50 - - -0 -10 -10 -digikey-footprints -LED_0603 - - -0 -2 -2 -digikey-footprints -LED_Bar_Graph_LTA-1000 - - -0 -20 -20 -digikey-footprints -LED_Breakout_Parallax_WS2812B -https://www.parallax.com/product/28086 - -0 -6 -6 -digikey-footprints -LED_Dual0603 -http://optoelectronics.liteon.com/upload/download/DS22-2008-0044/LTST-C19HE1WT.pdf - -0 -4 -4 -digikey-footprints -LED_IR_TSAL6100 - - -0 -2 -2 -digikey-footprints -LED_RGB_WP154A4SUREQBFZGC -http://www.kingbrightusa.com/images/catalog/SPEC/WP154A4SUREQBFZGC.pdf - -0 -4 -4 -digikey-footprints -LFQFN-16-1EP_3x3mm - - -0 -17 -17 -digikey-footprints -LFQFN-16-1EP_4x4mm - - -0 -17 -17 -digikey-footprints -LGA-8_2x2.5mm_BMP280 - - -0 -8 -8 -digikey-footprints -LGA-12_4.8x2.8_VL6180 -http://www.st.com/content/ccc/resource/technical/document/datasheet/c4/11/28/86/e6/26/44/b3/DM00112632.pdf/files/DM00112632.pdf/jcr:content/translations/en.DM00112632.pdf - -0 -12 -12 -digikey-footprints -LGA-12_9x9mm_LSM303C -http://www.st.com/content/ccc/resource/technical/document/datasheet/59/aa/fb/3b/85/9e/4e/0a/DM00089896.pdf/files/DM00089896.pdf/jcr:content/translations/en.DM00089896.pdf - -0 -12 -12 -digikey-footprints -LGA-14L_2.5x3mm__LSM6DS3 -http://www.st.com/content/ccc/resource/technical/document/datasheet/a3/f5/4f/ae/8e/44/41/d7/DM00133076.pdf/files/DM00133076.pdf/jcr:content/translations/en.DM00133076.pdf - -0 -14 -14 -digikey-footprints -LGA-14_2x2mm -http://www.st.com/content/ccc/resource/technical/document/datasheet/c1/e1/62/31/d2/b1/4d/bb/DM00042751.pdf/files/DM00042751.pdf/jcr:content/translations/en.DM00042751.pdf - -0 -14 -14 -digikey-footprints -LGA-14_3x5mm_RevA -http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL343.pdf - -0 -14 -14 -digikey-footprints -LGA-24_3x3.5mm_LSM9DS1 -http://www.st.com/content/ccc/resource/technical/document/datasheet/1e/3f/2a/d6/25/eb/48/46/DM00103319.pdf/files/DM00103319.pdf/jcr:content/translations/en.DM00103319.pdf - -0 -24 -24 -digikey-footprints -LGA-28_5.2x3.8mm_BNO0055 - - -0 -28 -28 -digikey-footprints -LLC-36_9x9mm_HMC6343 - - -0 -36 -36 -digikey-footprints -LLGA-10_2.5x2.5mm_LPS25HB -http://www.st.com/content/ccc/resource/technical/document/datasheet/9a/4c/aa/72/1f/45/4e/24/DM00141379.pdf/files/DM00141379.pdf/jcr:content/translations/en.DM00141379.pdf - -0 -10 -10 -digikey-footprints -LORA_Module_RM103 -http://ww1.microchip.com/downloads/en/DeviceDoc/50002346C.pdf - -0 -47 -47 -digikey-footprints -LQFP-32_7x7mm - - -0 -32 -32 -digikey-footprints -LQFP-48_7x7mm -http://wizwiki.net/wiki/lib/exe/fetch.php?media=products:w5500:w5500_ds_v106e_141230.pdf - -0 -48 -48 -digikey-footprints -LQFP-64_10x10mm - - -0 -64 -64 -digikey-footprints -LQFP-100_14x14mm - - -0 -100 -100 -digikey-footprints -LSOJ-6_W3.76mm -http://pdfserv.maximintegrated.com/package_dwgs/21-0382.PDF - -0 -6 -6 -digikey-footprints -LSSOP-24_W5.6mm -file:///C:/Users/alex_wegscheid/Downloads/TB6612FNG_datasheet_en_20141001%20(7).pdf - -0 -24 -24 -digikey-footprints -Light_to_Freq_TSL235R-LF -file:///C:/Users/alex_wegscheid/Downloads/TSL235R_DS000120_2-00%20(6).pdf - -0 -3 -3 -digikey-footprints -MSOP-8-1EP_W3mm -http://www.ti.com/lit/ds/symlink/tpa2005d1-q1.pdf - -0 -14 -9 -digikey-footprints -MSOP-8_W2.80mm - - -0 -8 -8 -digikey-footprints -MSOP-10-1EP_W3mm - - -0 -11 -11 -digikey-footprints -MSOP-10_W3mm - - -0 -10 -10 -digikey-footprints -MSOP-12-1EP_W3mm - - -0 -13 -13 -digikey-footprints -Mag_Jack_Module_WIZ820IO -http://wiznethome.cafe24.com/wp-content/uploads/wiznethome/Network%20Module/WIZ820io/Document/WIZ820io_User_Manual_V1.0.pdf - -0 -12 -12 -digikey-footprints -Mic_CMA-4544PF-W - - -0 -2 -2 -digikey-footprints -MicroSD_2908-05WB-MG - - -0 -12 -9 -digikey-footprints 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-http://www.osram-os.com/Graphics/XPic1/00211421_0.pdf - -0 -2 -2 -digikey-footprints -Photodiode_THT_BPW34 - - -0 -2 -2 -digikey-footprints -Phototransistor_4.4x1.5mm_P2.54_Radial -http://optoelectronics.liteon.com/upload/download/DS20-2000-343/1CHKxKNN.pdf - -0 -2 -2 -digikey-footprints -Phototransistor_SMD_4x2mm_TEMT6000X01 - - -0 -3 -3 -digikey-footprints -Piezo_9x9mm_PKMCS0909E4000-R1 - - -0 -2 -2 -digikey-footprints -Piezo_Transducer_THT_PS1240P02BT - - -0 -2 -2 -digikey-footprints -PinHeader_1x2_P2.5mm_Drill1.1mm -http://www.jst-mfg.com/product/pdf/eng/eXH.pdf - -0 -2 -2 -digikey-footprints -PinHeader_1x2_P2.54mm - - -0 -2 -2 -digikey-footprints -PinHeader_1x2_P2.54mm_Drill1.02mm -http://www.molex.com/pdm_docs/sd/022232031_sd.pdf - -0 -2 -2 -digikey-footprints -PinHeader_1x2_P2mm -http://www.jst-mfg.com/product/pdf/eng/ePH.pdf - -0 -4 -2 -digikey-footprints -PinHeader_1x2_P2mm_Drill1mm -http://www.jst-mfg.com/product/pdf/eng/ePH.pdf - -0 -2 -2 -digikey-footprints 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-http://www.molex.com/pdm_docs/sd/878322620_sd.pdf - -0 -14 -14 -digikey-footprints -PinHeader_6x2_P2.54mm_Horizontal -http://portal.fciconnect.com/Comergent//fci/drawing/68020.pdf - -0 -12 -12 -digikey-footprints -PinHeader_6x2_P2.54mm_Vertical -http://portal.fciconnect.com/Comergent//fci/drawing/68020.pdf - -0 -12 -12 -digikey-footprints -Potentiometer_P120PK-Y25BR10K - - -0 -5 -4 -digikey-footprints -PowerSOIC-8_W3.9mm - - -0 -16 -9 -digikey-footprints -Pressure_Sensor_LGA-8_2.5x2.5mm_BME280 - - -0 -8 -8 -digikey-footprints -PushButton_12x12mm_THT_GPTS203211B - - -0 -2 -2 -digikey-footprints -PushButton_Round_D12mm_THT_KS-01Q-01 -http://spec_sheets.e-switch.com/specs/29-KS01Q01.pdf - -0 -4 -4 -digikey-footprints -QFN-10-1EP_3x3mm - - -0 -11 -11 -digikey-footprints -QFN-20-1EP_3x3mm - - -0 -37 -21 -digikey-footprints -QFN-20-1EP_4x4mm - - -0 -37 -21 -digikey-footprints -QFN-20-1EP_4x4mm_RevA - - -0 -21 -21 -digikey-footprints -QFN-24-1EP_3x3mm - - -0 -25 -25 -digikey-footprints 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-https://power.murata.com/data/power/oki-78sr.pdf - -0 -3 -3 -digikey-footprints -SIP-4_W3.81mm -https://www.diodes.com/assets/Datasheets/ds21203.pdf - -0 -4 -4 -digikey-footprints -SIP-9_P2.54mm -http://www.bourns.com/docs/Product-Datasheets/4600x.pdf - -0 -9 -9 -digikey-footprints -SMD-2_3.2x1.5mm -http://www.ecsxtal.com/store/pdf/ecx-31b.pdf - -0 -2 -2 -digikey-footprints -SMD-2_3.2x2.5mm -http://www.ndk.com/images/products/catalog/c_NX3225GD-STD-CRA-3_e.pdf - -0 -2 -2 -digikey-footprints -SMD-4_3.3x2.8_PD15-22C_TR8 - - -0 -4 -2 -digikey-footprints -SMD-4_3.4x2.7mm_P1.8mm -https://www.fairchildsemi.com/datasheets/QR/QRE1113.pdf - -0 -4 -4 -digikey-footprints -SMD-4_4.4x3.85mm_P2.54mm -http://optoelectronics.liteon.com/upload/download/DS70-2001-010/LTV-356T%20series%20201610.pdf - -0 -4 -4 -digikey-footprints -SMD-4_4.6x7.62mm_P2.54mm -https://media.digikey.com/pdf/Data%20Sheets/Lite-On%20PDFs/LTV-816_826_846.pdf - -0 -4 -4 -digikey-footprints -SMD-4_5x4.4mm_P4mm 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-http://www.st.com/content/ccc/resource/technical/document/datasheet/9a/e6/1c/4f/b6/9a/44/e6/CD00047494.pdf/files/CD00047494.pdf/jcr:content/translations/en.CD00047494.pdf - -0 -6 -6 -digikey-footprints -SPH0645LM4H-B -http://www.digikey.com/products/en?keywords=423-1405-1-ND - -0 -9 -6 -digikey-footprints -SSOP-16_W3.90mm - - -0 -16 -16 -digikey-footprints -SSOP-20_W3.9mm -http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT231X.pdf - -0 -20 -20 -digikey-footprints -SSOP-20_W5.3mm -http://ww1.microchip.com/downloads/en/DeviceDoc/41606B.pdf - -0 -20 -20 -digikey-footprints -SSOP-24_W5.30mm - - -0 -24 -24 -digikey-footprints -SSOP-28_W5.30mm - - -0 -28 -28 -digikey-footprints -SiTIME_SMD-6-1EP -https://www.sitime.com/products/datasheets/sit9102/SiT9102-datasheet.pdf - -0 -7 -7 -digikey-footprints -Smoke_Sensor_MAX30105EFD+ -http://datasheets.maximintegrated.com/en/ds/MAX30105.pdf - -0 -14 -14 -digikey-footprints -Socket_DIP-14_7.62mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -14 -14 -digikey-footprints -Socket_DIP-16_7.62mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -16 -16 -digikey-footprints -Socket_DIP-18_7.62mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -18 -18 -digikey-footprints -Socket_DIP-20_7.62mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -20 -20 -digikey-footprints -Socket_DIP-24_7.62mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -24 -24 -digikey-footprints -Socket_DIP-24_15.24mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -24 -24 -digikey-footprints -Socket_DIP-28_7.62mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -28 -28 -digikey-footprints -Socket_DIP-28_15.24mm_Conn -http://www.assmann-wsw.com/fileadmin/datasheets/ASS_0810_CO.pdf - -0 -28 -28 -digikey-footprints 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-WIFI_Module_ESP8266_2491 -http://media.digikey.com/pdf/Data%20Sheets/Adafruit%20PDFs/ESP-12S_UM%20_Rev1.0_8-1-16.pdf - -0 -16 -16 -digikey-footprints -WIFI_Module_WF111-E-V1 -http://media.digikey.com/pdf/Data%20Sheets/BlueGiga%20PDFs/WF111.pdf - -0 -33 -33 -digikey-footprints -WIFI_Module_WF121-A-V2 - - -0 -55 -55 -digikey-footprints -WQFN-16-1EP_4x4mm -http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT230X.pdf - -0 -17 -17 -digikey-footprints -WQFN-20-1EP_4x4mm -http://www.ti.com/lit/ds/symlink/tpa2016d2.pdf - -0 -50 -21 -digikey-footprints -WQFN-24-1EP_4x4mm - - -0 -25 -25 -digikey-footprints -WSON-8_2x2mm -http://www.ti.com/lit/ds/symlink/drv8837.pdf - -0 -11 -9 -digikey-footprints -WiFi_Module_MRF24WG0MA - - -0 -36 -36 -digikey-footprints -Wifi_Module_ESP8266_WRL-13678 - - -0 -8 -8 -digikey-footprints -Wifi_Module_RN171 - - -0 -52 -50 -digikey-footprints -WizNet_Module_WIZ810MJ -http://wiznethome.cafe24.com/wp-content/uploads/wiznethome/Network%20Module/WIZ8XXMJ/Document/WIZ810MJ_DS_V130E.pdf - -0 -56 -56 -digikey-footprints -XBEE-20_THT -https://www.digi.com/pdf/ds_xbeemultipointmodules.pdf - -0 -20 -20 -digikey-footprints -XBEE_PRO-20_THT - - -0 -20 -20 -digikey-footprints -XBEE_and_XBEE-PRO_37_SMD - - -0 -74 -37 -digikey-footprints -XDFN-2_1x0.60mm - - -0 -2 -2 -digikey-footprints -Zigbee_Module_MRF24J40MA -http://ww1.microchip.com/downloads/en/DeviceDoc/70329b.pdf - -0 -12 -12 -digikey-footprints -Zigbee_Module_MRF24J40MD - - -0 -12 -12 -penguin -ATSAMD21J18A - - -0 -64 -64 -penguin -MPU-9250 - - -0 -25 -25 -penguin -MS8607 - - -0 -8 -8 -penguin -PinHeaderBlockArduino -Through hole straight pin header, 2x19, 2.54mm pitch, double rows -Through hole pin header THT 2x19 2.54mm double row -0 -38 -38 -penguin -QFN40P300X300X105-25N - - -0 -25 -25 -penguin -QFP40P1600X1600X120-128N_ATSAME54P20A - - -0 -128 -128 -penguin -QFP80P1600X1600X120-64N - - -0 -64 -64 -penguin -TE_MS860702BA01-50 - - -0 -8 -8 -penguin -finaltesthopefully - - -0 -0 -0 -penguin -ggsgfdsgfdg - - -0 -0 -0 -penguin -penguinkicad - - -0 -0 -0 -penguin -penguinlogo - - -0 -0 -0 -penguin -penguinlogofinal - - -0 -0 -0 -penguin -pin_array - - -0 -0 -0 -penguin -test2 - - -0 -0 -0 -penguin -test3 - - -0 -0 -0 -penguin -test4 - - -0 -0 -0 -penguin -test5 - - -0 -0 -0 -penguin -test6 - - -0 -0 -0 -penguin -test7 - - -0 -0 -0 -penguin -test8 - - -0 -0 -0 -penguin -test9 - - -0 -0 -0 -penguin -test10 - - -0 -0 -0 -penguin -test11 - - -0 -0 -0 -penguin -test12 - - -0 -0 -0 -penguin -test13 - - -0 -0 -0 -penguin -test14 - - -0 -0 -0 -penguin -test15 - - -0 -0 -0 -penguin -test99 - - -0 -0 -0 -penguin -test100 - - -0 -0 -0 -penguin -test101 - - -0 -0 -0 -penguin -test102 - - -0 -0 -0 -penguin -test103 - - -0 -0 -0 -penguin -test104 - - -0 -0 -0 -penguin -test105 - - -0 -0 -0 -penguin -test106 - - -0 -0 -0 -proj_modules -SOP80P1030X264-36N - - -0 -36 -36 +17824947138230346 +Battery +BatteryHolder_Bulgin_BX0036_1xC +Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf) +Bulgin BX0036 +0 +2 +2 +Battery +BatteryHolder_ComfortableElectronic_CH273-2450_1x2450 +Comfortable Electronic CR2450 battery holder, http://www.comf.com.tw/ProductDetail.asp?no=148 +Comfortable Electronic CR2450 +0 +2 +2 +Battery +BatteryHolder_Eagle_12BH611-GR +https://eu.mouser.com/datasheet/2/209/EPD-200766-1274481.pdf +9V Battery Holder +0 +2 +2 +Battery +BatteryHolder_Keystone_103_1x20mm +http://www.keyelco.com/product-pdf.cfm?p=719 +Keystone type 103 battery holder +0 +2 +2 +Battery +BatteryHolder_Keystone_104_1x23mm +http://www.keyelco.com/product-pdf.cfm?p=744 +Keystone type 104 battery holder +0 +2 +2 +Battery +BatteryHolder_Keystone_105_1x2430 +http://www.keyelco.com/product-pdf.cfm?p=745 +Keystone type 105 battery holder +0 +2 +2 +Battery +BatteryHolder_Keystone_106_1x20mm +http://www.keyelco.com/product-pdf.cfm?p=720 +Keystone type 106 battery holder +0 +2 +2 +Battery +BatteryHolder_Keystone_107_1x23mm +http://www.keyelco.com/product-pdf.cfm?p=746 +Keystone type 107 battery holder +0 +2 +2 +Battery +BatteryHolder_Keystone_500 +Keystone #500, CR1220 battery holder, http://www.keyelco.com/product-pdf.cfm?p=710 +CR1220 battery holder +0 +2 +2 +Battery +BatteryHolder_Keystone_1042_1x18650 +Battery holder for 18650 cylindrical cells http://www.keyelco.com/product.cfm/product_id/918 +18650 Keystone 1042 Li-ion +0 +2 +2 +Battery +BatteryHolder_Keystone_1058_1x2032 +http://www.keyelco.com/product-pdf.cfm?p=14028 +Keystone type 1058 coin cell retainer +0 +2 +2 +Battery +BatteryHolder_Keystone_1060_1x2032 +http://www.keyelco.com/product-pdf.cfm?p=726 +CR2032 BR2032 BatteryHolder Battery +0 +2 +2 +Battery +BatteryHolder_Keystone_2460_1xAA +https://www.keyelco.com/product-pdf.cfm?p=1025 +AA battery cell holder +0 +2 +2 +Battery +BatteryHolder_Keystone_2462_2xAA +2xAA cell battery holder, Keystone P/N 2462, https://www.keyelco.com/product-pdf.cfm?p=1027 +AA battery cell holder +0 +2 +2 +Battery +BatteryHolder_Keystone_2466_1xAAA +1xAAA Battery Holder, Keystone, Plastic Case, http://www.keyelco.com/product-pdf.cfm?p=1031 +AAA battery holder Keystone +0 +2 +2 +Battery +BatteryHolder_Keystone_2468_2xAAA +2xAAA cell battery holder, Keystone P/N 2468, http://www.keyelco.com/product-pdf.cfm?p=1033 +AAA battery cell holder +0 +2 +2 +Battery +BatteryHolder_Keystone_2479_3xAAA +3xAAA cell battery holder, Keystone P/N 2479, http://www.keyelco.com/product-pdf.cfm?p=1041 +AAA battery cell holder +0 +2 +2 +Battery +BatteryHolder_Keystone_2993 +http://www.keyelco.com/product-pdf.cfm?p=776 +Keystone type 2993 negative battery contact +0 +1 +1 +Battery +BatteryHolder_Keystone_3000_1x12mm +http://www.keyelco.com/product-pdf.cfm?p=777 +Keystone type 3000 coin cell retainer +0 +3 +2 +Battery +BatteryHolder_Keystone_3001_1x12mm +http://www.keyelco.com/product-pdf.cfm?p=778 +Keystone type 3001 coin cell retainer +0 +3 +2 +Battery +BatteryHolder_Keystone_3002_1x2032 +https://www.tme.eu/it/Document/a823211ec201a9e209042d155fe22d2b/KEYS2996.pdf +BR2016 CR2016 DL2016 BR2020 CL2020 BR2025 CR2025 DL2025 DR2032 CR2032 DL2032 +0 +3 +2 +Battery +BatteryHolder_Keystone_3008_1x2450 +http://www.keyelco.com/product-pdf.cfm?p=786 +Keystone type 3008 coin cell retainer +0 +3 +2 +Battery +BatteryHolder_Keystone_3009_1x2450 +http://www.keyelco.com/product-pdf.cfm?p=787 +Keystone type 3009 coin cell retainer +0 +3 +2 +Battery +BatteryHolder_Keystone_3034_1x20mm +Keystone 3034 SMD battery holder for 2020, 2025 and 2032 coincell batteries. http://www.keyelco.com/product-pdf.cfm?p=798 +Keystone type 3034 coin cell retainer +0 +3 +2 +Battery +BatteryHolder_LINX_BAT-HLD-012-SMT +SMT battery holder for CR1216/1220/1225, https://linxtechnologies.com/wp/wp-content/uploads/bat-hld-012-smt.pdf +battery holder coin cell cr1216 cr1220 cr1225 +0 +3 +2 +Battery +BatteryHolder_MPD_BC2AAPC_2xAA +2xAA cell battery holder, Memory Protection Devices P/N BC2AAPC, http://www.memoryprotectiondevices.com/datasheets/BC2AAPC-datasheet.pdf +AA battery cell holder +0 +2 +2 +Battery +BatteryHolder_MPD_BC12AAPC_2xAA +2xAA cell battery holder, Memory Protection Devices P/N BC12AAPC, http://www.memoryprotectiondevices.com/datasheets/BC12AAPC-datasheet.pdf +AA battery cell holder +0 +2 +2 +Battery +BatteryHolder_MPD_BC2003_1x2032 +http://www.memoryprotectiondevices.com/datasheets/BC-2003-datasheet.pdf +BC2003 CR2032 2032 Battery Holder +0 +3 +2 +Battery +BatteryHolder_MPD_BH-18650-PC2 +18650 Battery Holder (http://www.memoryprotectiondevices.com/datasheets/BK-18650-PC2-datasheet.pdf) +18650 Battery Holder +0 +2 +2 +Battery +BatteryHolder_Seiko_MS621F +Seiko MS621F, https://www.sii.co.jp/en/me/files/2014/02/file_EXTENDED_PRDCT_SPEC_75_FILE_11.jpg +Seiko MS621F +0 +2 +2 +Battery +BatteryHolder_TruPower_BH-331P_3xAA +Keystone Battery Holder BH-331P Battery Type 3xAA (Script generated with StandardBox.py) (Keystone Battery Holder BH-331P Battery Type 3xAA) +Battery Holder BH-331P Battery Type 3xAA +0 +2 +2 +Battery +Battery_CR1225 +CR1225 battery +battery CR1225 coin cell +0 +0 +0 +Battery +Battery_Panasonic_CR1025-VSK_Vertical_CircularHoles +Panasonic CR-1025/VSK battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-1025 coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR1220-VCN_Vertical_CircularHoles +Panasonic CR-1220/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-1220 coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR1632-V1AN_Vertical_CircularHoles +Panasonic CR-1632-V1AN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-1632 coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR2025-V1AK_Vertical_CircularHoles +Panasonic CR-2025/V1AK battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-2025 coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR2032-VS1N_Vertical_CircularHoles +Panasonic CR-2032/VS1N battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-2032 coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR2354-VCN_Vertical_CircularHoles +Panasonic CR-2354/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-2354/VCN coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR2450-VAN_Vertical_CircularHoles +Panasonic CR-2450/VAN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-2450 coin cell +0 +2 +2 +Battery +Battery_Panasonic_CR2477-VCN_Vertical_CircularHoles +Panasonic CR-2477/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-2477 coin cell vertical +0 +2 +2 +Battery +Battery_Panasonic_CR3032-VCN_Vertical_CircularHoles +Panasonic CR-3032/VCN battery, https://industrial.panasonic.com/cdbs/www-data/pdf2/AAA4000/AAA4000D140.pdf +battery CR-3032 coin cell vertical +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.00u_PCB +Cherry MX keyswitch, 1.00u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.00u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.00u_Plate +Cherry MX keyswitch, 1.00u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.00u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.25u_PCB +Cherry MX keyswitch, 1.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.25u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.25u_Plate +Cherry MX keyswitch, 1.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.25u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.50u_PCB +Cherry MX keyswitch, 1.50u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.50u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.50u_Plate +Cherry MX keyswitch, 1.50u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.50u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.75u_PCB +Cherry MX keyswitch, 1.75u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.75u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_1.75u_Plate +Cherry MX keyswitch, 1.75u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 1.75u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.00u_PCB +Cherry MX keyswitch, 2.00u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.00u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.00u_Plate +Cherry MX keyswitch, 2.00u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.00u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.00u_Vertical_PCB +Cherry MX keyswitch, 2.00u, vertical, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.00u vertical PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.00u_Vertical_Plate +Cherry MX keyswitch, 2.00u, vertical, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.00u vertical plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.25u_PCB +Cherry MX keyswitch, 2.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.25u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.25u_Plate +Cherry MX keyswitch, 2.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.25u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.75u_PCB +Cherry MX keyswitch, 2.75u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.75u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_2.75u_Plate +Cherry MX keyswitch, 2.75u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 2.75u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_6.25u_PCB +Cherry MX keyswitch, 6.25u, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 6.25u PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_6.25u_Plate +Cherry MX keyswitch, 6.25u, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch 6.25u plate +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_ISOEnter_PCB +Cherry MX keyswitch, ISO Enter, PCB mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch ISO enter PCB +0 +2 +2 +Button_Switch_Keyboard +SW_Cherry_MX_ISOEnter_Plate +Cherry MX keyswitch, ISO Enter, plate mount, http://cherryamericas.com/wp-content/uploads/2014/12/mx_cat.pdf +Cherry MX keyswitch ISO enter plate +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_1.00u +Matias/ALPS keyswitch, 1.00u, http://matias.ca/switches/ +Matias ALPS keyswitch 1.00u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_1.25u +Matias/ALPS keyswitch, 1.25u, http://matias.ca/switches/ +Matias ALPS keyswitch 1.25u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_1.50u +Matias/ALPS keyswitch, 1.50u, http://matias.ca/switches/ +Matias ALPS keyswitch 1.50u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_1.75u +Matias/ALPS keyswitch, 1.75u, http://matias.ca/switches/ +Matias ALPS keyswitch 1.75u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_2.00u +Matias/ALPS keyswitch, 2.00u, http://matias.ca/switches/ +Matias ALPS keyswitch 2.00u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_2.25u +Matias/ALPS keyswitch, 2.25u, http://matias.ca/switches/ +Matias ALPS keyswitch 2.25u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_2.75u +Matias/ALPS keyswitch, 2.75u, http://matias.ca/switches/ +Matias ALPS keyswitch 2.75u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_6.25u +Matias/ALPS keyswitch, 6.25u, http://matias.ca/switches/ +Matias ALPS keyswitch 6.25u +0 +2 +2 +Button_Switch_Keyboard +SW_Matias_ISOEnter +Matias/ALPS keyswitch, ISO Enter, http://matias.ca/switches/ +Matias ALPS keyswitch ISO enter +0 +2 +2 +Button_Switch_SMD +Nidec_Copal_SH-7010A +4-bit rotary coded switch, J-hook, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf +rotary switch bcd +0 +6 +5 +Button_Switch_SMD +Nidec_Copal_SH-7010B +4-bit rotary coded switch, gull wing, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf +rotary switch bcd +0 +6 +5 +Button_Switch_SMD +Nidec_Copal_SH-7040B +4-bit rotary coded switch, gull wing, Gray code, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf +rotary switch bcd +0 +5 +5 +Button_Switch_SMD +Panasonic_EVQPUJ_EVQPUA +http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf +SMD SMT SPST EVQPUJ EVQPUA +0 +4 +2 +Button_Switch_SMD +Panasonic_EVQPUK_EVQPUB +http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf +SMD SMT SPST EVQPUK EVQPUB +0 +4 +2 +Button_Switch_SMD +Panasonic_EVQPUL_EVQPUC +http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf +SMD SMT SPST EVQPUL EVQPUC +0 +4 +2 +Button_Switch_SMD +Panasonic_EVQPUM_EVQPUD +http://industrial.panasonic.com/cdbs/www-data/pdf/ATV0000/ATV0000CE5.pdf +SMD SMT SPST EVQPUM EVQPUD +0 +4 +2 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_6.7x4.1mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 1x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +2 +2 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_6.7x4.1mm_W8.61mm_P2.54mm_LowProfile +SMD 1x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +2 +2 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_9.78x4.72mm_W8.61mm_P2.54mm +SMD 1x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x4.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +2 +2 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_Copal_CHS-01A_W5.08mm_P1.27mm_JPin +SMD 1x-dip-switch SPST Copal_CHS-01A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin +SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin +0 +2 +2 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_Copal_CHS-01B_W7.62mm_P1.27mm +SMD 1x-dip-switch SPST Copal_CHS-01B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD +SMD DIP Switch SPST Slide 7.62mm 300mil SMD +0 +2 +2 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_Copal_CVS-01xB_W5.9mm_P1mm +SMD 1x-dip-switch SPST Copal_CVS-01xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) +SMD DIP Switch SPST Slide 5.9mm 232mil +0 +6 +3 +Button_Switch_SMD +SW_DIP_SPSTx01_Slide_Omron_A6S-110x_W8.9mm_P2.54mm +SMD 1x-dip-switch SPST Omron_A6S-110x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +2 +2 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_6.7x6.64mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 2x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_6.7x6.64mm_W8.61mm_P2.54mm_LowProfile +SMD 2x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_9.78x7.26mm_W8.61mm_P2.54mm +SMD 2x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x7.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_Copal_CHS-02A_W5.08mm_P1.27mm_JPin +SMD 2x-dip-switch SPST Copal_CHS-02A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin +SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_Copal_CHS-02B_W7.62mm_P1.27mm +SMD 2x-dip-switch SPST Copal_CHS-02B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD +SMD DIP Switch SPST Slide 7.62mm 300mil SMD +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_Copal_CVS-02xB_W5.9mm_P1mm +SMD 2x-dip-switch SPST Copal_CVS-02xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) +SMD DIP Switch SPST Slide 5.9mm 232mil +0 +8 +5 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_KingTek_DSHP02TJ_W5.25mm_P1.27mm_JPin +SMD 2x-dip-switch SPST KingTek_DSHP02TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_KingTek_DSHP02TS_W7.62mm_P1.27mm +SMD 2x-dip-switch SPST KingTek_DSHP02TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_Omron_A6H-2101_W6.15mm_P1.27mm +SMD 2x-dip-switch SPST Omron_A6H-2101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) +SMD DIP Switch SPST Slide 6.15mm 242mil +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx02_Slide_Omron_A6S-210x_W8.9mm_P2.54mm +SMD 2x-dip-switch SPST Omron_A6S-210x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +4 +4 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_6.7x9.18mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 3x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +6 +6 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_6.7x9.18mm_W8.61mm_P2.54mm_LowProfile +SMD 3x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +6 +6 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_9.78x9.8mm_W8.61mm_P2.54mm +SMD 3x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x9.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +6 +6 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_Copal_CVS-03xB_W5.9mm_P1mm +SMD 3x-dip-switch SPST Copal_CVS-03xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) +SMD DIP Switch SPST Slide 5.9mm 232mil +0 +10 +7 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_KingTek_DSHP03TJ_W5.25mm_P1.27mm_JPin +SMD 3x-dip-switch SPST KingTek_DSHP03TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +6 +6 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_KingTek_DSHP03TS_W7.62mm_P1.27mm +SMD 3x-dip-switch SPST KingTek_DSHP03TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +6 +6 +Button_Switch_SMD +SW_DIP_SPSTx03_Slide_Omron_A6S-310x_W8.9mm_P2.54mm +SMD 3x-dip-switch SPST Omron_A6S-310x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +6 +6 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_6.7x11.72mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 4x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_6.7x11.72mm_W8.61mm_P2.54mm_LowProfile +SMD 4x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_9.78x12.34mm_W8.61mm_P2.54mm +SMD 4x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x12.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_Copal_CHS-04A_W5.08mm_P1.27mm_JPin +SMD 4x-dip-switch SPST Copal_CHS-04A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin +SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_Copal_CHS-04B_W7.62mm_P1.27mm +SMD 4x-dip-switch SPST Copal_CHS-04B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD +SMD DIP Switch SPST Slide 7.62mm 300mil SMD +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_Copal_CVS-04xB_W5.9mm_P1mm +SMD 4x-dip-switch SPST Copal_CVS-04xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) +SMD DIP Switch SPST Slide 5.9mm 232mil +0 +12 +9 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_KingTek_DSHP04TJ_W5.25mm_P1.27mm_JPin +SMD 4x-dip-switch SPST KingTek_DSHP04TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_KingTek_DSHP04TS_W7.62mm_P1.27mm +SMD 4x-dip-switch SPST KingTek_DSHP04TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_Omron_A6H-4101_W6.15mm_P1.27mm +SMD 4x-dip-switch SPST Omron_A6H-4101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) +SMD DIP Switch SPST Slide 6.15mm 242mil +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx04_Slide_Omron_A6S-410x_W8.9mm_P2.54mm +SMD 4x-dip-switch SPST Omron_A6S-410x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +8 +8 +Button_Switch_SMD +SW_DIP_SPSTx05_Slide_6.7x14.26mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 5x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +10 +10 +Button_Switch_SMD +SW_DIP_SPSTx05_Slide_6.7x14.26mm_W8.61mm_P2.54mm_LowProfile +SMD 5x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +10 +10 +Button_Switch_SMD +SW_DIP_SPSTx05_Slide_9.78x14.88mm_W8.61mm_P2.54mm +SMD 5x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x14.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +10 +10 +Button_Switch_SMD +SW_DIP_SPSTx05_Slide_KingTek_DSHP05TJ_W5.25mm_P1.27mm_JPin +SMD 5x-dip-switch SPST KingTek_DSHP05TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +10 +10 +Button_Switch_SMD +SW_DIP_SPSTx05_Slide_KingTek_DSHP05TS_W7.62mm_P1.27mm +SMD 5x-dip-switch SPST KingTek_DSHP05TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +10 +10 +Button_Switch_SMD +SW_DIP_SPSTx05_Slide_Omron_A6S-510x_W8.9mm_P2.54mm +SMD 5x-dip-switch SPST Omron_A6S-510x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +10 +10 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_6.7x16.8mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 6x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_6.7x16.8mm_W8.61mm_P2.54mm_LowProfile +SMD 6x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_9.78x17.42mm_W8.61mm_P2.54mm +SMD 6x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_Copal_CHS-06A_W5.08mm_P1.27mm_JPin +SMD 6x-dip-switch SPST Copal_CHS-06A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin +SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_Copal_CHS-06B_W7.62mm_P1.27mm +SMD 6x-dip-switch SPST Copal_CHS-06B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD +SMD DIP Switch SPST Slide 7.62mm 300mil SMD +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_KingTek_DSHP06TJ_W5.25mm_P1.27mm_JPin +SMD 6x-dip-switch SPST KingTek_DSHP06TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_KingTek_DSHP06TS_W7.62mm_P1.27mm +SMD 6x-dip-switch SPST KingTek_DSHP06TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_Omron_A6H-6101_W6.15mm_P1.27mm +SMD 6x-dip-switch SPST Omron_A6H-6101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) +SMD DIP Switch SPST Slide 6.15mm 242mil +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx06_Slide_Omron_A6S-610x_W8.9mm_P2.54mm +SMD 6x-dip-switch SPST Omron_A6S-610x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +12 +12 +Button_Switch_SMD +SW_DIP_SPSTx07_Slide_6.7x19.34mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 7x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +14 +14 +Button_Switch_SMD +SW_DIP_SPSTx07_Slide_6.7x19.34mm_W8.61mm_P2.54mm_LowProfile +SMD 7x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +14 +14 +Button_Switch_SMD +SW_DIP_SPSTx07_Slide_9.78x19.96mm_W8.61mm_P2.54mm +SMD 7x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x19.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +14 +14 +Button_Switch_SMD +SW_DIP_SPSTx07_Slide_KingTek_DSHP07TJ_W5.25mm_P1.27mm_JPin +SMD 7x-dip-switch SPST KingTek_DSHP07TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +14 +14 +Button_Switch_SMD +SW_DIP_SPSTx07_Slide_KingTek_DSHP07TS_W7.62mm_P1.27mm +SMD 7x-dip-switch SPST KingTek_DSHP07TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +14 +14 +Button_Switch_SMD +SW_DIP_SPSTx07_Slide_Omron_A6S-710x_W8.9mm_P2.54mm +SMD 7x-dip-switch SPST Omron_A6S-710x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +14 +14 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_6.7x21.88mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 8x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_6.7x21.88mm_W8.61mm_P2.54mm_LowProfile +SMD 8x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_9.78x22.5mm_W8.61mm_P2.54mm +SMD 8x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_Copal_CHS-08A_W5.08mm_P1.27mm_JPin +SMD 8x-dip-switch SPST Copal_CHS-08A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin +SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_Copal_CHS-08B_W7.62mm_P1.27mm +SMD 8x-dip-switch SPST Copal_CHS-08B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD +SMD DIP Switch SPST Slide 7.62mm 300mil SMD +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_Copal_CVS-08xB_W5.9mm_P1mm +SMD 8x-dip-switch SPST Copal_CVS-08xB, Slide, row spacing 5.9 mm (232 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/cvs.pdf) +SMD DIP Switch SPST Slide 5.9mm 232mil +0 +20 +17 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_KingTek_DSHP08TJ_W5.25mm_P1.27mm_JPin +SMD 8x-dip-switch SPST KingTek_DSHP08TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_KingTek_DSHP08TS_W7.62mm_P1.27mm +SMD 8x-dip-switch SPST KingTek_DSHP08TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_Omron_A6H-8101_W6.15mm_P1.27mm +SMD 8x-dip-switch SPST Omron_A6H-8101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) +SMD DIP Switch SPST Slide 6.15mm 242mil +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx08_Slide_Omron_A6S-810x_W8.9mm_P2.54mm +SMD 8x-dip-switch SPST Omron_A6S-810x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +16 +16 +Button_Switch_SMD +SW_DIP_SPSTx09_Slide_6.7x24.42mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 9x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +18 +18 +Button_Switch_SMD +SW_DIP_SPSTx09_Slide_6.7x24.42mm_W8.61mm_P2.54mm_LowProfile +SMD 9x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +18 +18 +Button_Switch_SMD +SW_DIP_SPSTx09_Slide_9.78x25.04mm_W8.61mm_P2.54mm +SMD 9x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x25.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +18 +18 +Button_Switch_SMD +SW_DIP_SPSTx09_Slide_KingTek_DSHP09TJ_W5.25mm_P1.27mm_JPin +SMD 9x-dip-switch SPST KingTek_DSHP09TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +18 +18 +Button_Switch_SMD +SW_DIP_SPSTx09_Slide_KingTek_DSHP09TS_W7.62mm_P1.27mm +SMD 9x-dip-switch SPST KingTek_DSHP09TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +18 +18 +Button_Switch_SMD +SW_DIP_SPSTx09_Slide_Omron_A6S-910x_W8.9mm_P2.54mm +SMD 9x-dip-switch SPST Omron_A6S-910x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +18 +18 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_6.7x26.96mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 10x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_6.7x26.96mm_W8.61mm_P2.54mm_LowProfile +SMD 10x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_9.78x27.58mm_W8.61mm_P2.54mm +SMD 10x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x27.58mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_Copal_CHS-10A_W5.08mm_P1.27mm_JPin +SMD 10x-dip-switch SPST Copal_CHS-10A, Slide, row spacing 5.08 mm (200 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD, JPin +SMD DIP Switch SPST Slide 5.08mm 200mil SMD JPin +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_Copal_CHS-10B_W7.62mm_P1.27mm +SMD 10x-dip-switch SPST Copal_CHS-10B, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.nidec-copal-electronics.com/e/catalog/switch/chs.pdf), SMD +SMD DIP Switch SPST Slide 7.62mm 300mil SMD +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_KingTek_DSHP10TJ_W5.25mm_P1.27mm_JPin +SMD 10x-dip-switch SPST KingTek_DSHP10TJ, Slide, row spacing 5.25 mm (206 mils), body size (see http://www.kingtek.net.cn/pic/201601201446313350.pdf), JPin +SMD DIP Switch SPST Slide 5.25mm 206mil JPin +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_KingTek_DSHP10TS_W7.62mm_P1.27mm +SMD 10x-dip-switch SPST KingTek_DSHP10TS, Slide, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf) +SMD DIP Switch SPST Slide 7.62mm 300mil +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_Omron_A6H-10101_W6.15mm_P1.27mm +SMD 10x-dip-switch SPST Omron_A6H-10101, Slide, row spacing 6.15 mm (242 mils), body size (see https://www.omron.com/ecb/products/pdf/en-a6h.pdf) +SMD DIP Switch SPST Slide 6.15mm 242mil +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx10_Slide_Omron_A6S-1010x_W8.9mm_P2.54mm +SMD 10x-dip-switch SPST Omron_A6S-1010x, Slide, row spacing 8.9 mm (350 mils), body size (see http://omronfs.omron.com/en_US/ecb/products/pdf/en-a6s.pdf) +SMD DIP Switch SPST Slide 8.9mm 350mil +0 +20 +20 +Button_Switch_SMD +SW_DIP_SPSTx11_Slide_6.7x29.5mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 11x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +22 +22 +Button_Switch_SMD +SW_DIP_SPSTx11_Slide_6.7x29.5mm_W8.61mm_P2.54mm_LowProfile +SMD 11x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +22 +22 +Button_Switch_SMD +SW_DIP_SPSTx11_Slide_9.78x30.12mm_W8.61mm_P2.54mm +SMD 11x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x30.12mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +22 +22 +Button_Switch_SMD +SW_DIP_SPSTx12_Slide_6.7x32.04mm_W6.73mm_P2.54mm_LowProfile_JPin +SMD 12x-dip-switch SPST , Slide, row spacing 6.73 mm (264 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile, JPin +SMD DIP Switch SPST Slide 6.73mm 264mil SMD LowProfile JPin +0 +24 +24 +Button_Switch_SMD +SW_DIP_SPSTx12_Slide_6.7x32.04mm_W8.61mm_P2.54mm_LowProfile +SMD 12x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/219.pdf), SMD, LowProfile +SMD DIP Switch SPST Slide 8.61mm 338mil SMD LowProfile +0 +24 +24 +Button_Switch_SMD +SW_DIP_SPSTx12_Slide_9.78x32.66mm_W8.61mm_P2.54mm +SMD 12x-dip-switch SPST , Slide, row spacing 8.61 mm (338 mils), body size 9.78x32.66mm (see e.g. https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD +SMD DIP Switch SPST Slide 8.61mm 338mil SMD +0 +24 +24 +Button_Switch_SMD +SW_MEC_5GSH9 +MEC 5G single pole normally-open tactile switch +switch normally-open pushbutton push-button +0 +4 +4 +Button_Switch_SMD +SW_Push_1P1T-SH_NO_CK_KMR2xxG +CK components KMR2 tactile switch with ground pin http://www.ckswitches.com/media/1479/kmr2.pdf +tactile switch kmr2 +0 +5 +3 +Button_Switch_SMD +SW_Push_1P1T_NO_6x6mm_H9.5mm +tactile push button, 6x6mm e.g. PTS645xx series, height=9.5mm +tact sw push 6mm smd +0 +4 +2 +Button_Switch_SMD +SW_Push_1P1T_NO_CK_KMR2 +CK components KMR2 tactile switch http://www.ckswitches.com/media/1479/kmr2.pdf +tactile switch kmr2 +0 +4 +2 +Button_Switch_SMD +SW_Push_1P1T_NO_CK_KSC6xxJ +CK components KSC6 tactile switch https://www.ckswitches.com/media/1972/ksc6.pdf +tactile switch ksc6 +0 +4 +2 +Button_Switch_SMD +SW_Push_1P1T_NO_CK_KSC7xxJ +CK components KSC7 tactile switch https://www.ckswitches.com/media/1973/ksc7.pdf +tactile switch ksc7 +0 +4 +2 +Button_Switch_SMD +SW_Push_1P1T_NO_CK_PTS125Sx43PSMTR +C&K Switches 1P1T SMD PTS125 Series 12mm Tact Switch with Pegs, https://www.ckswitches.com/media/1462/pts125.pdf +Button Tactile Switch SPST 1P1T +0 +4 +2 +Button_Switch_SMD +SW_Push_1P1T_NO_Vertical_Wuerth_434133025816 +https://katalog.we-online.com/em/datasheet/434133025816.pdf +tactile switch Wurth Wuerth +0 +4 +2 +Button_Switch_SMD +SW_Push_SPST_NO_Alps_SKRK +http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKRK/SKRKAHE020.html +SMD SMT button +0 +2 +2 +Button_Switch_SMD +SW_SP3T_PCM13 +Ultraminiature Surface Mount Slide Switch, right-angle, https://www.ckswitches.com/media/1424/pcm.pdf + +0 +8 +4 +Button_Switch_SMD +SW_SPDT_CK-JS102011SAQN +Sub-miniature slide switch, right-angle, http://www.ckswitches.com/media/1422/js.pdf +switch spdt +0 +3 +3 +Button_Switch_SMD +SW_SPDT_PCM12 +Ultraminiature Surface Mount Slide Switch, right-angle, https://www.ckswitches.com/media/1424/pcm.pdf + +0 +7 +3 +Button_Switch_SMD +SW_SPST_B3S-1000 +Surface Mount Tactile Switch for High-Density Packaging +Tactile Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_B3S-1100 +Surface Mount Tactile Switch for High-Density Packaging with Ground Terminal +Tactile Switch +0 +5 +3 +Button_Switch_SMD +SW_SPST_B3SL-1002P +Middle Stroke Tactile Switch, B3SL +Middle Stroke Tactile Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_B3SL-1022P +Middle Stroke Tactile Switch, B3SL +Middle Stroke Tactile Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_B3U-1000P +Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, without Ground Terminal, without Boss +Tactile Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_B3U-1000P-B +Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, without Ground Terminal, with Boss +Tactile Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_B3U-1100P +Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, with Ground Terminal, without Boss +Tactile Switch +0 +3 +3 +Button_Switch_SMD +SW_SPST_B3U-1100P-B +Ultra-small-sized Tactile Switch with High Contact Reliability, Top-actuated Model, with Ground Terminal, with Boss +Tactile Switch +0 +3 +3 +Button_Switch_SMD +SW_SPST_B3U-3000P +Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, without Ground Terminal, without Boss +Tactile Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_B3U-3000P-B +Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, without Ground Terminal, with Boss +Tactile Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_B3U-3100P +Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, with Ground Terminal, without Boss +Tactile Switch +0 +3 +3 +Button_Switch_SMD +SW_SPST_B3U-3100P-B +Ultra-small-sized Tactile Switch with High Contact Reliability, Side-actuated Model, with Ground Terminal, with Boss +Tactile Switch +0 +3 +3 +Button_Switch_SMD +SW_SPST_CK_KXT3 +https://www.ckswitches.com/media/1465/kxt3.pdf +Switch SPST KXT3 +0 +2 +2 +Button_Switch_SMD +SW_SPST_CK_RS282G05A3 +https://www.mouser.com/ds/2/60/RS-282G05A-SM_RT-1159762.pdf +SPST button tactile switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_EVPBF +Light Touch Switch + +0 +4 +2 +Button_Switch_SMD +SW_SPST_EVQP0 +Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE28.pdf + +0 +4 +2 +Button_Switch_SMD +SW_SPST_EVQP2 +Light Touch Switch + +0 +4 +2 +Button_Switch_SMD +SW_SPST_EVQP7A +Light Touch Switch,https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE20.pdf + +0 +4 +2 +Button_Switch_SMD +SW_SPST_EVQP7C +Light Touch Switch + +0 +4 +2 +Button_Switch_SMD +SW_SPST_EVQPE1 +Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE7.pdf + +0 +2 +2 +Button_Switch_SMD +SW_SPST_EVQQ2 +Light Touch Switch, https://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE28.pdf + +0 +4 +2 +Button_Switch_SMD +SW_SPST_FSMSM +http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=1437566-3&DocType=Customer+Drawing&DocLang=English +SPST button tactile switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_PTS645 +C&K Components SPST SMD PTS645 Series 6mm Tact Switch +SPST Button Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_PTS810 +C&K Components, PTS 810 Series, Microminiature SMT Top Actuated, http://www.ckswitches.com/media/1476/pts810.pdf +SPST Button Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_Panasonic_EVQPL_3PL_5PL_PT_A08 +Light Touch Switch, http://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE3.pdf +SMD SMT SPST EVQPL EVQPT +0 +6 +3 +Button_Switch_SMD +SW_SPST_Panasonic_EVQPL_3PL_5PL_PT_A15 +Light Touch Switch, http://industrial.panasonic.com/cdbs/www-data/pdf/ATK0000/ATK0000CE3.pdf +SMD SMT SPST EVQPL EVQPT +0 +6 +3 +Button_Switch_SMD +SW_SPST_REED_CT05-XXXX-G1 +Coto Technologies SPST Reed Switch CT05-XXXX-G1 +Coto Reed SPST Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_REED_CT05-XXXX-J1 +Coto Technologies SPST Reed Switch CT05-XXXX-J1 +Coto Reed SPST Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_REED_CT10-XXXX-G1 +Coto Technologies SPST Reed Switch CT10-XXXX-G1 +Coto Reed SPST Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_REED_CT10-XXXX-G2 +Coto Technologies SPST Reed Switch CT10-XXXX-G2 +Coto Reed SPST Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_REED_CT10-XXXX-G4 +Coto Technologies SPST Reed Switch CT10-XXXX-G4 +Coto Reed SPST Switch +0 +2 +2 +Button_Switch_SMD +SW_SPST_SKQG_WithStem +ALPS 5.2mm Square Low-profile Type (Surface Mount) SKQG Series, With stem, http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKQG/SKQGAFE010.html +SPST Button Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_SKQG_WithoutStem +ALPS 5.2mm Square Low-profile Type (Surface Mount) SKQG Series, Without stem, http://www.alps.com/prod/info/E/HTML/Tact/SurfaceMount/SKQG/SKQGAEE010.html +SPST Button Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_TL3305A +https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf +TL3305 Series Tact Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_TL3305B +https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf +TL3305 Series Tact Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_TL3305C +https://www.e-switch.com/system/asset/product_line/data_sheet/213/TL3305.pdf +TL3305 Series Tact Switch +0 +4 +2 +Button_Switch_SMD +SW_SPST_TL3342 +Low-profile SMD Tactile Switch, https://www.e-switch.com/system/asset/product_line/data_sheet/165/TL3342.pdf +SPST Tactile Switch +0 +4 +2 +Button_Switch_THT +KSA_Tactile_SPST +KSA http://www.ckswitches.com/media/1457/ksa_ksl.pdf +SWITCH SMD KSA SW +0 +5 +5 +Button_Switch_THT +Nidec_Copal_SH-7010C +4-bit rotary coded switch, through-hole, https://www.nidec-copal-electronics.com/e/catalog/switch/sh-7000.pdf +rotary switch bcd +0 +6 +5 +Button_Switch_THT +Push_E-Switch_KS01Q01 +E-Switch KS01Q01 http://spec_sheets.e-switch.com/specs/29-KS01Q01.pdf +Push Button +0 +4 +4 +Button_Switch_THT +SW_CW_GPTS203211B +SPST Off-On Pushbutton, 1A, 30V, CW Industries P/N GPTS203211B, http://switches-connectors-custom.cwind.com/Asset/GPTS203211BR2.pdf +SPST button switch Off-On +0 +2 +2 +Button_Switch_THT +SW_CuK_JS202011AQN_DPDT_Angled +CuK sub miniature slide switch, JS series, DPDT, right angle, http://www.ckswitches.com/media/1422/js.pdf +switch DPDT +0 +6 +6 +Button_Switch_THT +SW_CuK_JS202011CQN_DPDT_Straight +CuK sub miniature slide switch, JS series, DPDT, right angle, http://www.ckswitches.com/media/1422/js.pdf +switch DPDT +0 +6 +6 +Button_Switch_THT +SW_CuK_OS102011MA1QN1_SPDT_Angled +CuK miniature slide switch, OS series, SPDT, right angle, http://www.ckswitches.com/media/1428/os.pdf +switch SPDT +0 +5 +3 +Button_Switch_THT +SW_DIP_SPSTx01_Piano_10.8x4.1mm_W7.62mm_P2.54mm +1x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x4.1mm +DIP Switch SPST Piano 7.62mm 300mil +0 +2 +2 +Button_Switch_THT +SW_DIP_SPSTx01_Slide_6.7x4.1mm_W7.62mm_P2.54mm_LowProfile +1x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x4.1mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +2 +2 +Button_Switch_THT +SW_DIP_SPSTx01_Slide_9.78x4.72mm_W7.62mm_P2.54mm +1x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x4.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +2 +2 +Button_Switch_THT +SW_DIP_SPSTx02_Piano_10.8x6.64mm_W7.62mm_P2.54mm +2x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x6.64mm +DIP Switch SPST Piano 7.62mm 300mil +0 +4 +4 +Button_Switch_THT +SW_DIP_SPSTx02_Piano_CTS_Series194-2MSTN_W7.62mm_P2.54mm +2x-dip-switch SPST CTS_Series194-2MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +4 +4 +Button_Switch_THT +SW_DIP_SPSTx02_Slide_6.7x6.64mm_W7.62mm_P2.54mm_LowProfile +2x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x6.64mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +4 +4 +Button_Switch_THT +SW_DIP_SPSTx02_Slide_9.78x7.26mm_W7.62mm_P2.54mm +2x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x7.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +4 +4 +Button_Switch_THT +SW_DIP_SPSTx03_Piano_10.8x9.18mm_W7.62mm_P2.54mm +3x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x9.18mm +DIP Switch SPST Piano 7.62mm 300mil +0 +6 +6 +Button_Switch_THT +SW_DIP_SPSTx03_Piano_CTS_Series194-3MSTN_W7.62mm_P2.54mm +3x-dip-switch SPST CTS_Series194-3MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +6 +6 +Button_Switch_THT +SW_DIP_SPSTx03_Slide_6.7x9.18mm_W7.62mm_P2.54mm_LowProfile +3x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x9.18mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +6 +6 +Button_Switch_THT +SW_DIP_SPSTx03_Slide_9.78x9.8mm_W7.62mm_P2.54mm +3x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x9.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +6 +6 +Button_Switch_THT +SW_DIP_SPSTx04_Piano_10.8x11.72mm_W7.62mm_P2.54mm +4x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x11.72mm +DIP Switch SPST Piano 7.62mm 300mil +0 +8 +8 +Button_Switch_THT +SW_DIP_SPSTx04_Piano_CTS_Series194-4MSTN_W7.62mm_P2.54mm +4x-dip-switch SPST CTS_Series194-4MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +8 +8 +Button_Switch_THT +SW_DIP_SPSTx04_Slide_6.7x11.72mm_W7.62mm_P2.54mm_LowProfile +4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x11.72mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +8 +8 +Button_Switch_THT +SW_DIP_SPSTx04_Slide_9.78x12.34mm_W7.62mm_P2.54mm +4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x12.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +8 +8 +Button_Switch_THT +SW_DIP_SPSTx05_Piano_10.8x14.26mm_W7.62mm_P2.54mm +5x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x14.26mm +DIP Switch SPST Piano 7.62mm 300mil +0 +10 +10 +Button_Switch_THT +SW_DIP_SPSTx05_Piano_CTS_Series194-5MSTN_W7.62mm_P2.54mm +5x-dip-switch SPST CTS_Series194-5MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +10 +10 +Button_Switch_THT +SW_DIP_SPSTx05_Slide_6.7x14.26mm_W7.62mm_P2.54mm_LowProfile +5x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x14.26mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +10 +10 +Button_Switch_THT +SW_DIP_SPSTx05_Slide_9.78x14.88mm_W7.62mm_P2.54mm +5x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x14.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +10 +10 +Button_Switch_THT +SW_DIP_SPSTx06_Piano_10.8x16.8mm_W7.62mm_P2.54mm +6x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x16.8mm +DIP Switch SPST Piano 7.62mm 300mil +0 +12 +12 +Button_Switch_THT +SW_DIP_SPSTx06_Piano_CTS_Series194-6MSTN_W7.62mm_P2.54mm +6x-dip-switch SPST CTS_Series194-6MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +12 +12 +Button_Switch_THT +SW_DIP_SPSTx06_Slide_6.7x16.8mm_W7.62mm_P2.54mm_LowProfile +6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x16.8mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +12 +12 +Button_Switch_THT +SW_DIP_SPSTx06_Slide_9.78x17.42mm_W7.62mm_P2.54mm +6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +12 +12 +Button_Switch_THT +SW_DIP_SPSTx07_Piano_10.8x19.34mm_W7.62mm_P2.54mm +7x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x19.34mm +DIP Switch SPST Piano 7.62mm 300mil +0 +14 +14 +Button_Switch_THT +SW_DIP_SPSTx07_Piano_CTS_Series194-7MSTN_W7.62mm_P2.54mm +7x-dip-switch SPST CTS_Series194-7MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +14 +14 +Button_Switch_THT +SW_DIP_SPSTx07_Slide_6.7x19.34mm_W7.62mm_P2.54mm_LowProfile +7x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x19.34mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +14 +14 +Button_Switch_THT +SW_DIP_SPSTx07_Slide_9.78x19.96mm_W7.62mm_P2.54mm +7x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x19.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +14 +14 +Button_Switch_THT +SW_DIP_SPSTx08_Piano_10.8x21.88mm_W7.62mm_P2.54mm +8x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x21.88mm +DIP Switch SPST Piano 7.62mm 300mil +0 +16 +16 +Button_Switch_THT +SW_DIP_SPSTx08_Piano_CTS_Series194-8MSTN_W7.62mm_P2.54mm +8x-dip-switch SPST CTS_Series194-8MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +16 +16 +Button_Switch_THT +SW_DIP_SPSTx08_Slide_6.7x21.88mm_W7.62mm_P2.54mm_LowProfile +8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x21.88mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +16 +16 +Button_Switch_THT +SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm +8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +16 +16 +Button_Switch_THT +SW_DIP_SPSTx09_Piano_10.8x24.42mm_W7.62mm_P2.54mm +9x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x24.42mm +DIP Switch SPST Piano 7.62mm 300mil +0 +18 +18 +Button_Switch_THT +SW_DIP_SPSTx09_Piano_CTS_Series194-9MSTN_W7.62mm_P2.54mm +9x-dip-switch SPST CTS_Series194-9MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +18 +18 +Button_Switch_THT +SW_DIP_SPSTx09_Slide_6.7x24.42mm_W7.62mm_P2.54mm_LowProfile +9x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x24.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +18 +18 +Button_Switch_THT +SW_DIP_SPSTx09_Slide_9.78x25.04mm_W7.62mm_P2.54mm +9x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x25.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +18 +18 +Button_Switch_THT +SW_DIP_SPSTx10_Piano_10.8x26.96mm_W7.62mm_P2.54mm +10x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x26.96mm +DIP Switch SPST Piano 7.62mm 300mil +0 +20 +20 +Button_Switch_THT +SW_DIP_SPSTx10_Piano_CTS_Series194-10MSTN_W7.62mm_P2.54mm +10x-dip-switch SPST CTS_Series194-10MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +20 +20 +Button_Switch_THT +SW_DIP_SPSTx10_Slide_6.7x26.96mm_W7.62mm_P2.54mm_LowProfile +10x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x26.96mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +20 +20 +Button_Switch_THT +SW_DIP_SPSTx10_Slide_9.78x27.58mm_W7.62mm_P2.54mm +10x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x27.58mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +20 +20 +Button_Switch_THT +SW_DIP_SPSTx11_Piano_10.8x29.5mm_W7.62mm_P2.54mm +11x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x29.5mm +DIP Switch SPST Piano 7.62mm 300mil +0 +22 +22 +Button_Switch_THT +SW_DIP_SPSTx11_Piano_CTS_Series194-11MSTN_W7.62mm_P2.54mm +11x-dip-switch SPST CTS_Series194-11MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +22 +22 +Button_Switch_THT +SW_DIP_SPSTx11_Slide_6.7x29.5mm_W7.62mm_P2.54mm_LowProfile +11x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x29.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +22 +22 +Button_Switch_THT +SW_DIP_SPSTx11_Slide_9.78x30.12mm_W7.62mm_P2.54mm +11x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x30.12mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +22 +22 +Button_Switch_THT +SW_DIP_SPSTx12_Piano_10.8x32.04mm_W7.62mm_P2.54mm +12x-dip-switch SPST , Piano, row spacing 7.62 mm (300 mils), body size 10.8x32.04mm +DIP Switch SPST Piano 7.62mm 300mil +0 +24 +24 +Button_Switch_THT +SW_DIP_SPSTx12_Piano_CTS_Series194-12MSTN_W7.62mm_P2.54mm +12x-dip-switch SPST CTS_Series194-12MSTN, Piano, row spacing 7.62 mm (300 mils), body size (see https://www.ctscorp.com/wp-content/uploads/194-195.pdf) +DIP Switch SPST Piano 7.62mm 300mil +0 +24 +24 +Button_Switch_THT +SW_DIP_SPSTx12_Slide_6.7x32.04mm_W7.62mm_P2.54mm_LowProfile +12x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 6.7x32.04mm (see e.g. https://www.ctscorp.com/wp-content/uploads/209-210.pdf), LowProfile +DIP Switch SPST Slide 7.62mm 300mil LowProfile +0 +24 +24 +Button_Switch_THT +SW_DIP_SPSTx12_Slide_9.78x32.66mm_W7.62mm_P2.54mm +12x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x32.66mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf) +DIP Switch SPST Slide 7.62mm 300mil +0 +24 +24 +Button_Switch_THT +SW_E-Switch_EG1224_SPDT_Angled +E-Switch slide switch, EG series, SPDT, right angle, http://spec_sheets.e-switch.com/specs/P040042.pdf +switch SPDT +0 +7 +3 +Button_Switch_THT +SW_E-Switch_EG1271_DPDT +E-Switch sub miniature slide switch, EG series, DPDT, http://spec_sheets.e-switch.com/specs/P040047.pdf +switch DPDT +0 +6 +6 +Button_Switch_THT +SW_E-Switch_EG2219_DPDT_Angled +E-Switch slide switch, EG series, DPDT, right angle, http://spec_sheets.e-switch.com/specs/P040170.pdf +switch DPDT +0 +10 +6 +Button_Switch_THT +SW_Lever_1P2T_NKK_GW12LxH +Switch, single pole double throw, right angle, http://www.nkkswitches.com/pdf/GW.pdf +switch single-pole double-throw spdt ON-ON horizontal +0 +5 +3 +Button_Switch_THT +SW_MEC_5GTH9 +MEC 5G single pole normally-open tactile switch https://cdn.sos.sk/productdata/80/f6/aabf7be6/5gth9358222.pdf +switch normally-open pushbutton push-button +0 +4 +2 +Button_Switch_THT +SW_NKK_BB15AH +https://www.nkkswitches.com/pdf/Bpushbuttons-1.pdf +Pushbutton Right-angle +0 +5 +3 +Button_Switch_THT +SW_NKK_G1xJP +Switch NKK G1xJP http://www.nkkswitches.com/pdf/gwillum.pdf +SWITCH TOGGLE ILLUM SPDT NKK +0 +6 +6 +Button_Switch_THT +SW_NKK_GW12LJP +Switch, single pole double throw, illuminated paddle, http://www.nkkswitches.com/pdf/gwillum.pdf +switch single-pole double-throw spdt ON-ON illuminated LED +0 +6 +6 +Button_Switch_THT +SW_PUSH-12mm +SW PUSH 12mm https://www.e-switch.com/system/asset/product_line/data_sheet/143/TL1100.pdf +tact sw push 12mm +0 +4 +2 +Button_Switch_THT +SW_PUSH-12mm_Wuerth-430476085716 +SW PUSH 12mm http://katalog.we-online.de/em/datasheet/430476085716.pdf +tact sw push 12mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm +https://www.omron.com/ecb/products/pdf/en-b3f.pdf +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H4.3mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=4.3mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H5mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=5mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H7.3mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=7.3mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H8.5mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=8.5mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H8mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=8mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H9.5mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=9.5mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_6mm_H13mm +tactile push button, 6x6mm e.g. PHAP33xx series, height=13mm +tact sw push 6mm +0 +4 +2 +Button_Switch_THT +SW_PUSH_E-Switch_FS5700DP_DPDT +FS5700 series pushbutton footswitch, DPDT, https://www.e-switch.com/system/asset/product_line/data_sheet/226/FS5700.pdf +switch DPDT footswitch +0 +6 +6 +Button_Switch_THT +SW_PUSH_LCD_E3_SAxxxx +Switch with LCD screen E3 SAxxxx +switch normally-open pushbutton push-button LCD +0 +6 +6 +Button_Switch_THT +SW_PUSH_LCD_E3_SAxxxx_SocketPins +Switch with LCD screen E3 SAxxxx +switch normally-open pushbutton push-button LCD +0 +6 +6 +Button_Switch_THT +SW_Push_1P1T_NO_LED_E-Switch_TL1250 +illuminated right angle tact switch https://www.e-switch.com/system/asset/product_line/data_sheet/148/TL1250.pdf +led push switch right angle +0 +6 +4 +Button_Switch_THT +SW_Push_1P2T_Vertical_E-Switch_800UDP8P1A1M6 + right angle SPDT push button https://www.e-switch.com/system/asset/product_line/data_sheet/210/800U.pdf +IP67 ultra-miniture horizontal +0 +5 +3 +Button_Switch_THT +SW_Push_2P2T_Vertical_E-Switch_800UDP8P1A1M6 + right angle DPDT push button https://www.e-switch.com/system/asset/product_line/data_sheet/210/800U.pdf +IP67 ultra-miniture horizontal +0 +8 +6 +Button_Switch_THT +SW_Slide_1P2T_CK_OS102011MS2Q +CuK miniature slide switch, OS series, SPDT, https://www.ckswitches.com/media/1428/os.pdf +switch SPDT +0 +5 +3 +Button_Switch_THT +SW_TH_Tactile_Omron_B3F-10xx +SW_TH_Tactile_Omron_B3F-10xx_https://www.omron.com/ecb/products/pdf/en-b3f.pdf +Omron B3F-10xx +0 +4 +4 +Button_Switch_THT +SW_Tactile_SKHH_Angled +tactile switch 6mm ALPS SKHH right angle http://www.alps.com/prod/info/E/HTML/Tact/SnapIn/SKHH/SKHHLUA010.html +tactile switch 6mm ALPS SKHH right angle +0 +4 +2 +Button_Switch_THT +SW_Tactile_SPST_Angled_PTS645Vx31-2LFS +tactile switch SPST right angle, PTS645VL31-2 LFS +tactile switch SPST angled PTS645VL31-2 LFS C&K Button +0 +4 +2 +Button_Switch_THT +SW_Tactile_SPST_Angled_PTS645Vx39-2LFS +tactile switch SPST right angle, PTS645VL39-2 LFS +tactile switch SPST angled PTS645VL39-2 LFS C&K Button +0 +4 +2 +Button_Switch_THT +SW_Tactile_SPST_Angled_PTS645Vx58-2LFS +tactile switch SPST right angle, PTS645VL58-2 LFS +tactile switch SPST angled PTS645VL58-2 LFS C&K Button +0 +4 +2 +Button_Switch_THT +SW_Tactile_SPST_Angled_PTS645Vx83-2LFS +tactile switch SPST right angle, PTS645VL83-2 LFS +tactile switch SPST angled PTS645VL83-2 LFS C&K Button +0 +4 +2 +Button_Switch_THT +SW_Tactile_Straight_KSA0Axx1LFTR +SW PUSH SMALL http://www.ckswitches.com/media/1457/ksa_ksl.pdf +SW PUSH SMALL Tactile C&K +0 +4 +2 +Button_Switch_THT +SW_Tactile_Straight_KSL0Axx1LFTR +SW PUSH SMALL http://www.ckswitches.com/media/1457/ksa_ksl.pdf +SW PUSH SMALL Tactile C&K +0 +4 +2 +Buzzer_Beeper +Buzzer_12x9.5RM7.6 +Generic Buzzer, D12mm height 9.5mm with RM7.6mm +buzzer +0 +2 +2 +Buzzer_Beeper +Buzzer_15x7.5RM7.6 +Generic Buzzer, D15mm height 7.5mm with RM7.6mm +buzzer +0 +2 +2 +Buzzer_Beeper +Buzzer_CUI_CPT-9019S-SMT +https://www.cui.com/product/resource/cpt-9019s-smt.pdf +buzzer piezo +0 +2 +2 +Buzzer_Beeper +Buzzer_D14mm_H7mm_P10mm +Generic Buzzer, D14mm height 7mm with pitch 10mm +buzzer +0 +2 +2 +Buzzer_Beeper +Buzzer_Mallory_AST1109MLTRQ +Mallory low-profile piezo buzzer, https://www.mspindy.com/specifications/AST1109MLTRQ.pdf +buzzer piezo +0 +2 +2 +Buzzer_Beeper +Buzzer_Murata_PKMCS0909E4000-R1 +Murata Buzzer http://www.murata.com/en-us/api/pdfdownloadapi?cate=&partno=PKMCS0909E4000-R1 +Murata Buzzer Beeper +0 +2 +2 +Buzzer_Beeper +Buzzer_TDK_PS1240P02BT_D12.2mm_H6.5mm +Buzzer, D12.2mm height 6.5mm, https://product.tdk.com/info/en/catalog/datasheets/piezoelectronic_buzzer_ps_en.pdf +buzzer +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_CUI_CST-931RP-A +CST-931RP-A, http://www.cui.com/product/resource/cst-931rp-a.pdf +CST-931RP-A +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_Kingstate_KCG0601 +Buzzer, Elektromagnetic Beeper, Summer, +Kingstate KCG0601 +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_Kobitone_254-EMB84Q-RO +MagneticBuzzer Kobitone 254-EMB84Q-RO https://www.mouser.es/datasheet/2/209/KT-400385-1171904.pdf +MagneticBuzzer Kobitone 254-EMB84Q-RO +0 +3 +3 +Buzzer_Beeper +MagneticBuzzer_PUI_AT-0927-TT-6-R +Buzzer Magnetic 9mm AT-0927-TT-6-R, http://www.puiaudio.com/pdf/AT-0927-TT-6-R.pdf +Buzzer Magnetic 9mm AT-0927-TT-6-R +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_ProSignal_ABI-009-RC +Buzzer, Elektromagnetic Beeper, Summer, 6V-DC, +Pro Signal ABI-009-RC +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_ProSignal_ABI-010-RC +Buzzer, Elektromagnetic Beeper, Summer, 12V-DC, +Pro Signal ABI-010-RC +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_ProSignal_ABT-410-RC +Buzzer, Elektromagnetic Beeper, Summer, 1,5V-DC, +Pro Signal ABT-410-RC +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_ProjectsUnlimited_AI-4228-TWT-R +Buzzer, Elektromagnetic Beeper, Summer, 3-28V-DC, https://www.kynix.com/uploadfiles/pdf/AI-4228-TWT-R.pdf +Projects Unlimited AI-4228-TWT-R +0 +2 +2 +Buzzer_Beeper +MagneticBuzzer_StarMicronics_HMB-06_HMB-12 +Buzzer, Elektromagnetic Beeper, Summer, +Star Micronics HMB-06 HMB-12 +0 +2 +2 +Buzzer_Beeper +PUIAudio_SMT_0825_S_4_R +SMD 8540, http://www.puiaudio.com/product-detail.aspx?partnumber=SMT-0825-S-4-R +SMD 8540 +0 +4 +4 +Calibration_Scale +Gauge_10mm_Type1_CopperTop +Gauge, Massstab, 10mm, CopperTop, Type 1, +Gauge Massstab 10mm CopperTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type1_SilkScreenTop +Gauge, Massstab, 10mm, SilkScreenTop, Type 1, +Gauge Massstab 10mm SilkScreenTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type2_CopperTop +Gauge, Massstab, 10mm, CopperTop, Type 2, +Gauge Massstab 10mm CopperTop Type 2 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type2_SilkScreenTop +Gauge, Massstab, 10mm, SilkScreenTop, Type 2, +Gauge Massstab 10mm SilkScreenTop Type 2 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type3_CopperTop +Gauge, Massstab, 10mm, CopperTop, Type 3, +Gauge Massstab 10mm CopperTop Type 3 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type3_SilkScreenTop +Gauge, Massstab, 10mm, SilkScreenTop, Type 3, +Gauge Massstab 10mm SilkScreenTop Type 3 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type4_CopperTop +Gauge, Massstab, 10mm, CopperTop, Type 4, +Gauge Massstab 10mm CopperTop Type 4 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type4_SilkScreenTop +Gauge, Massstab, 10mm, SilkScreenTop, Type 4, +Gauge Massstab 10mm SilkScreenTop Type 4 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type5_CopperTop +Gauge, Massstab, 10mm, CopperTop, Type 5, +Gauge Massstab 10mm CopperTop Type 5 +0 +0 +0 +Calibration_Scale +Gauge_10mm_Type5_SilkScreenTop +Gauge, Massstab, 10mm, SilkScreenTop, Type 5, +Gauge Massstab 10mm SilkScreenTop Type 5 +0 +0 +0 +Calibration_Scale +Gauge_50mm_Type1_CopperTop +Gauge, Massstab, 50mm, CopperTop, Type 1, +Gauge Massstab 50mm CopperTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_50mm_Type1_SilkScreenTop +Gauge, Massstab, 50mm, SilkScreenTop, Type 1, +Gauge Massstab 50mm SilkScreenTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_50mm_Type2_CopperTop +Gauge, Massstab, 50mm, CopperTop, Type 2, +Gauge Massstab 50mm CopperTop Type 2 +0 +0 +0 +Calibration_Scale +Gauge_50mm_Type2_SilkScreenTop +Gauge, Massstab, 50mm, SilkScreenTop, Type 2, +Gauge Massstab 50mm SilkScreenTop Type 2 +0 +0 +0 +Calibration_Scale +Gauge_100mm_Grid_Type1_CopperTop +Gauge, Massstab, 100mm, Gitter, Grid, CopperTop, Type 1, +Gauge Massstab 100mm Gitter Grid CopperTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_100mm_Type1_CopperTop +Gauge, Massstab, 100mm, CopperTop, Type 1, +Gauge Massstab 100mm CopperTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_100mm_Type1_SilkScreenTop +Gauge, Massstab, 100mm, SilkScreenTop, Type 1, +Gauge Massstab 100mm SilkScreenTop Type 1 +0 +0 +0 +Calibration_Scale +Gauge_100mm_Type2_CopperTop +Gauge, Massstab, 100mm, CopperTop, Type 2, +Gauge Massstab 100mm CopperTop Type 2 +0 +0 +0 +Calibration_Scale +Gauge_100mm_Type2_SilkScreenTop +Gauge, Massstab, 100mm, SilkScreenTop, Type 2, +Gauge Massstab 100mm SilkScreenTop Type 2 +0 +0 +0 +Capacitor_SMD +CP_Elec_3x5.3 +SMT capacitor, aluminium electrolytic, 3x5.3, Cornell Dubilier Electronics +Capacitor Electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_3x5.4 +SMD capacitor, aluminum electrolytic, Nichicon, 3.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x3 +SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x3.9 +SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x4.5 +SMD capacitor, aluminum electrolytic, Nichicon, 4.0x4.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.3 +SMD capacitor, aluminum electrolytic, Vishay, 4.0x5.3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.4 +SMD capacitor, aluminum electrolytic, Panasonic A5 / Nichicon, 4.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 4.0x5.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.8 +SMD capacitor, aluminum electrolytic, Panasonic, 4.0x5.8mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x3 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.0mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x3.9 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x4.4 +SMD capacitor, aluminum electrolytic, Panasonic B45, 5.0x4.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x4.5 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x4.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.3 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.4 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 5.0x5.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.8 +SMD capacitor, aluminum electrolytic, Panasonic, 5.0x5.8mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.9 +SMD capacitor, aluminum electrolytic, Panasonic B6, 5.0x5.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x3 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.0mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x3.9 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x4.5 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x4.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x4.9 +SMD capacitor, aluminum electrolytic, Panasonic C5, 6.3x4.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.2 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.2mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.3 +SMD capacitor, aluminum electrolytic, Cornell Dubilier, 6.3x5.3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.4 +SMD capacitor, aluminum electrolytic, Panasonic C55, 6.3x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.4_Nichicon +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.8 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.8mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.9 +SMD capacitor, aluminum electrolytic, Panasonic C6, 6.3x5.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x7.7 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x7.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x9.9 +SMD capacitor, aluminum electrolytic, Panasonic C10, 6.3x9.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x5.4 +SMD capacitor, aluminum electrolytic, Nichicon, 8.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.2 +SMD capacitor, aluminum electrolytic, Nichicon, 8.0x6.2mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.5 +SMD capacitor, aluminum electrolytic, Rubycon, 8.0x6.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 8.0x6.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.9 +SMD capacitor, aluminum electrolytic, Panasonic E7, 8.0x6.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x10 +SMD capacitor, aluminum electrolytic, Nichicon, 8.0x10mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x10.5 +SMD capacitor, aluminum electrolytic, Vishay 0810, 8.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x11.9 +SMD capacitor, aluminum electrolytic, Panasonic E12, 8.0x11.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x7.7 +SMD capacitor, aluminum electrolytic, Nichicon, 10.0x7.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x7.9 +SMD capacitor, aluminum electrolytic, Panasonic F8, 10.0x7.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x10 +SMD capacitor, aluminum electrolytic, Nichicon, 10.0x10.0mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x10.5 +SMD capacitor, aluminum electrolytic, Vishay 1010, 10.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x12.5 +SMD capacitor, aluminum electrolytic, Vishay 1012, 10.0x12.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x12.6 +SMD capacitor, aluminum electrolytic, Panasonic F12, 10.0x12.6mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x14.3 +SMD capacitor, aluminum electrolytic, Vishay 1014, 10.0x14.3mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_16x17.5 +SMD capacitor, aluminum electrolytic, Vishay 1616, 16.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_16x22 +SMD capacitor, aluminum electrolytic, Vishay 1621, 16.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_18x17.5 +SMD capacitor, aluminum electrolytic, Vishay 1816, 18.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_18x22 +SMD capacitor, aluminum electrolytic, Vishay 1821, 18.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +C_0201_0603Metric +Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +capacitor +0 +4 +2 +Capacitor_SMD +C_0402_1005Metric +Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0603_1608Metric +Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0603_1608Metric_Pad1.05x0.95mm_HandSolder +Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_0805_2012Metric +Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0805_2012Metric_Pad1.15x1.40mm_HandSolder +Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_01005_0402Metric +Capacitor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +capacitor +0 +4 +2 +Capacitor_SMD +C_1206_3216Metric +Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1206_3216Metric_Pad1.42x1.75mm_HandSolder +Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1210_3225Metric +Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1210_3225Metric_Pad1.42x2.65mm_HandSolder +Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1806_4516Metric +Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1806_4516Metric_Pad1.57x1.80mm_HandSolder +Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1812_4532Metric +Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1812_4532Metric_Pad1.30x3.40mm_HandSolder +Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1825_4564Metric +Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1825_4564Metric_Pad1.88x6.70mm_HandSolder +Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2010_5025Metric +Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2010_5025Metric_Pad1.52x2.65mm_HandSolder +Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2220_5650Metric +Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2220_5650Metric_Pad1.97x5.40mm_HandSolder +Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2225_5664Metric +Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2225_5664Metric_Pad1.80x6.60mm_HandSolder +Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2512_6332Metric +Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2512_6332Metric_Pad1.52x3.35mm_HandSolder +Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2816_7142Metric +Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2816_7142Metric_Pad3.20x4.45mm_HandSolder +Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_3640_9110Metric +Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_3640_9110Metric_Pad2.10x10.45mm_HandSolder +Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_Elec_3x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 3.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_4x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_4x5.8 +SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.8mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_5x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_5x5.8 +SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.8mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_6.3x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_6.3x5.8 +SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.8mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_6.3x7.7 +SMD capacitor, aluminum electrolytic nonpolar, 6.3x7.7mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_8x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 8.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_8x6.2 +SMD capacitor, aluminum electrolytic nonpolar, 8.0x6.2mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_8x10.2 +SMD capacitor, aluminum electrolytic nonpolar, 8.0x10.2mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_10x10.2 +SMD capacitor, aluminum electrolytic nonpolar, 10.0x10.2mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZB4-A +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZB4 TZB4-A +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZB4-B +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZB4 TZB4-A +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZC3 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZC3 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZR1 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZR1 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZW4 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZW4 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZY2 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZY2 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Sprague-Goodman_SGC3 +trimmer capacitor SMD horizontal, http://media.wix.com/ugd/d86717_38d9821e12823a7aa9cef38c6c2a73cc.pdf + Sprague Goodman SGC3 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JN +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JN +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JQ +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JQ +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JR +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JR +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JV +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JV +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JZ +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JR +0 +2 +2 +Capacitor_THT +CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*4.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 15mm length 10mm diameter 4.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L10.0mm_D6.0mm_P15.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*6mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 15mm length 10mm diameter 6mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L11.0mm_D5.0mm_P18.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*5mm^2, Electrolytic Capacitor +CP Axial series Axial Horizontal pin pitch 18mm length 11mm diameter 5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*6mm^2, Electrolytic Capacitor +CP Axial series Axial Horizontal pin pitch 18mm length 11mm diameter 6mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L11.0mm_D8.0mm_P15.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=11*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 15mm length 11mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L18.0mm_D6.5mm_P25.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*6.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 6.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L18.0mm_D8.0mm_P25.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L18.0mm_D10.0mm_P25.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=18*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 25mm length 18mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L20.0mm_D10.0mm_P26.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 26mm length 20mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L20.0mm_D13.0mm_P26.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 26mm length 20mm diameter 13mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L21.0mm_D8.0mm_P28.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=28mm, , length*diameter=21*8mm^2, Electrolytic Capacitor +CP Axial series Axial Horizontal pin pitch 28mm length 21mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L25.0mm_D10.0mm_P30.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=30mm, , length*diameter=25*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 30mm length 25mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L26.5mm_D20.0mm_P33.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=33mm, , length*diameter=26.5*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 33mm length 26.5mm diameter 20mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L29.0mm_D10.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L29.0mm_D13.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 13mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L29.0mm_D16.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*16mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 16mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L29.0mm_D20.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=29*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 29mm diameter 20mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L30.0mm_D10.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*10mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L30.0mm_D12.5mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*12.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 12.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L30.0mm_D15.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*15mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 15mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L30.0mm_D18.0mm_P35.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=30*18mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 35mm length 30mm diameter 18mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L34.5mm_D20.0mm_P41.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=41mm, , length*diameter=34.5*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 41mm length 34.5mm diameter 20mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L37.0mm_D13.0mm_P43.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*13mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 43mm length 37mm diameter 13mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L37.0mm_D16.0mm_P43.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*16mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 43mm length 37mm diameter 16mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L37.0mm_D20.0mm_P43.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=43mm, , length*diameter=37*20mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf +CP Axial series Axial Horizontal pin pitch 43mm length 37mm diameter 20mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L38.0mm_D18.0mm_P44.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=44mm, , length*diameter=38*18mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 44mm length 38mm diameter 18mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L38.0mm_D21.0mm_P44.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=44mm, , length*diameter=38*21mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf +CP Axial series Axial Horizontal pin pitch 44mm length 38mm diameter 21mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L40.0mm_D16.0mm_P48.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=48mm, , length*diameter=40*16mm^2, Electrolytic Capacitor +CP Axial series Axial Horizontal pin pitch 48mm length 40mm diameter 16mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L42.0mm_D23.0mm_P45.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 23.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L42.0mm_D26.0mm_P45.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 26mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L42.0mm_D29.0mm_P45.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 29.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L42.0mm_D32.0mm_P45.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 32.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L42.0mm_D35.0mm_P45.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=45mm, , length*diameter=42*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 45mm length 42mm diameter 35.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L42.5mm_D20.0mm_P49.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=49mm, , length*diameter=42.5*20mm^2, Electrolytic Capacitor +CP Axial series Axial Horizontal pin pitch 49mm length 42.5mm diameter 20mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L46.0mm_D20.0mm_P52.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=52mm, , length*diameter=46*20mm^2, Electrolytic Capacitor +CP Axial series Axial Horizontal pin pitch 52mm length 46mm diameter 20mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L55.0mm_D23.0mm_P60.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 23.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L55.0mm_D26.0mm_P60.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 26mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L55.0mm_D29.0mm_P60.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 29.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L55.0mm_D32.0mm_P60.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 32.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L55.0mm_D35.0mm_P60.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=60mm, , length*diameter=55*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 60mm length 55mm diameter 35.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L67.0mm_D23.0mm_P75.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 23.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L67.0mm_D26.0mm_P75.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 26mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L67.0mm_D29.0mm_P75.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 29.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L67.0mm_D32.0mm_P75.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 32.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L67.0mm_D35.0mm_P75.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=75mm, , length*diameter=67*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 75mm length 67mm diameter 35.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L80.0mm_D23.0mm_P85.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 23.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L80.0mm_D26.0mm_P85.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 26mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L80.0mm_D29.0mm_P85.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 29.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L80.0mm_D32.0mm_P85.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 32.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L80.0mm_D35.0mm_P85.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=85mm, , length*diameter=80*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 85mm length 80mm diameter 35.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L93.0mm_D23.0mm_P100.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*23.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 23.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L93.0mm_D26.0mm_P100.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*26mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 26mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L93.0mm_D29.0mm_P100.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*29.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 29.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L93.0mm_D32.0mm_P100.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*32.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 32.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Axial_L93.0mm_D35.0mm_P100.00mm_Horizontal +CP, Axial series, Axial, Horizontal, pin pitch=100mm, , length*diameter=93*35.0mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/42037/53d.pdf +CP Axial series Axial Horizontal pin pitch 100mm length 93mm diameter 35.0mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D4.0mm_P1.50mm +CP, Radial series, Radial, pin pitch=1.50mm, , diameter=4mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 1.50mm diameter 4mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D4.0mm_P2.00mm +CP, Radial series, Radial, pin pitch=2.00mm, , diameter=4mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.00mm diameter 4mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D5.0mm_P2.00mm +CP, Radial series, Radial, pin pitch=2.00mm, , diameter=5mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.00mm diameter 5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D5.0mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=5mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D6.3mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=6.3mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 6.3mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D7.5mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=7.5mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 7.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D8.0mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=8mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D8.0mm_P3.50mm +CP, Radial series, Radial, pin pitch=3.50mm, , diameter=8mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 3.50mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D8.0mm_P3.80mm +CP, Radial series, Radial, pin pitch=3.80mm, , diameter=8mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 3.80mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D8.0mm_P5.00mm +CP, Radial series, Radial, pin pitch=5.00mm, , diameter=8mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 5.00mm diameter 8mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D10.0mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D10.0mm_P2.50mm_P5.00mm +CP, Radial series, Radial, pin pitch=2.50mm 5.00mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm 5.00mm diameter 10mm Electrolytic Capacitor +0 +4 +2 +Capacitor_THT +CP_Radial_D10.0mm_P3.50mm +CP, Radial series, Radial, pin pitch=3.50mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 3.50mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D10.0mm_P3.80mm +CP, Radial series, Radial, pin pitch=3.80mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 3.80mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D10.0mm_P5.00mm +CP, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 5.00mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D10.0mm_P5.00mm_P7.50mm +CP, Radial series, Radial, pin pitch=5.00mm 7.50mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 5.00mm 7.50mm diameter 10mm Electrolytic Capacitor +0 +4 +2 +Capacitor_THT +CP_Radial_D10.0mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=10mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 10mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D12.5mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=12.5mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 12.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D12.5mm_P5.00mm +CP, Radial series, Radial, pin pitch=5.00mm, , diameter=12.5mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 5.00mm diameter 12.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D12.5mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=12.5mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 12.5mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D13.0mm_P2.50mm +CP, Radial series, Radial, pin pitch=2.50mm, , diameter=13mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 2.50mm diameter 13mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D13.0mm_P5.00mm +CP, Radial series, Radial, pin pitch=5.00mm, , diameter=13mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 5.00mm diameter 13mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D13.0mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=13mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 13mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D14.0mm_P5.00mm +CP, Radial series, Radial, pin pitch=5.00mm, , diameter=14mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 5.00mm diameter 14mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D14.0mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=14mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 14mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D16.0mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=16mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 16mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D17.0mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=17mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 17mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D18.0mm_P7.50mm +CP, Radial series, Radial, pin pitch=7.50mm, , diameter=18mm, Electrolytic Capacitor +CP Radial series Radial pin pitch 7.50mm diameter 18mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D22.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 22mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D22.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=22mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 22mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D24.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=24mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 24mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D24.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=24mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 24mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D25.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=25mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 25mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D25.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=25mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 25mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D26.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=26mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 26mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D26.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=26mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 26mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D30.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=30mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 30mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D30.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=30mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 30mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D35.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=35mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 35mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D35.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=35mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 35mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_D40.0mm_P10.00mm_3pin_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=40mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 40mm Electrolytic Capacitor +0 +3 +2 +Capacitor_THT +CP_Radial_D40.0mm_P10.00mm_SnapIn +CP, Radial series, Radial, pin pitch=10.00mm, , diameter=40mm, Electrolytic Capacitor, , http://www.vishay.com/docs/28342/058059pll-si.pdf +CP Radial series Radial pin pitch 10.00mm diameter 40mm Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D4.5mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=4.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 4.5mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D4.5mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=4.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 4.5mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D5.0mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=5.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 5.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D5.0mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=5.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 5.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D5.5mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=5.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 5.5mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D5.5mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=5.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 5.5mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D6.0mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=6.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 6.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D6.0mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=6.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 6.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D7.0mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=7.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 7.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D7.0mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=7.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 7.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D8.0mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=8.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 8.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D8.0mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=8.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 8.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D9.0mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=9.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 9.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D9.0mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=9.0mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 9.0mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D10.5mm_P2.50mm +CP, Radial_Tantal series, Radial, pin pitch=2.50mm, , diameter=10.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 2.50mm diameter 10.5mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +CP_Radial_Tantal_D10.5mm_P5.00mm +CP, Radial_Tantal series, Radial, pin pitch=5.00mm, , diameter=10.5mm, Tantal Electrolytic Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/TANTAL-TB-Serie%23.pdf +CP Radial_Tantal series Radial pin pitch 5.00mm diameter 10.5mm Tantal Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Axial_L3.8mm_D2.6mm_P7.50mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=7.5mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 7.5mm length 3.8mm diameter 2.6mm +0 +2 +2 +Capacitor_THT +C_Axial_L3.8mm_D2.6mm_P10.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=10mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 10mm length 3.8mm diameter 2.6mm +0 +2 +2 +Capacitor_THT +C_Axial_L3.8mm_D2.6mm_P12.50mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=12.5mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 12.5mm length 3.8mm diameter 2.6mm +0 +2 +2 +Capacitor_THT +C_Axial_L3.8mm_D2.6mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=3.8*2.6mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 15mm length 3.8mm diameter 2.6mm +0 +2 +2 +Capacitor_THT +C_Axial_L5.1mm_D3.1mm_P7.50mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=7.5mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 7.5mm length 5.1mm diameter 3.1mm +0 +2 +2 +Capacitor_THT +C_Axial_L5.1mm_D3.1mm_P10.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=10mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 10mm length 5.1mm diameter 3.1mm +0 +2 +2 +Capacitor_THT +C_Axial_L5.1mm_D3.1mm_P12.50mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=12.5mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 12.5mm length 5.1mm diameter 3.1mm +0 +2 +2 +Capacitor_THT +C_Axial_L5.1mm_D3.1mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=5.1*3.1mm^2, http://www.vishay.com/docs/45231/arseries.pdf +C Axial series Axial Horizontal pin pitch 15mm length 5.1mm diameter 3.1mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D6.5mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 6.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D6.5mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 6.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D7.5mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 7.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D7.5mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 7.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D8.5mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*8.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 8.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D8.5mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*8.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 8.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D9.5mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 9.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D9.5mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 9.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D10.5mm_P15.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=12*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 15mm length 12mm diameter 10.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L12.0mm_D10.5mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=12*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 12mm diameter 10.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L17.0mm_D6.5mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=17*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 17mm diameter 6.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L17.0mm_D6.5mm_P25.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=17*6.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 25mm length 17mm diameter 6.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L17.0mm_D7.0mm_P20.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=20mm, , length*diameter=17*7.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 20mm length 17mm diameter 7.0mm +0 +2 +2 +Capacitor_THT +C_Axial_L17.0mm_D7.0mm_P25.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=17*7.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 25mm length 17mm diameter 7.0mm +0 +2 +2 +Capacitor_THT +C_Axial_L19.0mm_D7.5mm_P25.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*7.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 7.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L19.0mm_D8.0mm_P25.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*8.0mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 8.0mm +0 +2 +2 +Capacitor_THT +C_Axial_L19.0mm_D9.0mm_P25.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*9mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 9mm +0 +2 +2 +Capacitor_THT +C_Axial_L19.0mm_D9.5mm_P25.00mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=25mm, , length*diameter=19*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 25mm length 19mm diameter 9.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L22.0mm_D9.5mm_P27.50mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=27.5mm, , length*diameter=22*9.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 27.5mm length 22mm diameter 9.5mm +0 +2 +2 +Capacitor_THT +C_Axial_L22.0mm_D10.5mm_P27.50mm_Horizontal +C, Axial series, Axial, Horizontal, pin pitch=27.5mm, , length*diameter=22*10.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B300/STYROFLEX.pdf +C Axial series Axial Horizontal pin pitch 27.5mm length 22mm diameter 10.5mm +0 +2 +2 +Capacitor_THT +C_Disc_D3.0mm_W1.6mm_P2.50mm +C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.0*1.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf +C Disc series Radial pin pitch 2.50mm diameter 3.0mm width 1.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D3.0mm_W2.0mm_P2.50mm +C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3*2mm^2, Capacitor +C Disc series Radial pin pitch 2.50mm diameter 3mm width 2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D3.4mm_W2.1mm_P2.50mm +C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.4*2.1mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf +C Disc series Radial pin pitch 2.50mm diameter 3.4mm width 2.1mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D3.8mm_W2.6mm_P2.50mm +C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=3.8*2.6mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf +C Disc series Radial pin pitch 2.50mm diameter 3.8mm width 2.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D4.3mm_W1.9mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.3*1.9mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf +C Disc series Radial pin pitch 5.00mm diameter 4.3mm width 1.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D4.7mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf +C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D5.0mm_W2.5mm_P2.50mm +C, Disc series, Radial, pin pitch=2.50mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 2.50mm diameter 5mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D5.0mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 5.00mm diameter 5mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D5.1mm_W3.2mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=5.1*3.2mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf +C Disc series Radial pin pitch 5.00mm diameter 5.1mm width 3.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D6.0mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=6*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 5.00mm diameter 6mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D6.0mm_W4.4mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=6*4.4mm^2, Capacitor +C Disc series Radial pin pitch 5.00mm diameter 6mm width 4.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D7.0mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 5.00mm diameter 7mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D7.5mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*2.5mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 5.00mm diameter 7.5mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D7.5mm_W4.4mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*4.4mm^2, Capacitor +C Disc series Radial pin pitch 5.00mm diameter 7.5mm width 4.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D7.5mm_W5.0mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 5.00mm diameter 7.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D7.5mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 7.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D7.5mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=7.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 7.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D8.0mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=8*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 5.00mm diameter 8mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D8.0mm_W5.0mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 5.00mm diameter 8mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D8.0mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 8mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D8.0mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=8*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 8mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D9.0mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=9*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 5.00mm diameter 9mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D9.0mm_W5.0mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 5.00mm diameter 9mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D9.0mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 9mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D9.0mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=9*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 9mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D10.0mm_W2.5mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=10*2.5mm^2, Capacitor, http://cdn-reichelt.de/documents/datenblatt/B300/DS_KERKO_TC.pdf +C Disc series Radial pin pitch 5.00mm diameter 10mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D10.5mm_W5.0mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 5.00mm diameter 10.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D10.5mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 10.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D10.5mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=10.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 10.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D11.0mm_W5.0mm_P5.00mm +C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 5.00mm diameter 11mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D11.0mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 11mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D11.0mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=11*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 11mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D12.0mm_W4.4mm_P7.75mm +C, Disc series, Radial, pin pitch=7.75mm, , diameter*width=12*4.4mm^2, Capacitor +C Disc series Radial pin pitch 7.75mm diameter 12mm width 4.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D12.5mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=12.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 12.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D12.5mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=12.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 12.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D14.5mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=14.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 14.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D14.5mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=14.5*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 14.5mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D16.0mm_W5.0mm_P7.50mm +C, Disc series, Radial, pin pitch=7.50mm, , diameter*width=16.0*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 7.50mm diameter 16.0mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Disc_D16.0mm_W5.0mm_P10.00mm +C, Disc series, Radial, pin pitch=10.00mm, , diameter*width=16.0*5.0mm^2, Capacitor, http://www.vishay.com/docs/28535/vy2series.pdf +C Disc series Radial pin pitch 10.00mm diameter 16.0mm width 5.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D4.0mm_H5.0mm_P1.50mm +C, Radial series, Radial, pin pitch=1.50mm, diameter=4mm, height=5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 1.50mm diameter 4mm height 5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D4.0mm_H7.0mm_P1.50mm +C, Radial series, Radial, pin pitch=1.50mm, diameter=4mm, height=7mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 1.50mm diameter 4mm height 7mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D5.0mm_H5.0mm_P2.00mm +C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 2.00mm diameter 5mm height 5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D5.0mm_H7.0mm_P2.00mm +C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=7mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 2.00mm diameter 5mm height 7mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D5.0mm_H11.0mm_P2.00mm +C, Radial series, Radial, pin pitch=2.00mm, diameter=5mm, height=11mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 2.00mm diameter 5mm height 11mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D6.3mm_H5.0mm_P2.50mm +C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D6.3mm_H7.0mm_P2.50mm +C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=7mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 7mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D6.3mm_H11.0mm_P2.50mm +C, Radial series, Radial, pin pitch=2.50mm, diameter=6.3mm, height=11mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 2.50mm diameter 6.3mm height 11mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D8.0mm_H7.0mm_P3.50mm +C, Radial series, Radial, pin pitch=3.50mm, diameter=8mm, height=7mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 3.50mm diameter 8mm height 7mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D8.0mm_H11.5mm_P3.50mm +C, Radial series, Radial, pin pitch=3.50mm, diameter=8mm, height=11.5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 3.50mm diameter 8mm height 11.5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D10.0mm_H12.5mm_P5.00mm +C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=12.5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 5.00mm diameter 10mm height 12.5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D10.0mm_H16.0mm_P5.00mm +C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=16mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 5.00mm diameter 10mm height 16mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D10.0mm_H20.0mm_P5.00mm +C, Radial series, Radial, pin pitch=5.00mm, diameter=10mm, height=20mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 5.00mm diameter 10mm height 20mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D12.5mm_H20.0mm_P5.00mm +C, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=20mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 5.00mm diameter 12.5mm height 20mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D12.5mm_H25.0mm_P5.00mm +C, Radial series, Radial, pin pitch=5.00mm, diameter=12.5mm, height=25mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 5.00mm diameter 12.5mm height 25mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D16.0mm_H25.0mm_P7.50mm +C, Radial series, Radial, pin pitch=7.50mm, diameter=16mm, height=25mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 7.50mm diameter 16mm height 25mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D16.0mm_H31.5mm_P7.50mm +C, Radial series, Radial, pin pitch=7.50mm, diameter=16mm, height=31.5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 7.50mm diameter 16mm height 31.5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Radial_D18.0mm_H35.5mm_P7.50mm +C, Radial series, Radial, pin pitch=7.50mm, diameter=18mm, height=35.5mm, Non-Polar Electrolytic Capacitor +C Radial series Radial pin pitch 7.50mm diameter 18mm height 35.5mm Non-Polar Electrolytic Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L4.0mm_W2.5mm_P2.50mm +C, Rect series, Radial, pin pitch=2.50mm, , length*width=4*2.5mm^2, Capacitor +C Rect series Radial pin pitch 2.50mm length 4mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L4.6mm_W2.0mm_P2.50mm_MKS02_FKP02 +C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*2mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf +C Rect series Radial pin pitch 2.50mm length 4.6mm width 2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L4.6mm_W3.0mm_P2.50mm_MKS02_FKP02 +C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*3.0mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf +C Rect series Radial pin pitch 2.50mm length 4.6mm width 3.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L4.6mm_W3.8mm_P2.50mm_MKS02_FKP02 +C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*3.8mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf +C Rect series Radial pin pitch 2.50mm length 4.6mm width 3.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L4.6mm_W4.6mm_P2.50mm_MKS02_FKP02 +C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*4.6mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf +C Rect series Radial pin pitch 2.50mm length 4.6mm width 4.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L4.6mm_W5.5mm_P2.50mm_MKS02_FKP02 +C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*5.5mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf +C Rect series Radial pin pitch 2.50mm length 4.6mm width 5.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.0mm_W2.0mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*2mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7mm width 2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.0mm_W2.5mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*2.5mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.0mm_W3.5mm_P2.50mm_P5.00mm +C, Rect series, Radial, pin pitch=2.50mm 5.00mm, , length*width=7*3.5mm^2, Capacitor +C Rect series Radial pin pitch 2.50mm 5.00mm length 7mm width 3.5mm Capacitor +0 +4 +2 +Capacitor_THT +C_Rect_L7.0mm_W3.5mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*3.5mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7mm width 3.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.0mm_W4.5mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*4.5mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7mm width 4.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.0mm_W6.0mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*6mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7mm width 6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.0mm_W6.5mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7*6.5mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7mm width 6.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*2.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W3.0mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*3.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 3.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W3.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*3.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 3.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W4.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*4.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 4.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W5.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*5.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 5.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W7.2mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*7.2mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 7.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W8.5mm_P5.00mm_FKP2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*8.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 8.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.2mm_W11.0mm_P5.00mm_FKS2_FKP2_MKS2_MKP2 +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.2*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_2.pdf +C Rect series Radial pin pitch 5.00mm length 7.2mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L7.5mm_W6.5mm_P5.00mm +C, Rect series, Radial, pin pitch=5.00mm, , length*width=7.5*6.5mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm length 7.5mm width 6.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W2.5mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W2.6mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 2.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W2.7mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*2.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 2.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W3.2mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 3.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W3.3mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 3.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W3.4mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 3.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W3.6mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 3.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W3.8mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 3.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W3.9mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*3.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 3.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W4.0mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 4.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W4.2mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 4.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W4.9mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*4.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 4.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W5.1mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 5.1mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W5.7mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*5.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 5.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W6.4mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 6.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W6.7mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*6.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 6.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W7.7mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*7.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 7.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W8.5mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*8.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 8.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W9.5mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*9.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 9.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L9.0mm_W9.8mm_P7.50mm_MKT +C, Rect series, Radial, pin pitch=7.50mm, , length*width=9*9.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 7.50mm length 9mm width 9.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.0mm_W2.5mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*2.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10mm width 2.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.0mm_W3.0mm_P7.50mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*3mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 7.50mm length 10mm width 3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.0mm_W3.0mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*3.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10mm width 3.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.0mm_W4.0mm_P7.50mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 7.50mm length 10mm width 4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.0mm_W4.0mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10*4.0mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10mm width 4.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.0mm_W5.0mm_P5.00mm_P7.50mm +C, Rect series, Radial, pin pitch=5.00mm 7.50mm, , length*width=10*5mm^2, Capacitor +C Rect series Radial pin pitch 5.00mm 7.50mm length 10mm width 5mm Capacitor +0 +4 +2 +Capacitor_THT +C_Rect_L10.3mm_W4.5mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*4.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10.3mm width 4.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.3mm_W5.0mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10.3mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.3mm_W5.7mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*5.7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10.3mm width 5.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L10.3mm_W7.2mm_P7.50mm_MKS4 +C, Rect series, Radial, pin pitch=7.50mm, , length*width=10.3*7.2mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 7.50mm length 10.3mm width 7.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W2.8mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*2.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 2.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W3.4mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*3.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 3.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W3.5mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*3.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 3.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W4.2mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*4.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 4.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W4.3mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*4.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 4.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W5.1mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 5.1mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W5.3mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*5.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 5.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W6.3mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*6.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 6.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W6.4mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 6.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W7.3mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 7.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.0mm_W8.8mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.0*8.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.0mm width 8.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W2.0mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W2.6mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 2.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W2.8mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*2.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 2.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W3.2mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 3.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W3.5mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 3.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W3.6mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*3.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 3.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W4.0mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 4.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W4.3mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 4.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W4.5mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*4.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 4.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W5.0mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W5.1mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 5.1mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W5.2mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 5.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W5.6mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*5.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 5.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W6.4mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.4mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 6.4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W6.6mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 6.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W6.9mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*6.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 6.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W7.3mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 7.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W7.5mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 7.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W7.8mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*7.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 7.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W8.0mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*8.0mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 8.0mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W8.8mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*8.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 8.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W9.5mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*9.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 9.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L11.5mm_W9.8mm_P10.00mm_MKT +C, Rect series, Radial, pin pitch=10.00mm, , length*width=11.5*9.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 10.00mm length 11.5mm width 9.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.0mm_W3.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*3mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13mm width 3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.0mm_W4.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13mm width 4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.0mm_W5.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.0mm_W6.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13mm width 6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.0mm_W6.5mm_P7.50mm_P10.00mm +C, Rect series, Radial, pin pitch=7.50mm 10.00mm, , length*width=13*6.5mm^2, Capacitor +C Rect series Radial pin pitch 7.50mm 10.00mm length 13mm width 6.5mm Capacitor +0 +4 +2 +Capacitor_THT +C_Rect_L13.0mm_W8.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13mm width 8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.5mm_W4.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13.5*4mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13.5mm width 4mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L13.5mm_W5.0mm_P10.00mm_FKS3_FKP3_MKS4 +C, Rect series, Radial, pin pitch=10.00mm, , length*width=13.5*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 10.00mm length 13.5mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W4.7mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*4.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 4.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W4.9mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*4.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 4.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W5.0mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W6.0mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W7.0mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W7.3mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*7.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 7.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W8.7mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*8.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 8.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W8.9mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*8.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 8.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W9.0mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W9.2mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*9.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 9.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W10.7mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*10.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 10.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W10.9mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*10.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 10.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W11.2mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*11.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 11.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W11.8mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*11.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 11.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W13.5mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.5mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 13.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W13.7mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 13.7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L16.5mm_W13.9mm_P15.00mm_MKT +C, Rect series, Radial, pin pitch=15.00mm, , length*width=16.5*13.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 15.00mm length 16.5mm width 13.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L18.0mm_W5.0mm_P15.00mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 15.00mm length 18mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L18.0mm_W6.0mm_P15.00mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 15.00mm length 18mm width 6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 15.00mm length 18mm width 7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L18.0mm_W8.0mm_P15.00mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 15.00mm length 18mm width 8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L18.0mm_W9.0mm_P15.00mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 15.00mm length 18mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L18.0mm_W11.0mm_P15.00mm_FKS3_FKP3 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf +C Rect series Radial pin pitch 15.00mm length 18mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L19.0mm_W5.0mm_P15.00mm_MKS4 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 15.00mm length 19mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L19.0mm_W6.0mm_P15.00mm_MKS4 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 15.00mm length 19mm width 6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L19.0mm_W7.0mm_P15.00mm_MKS4 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 15.00mm length 19mm width 7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L19.0mm_W8.0mm_P15.00mm_MKS4 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 15.00mm length 19mm width 8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L19.0mm_W9.0mm_P15.00mm_MKS4 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 15.00mm length 19mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L19.0mm_W11.0mm_P15.00mm_MKS4 +C, Rect series, Radial, pin pitch=15.00mm, , length*width=19*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 15.00mm length 19mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W7.0mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*7mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W8.3mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*8.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 8.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W8.6mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*8.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 8.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W10.1mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 10.1mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W10.3mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.3mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 10.3mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W10.9mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*10.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 10.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W12.2mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 12.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W12.6mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 12.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L24.0mm_W12.8mm_P22.50mm_MKT +C, Rect series, Radial, pin pitch=22.50mm, , length*width=24*12.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 22.50mm length 24mm width 12.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L26.5mm_W5.0mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 26.5mm width 5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L26.5mm_W6.0mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*6mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 26.5mm width 6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L26.5mm_W7.0mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 26.5mm width 7mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L26.5mm_W8.5mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*8.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 26.5mm width 8.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L26.5mm_W10.5mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*10.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 26.5mm width 10.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L26.5mm_W11.5mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=26.5*11.5mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 26.5mm width 11.5mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L27.0mm_W9.0mm_P22.00mm +C, Rect series, Radial, pin pitch=22.00mm, , length*width=27*9mm^2, Capacitor +C Rect series Radial pin pitch 22.00mm length 27mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L27.0mm_W9.0mm_P23.00mm +C, Rect series, Radial, pin pitch=23.00mm, , length*width=27*9mm^2, Capacitor +C Rect series Radial pin pitch 23.00mm length 27mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L27.0mm_W11.0mm_P22.00mm +C, Rect series, Radial, pin pitch=22.00mm, , length*width=27*11mm^2, Capacitor +C Rect series Radial pin pitch 22.00mm length 27mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L28.0mm_W8.0mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*8mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 28mm width 8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L28.0mm_W10.0mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*10mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 28mm width 10mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L28.0mm_W12.0mm_P22.50mm_MKS4 +C, Rect series, Radial, pin pitch=22.50mm, , length*width=28*12mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 22.50mm length 28mm width 12mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W7.6mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 7.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W7.8mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 7.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W7.9mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*7.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 7.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W9.1mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*9.1mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 9.1mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W9.6mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*9.6mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 9.6mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W11.0mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*11mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W11.9mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*11.9mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 11.9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W12.2mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*12.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 12.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W13.0mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*13mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 13mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W13.8mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*13.8mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 13.8mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W14.2mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*14.2mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 14.2mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L29.0mm_W16.0mm_P27.50mm_MKT +C, Rect series, Radial, pin pitch=27.50mm, , length*width=29*16mm^2, Capacitor, https://en.tdk.eu/inf/20/20/db/fc_2009/MKT_B32560_564.pdf +C Rect series Radial pin pitch 27.50mm length 29mm width 16mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L31.5mm_W9.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 31.5mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L31.5mm_W11.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 31.5mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L31.5mm_W13.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 31.5mm width 13mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 31.5mm width 15mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L31.5mm_W17.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*17mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 31.5mm width 17mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L31.5mm_W20.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 31.5mm width 20mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L32.0mm_W15.0mm_P27.00mm +C, Rect series, Radial, pin pitch=27.00mm, , length*width=32*15mm^2, Capacitor +C Rect series Radial pin pitch 27.00mm length 32mm width 15mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L33.0mm_W13.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 33mm width 13mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L33.0mm_W15.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 33mm width 15mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L33.0mm_W20.0mm_P27.50mm_MKS4 +C, Rect series, Radial, pin pitch=27.50mm, , length*width=33*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 27.50mm length 33mm width 20mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W9.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 9mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W11.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*11mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 11mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W13.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*13mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 13mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W15.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 15mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W17.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*17mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 17mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W19.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*19mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 19mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W20.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*20mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 20mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W24.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*24mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 24mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W31.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*31mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 31mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W35.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*35mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 35mm Capacitor +0 +2 +2 +Capacitor_THT +C_Rect_L41.5mm_W40.0mm_P37.50mm_MKS4 +C, Rect series, Radial, pin pitch=37.50mm, , length*width=41.5*40mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf +C Rect series Radial pin pitch 37.50mm length 41.5mm width 40mm Capacitor +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-1608-08_AVX-J +Tantalum Capacitor SMD AVX-J (1608-08 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-1608-08_AVX-J_Pad1.25x1.05mm_HandSolder +Tantalum Capacitor SMD AVX-J (1608-08 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-1608-10_AVX-L +Tantalum Capacitor SMD AVX-L (1608-10 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-1608-10_AVX-L_Pad1.25x1.05mm_HandSolder +Tantalum Capacitor SMD AVX-L (1608-10 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/48064/_t58_vmn_pt0471_1601.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-2012-12_Kemet-R +Tantalum Capacitor SMD Kemet-R (2012-12 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-2012-12_Kemet-R_Pad1.30x1.05mm_HandSolder +Tantalum Capacitor SMD Kemet-R (2012-12 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-2012-15_AVX-P +Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-2012-15_AVX-P_Pad1.30x1.05mm_HandSolder +Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3216-10_Kemet-I +Tantalum Capacitor SMD Kemet-I (3216-10 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3216-10_Kemet-I_Pad1.58x1.35mm_HandSolder +Tantalum Capacitor SMD Kemet-I (3216-10 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3216-12_Kemet-S +Tantalum Capacitor SMD Kemet-S (3216-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3216-12_Kemet-S_Pad1.58x1.35mm_HandSolder +Tantalum Capacitor SMD Kemet-S (3216-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3216-18_Kemet-A +Tantalum Capacitor SMD Kemet-A (3216-18 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3216-18_Kemet-A_Pad1.58x1.35mm_HandSolder +Tantalum Capacitor SMD Kemet-A (3216-18 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3528-12_Kemet-T +Tantalum Capacitor SMD Kemet-T (3528-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3528-12_Kemet-T_Pad1.50x2.35mm_HandSolder +Tantalum Capacitor SMD Kemet-T (3528-12 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3528-15_AVX-H +Tantalum Capacitor SMD AVX-H (3528-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3528-15_AVX-H_Pad1.50x2.35mm_HandSolder +Tantalum Capacitor SMD AVX-H (3528-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3528-21_Kemet-B +Tantalum Capacitor SMD Kemet-B (3528-21 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-3528-21_Kemet-B_Pad1.50x2.35mm_HandSolder +Tantalum Capacitor SMD Kemet-B (3528-21 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-6032-15_Kemet-U +Tantalum Capacitor SMD Kemet-U (6032-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-6032-15_Kemet-U_Pad2.25x2.35mm_HandSolder +Tantalum Capacitor SMD Kemet-U (6032-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-6032-20_AVX-F +Tantalum Capacitor SMD AVX-F (6032-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-6032-20_AVX-F_Pad2.25x2.35mm_HandSolder +Tantalum Capacitor SMD AVX-F (6032-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-6032-28_Kemet-C +Tantalum Capacitor SMD Kemet-C (6032-28 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-6032-28_Kemet-C_Pad2.25x2.35mm_HandSolder +Tantalum Capacitor SMD Kemet-C (6032-28 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7132-20_AVX-U +Tantalum Capacitor SMD AVX-U (7132-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7132-20_AVX-U_Pad2.72x3.50mm_HandSolder +Tantalum Capacitor SMD AVX-U (7132-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7132-28_AVX-C +Tantalum Capacitor SMD AVX-C (7132-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7132-28_AVX-C_Pad2.72x3.50mm_HandSolder +Tantalum Capacitor SMD AVX-C (7132-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-15_AVX-R +Tantalum Capacitor SMD AVX-R (7260-15 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-15_AVX-R_Pad2.68x6.30mm_HandSolder +Tantalum Capacitor SMD AVX-R (7260-15 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-20_AVX-M +Tantalum Capacitor SMD AVX-M (7260-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-20_AVX-M_Pad2.68x6.30mm_HandSolder +Tantalum Capacitor SMD AVX-M (7260-20 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-28_AVX-M +Tantalum Capacitor SMD AVX-M (7260-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-28_AVX-M_Pad2.68x6.30mm_HandSolder +Tantalum Capacitor SMD AVX-M (7260-28 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-38_AVX-R +Tantalum Capacitor SMD AVX-R (7260-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7260-38_AVX-R_Pad2.68x6.30mm_HandSolder +Tantalum Capacitor SMD AVX-R (7260-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/F72-F75.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-15_Kemet-W +Tantalum Capacitor SMD Kemet-W (7343-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-15_Kemet-W_Pad2.25x2.55mm_HandSolder +Tantalum Capacitor SMD Kemet-W (7343-15 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-20_Kemet-V +Tantalum Capacitor SMD Kemet-V (7343-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-20_Kemet-V_Pad2.25x2.55mm_HandSolder +Tantalum Capacitor SMD Kemet-V (7343-20 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-30_AVX-N +Tantalum Capacitor SMD AVX-N (7343-30 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-30_AVX-N_Pad2.25x2.55mm_HandSolder +Tantalum Capacitor SMD AVX-N (7343-30 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-31_Kemet-D +Tantalum Capacitor SMD Kemet-D (7343-31 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-31_Kemet-D_Pad2.25x2.55mm_HandSolder +Tantalum Capacitor SMD Kemet-D (7343-31 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-40_Kemet-Y +Tantalum Capacitor SMD Kemet-Y (7343-40 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-40_Kemet-Y_Pad2.25x2.55mm_HandSolder +Tantalum Capacitor SMD Kemet-Y (7343-40 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-43_Kemet-X +Tantalum Capacitor SMD Kemet-X (7343-43 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7343-43_Kemet-X_Pad2.25x2.55mm_HandSolder +Tantalum Capacitor SMD Kemet-X (7343-43 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7360-38_Kemet-E +Tantalum Capacitor SMD Kemet-E (7360-38 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7360-38_Kemet-E_Pad2.25x4.25mm_HandSolder +Tantalum Capacitor SMD Kemet-E (7360-38 Metric), IPC_7351 nominal, (Body size from: http://www.kemet.com/Lists/ProductCatalog/Attachments/253/KEM_TC101_STD.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7361-38_AVX-V +Tantalum Capacitor SMD AVX-V (7361-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7361-38_AVX-V_Pad2.18x3.30mm_HandSolder +Tantalum Capacitor SMD AVX-V (7361-38 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7361-438_AVX-U +Tantalum Capacitor SMD AVX-U (7361-438 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Capacitor_Tantalum_SMD +CP_EIA-7361-438_AVX-U_Pad2.18x3.30mm_HandSolder +Tantalum Capacitor SMD AVX-U (7361-438 Metric), IPC_7351 nominal, (Body size from: http://datasheets.avx.com/NOS.pdf), generated with kicad-footprint-generator +capacitor tantalum +0 +2 +2 +Connector +Banana_Jack_1Pin +Single banana socket, footprint - 6mm drill +banana socket +0 +1 +1 +Connector +Banana_Jack_2Pin +Dual banana socket, footprint - 2 x 6mm drills +banana socket +0 +2 +2 +Connector +Banana_Jack_3Pin +Triple banana socket, footprint - 3 x 6mm drills +banana socket +0 +3 +3 +Connector +CUI_PD-30 +3 pin connector, PD-30, http://www.cui.com/product/resource/pd-30.pdf +connector 3-pin PD-30 power DIN +0 +4 +4 +Connector +CalTest_CT3151 +Right-angle standard banana jack, http://www.caltestelectronics.com/images/attachments/P315100rH_drawing.pdf +banana jack horizontal +0 +4 +1 +Connector +Connector_SFP_and_Cage +https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=2227302&DocType=Customer+Drawing&DocLang=English +SFP+ SFP +0 +40 +21 +Connector +DTF13-12Px +http://www.te.com/usa-en/product-DTF13-12PA-G003.html +DEUTSCH DT header 12 pin +0 +12 +12 +Connector +FanPinHeader_1x03_P2.54mm_Vertical +3-pin CPU fan Through hole pin header, see http://www.formfactors.org/developer%5Cspecs%5Crev1_2_public.pdf +pin header 3-pin CPU fan +0 +3 +3 +Connector +FanPinHeader_1x04_P2.54mm_Vertical +4-pin CPU fan Through hole pin header, e.g. for Wieson part number 2366C888-007 Molex 47053-1000, Foxconn HF27040-M1, Tyco 1470947-1 or equivalent, see http://www.formfactors.org/developer%5Cspecs%5Crev1_2_public.pdf +pin header 4-pin CPU fan +0 +4 +4 +Connector +GB042-34S-H10 +http://www.lsmtron.com/pdf/Connector&Antenna_catalog.PDF +34pin SMD connector +0 +34 +34 +Connector +IHI_B6A-PCB-45_Vertical +https://lugsdirect.com/PDF_Webprint/B6A-PCB-45-XX(-X).pdf +connector IHI B6A-PCB-45 +0 +49 +1 +Connector +JWT_A3963_1x02_P3.96mm_Vertical +JWT A3963, 3.96mm pitch Pin head connector (http://www.jwt.com.tw/pro_pdf/A3963.pdf) +connector JWT A3963 pinhead +0 +2 +2 +Connector +NS-Tech_Grove_1x04_P2mm_Vertical +https://statics3.seeedstudio.com/images/opl/datasheet/3470130P1.pdf +Grove-1x04 +0 +4 +4 +Connector +Tag-Connect_TC2030-IDC-FP_2x03_P1.27mm_Vertical +Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC.pdf +tag connect programming header pogo pins +0 +6 +6 +Connector +Tag-Connect_TC2030-IDC-NL_2x03_P1.27mm_Vertical +Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2030-IDC-NL.pdf +tag connect programming header pogo pins +0 +6 +6 +Connector +Tag-Connect_TC2050-IDC-FP_2x05_P1.27mm_Vertical +Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-430%20Datasheet.pdf +tag connect programming header pogo pins +0 +10 +10 +Connector +Tag-Connect_TC2050-IDC-NL_2x05_P1.27mm_Vertical +Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2050-IDC-NL%20Datasheet.pdf +tag connect programming header pogo pins +0 +10 +10 +Connector +Tag-Connect_TC2070-IDC-FP_2x07_P1.27mm_Vertical +Tag-Connect programming header; http://www.tag-connect.com/Materials/TC2070-IDC%20Datasheet.pdf +tag connect programming header pogo pins +0 +14 +14 +Connector_AMASS +AMASS_MR30PW-FB_1x03_P3.50mm_Horizontal +Connector XT30 Horizontal PCB Female, https://www.tme.eu/en/Document/5e47640ba39fa492dbd4c0f4c8ae7b93/MR30PW%20SPEC.pdf +RC Connector XT30 +0 +5 +3 +Connector_AMASS +AMASS_MR30PW-M_1x03_P3.50mm_Horizontal +Connector XT30 Horizontal PCB Male, https://www.tme.eu/en/Document/5e47640ba39fa492dbd4c0f4c8ae7b93/MR30PW%20SPEC.pdf +RC Connector XT30 +0 +5 +3 +Connector_AMASS +AMASS_XT30PW-F_1x02_P2.50mm_Horizontal +Connector XT30 Horizontal PCB Female, https://www.tme.eu/en/Document/ce4077e36b79046da520ca73227e15de/XT30PW%20SPEC.pdf +RC Connector XT30 +0 +4 +2 +Connector_AMASS +AMASS_XT30PW-M_1x02_P2.50mm_Horizontal +Connector XT30 Horizontal PCB Male, https://www.tme.eu/en/Document/ce4077e36b79046da520ca73227e15de/XT30PW%20SPEC.pdf +RC Connector XT30 +0 +4 +2 +Connector_AMASS +AMASS_XT30U-F_1x02_P5.0mm_Vertical +Connector XT30 Vertical Cable Female, https://www.tme.eu/en/Document/3cbfa5cfa544d79584972dd5234a409e/XT30U%20SPEC.pdf +RC Connector XT30 +0 +2 +2 +Connector_AMASS +AMASS_XT30U-M_1x02_P5.0mm_Vertical +Connector XT30 Vertical Cable Male, https://www.tme.eu/en/Document/3cbfa5cfa544d79584972dd5234a409e/XT30U%20SPEC.pdf +RC Connector XT30 +0 +2 +2 +Connector_AMASS +AMASS_XT30UPB-F_1x02_P5.0mm_Vertical +Connector XT30 Vertical PCB Female, https://www.tme.eu/en/Document/4acc913878197f8c2e30d4b8cdc47230/XT30UPB%20SPEC.pdf +RC Connector XT30 +0 +2 +2 +Connector_AMASS +AMASS_XT30UPB-M_1x02_P5.0mm_Vertical +Connector XT30 Vertical PCB Male, https://www.tme.eu/en/Document/4acc913878197f8c2e30d4b8cdc47230/XT30UPB%20SPEC.pdf +RC Connector XT30 +0 +2 +2 +Connector_AMASS +AMASS_XT60-F_1x02_P7.20mm_Vertical +AMASS female XT60, through hole, vertical, https://www.tme.eu/Document/2d152ced3b7a446066e6c419d84bb460/XT60%20SPEC.pdf +XT60 female vertical +0 +2 +2 +Connector_AMASS +AMASS_XT60-M_1x02_P7.20mm_Vertical +AMASS female XT60, through hole, vertical, https://www.tme.eu/Document/2d152ced3b7a446066e6c419d84bb460/XT60%20SPEC.pdf +XT60 female vertical +0 +2 +2 +Connector_Audio +Jack_3.5mm_CUI_SJ-3523-SMT_Horizontal +3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf) +3.5mm audio cui horizontal jack stereo +0 +3 +3 +Connector_Audio +Jack_3.5mm_CUI_SJ-3524-SMT_Horizontal +3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf) +3.5mm audio cui horizontal jack stereo +0 +4 +4 +Connector_Audio +Jack_3.5mm_CUI_SJ1-3533NG_Horizontal +TRS 3.5mm, horizontal, through-hole, https://www.cui.com/product/resource/sj1-353xng.pdf +TRS audio jack stereo horizontal +0 +3 +3 +Connector_Audio +Jack_3.5mm_CUI_SJ1-3533NG_Horizontal_CircularHoles +TRS 3.5mm, horizontal, through-hole, , circular holeshttps://www.cui.com/product/resource/sj1-353xng.pdf +TRS audio jack stereo horizontal circular +0 +3 +3 +Connector_Audio +Jack_3.5mm_CUI_SJ1-3535NG_Horizontal +TRS 3.5mm, horizontal, through-hole, with switch, https://www.cui.com/product/resource/sj1-353xng.pdf +TRS audio jack stereo horizontal +0 +5 +5 +Connector_Audio +Jack_3.5mm_CUI_SJ1-3535NG_Horizontal_CircularHoles +TRS 3.5mm, horizontal, through-hole, with switch, circular holes, https://www.cui.com/product/resource/sj1-353xng.pdf +TRS audio jack stereo horizontal circular +0 +5 +5 +Connector_Audio +Jack_3.5mm_Ledino_KB3SPRS_Horizontal +https://www.reichelt.de/index.html?ACTION=7&LA=3&OPEN=0&INDEX=0&FILENAME=C160%252FKB3SPRS.pdf +jack stereo TRS +0 +5 +5 +Connector_Audio +Jack_3.5mm_Neutrik_NMJ6HCD2_Horizontal +NMJ6HCD2, TRS 1/4in (http://www.neutrik.com/en/audio/plugs-and-jacks/m-series/nmj6hcd2) +NMJ6HCD2 TRS stereo jack connector +0 +6 +6 +Connector_Audio +Jack_3.5mm_PJ311_Horizontal +PJ311 6pin SMD 3.5mm stereo headphones jack. +headphones jack plug stereo 3.5mm PJ311 +0 +6 +6 +Connector_Audio +Jack_3.5mm_PJ320D_Horizontal +Headphones with microphone connector, 3.5mm, 4 pins (http://www.qingpu-electronics.com/en/products/WQP-PJ320D-72.html) +3.5mm jack mic microphone phones headphones 4pins audio plug +0 +4 +4 +Connector_Audio +Jack_3.5mm_PJ320E_Horizontal +Headphones with microphone connector, 3.5mm, 4 pins (http://www.qingpu-electronics.com/en/products/WQP-PJ320E-177.html) +3.5mm jack mic microphone phones headphones 4pins audio plug +0 +5 +4 +Connector_Audio +Jack_3.5mm_PJ31060-I_Horizontal +PJ31060-I 6pin SMD 3.5mm headphones jack (http://www.china-bsun.com/Product48/1577.html) +headphones jack plug stereo 3.5mm PJ31060-I PJ31060 +0 +6 +6 +Connector_Audio +Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles +TRS 3.5mm, vertical, Thonkiconn, PCB mount, (http://www.qingpu-electronics.com/en/products/WQP-PJ398SM-362.html) +WQP-PJ398SM WQP-PJ301M-12 TRS 3.5mm mono vertical jack thonkiconn qingpu +0 +3 +3 +Connector_Audio +Jack_3.5mm_Switronic_ST-005-G_horizontal +3.5mm horizontal headphones jack, http://akizukidenshi.com/download/ds/switronic/ST-005-G.pdf +Connector Audio Switronic ST-005-G +0 +4 +3 +Connector_Audio +MiniXLR-5_Switchcraft_TRAPC_Horizontal +http://www.switchcraft.com/ProductSummary.aspx?Parent=620 http://www.switchcraft.com/Drawings/TRAPC_X-TRASM_X_SERIES_CD.PDF +THT Mini XLR 5Pin right angle +0 +5 +5 +Connector_BarrelJack +BarrelJack_CUI_PJ-036AH-SMT_Horizontal +Surface-mount DC Barrel Jack, http://www.cui.com/product/resource/pj-036ah-smt.pdf +Power Jack SMT +0 +3 +3 +Connector_BarrelJack +BarrelJack_CUI_PJ-063AH_Horizontal +Barrel Jack, 2.0mm ID, 5.5mm OD, 24V, 8A, no switch, https://www.cui.com/product/resource/pj-063ah.pdf +barrel jack cui dc power +0 +4 +3 +Connector_BarrelJack +BarrelJack_CUI_PJ-063AH_Horizontal_CircularHoles +Barrel Jack, 2.0mm ID, 5.5mm OD, 24V, 8A, no switch, https://www.cui.com/product/resource/pj-063ah.pdf +barrel jack cui dc power +0 +4 +3 +Connector_BarrelJack +BarrelJack_CUI_PJ-102AH_Horizontal +Thin-pin DC Barrel Jack, https://cdn-shop.adafruit.com/datasheets/21mmdcjackDatasheet.pdf +Power Jack +0 +3 +3 +Connector_BarrelJack +BarrelJack_Horizontal +DC Barrel Jack +Power Jack +0 +3 +3 +Connector_BarrelJack +BarrelJack_Wuerth_6941xx301002 +Wuerth electronics barrel jack connector (5.5mm outher diameter, inner diameter 2.05mm or 2.55mm depending on exact order number), See: http://katalog.we-online.de/em/datasheet/6941xx301002.pdf +connector barrel jack +0 +3 +3 +Connector_Card +CF-Card_3M_N7E50-7516PK-20-WF +Compact Flash Card connector (https://multimedia.3m.com/mws/media/22365O/3mtm-cf-card-header-compactflashtm-type-i-sm-ts0662.pdf) +connector cf +0 +54 +50 +Connector_Card +SD_Kyocera_145638009211859+ +SD Card Connector, Normal Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) +sd card smt +0 +13 +12 +Connector_Card +SD_Kyocera_145638009511859+ +SD Card Connector, Normal Type, Outer Tail, Spring Eject Type (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) +sd card smt +0 +13 +12 +Connector_Card +SD_Kyocera_145638109211859+ +SD Card Connector, Reverse Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) +sd card smt +0 +13 +12 +Connector_Card +SD_Kyocera_145638109511859+ +SD Card Connector, Reverse Type, Outer Tail, Spring Eject Type (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf) +sd card smt +0 +13 +12 +Connector_Card +SD_TE_2041021 +SD card connector, top mount, SMT (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F2041021%7FB%7Fpdf%7FEnglish%7FENG_CD_2041021_B_C_2041021_B.pdf%7F2041021-4) +sd card +0 +15 +12 +Connector_Card +microSD_HC_Hirose_DM3AT-SF-PEJM5 +Micro SD, SMD, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3AT-SF-PEJM5/category/Drawing%20(2D)/doc_file_id/44099/?file_category_id=6&item_id=06090031000&is_series=) +Micro SD +0 +14 +11 +Connector_Card +microSD_HC_Hirose_DM3BT-DSF-PEJS +Micro SD, SMD, reverse on-board, right-angle, push-pull (https://www.hirose.com/product/en/download_file/key_name/DM3BT-DSF-PEJS/category/Drawing%20(2D)/doc_file_id/44097/?file_category_id=6&item_id=06090029900&is_series=) +Micro SD +0 +16 +11 +Connector_Card +microSD_HC_Hirose_DM3D-SF +Micro SD, SMD, right-angle, push-pull (https://media.digikey.com/PDF/Data%20Sheets/Hirose%20PDFs/DM3D-SF.pdf) +Micro SD +0 +14 +11 +Connector_Card +microSD_HC_Molex_104031-0811 +1.10mm Pitch microSD Memory Card Connector, Surface Mount, Push-Pull Type, 1.42mm Height, with Detect Switch (https://www.molex.com/pdm_docs/sd/1040310811_sd.pdf) +microSD SD molex +0 +14 +11 +Connector_Card +microSD_HC_Wuerth_693072010801 +http://katalog.we-online.de/em/datasheet/693072010801.pdf +Micro SD Wuerth Wurth Würth +0 +12 +9 +Connector_Card +microSIM_JAE_SF53S006VCBR2000 +https://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ115712.pdf +microSIM GSM Card +0 +14 +7 +Connector_Coaxial +BNC_Amphenol_031-6575_Horizontal +dual independently isolated BNC plug (https://www.amphenolrf.com/downloads/dl/file/id/2980/product/644/031_6575_customer_drawing.pdf) +Dual BNC Amphenol Horizontal +0 +6 +4 +Connector_Coaxial +BNC_Amphenol_B6252HB-NPP3G-50_Horizontal +http://www.farnell.com/datasheets/612848.pdf +BNC Amphenol Horizontal +0 +4 +2 +Connector_Coaxial +BNC_PanelMountable_Vertical +Panel-mountable BNC connector mounted through PCB, vertical +BNC connector +0 +2 +2 +Connector_Coaxial +BNC_TEConnectivity_1478204_Vertical +BNC female PCB mount 4 pin straight chassis connector http://www.te.com/usa-en/product-1-1478204-0.html +BNC female PCB mount 4 pin straight chassis connector +0 +5 +2 +Connector_Coaxial +BNC_Win_364A2x95_Horizontal +Dual front isolated BNC plug (https://www.winconn.com/wp-content/uploads/364A2595.pdf) +Dual BNC Horizontal Isolated +0 +6 +3 +Connector_Coaxial +MMCX_Molex_73415-0961_Horizontal_0.8mm-PCB +Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf +Molex MMCX Horizontal Coaxial +0 +3 +2 +Connector_Coaxial +MMCX_Molex_73415-0961_Horizontal_1.0mm-PCB +Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf +Molex MMCX Horizontal Coaxial +0 +3 +2 +Connector_Coaxial +MMCX_Molex_73415-0961_Horizontal_1.6mm-PCB +Molex MMCX Horizontal Coaxial https://www.molex.com/pdm_docs/sd/734150961_sd.pdf +Molex MMCX Horizontal Coaxial +0 +3 +2 +Connector_Coaxial +MMCX_Molex_73415-1471_Vertical +http://www.molex.com/pdm_docs/sd/734151471_sd.pdf +Molex MMCX Coaxial Connector 50 ohms Female Jack Vertical THT +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_901-144_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/7023/product/3103/901_144_customer_drawing.pdf +SMA THT Female Jack Vertical +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132134-10_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/4007/product/2974/132134_10_customer_drawing.pdf +SMA SMD Female Jack Vertical +0 +3 +2 +Connector_Coaxial +SMA_Amphenol_132134-11_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/3406/product/2975/132134_11_customer_drawing.pdf +SMA THT Female Jack Vertical ExtendedLegs +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132134-14_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/1793/product/2976/132134_14_customer_drawing.pdf +SMA THT Female Jack Vertical ExtendedLegs +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132134-16_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/1141/product/2978/132134_16_customer_drawing.pdf +SMA THT Female Jack Vertical ExtendedLegs +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132134_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/2187/product/2843/132134_customer_drawing.pdf +SMA THT Female Jack Vertical ExtendedLegs +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132203-12_Horizontal +https://www.amphenolrf.com/media/downloads/1769/132203-12.pdf +SMA THT Female Jack Horizontal +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132289_EdgeMount +http://www.amphenolrf.com/132289.html +SMA +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132291-12_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/1688/product/3020/132291_12_customer_drawing.pdf +SMA THT Female Jack Vertical Bulkhead +0 +5 +2 +Connector_Coaxial +SMA_Amphenol_132291_Vertical +https://www.amphenolrf.com/downloads/dl/file/id/3222/product/2918/132291_customer_drawing.pdf +SMA THT Female Jack Vertical Bulkhead +0 +5 +2 +Connector_Coaxial +SMA_Molex_73251-1153_EdgeMount_Horizontal +Molex SMA RF Connectors, Edge Mount, (http://www.molex.com/pdm_docs/sd/732511150_sd.pdf) +sma edge +0 +11 +2 +Connector_Coaxial +SMA_Molex_73251-2200_Horizontal +https://www.molex.com/webdocs/datasheets/pdf/en-us/0732512200_RF_COAX_CONNECTORS.pdf +SMA THT Female Jack Horizontal +0 +5 +2 +Connector_Coaxial +SMA_Samtec_SMA-J-P-X-ST-EM1_EdgeMount +Connector SMA, 0Hz to 20GHz, 50Ohm, Edge Mount (http://suddendocs.samtec.com/prints/sma-j-p-x-st-em1-mkt.pdf) +SMA Straight Samtec Edge Mount +0 +5 +2 +Connector_Coaxial +SMB_Jack_Vertical +SMB pcb mounting jack +SMB Jack Striaght +0 +5 +2 +Connector_Coaxial +U.FL_Hirose_U.FL-R-SMT-1_Vertical +Hirose U.FL Coaxial https://www.hirose.com/product/en/products/U.FL/U.FL-R-SMT-1%2810%29/ +Hirose U.FL Coaxial +0 +3 +2 +Connector_Coaxial +U.FL_Molex_MCRF_73412-0110_Vertical +Molex Microcoaxial RF Connectors (MCRF), mates Hirose U.FL, (http://www.molex.com/pdm_docs/sd/734120110_sd.pdf) +mcrf hirose ufl u.fl microcoaxial +0 +4 +2 +Connector_DIN +DIN41612_B2_2x8_Horizontal +DIN 41612 connector, type B/2, horizontal, 16 pins wide, 2 rows, even columns +DIN 41512 IEC 60603 B/2 +0 +16 +16 +Connector_DIN +DIN41612_B2_2x8_Vertical +DIN 41612 connector, type B/2, vertical, 16 pins wide, 2 rows, even columns +DIN 41512 IEC 60603 B/2 +0 +16 +16 +Connector_DIN +DIN41612_B2_2x16_Horizontal +DIN 41612 connector, type B/2, horizontal, 16 pins wide, 2 rows, full configuration +DIN 41512 IEC 60603 B/2 +0 +32 +32 +Connector_DIN +DIN41612_B2_2x16_Vertical +DIN 41612 connector, type B/2, vertical, 16 pins wide, 2 rows, full configuration +DIN 41512 IEC 60603 B/2 +0 +32 +32 +Connector_DIN +DIN41612_B3_2x5_Horizontal +DIN 41612 connector, type B/3, horizontal, 10 pins wide, 2 rows, even columns +DIN 41512 IEC 60603 B/3 +0 +10 +10 +Connector_DIN +DIN41612_B3_2x5_Vertical +DIN 41612 connector, type B/3, vertical, 10 pins wide, 2 rows, even columns +DIN 41512 IEC 60603 B/3 +0 +10 +10 +Connector_DIN +DIN41612_B3_2x10_Horizontal +DIN 41612 connector, type B/3, horizontal, 10 pins wide, 2 rows, full configuration +DIN 41512 IEC 60603 B/3 +0 +20 +20 +Connector_DIN +DIN41612_B3_2x10_Vertical +DIN 41612 connector, type B/3, vertical, 10 pins wide, 2 rows, full configuration +DIN 41512 IEC 60603 B/3 +0 +20 +20 +Connector_DIN +DIN41612_B_2x16_Horizontal +DIN 41612 connector, type B, horizontal, 32 pins wide, 2 rows, even columns +DIN 41512 IEC 60603 B +0 +32 +32 +Connector_DIN +DIN41612_B_2x16_Vertical +DIN 41612 connector, type B, vertical, 32 pins wide, 2 rows, even columns +DIN 41512 IEC 60603 B +0 +32 +32 +Connector_DIN +DIN41612_B_2x32_Horizontal +DIN 41612 connector, type B, horizontal, 32 pins wide, 2 rows, full configuration +DIN 41512 IEC 60603 B +0 +64 +64 +Connector_DIN +DIN41612_B_2x32_Vertical +DIN 41612 connector, type B, vertical, 32 pins wide, 2 rows, full configuration +DIN 41512 IEC 60603 B +0 +64 +64 +Connector_Dsub +DSUB-9_Female_EdgeMount_P2.77mm +9-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 25mm +0 +9 +9 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +9 +9 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +9 +9 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Female_Vertical_P2.77x2.84mm +9-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 25mm +0 +9 +9 +Connector_Dsub +DSUB-9_Female_Vertical_P2.77x2.84mm_MountingHoles +9-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Male_EdgeMount_P2.77mm +9-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 25mm +0 +9 +9 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +9 +9 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +9 +9 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +9-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +11 +10 +Connector_Dsub +DSUB-9_Male_Vertical_P2.77x2.84mm +9-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 25mm +0 +9 +9 +Connector_Dsub +DSUB-9_Male_Vertical_P2.77x2.84mm_MountingHoles +9-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +9-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 25mm +0 +11 +10 +Connector_Dsub +DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +17 +16 +Connector_Dsub +DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +17 +16 +Connector_Dsub +DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15-HD_Female_Vertical_P2.29x1.98mm_MountingHoles +15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 25mm +0 +17 +16 +Connector_Dsub +DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +17 +16 +Connector_Dsub +DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 25mm mounting-hole-offset 25mm +0 +17 +16 +Connector_Dsub +DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15-HD_Male_Vertical_P2.29x1.98mm_MountingHoles +15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 25mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 25mm +0 +17 +16 +Connector_Dsub +DSUB-15_Female_EdgeMount_P2.77mm +15-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 33.3mm +0 +15 +15 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Female_Vertical_P2.77x2.84mm +15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 33.3mm +0 +15 +15 +Connector_Dsub +DSUB-15_Female_Vertical_P2.77x2.84mm_MountingHoles +15-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Male_EdgeMount_P2.77mm +15-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 33.3mm +0 +15 +15 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +15 +15 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-15_Male_Vertical_P2.77x2.84mm +15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 33.3mm +0 +15 +15 +Connector_Dsub +DSUB-15_Male_Vertical_P2.77x2.84mm_MountingHoles +15-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +15-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 33.3mm +0 +17 +16 +Connector_Dsub +DSUB-25_Female_EdgeMount_P2.77mm +25-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 47.1mm +0 +25 +25 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +25 +25 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +25 +25 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Female_Vertical_P2.77x2.84mm +25-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 47.1mm +0 +25 +25 +Connector_Dsub +DSUB-25_Female_Vertical_P2.77x2.84mm_MountingHoles +25-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Male_EdgeMount_P2.77mm +25-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 47.1mm +0 +25 +25 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +25 +25 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +25 +25 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +25-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-25_Male_Vertical_P2.77x2.84mm +25-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 47.1mm +0 +25 +25 +Connector_Dsub +DSUB-25_Male_Vertical_P2.77x2.84mm_MountingHoles +25-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +25-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 47.1mm +0 +27 +26 +Connector_Dsub +DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +28 +27 +Connector_Dsub +DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +28 +27 +Connector_Dsub +DSUB-26-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm +0 +26 +26 +Connector_Dsub +DSUB-26-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +26-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm +0 +26 +26 +Connector_Dsub +DSUB-26-HD_Female_Vertical_P2.29x1.98mm_MountingHoles +26-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +26-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 33.3mm +0 +28 +27 +Connector_Dsub +DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +28 +27 +Connector_Dsub +DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 33.3mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 33.3mm mounting-hole-offset 33.3mm +0 +28 +27 +Connector_Dsub +DSUB-26-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm +0 +26 +26 +Connector_Dsub +DSUB-26-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm +26-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +26-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm +0 +26 +26 +Connector_Dsub +DSUB-26-HD_Male_Vertical_P2.29x1.98mm_MountingHoles +26-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 33.3mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +26-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 33.3mm +0 +28 +27 +Connector_Dsub +DSUB-37_Female_EdgeMount_P2.77mm +37-pin D-Sub connector, solder-cups edge-mounted, female, x-pin-pitch 2.77mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector edge mount solder cup female x-pin-pitch 2.77mm mounting holes distance 63.5mm +0 +37 +37 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +37 +37 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +37 +37 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Female_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Female_Vertical_P2.77x2.84mm +37-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 63.5mm +0 +37 +37 +Connector_Dsub +DSUB-37_Female_Vertical_P2.77x2.84mm_MountingHoles +37-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector straight vertical THT female pitch 2.77x2.84mm mounting holes distance 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Male_EdgeMount_P2.77mm +37-pin D-Sub connector, solder-cups edge-mounted, male, x-pin-pitch 2.77mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector edge mount solder cup male x-pin-pitch 2.77mm mounting holes distance 63.5mm +0 +37 +37 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.54mm_EdgePinOffset9.40mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.54mm pin-PCB-offset 9.4mm +0 +37 +37 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset4.94mm_Housed_MountingHolesOffset7.48mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 4.9399999999999995mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 7.4799999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 4.9399999999999995mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 7.699999999999999mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 9.12mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 7.699999999999999mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.40mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.4mm +0 +37 +37 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset9.90mm_Housed_MountingHolesOffset11.32mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 9.9mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 11.32mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 9.9mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset8.20mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Male_Horizontal_P2.77x2.84mm_EdgePinOffset14.56mm_Housed_MountingHolesOffset15.98mm +37-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.77x2.84mm, pin-PCB-offset 14.56mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 15.979999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector horizontal angled 90deg THT male pitch 2.77x2.84mm pin-PCB-offset 14.56mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-37_Male_Vertical_P2.77x2.84mm +37-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 63.5mm +0 +37 +37 +Connector_Dsub +DSUB-37_Male_Vertical_P2.77x2.84mm_MountingHoles +37-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.77x2.84mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +37-pin D-Sub connector straight vertical THT male pitch 2.77x2.84mm mounting holes distance 63.5mm +0 +39 +38 +Connector_Dsub +DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +46 +45 +Connector_Dsub +DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +46 +45 +Connector_Dsub +DSUB-44-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 9.4mm +0 +44 +44 +Connector_Dsub +DSUB-44-HD_Female_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +44-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x2.54mm pin-PCB-offset 9.4mm +0 +44 +44 +Connector_Dsub +DSUB-44-HD_Female_Vertical_P2.29x1.98mm_MountingHoles +44-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.29x1.98mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +44-pin D-Sub connector straight vertical THT female pitch 2.29x1.98mm mounting holes distance 47.1mm +0 +46 +45 +Connector_Dsub +DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +46 +45 +Connector_Dsub +DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 47.1mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 47.1mm mounting-hole-offset 47.1mm +0 +46 +45 +Connector_Dsub +DSUB-44-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset9.40mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 9.4mm +0 +44 +44 +Connector_Dsub +DSUB-44-HD_Male_Horizontal_P2.29x2.54mm_EdgePinOffset9.40mm +44-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.29x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +44-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x2.54mm pin-PCB-offset 9.4mm +0 +44 +44 +Connector_Dsub +DSUB-44-HD_Male_Vertical_P2.29x1.98mm_MountingHoles +44-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.29x1.98mm, distance of mounting holes 47.1mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +44-pin D-Sub connector straight vertical THT male pitch 2.29x1.98mm mounting holes distance 47.1mm +0 +46 +45 +Connector_Dsub +DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +64 +63 +Connector_Dsub +DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +64 +63 +Connector_Dsub +DSUB-62-HD_Female_Horizontal_P2.41x1.98mm_EdgePinOffset9.40mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x1.98mm pin-PCB-offset 9.4mm +0 +62 +62 +Connector_Dsub +DSUB-62-HD_Female_Horizontal_P2.41x2.54mm_EdgePinOffset9.40mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.41x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +62-pin D-Sub connector horizontal angled 90deg THT female pitch 2.41x2.54mm pin-PCB-offset 9.4mm +0 +62 +62 +Connector_Dsub +DSUB-62-HD_Female_Vertical_P2.41x1.98mm_MountingHoles +62-pin D-Sub connector, straight/vertical, THT-mount, female, pitch 2.41x1.98mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +62-pin D-Sub connector straight vertical THT female pitch 2.41x1.98mm mounting holes distance 63.5mm +0 +64 +63 +Connector_Dsub +DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +64 +63 +Connector_Dsub +DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 8.35mm, distance of mounting holes 63.5mm, distance of mounting holes to PCB edge 10.889999999999999mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 8.35mm mounting-holes-distance 63.5mm mounting-hole-offset 63.5mm +0 +64 +63 +Connector_Dsub +DSUB-62-HD_Male_Horizontal_P2.41x1.98mm_EdgePinOffset9.40mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x1.98mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x1.98mm pin-PCB-offset 9.4mm +0 +62 +62 +Connector_Dsub +DSUB-62-HD_Male_Horizontal_P2.41x2.54mm_EdgePinOffset9.40mm +62-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, male, pitch 2.41x2.54mm, pin-PCB-offset 9.4mm, see http://docs-europe.electrocomponents.com/webdocs/1585/0900766b81585df2.pdf +62-pin D-Sub connector horizontal angled 90deg THT male pitch 2.41x2.54mm pin-PCB-offset 9.4mm +0 +62 +62 +Connector_Dsub +DSUB-62-HD_Male_Vertical_P2.41x1.98mm_MountingHoles +62-pin D-Sub connector, straight/vertical, THT-mount, male, pitch 2.41x1.98mm, distance of mounting holes 63.5mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf +62-pin D-Sub connector straight vertical THT male pitch 2.41x1.98mm mounting holes distance 63.5mm +0 +64 +63 +Connector_FFC-FPC +Hirose_FH12-6S-0.5SH_1x06-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-6S-0.5SH, 6 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +8 +7 +Connector_FFC-FPC +Hirose_FH12-8S-0.5SH_1x08-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-8S-0.5SH, 8 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +10 +9 +Connector_FFC-FPC +Hirose_FH12-10S-0.5SH_1x10-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-10S-0.5SH, 10 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +12 +11 +Connector_FFC-FPC +Hirose_FH12-11S-0.5SH_1x11-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-11S-0.5SH, 11 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +13 +12 +Connector_FFC-FPC +Hirose_FH12-12S-0.5SH_1x12-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-12S-0.5SH, 12 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +14 +13 +Connector_FFC-FPC +Hirose_FH12-13S-0.5SH_1x13-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-13S-0.5SH, 13 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +15 +14 +Connector_FFC-FPC +Hirose_FH12-14S-0.5SH_1x14-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-14S-0.5SH, 14 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +16 +15 +Connector_FFC-FPC +Hirose_FH12-15S-0.5SH_1x15-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-15S-0.5SH, 15 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +17 +16 +Connector_FFC-FPC +Hirose_FH12-16S-0.5SH_1x16-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-16S-0.5SH, 16 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +18 +17 +Connector_FFC-FPC +Hirose_FH12-17S-0.5SH_1x17-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-17S-0.5SH, 17 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +19 +18 +Connector_FFC-FPC +Hirose_FH12-18S-0.5SH_1x18-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-18S-0.5SH, 18 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +20 +19 +Connector_FFC-FPC +Hirose_FH12-19S-0.5SH_1x19-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-19S-0.5SH, 19 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +21 +20 +Connector_FFC-FPC +Hirose_FH12-20S-0.5SH_1x20-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-20S-0.5SH, 20 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +22 +21 +Connector_FFC-FPC +Hirose_FH12-22S-0.5SH_1x22-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-22S-0.5SH, 22 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +24 +23 +Connector_FFC-FPC +Hirose_FH12-24S-0.5SH_1x24-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-24S-0.5SH, 24 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +26 +25 +Connector_FFC-FPC +Hirose_FH12-25S-0.5SH_1x25-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-25S-0.5SH, 25 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +27 +26 +Connector_FFC-FPC +Hirose_FH12-26S-0.5SH_1x26-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-26S-0.5SH, 26 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +28 +27 +Connector_FFC-FPC +Hirose_FH12-28S-0.5SH_1x28-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-28S-0.5SH, 28 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +30 +29 +Connector_FFC-FPC +Hirose_FH12-30S-0.5SH_1x30-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-30S-0.5SH, 30 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +32 +31 +Connector_FFC-FPC +Hirose_FH12-32S-0.5SH_1x32-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-32S-0.5SH, 32 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +34 +33 +Connector_FFC-FPC +Hirose_FH12-33S-0.5SH_1x33-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-33S-0.5SH, 33 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +35 +34 +Connector_FFC-FPC +Hirose_FH12-34S-0.5SH_1x34-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-34S-0.5SH, 34 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +36 +35 +Connector_FFC-FPC +Hirose_FH12-35S-0.5SH_1x35-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-35S-0.5SH, 35 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +37 +36 +Connector_FFC-FPC +Hirose_FH12-36S-0.5SH_1x36-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-36S-0.5SH, 36 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +38 +37 +Connector_FFC-FPC +Hirose_FH12-40S-0.5SH_1x40-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-40S-0.5SH, 40 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +42 +41 +Connector_FFC-FPC +Hirose_FH12-45S-0.5SH_1x45-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-45S-0.5SH, 45 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +47 +46 +Connector_FFC-FPC +Hirose_FH12-50S-0.5SH_1x50-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-50S-0.5SH, 50 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +52 +51 +Connector_FFC-FPC +Hirose_FH12-53S-0.5SH_1x53-1MP_P0.50mm_Horizontal +Hirose FH12, FFC/FPC connector, FH12-53S-0.5SH, 53 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator +connector Hirose FH12 horizontal +0 +55 +54 +Connector_FFC-FPC +JAE_FF0825SA1_2Rows-25Pins_P0.40mm_Horizontal +Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0825SA1, 25 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +25 +25 +Connector_FFC-FPC +JAE_FF0829SA1_2Rows-29Pins_P0.40mm_Horizontal +Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0829SA1, 29 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +29 +29 +Connector_FFC-FPC +JAE_FF0841SA1_2Rows-41Pins_P0.40mm_Horizontal +Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0841SA1, 41 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +41 +41 +Connector_FFC-FPC +JAE_FF0851SA1_2Rows-51Pins_P0.40mm_Horizontal +Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0851SA1, 51 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +51 +51 +Connector_FFC-FPC +JAE_FF0871SA1_2Rows-71Pins_P0.40mm_Horizontal +Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0871SA1, 71 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +71 +71 +Connector_FFC-FPC +JAE_FF0881SA1_2Rows-81Pins_P0.40mm_Horizontal +Molex JAE 0.2mm pitch, 1mm overall height FFC/FPC connector, FF0881SA1, 81 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ108178.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +81 +81 +Connector_FFC-FPC +Molex_54132-5033_1x50-1MP_P0.5mm_Horizontal +Molex FFC/FPC connector, 50 bottom-side contacts, 0.5mm pitch, 2.0mm height, https://www.molex.com/pdm_docs/sd/541325033_sd.pdf +FFC FPC +0 +54 +51 +Connector_FFC-FPC +Molex_200528-0040_1x04-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0040, 4 Circuits (https://www.molex.com/pdm_docs/sd/2005280040_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +6 +5 +Connector_FFC-FPC +Molex_200528-0050_1x05-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0050, 5 Circuits (https://www.molex.com/pdm_docs/sd/2005280050_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +7 +6 +Connector_FFC-FPC +Molex_200528-0060_1x06-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0060, 6 Circuits (https://www.molex.com/pdm_docs/sd/2005280060_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +8 +7 +Connector_FFC-FPC +Molex_200528-0070_1x07-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0070, 7 Circuits (https://www.molex.com/pdm_docs/sd/2005280070_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +9 +8 +Connector_FFC-FPC +Molex_200528-0080_1x08-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0080, 8 Circuits (https://www.molex.com/pdm_docs/sd/2005280080_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +10 +9 +Connector_FFC-FPC +Molex_200528-0090_1x09-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0090, 9 Circuits (https://www.molex.com/pdm_docs/sd/2005280090_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +11 +10 +Connector_FFC-FPC +Molex_200528-0100_1x10-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0100, 10 Circuits (https://www.molex.com/pdm_docs/sd/2005280100_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +12 +11 +Connector_FFC-FPC +Molex_200528-0110_1x11-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0110, 11 Circuits (https://www.molex.com/pdm_docs/sd/2005280110_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +13 +12 +Connector_FFC-FPC +Molex_200528-0120_1x12-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0120, 12 Circuits (https://www.molex.com/pdm_docs/sd/2005280120_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +14 +13 +Connector_FFC-FPC +Molex_200528-0130_1x13-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0130, 13 Circuits (https://www.molex.com/pdm_docs/sd/2005280130_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +15 +14 +Connector_FFC-FPC +Molex_200528-0140_1x14-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0140, 14 Circuits (https://www.molex.com/pdm_docs/sd/2005280140_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +16 +15 +Connector_FFC-FPC +Molex_200528-0150_1x15-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0150, 15 Circuits (https://www.molex.com/pdm_docs/sd/2005280150_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +17 +16 +Connector_FFC-FPC +Molex_200528-0160_1x16-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0160, 16 Circuits (https://www.molex.com/pdm_docs/sd/2005280160_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +18 +17 +Connector_FFC-FPC +Molex_200528-0170_1x17-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0170, 17 Circuits (https://www.molex.com/pdm_docs/sd/2005280170_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +19 +18 +Connector_FFC-FPC +Molex_200528-0180_1x18-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0180, 18 Circuits (https://www.molex.com/pdm_docs/sd/2005280180_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +20 +19 +Connector_FFC-FPC +Molex_200528-0190_1x19-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0190, 19 Circuits (https://www.molex.com/pdm_docs/sd/2005280190_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +21 +20 +Connector_FFC-FPC +Molex_200528-0200_1x20-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0200, 20 Circuits (https://www.molex.com/pdm_docs/sd/2005280200_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +22 +21 +Connector_FFC-FPC +Molex_200528-0210_1x21-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0210, 21 Circuits (https://www.molex.com/pdm_docs/sd/2005280210_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +23 +22 +Connector_FFC-FPC +Molex_200528-0220_1x22-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0220, 22 Circuits (https://www.molex.com/pdm_docs/sd/2005280220_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +24 +23 +Connector_FFC-FPC +Molex_200528-0230_1x23-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0230, 23 Circuits (https://www.molex.com/pdm_docs/sd/2005280230_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +25 +24 +Connector_FFC-FPC +Molex_200528-0240_1x24-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0240, 24 Circuits (https://www.molex.com/pdm_docs/sd/2005280240_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +26 +25 +Connector_FFC-FPC +Molex_200528-0250_1x25-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0250, 25 Circuits (https://www.molex.com/pdm_docs/sd/2005280250_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +27 +26 +Connector_FFC-FPC +Molex_200528-0260_1x26-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0260, 26 Circuits (https://www.molex.com/pdm_docs/sd/2005280260_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +28 +27 +Connector_FFC-FPC +Molex_200528-0270_1x27-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0270, 27 Circuits (https://www.molex.com/pdm_docs/sd/2005280270_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +29 +28 +Connector_FFC-FPC +Molex_200528-0280_1x28-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0280, 28 Circuits (https://www.molex.com/pdm_docs/sd/2005280280_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +30 +29 +Connector_FFC-FPC +Molex_200528-0290_1x29-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0290, 29 Circuits (https://www.molex.com/pdm_docs/sd/2005280290_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +31 +30 +Connector_FFC-FPC +Molex_200528-0300_1x30-1MP_P1.00mm_Horizontal +Molex Molex 1.00mm Pitch Easy-On BackFlip, Right-Angle, Bottom Contact FFC/FPC, 200528-0300, 30 Circuits (https://www.molex.com/pdm_docs/sd/2005280300_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +32 +31 +Connector_FFC-FPC +Molex_502231-1500_1x15-1SH_P0.5mm_Vertical +Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 15 Circuits (https://www.molex.com/pdm_docs/sd/5022311500_sd.pdf) +molex FFC/FPC connector Pitch 0.5mm vertical +0 +17 +16 +Connector_FFC-FPC +Molex_502231-2400_1x24-1SH_P0.5mm_Vertical +Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 24 Circuits (https://www.molex.com/pdm_docs/sd/5022312400_sd.pdf) +molex FFC/FPC connector Pitch 0.5mm vertical +0 +26 +25 +Connector_FFC-FPC +Molex_502231-3300_1x33-1SH_P0.5mm_Vertical +Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 6.05mm Height, Vertical, Surface Mount, ZIF, 33 Circuits (https://www.molex.com/pdm_docs/sd/5022313300_sd.pdf) +molex FFC/FPC connector Pitch 0.5mm vertical +0 +36 +34 +Connector_FFC-FPC +Molex_502244-1530_1x15-1MP_P0.5mm_Horizontal +Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 15 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf) +molex FFC/FPC connector Pitch 0.5mm right angle +0 +19 +16 +Connector_FFC-FPC +Molex_502244-2430_1x24-1MP_P0.5mm_Horizontal +Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 24 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf) +molex FFC/FPC connector Pitch 0.5mm right angle +0 +28 +25 +Connector_FFC-FPC +Molex_502244-3330_1x33-1MP_P0.5mm_Horizontal +Molex 0.50mm Pitch Easy-On Type FFC/FPC Connector, For LVDS, 2.33mm Height, Right Angle, Surface Mount, ZIF, Bottom Contact Style, 33 Circuits (http://www.molex.com/pdm_docs/sd/5022441530_sd.pdf) +molex FFC/FPC connector Pitch 0.5mm right angle +0 +39 +34 +Connector_FFC-FPC +Molex_502250-1791_2Rows-17Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-1791, 17 Circuits (http://www.molex.com/pdm_docs/sd/5022501791_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +19 +18 +Connector_FFC-FPC +Molex_502250-2191_2Rows-21Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2191, 21 Circuits (http://www.molex.com/pdm_docs/sd/5022502191_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +23 +22 +Connector_FFC-FPC +Molex_502250-2391_2Rows-23Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2391, 23 Circuits (http://www.molex.com/pdm_docs/sd/5022502391_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +25 +24 +Connector_FFC-FPC +Molex_502250-2791_2Rows-27Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-2791, 27 Circuits (http://www.molex.com/pdm_docs/sd/5022502791_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +29 +28 +Connector_FFC-FPC +Molex_502250-3391_2Rows-33Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3391, 33 Circuits (http://www.molex.com/pdm_docs/sd/5022503391_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +35 +34 +Connector_FFC-FPC +Molex_502250-3591_2Rows-35Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3591, 35 Circuits (http://www.molex.com/pdm_docs/sd/5022503591_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +37 +36 +Connector_FFC-FPC +Molex_502250-3991_2Rows-39Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-3991, 39 Circuits (http://www.molex.com/pdm_docs/sd/5022503991_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +41 +40 +Connector_FFC-FPC +Molex_502250-4191_2Rows-41Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-4191, 41 Circuits (http://www.molex.com/pdm_docs/sd/5022504191_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +43 +42 +Connector_FFC-FPC +Molex_502250-5191_2Rows-51Pins-1MP_P0.60mm_Horizontal +Molex Molex 0.30mm Pitch Easy-On BackFlip Type FFC/FPC, 502250-5191, 51 Circuits (http://www.molex.com/pdm_docs/sd/5022505191_sd.pdf), generated with kicad-footprint-generator +connector Molex top entry +0 +53 +52 +Connector_FFC-FPC +TE_0-1734839-5_1x05-1MP_P0.5mm_Horizontal +TE FPC connector, 05 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +7 +6 +Connector_FFC-FPC +TE_0-1734839-6_1x06-1MP_P0.5mm_Horizontal +TE FPC connector, 06 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +8 +7 +Connector_FFC-FPC +TE_0-1734839-7_1x07-1MP_P0.5mm_Horizontal +TE FPC connector, 07 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +9 +8 +Connector_FFC-FPC +TE_0-1734839-8_1x08-1MP_P0.5mm_Horizontal +TE FPC connector, 08 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +10 +9 +Connector_FFC-FPC +TE_0-1734839-9_1x09-1MP_P0.5mm_Horizontal +TE FPC connector, 09 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +11 +10 +Connector_FFC-FPC +TE_1-84952-0_1x10-1MP_P1.0mm_Horizontal +TE FPC connector, 10 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +12 +11 +Connector_FFC-FPC +TE_1-84952-1_1x11-1MP_P1.0mm_Horizontal +TE FPC connector, 11 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +13 +12 +Connector_FFC-FPC +TE_1-84952-2_1x12-1MP_P1.0mm_Horizontal +TE FPC connector, 12 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +14 +13 +Connector_FFC-FPC +TE_1-84952-3_1x13-1MP_P1.0mm_Horizontal +TE FPC connector, 13 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +15 +14 +Connector_FFC-FPC +TE_1-84952-4_1x14-1MP_P1.0mm_Horizontal +TE FPC connector, 14 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +16 +15 +Connector_FFC-FPC +TE_1-84952-5_1x15-1MP_P1.0mm_Horizontal +TE FPC connector, 15 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +17 +16 +Connector_FFC-FPC +TE_1-84952-6_1x16-1MP_P1.0mm_Horizontal +TE FPC connector, 16 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +18 +17 +Connector_FFC-FPC +TE_1-84952-7_1x17-1MP_P1.0mm_Horizontal +TE FPC connector, 17 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +19 +18 +Connector_FFC-FPC +TE_1-84952-8_1x18-1MP_P1.0mm_Horizontal +TE FPC connector, 18 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +20 +19 +Connector_FFC-FPC +TE_1-84952-9_1x19-1MP_P1.0mm_Horizontal +TE FPC connector, 19 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +21 +20 +Connector_FFC-FPC +TE_1-84953-0_1x10-1MP_P1.0mm_Horizontal +TE FPC connector, 10 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +12 +11 +Connector_FFC-FPC +TE_1-84953-1_1x11-1MP_P1.0mm_Horizontal +TE FPC connector, 11 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +13 +12 +Connector_FFC-FPC +TE_1-84953-2_1x12-1MP_P1.0mm_Horizontal +TE FPC connector, 12 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +14 +13 +Connector_FFC-FPC +TE_1-84953-3_1x13-1MP_P1.0mm_Horizontal +TE FPC connector, 13 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +15 +14 +Connector_FFC-FPC +TE_1-84953-4_1x14-1MP_P1.0mm_Horizontal +TE FPC connector, 14 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +16 +15 +Connector_FFC-FPC +TE_1-84953-5_1x15-1MP_P1.0mm_Horizontal +TE FPC connector, 15 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +17 +16 +Connector_FFC-FPC +TE_1-84953-6_1x16-1MP_P1.0mm_Horizontal +TE FPC connector, 16 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +18 +17 +Connector_FFC-FPC +TE_1-84953-7_1x17-1MP_P1.0mm_Horizontal +TE FPC connector, 17 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +19 +18 +Connector_FFC-FPC +TE_1-84953-8_1x18-1MP_P1.0mm_Horizontal +TE FPC connector, 18 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +20 +19 +Connector_FFC-FPC +TE_1-84953-9_1x19-1MP_P1.0mm_Horizontal +TE FPC connector, 19 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +21 +20 +Connector_FFC-FPC +TE_1-1734839-0_1x10-1MP_P0.5mm_Horizontal +TE FPC connector, 10 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +12 +11 +Connector_FFC-FPC +TE_1-1734839-1_1x11-1MP_P0.5mm_Horizontal +TE FPC connector, 11 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +13 +12 +Connector_FFC-FPC +TE_1-1734839-2_1x12-1MP_P0.5mm_Horizontal +TE FPC connector, 12 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +14 +13 +Connector_FFC-FPC +TE_1-1734839-3_1x13-1MP_P0.5mm_Horizontal +TE FPC connector, 13 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +15 +14 +Connector_FFC-FPC +TE_1-1734839-4_1x14-1MP_P0.5mm_Horizontal +TE FPC connector, 14 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +16 +15 +Connector_FFC-FPC +TE_1-1734839-5_1x15-1MP_P0.5mm_Horizontal +TE FPC connector, 15 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +17 +16 +Connector_FFC-FPC +TE_1-1734839-6_1x16-1MP_P0.5mm_Horizontal +TE FPC connector, 16 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +18 +17 +Connector_FFC-FPC +TE_1-1734839-7_1x17-1MP_P0.5mm_Horizontal +TE FPC connector, 17 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +19 +18 +Connector_FFC-FPC +TE_1-1734839-8_1x18-1MP_P0.5mm_Horizontal +TE FPC connector, 18 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +20 +19 +Connector_FFC-FPC +TE_1-1734839-9_1x19-1MP_P0.5mm_Horizontal +TE FPC connector, 19 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +21 +20 +Connector_FFC-FPC +TE_2-84952-0_1x20-1MP_P1.0mm_Horizontal +TE FPC connector, 20 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +22 +21 +Connector_FFC-FPC +TE_2-84952-1_1x21-1MP_P1.0mm_Horizontal +TE FPC connector, 21 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +23 +22 +Connector_FFC-FPC +TE_2-84952-2_1x22-1MP_P1.0mm_Horizontal +TE FPC connector, 22 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +24 +23 +Connector_FFC-FPC +TE_2-84952-3_1x23-1MP_P1.0mm_Horizontal +TE FPC connector, 23 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +25 +24 +Connector_FFC-FPC +TE_2-84952-4_1x24-1MP_P1.0mm_Horizontal +TE FPC connector, 24 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +26 +25 +Connector_FFC-FPC +TE_2-84952-5_1x25-1MP_P1.0mm_Horizontal +TE FPC connector, 25 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +27 +26 +Connector_FFC-FPC +TE_2-84952-6_1x26-1MP_P1.0mm_Horizontal +TE FPC connector, 26 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +28 +27 +Connector_FFC-FPC +TE_2-84952-7_1x27-1MP_P1.0mm_Horizontal +TE FPC connector, 27 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +29 +28 +Connector_FFC-FPC +TE_2-84952-8_1x28-1MP_P1.0mm_Horizontal +TE FPC connector, 28 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +30 +29 +Connector_FFC-FPC +TE_2-84952-9_1x29-1MP_P1.0mm_Horizontal +TE FPC connector, 29 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +31 +30 +Connector_FFC-FPC +TE_2-84953-0_1x20-1MP_P1.0mm_Horizontal +TE FPC connector, 20 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +22 +21 +Connector_FFC-FPC +TE_2-84953-1_1x21-1MP_P1.0mm_Horizontal +TE FPC connector, 21 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +23 +22 +Connector_FFC-FPC +TE_2-84953-2_1x22-1MP_P1.0mm_Horizontal +TE FPC connector, 22 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +24 +23 +Connector_FFC-FPC +TE_2-84953-3_1x23-1MP_P1.0mm_Horizontal +TE FPC connector, 23 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +25 +24 +Connector_FFC-FPC +TE_2-84953-4_1x24-1MP_P1.0mm_Horizontal +TE FPC connector, 24 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +26 +25 +Connector_FFC-FPC +TE_2-84953-5_1x25-1MP_P1.0mm_Horizontal +TE FPC connector, 25 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +27 +26 +Connector_FFC-FPC +TE_2-84953-6_1x26-1MP_P1.0mm_Horizontal +TE FPC connector, 26 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +28 +27 +Connector_FFC-FPC +TE_2-84953-7_1x27-1MP_P1.0mm_Horizontal +TE FPC connector, 27 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +29 +28 +Connector_FFC-FPC +TE_2-84953-8_1x28-1MP_P1.0mm_Horizontal +TE FPC connector, 28 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +30 +29 +Connector_FFC-FPC +TE_2-84953-9_1x29-1MP_P1.0mm_Horizontal +TE FPC connector, 29 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +31 +30 +Connector_FFC-FPC +TE_2-1734839-0_1x20-1MP_P0.5mm_Horizontal +TE FPC connector, 20 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +22 +21 +Connector_FFC-FPC +TE_2-1734839-1_1x21-1MP_P0.5mm_Horizontal +TE FPC connector, 21 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +23 +22 +Connector_FFC-FPC +TE_2-1734839-2_1x22-1MP_P0.5mm_Horizontal +TE FPC connector, 22 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +24 +23 +Connector_FFC-FPC +TE_2-1734839-3_1x23-1MP_P0.5mm_Horizontal +TE FPC connector, 23 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +25 +24 +Connector_FFC-FPC +TE_2-1734839-4_1x24-1MP_P0.5mm_Horizontal +TE FPC connector, 24 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +26 +25 +Connector_FFC-FPC +TE_2-1734839-5_1x25-1MP_P0.5mm_Horizontal +TE FPC connector, 25 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +27 +26 +Connector_FFC-FPC +TE_2-1734839-6_1x26-1MP_P0.5mm_Horizontal +TE FPC connector, 26 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +28 +27 +Connector_FFC-FPC +TE_2-1734839-7_1x27-1MP_P0.5mm_Horizontal +TE FPC connector, 27 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +29 +28 +Connector_FFC-FPC +TE_2-1734839-8_1x28-1MP_P0.5mm_Horizontal +TE FPC connector, 28 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +30 +29 +Connector_FFC-FPC +TE_2-1734839-9_1x29-1MP_P0.5mm_Horizontal +TE FPC connector, 29 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +31 +30 +Connector_FFC-FPC +TE_3-84952-0_1x30-1MP_P1.0mm_Horizontal +TE FPC connector, 30 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +32 +31 +Connector_FFC-FPC +TE_3-84953-0_1x30-1MP_P1.0mm_Horizontal +TE FPC connector, 30 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +32 +31 +Connector_FFC-FPC +TE_3-1734839-0_1x30-1MP_P0.5mm_Horizontal +TE FPC connector, 30 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +32 +31 +Connector_FFC-FPC +TE_3-1734839-1_1x31-1MP_P0.5mm_Horizontal +TE FPC connector, 31 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +33 +32 +Connector_FFC-FPC +TE_3-1734839-2_1x32-1MP_P0.5mm_Horizontal +TE FPC connector, 32 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +34 +33 +Connector_FFC-FPC +TE_3-1734839-3_1x33-1MP_P0.5mm_Horizontal +TE FPC connector, 33 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +35 +34 +Connector_FFC-FPC +TE_3-1734839-4_1x34-1MP_P0.5mm_Horizontal +TE FPC connector, 34 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +36 +35 +Connector_FFC-FPC +TE_3-1734839-5_1x35-1MP_P0.5mm_Horizontal +TE FPC connector, 35 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +37 +36 +Connector_FFC-FPC +TE_3-1734839-6_1x36-1MP_P0.5mm_Horizontal +TE FPC connector, 36 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +38 +37 +Connector_FFC-FPC +TE_3-1734839-7_1x37-1MP_P0.5mm_Horizontal +TE FPC connector, 37 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +39 +38 +Connector_FFC-FPC +TE_3-1734839-8_1x38-1MP_P0.5mm_Horizontal +TE FPC connector, 38 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +40 +39 +Connector_FFC-FPC +TE_3-1734839-9_1x39-1MP_P0.5mm_Horizontal +TE FPC connector, 39 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +41 +40 +Connector_FFC-FPC +TE_4-1734839-0_1x40-1MP_P0.5mm_Horizontal +TE FPC connector, 40 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +42 +41 +Connector_FFC-FPC +TE_4-1734839-1_1x41-1MP_P0.5mm_Horizontal +TE FPC connector, 41 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +43 +42 +Connector_FFC-FPC +TE_4-1734839-2_1x42-1MP_P0.5mm_Horizontal +TE FPC connector, 42 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +44 +43 +Connector_FFC-FPC +TE_4-1734839-3_1x43-1MP_P0.5mm_Horizontal +TE FPC connector, 43 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +45 +44 +Connector_FFC-FPC +TE_4-1734839-4_1x44-1MP_P0.5mm_Horizontal +TE FPC connector, 44 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +46 +45 +Connector_FFC-FPC +TE_4-1734839-5_1x45-1MP_P0.5mm_Horizontal +TE FPC connector, 45 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +47 +46 +Connector_FFC-FPC +TE_4-1734839-6_1x46-1MP_P0.5mm_Horizontal +TE FPC connector, 46 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +48 +47 +Connector_FFC-FPC +TE_4-1734839-7_1x47-1MP_P0.5mm_Horizontal +TE FPC connector, 47 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +49 +48 +Connector_FFC-FPC +TE_4-1734839-8_1x48-1MP_P0.5mm_Horizontal +TE FPC connector, 48 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +50 +49 +Connector_FFC-FPC +TE_4-1734839-9_1x49-1MP_P0.5mm_Horizontal +TE FPC connector, 49 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +51 +50 +Connector_FFC-FPC +TE_5-1734839-0_1x50-1MP_P0.5mm_Horizontal +TE FPC connector, 50 top-side contacts, 0.5mm pitch, SMT, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1734839%7FC%7Fpdf%7FEnglish%7FENG_CD_1734839_C_C_1734839.pdf%7F4-1734839-0 +te fpc 1734839 +0 +52 +51 +Connector_FFC-FPC +TE_84952-4_1x04-1MP_P1.0mm_Horizontal +TE FPC connector, 04 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +6 +5 +Connector_FFC-FPC +TE_84952-5_1x05-1MP_P1.0mm_Horizontal +TE FPC connector, 05 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +7 +6 +Connector_FFC-FPC +TE_84952-6_1x06-1MP_P1.0mm_Horizontal +TE FPC connector, 06 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +8 +7 +Connector_FFC-FPC +TE_84952-7_1x07-1MP_P1.0mm_Horizontal +TE FPC connector, 07 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +9 +8 +Connector_FFC-FPC +TE_84952-8_1x08-1MP_P1.0mm_Horizontal +TE FPC connector, 08 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +10 +9 +Connector_FFC-FPC +TE_84952-9_1x09-1MP_P1.0mm_Horizontal +TE FPC connector, 09 bottom-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84952&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84952-4 +te fpc 84952 +0 +11 +10 +Connector_FFC-FPC +TE_84953-4_1x04-1MP_P1.0mm_Horizontal +TE FPC connector, 04 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +6 +5 +Connector_FFC-FPC +TE_84953-5_1x05-1MP_P1.0mm_Horizontal +TE FPC connector, 05 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +7 +6 +Connector_FFC-FPC +TE_84953-6_1x06-1MP_P1.0mm_Horizontal +TE FPC connector, 06 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +8 +7 +Connector_FFC-FPC +TE_84953-7_1x07-1MP_P1.0mm_Horizontal +TE FPC connector, 07 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +9 +8 +Connector_FFC-FPC +TE_84953-8_1x08-1MP_P1.0mm_Horizontal +TE FPC connector, 08 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +10 +9 +Connector_FFC-FPC +TE_84953-9_1x09-1MP_P1.0mm_Horizontal +TE FPC connector, 09 top-side contacts, 1.0mm pitch, 1.0mm height, SMT, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=84953&DocType=Customer+Drawing&DocLang=English&DocFormat=pdf&PartCntxt=84953-4 +te fpc 84953 +0 +11 +10 +Connector_FFC-FPC +Wuerth_68611214422_1x12-1MP_P1.0mm_Horizontal +http://katalog.we-online.de/em/datasheet/68611214422.pdf +Wuerth FPC 68611214422 connector 12 bottom-side contacts 1.0mm pitch 1.0mm height SMT +0 +14 +13 +Connector_HDMI +HDMI_A_Contact_Technology_HDMI-19APL2_Horizontal +HDMI Contact Technology Type A http://www.contactswitch.com/en/download.aspx?id=1449 +HDMI Contact Technology Type A +0 +23 +20 +Connector_HDMI +HDMI_A_Kycon_KDMIX-SL1-NS-WS-B15_VerticalRightAngle +HDMI, Type A, Kycon KDMIX-SL1-NS-WS-B15, Vertical Right Angle, http://www.kycon.com/Pub_Eng_Draw/KDMIX-SL1-NS-WS-B15.pdf +hdmi type a +0 +23 +20 +Connector_HDMI +HDMI_Micro-D_Molex_46765-0x01 +HDMI, Micro, Type D, SMD, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf) +hdmi micro type d right angle smd +0 +23 +20 +Connector_HDMI +HDMI_Micro-D_Molex_46765-1x01 +HDMI, Micro, Type D, THT, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf) +hdmi micro type d right angle tht +0 +23 +20 +Connector_HDMI +HDMI_Micro-D_Molex_46765-2x0x +HDMI, Micro, Type D, THT/SMD hybrid, 0.4mm pitch, 19 ckt, right angle (http://www.molex.com/pdm_docs/sd/467651301_sd.pdf) +hdmi micro type d right angle tht smd hybrid +0 +23 +20 +Connector_Harwin +Harwin_Gecko-G125-FVX0605L0X_2x03_P1.25mm_Vertical +Harwin Gecko Connector, 6 pins, dual row female, vertical entry, PN:G125-FVX0605L0X +connector harwin gecko +0 +6 +6 +Connector_Harwin +Harwin_Gecko-G125-FVX1005L0X_2x05_P1.25mm_Vertical +Harwin Gecko Connector, 10 pins, dual row female, vertical entry, PN:G125-FVX1005L0X +connector harwin gecko +0 +10 +10 +Connector_Harwin +Harwin_Gecko-G125-FVX1205L0X_2x06_P1.25mm_Vertical +Harwin Gecko Connector, 12 pins, dual row female, vertical entry, PN:G125-FVX1205L0X +connector harwin gecko +0 +12 +12 +Connector_Harwin +Harwin_Gecko-G125-FVX1605L0X_2x08_P1.25mm_Vertical +Harwin Gecko Connector, 16 pins, dual row female, vertical entry, PN:G125-FVX1605L0X +connector harwin gecko +0 +16 +16 +Connector_Harwin +Harwin_Gecko-G125-FVX2005L0X_2x10_P1.25mm_Vertical +Harwin Gecko Connector, 20 pins, dual row female, vertical entry, PN:G125-FVX2005L0X +connector harwin gecko +0 +20 +20 +Connector_Harwin +Harwin_Gecko-G125-FVX2605L0X_2x13_P1.25mm_Vertical +Harwin Gecko Connector, 26 pins, dual row female, vertical entry, PN:G125-FVX2605L0X +connector harwin gecko +0 +26 +26 +Connector_Harwin +Harwin_Gecko-G125-FVX3405L0X_2x17_P1.25mm_Vertical +Harwin Gecko Connector, 34 pins, dual row female, vertical entry, PN:G125-FVX3405L0X +connector harwin gecko +0 +34 +34 +Connector_Harwin +Harwin_Gecko-G125-FVX5005L0X_2x25_P1.25mm_Vertical +Harwin Gecko Connector, 50 pins, dual row female, vertical entry, PN:G125-FVX5005L0X +connector harwin gecko +0 +50 +50 +Connector_Harwin +Harwin_Gecko-G125-MVX0605L0X_2x03_P1.25mm_Vertical +Harwin Gecko Connector, 6 pins, dual row male, vertical entry, no latches, PN:G125-MVX0605L0X +connector harwin gecko +0 +6 +6 +Connector_Harwin +Harwin_Gecko-G125-MVX0605L1X_2x03_P1.25mm_Vertical +Harwin Gecko Connector, 6 pins, dual row male, vertical entry, with latches, PN:G125-MVX0605L1X +connector harwin gecko +0 +6 +6 +Connector_Harwin +Harwin_Gecko-G125-MVX1005L0X_2x05_P1.25mm_Vertical +Harwin Gecko Connector, 10 pins, dual row male, vertical entry, no latches, PN:G125-MVX1005L0X +connector harwin gecko +0 +10 +10 +Connector_Harwin +Harwin_Gecko-G125-MVX1005L1X_2x05_P1.25mm_Vertical +Harwin Gecko Connector, 10 pins, dual row male, vertical entry, with latches, PN:G125-MVX1005L1X +connector harwin gecko +0 +10 +10 +Connector_Harwin +Harwin_Gecko-G125-MVX1205L0X_2x06_P1.25mm_Vertical +Harwin Gecko Connector, 12 pins, dual row male, vertical entry, no latches, PN:G125-MVX1205L0X +connector harwin gecko +0 +12 +12 +Connector_Harwin +Harwin_Gecko-G125-MVX1205L1X_2x06_P1.25mm_Vertical +Harwin Gecko Connector, 12 pins, dual row male, vertical entry, with latches, PN:G125-MVX1205L1X +connector harwin gecko +0 +12 +12 +Connector_Harwin +Harwin_Gecko-G125-MVX1605L0X_2x08_P1.25mm_Vertical +Harwin Gecko Connector, 16 pins, dual row male, vertical entry, no latches, PN:G125-MVX1605L0X +connector harwin gecko +0 +16 +16 +Connector_Harwin +Harwin_Gecko-G125-MVX1605L1X_2x08_P1.25mm_Vertical +Harwin Gecko Connector, 16 pins, dual row male, vertical entry, with latches, PN:G125-MVX1605L1X +connector harwin gecko +0 +16 +16 +Connector_Harwin +Harwin_Gecko-G125-MVX2005L0X_2x10_P1.25mm_Vertical +Harwin Gecko Connector, 20 pins, dual row male, vertical entry, no latches, PN:G125-MVX2005L0X +connector harwin gecko +0 +20 +20 +Connector_Harwin +Harwin_Gecko-G125-MVX2005L1X_2x10_P1.25mm_Vertical +Harwin Gecko Connector, 20 pins, dual row male, vertical entry, with latches, PN:G125-MVX2005L1X +connector harwin gecko +0 +20 +20 +Connector_Harwin +Harwin_Gecko-G125-MVX2605L0X_2x13_P1.25mm_Vertical +Harwin Gecko Connector, 26 pins, dual row male, vertical entry, no latches, PN:G125-MVX2605L0X +connector harwin gecko +0 +26 +26 +Connector_Harwin +Harwin_Gecko-G125-MVX2605L1X_2x13_P1.25mm_Vertical +Harwin Gecko Connector, 26 pins, dual row male, vertical entry, with latches, PN:G125-MVX2605L1X +connector harwin gecko +0 +26 +26 +Connector_Harwin +Harwin_Gecko-G125-MVX3405L0X_2x17_P1.25mm_Vertical +Harwin Gecko Connector, 34 pins, dual row male, vertical entry, no latches, PN:G125-MVX3405L0X +connector harwin gecko +0 +34 +34 +Connector_Harwin +Harwin_Gecko-G125-MVX3405L1X_2x17_P1.25mm_Vertical +Harwin Gecko Connector, 34 pins, dual row male, vertical entry, with latches, PN:G125-MVX3405L1X +connector harwin gecko +0 +34 +34 +Connector_Harwin +Harwin_Gecko-G125-MVX5005L0X_2x25_P1.25mm_Vertical +Harwin Gecko Connector, 50 pins, dual row male, vertical entry, no latches, PN:G125-MVX5005L0X +connector harwin gecko +0 +50 +50 +Connector_Harwin +Harwin_Gecko-G125-MVX5005L1X_2x25_P1.25mm_Vertical +Harwin Gecko Connector, 50 pins, dual row male, vertical entry, with latches, PN:G125-MVX5005L1X +connector harwin gecko +0 +50 +50 +Connector_Harwin +Harwin_LTek-Male_02_P2.00mm_Vertical +Harwin LTek Connector, 2 pins, single row male, vertical entry +connector harwin ltek M80 +0 +2 +2 +Connector_Harwin +Harwin_LTek-Male_02_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 2 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +6 +2 +Connector_Harwin +Harwin_LTek-Male_2x02_P2.00mm_Vertical +Harwin LTek Connector, 4 pins, single row male, vertical entry +connector harwin ltek M80 +0 +4 +4 +Connector_Harwin +Harwin_LTek-Male_2x02_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 4 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +8 +4 +Connector_Harwin +Harwin_LTek-Male_2x03_P2.00mm_Vertical +Harwin LTek Connector, 6 pins, single row male, vertical entry +connector harwin ltek M80 +0 +6 +6 +Connector_Harwin +Harwin_LTek-Male_2x03_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 6 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +10 +6 +Connector_Harwin +Harwin_LTek-Male_2x04_P2.00mm_Vertical +Harwin LTek Connector, 8 pins, single row male, vertical entry +connector harwin ltek M80 +0 +8 +8 +Connector_Harwin +Harwin_LTek-Male_2x04_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 8 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +12 +8 +Connector_Harwin +Harwin_LTek-Male_2x05_P2.00mm_Vertical +Harwin LTek Connector, 10 pins, single row male, vertical entry +connector harwin ltek M80 +0 +10 +10 +Connector_Harwin +Harwin_LTek-Male_2x05_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 10 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +14 +10 +Connector_Harwin +Harwin_LTek-Male_2x06_P2.00mm_Vertical +Harwin LTek Connector, 12 pins, single row male, vertical entry +connector harwin ltek M80 +0 +12 +12 +Connector_Harwin +Harwin_LTek-Male_2x06_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 12 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +16 +12 +Connector_Harwin +Harwin_LTek-Male_2x07_P2.00mm_Vertical +Harwin LTek Connector, 14 pins, single row male, vertical entry +connector harwin ltek M80 +0 +14 +14 +Connector_Harwin +Harwin_LTek-Male_2x07_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 14 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +18 +14 +Connector_Harwin +Harwin_LTek-Male_2x08_P2.00mm_Vertical +Harwin LTek Connector, 16 pins, single row male, vertical entry +connector harwin ltek M80 +0 +16 +16 +Connector_Harwin +Harwin_LTek-Male_2x08_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 16 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +20 +16 +Connector_Harwin +Harwin_LTek-Male_2x09_P2.00mm_Vertical +Harwin LTek Connector, 18 pins, single row male, vertical entry +connector harwin ltek M80 +0 +18 +18 +Connector_Harwin +Harwin_LTek-Male_2x09_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 18 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +22 +18 +Connector_Harwin +Harwin_LTek-Male_2x10_P2.00mm_Vertical +Harwin LTek Connector, 20 pins, single row male, vertical entry +connector harwin ltek M80 +0 +20 +20 +Connector_Harwin +Harwin_LTek-Male_2x10_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 20 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +24 +20 +Connector_Harwin +Harwin_LTek-Male_2x13_P2.00mm_Vertical +Harwin LTek Connector, 26 pins, single row male, vertical entry +connector harwin ltek M80 +0 +26 +26 +Connector_Harwin +Harwin_LTek-Male_2x13_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 26 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +30 +26 +Connector_Harwin +Harwin_LTek-Male_2x17_P2.00mm_Vertical +Harwin LTek Connector, 34 pins, single row male, vertical entry +connector harwin ltek M80 +0 +34 +34 +Connector_Harwin +Harwin_LTek-Male_2x17_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 34 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +38 +34 +Connector_Harwin +Harwin_LTek-Male_2x22_P2.00mm_Vertical +Harwin LTek Connector, 44 pins, single row male, vertical entry +connector harwin ltek M80 +0 +44 +44 +Connector_Harwin +Harwin_LTek-Male_2x22_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 44 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +48 +44 +Connector_Harwin +Harwin_LTek-Male_03_P2.00mm_Vertical +Harwin LTek Connector, 3 pins, single row male, vertical entry +connector harwin ltek M80 +0 +3 +3 +Connector_Harwin +Harwin_LTek-Male_03_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 3 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +7 +3 +Connector_Harwin +Harwin_LTek-Male_04_P2.00mm_Vertical +Harwin LTek Connector, 4 pins, single row male, vertical entry +connector harwin ltek M80 +0 +4 +4 +Connector_Harwin +Harwin_LTek-Male_04_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 4 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +8 +4 +Connector_Harwin +Harwin_LTek-Male_05_P2.00mm_Vertical +Harwin LTek Connector, 5 pins, single row male, vertical entry +connector harwin ltek M80 +0 +5 +5 +Connector_Harwin +Harwin_LTek-Male_05_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 5 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +9 +5 +Connector_Harwin +Harwin_LTek-Male_06_P2.00mm_Vertical +Harwin LTek Connector, 6 pins, single row male, vertical entry +connector harwin ltek M80 +0 +6 +6 +Connector_Harwin +Harwin_LTek-Male_06_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 6 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +10 +6 +Connector_Harwin +Harwin_LTek-Male_07_P2.00mm_Vertical +Harwin LTek Connector, 7 pins, single row male, vertical entry +connector harwin ltek M80 +0 +7 +7 +Connector_Harwin +Harwin_LTek-Male_07_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 7 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +11 +7 +Connector_Harwin +Harwin_LTek-Male_17_P2.00mm_Vertical +Harwin LTek Connector, 17 pins, single row male, vertical entry +connector harwin ltek M80 +0 +17 +17 +Connector_Harwin +Harwin_LTek-Male_17_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 17 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +21 +17 +Connector_Harwin +Harwin_LTek-Male_22_P2.00mm_Vertical +Harwin LTek Connector, 22 pins, single row male, vertical entry +connector harwin ltek M80 +0 +22 +22 +Connector_Harwin +Harwin_LTek-Male_22_P2.00mm_Vertical_StrainRelief +Harwin LTek Connector, 22 pins, single row male, vertical entry, strain relief clip +connector harwin ltek M80 +0 +26 +22 +Connector_Harwin +Harwin_M20-89003xx_1x03_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89003xx, 3 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +4 +3 +Connector_Harwin +Harwin_M20-89004xx_1x04_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89004xx, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +5 +4 +Connector_Harwin +Harwin_M20-89005xx_1x05_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89005xx, 5 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +6 +5 +Connector_Harwin +Harwin_M20-89006xx_1x06_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89006xx, 6 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +7 +6 +Connector_Harwin +Harwin_M20-89007xx_1x07_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89007xx, 7 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +8 +7 +Connector_Harwin +Harwin_M20-89008xx_1x08_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89008xx, 8 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +9 +8 +Connector_Harwin +Harwin_M20-89009xx_1x09_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89009xx, 9 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +10 +9 +Connector_Harwin +Harwin_M20-89010xx_1x10_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89010xx, 10 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +11 +10 +Connector_Harwin +Harwin_M20-89011xx_1x11_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89011xx, 11 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +12 +11 +Connector_Harwin +Harwin_M20-89012xx_1x12_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89012xx, 12 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +13 +12 +Connector_Harwin +Harwin_M20-89013xx_1x13_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89013xx, 13 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +14 +13 +Connector_Harwin +Harwin_M20-89014xx_1x14_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89014xx, 14 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +15 +14 +Connector_Harwin +Harwin_M20-89015xx_1x15_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89015xx, 15 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +16 +15 +Connector_Harwin +Harwin_M20-89016xx_1x16_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89016xx, 16 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +17 +16 +Connector_Harwin +Harwin_M20-89017xx_1x17_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89017xx, 17 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +18 +17 +Connector_Harwin +Harwin_M20-89018xx_1x18_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89018xx, 18 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +19 +18 +Connector_Harwin +Harwin_M20-89019xx_1x19_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89019xx, 19 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +20 +19 +Connector_Harwin +Harwin_M20-89020xx_1x20_P2.54mm_Horizontal +Harwin Male Horizontal Surface Mount Single Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-89020xx, 20 Pins per row (https://cdn.harwin.com/pdfs/M20-890.pdf), generated with kicad-footprint-generator +connector Harwin M20-890 horizontal +0 +21 +20 +Connector_Harwin +Harwin_M20-7810245_2x02_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810245, 2 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +4 +4 +Connector_Harwin +Harwin_M20-7810345_2x03_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810345, 3 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +6 +6 +Connector_Harwin +Harwin_M20-7810445_2x04_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810445, 4 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +8 +8 +Connector_Harwin +Harwin_M20-7810545_2x05_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810545, 5 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +10 +10 +Connector_Harwin +Harwin_M20-7810645_2x06_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810645, 6 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +12 +12 +Connector_Harwin +Harwin_M20-7810745_2x07_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810745, 7 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +14 +14 +Connector_Harwin +Harwin_M20-7810845_2x08_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810845, 8 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +16 +16 +Connector_Harwin +Harwin_M20-7810945_2x09_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7810945, 9 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +18 +18 +Connector_Harwin +Harwin_M20-7811045_2x10_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811045, 10 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +20 +20 +Connector_Harwin +Harwin_M20-7811245_2x12_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811245, 12 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +24 +24 +Connector_Harwin +Harwin_M20-7811545_2x15_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7811545, 15 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +30 +30 +Connector_Harwin +Harwin_M20-7812045_2x20_P2.54mm_Vertical +Harwin Female Vertical Surface Mount Double Row 2.54mm (0.1 inch) Pitch PCB Connector, M20-7812045, 20 Pins per row (https://cdn.harwin.com/pdfs/M20-781.pdf), generated with kicad-footprint-generator +connector Harwin M20 side entry +0 +40 +40 +Connector_Hirose +Hirose_BM24_BM24-40DP-2-0.35V_2x20_P0.35mm_PowerPin2_Vertical +Hirose BM24 series connector, BM24-40DP/2-0.35V (https://www.hirose.com/product/en/download_file/key_name/BM24/category/Catalog/doc_file_id/47680/?file_category_id=4&item_id=50&is_series=1) +connector Hirose BM24 40pin header +0 +44 +42 +Connector_Hirose +Hirose_BM24_BM24-40DS-2-0.35V_2x20_P0.35mm_PowerPin2_Vertical +Hirose BM24 series connector, BM24-40DS/2-0.35V (https://www.hirose.com/product/en/download_file/key_name/BM24/category/Catalog/doc_file_id/47680/?file_category_id=4&item_id=50&is_series=1) +connector Hirose 40pin receptacle vertical +0 +42 +42 +Connector_Hirose +Hirose_DF3EA-02P-2H_1x02-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-02P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +4 +3 +Connector_Hirose +Hirose_DF3EA-03P-2H_1x03-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-03P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +5 +4 +Connector_Hirose +Hirose_DF3EA-04P-2H_1x04-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-04P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +6 +5 +Connector_Hirose +Hirose_DF3EA-05P-2H_1x05-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-05P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +7 +6 +Connector_Hirose +Hirose_DF3EA-06P-2H_1x06-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-06P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +8 +7 +Connector_Hirose +Hirose_DF3EA-07P-2H_1x07-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-07P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +9 +8 +Connector_Hirose +Hirose_DF3EA-08P-2H_1x08-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-08P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +10 +9 +Connector_Hirose +Hirose_DF3EA-09P-2H_1x09-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-09P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +11 +10 +Connector_Hirose +Hirose_DF3EA-10P-2H_1x10-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-10P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +12 +11 +Connector_Hirose +Hirose_DF3EA-11P-2H_1x11-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-11P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +13 +12 +Connector_Hirose +Hirose_DF3EA-12P-2H_1x12-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-12P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +14 +13 +Connector_Hirose +Hirose_DF3EA-13P-2H_1x13-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-13P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +15 +14 +Connector_Hirose +Hirose_DF3EA-14P-2H_1x14-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-14P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +16 +15 +Connector_Hirose +Hirose_DF3EA-15P-2H_1x15-1MP_P2.00mm_Horizontal +Hirose series connector, DF3EA-15P-2H (https://www.hirose.com/product/document?clcode=CL0543-0332-0-51&productname=DF3EA-5P-2H(51)&series=DF3&documenttype=2DDrawing&lang=en&documentid=0001163317), generated with kicad-footprint-generator +connector Hirose top entry +0 +17 +16 +Connector_Hirose +Hirose_DF11-4DP-2DSA_2x02_P2.00mm_Vertical +Hirose DF11 through hole, DF11-4DP-2DSA, 2 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +4 +4 +Connector_Hirose +Hirose_DF11-6DP-2DSA_2x03_P2.00mm_Vertical +Hirose DF11 through hole, DF11-6DP-2DSA, 3 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +6 +6 +Connector_Hirose +Hirose_DF11-8DP-2DSA_2x04_P2.00mm_Vertical +Hirose DF11 through hole, DF11-8DP-2DSA, 4 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +8 +8 +Connector_Hirose +Hirose_DF11-10DP-2DSA_2x05_P2.00mm_Vertical +Hirose DF11 through hole, DF11-10DP-2DSA, 5 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +10 +10 +Connector_Hirose +Hirose_DF11-12DP-2DSA_2x06_P2.00mm_Vertical +Hirose DF11 through hole, DF11-12DP-2DSA, 6 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +12 +12 +Connector_Hirose +Hirose_DF11-14DP-2DSA_2x07_P2.00mm_Vertical +Hirose DF11 through hole, DF11-14DP-2DSA, 7 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +14 +14 +Connector_Hirose +Hirose_DF11-16DP-2DSA_2x08_P2.00mm_Vertical +Hirose DF11 through hole, DF11-16DP-2DSA, 8 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +16 +16 +Connector_Hirose +Hirose_DF11-18DP-2DSA_2x09_P2.00mm_Vertical +Hirose DF11 through hole, DF11-18DP-2DSA, 9 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +18 +18 +Connector_Hirose +Hirose_DF11-20DP-2DSA_2x10_P2.00mm_Vertical +Hirose DF11 through hole, DF11-20DP-2DSA, 10 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +20 +20 +Connector_Hirose +Hirose_DF11-22DP-2DSA_2x11_P2.00mm_Vertical +Hirose DF11 through hole, DF11-22DP-2DSA, 11 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +22 +22 +Connector_Hirose +Hirose_DF11-24DP-2DSA_2x12_P2.00mm_Vertical +Hirose DF11 through hole, DF11-24DP-2DSA, 12 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +24 +24 +Connector_Hirose +Hirose_DF11-26DP-2DSA_2x13_P2.00mm_Vertical +Hirose DF11 through hole, DF11-26DP-2DSA, 13 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +26 +26 +Connector_Hirose +Hirose_DF11-28DP-2DSA_2x14_P2.00mm_Vertical +Hirose DF11 through hole, DF11-28DP-2DSA, 14 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +28 +28 +Connector_Hirose +Hirose_DF11-30DP-2DSA_2x15_P2.00mm_Vertical +Hirose DF11 through hole, DF11-30DP-2DSA, 15 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +30 +30 +Connector_Hirose +Hirose_DF11-32DP-2DSA_2x16_P2.00mm_Vertical +Hirose DF11 through hole, DF11-32DP-2DSA, 16 Pins per row (https://www.hirose.com/product/document?clcode=&productname=&series=DF11&documenttype=Catalog&lang=en&documentid=D31688_en), generated with kicad-footprint-generator +connector Hirose DF11 vertical +0 +32 +32 +Connector_Hirose +Hirose_DF12_DF12C3.0-10DS-0.5V_2x05_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-10DS-0.5V, 10 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +20 +10 +Connector_Hirose +Hirose_DF12_DF12C3.0-14DS-0.5V_2x07_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-14DS-0.5V, 14 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +28 +14 +Connector_Hirose +Hirose_DF12_DF12C3.0-20DS-0.5V_2x10_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-20DS-0.5V, 20 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +40 +20 +Connector_Hirose +Hirose_DF12_DF12C3.0-30DS-0.5V_2x15_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-30DS-0.5V, 30 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +60 +30 +Connector_Hirose +Hirose_DF12_DF12C3.0-32DS-0.5V_2x16_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-32DS-0.5V, 32 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +64 +32 +Connector_Hirose +Hirose_DF12_DF12C3.0-36DS-0.5V_2x18_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-36DS-0.5V, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +72 +36 +Connector_Hirose +Hirose_DF12_DF12C3.0-40DS-0.5V_2x20_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-40DS-0.5V, 40 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +80 +40 +Connector_Hirose +Hirose_DF12_DF12C3.0-50DS-0.5V_2x25_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-50DS-0.5V, 50 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +100 +50 +Connector_Hirose +Hirose_DF12_DF12C3.0-60DS-0.5V_2x30_P0.50mm_Vertical +Hirose DF12C SMD, DF12C3.0-60DS-0.5V, 60 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0694-9-81&productname=DF12C(3.0)-50DS-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000994748), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +120 +60 +Connector_Hirose +Hirose_DF12_DF12E3.0-10DP-0.5V_2x05_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-10DP-0.5V, 10 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +20 +10 +Connector_Hirose +Hirose_DF12_DF12E3.0-14DP-0.5V_2x07_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-14DP-0.5V, 14 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +28 +14 +Connector_Hirose +Hirose_DF12_DF12E3.0-20DP-0.5V_2x10_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-20DP-0.5V, 20 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +40 +20 +Connector_Hirose +Hirose_DF12_DF12E3.0-30DP-0.5V_2x15_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-30DP-0.5V, 30 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +60 +30 +Connector_Hirose +Hirose_DF12_DF12E3.0-32DP-0.5V_2x16_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-32DP-0.5V, 32 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +64 +32 +Connector_Hirose +Hirose_DF12_DF12E3.0-36DP-0.5V_2x18_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-36DP-0.5V, 36 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +72 +36 +Connector_Hirose +Hirose_DF12_DF12E3.0-40DP-0.5V_2x20_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-40DP-0.5V, 40 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +80 +40 +Connector_Hirose +Hirose_DF12_DF12E3.0-50DP-0.5V_2x25_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-50DP-0.5V, 50 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +100 +50 +Connector_Hirose +Hirose_DF12_DF12E3.0-60DP-0.5V_2x30_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-60DP-0.5V, 60 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +120 +60 +Connector_Hirose +Hirose_DF12_DF12E3.0-80DP-0.5V_2x40_P0.50mm_Vertical +Hirose DF12E SMD, DF12E3.0-80DP-0.5V, 80 Pins per row (https://www.hirose.com/product/document?clcode=CL0537-0834-6-81&productname=DF12E(3.0)-50DP-0.5V(81)&series=DF12&documenttype=2DDrawing&lang=en&documentid=0000992393), generated with kicad-footprint-generator +connector Hirose DF12 vertical +0 +160 +80 +Connector_Hirose +Hirose_DF13-02P-1.25DSA_1x02_P1.25mm_Vertical +Hirose DF13 through hole, DF13-02P-1.25DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +2 +2 +Connector_Hirose +Hirose_DF13-02P-1.25DS_1x02_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-02P-1.25DS, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +2 +2 +Connector_Hirose +Hirose_DF13-03P-1.25DSA_1x03_P1.25mm_Vertical +Hirose DF13 through hole, DF13-03P-1.25DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +3 +3 +Connector_Hirose +Hirose_DF13-03P-1.25DS_1x03_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-03P-1.25DS, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +3 +3 +Connector_Hirose +Hirose_DF13-04P-1.25DSA_1x04_P1.25mm_Vertical +Hirose DF13 through hole, DF13-04P-1.25DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +4 +4 +Connector_Hirose +Hirose_DF13-04P-1.25DS_1x04_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-04P-1.25DS, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +4 +4 +Connector_Hirose +Hirose_DF13-05P-1.25DSA_1x05_P1.25mm_Vertical +Hirose DF13 through hole, DF13-05P-1.25DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +5 +5 +Connector_Hirose +Hirose_DF13-05P-1.25DS_1x05_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-05P-1.25DS, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +5 +5 +Connector_Hirose +Hirose_DF13-06P-1.25DSA_1x06_P1.25mm_Vertical +Hirose DF13 through hole, DF13-06P-1.25DSA, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +6 +6 +Connector_Hirose +Hirose_DF13-06P-1.25DS_1x06_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-06P-1.25DS, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +6 +6 +Connector_Hirose +Hirose_DF13-07P-1.25DSA_1x07_P1.25mm_Vertical +Hirose DF13 through hole, DF13-07P-1.25DSA, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +7 +7 +Connector_Hirose +Hirose_DF13-07P-1.25DS_1x07_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-07P-1.25DS, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +7 +7 +Connector_Hirose +Hirose_DF13-08P-1.25DSA_1x08_P1.25mm_Vertical +Hirose DF13 through hole, DF13-08P-1.25DSA, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +8 +8 +Connector_Hirose +Hirose_DF13-08P-1.25DS_1x08_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-08P-1.25DS, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +8 +8 +Connector_Hirose +Hirose_DF13-09P-1.25DSA_1x09_P1.25mm_Vertical +Hirose DF13 through hole, DF13-09P-1.25DSA, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +9 +9 +Connector_Hirose +Hirose_DF13-09P-1.25DS_1x09_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-09P-1.25DS, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +9 +9 +Connector_Hirose +Hirose_DF13-10P-1.25DSA_1x10_P1.25mm_Vertical +Hirose DF13 through hole, DF13-10P-1.25DSA, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +10 +10 +Connector_Hirose +Hirose_DF13-10P-1.25DS_1x10_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-10P-1.25DS, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +10 +10 +Connector_Hirose +Hirose_DF13-11P-1.25DSA_1x11_P1.25mm_Vertical +Hirose DF13 through hole, DF13-11P-1.25DSA, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +11 +11 +Connector_Hirose +Hirose_DF13-11P-1.25DS_1x11_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-11P-1.25DS, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +11 +11 +Connector_Hirose +Hirose_DF13-12P-1.25DSA_1x12_P1.25mm_Vertical +Hirose DF13 through hole, DF13-12P-1.25DSA, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +12 +12 +Connector_Hirose +Hirose_DF13-12P-1.25DS_1x12_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-12P-1.25DS, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +12 +12 +Connector_Hirose +Hirose_DF13-13P-1.25DSA_1x13_P1.25mm_Vertical +Hirose DF13 through hole, DF13-13P-1.25DSA, 13 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +13 +13 +Connector_Hirose +Hirose_DF13-14P-1.25DSA_1x14_P1.25mm_Vertical +Hirose DF13 through hole, DF13-14P-1.25DSA, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +14 +14 +Connector_Hirose +Hirose_DF13-14P-1.25DS_1x14_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-14P-1.25DS, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +14 +14 +Connector_Hirose +Hirose_DF13-15P-1.25DSA_1x15_P1.25mm_Vertical +Hirose DF13 through hole, DF13-15P-1.25DSA, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-2P-1.25DSA%2850%29/), generated with kicad-footprint-generator +connector Hirose DF13 vertical +0 +15 +15 +Connector_Hirose +Hirose_DF13-15P-1.25DS_1x15_P1.25mm_Horizontal +Hirose DF13 through hole, DF13-15P-1.25DS, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13-4P-1.25DS%2820%29/), generated with kicad-footprint-generator +connector Hirose DF13 horizontal +0 +15 +15 +Connector_Hirose +Hirose_DF13C_CL535-0402-2-51_1x02-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0402-2-51, 2 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +4 +3 +Connector_Hirose +Hirose_DF13C_CL535-0403-5-51_1x03-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0403-5-51, 3 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +5 +4 +Connector_Hirose +Hirose_DF13C_CL535-0404-8-51_1x04-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0404-8-51, 4 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +6 +5 +Connector_Hirose +Hirose_DF13C_CL535-0405-0-51_1x05-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0405-0-51, 5 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +7 +6 +Connector_Hirose +Hirose_DF13C_CL535-0406-3-51_1x06-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0406-3-51, 6 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +8 +7 +Connector_Hirose +Hirose_DF13C_CL535-0407-6-51_1x07-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0407-6-51, 7 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +9 +8 +Connector_Hirose +Hirose_DF13C_CL535-0408-9-51_1x08-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0408-9-51, 8 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +10 +9 +Connector_Hirose +Hirose_DF13C_CL535-0409-1-51_1x09-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0409-1-51, 9 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +11 +10 +Connector_Hirose +Hirose_DF13C_CL535-0410-4-51_1x10-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0410-4-51, 10 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +12 +11 +Connector_Hirose +Hirose_DF13C_CL535-0411-3-51_1x11-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0411-3-51, 11 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +13 +12 +Connector_Hirose +Hirose_DF13C_CL535-0412-6-51_1x12-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0412-6-51, 12 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +14 +13 +Connector_Hirose +Hirose_DF13C_CL535-0414-1-51_1x14-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0414-1-51, 14 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +16 +15 +Connector_Hirose +Hirose_DF13C_CL535-0415-4-51_1x15-1MP_P1.25mm_Vertical +Hirose DF13C SMD, CL535-0415-4-51, 15 Pins per row (https://www.hirose.com/product/en/products/DF13/DF13C-10P-1.25V%2851%29/), generated with kicad-footprint-generator +connector Hirose DF13C vertical +0 +17 +16 +Connector_Hirose +Hirose_DF52-2S-0.8H_1x02-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-2S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +4 +3 +Connector_Hirose +Hirose_DF52-3S-0.8H_1x03-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-3S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +5 +4 +Connector_Hirose +Hirose_DF52-4S-0.8H_1x04-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-4S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +6 +5 +Connector_Hirose +Hirose_DF52-5S-0.8H_1x05-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-5S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +7 +6 +Connector_Hirose +Hirose_DF52-6S-0.8H_1x06-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-6S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +8 +7 +Connector_Hirose +Hirose_DF52-7S-0.8H_1x07-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-7S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +9 +8 +Connector_Hirose +Hirose_DF52-8S-0.8H_1x08-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-8S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +10 +9 +Connector_Hirose +Hirose_DF52-9S-0.8H_1x09-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-9S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +11 +10 +Connector_Hirose +Hirose_DF52-10S-0.8H_1x10-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-10S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +12 +11 +Connector_Hirose +Hirose_DF52-11S-0.8H_1x11-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-11S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +13 +12 +Connector_Hirose +Hirose_DF52-12S-0.8H_1x12-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-12S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +14 +13 +Connector_Hirose +Hirose_DF52-14S-0.8H_1x14-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-14S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +16 +15 +Connector_Hirose +Hirose_DF52-15S-0.8H_1x15-1MP_P0.80mm_Horizontal +Hirose series connector, DF52-15S-0.8H (https://www.hirose.com/product/en/products/DF52/DF52-3S-0.8H%2821%29/), generated with kicad-footprint-generator +connector Hirose top entry +0 +17 +16 +Connector_Hirose +Hirose_DF63-5P-3.96DSA_1x05_P3.96mm_Vertical +Hirose DF63 through hole, DF63-5P-3.96DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +5 +5 +Connector_Hirose +Hirose_DF63-6P-3.96DSA_1x06_P3.96mm_Vertical +Hirose DF63 through hole, DF63-6P-3.96DSA, 6 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +6 +6 +Connector_Hirose +Hirose_DF63M-1P-3.96DSA_1x01_P3.96mm_Vertical +Hirose DF63 through hole, DF63M-1P-3.96DSA, 1 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +1 +1 +Connector_Hirose +Hirose_DF63M-2P-3.96DSA_1x02_P3.96mm_Vertical +Hirose DF63 through hole, DF63M-2P-3.96DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +2 +2 +Connector_Hirose +Hirose_DF63M-3P-3.96DSA_1x03_P3.96mm_Vertical +Hirose DF63 through hole, DF63M-3P-3.96DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +3 +3 +Connector_Hirose +Hirose_DF63M-4P-3.96DSA_1x04_P3.96mm_Vertical +Hirose DF63 through hole, DF63M-4P-3.96DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +4 +4 +Connector_Hirose +Hirose_DF63R-1P-3.96DSA_1x01_P3.96mm_Vertical +Hirose DF63 through hole, DF63R-1P-3.96DSA, 1 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +1 +1 +Connector_Hirose +Hirose_DF63R-2P-3.96DSA_1x02_P3.96mm_Vertical +Hirose DF63 through hole, DF63R-2P-3.96DSA, 2 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +2 +2 +Connector_Hirose +Hirose_DF63R-3P-3.96DSA_1x03_P3.96mm_Vertical +Hirose DF63 through hole, DF63R-3P-3.96DSA, 3 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +3 +3 +Connector_Hirose +Hirose_DF63R-4P-3.96DSA_1x04_P3.96mm_Vertical +Hirose DF63 through hole, DF63R-4P-3.96DSA, 4 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +4 +4 +Connector_Hirose +Hirose_DF63R-5P-3.96DSA_1x05_P3.96mm_Vertical +Hirose DF63 through hole, DF63R-5P-3.96DSA, 5 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated with kicad-footprint-generator +connector Hirose DF63 vertical +0 +5 +5 +Connector_IDC +IDC-Header_2x03_P2.54mm_Horizontal +Through hole angled IDC box header, 2x03, 2.54mm pitch, double rows +Through hole IDC box header THT 2x03 2.54mm double row +0 +6 +6 +Connector_IDC +IDC-Header_2x03_P2.54mm_Vertical +Through hole straight IDC box header, 2x03, 2.54mm pitch, double rows +Through hole IDC box header THT 2x03 2.54mm double row +0 +6 +6 +Connector_IDC +IDC-Header_2x04_P2.54mm_Horizontal +Through hole angled IDC box header, 2x04, 2.54mm pitch, double rows +Through hole IDC box header THT 2x04 2.54mm double row +0 +8 +8 +Connector_IDC +IDC-Header_2x04_P2.54mm_Vertical +Through hole straight IDC box header, 2x04, 2.54mm pitch, double rows +Through hole IDC box header THT 2x04 2.54mm double row +0 +8 +8 +Connector_IDC +IDC-Header_2x05_P2.54mm_Horizontal +Through hole angled IDC box header, 2x05, 2.54mm pitch, double rows +Through hole IDC box header THT 2x05 2.54mm double row +0 +10 +10 +Connector_IDC +IDC-Header_2x05_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +12 +10 +Connector_IDC +IDC-Header_2x05_P2.54mm_Vertical +Through hole straight IDC box header, 2x05, 2.54mm pitch, double rows +Through hole IDC box header THT 2x05 2.54mm double row +0 +10 +10 +Connector_IDC +IDC-Header_2x05_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +12 +10 +Connector_IDC +IDC-Header_2x06_P2.54mm_Horizontal +Through hole angled IDC box header, 2x06, 2.54mm pitch, double rows +Through hole IDC box header THT 2x06 2.54mm double row +0 +12 +12 +Connector_IDC +IDC-Header_2x06_P2.54mm_Vertical +Through hole straight IDC box header, 2x06, 2.54mm pitch, double rows +Through hole IDC box header THT 2x06 2.54mm double row +0 +12 +12 +Connector_IDC +IDC-Header_2x07_P2.54mm_Horizontal +Through hole angled IDC box header, 2x07, 2.54mm pitch, double rows +Through hole IDC box header THT 2x07 2.54mm double row +0 +14 +14 +Connector_IDC +IDC-Header_2x07_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +16 +14 +Connector_IDC +IDC-Header_2x07_P2.54mm_Vertical +Through hole straight IDC box header, 2x07, 2.54mm pitch, double rows +Through hole IDC box header THT 2x07 2.54mm double row +0 +14 +14 +Connector_IDC +IDC-Header_2x07_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +16 +14 +Connector_IDC +IDC-Header_2x08_P2.54mm_Horizontal +Through hole angled IDC box header, 2x08, 2.54mm pitch, double rows +Through hole IDC box header THT 2x08 2.54mm double row +0 +16 +16 +Connector_IDC +IDC-Header_2x08_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +18 +16 +Connector_IDC +IDC-Header_2x08_P2.54mm_Vertical +Through hole straight IDC box header, 2x08, 2.54mm pitch, double rows +Through hole IDC box header THT 2x08 2.54mm double row +0 +16 +16 +Connector_IDC +IDC-Header_2x08_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +18 +16 +Connector_IDC +IDC-Header_2x10_P2.54mm_Horizontal +Through hole angled IDC box header, 2x10, 2.54mm pitch, double rows +Through hole IDC box header THT 2x10 2.54mm double row +0 +20 +20 +Connector_IDC +IDC-Header_2x10_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +22 +20 +Connector_IDC +IDC-Header_2x10_P2.54mm_Vertical +Through hole straight IDC box header, 2x10, 2.54mm pitch, double rows +Through hole IDC box header THT 2x10 2.54mm double row +0 +20 +20 +Connector_IDC +IDC-Header_2x10_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +22 +20 +Connector_IDC +IDC-Header_2x13_P2.54mm_Horizontal +Through hole angled IDC box header, 2x13, 2.54mm pitch, double rows +Through hole IDC box header THT 2x13 2.54mm double row +0 +26 +26 +Connector_IDC +IDC-Header_2x13_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +28 +26 +Connector_IDC +IDC-Header_2x13_P2.54mm_Vertical +Through hole straight IDC box header, 2x13, 2.54mm pitch, double rows +Through hole IDC box header THT 2x13 2.54mm double row +0 +26 +26 +Connector_IDC +IDC-Header_2x13_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +28 +26 +Connector_IDC +IDC-Header_2x15_P2.54mm_Horizontal +Through hole angled IDC box header, 2x15, 2.54mm pitch, double rows +Through hole IDC box header THT 2x15 2.54mm double row +0 +30 +30 +Connector_IDC +IDC-Header_2x15_P2.54mm_Vertical +Through hole straight IDC box header, 2x15, 2.54mm pitch, double rows +Through hole IDC box header THT 2x15 2.54mm double row +0 +30 +30 +Connector_IDC +IDC-Header_2x17_P2.54mm_Horizontal +Through hole angled IDC box header, 2x17, 2.54mm pitch, double rows +Through hole IDC box header THT 2x17 2.54mm double row +0 +34 +34 +Connector_IDC +IDC-Header_2x17_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +36 +34 +Connector_IDC +IDC-Header_2x17_P2.54mm_Vertical +Through hole straight IDC box header, 2x17, 2.54mm pitch, double rows +Through hole IDC box header THT 2x17 2.54mm double row +0 +34 +34 +Connector_IDC +IDC-Header_2x17_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +36 +34 +Connector_IDC +IDC-Header_2x20_P2.54mm_Horizontal +Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows +Through hole IDC box header THT 2x20 2.54mm double row +0 +40 +40 +Connector_IDC +IDC-Header_2x20_P2.54mm_Horizontal_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +42 +41 +Connector_IDC +IDC-Header_2x20_P2.54mm_Vertical +Through hole straight IDC box header, 2x20, 2.54mm pitch, double rows +Through hole IDC box header THT 2x20 2.54mm double row +0 +40 +40 +Connector_IDC +IDC-Header_2x20_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +42 +40 +Connector_IDC +IDC-Header_2x25_P2.54mm_Horizontal +Through hole angled IDC box header, 2x25, 2.54mm pitch, double rows +Through hole IDC box header THT 2x25 2.54mm double row +0 +50 +50 +Connector_IDC +IDC-Header_2x25_P2.54mm_Vertical +Through hole straight IDC box header, 2x25, 2.54mm pitch, double rows +Through hole IDC box header THT 2x25 2.54mm double row +0 +50 +50 +Connector_IDC +IDC-Header_2x25_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +52 +50 +Connector_IDC +IDC-Header_2x30_P2.54mm_Horizontal +Through hole angled IDC box header, 2x30, 2.54mm pitch, double rows +Through hole IDC box header THT 2x30 2.54mm double row +0 +60 +60 +Connector_IDC +IDC-Header_2x30_P2.54mm_Vertical +Through hole straight IDC box header, 2x30, 2.54mm pitch, double rows +Through hole IDC box header THT 2x30 2.54mm double row +0 +60 +60 +Connector_IDC +IDC-Header_2x30_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +62 +60 +Connector_IDC +IDC-Header_2x32_P2.54mm_Horizontal +Through hole angled IDC box header, 2x32, 2.54mm pitch, double rows +Through hole IDC box header THT 2x32 2.54mm double row +0 +64 +64 +Connector_IDC +IDC-Header_2x32_P2.54mm_Vertical +Through hole straight IDC box header, 2x32, 2.54mm pitch, double rows +Through hole IDC box header THT 2x32 2.54mm double row +0 +64 +64 +Connector_IDC +IDC-Header_2x32_P2.54mm_Vertical_Lock +Connector IDC Locked, 10 contacts, compatible header: PANCON HE10 (Series 50, (https://www.reboul.fr/storage/00003af6.pdf) +connector idc locked +0 +66 +64 +Connector_JAE +JAE_LY20-4P-DLT1_2x02_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-4P-DLT1, 2 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +4 +4 +Connector_JAE +JAE_LY20-4P-DT1_2x02_P2.00mm_Vertical +Molex LY 20 series connector, LY20-4P-DT1, 2 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +4 +4 +Connector_JAE +JAE_LY20-6P-DLT1_2x03_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-6P-DLT1, 3 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +6 +6 +Connector_JAE +JAE_LY20-6P-DT1_2x03_P2.00mm_Vertical +Molex LY 20 series connector, LY20-6P-DT1, 3 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +6 +6 +Connector_JAE +JAE_LY20-8P-DLT1_2x04_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-8P-DLT1, 4 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +8 +8 +Connector_JAE +JAE_LY20-8P-DT1_2x04_P2.00mm_Vertical +Molex LY 20 series connector, LY20-8P-DT1, 4 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +8 +8 +Connector_JAE +JAE_LY20-10P-DLT1_2x05_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-10P-DLT1, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +10 +10 +Connector_JAE +JAE_LY20-10P-DT1_2x05_P2.00mm_Vertical +Molex LY 20 series connector, LY20-10P-DT1, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +10 +10 +Connector_JAE +JAE_LY20-12P-DLT1_2x06_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-12P-DLT1, 6 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +12 +12 +Connector_JAE +JAE_LY20-12P-DT1_2x06_P2.00mm_Vertical +Molex LY 20 series connector, LY20-12P-DT1, 6 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +12 +12 +Connector_JAE +JAE_LY20-14P-DLT1_2x07_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-14P-DLT1, 7 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +14 +14 +Connector_JAE +JAE_LY20-14P-DT1_2x07_P2.00mm_Vertical +Molex LY 20 series connector, LY20-14P-DT1, 7 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +14 +14 +Connector_JAE +JAE_LY20-16P-DLT1_2x08_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-16P-DLT1, 8 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +16 +16 +Connector_JAE +JAE_LY20-16P-DT1_2x08_P2.00mm_Vertical +Molex LY 20 series connector, LY20-16P-DT1, 8 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +16 +16 +Connector_JAE +JAE_LY20-18P-DLT1_2x09_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-18P-DLT1, 9 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +18 +18 +Connector_JAE +JAE_LY20-18P-DT1_2x09_P2.00mm_Vertical +Molex LY 20 series connector, LY20-18P-DT1, 9 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +18 +18 +Connector_JAE +JAE_LY20-20P-DLT1_2x10_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-20P-DLT1, 10 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +20 +20 +Connector_JAE +JAE_LY20-20P-DT1_2x10_P2.00mm_Vertical +Molex LY 20 series connector, LY20-20P-DT1, 10 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +20 +20 +Connector_JAE +JAE_LY20-22P-DLT1_2x11_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-22P-DLT1, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +22 +22 +Connector_JAE +JAE_LY20-22P-DT1_2x11_P2.00mm_Vertical +Molex LY 20 series connector, LY20-22P-DT1, 11 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +22 +22 +Connector_JAE +JAE_LY20-24P-DLT1_2x12_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-24P-DLT1, 12 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +24 +24 +Connector_JAE +JAE_LY20-24P-DT1_2x12_P2.00mm_Vertical +Molex LY 20 series connector, LY20-24P-DT1, 12 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +24 +24 +Connector_JAE +JAE_LY20-26P-DLT1_2x13_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-26P-DLT1, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +26 +26 +Connector_JAE +JAE_LY20-26P-DT1_2x13_P2.00mm_Vertical +Molex LY 20 series connector, LY20-26P-DT1, 13 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +26 +26 +Connector_JAE +JAE_LY20-28P-DLT1_2x14_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-28P-DLT1, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +28 +28 +Connector_JAE +JAE_LY20-28P-DT1_2x14_P2.00mm_Vertical +Molex LY 20 series connector, LY20-28P-DT1, 14 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +28 +28 +Connector_JAE +JAE_LY20-30P-DLT1_2x15_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-30P-DLT1, 15 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +30 +30 +Connector_JAE +JAE_LY20-30P-DT1_2x15_P2.00mm_Vertical +Molex LY 20 series connector, LY20-30P-DT1, 15 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +30 +30 +Connector_JAE +JAE_LY20-32P-DLT1_2x16_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-32P-DLT1, 16 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +32 +32 +Connector_JAE +JAE_LY20-32P-DT1_2x16_P2.00mm_Vertical +Molex LY 20 series connector, LY20-32P-DT1, 16 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +32 +32 +Connector_JAE +JAE_LY20-34P-DLT1_2x17_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-34P-DLT1, 17 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +34 +34 +Connector_JAE +JAE_LY20-34P-DT1_2x17_P2.00mm_Vertical +Molex LY 20 series connector, LY20-34P-DT1, 17 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +34 +34 +Connector_JAE +JAE_LY20-36P-DLT1_2x18_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-36P-DLT1, 18 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +36 +36 +Connector_JAE +JAE_LY20-36P-DT1_2x18_P2.00mm_Vertical +Molex LY 20 series connector, LY20-36P-DT1, 18 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +36 +36 +Connector_JAE +JAE_LY20-38P-DLT1_2x19_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-38P-DLT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +38 +38 +Connector_JAE +JAE_LY20-38P-DT1_2x19_P2.00mm_Vertical +Molex LY 20 series connector, LY20-38P-DT1, 19 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +38 +38 +Connector_JAE +JAE_LY20-40P-DLT1_2x20_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-40P-DLT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +40 +40 +Connector_JAE +JAE_LY20-40P-DT1_2x20_P2.00mm_Vertical +Molex LY 20 series connector, LY20-40P-DT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +40 +40 +Connector_JAE +JAE_LY20-42P-DLT1_2x21_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-42P-DLT1, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +42 +42 +Connector_JAE +JAE_LY20-42P-DT1_2x21_P2.00mm_Vertical +Molex LY 20 series connector, LY20-42P-DT1, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +42 +42 +Connector_JAE +JAE_LY20-44P-DLT1_2x22_P2.00mm_Horizontal +Molex LY 20 series connector, LY20-44P-DLT1, 22 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator +connector JAE top entry +0 +44 +44 +Connector_JAE +JAE_LY20-44P-DT1_2x22_P2.00mm_Vertical +Molex LY 20 series connector, LY20-44P-DT1, 22 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ103130.pdf), generated with kicad-footprint-generator +connector JAE side entry +0 +44 +44 +Connector_JAE +JAE_MM70-314-310B1 +http://www.heilind.com/marketing/documents/jae/JAE_MM70.pdf +connector JAE MXM +0 +280 +279 +Connector_JST +JST_ACH_BM01B-ACHSS-A-GAN-ETF_1x01-1MP_P1.20mm_Vertical +JST ACH series connector, BM01B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator +connector JST ACH vertical +0 +3 +2 +Connector_JST +JST_ACH_BM02B-ACHSS-GAN-ETF_1x02-1MP_P1.20mm_Vertical +JST ACH series connector, BM02B-ACHSS-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator +connector JST ACH vertical +0 +4 +3 +Connector_JST +JST_ACH_BM03B-ACHSS-GAN-ETF_1x03-1MP_P1.20mm_Vertical +JST ACH series connector, BM03B-ACHSS-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator +connector JST ACH vertical +0 +5 +4 +Connector_JST +JST_ACH_BM04B-ACHSS-A-GAN-ETF_1x04-1MP_P1.20mm_Vertical +JST ACH series connector, BM04B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator +connector JST ACH vertical +0 +6 +5 +Connector_JST +JST_ACH_BM05B-ACHSS-A-GAN-ETF_1x05-1MP_P1.20mm_Vertical +JST ACH series connector, BM05B-ACHSS-A-GAN-ETF (http://www.jst-mfg.com/product/pdf/eng/eACH.pdf), generated with kicad-footprint-generator +connector JST ACH vertical +0 +7 +6 +Connector_JST +JST_AUH_BM03B-AUHKS-GA-TB_1x03-1MP_P1.50mm_Vertical +JST AUH series connector, BM03B-AUHKS-GA-TB (http://www.jst-mfg.com/product/pdf/eng/eAUH.pdf), generated with kicad-footprint-generator +connector JST AUH side entry +0 +5 +4 +Connector_JST +JST_AUH_BM05B-AUHKS-GA-TB_1x05-1MP_P1.50mm_Vertical +JST AUH series connector, BM05B-AUHKS-GA-TB (http://www.jst-mfg.com/product/pdf/eng/eAUH.pdf), generated with kicad-footprint-generator +connector JST AUH side entry +0 +7 +6 +Connector_JST +JST_EH_B2B-EH-A_1x02_P2.50mm_Vertical +JST EH series connector, B2B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +2 +2 +Connector_JST +JST_EH_B3B-EH-A_1x03_P2.50mm_Vertical +JST EH series connector, B3B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +3 +3 +Connector_JST +JST_EH_B4B-EH-A_1x04_P2.50mm_Vertical +JST EH series connector, B4B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +4 +4 +Connector_JST +JST_EH_B5B-EH-A_1x05_P2.50mm_Vertical +JST EH series connector, B5B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +5 +5 +Connector_JST +JST_EH_B6B-EH-A_1x06_P2.50mm_Vertical +JST EH series connector, B6B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +6 +6 +Connector_JST +JST_EH_B7B-EH-A_1x07_P2.50mm_Vertical +JST EH series connector, B7B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +7 +7 +Connector_JST +JST_EH_B8B-EH-A_1x08_P2.50mm_Vertical +JST EH series connector, B8B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +8 +8 +Connector_JST +JST_EH_B9B-EH-A_1x09_P2.50mm_Vertical +JST EH series connector, B9B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH vertical +0 +9 +9 +Connector_JST +JST_EH_B10B-EH-A_1x10_P2.50mm_Vertical +JST EH series connector, B10B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH side entry +0 +10 +10 +Connector_JST +JST_EH_B11B-EH-A_1x11_P2.50mm_Vertical +JST EH series connector, B11B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH side entry +0 +11 +11 +Connector_JST +JST_EH_B12B-EH-A_1x12_P2.50mm_Vertical +JST EH series connector, B12B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH side entry +0 +12 +12 +Connector_JST +JST_EH_B13B-EH-A_1x13_P2.50mm_Vertical +JST EH series connector, B13B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH side entry +0 +13 +13 +Connector_JST +JST_EH_B14B-EH-A_1x14_P2.50mm_Vertical +JST EH series connector, B14B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH side entry +0 +14 +14 +Connector_JST +JST_EH_B15B-EH-A_1x15_P2.50mm_Vertical +JST EH series connector, B15B-EH-A (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH side entry +0 +15 +15 +Connector_JST +JST_EH_S2B-EH_1x02_P2.50mm_Horizontal +JST EH series connector, S2B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +2 +2 +Connector_JST +JST_EH_S3B-EH_1x03_P2.50mm_Horizontal +JST EH series connector, S3B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +3 +3 +Connector_JST +JST_EH_S4B-EH_1x04_P2.50mm_Horizontal +JST EH series connector, S4B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +4 +4 +Connector_JST +JST_EH_S5B-EH_1x05_P2.50mm_Horizontal +JST EH series connector, S5B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +5 +5 +Connector_JST +JST_EH_S6B-EH_1x06_P2.50mm_Horizontal +JST EH series connector, S6B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +6 +6 +Connector_JST +JST_EH_S7B-EH_1x07_P2.50mm_Horizontal +JST EH series connector, S7B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +7 +7 +Connector_JST +JST_EH_S8B-EH_1x08_P2.50mm_Horizontal +JST EH series connector, S8B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +8 +8 +Connector_JST +JST_EH_S9B-EH_1x09_P2.50mm_Horizontal +JST EH series connector, S9B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH horizontal +0 +9 +9 +Connector_JST +JST_EH_S10B-EH_1x10_P2.50mm_Horizontal +JST EH series connector, S10B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH top entry +0 +10 +10 +Connector_JST +JST_EH_S11B-EH_1x11_P2.50mm_Horizontal +JST EH series connector, S11B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH top entry +0 +11 +11 +Connector_JST +JST_EH_S12B-EH_1x12_P2.50mm_Horizontal +JST EH series connector, S12B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH top entry +0 +12 +12 +Connector_JST +JST_EH_S13B-EH_1x13_P2.50mm_Horizontal +JST EH series connector, S13B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH top entry +0 +13 +13 +Connector_JST +JST_EH_S14B-EH_1x14_P2.50mm_Horizontal +JST EH series connector, S14B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH top entry +0 +14 +14 +Connector_JST +JST_EH_S15B-EH_1x15_P2.50mm_Horizontal +JST EH series connector, S15B-EH (http://www.jst-mfg.com/product/pdf/eng/eEH.pdf), generated with kicad-footprint-generator +connector JST EH top entry +0 +15 +15 +Connector_JST +JST_GH_BM02B-GHS-TBT_1x02-1MP_P1.25mm_Vertical +JST GH series connector, BM02B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +4 +3 +Connector_JST +JST_GH_BM03B-GHS-TBT_1x03-1MP_P1.25mm_Vertical +JST GH series connector, BM03B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +5 +4 +Connector_JST +JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical +JST GH series connector, BM04B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +6 +5 +Connector_JST +JST_GH_BM05B-GHS-TBT_1x05-1MP_P1.25mm_Vertical +JST GH series connector, BM05B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +7 +6 +Connector_JST +JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical +JST GH series connector, BM06B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +8 +7 +Connector_JST +JST_GH_BM07B-GHS-TBT_1x07-1MP_P1.25mm_Vertical +JST GH series connector, BM07B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +9 +8 +Connector_JST +JST_GH_BM08B-GHS-TBT_1x08-1MP_P1.25mm_Vertical +JST GH series connector, BM08B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +10 +9 +Connector_JST +JST_GH_BM09B-GHS-TBT_1x09-1MP_P1.25mm_Vertical +JST GH series connector, BM09B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +11 +10 +Connector_JST +JST_GH_BM10B-GHS-TBT_1x10-1MP_P1.25mm_Vertical +JST GH series connector, BM10B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +12 +11 +Connector_JST +JST_GH_BM11B-GHS-TBT_1x11-1MP_P1.25mm_Vertical +JST GH series connector, BM11B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +13 +12 +Connector_JST +JST_GH_BM12B-GHS-TBT_1x12-1MP_P1.25mm_Vertical +JST GH series connector, BM12B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +14 +13 +Connector_JST +JST_GH_BM13B-GHS-TBT_1x13-1MP_P1.25mm_Vertical +JST GH series connector, BM13B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +15 +14 +Connector_JST +JST_GH_BM14B-GHS-TBT_1x14-1MP_P1.25mm_Vertical +JST GH series connector, BM14B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +16 +15 +Connector_JST +JST_GH_BM15B-GHS-TBT_1x15-1MP_P1.25mm_Vertical +JST GH series connector, BM15B-GHS-TBT (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH side entry +0 +17 +16 +Connector_JST +JST_GH_SM02B-GHS-TB_1x02-1MP_P1.25mm_Horizontal +JST GH series connector, SM02B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +4 +3 +Connector_JST +JST_GH_SM03B-GHS-TB_1x03-1MP_P1.25mm_Horizontal +JST GH series connector, SM03B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +5 +4 +Connector_JST +JST_GH_SM04B-GHS-TB_1x04-1MP_P1.25mm_Horizontal +JST GH series connector, SM04B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +6 +5 +Connector_JST +JST_GH_SM05B-GHS-TB_1x05-1MP_P1.25mm_Horizontal +JST GH series connector, SM05B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +7 +6 +Connector_JST +JST_GH_SM06B-GHS-TB_1x06-1MP_P1.25mm_Horizontal +JST GH series connector, SM06B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +8 +7 +Connector_JST +JST_GH_SM07B-GHS-TB_1x07-1MP_P1.25mm_Horizontal +JST GH series connector, SM07B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +9 +8 +Connector_JST +JST_GH_SM08B-GHS-TB_1x08-1MP_P1.25mm_Horizontal +JST GH series connector, SM08B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +10 +9 +Connector_JST +JST_GH_SM09B-GHS-TB_1x09-1MP_P1.25mm_Horizontal +JST GH series connector, SM09B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +11 +10 +Connector_JST +JST_GH_SM10B-GHS-TB_1x10-1MP_P1.25mm_Horizontal +JST GH series connector, SM10B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +12 +11 +Connector_JST +JST_GH_SM11B-GHS-TB_1x11-1MP_P1.25mm_Horizontal +JST GH series connector, SM11B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +13 +12 +Connector_JST +JST_GH_SM12B-GHS-TB_1x12-1MP_P1.25mm_Horizontal +JST GH series connector, SM12B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +14 +13 +Connector_JST +JST_GH_SM13B-GHS-TB_1x13-1MP_P1.25mm_Horizontal +JST GH series connector, SM13B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +15 +14 +Connector_JST +JST_GH_SM14B-GHS-TB_1x14-1MP_P1.25mm_Horizontal +JST GH series connector, SM14B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +16 +15 +Connector_JST +JST_GH_SM15B-GHS-TB_1x15-1MP_P1.25mm_Horizontal +JST GH series connector, SM15B-GHS-TB (http://www.jst-mfg.com/product/pdf/eng/eGH.pdf), generated with kicad-footprint-generator +connector JST GH top entry +0 +17 +16 +Connector_JST +JST_J2100_B06B-J21DK-GGXR_2x03_P2.50x4.00mm_Vertical +JST J2100 series connector, B06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 vertical +0 +8 +6 +Connector_JST +JST_J2100_B08B-J21DK-GGXR_2x04_P2.50x4.00mm_Vertical +JST J2100 series connector, B08B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 vertical +0 +10 +8 +Connector_JST +JST_J2100_B10B-J21DK-GGXR_2x05_P2.50x4.00mm_Vertical +JST J2100 series connector, B10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 vertical +0 +12 +10 +Connector_JST +JST_J2100_B12B-J21DK-GGXR_2x06_P2.50x4.00mm_Vertical +JST J2100 series connector, B12B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 vertical +0 +14 +12 +Connector_JST +JST_J2100_B16B-J21DK-GGXR_2x08_P2.50x4.00mm_Vertical +JST J2100 series connector, B16B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 vertical +0 +18 +16 +Connector_JST +JST_J2100_B20B-J21DK-GGXR_2x10_P2.50x4.00mm_Vertical +JST J2100 series connector, B20B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 vertical +0 +22 +20 +Connector_JST +JST_J2100_S06B-J21DK-GGXR_2x03_P2.50mm_Horizontal +JST J2100 series connector, S06B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 horizontal +0 +7 +6 +Connector_JST +JST_J2100_S08B-J21DK-GGXR_2x04_P2.50mm_Horizontal +JST J2100 series connector, S08B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 horizontal +0 +10 +8 +Connector_JST +JST_J2100_S10B-J21DK-GGXR_2x05_P2.50mm_Horizontal +JST J2100 series connector, S10B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 horizontal +0 +12 +10 +Connector_JST +JST_J2100_S12B-J21DK-GGXR_2x06_P2.50mm_Horizontal +JST J2100 series connector, S12B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 horizontal +0 +14 +12 +Connector_JST +JST_J2100_S16B-J21DK-GGXR_2x08_P2.50mm_Horizontal +JST J2100 series connector, S16B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 horizontal +0 +18 +16 +Connector_JST +JST_J2100_S20B-J21DK-GGXR_2x10_P2.50mm_Horizontal +JST J2100 series connector, S20B-J21DK-GGXR (http://www.jst-mfg.com/product/pdf/eng/eJFA-J2000.pdf), generated with kicad-footprint-generator +connector JST J2100 horizontal +0 +22 +20 +Connector_JST +JST_JWPF_B02B-JWPF-SK-R_1x02_P2.00mm_Vertical +JST JWPF series connector, B02B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator +connector JST JWPF side entry +0 +2 +2 +Connector_JST +JST_JWPF_B03B-JWPF-SK-R_1x03_P2.00mm_Vertical +JST JWPF series connector, B03B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator +connector JST JWPF side entry +0 +3 +3 +Connector_JST +JST_JWPF_B04B-JWPF-SK-R_1x04_P2.00mm_Vertical +JST JWPF series connector, B04B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator +connector JST JWPF side entry +0 +4 +4 +Connector_JST +JST_JWPF_B06B-JWPF-SK-R_2x03_P2.00mm_Vertical +JST JWPF series connector, B06B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator +connector JST JWPF side entry +0 +6 +6 +Connector_JST +JST_JWPF_B08B-JWPF-SK-R_2x04_P2.00mm_Vertical +JST JWPF series connector, B08B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator +connector JST JWPF side entry +0 +8 +8 +Connector_JST +JST_LEA_SM02B-LEASS-TF_1x02-1MP_P4.20mm_Horizontal +JST LEA series connector, SM02B-LEASS-TF (http://www.jst-mfg.com/product/pdf/eng/eLEA.pdf), generated with kicad-footprint-generator +connector JST LEA top entry +0 +4 +3 +Connector_JST +JST_NV_B02P-NV_1x02_P5.00mm_Vertical +JST NV series connector, B02P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator +connector JST NV side entry +0 +2 +2 +Connector_JST +JST_NV_B03P-NV_1x03_P5.00mm_Vertical +JST NV series connector, B03P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator +connector JST NV side entry +0 +3 +3 +Connector_JST +JST_NV_B04P-NV_1x04_P5.00mm_Vertical +JST NV series connector, B04P-NV (http://www.jst-mfg.com/product/pdf/eng/eNV.pdf), generated with kicad-footprint-generator +connector JST NV side entry +0 +4 +4 +Connector_JST +JST_PHD_B8B-PHDSS_2x04_P2.00mm_Vertical +JST PHD series connector, B8B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +8 +8 +Connector_JST +JST_PHD_B10B-PHDSS_2x05_P2.00mm_Vertical +JST PHD series connector, B10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +10 +10 +Connector_JST +JST_PHD_B12B-PHDSS_2x06_P2.00mm_Vertical +JST PHD series connector, B12B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +12 +12 +Connector_JST +JST_PHD_B14B-PHDSS_2x07_P2.00mm_Vertical +JST PHD series connector, B14B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +14 +14 +Connector_JST +JST_PHD_B16B-PHDSS_2x08_P2.00mm_Vertical +JST PHD series connector, B16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +16 +16 +Connector_JST +JST_PHD_B18B-PHDSS_2x09_P2.00mm_Vertical +JST PHD series connector, B18B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +18 +18 +Connector_JST +JST_PHD_B20B-PHDSS_2x10_P2.00mm_Vertical +JST PHD series connector, B20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +20 +20 +Connector_JST +JST_PHD_B22B-PHDSS_2x11_P2.00mm_Vertical +JST PHD series connector, B22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +22 +22 +Connector_JST +JST_PHD_B24B-PHDSS_2x12_P2.00mm_Vertical +JST PHD series connector, B24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +24 +24 +Connector_JST +JST_PHD_B26B-PHDSS_2x13_P2.00mm_Vertical +JST PHD series connector, B26B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +26 +26 +Connector_JST +JST_PHD_B28B-PHDSS_2x14_P2.00mm_Vertical +JST PHD series connector, B28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +28 +28 +Connector_JST +JST_PHD_B30B-PHDSS_2x15_P2.00mm_Vertical +JST PHD series connector, B30B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +30 +30 +Connector_JST +JST_PHD_B32B-PHDSS_2x16_P2.00mm_Vertical +JST PHD series connector, B32B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +32 +32 +Connector_JST +JST_PHD_B34B-PHDSS_2x17_P2.00mm_Vertical +JST PHD series connector, B34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD vertical +0 +34 +34 +Connector_JST +JST_PHD_S8B-PHDSS_2x04_P2.00mm_Horizontal +JST PHD series connector, S8B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +8 +8 +Connector_JST +JST_PHD_S10B-PHDSS_2x05_P2.00mm_Horizontal +JST PHD series connector, S10B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +10 +10 +Connector_JST +JST_PHD_S12B-PHDSS_2x06_P2.00mm_Horizontal +JST PHD series connector, S12B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +12 +12 +Connector_JST +JST_PHD_S14B-PHDSS_2x07_P2.00mm_Horizontal +JST PHD series connector, S14B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +14 +14 +Connector_JST +JST_PHD_S16B-PHDSS_2x08_P2.00mm_Horizontal +JST PHD series connector, S16B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +16 +16 +Connector_JST +JST_PHD_S18B-PHDSS_2x09_P2.00mm_Horizontal +JST PHD series connector, S18B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +18 +18 +Connector_JST +JST_PHD_S20B-PHDSS_2x10_P2.00mm_Horizontal +JST PHD series connector, S20B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +20 +20 +Connector_JST +JST_PHD_S22B-PHDSS_2x11_P2.00mm_Horizontal +JST PHD series connector, S22B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +22 +22 +Connector_JST +JST_PHD_S24B-PHDSS_2x12_P2.00mm_Horizontal +JST PHD series connector, S24B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +24 +24 +Connector_JST +JST_PHD_S26B-PHDSS_2x13_P2.00mm_Horizontal +JST PHD series connector, S26B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +26 +26 +Connector_JST +JST_PHD_S28B-PHDSS_2x14_P2.00mm_Horizontal +JST PHD series connector, S28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +28 +28 +Connector_JST +JST_PHD_S30B-PHDSS_2x15_P2.00mm_Horizontal +JST PHD series connector, S30B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +30 +30 +Connector_JST +JST_PHD_S32B-PHDSS_2x16_P2.00mm_Horizontal +JST PHD series connector, S32B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +32 +32 +Connector_JST +JST_PHD_S34B-PHDSS_2x17_P2.00mm_Horizontal +JST PHD series connector, S34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator +connector JST PHD horizontal +0 +34 +34 +Connector_JST +JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical +JST PH series connector, B2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +2 +2 +Connector_JST +JST_PH_B2B-PH-SM4-TB_1x02-1MP_P2.00mm_Vertical +JST PH series connector, B2B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +4 +3 +Connector_JST +JST_PH_B3B-PH-K_1x03_P2.00mm_Vertical +JST PH series connector, B3B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +3 +3 +Connector_JST +JST_PH_B3B-PH-SM4-TB_1x03-1MP_P2.00mm_Vertical +JST PH series connector, B3B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +5 +4 +Connector_JST +JST_PH_B4B-PH-K_1x04_P2.00mm_Vertical +JST PH series connector, B4B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +4 +4 +Connector_JST +JST_PH_B4B-PH-SM4-TB_1x04-1MP_P2.00mm_Vertical +JST PH series connector, B4B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +6 +5 +Connector_JST +JST_PH_B5B-PH-K_1x05_P2.00mm_Vertical +JST PH series connector, B5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +5 +5 +Connector_JST +JST_PH_B5B-PH-SM4-TB_1x05-1MP_P2.00mm_Vertical +JST PH series connector, B5B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +7 +6 +Connector_JST +JST_PH_B6B-PH-K_1x06_P2.00mm_Vertical +JST PH series connector, B6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +6 +6 +Connector_JST +JST_PH_B6B-PH-SM4-TB_1x06-1MP_P2.00mm_Vertical +JST PH series connector, B6B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +8 +7 +Connector_JST +JST_PH_B7B-PH-K_1x07_P2.00mm_Vertical +JST PH series connector, B7B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +7 +7 +Connector_JST +JST_PH_B7B-PH-SM4-TB_1x07-1MP_P2.00mm_Vertical +JST PH series connector, B7B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +9 +8 +Connector_JST +JST_PH_B8B-PH-K_1x08_P2.00mm_Vertical +JST PH series connector, B8B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +8 +8 +Connector_JST +JST_PH_B8B-PH-SM4-TB_1x08-1MP_P2.00mm_Vertical +JST PH series connector, B8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +10 +9 +Connector_JST +JST_PH_B9B-PH-K_1x09_P2.00mm_Vertical +JST PH series connector, B9B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +9 +9 +Connector_JST +JST_PH_B9B-PH-SM4-TB_1x09-1MP_P2.00mm_Vertical +JST PH series connector, B9B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +11 +10 +Connector_JST +JST_PH_B10B-PH-K_1x10_P2.00mm_Vertical +JST PH series connector, B10B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +10 +10 +Connector_JST +JST_PH_B10B-PH-SM4-TB_1x10-1MP_P2.00mm_Vertical +JST PH series connector, B10B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +12 +11 +Connector_JST +JST_PH_B11B-PH-K_1x11_P2.00mm_Vertical +JST PH series connector, B11B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +11 +11 +Connector_JST +JST_PH_B11B-PH-SM4-TB_1x11-1MP_P2.00mm_Vertical +JST PH series connector, B11B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +13 +12 +Connector_JST +JST_PH_B12B-PH-K_1x12_P2.00mm_Vertical +JST PH series connector, B12B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +12 +12 +Connector_JST +JST_PH_B12B-PH-SM4-TB_1x12-1MP_P2.00mm_Vertical +JST PH series connector, B12B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +14 +13 +Connector_JST +JST_PH_B13B-PH-K_1x13_P2.00mm_Vertical +JST PH series connector, B13B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +13 +13 +Connector_JST +JST_PH_B13B-PH-SM4-TB_1x13-1MP_P2.00mm_Vertical +JST PH series connector, B13B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +15 +14 +Connector_JST +JST_PH_B14B-PH-K_1x14_P2.00mm_Vertical +JST PH series connector, B14B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +14 +14 +Connector_JST +JST_PH_B14B-PH-SM4-TB_1x14-1MP_P2.00mm_Vertical +JST PH series connector, B14B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +16 +15 +Connector_JST +JST_PH_B15B-PH-K_1x15_P2.00mm_Vertical +JST PH series connector, B15B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +15 +15 +Connector_JST +JST_PH_B15B-PH-SM4-TB_1x15-1MP_P2.00mm_Vertical +JST PH series connector, B15B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +17 +16 +Connector_JST +JST_PH_B16B-PH-K_1x16_P2.00mm_Vertical +JST PH series connector, B16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +16 +16 +Connector_JST +JST_PH_B16B-PH-SM4-TB_1x16-1MP_P2.00mm_Vertical +JST PH series connector, B16B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH side entry +0 +18 +17 +Connector_JST +JST_PH_S2B-PH-K_1x02_P2.00mm_Horizontal +JST PH series connector, S2B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +2 +2 +Connector_JST +JST_PH_S2B-PH-SM4-TB_1x02-1MP_P2.00mm_Horizontal +JST PH series connector, S2B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +4 +3 +Connector_JST +JST_PH_S3B-PH-K_1x03_P2.00mm_Horizontal +JST PH series connector, S3B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +3 +3 +Connector_JST +JST_PH_S3B-PH-SM4-TB_1x03-1MP_P2.00mm_Horizontal +JST PH series connector, S3B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +5 +4 +Connector_JST +JST_PH_S4B-PH-K_1x04_P2.00mm_Horizontal +JST PH series connector, S4B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +4 +4 +Connector_JST +JST_PH_S4B-PH-SM4-TB_1x04-1MP_P2.00mm_Horizontal +JST PH series connector, S4B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +6 +5 +Connector_JST +JST_PH_S5B-PH-K_1x05_P2.00mm_Horizontal +JST PH series connector, S5B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +5 +5 +Connector_JST +JST_PH_S5B-PH-SM4-TB_1x05-1MP_P2.00mm_Horizontal +JST PH series connector, S5B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +7 +6 +Connector_JST +JST_PH_S6B-PH-K_1x06_P2.00mm_Horizontal +JST PH series connector, S6B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +6 +6 +Connector_JST +JST_PH_S6B-PH-SM4-TB_1x06-1MP_P2.00mm_Horizontal +JST PH series connector, S6B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +8 +7 +Connector_JST +JST_PH_S7B-PH-K_1x07_P2.00mm_Horizontal +JST PH series connector, S7B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +7 +7 +Connector_JST +JST_PH_S7B-PH-SM4-TB_1x07-1MP_P2.00mm_Horizontal +JST PH series connector, S7B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +9 +8 +Connector_JST +JST_PH_S8B-PH-K_1x08_P2.00mm_Horizontal +JST PH series connector, S8B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +8 +8 +Connector_JST +JST_PH_S8B-PH-SM4-TB_1x08-1MP_P2.00mm_Horizontal +JST PH series connector, S8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +10 +9 +Connector_JST +JST_PH_S9B-PH-K_1x09_P2.00mm_Horizontal +JST PH series connector, S9B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +9 +9 +Connector_JST +JST_PH_S9B-PH-SM4-TB_1x09-1MP_P2.00mm_Horizontal +JST PH series connector, S9B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +11 +10 +Connector_JST +JST_PH_S10B-PH-K_1x10_P2.00mm_Horizontal +JST PH series connector, S10B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +10 +10 +Connector_JST +JST_PH_S10B-PH-SM4-TB_1x10-1MP_P2.00mm_Horizontal +JST PH series connector, S10B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +12 +11 +Connector_JST +JST_PH_S11B-PH-K_1x11_P2.00mm_Horizontal +JST PH series connector, S11B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +11 +11 +Connector_JST +JST_PH_S11B-PH-SM4-TB_1x11-1MP_P2.00mm_Horizontal +JST PH series connector, S11B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +13 +12 +Connector_JST +JST_PH_S12B-PH-K_1x12_P2.00mm_Horizontal +JST PH series connector, S12B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +12 +12 +Connector_JST +JST_PH_S12B-PH-SM4-TB_1x12-1MP_P2.00mm_Horizontal +JST PH series connector, S12B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +14 +13 +Connector_JST +JST_PH_S13B-PH-K_1x13_P2.00mm_Horizontal +JST PH series connector, S13B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +13 +13 +Connector_JST +JST_PH_S13B-PH-SM4-TB_1x13-1MP_P2.00mm_Horizontal +JST PH series connector, S13B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +15 +14 +Connector_JST +JST_PH_S14B-PH-K_1x14_P2.00mm_Horizontal +JST PH series connector, S14B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +14 +14 +Connector_JST +JST_PH_S14B-PH-SM4-TB_1x14-1MP_P2.00mm_Horizontal +JST PH series connector, S14B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +16 +15 +Connector_JST +JST_PH_S15B-PH-K_1x15_P2.00mm_Horizontal +JST PH series connector, S15B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +15 +15 +Connector_JST +JST_PH_S15B-PH-SM4-TB_1x15-1MP_P2.00mm_Horizontal +JST PH series connector, S15B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +17 +16 +Connector_JST +JST_PH_S16B-PH-K_1x16_P2.00mm_Horizontal +JST PH series connector, S16B-PH-K (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator +connector JST PH top entry +0 +16 +16 +Connector_JST +JST_PUD_B08B-PUDSS_2x04_P2.00mm_Vertical +JST PUD series connector, B08B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +8 +8 +Connector_JST +JST_PUD_B10B-PUDSS_2x05_P2.00mm_Vertical +JST PUD series connector, B10B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +10 +10 +Connector_JST +JST_PUD_B12B-PUDSS_2x06_P2.00mm_Vertical +JST PUD series connector, B12B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +12 +12 +Connector_JST +JST_PUD_B14B-PUDSS_2x07_P2.00mm_Vertical +JST PUD series connector, B14B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +14 +14 +Connector_JST +JST_PUD_B16B-PUDSS_2x08_P2.00mm_Vertical +JST PUD series connector, B16B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +16 +16 +Connector_JST +JST_PUD_B18B-PUDSS_2x09_P2.00mm_Vertical +JST PUD series connector, B18B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +18 +18 +Connector_JST +JST_PUD_B20B-PUDSS_2x10_P2.00mm_Vertical +JST PUD series connector, B20B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +20 +20 +Connector_JST +JST_PUD_B22B-PUDSS_2x11_P2.00mm_Vertical +JST PUD series connector, B22B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +22 +22 +Connector_JST +JST_PUD_B24B-PUDSS_2x12_P2.00mm_Vertical +JST PUD series connector, B24B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +24 +24 +Connector_JST +JST_PUD_B26B-PUDSS_2x13_P2.00mm_Vertical +JST PUD series connector, B26B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +26 +26 +Connector_JST +JST_PUD_B28B-PUDSS_2x14_P2.00mm_Vertical +JST PUD series connector, B28B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +28 +28 +Connector_JST +JST_PUD_B30B-PUDSS_2x15_P2.00mm_Vertical +JST PUD series connector, B30B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +30 +30 +Connector_JST +JST_PUD_B32B-PUDSS_2x16_P2.00mm_Vertical +JST PUD series connector, B32B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +32 +32 +Connector_JST +JST_PUD_B34B-PUDSS_2x17_P2.00mm_Vertical +JST PUD series connector, B34B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +34 +34 +Connector_JST +JST_PUD_B36B-PUDSS_2x18_P2.00mm_Vertical +JST PUD series connector, B36B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +36 +36 +Connector_JST +JST_PUD_B38B-PUDSS_2x19_P2.00mm_Vertical +JST PUD series connector, B38B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +38 +38 +Connector_JST +JST_PUD_B40B-PUDSS_2x20_P2.00mm_Vertical +JST PUD series connector, B40B-PUDSS (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD side entry +0 +40 +40 +Connector_JST +JST_PUD_S08B-PUDSS-1_2x04_P2.00mm_Horizontal +JST PUD series connector, S08B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +8 +8 +Connector_JST +JST_PUD_S10B-PUDSS-1_2x05_P2.00mm_Horizontal +JST PUD series connector, S10B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +10 +10 +Connector_JST +JST_PUD_S12B-PUDSS-1_2x06_P2.00mm_Horizontal +JST PUD series connector, S12B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +12 +12 +Connector_JST +JST_PUD_S14B-PUDSS-1_2x07_P2.00mm_Horizontal +JST PUD series connector, S14B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +14 +14 +Connector_JST +JST_PUD_S16B-PUDSS-1_2x08_P2.00mm_Horizontal +JST PUD series connector, S16B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +16 +16 +Connector_JST +JST_PUD_S18B-PUDSS-1_2x09_P2.00mm_Horizontal +JST PUD series connector, S18B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +18 +18 +Connector_JST +JST_PUD_S20B-PUDSS-1_2x10_P2.00mm_Horizontal +JST PUD series connector, S20B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +20 +20 +Connector_JST +JST_PUD_S22B-PUDSS-1_2x11_P2.00mm_Horizontal +JST PUD series connector, S22B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +22 +22 +Connector_JST +JST_PUD_S24B-PUDSS-1_2x12_P2.00mm_Horizontal +JST PUD series connector, S24B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +24 +24 +Connector_JST +JST_PUD_S26B-PUDSS-1_2x13_P2.00mm_Horizontal +JST PUD series connector, S26B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +26 +26 +Connector_JST +JST_PUD_S28B-PUDSS-1_2x14_P2.00mm_Horizontal +JST PUD series connector, S28B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +28 +28 +Connector_JST +JST_PUD_S30B-PUDSS-1_2x15_P2.00mm_Horizontal +JST PUD series connector, S30B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +30 +30 +Connector_JST +JST_PUD_S32B-PUDSS-1_2x16_P2.00mm_Horizontal +JST PUD series connector, S32B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +32 +32 +Connector_JST +JST_PUD_S34B-PUDSS-1_2x17_P2.00mm_Horizontal +JST PUD series connector, S34B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +34 +34 +Connector_JST +JST_PUD_S36B-PUDSS-1_2x18_P2.00mm_Horizontal +JST PUD series connector, S36B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +36 +36 +Connector_JST +JST_PUD_S38B-PUDSS-1_2x19_P2.00mm_Horizontal +JST PUD series connector, S38B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +38 +38 +Connector_JST +JST_PUD_S40B-PUDSS-1_2x20_P2.00mm_Horizontal +JST PUD series connector, S40B-PUDSS-1 (http://www.jst-mfg.com/product/pdf/eng/ePUD.pdf), generated with kicad-footprint-generator +connector JST PUD top entry +0 +40 +40 +Connector_JST +JST_SFH_SM02B-SFHRS-TF_1x02-1MP_P4.20mm_Horizontal +JST SFH series connector, SM02B-SFHRS-TF (http://www.jst-mfg.com/product/pdf/eng/eSFH.pdf), generated with kicad-footprint-generator +connector JST SFH horizontal +0 +4 +3 +Connector_JST +JST_SHL_SM02B-SHLS-TF_1x02-1MP_P1.00mm_Horizontal +JST SHL series connector, SM02B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +4 +3 +Connector_JST +JST_SHL_SM05B-SHLS-TF_1x05-1MP_P1.00mm_Horizontal +JST SHL series connector, SM05B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +7 +6 +Connector_JST +JST_SHL_SM06B-SHLS-TF_1x06-1MP_P1.00mm_Horizontal +JST SHL series connector, SM06B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +8 +7 +Connector_JST +JST_SHL_SM07B-SHLS-TF_1x07-1MP_P1.00mm_Horizontal +JST SHL series connector, SM07B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +9 +8 +Connector_JST +JST_SHL_SM08B-SHLS-TF_1x08-1MP_P1.00mm_Horizontal +JST SHL series connector, SM08B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +10 +9 +Connector_JST +JST_SHL_SM10B-SHLS-TF_1x10-1MP_P1.00mm_Horizontal +JST SHL series connector, SM10B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +12 +11 +Connector_JST +JST_SHL_SM11B-SHLS-TF_1x11-1MP_P1.00mm_Horizontal +JST SHL series connector, SM11B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +13 +12 +Connector_JST +JST_SHL_SM12B-SHLS-TF_1x12-1MP_P1.00mm_Horizontal +JST SHL series connector, SM12B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +14 +13 +Connector_JST +JST_SHL_SM14B-SHLS-TF_1x14-1MP_P1.00mm_Horizontal +JST SHL series connector, SM14B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +16 +15 +Connector_JST +JST_SHL_SM16B-SHLS-TF_1x16-1MP_P1.00mm_Horizontal +JST SHL series connector, SM16B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +18 +17 +Connector_JST +JST_SHL_SM20B-SHLS-TF_1x20-1MP_P1.00mm_Horizontal +JST SHL series connector, SM20B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +22 +21 +Connector_JST +JST_SHL_SM22B-SHLS-TF_1x22-1MP_P1.00mm_Horizontal +JST SHL series connector, SM22B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +24 +23 +Connector_JST +JST_SHL_SM26B-SHLS-TF_1x26-1MP_P1.00mm_Horizontal +JST SHL series connector, SM26B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +28 +27 +Connector_JST +JST_SHL_SM30B-SHLS-TF_1x30-1MP_P1.00mm_Horizontal +JST SHL series connector, SM30B-SHLS-TF (http://www.jst-mfg.com/product/pdf/eng/eSHL.pdf), generated with kicad-footprint-generator +connector JST SHL top entry +0 +32 +31 +Connector_JST +JST_SH_BM02B-SRSS-TB_1x02-1MP_P1.00mm_Vertical +JST SH series connector, BM02B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +4 +3 +Connector_JST +JST_SH_BM03B-SRSS-TB_1x03-1MP_P1.00mm_Vertical +JST SH series connector, BM03B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +5 +4 +Connector_JST +JST_SH_BM04B-SRSS-TB_1x04-1MP_P1.00mm_Vertical +JST SH series connector, BM04B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +6 +5 +Connector_JST +JST_SH_BM05B-SRSS-TB_1x05-1MP_P1.00mm_Vertical +JST SH series connector, BM05B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +7 +6 +Connector_JST +JST_SH_BM06B-SRSS-TB_1x06-1MP_P1.00mm_Vertical +JST SH series connector, BM06B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +8 +7 +Connector_JST +JST_SH_BM07B-SRSS-TB_1x07-1MP_P1.00mm_Vertical +JST SH series connector, BM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +9 +8 +Connector_JST +JST_SH_BM08B-SRSS-TB_1x08-1MP_P1.00mm_Vertical +JST SH series connector, BM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +10 +9 +Connector_JST +JST_SH_BM09B-SRSS-TB_1x09-1MP_P1.00mm_Vertical +JST SH series connector, BM09B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +11 +10 +Connector_JST +JST_SH_BM10B-SRSS-TB_1x10-1MP_P1.00mm_Vertical +JST SH series connector, BM10B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +12 +11 +Connector_JST +JST_SH_BM11B-SRSS-TB_1x11-1MP_P1.00mm_Vertical +JST SH series connector, BM11B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +13 +12 +Connector_JST +JST_SH_BM12B-SRSS-TB_1x12-1MP_P1.00mm_Vertical +JST SH series connector, BM12B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +14 +13 +Connector_JST +JST_SH_BM13B-SRSS-TB_1x13-1MP_P1.00mm_Vertical +JST SH series connector, BM13B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +15 +14 +Connector_JST +JST_SH_BM14B-SRSS-TB_1x14-1MP_P1.00mm_Vertical +JST SH series connector, BM14B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +16 +15 +Connector_JST +JST_SH_BM15B-SRSS-TB_1x15-1MP_P1.00mm_Vertical +JST SH series connector, BM15B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH side entry +0 +17 +16 +Connector_JST +JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal +JST SH series connector, SM02B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +4 +3 +Connector_JST +JST_SH_SM03B-SRSS-TB_1x03-1MP_P1.00mm_Horizontal +JST SH series connector, SM03B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +5 +4 +Connector_JST +JST_SH_SM04B-SRSS-TB_1x04-1MP_P1.00mm_Horizontal +JST SH series connector, SM04B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +6 +5 +Connector_JST +JST_SH_SM05B-SRSS-TB_1x05-1MP_P1.00mm_Horizontal +JST SH series connector, SM05B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +7 +6 +Connector_JST +JST_SH_SM06B-SRSS-TB_1x06-1MP_P1.00mm_Horizontal +JST SH series connector, SM06B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +8 +7 +Connector_JST +JST_SH_SM07B-SRSS-TB_1x07-1MP_P1.00mm_Horizontal +JST SH series connector, SM07B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +9 +8 +Connector_JST +JST_SH_SM08B-SRSS-TB_1x08-1MP_P1.00mm_Horizontal +JST SH series connector, SM08B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +10 +9 +Connector_JST +JST_SH_SM09B-SRSS-TB_1x09-1MP_P1.00mm_Horizontal +JST SH series connector, SM09B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +11 +10 +Connector_JST +JST_SH_SM10B-SRSS-TB_1x10-1MP_P1.00mm_Horizontal +JST SH series connector, SM10B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +12 +11 +Connector_JST +JST_SH_SM11B-SRSS-TB_1x11-1MP_P1.00mm_Horizontal +JST SH series connector, SM11B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +13 +12 +Connector_JST +JST_SH_SM12B-SRSS-TB_1x12-1MP_P1.00mm_Horizontal +JST SH series connector, SM12B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +14 +13 +Connector_JST +JST_SH_SM13B-SRSS-TB_1x13-1MP_P1.00mm_Horizontal +JST SH series connector, SM13B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +15 +14 +Connector_JST +JST_SH_SM14B-SRSS-TB_1x14-1MP_P1.00mm_Horizontal +JST SH series connector, SM14B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +16 +15 +Connector_JST +JST_SH_SM15B-SRSS-TB_1x15-1MP_P1.00mm_Horizontal +JST SH series connector, SM15B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +17 +16 +Connector_JST +JST_SH_SM20B-SRSS-TB_1x20-1MP_P1.00mm_Horizontal +JST SH series connector, SM20B-SRSS-TB (http://www.jst-mfg.com/product/pdf/eng/eSH.pdf), generated with kicad-footprint-generator +connector JST SH top entry +0 +22 +21 +Connector_JST +JST_SUR_BM02B-SURS-TF_1x02-1MP_P0.80mm_Vertical +JST SUR series connector, BM02B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +4 +3 +Connector_JST +JST_SUR_BM03B-SURS-TF_1x03-1MP_P0.80mm_Vertical +JST SUR series connector, BM03B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +5 +4 +Connector_JST +JST_SUR_BM04B-SURS-TF_1x04-1MP_P0.80mm_Vertical +JST SUR series connector, BM04B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +6 +5 +Connector_JST +JST_SUR_BM05B-SURS-TF_1x05-1MP_P0.80mm_Vertical +JST SUR series connector, BM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +7 +6 +Connector_JST +JST_SUR_BM06B-SURS-TF_1x06-1MP_P0.80mm_Vertical +JST SUR series connector, BM06B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +8 +7 +Connector_JST +JST_SUR_BM08B-SURS-TF_1x08-1MP_P0.80mm_Vertical +JST SUR series connector, BM08B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +10 +9 +Connector_JST +JST_SUR_BM10B-SURS-TF_1x10-1MP_P0.80mm_Vertical +JST SUR series connector, BM10B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +12 +11 +Connector_JST +JST_SUR_BM12B-SURS-TF_1x12-1MP_P0.80mm_Vertical +JST SUR series connector, BM12B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +14 +13 +Connector_JST +JST_SUR_BM14B-SURS-TF_1x14-1MP_P0.80mm_Vertical +JST SUR series connector, BM14B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +16 +15 +Connector_JST +JST_SUR_BM15B-SURS-TF_1x15-1MP_P0.80mm_Vertical +JST SUR series connector, BM15B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +17 +16 +Connector_JST +JST_SUR_BM16B-SURS-TF_1x16-1MP_P0.80mm_Vertical +JST SUR series connector, BM16B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +18 +17 +Connector_JST +JST_SUR_BM17B-SURS-TF_1x17-1MP_P0.80mm_Vertical +JST SUR series connector, BM17B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +19 +18 +Connector_JST +JST_SUR_BM20B-SURS-TF_1x20-1MP_P0.80mm_Vertical +JST SUR series connector, BM20B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR side entry +0 +22 +21 +Connector_JST +JST_SUR_SM02B-SURS-TF_1x02-1MP_P0.80mm_Horizontal +JST SUR series connector, SM02B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +4 +3 +Connector_JST +JST_SUR_SM03B-SURS-TF_1x03-1MP_P0.80mm_Horizontal +JST SUR series connector, SM03B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +5 +4 +Connector_JST +JST_SUR_SM04B-SURS-TF_1x04-1MP_P0.80mm_Horizontal +JST SUR series connector, SM04B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +6 +5 +Connector_JST +JST_SUR_SM05B-SURS-TF_1x05-1MP_P0.80mm_Horizontal +JST SUR series connector, SM05B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +7 +6 +Connector_JST +JST_SUR_SM06B-SURS-TF_1x06-1MP_P0.80mm_Horizontal +JST SUR series connector, SM06B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +8 +7 +Connector_JST +JST_SUR_SM08B-SURS-TF_1x08-1MP_P0.80mm_Horizontal +JST SUR series connector, SM08B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +10 +9 +Connector_JST +JST_SUR_SM10B-SURS-TF_1x10-1MP_P0.80mm_Horizontal +JST SUR series connector, SM10B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +12 +11 +Connector_JST +JST_SUR_SM12B-SURS-TF_1x12-1MP_P0.80mm_Horizontal +JST SUR series connector, SM12B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +14 +13 +Connector_JST +JST_SUR_SM14B-SURS-TF_1x14-1MP_P0.80mm_Horizontal +JST SUR series connector, SM14B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +16 +15 +Connector_JST +JST_SUR_SM15B-SURS-TF_1x15-1MP_P0.80mm_Horizontal +JST SUR series connector, SM15B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +17 +16 +Connector_JST +JST_SUR_SM16B-SURS-TF_1x16-1MP_P0.80mm_Horizontal +JST SUR series connector, SM16B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +18 +17 +Connector_JST +JST_SUR_SM17B-SURS-TF_1x17-1MP_P0.80mm_Horizontal +JST SUR series connector, SM17B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +19 +18 +Connector_JST +JST_SUR_SM20B-SURS-TF_1x20-1MP_P0.80mm_Horizontal +JST SUR series connector, SM20B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +22 +21 +Connector_JST +JST_SUR_SM22B-SURS-TF_1x22-1MP_P0.80mm_Horizontal +JST SUR series connector, SM22B-SURS-TF (http://www.jst-mfg.com/product/pdf/eng/eSUR.pdf), generated with kicad-footprint-generator +connector JST SUR top entry +0 +24 +23 +Connector_JST +JST_VH_B2P-VH-B_1x02_P3.96mm_Vertical +JST VH PBT series connector, B2P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +2 +2 +Connector_JST +JST_VH_B2P-VH-FB-B_1x02_P3.96mm_Vertical +JST VH series connector, B2P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +2 +2 +Connector_JST +JST_VH_B2P-VH_1x02_P3.96mm_Vertical +JST VH series connector, B2P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +2 +2 +Connector_JST +JST_VH_B2P3-VH_1x02_P7.92mm_Vertical +JST VH series connector, B2P3-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +2 +2 +Connector_JST +JST_VH_B2PS-VH_1x02_P3.96mm_Horizontal +JST VH series connector, B2PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +2 +2 +Connector_JST +JST_VH_B3P-VH-B_1x03_P3.96mm_Vertical +JST VH PBT series connector, B3P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +3 +3 +Connector_JST +JST_VH_B3P-VH-FB-B_1x03_P3.96mm_Vertical +JST VH series connector, B3P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +3 +3 +Connector_JST +JST_VH_B3P-VH_1x03_P3.96mm_Vertical +JST VH series connector, B3P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +3 +3 +Connector_JST +JST_VH_B3PS-VH_1x03_P3.96mm_Horizontal +JST VH series connector, B3PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +3 +3 +Connector_JST +JST_VH_B4P-VH-B_1x04_P3.96mm_Vertical +JST VH PBT series connector, B4P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +4 +4 +Connector_JST +JST_VH_B4P-VH-FB-B_1x04_P3.96mm_Vertical +JST VH series connector, B4P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +4 +4 +Connector_JST +JST_VH_B4P-VH_1x04_P3.96mm_Vertical +JST VH series connector, B4P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +4 +4 +Connector_JST +JST_VH_B4PS-VH_1x04_P3.96mm_Horizontal +JST VH series connector, B4PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +4 +4 +Connector_JST +JST_VH_B5P-VH-B_1x05_P3.96mm_Vertical +JST VH PBT series connector, B5P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +5 +5 +Connector_JST +JST_VH_B5P-VH-FB-B_1x05_P3.96mm_Vertical +JST VH series connector, B5P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +5 +5 +Connector_JST +JST_VH_B5P-VH_1x05_P3.96mm_Vertical +JST VH series connector, B5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +5 +5 +Connector_JST +JST_VH_B5PS-VH_1x05_P3.96mm_Horizontal +JST VH series connector, B5PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +5 +5 +Connector_JST +JST_VH_B6P-VH-B_1x06_P3.96mm_Vertical +JST VH PBT series connector, B6P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +6 +6 +Connector_JST +JST_VH_B6P-VH-FB-B_1x06_P3.96mm_Vertical +JST VH series connector, B6P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +6 +6 +Connector_JST +JST_VH_B6P-VH_1x06_P3.96mm_Vertical +JST VH series connector, B6P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +6 +6 +Connector_JST +JST_VH_B6PS-VH_1x06_P3.96mm_Horizontal +JST VH series connector, B6PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +6 +6 +Connector_JST +JST_VH_B7P-VH-B_1x07_P3.96mm_Vertical +JST VH PBT series connector, B7P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +7 +7 +Connector_JST +JST_VH_B7P-VH-FB-B_1x07_P3.96mm_Vertical +JST VH series connector, B7P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +7 +7 +Connector_JST +JST_VH_B7P-VH_1x07_P3.96mm_Vertical +JST VH series connector, B7P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +7 +7 +Connector_JST +JST_VH_B7PS-VH_1x07_P3.96mm_Horizontal +JST VH series connector, B7PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +7 +7 +Connector_JST +JST_VH_B8P-VH-B_1x08_P3.96mm_Vertical +JST VH PBT series connector, B8P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +8 +8 +Connector_JST +JST_VH_B8P-VH-FB-B_1x08_P3.96mm_Vertical +JST VH series connector, B8P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +8 +8 +Connector_JST +JST_VH_B8P-VH_1x08_P3.96mm_Vertical +JST VH series connector, B8P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +8 +8 +Connector_JST +JST_VH_B8PS-VH_1x08_P3.96mm_Horizontal +JST VH series connector, B8PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +8 +8 +Connector_JST +JST_VH_B9P-VH-B_1x09_P3.96mm_Vertical +JST VH PBT series connector, B9P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +9 +9 +Connector_JST +JST_VH_B9P-VH-FB-B_1x09_P3.96mm_Vertical +JST VH series connector, B9P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +9 +9 +Connector_JST +JST_VH_B9P-VH_1x09_P3.96mm_Vertical +JST VH series connector, B9P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +9 +9 +Connector_JST +JST_VH_B9PS-VH_1x09_P3.96mm_Horizontal +JST VH series connector, B9PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +9 +9 +Connector_JST +JST_VH_B10P-VH-B_1x10_P3.96mm_Vertical +JST VH PBT series connector, B10P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +10 +10 +Connector_JST +JST_VH_B10P-VH-FB-B_1x10_P3.96mm_Vertical +JST VH series connector, B10P-VH-FB-B, shrouded (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH side entry +0 +10 +10 +Connector_JST +JST_VH_B10P-VH_1x10_P3.96mm_Vertical +JST VH series connector, B10P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +10 +10 +Connector_JST +JST_VH_B10PS-VH_1x10_P3.96mm_Horizontal +JST VH series connector, B10PS-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +10 +10 +Connector_JST +JST_VH_B11P-VH-B_1x11_P3.96mm_Vertical +JST VH PBT series connector, B11P-VH-B (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH vertical +0 +11 +11 +Connector_JST +JST_VH_S2P-VH_1x02_P3.96mm_Horizontal +JST VH series connector, S2P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +2 +2 +Connector_JST +JST_VH_S3P-VH_1x03_P3.96mm_Horizontal +JST VH series connector, S3P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +3 +3 +Connector_JST +JST_VH_S4P-VH_1x04_P3.96mm_Horizontal +JST VH series connector, S4P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +4 +4 +Connector_JST +JST_VH_S5P-VH_1x05_P3.96mm_Horizontal +JST VH series connector, S5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +5 +5 +Connector_JST +JST_VH_S6P-VH_1x06_P3.96mm_Horizontal +JST VH series connector, S6P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +6 +6 +Connector_JST +JST_VH_S7P-VH_1x07_P3.96mm_Horizontal +JST VH series connector, S7P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator +connector JST VH top entry +0 +7 +7 +Connector_JST +JST_XAG_SM05B-XAGKS-BN-TB_1x05-1MP_P2.50mm_Horizontal +JST XAG series connector, SM05B-XAGKS-BN-TB (http://www.jst-mfg.com/product/pdf/eng/eXAG.pdf), generated with kicad-footprint-generator +connector JST XAG top entry +0 +7 +6 +Connector_JST +JST_XH_B1B-XH-AM_1x01_P2.50mm_Vertical +JST XH series connector, B1B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +1 +1 +Connector_JST +JST_XH_B2B-XH-AM_1x02_P2.50mm_Vertical +JST XH series connector, B2B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +2 +2 +Connector_JST +JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical +JST XH series connector, B2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +2 +2 +Connector_JST +JST_XH_B3B-XH-AM_1x03_P2.50mm_Vertical +JST XH series connector, B3B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +3 +3 +Connector_JST +JST_XH_B3B-XH-A_1x03_P2.50mm_Vertical +JST XH series connector, B3B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +3 +3 +Connector_JST +JST_XH_B4B-XH-AM_1x04_P2.50mm_Vertical +JST XH series connector, B4B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +4 +4 +Connector_JST +JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical +JST XH series connector, B4B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +4 +4 +Connector_JST +JST_XH_B5B-XH-AM_1x05_P2.50mm_Vertical +JST XH series connector, B5B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +5 +5 +Connector_JST +JST_XH_B5B-XH-A_1x05_P2.50mm_Vertical +JST XH series connector, B5B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +5 +5 +Connector_JST +JST_XH_B6B-XH-AM_1x06_P2.50mm_Vertical +JST XH series connector, B6B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +6 +6 +Connector_JST +JST_XH_B6B-XH-A_1x06_P2.50mm_Vertical +JST XH series connector, B6B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +6 +6 +Connector_JST +JST_XH_B7B-XH-AM_1x07_P2.50mm_Vertical +JST XH series connector, B7B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +7 +7 +Connector_JST +JST_XH_B7B-XH-A_1x07_P2.50mm_Vertical +JST XH series connector, B7B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +7 +7 +Connector_JST +JST_XH_B8B-XH-AM_1x08_P2.50mm_Vertical +JST XH series connector, B8B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +8 +8 +Connector_JST +JST_XH_B8B-XH-A_1x08_P2.50mm_Vertical +JST XH series connector, B8B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +8 +8 +Connector_JST +JST_XH_B9B-XH-AM_1x09_P2.50mm_Vertical +JST XH series connector, B9B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical boss +0 +9 +9 +Connector_JST +JST_XH_B9B-XH-A_1x09_P2.50mm_Vertical +JST XH series connector, B9B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH vertical +0 +9 +9 +Connector_JST +JST_XH_B10B-XH-AM_1x10_P2.50mm_Vertical +JST XH series connector, B10B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry boss +0 +10 +10 +Connector_JST +JST_XH_B10B-XH-A_1x10_P2.50mm_Vertical +JST XH series connector, B10B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +10 +10 +Connector_JST +JST_XH_B11B-XH-A_1x11_P2.50mm_Vertical +JST XH series connector, B11B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +11 +11 +Connector_JST +JST_XH_B12B-XH-AM_1x12_P2.50mm_Vertical +JST XH series connector, B12B-XH-AM, with boss (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry boss +0 +12 +12 +Connector_JST +JST_XH_B12B-XH-A_1x12_P2.50mm_Vertical +JST XH series connector, B12B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +12 +12 +Connector_JST +JST_XH_B13B-XH-A_1x13_P2.50mm_Vertical +JST XH series connector, B13B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +13 +13 +Connector_JST +JST_XH_B14B-XH-A_1x14_P2.50mm_Vertical +JST XH series connector, B14B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +14 +14 +Connector_JST +JST_XH_B15B-XH-A_1x15_P2.50mm_Vertical +JST XH series connector, B15B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +15 +15 +Connector_JST +JST_XH_B16B-XH-A_1x16_P2.50mm_Vertical +JST XH series connector, B16B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +16 +16 +Connector_JST +JST_XH_B20B-XH-A_1x20_P2.50mm_Vertical +JST XH series connector, B20B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH side entry +0 +20 +20 +Connector_JST +JST_XH_S2B-XH-A-1_1x02_P2.50mm_Horizontal +JST XH series connector, S2B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +2 +2 +Connector_JST +JST_XH_S2B-XH-A_1x02_P2.50mm_Horizontal +JST XH series connector, S2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +2 +2 +Connector_JST +JST_XH_S3B-XH-A-1_1x03_P2.50mm_Horizontal +JST XH series connector, S3B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +3 +3 +Connector_JST +JST_XH_S3B-XH-A_1x03_P2.50mm_Horizontal +JST XH series connector, S3B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +3 +3 +Connector_JST +JST_XH_S4B-XH-A-1_1x04_P2.50mm_Horizontal +JST XH series connector, S4B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +4 +4 +Connector_JST +JST_XH_S4B-XH-A_1x04_P2.50mm_Horizontal +JST XH series connector, S4B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +4 +4 +Connector_JST +JST_XH_S5B-XH-A-1_1x05_P2.50mm_Horizontal +JST XH series connector, S5B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +5 +5 +Connector_JST +JST_XH_S5B-XH-A_1x05_P2.50mm_Horizontal +JST XH series connector, S5B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +5 +5 +Connector_JST +JST_XH_S6B-XH-A-1_1x06_P2.50mm_Horizontal +JST XH series connector, S6B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +6 +6 +Connector_JST +JST_XH_S6B-XH-A_1x06_P2.50mm_Horizontal +JST XH series connector, S6B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +6 +6 +Connector_JST +JST_XH_S7B-XH-A-1_1x07_P2.50mm_Horizontal +JST XH series connector, S7B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +7 +7 +Connector_JST +JST_XH_S7B-XH-A_1x07_P2.50mm_Horizontal +JST XH series connector, S7B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +7 +7 +Connector_JST +JST_XH_S8B-XH-A-1_1x08_P2.50mm_Horizontal +JST XH series connector, S8B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +8 +8 +Connector_JST +JST_XH_S8B-XH-A_1x08_P2.50mm_Horizontal +JST XH series connector, S8B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +8 +8 +Connector_JST +JST_XH_S9B-XH-A-1_1x09_P2.50mm_Horizontal +JST XH series connector, S9B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +9 +9 +Connector_JST +JST_XH_S9B-XH-A_1x09_P2.50mm_Horizontal +JST XH series connector, S9B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH horizontal +0 +9 +9 +Connector_JST +JST_XH_S10B-XH-A-1_1x10_P2.50mm_Horizontal +JST XH series connector, S10B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +10 +10 +Connector_JST +JST_XH_S10B-XH-A_1x10_P2.50mm_Horizontal +JST XH series connector, S10B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +10 +10 +Connector_JST +JST_XH_S11B-XH-A-1_1x11_P2.50mm_Horizontal +JST XH series connector, S11B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +11 +11 +Connector_JST +JST_XH_S11B-XH-A_1x11_P2.50mm_Horizontal +JST XH series connector, S11B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +11 +11 +Connector_JST +JST_XH_S12B-XH-A-1_1x12_P2.50mm_Horizontal +JST XH series connector, S12B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +12 +12 +Connector_JST +JST_XH_S12B-XH-A_1x12_P2.50mm_Horizontal +JST XH series connector, S12B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +12 +12 +Connector_JST +JST_XH_S13B-XH-A-1_1x13_P2.50mm_Horizontal +JST XH series connector, S13B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +13 +13 +Connector_JST +JST_XH_S13B-XH-A_1x13_P2.50mm_Horizontal +JST XH series connector, S13B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +13 +13 +Connector_JST +JST_XH_S14B-XH-A-1_1x14_P2.50mm_Horizontal +JST XH series connector, S14B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +14 +14 +Connector_JST +JST_XH_S14B-XH-A_1x14_P2.50mm_Horizontal +JST XH series connector, S14B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +14 +14 +Connector_JST +JST_XH_S15B-XH-A-1_1x15_P2.50mm_Horizontal +JST XH series connector, S15B-XH-A-1 (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +15 +15 +Connector_JST +JST_XH_S15B-XH-A_1x15_P2.50mm_Horizontal +JST XH series connector, S15B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +15 +15 +Connector_JST +JST_XH_S16B-XH-A_1x16_P2.50mm_Horizontal +JST XH series connector, S16B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator +connector JST XH top entry +0 +16 +16 +Connector_JST +JST_ZE_B02B-ZESK-1D_1x02_P1.50mm_Vertical +JST ZE series connector, B02B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +2 +2 +Connector_JST +JST_ZE_B03B-ZESK-1D_1x03_P1.50mm_Vertical +JST ZE series connector, B03B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +3 +3 +Connector_JST +JST_ZE_B03B-ZESK-D_1x03_P1.50mm_Vertical +JST ZE series connector, B03B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +3 +3 +Connector_JST +JST_ZE_B04B-ZESK-1D_1x04_P1.50mm_Vertical +JST ZE series connector, B04B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +4 +4 +Connector_JST +JST_ZE_B04B-ZESK-D_1x04_P1.50mm_Vertical +JST ZE series connector, B04B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +4 +4 +Connector_JST +JST_ZE_B05B-ZESK-1D_1x05_P1.50mm_Vertical +JST ZE series connector, B05B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +5 +5 +Connector_JST +JST_ZE_B05B-ZESK-D_1x05_P1.50mm_Vertical +JST ZE series connector, B05B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +5 +5 +Connector_JST +JST_ZE_B06B-ZESK-1D_1x06_P1.50mm_Vertical +JST ZE series connector, B06B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +6 +6 +Connector_JST +JST_ZE_B06B-ZESK-D_1x06_P1.50mm_Vertical +JST ZE series connector, B06B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +6 +6 +Connector_JST +JST_ZE_B07B-ZESK-1D_1x07_P1.50mm_Vertical +JST ZE series connector, B07B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +7 +7 +Connector_JST +JST_ZE_B07B-ZESK-D_1x07_P1.50mm_Vertical +JST ZE series connector, B07B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +7 +7 +Connector_JST +JST_ZE_B08B-ZESK-1D_1x08_P1.50mm_Vertical +JST ZE series connector, B08B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +8 +8 +Connector_JST +JST_ZE_B08B-ZESK-D_1x08_P1.50mm_Vertical +JST ZE series connector, B08B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +8 +8 +Connector_JST +JST_ZE_B09B-ZESK-1D_1x09_P1.50mm_Vertical +JST ZE series connector, B09B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +9 +9 +Connector_JST +JST_ZE_B09B-ZESK-D_1x09_P1.50mm_Vertical +JST ZE series connector, B09B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +9 +9 +Connector_JST +JST_ZE_B10B-ZESK-1D_1x10_P1.50mm_Vertical +JST ZE series connector, B10B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +10 +10 +Connector_JST +JST_ZE_B10B-ZESK-D_1x10_P1.50mm_Vertical +JST ZE series connector, B10B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +10 +10 +Connector_JST +JST_ZE_B11B-ZESK-1D_1x11_P1.50mm_Vertical +JST ZE series connector, B11B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +11 +11 +Connector_JST +JST_ZE_B11B-ZESK-D_1x11_P1.50mm_Vertical +JST ZE series connector, B11B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +11 +11 +Connector_JST +JST_ZE_B12B-ZESK-1D_1x12_P1.50mm_Vertical +JST ZE series connector, B12B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +12 +12 +Connector_JST +JST_ZE_B12B-ZESK-D_1x12_P1.50mm_Vertical +JST ZE series connector, B12B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +12 +12 +Connector_JST +JST_ZE_B13B-ZESK-1D_1x13_P1.50mm_Vertical +JST ZE series connector, B13B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +13 +13 +Connector_JST +JST_ZE_B13B-ZESK-D_1x13_P1.50mm_Vertical +JST ZE series connector, B13B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +13 +13 +Connector_JST +JST_ZE_B14B-ZESK-1D_1x14_P1.50mm_Vertical +JST ZE series connector, B14B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +14 +14 +Connector_JST +JST_ZE_B14B-ZESK-D_1x14_P1.50mm_Vertical +JST ZE series connector, B14B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +14 +14 +Connector_JST +JST_ZE_B15B-ZESK-1D_1x15_P1.50mm_Vertical +JST ZE series connector, B15B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +15 +15 +Connector_JST +JST_ZE_B15B-ZESK-D_1x15_P1.50mm_Vertical +JST ZE series connector, B15B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +15 +15 +Connector_JST +JST_ZE_B16B-ZESK-1D_1x16_P1.50mm_Vertical +JST ZE series connector, B16B-ZESK-1D, with boss (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry boss +0 +16 +16 +Connector_JST +JST_ZE_B16B-ZESK-D_1x16_P1.50mm_Vertical +JST ZE series connector, B16B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE side entry +0 +16 +16 +Connector_JST +JST_ZE_BM02B-ZESS-TBT_1x02-1MP_P1.50mm_Vertical +JST ZE series connector, BM02B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +4 +3 +Connector_JST +JST_ZE_BM03B-ZESS-TBT_1x03-1MP_P1.50mm_Vertical +JST ZE series connector, BM03B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +5 +4 +Connector_JST +JST_ZE_BM04B-ZESS-TBT_1x04-1MP_P1.50mm_Vertical +JST ZE series connector, BM04B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +6 +5 +Connector_JST +JST_ZE_BM05B-ZESS-TBT_1x05-1MP_P1.50mm_Vertical +JST ZE series connector, BM05B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +7 +6 +Connector_JST +JST_ZE_BM06B-ZESS-TBT_1x06-1MP_P1.50mm_Vertical +JST ZE series connector, BM06B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +8 +7 +Connector_JST +JST_ZE_BM07B-ZESS-TBT_1x07-1MP_P1.50mm_Vertical +JST ZE series connector, BM07B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +9 +8 +Connector_JST +JST_ZE_BM08B-ZESS-TBT_1x08-1MP_P1.50mm_Vertical +JST ZE series connector, BM08B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +10 +9 +Connector_JST +JST_ZE_BM09B-ZESS-TBT_1x09-1MP_P1.50mm_Vertical +JST ZE series connector, BM09B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +11 +10 +Connector_JST +JST_ZE_BM10B-ZESS-TBT_1x10-1MP_P1.50mm_Vertical +JST ZE series connector, BM10B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +12 +11 +Connector_JST +JST_ZE_BM11B-ZESS-TBT_1x11-1MP_P1.50mm_Vertical +JST ZE series connector, BM11B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +13 +12 +Connector_JST +JST_ZE_BM12B-ZESS-TBT_1x12-1MP_P1.50mm_Vertical +JST ZE series connector, BM12B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +14 +13 +Connector_JST +JST_ZE_BM13B-ZESS-TBT_1x13-1MP_P1.50mm_Vertical +JST ZE series connector, BM13B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +15 +14 +Connector_JST +JST_ZE_BM14B-ZESS-TBT_1x14-1MP_P1.50mm_Vertical +JST ZE series connector, BM14B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +16 +15 +Connector_JST +JST_ZE_BM15B-ZESS-TBT_1x15-1MP_P1.50mm_Vertical +JST ZE series connector, BM15B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +17 +16 +Connector_JST +JST_ZE_BM16B-ZESS-TBT_1x16-1MP_P1.50mm_Vertical +JST ZE series connector, BM16B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE vertical +0 +18 +17 +Connector_JST +JST_ZE_S02B-ZESK-2D_1x02_P1.50mm_Horizontal +JST ZE series connector, S02B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +2 +2 +Connector_JST +JST_ZE_S03B-ZESK-2D_1x03_P1.50mm_Horizontal +JST ZE series connector, S03B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +3 +3 +Connector_JST +JST_ZE_S04B-ZESK-2D_1x04_P1.50mm_Horizontal +JST ZE series connector, S04B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +4 +4 +Connector_JST +JST_ZE_S05B-ZESK-2D_1x05_P1.50mm_Horizontal +JST ZE series connector, S05B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +5 +5 +Connector_JST +JST_ZE_S06B-ZESK-2D_1x06_P1.50mm_Horizontal +JST ZE series connector, S06B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +6 +6 +Connector_JST +JST_ZE_S07B-ZESK-2D_1x07_P1.50mm_Horizontal +JST ZE series connector, S07B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +7 +7 +Connector_JST +JST_ZE_S08B-ZESK-2D_1x08_P1.50mm_Horizontal +JST ZE series connector, S08B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +8 +8 +Connector_JST +JST_ZE_S09B-ZESK-2D_1x09_P1.50mm_Horizontal +JST ZE series connector, S09B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +9 +9 +Connector_JST +JST_ZE_S10B-ZESK-2D_1x10_P1.50mm_Horizontal +JST ZE series connector, S10B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +10 +10 +Connector_JST +JST_ZE_S11B-ZESK-2D_1x11_P1.50mm_Horizontal +JST ZE series connector, S11B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +11 +11 +Connector_JST +JST_ZE_S12B-ZESK-2D_1x12_P1.50mm_Horizontal +JST ZE series connector, S12B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +12 +12 +Connector_JST +JST_ZE_S13B-ZESK-2D_1x13_P1.50mm_Horizontal +JST ZE series connector, S13B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +13 +13 +Connector_JST +JST_ZE_S14B-ZESK-2D_1x14_P1.50mm_Horizontal +JST ZE series connector, S14B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +14 +14 +Connector_JST +JST_ZE_S15B-ZESK-2D_1x15_P1.50mm_Horizontal +JST ZE series connector, S15B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +15 +15 +Connector_JST +JST_ZE_S16B-ZESK-2D_1x16_P1.50mm_Horizontal +JST ZE series connector, S16B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE top entry +0 +16 +16 +Connector_JST +JST_ZE_SM02B-ZESS-TB_1x02-1MP_P1.50mm_Horizontal +JST ZE series connector, SM02B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +4 +3 +Connector_JST +JST_ZE_SM03B-ZESS-TB_1x03-1MP_P1.50mm_Horizontal +JST ZE series connector, SM03B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +5 +4 +Connector_JST +JST_ZE_SM04B-ZESS-TB_1x04-1MP_P1.50mm_Horizontal +JST ZE series connector, SM04B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +6 +5 +Connector_JST +JST_ZE_SM05B-ZESS-TB_1x05-1MP_P1.50mm_Horizontal +JST ZE series connector, SM05B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +7 +6 +Connector_JST +JST_ZE_SM06B-ZESS-TB_1x06-1MP_P1.50mm_Horizontal +JST ZE series connector, SM06B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +8 +7 +Connector_JST +JST_ZE_SM07B-ZESS-TB_1x07-1MP_P1.50mm_Horizontal +JST ZE series connector, SM07B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +9 +8 +Connector_JST +JST_ZE_SM08B-ZESS-TB_1x08-1MP_P1.50mm_Horizontal +JST ZE series connector, SM08B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +10 +9 +Connector_JST +JST_ZE_SM09B-ZESS-TB_1x09-1MP_P1.50mm_Horizontal +JST ZE series connector, SM09B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +11 +10 +Connector_JST +JST_ZE_SM10B-ZESS-TB_1x10-1MP_P1.50mm_Horizontal +JST ZE series connector, SM10B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +12 +11 +Connector_JST +JST_ZE_SM11B-ZESS-TB_1x11-1MP_P1.50mm_Horizontal +JST ZE series connector, SM11B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +13 +12 +Connector_JST +JST_ZE_SM12B-ZESS-TB_1x12-1MP_P1.50mm_Horizontal +JST ZE series connector, SM12B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +14 +13 +Connector_JST +JST_ZE_SM13B-ZESS-TB_1x13-1MP_P1.50mm_Horizontal +JST ZE series connector, SM13B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +15 +14 +Connector_JST +JST_ZE_SM14B-ZESS-TB_1x14-1MP_P1.50mm_Horizontal +JST ZE series connector, SM14B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +16 +15 +Connector_JST +JST_ZE_SM15B-ZESS-TB_1x15-1MP_P1.50mm_Horizontal +JST ZE series connector, SM15B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +17 +16 +Connector_JST +JST_ZE_SM16B-ZESS-TB_1x16-1MP_P1.50mm_Horizontal +JST ZE series connector, SM16B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator +connector JST ZE horizontal +0 +18 +17 +Connector_Molex +Molex_CLIK-Mate_502382-0270_1x02-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0270 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +4 +3 +Connector_Molex +Molex_CLIK-Mate_502382-0370_1x03-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0370 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +5 +4 +Connector_Molex +Molex_CLIK-Mate_502382-0470_1x04-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0470 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +6 +5 +Connector_Molex +Molex_CLIK-Mate_502382-0570_1x05-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0570 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +7 +6 +Connector_Molex +Molex_CLIK-Mate_502382-0670_1x06-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0670 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +8 +7 +Connector_Molex +Molex_CLIK-Mate_502382-0770_1x07-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0770 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +9 +8 +Connector_Molex +Molex_CLIK-Mate_502382-0870_1x08-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0870 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +10 +9 +Connector_Molex +Molex_CLIK-Mate_502382-0970_1x09-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-0970 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +11 +10 +Connector_Molex +Molex_CLIK-Mate_502382-1070_1x10-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-1070 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +12 +11 +Connector_Molex +Molex_CLIK-Mate_502382-1170_1x11-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-1170 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +13 +12 +Connector_Molex +Molex_CLIK-Mate_502382-1270_1x12-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-1270 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +14 +13 +Connector_Molex +Molex_CLIK-Mate_502382-1370_1x13-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-1370 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +15 +14 +Connector_Molex +Molex_CLIK-Mate_502382-1470_1x14-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-1470 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +16 +15 +Connector_Molex +Molex_CLIK-Mate_502382-1570_1x15-1MP_P1.25mm_Vertical +Molex CLIK-Mate series connector, 502382-1570 (http://www.molex.com/pdm_docs/sd/5023820270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +17 +16 +Connector_Molex +Molex_CLIK-Mate_502386-0270_1x02-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0270 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +4 +3 +Connector_Molex +Molex_CLIK-Mate_502386-0370_1x03-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +5 +4 +Connector_Molex +Molex_CLIK-Mate_502386-0470_1x04-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0470 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +6 +5 +Connector_Molex +Molex_CLIK-Mate_502386-0570_1x05-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0570 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +7 +6 +Connector_Molex +Molex_CLIK-Mate_502386-0670_1x06-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0670 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +8 +7 +Connector_Molex +Molex_CLIK-Mate_502386-0770_1x07-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0770 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +9 +8 +Connector_Molex +Molex_CLIK-Mate_502386-0870_1x08-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0870 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +10 +9 +Connector_Molex +Molex_CLIK-Mate_502386-0970_1x09-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-0970 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +11 +10 +Connector_Molex +Molex_CLIK-Mate_502386-1070_1x10-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-1070 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +12 +11 +Connector_Molex +Molex_CLIK-Mate_502386-1170_1x11-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-1170 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +13 +12 +Connector_Molex +Molex_CLIK-Mate_502386-1270_1x12-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-1270 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +14 +13 +Connector_Molex +Molex_CLIK-Mate_502386-1370_1x13-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-1370 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +15 +14 +Connector_Molex +Molex_CLIK-Mate_502386-1470_1x14-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-1470 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +16 +15 +Connector_Molex +Molex_CLIK-Mate_502386-1570_1x15-1MP_P1.25mm_Horizontal +Molex CLIK-Mate series connector, 502386-1570 (http://www.molex.com/pdm_docs/sd/5023860270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +17 +16 +Connector_Molex +Molex_CLIK-Mate_502443-0270_1x02-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0270 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +4 +3 +Connector_Molex +Molex_CLIK-Mate_502443-0370_1x03-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0370 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +5 +4 +Connector_Molex +Molex_CLIK-Mate_502443-0470_1x04-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0470 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +6 +5 +Connector_Molex +Molex_CLIK-Mate_502443-0570_1x05-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0570 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +7 +6 +Connector_Molex +Molex_CLIK-Mate_502443-0670_1x06-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0670 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +8 +7 +Connector_Molex +Molex_CLIK-Mate_502443-0770_1x07-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0770 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +9 +8 +Connector_Molex +Molex_CLIK-Mate_502443-0870_1x08-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0870 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +10 +9 +Connector_Molex +Molex_CLIK-Mate_502443-0970_1x09-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-0970 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +11 +10 +Connector_Molex +Molex_CLIK-Mate_502443-1270_1x12-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-1270 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +14 +13 +Connector_Molex +Molex_CLIK-Mate_502443-1370_1x13-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-1370 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +15 +14 +Connector_Molex +Molex_CLIK-Mate_502443-1470_1x14-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-1470 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +16 +15 +Connector_Molex +Molex_CLIK-Mate_502443-1570_1x15-1MP_P2.00mm_Vertical +Molex CLIK-Mate series connector, 502443-1570 (http://www.molex.com/pdm_docs/sd/5024430270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +17 +16 +Connector_Molex +Molex_CLIK-Mate_502494-0270_1x02-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-0270 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +4 +3 +Connector_Molex +Molex_CLIK-Mate_502494-0370_1x03-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-0370 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +5 +4 +Connector_Molex +Molex_CLIK-Mate_502494-0470_1x04-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-0470 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +6 +5 +Connector_Molex +Molex_CLIK-Mate_502494-0670_1x06-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-0670 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +8 +7 +Connector_Molex +Molex_CLIK-Mate_502494-0870_1x08-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-0870 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +10 +9 +Connector_Molex +Molex_CLIK-Mate_502494-1070_1x10-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-1070 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +12 +11 +Connector_Molex +Molex_CLIK-Mate_502494-1270_1x12-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-1270 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +14 +13 +Connector_Molex +Molex_CLIK-Mate_502494-1370_1x13-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-1370 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +15 +14 +Connector_Molex +Molex_CLIK-Mate_502494-1470_1x14-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-1470 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +16 +15 +Connector_Molex +Molex_CLIK-Mate_502494-1570_1x15-1MP_P2.00mm_Horizontal +Molex CLIK-Mate series connector, 502494-1570 (http://www.molex.com/pdm_docs/sd/5024940270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +17 +16 +Connector_Molex +Molex_CLIK-Mate_502585-0270_1x02-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0270 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +4 +3 +Connector_Molex +Molex_CLIK-Mate_502585-0370_1x03-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0370 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +5 +4 +Connector_Molex +Molex_CLIK-Mate_502585-0470_1x04-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0470 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +6 +5 +Connector_Molex +Molex_CLIK-Mate_502585-0570_1x05-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0570 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +7 +6 +Connector_Molex +Molex_CLIK-Mate_502585-0670_1x06-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0670 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +8 +7 +Connector_Molex +Molex_CLIK-Mate_502585-0770_1x07-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0770 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +9 +8 +Connector_Molex +Molex_CLIK-Mate_502585-0870_1x08-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0870 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +10 +9 +Connector_Molex +Molex_CLIK-Mate_502585-0970_1x09-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-0970 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +11 +10 +Connector_Molex +Molex_CLIK-Mate_502585-1070_1x10-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-1070 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +12 +11 +Connector_Molex +Molex_CLIK-Mate_502585-1170_1x11-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-1170 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +13 +12 +Connector_Molex +Molex_CLIK-Mate_502585-1270_1x12-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-1270 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +14 +13 +Connector_Molex +Molex_CLIK-Mate_502585-1370_1x13-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-1370 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +15 +14 +Connector_Molex +Molex_CLIK-Mate_502585-1470_1x14-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-1470 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +16 +15 +Connector_Molex +Molex_CLIK-Mate_502585-1570_1x15-1MP_P1.50mm_Horizontal +Molex CLIK-Mate series connector, 502585-1570 (http://www.molex.com/pdm_docs/sd/5025850270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate top entry +0 +17 +16 +Connector_Molex +Molex_CLIK-Mate_505405-0270_1x02-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0270 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +4 +3 +Connector_Molex +Molex_CLIK-Mate_505405-0370_1x03-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0370 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +5 +4 +Connector_Molex +Molex_CLIK-Mate_505405-0470_1x04-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0470 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +6 +5 +Connector_Molex +Molex_CLIK-Mate_505405-0570_1x05-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0570 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +7 +6 +Connector_Molex +Molex_CLIK-Mate_505405-0670_1x06-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0670 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +8 +7 +Connector_Molex +Molex_CLIK-Mate_505405-0770_1x07-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0770 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +9 +8 +Connector_Molex +Molex_CLIK-Mate_505405-0870_1x08-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0870 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +10 +9 +Connector_Molex +Molex_CLIK-Mate_505405-0970_1x09-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-0970 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +11 +10 +Connector_Molex +Molex_CLIK-Mate_505405-1070_1x10-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-1070 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +12 +11 +Connector_Molex +Molex_CLIK-Mate_505405-1170_1x11-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-1170 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +13 +12 +Connector_Molex +Molex_CLIK-Mate_505405-1270_1x12-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-1270 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +14 +13 +Connector_Molex +Molex_CLIK-Mate_505405-1370_1x13-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-1370 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +15 +14 +Connector_Molex +Molex_CLIK-Mate_505405-1470_1x14-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-1470 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +16 +15 +Connector_Molex +Molex_CLIK-Mate_505405-1570_1x15-1MP_P1.50mm_Vertical +Molex CLIK-Mate series connector, 505405-1570 (http://www.molex.com/pdm_docs/sd/5054050270_sd.pdf), generated with kicad-footprint-generator +connector Molex CLIK-Mate side entry +0 +17 +16 +Connector_Molex +Molex_KK-254_AE-6410-02A_1x02_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-02A example for new part number: 22-27-2021, 2 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +2 +2 +Connector_Molex +Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-03A example for new part number: 22-27-2031, 3 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +3 +3 +Connector_Molex +Molex_KK-254_AE-6410-04A_1x04_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-04A example for new part number: 22-27-2041, 4 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +4 +4 +Connector_Molex +Molex_KK-254_AE-6410-05A_1x05_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-05A example for new part number: 22-27-2051, 5 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +5 +5 +Connector_Molex +Molex_KK-254_AE-6410-06A_1x06_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-06A example for new part number: 22-27-2061, 6 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +6 +6 +Connector_Molex +Molex_KK-254_AE-6410-07A_1x07_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-07A example for new part number: 22-27-2071, 7 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +7 +7 +Connector_Molex +Molex_KK-254_AE-6410-08A_1x08_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-08A example for new part number: 22-27-2081, 8 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +8 +8 +Connector_Molex +Molex_KK-254_AE-6410-09A_1x09_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-09A example for new part number: 22-27-2091, 9 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +9 +9 +Connector_Molex +Molex_KK-254_AE-6410-10A_1x10_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-10A example for new part number: 22-27-2101, 10 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +10 +10 +Connector_Molex +Molex_KK-254_AE-6410-11A_1x11_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-11A example for new part number: 22-27-2111, 11 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +11 +11 +Connector_Molex +Molex_KK-254_AE-6410-12A_1x12_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-12A example for new part number: 22-27-2121, 12 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +12 +12 +Connector_Molex +Molex_KK-254_AE-6410-13A_1x13_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-13A example for new part number: 22-27-2131, 13 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +13 +13 +Connector_Molex +Molex_KK-254_AE-6410-14A_1x14_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-14A example for new part number: 22-27-2141, 14 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +14 +14 +Connector_Molex +Molex_KK-254_AE-6410-15A_1x15_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-15A example for new part number: 22-27-2151, 15 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +15 +15 +Connector_Molex +Molex_KK-254_AE-6410-16A_1x16_P2.54mm_Vertical +Molex KK-254 Interconnect System, old/engineering part number: AE-6410-16A example for new part number: 22-27-2161, 16 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-254 side entry +0 +16 +16 +Connector_Molex +Molex_KK-396_A-41791-0002_1x02_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0002 example for new part number: 26-60-4020, 2 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +2 +2 +Connector_Molex +Molex_KK-396_A-41791-0003_1x03_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0003 example for new part number: 26-60-4030, 3 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +3 +3 +Connector_Molex +Molex_KK-396_A-41791-0004_1x04_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0004 example for new part number: 26-60-4040, 4 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +4 +4 +Connector_Molex +Molex_KK-396_A-41791-0005_1x05_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0005 example for new part number: 26-60-4050, 5 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +5 +5 +Connector_Molex +Molex_KK-396_A-41791-0006_1x06_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0006 example for new part number: 26-60-4060, 6 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +6 +6 +Connector_Molex +Molex_KK-396_A-41791-0007_1x07_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0007 example for new part number: 26-60-4070, 7 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +7 +7 +Connector_Molex +Molex_KK-396_A-41791-0008_1x08_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0008 example for new part number: 26-60-4080, 8 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +8 +8 +Connector_Molex +Molex_KK-396_A-41791-0009_1x09_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0009 example for new part number: 26-60-4090, 9 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +9 +9 +Connector_Molex +Molex_KK-396_A-41791-0010_1x10_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0010 example for new part number: 26-60-4100, 10 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +10 +10 +Connector_Molex +Molex_KK-396_A-41791-0011_1x11_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0011 example for new part number: 26-60-4110, 11 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +11 +11 +Connector_Molex +Molex_KK-396_A-41791-0012_1x12_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0012 example for new part number: 26-60-4120, 12 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +12 +12 +Connector_Molex +Molex_KK-396_A-41791-0013_1x13_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0013 example for new part number: 26-60-4130, 13 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +13 +13 +Connector_Molex +Molex_KK-396_A-41791-0014_1x14_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0014 example for new part number: 26-60-4140, 14 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +14 +14 +Connector_Molex +Molex_KK-396_A-41791-0015_1x15_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0015 example for new part number: 26-60-4150, 15 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +15 +15 +Connector_Molex +Molex_KK-396_A-41791-0016_1x16_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0016 example for new part number: 26-60-4160, 16 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +16 +16 +Connector_Molex +Molex_KK-396_A-41791-0017_1x17_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0017 example for new part number: 26-60-4170, 17 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +17 +17 +Connector_Molex +Molex_KK-396_A-41791-0018_1x18_P3.96mm_Vertical +Molex KK 396 Interconnect System, old/engineering part number: A-41791-0018 example for new part number: 26-60-4180, 18 Pins (https://www.molex.com/pdm_docs/sd/026604020_sd.pdf), generated with kicad-footprint-generator +connector Molex KK-396 vertical +0 +18 +18 +Connector_Molex +Molex_Mega-Fit_76825-0002_2x01_P5.70mm_Horizontal +Molex Mega-Fit Power Connectors, 76825-0002 (compatible alternatives: 172064-0002, 172064-1002), 1 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit top entry +0 +2 +2 +Connector_Molex +Molex_Mega-Fit_76825-0004_2x02_P5.70mm_Horizontal +Molex Mega-Fit Power Connectors, 76825-0004 (compatible alternatives: 172064-0004, 172064-1004), 2 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit top entry +0 +4 +4 +Connector_Molex +Molex_Mega-Fit_76825-0006_2x03_P5.70mm_Horizontal +Molex Mega-Fit Power Connectors, 76825-0006 (compatible alternatives: 172064-0006, 172064-1006), 3 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit top entry +0 +6 +6 +Connector_Molex +Molex_Mega-Fit_76825-0008_2x04_P5.70mm_Horizontal +Molex Mega-Fit Power Connectors, 76825-0008 (compatible alternatives: 172064-0008, 172064-1008), 4 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit top entry +0 +8 +8 +Connector_Molex +Molex_Mega-Fit_76825-0010_2x05_P5.70mm_Horizontal +Molex Mega-Fit Power Connectors, 76825-0010 (compatible alternatives: 172064-0010, 172064-1010), 5 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit top entry +0 +10 +10 +Connector_Molex +Molex_Mega-Fit_76825-0012_2x06_P5.70mm_Horizontal +Molex Mega-Fit Power Connectors, 76825-0012 (compatible alternatives: 172064-0012, 172064-1012), 6 Pins per row (http://www.molex.com/pdm_docs/sd/1720640002_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit top entry +0 +12 +12 +Connector_Molex +Molex_Mega-Fit_76829-0002_2x01_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0002 (compatible alternatives: 172065-0002, 172065-1002), 1 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +2 +2 +Connector_Molex +Molex_Mega-Fit_76829-0004_2x02_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0004 (compatible alternatives: 172065-0004, 172065-1004), 2 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +4 +4 +Connector_Molex +Molex_Mega-Fit_76829-0006_2x03_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0006 (compatible alternatives: 172065-0006, 172065-1006), 3 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +6 +6 +Connector_Molex +Molex_Mega-Fit_76829-0008_2x04_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0008 (compatible alternatives: 172065-0008, 172065-1008), 4 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +8 +8 +Connector_Molex +Molex_Mega-Fit_76829-0010_2x05_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0010 (compatible alternatives: 172065-0010, 172065-1010), 5 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +10 +10 +Connector_Molex +Molex_Mega-Fit_76829-0012_2x06_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0012 (compatible alternatives: 172065-0012, 172065-1012), 6 Pins per row (http://www.molex.com/pdm_docs/sd/768290004_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +12 +12 +Connector_Molex +Molex_Mega-Fit_76829-0102_2x01_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0102 (compatible alternatives: 172065-0202, 172065-0302), 1 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +2 +2 +Connector_Molex +Molex_Mega-Fit_76829-0104_2x02_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0104 (compatible alternatives: 172065-0204, 172065-0304), 2 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +4 +4 +Connector_Molex +Molex_Mega-Fit_76829-0106_2x03_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0106 (compatible alternatives: 172065-0206, 172065-0306), 3 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +6 +6 +Connector_Molex +Molex_Mega-Fit_76829-0108_2x04_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0108 (compatible alternatives: 172065-0208, 172065-0308), 4 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +8 +8 +Connector_Molex +Molex_Mega-Fit_76829-0110_2x05_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0110 (compatible alternatives: 172065-0210, 172065-0310), 5 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +10 +10 +Connector_Molex +Molex_Mega-Fit_76829-0112_2x06_P5.70mm_Vertical +Molex Mega-Fit Power Connectors, 76829-0112 (compatible alternatives: 172065-0212, 172065-0312), 6 Pins per row (http://www.molex.com/pdm_docs/sd/768290102_sd.pdf), generated with kicad-footprint-generator +connector Molex Mega-Fit side entry +0 +12 +12 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0200_2x01_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0200 (alternative finishes: 43045-020x), 1 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +2 +2 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0210_2x01-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0210 (compatible alternatives: 43045-0211, 43045-0209), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +4 +3 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0212_2x01_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0212 (compatible alternatives: 43045-0213, 43045-0224), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +2 +2 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0215_2x01_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0215 (compatible alternatives: 43045-0216, 43045-0217), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +2 +2 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0218_2x01-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0218 (compatible alternatives: 43045-0219, 43045-0220), 1 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +4 +3 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0221_2x01-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0221 (alternative finishes: 43045-022x), 1 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +4 +3 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0400_2x02_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0400 (alternative finishes: 43045-040x), 2 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +4 +4 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0410_2x02-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0410 (compatible alternatives: 43045-0411, 43045-0409), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +6 +5 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0412_2x02_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0412 (compatible alternatives: 43045-0413, 43045-0424), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +4 +4 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0415_2x02_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0415 (compatible alternatives: 43045-0416, 43045-0417), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +4 +4 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0418_2x02-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0418 (compatible alternatives: 43045-0419, 43045-0420), 2 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +6 +5 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0421_2x02-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0421 (alternative finishes: 43045-042x), 2 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +6 +5 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0600_2x03_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0600 (alternative finishes: 43045-060x), 3 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +6 +6 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0610_2x03-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0610 (compatible alternatives: 43045-0611, 43045-0609), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +8 +7 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0612_2x03_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0612 (compatible alternatives: 43045-0613, 43045-0624), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +6 +6 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0615_2x03_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0615 (compatible alternatives: 43045-0616, 43045-0617), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +6 +6 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0618_2x03-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0618 (compatible alternatives: 43045-0619, 43045-0620), 3 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +8 +7 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0621_2x03-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0621 (alternative finishes: 43045-062x), 3 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +8 +7 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0800_2x04_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0800 (alternative finishes: 43045-080x), 4 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +8 +8 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0810_2x04-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0810 (compatible alternatives: 43045-0811, 43045-0809), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +10 +9 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0812_2x04_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0812 (compatible alternatives: 43045-0813, 43045-0824), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +8 +8 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0815_2x04_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0815 (compatible alternatives: 43045-0816, 43045-0817), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +8 +8 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0818_2x04-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-0818 (compatible alternatives: 43045-0819, 43045-0820), 4 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +10 +9 +Connector_Molex +Molex_Micro-Fit_3.0_43045-0821_2x04-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-0821 (alternative finishes: 43045-082x), 4 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +10 +9 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1000_2x05_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1000 (alternative finishes: 43045-100x), 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +10 +10 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1010_2x05-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1010 (compatible alternatives: 43045-1011, 43045-1009), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +12 +11 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1012_2x05_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1012 (compatible alternatives: 43045-1013, 43045-1024), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +10 +10 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1015_2x05_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1015 (compatible alternatives: 43045-1016, 43045-1017), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +10 +10 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1018_2x05-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1018 (compatible alternatives: 43045-1019, 43045-1020), 5 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +12 +11 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1021_2x05-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1021 (alternative finishes: 43045-102x), 5 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +12 +11 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1200_2x06_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1200 (alternative finishes: 43045-120x), 6 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +12 +12 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1210_2x06-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1210 (compatible alternatives: 43045-1211, 43045-1209), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +14 +13 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1212_2x06_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1212 (compatible alternatives: 43045-1213, 43045-1224), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +12 +12 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1215_2x06_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1215 (compatible alternatives: 43045-1216, 43045-1217), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +12 +12 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1218_2x06-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1218 (compatible alternatives: 43045-1219, 43045-1220), 6 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +14 +13 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1221_2x06-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1221 (alternative finishes: 43045-122x), 6 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +14 +13 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1400_2x07_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1400 (alternative finishes: 43045-140x), 7 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +14 +14 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1410_2x07-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1410 (compatible alternatives: 43045-1411, 43045-1409), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +16 +15 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1412_2x07_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1412 (compatible alternatives: 43045-1413, 43045-1424), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +14 +14 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1415_2x07_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1415 (compatible alternatives: 43045-1416, 43045-1417), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +14 +14 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1418_2x07-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1418 (compatible alternatives: 43045-1419, 43045-1420), 7 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +16 +15 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1421_2x07-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1421 (alternative finishes: 43045-142x), 7 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +16 +15 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1600_2x08_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1600 (alternative finishes: 43045-160x), 8 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +16 +16 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1610_2x08-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1610 (compatible alternatives: 43045-1611, 43045-1609), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +18 +17 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1612_2x08_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1612 (compatible alternatives: 43045-1613, 43045-1624), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +16 +16 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1615_2x08_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1615 (compatible alternatives: 43045-1616, 43045-1617), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +16 +16 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1618_2x08-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1618 (compatible alternatives: 43045-1619, 43045-1620), 8 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +18 +17 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1621_2x08-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1621 (alternative finishes: 43045-162x), 8 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +18 +17 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1800_2x09_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1800 (alternative finishes: 43045-180x), 9 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +18 +18 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1810_2x09-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1810 (compatible alternatives: 43045-1811, 43045-1809), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +20 +19 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1812_2x09_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1812 (compatible alternatives: 43045-1813, 43045-1824), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +18 +18 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1815_2x09_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1815 (compatible alternatives: 43045-1816, 43045-1817), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +18 +18 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1818_2x09-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-1818 (compatible alternatives: 43045-1819, 43045-1820), 9 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +20 +19 +Connector_Molex +Molex_Micro-Fit_3.0_43045-1821_2x09-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-1821 (alternative finishes: 43045-182x), 9 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +20 +19 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2000_2x10_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2000 (alternative finishes: 43045-200x), 10 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +20 +20 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2010_2x10-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2010 (compatible alternatives: 43045-2011, 43045-2009), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +22 +21 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2012_2x10_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2012 (compatible alternatives: 43045-2013, 43045-2024), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +20 +20 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2015_2x10_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2015 (compatible alternatives: 43045-2016, 43045-2017), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +20 +20 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2018_2x10-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2018 (compatible alternatives: 43045-2019, 43045-2020), 10 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +22 +21 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2021_2x10-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2021 (alternative finishes: 43045-202x), 10 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +22 +21 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2200_2x11_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2200 (alternative finishes: 43045-220x), 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +22 +22 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2210_2x11-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2210 (compatible alternatives: 43045-2211, 43045-2209), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +24 +23 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2212_2x11_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2212 (compatible alternatives: 43045-2213, 43045-2224), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +22 +22 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2215_2x11_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2215 (compatible alternatives: 43045-2216, 43045-2217), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +22 +22 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2218_2x11-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2218 (compatible alternatives: 43045-2219, 43045-2220), 11 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +24 +23 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2221_2x11-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2221 (alternative finishes: 43045-222x), 11 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +24 +23 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2400_2x12_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2400 (alternative finishes: 43045-240x), 12 Pins per row (https://www.molex.com/pdm_docs/sd/430450201_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +24 +24 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2410_2x12-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2410 (compatible alternatives: 43045-2411, 43045-2409), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450210_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +26 +25 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2412_2x12_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2412 (compatible alternatives: 43045-2413, 43045-2424), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450212_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +24 +24 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2415_2x12_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2415 (compatible alternatives: 43045-2416, 43045-2417), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450217_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +24 +24 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2418_2x12-1MP_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43045-2418 (compatible alternatives: 43045-2419, 43045-2420), 12 Pins per row (http://www.molex.com/pdm_docs/sd/430450218_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 side entry +0 +26 +25 +Connector_Molex +Molex_Micro-Fit_3.0_43045-2421_2x12-1MP_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43045-2421 (alternative finishes: 43045-242x), 12 Pins per row (https://www.molex.com/pdm_docs/sd/430450221_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 horizontal +0 +26 +25 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0200_1x02_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0200 (compatible alternatives: 43650-0201, 43650-0202), 2 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +2 +2 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0215_1x02_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0215 (compatible alternatives: 43650-0216, 43650-0217), 2 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +2 +2 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0300_1x03_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0300 (compatible alternatives: 43650-0301, 43650-0302), 3 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +3 +3 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0315_1x03_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0315 (compatible alternatives: 43650-0316, 43650-0317), 3 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +3 +3 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0400_1x04_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0400 (compatible alternatives: 43650-0401, 43650-0402), 4 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +4 +4 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0415_1x04_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0415 (compatible alternatives: 43650-0416, 43650-0417), 4 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +4 +4 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0500_1x05_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0500 (compatible alternatives: 43650-0501, 43650-0502), 5 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +5 +5 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0515_1x05_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0515 (compatible alternatives: 43650-0516, 43650-0517), 5 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +5 +5 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0600_1x06_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0600 (compatible alternatives: 43650-0601, 43650-0602), 6 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +6 +6 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0615_1x06_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0615 (compatible alternatives: 43650-0616, 43650-0617), 6 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +6 +6 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0700_1x07_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0700 (compatible alternatives: 43650-0701, 43650-0702), 7 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +7 +7 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0715_1x07_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0715 (compatible alternatives: 43650-0716, 43650-0717), 7 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +7 +7 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0800_1x08_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0800 (compatible alternatives: 43650-0801, 43650-0802), 8 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +8 +8 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0815_1x08_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0815 (compatible alternatives: 43650-0816, 43650-0817), 8 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +8 +8 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0900_1x09_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-0900 (compatible alternatives: 43650-0901, 43650-0902), 9 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +9 +9 +Connector_Molex +Molex_Micro-Fit_3.0_43650-0915_1x09_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-0915 (compatible alternatives: 43650-0916, 43650-0917), 9 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +9 +9 +Connector_Molex +Molex_Micro-Fit_3.0_43650-1000_1x10_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-1000 (compatible alternatives: 43650-1001, 43650-1002), 10 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +10 +10 +Connector_Molex +Molex_Micro-Fit_3.0_43650-1015_1x10_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-1015 (compatible alternatives: 43650-1016, 43650-1017), 10 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +10 +10 +Connector_Molex +Molex_Micro-Fit_3.0_43650-1100_1x11_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-1100 (compatible alternatives: 43650-1101, 43650-1102), 11 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +11 +11 +Connector_Molex +Molex_Micro-Fit_3.0_43650-1115_1x11_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-1115 (compatible alternatives: 43650-1116, 43650-1117), 11 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +11 +11 +Connector_Molex +Molex_Micro-Fit_3.0_43650-1200_1x12_P3.00mm_Horizontal +Molex Micro-Fit 3.0 Connector System, 43650-1200 (compatible alternatives: 43650-1201, 43650-1202), 12 Pins per row (https://www.molex.com/pdm_docs/sd/436500300_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 top entry +0 +12 +12 +Connector_Molex +Molex_Micro-Fit_3.0_43650-1215_1x12_P3.00mm_Vertical +Molex Micro-Fit 3.0 Connector System, 43650-1215 (compatible alternatives: 43650-1216, 43650-1217), 12 Pins per row (http://www.molex.com/pdm_docs/sd/436500215_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Fit_3.0 vertical +0 +12 +12 +Connector_Molex +Molex_Micro-Latch_53253-0270_1x02_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0270 (compatible alternatives: 53253-0250), 2 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +2 +2 +Connector_Molex +Molex_Micro-Latch_53253-0370_1x03_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0370 (compatible alternatives: 53253-0350), 3 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +3 +3 +Connector_Molex +Molex_Micro-Latch_53253-0470_1x04_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0470 (compatible alternatives: 53253-0450), 4 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +4 +4 +Connector_Molex +Molex_Micro-Latch_53253-0570_1x05_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0570 (compatible alternatives: 53253-0550), 5 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +5 +5 +Connector_Molex +Molex_Micro-Latch_53253-0670_1x06_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0670 (compatible alternatives: 53253-0650), 6 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +6 +6 +Connector_Molex +Molex_Micro-Latch_53253-0770_1x07_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0770 (compatible alternatives: 53253-0750), 7 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +7 +7 +Connector_Molex +Molex_Micro-Latch_53253-0870_1x08_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0870 (compatible alternatives: 53253-0850), 8 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +8 +8 +Connector_Molex +Molex_Micro-Latch_53253-0970_1x09_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-0970 (compatible alternatives: 53253-0950), 9 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +9 +9 +Connector_Molex +Molex_Micro-Latch_53253-1070_1x10_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-1070 (compatible alternatives: 53253-1050), 10 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +10 +10 +Connector_Molex +Molex_Micro-Latch_53253-1170_1x11_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-1170 (compatible alternatives: 53253-1150), 11 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +11 +11 +Connector_Molex +Molex_Micro-Latch_53253-1270_1x12_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-1270 (compatible alternatives: 53253-1250), 12 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +12 +12 +Connector_Molex +Molex_Micro-Latch_53253-1370_1x13_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-1370 (compatible alternatives: 53253-1350), 13 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +13 +13 +Connector_Molex +Molex_Micro-Latch_53253-1470_1x14_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-1470 (compatible alternatives: 53253-1450), 14 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +14 +14 +Connector_Molex +Molex_Micro-Latch_53253-1570_1x15_P2.00mm_Vertical +Molex Micro-Latch Wire-to-Board Connector System, 53253-1570 (compatible alternatives: 53253-1550), 15 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch side entry +0 +15 +15 +Connector_Molex +Molex_Micro-Latch_53254-0270_1x02_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0270 (compatible alternatives: 53254-0250), 2 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +2 +2 +Connector_Molex +Molex_Micro-Latch_53254-0370_1x03_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0370 (compatible alternatives: 53254-0350), 3 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +3 +3 +Connector_Molex +Molex_Micro-Latch_53254-0470_1x04_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0470 (compatible alternatives: 53254-0450), 4 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +4 +4 +Connector_Molex +Molex_Micro-Latch_53254-0570_1x05_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0570 (compatible alternatives: 53254-0550), 5 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +5 +5 +Connector_Molex +Molex_Micro-Latch_53254-0670_1x06_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0670 (compatible alternatives: 53254-0650), 6 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +6 +6 +Connector_Molex +Molex_Micro-Latch_53254-0770_1x07_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0770 (compatible alternatives: 53254-0750), 7 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +7 +7 +Connector_Molex +Molex_Micro-Latch_53254-0870_1x08_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0870 (compatible alternatives: 53254-0850), 8 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +8 +8 +Connector_Molex +Molex_Micro-Latch_53254-0970_1x09_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-0970 (compatible alternatives: 53254-0950), 9 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +9 +9 +Connector_Molex +Molex_Micro-Latch_53254-1070_1x10_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-1070 (compatible alternatives: 53254-1050), 10 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +10 +10 +Connector_Molex +Molex_Micro-Latch_53254-1170_1x11_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-1170 (compatible alternatives: 53254-1150), 11 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +11 +11 +Connector_Molex +Molex_Micro-Latch_53254-1270_1x12_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-1270 (compatible alternatives: 53254-1250), 12 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +12 +12 +Connector_Molex +Molex_Micro-Latch_53254-1370_1x13_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-1370 (compatible alternatives: 53254-1350), 13 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +13 +13 +Connector_Molex +Molex_Micro-Latch_53254-1470_1x14_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-1470 (compatible alternatives: 53254-1450), 14 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +14 +14 +Connector_Molex +Molex_Micro-Latch_53254-1570_1x15_P2.00mm_Horizontal +Molex Micro-Latch Wire-to-Board Connector System, 53254-1570 (compatible alternatives: 53254-1550), 15 Pins per row (http://www.molex.com/pdm_docs/sd/532530770_sd.pdf), generated with kicad-footprint-generator +connector Molex Micro-Latch top entry +0 +15 +15 +Connector_Molex +Molex_MicroClasp_55932-0210_1x02_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0210, with PCB locator, 2 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +2 +2 +Connector_Molex +Molex_MicroClasp_55932-0230_1x02_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0230, 2 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +2 +2 +Connector_Molex +Molex_MicroClasp_55932-0310_1x03_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0310, with PCB locator, 3 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +3 +3 +Connector_Molex +Molex_MicroClasp_55932-0330_1x03_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0330, 3 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +3 +3 +Connector_Molex +Molex_MicroClasp_55932-0410_1x04_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0410, with PCB locator, 4 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +4 +4 +Connector_Molex +Molex_MicroClasp_55932-0430_1x04_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0430, 4 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +4 +4 +Connector_Molex +Molex_MicroClasp_55932-0510_1x05_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0510, with PCB locator, 5 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +5 +5 +Connector_Molex +Molex_MicroClasp_55932-0530_1x05_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0530, 5 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +5 +5 +Connector_Molex +Molex_MicroClasp_55932-0610_1x06_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0610, with PCB locator, 6 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +6 +6 +Connector_Molex +Molex_MicroClasp_55932-0630_1x06_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0630, 6 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +6 +6 +Connector_Molex +Molex_MicroClasp_55932-0710_1x07_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0710, with PCB locator, 7 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +7 +7 +Connector_Molex +Molex_MicroClasp_55932-0730_1x07_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0730, 7 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +7 +7 +Connector_Molex +Molex_MicroClasp_55932-0810_1x08_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0810, with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +8 +8 +Connector_Molex +Molex_MicroClasp_55932-0830_1x08_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0830, 8 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +8 +8 +Connector_Molex +Molex_MicroClasp_55932-0910_1x09_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0910, with PCB locator, 9 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +9 +9 +Connector_Molex +Molex_MicroClasp_55932-0930_1x09_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-0930, 9 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +9 +9 +Connector_Molex +Molex_MicroClasp_55932-1010_1x10_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1010, with PCB locator, 10 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +10 +10 +Connector_Molex +Molex_MicroClasp_55932-1030_1x10_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1030, 10 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +10 +10 +Connector_Molex +Molex_MicroClasp_55932-1110_1x11_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1110, with PCB locator, 11 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +11 +11 +Connector_Molex +Molex_MicroClasp_55932-1130_1x11_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1130, 11 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +11 +11 +Connector_Molex +Molex_MicroClasp_55932-1210_1x12_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1210, with PCB locator, 12 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +12 +12 +Connector_Molex +Molex_MicroClasp_55932-1230_1x12_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1230, 12 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +12 +12 +Connector_Molex +Molex_MicroClasp_55932-1310_1x13_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1310, with PCB locator, 13 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +13 +13 +Connector_Molex +Molex_MicroClasp_55932-1330_1x13_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1330, 13 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +13 +13 +Connector_Molex +Molex_MicroClasp_55932-1410_1x14_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1410, with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +14 +14 +Connector_Molex +Molex_MicroClasp_55932-1430_1x14_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1430, 14 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +14 +14 +Connector_Molex +Molex_MicroClasp_55932-1510_1x15_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1510, with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +15 +15 +Connector_Molex +Molex_MicroClasp_55932-1530_1x15_P2.00mm_Vertical +Molex MicroClasp Wire-to-Board System, 55932-1530, 15 Pins (http://www.molex.com/pdm_docs/sd/559320530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp side entry +0 +15 +15 +Connector_Molex +Molex_MicroClasp_55935-0210_1x02_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0210, with PCB locator, 2 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +2 +2 +Connector_Molex +Molex_MicroClasp_55935-0230_1x02_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0230, 2 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +2 +2 +Connector_Molex +Molex_MicroClasp_55935-0310_1x03_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0310, with PCB locator, 3 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +3 +3 +Connector_Molex +Molex_MicroClasp_55935-0330_1x03_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0330, 3 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +3 +3 +Connector_Molex +Molex_MicroClasp_55935-0410_1x04_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0410, with PCB locator, 4 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +4 +4 +Connector_Molex +Molex_MicroClasp_55935-0430_1x04_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0430, 4 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +4 +4 +Connector_Molex +Molex_MicroClasp_55935-0510_1x05_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0510, with PCB locator, 5 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +5 +5 +Connector_Molex +Molex_MicroClasp_55935-0530_1x05_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0530, 5 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +5 +5 +Connector_Molex +Molex_MicroClasp_55935-0610_1x06_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0610, with PCB locator, 6 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +6 +6 +Connector_Molex +Molex_MicroClasp_55935-0630_1x06_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0630, 6 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +6 +6 +Connector_Molex +Molex_MicroClasp_55935-0710_1x07_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0710, with PCB locator, 7 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +7 +7 +Connector_Molex +Molex_MicroClasp_55935-0730_1x07_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0730, 7 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +7 +7 +Connector_Molex +Molex_MicroClasp_55935-0810_1x08_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0810, with PCB locator, 8 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +8 +8 +Connector_Molex +Molex_MicroClasp_55935-0830_1x08_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0830, 8 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +8 +8 +Connector_Molex +Molex_MicroClasp_55935-0910_1x09_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0910, with PCB locator, 9 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +9 +9 +Connector_Molex +Molex_MicroClasp_55935-0930_1x09_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-0930, 9 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +9 +9 +Connector_Molex +Molex_MicroClasp_55935-1010_1x10_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1010, with PCB locator, 10 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +10 +10 +Connector_Molex +Molex_MicroClasp_55935-1030_1x10_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1030, 10 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +10 +10 +Connector_Molex +Molex_MicroClasp_55935-1110_1x11_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1110, with PCB locator, 11 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +11 +11 +Connector_Molex +Molex_MicroClasp_55935-1130_1x11_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1130, 11 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +11 +11 +Connector_Molex +Molex_MicroClasp_55935-1210_1x12_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1210, with PCB locator, 12 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +12 +12 +Connector_Molex +Molex_MicroClasp_55935-1230_1x12_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1230, 12 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +12 +12 +Connector_Molex +Molex_MicroClasp_55935-1310_1x13_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1310, with PCB locator, 13 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +13 +13 +Connector_Molex +Molex_MicroClasp_55935-1330_1x13_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1330, 13 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +13 +13 +Connector_Molex +Molex_MicroClasp_55935-1410_1x14_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1410, with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +14 +14 +Connector_Molex +Molex_MicroClasp_55935-1430_1x14_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1430, 14 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +14 +14 +Connector_Molex +Molex_MicroClasp_55935-1510_1x15_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1510, with PCB locator, 15 Pins (http://www.molex.com/pdm_docs/sd/559350210_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +15 +15 +Connector_Molex +Molex_MicroClasp_55935-1530_1x15_P2.00mm_Horizontal +Molex MicroClasp Wire-to-Board System, 55935-1530, 15 Pins (http://www.molex.com/pdm_docs/sd/559350530_sd.pdf), generated with kicad-footprint-generator +connector Molex MicroClasp horizontal +0 +15 +15 +Connector_Molex +Molex_Mini-Fit_Jr_5566-02A2_2x01_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-02A2, example for new mpn: 39-28-902x, 1 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +2 +2 +Connector_Molex +Molex_Mini-Fit_Jr_5566-02A_2x01_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-02A, example for new mpn: 39-28-x02x, 1 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +2 +2 +Connector_Molex +Molex_Mini-Fit_Jr_5566-04A2_2x02_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-04A2, example for new mpn: 39-28-904x, 2 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +4 +4 +Connector_Molex +Molex_Mini-Fit_Jr_5566-04A_2x02_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-04A, example for new mpn: 39-28-x04x, 2 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +4 +4 +Connector_Molex +Molex_Mini-Fit_Jr_5566-06A2_2x03_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-06A2, example for new mpn: 39-28-906x, 3 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +6 +6 +Connector_Molex +Molex_Mini-Fit_Jr_5566-06A_2x03_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-06A, example for new mpn: 39-28-x06x, 3 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +6 +6 +Connector_Molex +Molex_Mini-Fit_Jr_5566-08A2_2x04_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-08A2, example for new mpn: 39-28-908x, 4 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +8 +8 +Connector_Molex +Molex_Mini-Fit_Jr_5566-08A_2x04_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-08A, example for new mpn: 39-28-x08x, 4 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +8 +8 +Connector_Molex +Molex_Mini-Fit_Jr_5566-10A2_2x05_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-10A2, example for new mpn: 39-28-910x, 5 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +10 +10 +Connector_Molex +Molex_Mini-Fit_Jr_5566-10A_2x05_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-10A, example for new mpn: 39-28-x10x, 5 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +10 +10 +Connector_Molex +Molex_Mini-Fit_Jr_5566-12A2_2x06_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-12A2, example for new mpn: 39-28-912x, 6 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +12 +12 +Connector_Molex +Molex_Mini-Fit_Jr_5566-12A_2x06_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-12A, example for new mpn: 39-28-x12x, 6 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +12 +12 +Connector_Molex +Molex_Mini-Fit_Jr_5566-14A2_2x07_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-14A2, example for new mpn: 39-28-914x, 7 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +14 +14 +Connector_Molex +Molex_Mini-Fit_Jr_5566-14A_2x07_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-14A, example for new mpn: 39-28-x14x, 7 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +14 +14 +Connector_Molex +Molex_Mini-Fit_Jr_5566-16A2_2x08_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-16A2, example for new mpn: 39-28-916x, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +16 +16 +Connector_Molex +Molex_Mini-Fit_Jr_5566-16A_2x08_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-16A, example for new mpn: 39-28-x16x, 8 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +16 +16 +Connector_Molex +Molex_Mini-Fit_Jr_5566-18A2_2x09_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-18A2, example for new mpn: 39-28-918x, 9 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +18 +18 +Connector_Molex +Molex_Mini-Fit_Jr_5566-18A_2x09_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-18A, example for new mpn: 39-28-x18x, 9 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +18 +18 +Connector_Molex +Molex_Mini-Fit_Jr_5566-20A2_2x10_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-20A2, example for new mpn: 39-28-920x, 10 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +20 +20 +Connector_Molex +Molex_Mini-Fit_Jr_5566-20A_2x10_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-20A, example for new mpn: 39-28-x20x, 10 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +20 +20 +Connector_Molex +Molex_Mini-Fit_Jr_5566-22A2_2x11_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-22A2, example for new mpn: 39-28-922x, 11 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +22 +22 +Connector_Molex +Molex_Mini-Fit_Jr_5566-22A_2x11_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-22A, example for new mpn: 39-28-x22x, 11 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +22 +22 +Connector_Molex +Molex_Mini-Fit_Jr_5566-24A2_2x12_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-24A2, example for new mpn: 39-28-924x, 12 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039289068_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entryplastic_peg +0 +24 +24 +Connector_Molex +Molex_Mini-Fit_Jr_5566-24A_2x12_P4.20mm_Vertical +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5566-24A, example for new mpn: 39-28-x24x, 12 Pins per row, Mounting: (http://www.molex.com/pdm_docs/sd/039281043_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr side entry +0 +24 +24 +Connector_Molex +Molex_Mini-Fit_Jr_5569-02A1_2x01_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-02A1, example for new mpn: 39-29-4029, 1 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +2 +2 +Connector_Molex +Molex_Mini-Fit_Jr_5569-02A2_2x01_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-02A2, example for new mpn: 39-30-0020, 1 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +2 +2 +Connector_Molex +Molex_Mini-Fit_Jr_5569-04A1_2x02_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-04A1, example for new mpn: 39-29-4049, 2 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +4 +4 +Connector_Molex +Molex_Mini-Fit_Jr_5569-04A2_2x02_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-04A2, example for new mpn: 39-30-0040, 2 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +4 +4 +Connector_Molex +Molex_Mini-Fit_Jr_5569-06A1_2x03_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-06A1, example for new mpn: 39-29-4069, 3 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +6 +6 +Connector_Molex +Molex_Mini-Fit_Jr_5569-06A2_2x03_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-06A2, example for new mpn: 39-30-0060, 3 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +6 +6 +Connector_Molex +Molex_Mini-Fit_Jr_5569-08A1_2x04_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-08A1, example for new mpn: 39-29-4089, 4 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +8 +8 +Connector_Molex +Molex_Mini-Fit_Jr_5569-08A2_2x04_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-08A2, example for new mpn: 39-30-0080, 4 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +8 +8 +Connector_Molex +Molex_Mini-Fit_Jr_5569-10A1_2x05_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-10A1, example for new mpn: 39-29-4109, 5 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +10 +10 +Connector_Molex +Molex_Mini-Fit_Jr_5569-10A2_2x05_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-10A2, example for new mpn: 39-30-0100, 5 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +10 +10 +Connector_Molex +Molex_Mini-Fit_Jr_5569-12A1_2x06_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-12A1, example for new mpn: 39-29-4129, 6 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +12 +12 +Connector_Molex +Molex_Mini-Fit_Jr_5569-12A2_2x06_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-12A2, example for new mpn: 39-30-0120, 6 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +12 +12 +Connector_Molex +Molex_Mini-Fit_Jr_5569-14A1_2x07_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A1, example for new mpn: 39-29-4149, 7 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +14 +14 +Connector_Molex +Molex_Mini-Fit_Jr_5569-14A2_2x07_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A2, example for new mpn: 39-30-0140, 7 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +14 +14 +Connector_Molex +Molex_Mini-Fit_Jr_5569-16A1_2x08_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-16A1, example for new mpn: 39-29-4169, 8 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +16 +16 +Connector_Molex +Molex_Mini-Fit_Jr_5569-16A2_2x08_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-16A2, example for new mpn: 39-30-0160, 8 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +16 +16 +Connector_Molex +Molex_Mini-Fit_Jr_5569-18A1_2x09_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-18A1, example for new mpn: 39-29-4189, 9 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +18 +18 +Connector_Molex +Molex_Mini-Fit_Jr_5569-18A2_2x09_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-18A2, example for new mpn: 39-30-0180, 9 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +18 +18 +Connector_Molex +Molex_Mini-Fit_Jr_5569-20A1_2x10_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-20A1, example for new mpn: 39-29-4209, 10 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +20 +20 +Connector_Molex +Molex_Mini-Fit_Jr_5569-20A2_2x10_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-20A2, example for new mpn: 39-30-0200, 10 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +20 +20 +Connector_Molex +Molex_Mini-Fit_Jr_5569-22A1_2x11_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-22A1, example for new mpn: 39-29-4229, 11 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +22 +22 +Connector_Molex +Molex_Mini-Fit_Jr_5569-22A2_2x11_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-22A2, example for new mpn: 39-30-0220, 11 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +22 +22 +Connector_Molex +Molex_Mini-Fit_Jr_5569-24A1_2x12_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-24A1, example for new mpn: 39-29-4249, 12 Pins per row, Mounting: PCB Mounting Flange (http://www.molex.com/pdm_docs/sd/039291047_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryscrew_flange +0 +24 +24 +Connector_Molex +Molex_Mini-Fit_Jr_5569-24A2_2x12_P4.20mm_Horizontal +Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-24A2, example for new mpn: 39-30-0240, 12 Pins per row, Mounting: Snap-in Plastic Peg PCB Lock (http://www.molex.com/pdm_docs/sd/039300020_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Jr top entryplastic_peg +0 +24 +24 +Connector_Molex +Molex_Mini-Fit_Sr_42819-22XX_1x02_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 42819-22XX, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +6 +2 +Connector_Molex +Molex_Mini-Fit_Sr_42819-22XX_1x02_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42819-22XX, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +32 +2 +Connector_Molex +Molex_Mini-Fit_Sr_42819-32XX_1x03_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 42819-32XX, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +8 +3 +Connector_Molex +Molex_Mini-Fit_Sr_42819-32XX_1x03_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42819-32XX, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +47 +3 +Connector_Molex +Molex_Mini-Fit_Sr_42819-42XX_1x04_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 42819-42XX, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +10 +4 +Connector_Molex +Molex_Mini-Fit_Sr_42819-42XX_1x04_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42819-42XX, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +62 +4 +Connector_Molex +Molex_Mini-Fit_Sr_42819-52XX_1x05_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 42819-52XX, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +12 +5 +Connector_Molex +Molex_Mini-Fit_Sr_42819-52XX_1x05_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42819-52XX, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +77 +5 +Connector_Molex +Molex_Mini-Fit_Sr_42819-62XX_1x06_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 42819-62XX, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +14 +6 +Connector_Molex +Molex_Mini-Fit_Sr_42819-62XX_1x06_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42819-62XX, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428192214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +92 +6 +Connector_Molex +Molex_Mini-Fit_Sr_42820-22XX_1x02_P10.00mm_Horizontal +Molex Mini-Fit Sr. Power Connectors, 42820-22XX, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +6 +2 +Connector_Molex +Molex_Mini-Fit_Sr_42820-22XX_1x02_P10.00mm_Horizontal_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42820-22XX, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +32 +2 +Connector_Molex +Molex_Mini-Fit_Sr_42820-32XX_1x03_P10.00mm_Horizontal +Molex Mini-Fit Sr. Power Connectors, 42820-32XX, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +8 +3 +Connector_Molex +Molex_Mini-Fit_Sr_42820-32XX_1x03_P10.00mm_Horizontal_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42820-32XX, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +47 +3 +Connector_Molex +Molex_Mini-Fit_Sr_42820-42XX_1x04_P10.00mm_Horizontal +Molex Mini-Fit Sr. Power Connectors, 42820-42XX, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +10 +4 +Connector_Molex +Molex_Mini-Fit_Sr_42820-42XX_1x04_P10.00mm_Horizontal_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42820-42XX, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +62 +4 +Connector_Molex +Molex_Mini-Fit_Sr_42820-52XX_1x05_P10.00mm_Horizontal +Molex Mini-Fit Sr. Power Connectors, 42820-52XX, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +12 +5 +Connector_Molex +Molex_Mini-Fit_Sr_42820-52XX_1x05_P10.00mm_Horizontal_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42820-52XX, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +77 +5 +Connector_Molex +Molex_Mini-Fit_Sr_42820-62XX_1x06_P10.00mm_Horizontal +Molex Mini-Fit Sr. Power Connectors, 42820-62XX, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +14 +6 +Connector_Molex +Molex_Mini-Fit_Sr_42820-62XX_1x06_P10.00mm_Horizontal_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 42820-62XX, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/428202214_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr top entry +0 +92 +6 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx06_2x03_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 43915-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +14 +6 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx06_2x03_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 43915-xx06, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +92 +6 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx08_2x04_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 43915-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +18 +8 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx08_2x04_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 43915-xx08, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +122 +8 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx10_2x05_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 43915-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +22 +10 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx10_2x05_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 43915-xx10, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +152 +10 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx12_2x06_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 43915-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +26 +12 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx12_2x06_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 43915-xx12, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +182 +12 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx14_2x07_P10.00mm_Vertical +Molex Mini-Fit Sr. Power Connectors, 43915-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +30 +14 +Connector_Molex +Molex_Mini-Fit_Sr_43915-xx14_2x07_P10.00mm_Vertical_ThermalVias +Molex Mini-Fit Sr. Power Connectors, 43915-xx14, With thermal vias in pads, 7 Pins per row (http://www.molex.com/pdm_docs/sd/439151404_sd.pdf), generated with kicad-footprint-generator +connector Molex Mini-Fit_Sr side entry +0 +212 +14 +Connector_Molex +Molex_Nano-Fit_105309-xx02_1x02_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx02, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +2 +2 +Connector_Molex +Molex_Nano-Fit_105309-xx03_1x03_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx03, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +3 +3 +Connector_Molex +Molex_Nano-Fit_105309-xx04_1x04_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx04, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +4 +4 +Connector_Molex +Molex_Nano-Fit_105309-xx05_1x05_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx05, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +5 +5 +Connector_Molex +Molex_Nano-Fit_105309-xx06_1x06_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx06, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +6 +6 +Connector_Molex +Molex_Nano-Fit_105309-xx07_1x07_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx07, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +7 +7 +Connector_Molex +Molex_Nano-Fit_105309-xx08_1x08_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105309-xx08, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053091203_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +8 +8 +Connector_Molex +Molex_Nano-Fit_105310-xx04_2x02_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx04, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +4 +4 +Connector_Molex +Molex_Nano-Fit_105310-xx06_2x03_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +6 +6 +Connector_Molex +Molex_Nano-Fit_105310-xx08_2x04_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +8 +8 +Connector_Molex +Molex_Nano-Fit_105310-xx10_2x05_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +10 +10 +Connector_Molex +Molex_Nano-Fit_105310-xx12_2x06_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +12 +12 +Connector_Molex +Molex_Nano-Fit_105310-xx14_2x07_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +14 +14 +Connector_Molex +Molex_Nano-Fit_105310-xx16_2x08_P2.50mm_Vertical +Molex Nano-Fit Power Connectors, 105310-xx16, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit side entry +0 +16 +16 +Connector_Molex +Molex_Nano-Fit_105313-xx02_1x02_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx02, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +2 +2 +Connector_Molex +Molex_Nano-Fit_105313-xx03_1x03_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx03, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +3 +3 +Connector_Molex +Molex_Nano-Fit_105313-xx04_1x04_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx04, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +4 +4 +Connector_Molex +Molex_Nano-Fit_105313-xx05_1x05_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx05, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +5 +5 +Connector_Molex +Molex_Nano-Fit_105313-xx06_1x06_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx06, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +6 +6 +Connector_Molex +Molex_Nano-Fit_105313-xx07_1x07_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx07, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +7 +7 +Connector_Molex +Molex_Nano-Fit_105313-xx08_1x08_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105313-xx08, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053131208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +8 +8 +Connector_Molex +Molex_Nano-Fit_105314-xx04_2x02_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx04, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +4 +4 +Connector_Molex +Molex_Nano-Fit_105314-xx06_2x03_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx06, 3 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +6 +6 +Connector_Molex +Molex_Nano-Fit_105314-xx08_2x04_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx08, 4 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +8 +8 +Connector_Molex +Molex_Nano-Fit_105314-xx10_2x05_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx10, 5 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +10 +10 +Connector_Molex +Molex_Nano-Fit_105314-xx12_2x06_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx12, 6 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +12 +12 +Connector_Molex +Molex_Nano-Fit_105314-xx14_2x07_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx14, 7 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +14 +14 +Connector_Molex +Molex_Nano-Fit_105314-xx16_2x08_P2.50mm_Horizontal +Molex Nano-Fit Power Connectors, 105314-xx16, 8 Pins per row (http://www.molex.com/pdm_docs/sd/1053141208_sd.pdf), generated with kicad-footprint-generator +connector Molex Nano-Fit top entry +0 +16 +16 +Connector_Molex +Molex_Panelmate_53780-0270_1x02-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0270 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +4 +3 +Connector_Molex +Molex_Panelmate_53780-0370_1x03-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0370 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +5 +4 +Connector_Molex +Molex_Panelmate_53780-0470_1x04-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0470 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +6 +5 +Connector_Molex +Molex_Panelmate_53780-0570_1x05-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0570 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +7 +6 +Connector_Molex +Molex_Panelmate_53780-0670_1x06-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0670 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +8 +7 +Connector_Molex +Molex_Panelmate_53780-0770_1x07-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0770 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +9 +8 +Connector_Molex +Molex_Panelmate_53780-0870_1x08-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0870 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +10 +9 +Connector_Molex +Molex_Panelmate_53780-0970_1x09-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-0970 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +11 +10 +Connector_Molex +Molex_Panelmate_53780-1070_1x10-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-1070 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +12 +11 +Connector_Molex +Molex_Panelmate_53780-1270_1x12-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-1270 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +14 +13 +Connector_Molex +Molex_Panelmate_53780-1470_1x14-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-1470 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +16 +15 +Connector_Molex +Molex_Panelmate_53780-1570_1x15-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-1570 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +17 +16 +Connector_Molex +Molex_Panelmate_53780-1870_1x18-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-1870 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +20 +19 +Connector_Molex +Molex_Panelmate_53780-3070_1x30-1MP_P1.25mm_Horizontal +Molex Panelmate series connector, 53780-3070 (), generated with kicad-footprint-generator +connector Molex Panelmate top entry +0 +32 +31 +Connector_Molex +Molex_Pico-Clasp_202396-0207_1x02-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0207 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +4 +3 +Connector_Molex +Molex_Pico-Clasp_202396-0307_1x03-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0307 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +5 +4 +Connector_Molex +Molex_Pico-Clasp_202396-0407_1x04-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0407 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +6 +5 +Connector_Molex +Molex_Pico-Clasp_202396-0507_1x05-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0507 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +7 +6 +Connector_Molex +Molex_Pico-Clasp_202396-0607_1x06-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0607 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +8 +7 +Connector_Molex +Molex_Pico-Clasp_202396-0707_1x07-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0707 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +9 +8 +Connector_Molex +Molex_Pico-Clasp_202396-0807_1x08-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0807 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +10 +9 +Connector_Molex +Molex_Pico-Clasp_202396-0907_1x09-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-0907 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +11 +10 +Connector_Molex +Molex_Pico-Clasp_202396-1007_1x10-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-1007 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +12 +11 +Connector_Molex +Molex_Pico-Clasp_202396-1107_1x11-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-1107 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +13 +12 +Connector_Molex +Molex_Pico-Clasp_202396-1207_1x12-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-1207 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +14 +13 +Connector_Molex +Molex_Pico-Clasp_202396-1307_1x13-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-1307 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +15 +14 +Connector_Molex +Molex_Pico-Clasp_202396-1407_1x14-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-1407 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +16 +15 +Connector_Molex +Molex_Pico-Clasp_202396-1507_1x15-1MP_P1.00mm_Horizontal +Molex Pico-Clasp series connector, 202396-1507 (http://www.molex.com/pdm_docs/sd/2023960207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp top entry +0 +17 +16 +Connector_Molex +Molex_Pico-Clasp_501331-0207_1x02-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0207 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +4 +3 +Connector_Molex +Molex_Pico-Clasp_501331-0307_1x03-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0307 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +5 +4 +Connector_Molex +Molex_Pico-Clasp_501331-0407_1x04-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0407 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +6 +5 +Connector_Molex +Molex_Pico-Clasp_501331-0507_1x05-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0507 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +7 +6 +Connector_Molex +Molex_Pico-Clasp_501331-0607_1x06-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0607 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +8 +7 +Connector_Molex +Molex_Pico-Clasp_501331-0707_1x07-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0707 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +9 +8 +Connector_Molex +Molex_Pico-Clasp_501331-0807_1x08-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0807 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +10 +9 +Connector_Molex +Molex_Pico-Clasp_501331-0907_1x09-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-0907 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +11 +10 +Connector_Molex +Molex_Pico-Clasp_501331-1007_1x10-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-1007 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +12 +11 +Connector_Molex +Molex_Pico-Clasp_501331-1107_1x11-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-1107 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +13 +12 +Connector_Molex +Molex_Pico-Clasp_501331-1207_1x12-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-1207 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +14 +13 +Connector_Molex +Molex_Pico-Clasp_501331-1307_1x13-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-1307 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +15 +14 +Connector_Molex +Molex_Pico-Clasp_501331-1407_1x14-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-1407 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +16 +15 +Connector_Molex +Molex_Pico-Clasp_501331-1507_1x15-1MP_P1.00mm_Vertical +Molex Pico-Clasp series connector, 501331-1507 (http://www.molex.com/pdm_docs/sd/5013310207_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Clasp side entry +0 +17 +16 +Connector_Molex +Molex_Pico-EZmate_78171-0002_1x02-1MP_P1.20mm_Vertical +Molex Pico-EZmate series connector, 78171-0002 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-EZmate side entry +0 +4 +3 +Connector_Molex +Molex_Pico-EZmate_78171-0003_1x03-1MP_P1.20mm_Vertical +Molex Pico-EZmate series connector, 78171-0003 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-EZmate side entry +0 +5 +4 +Connector_Molex +Molex_Pico-EZmate_78171-0004_1x04-1MP_P1.20mm_Vertical +Molex Pico-EZmate series connector, 78171-0004 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-EZmate side entry +0 +6 +5 +Connector_Molex +Molex_Pico-EZmate_78171-0005_1x05-1MP_P1.20mm_Vertical +Molex Pico-EZmate series connector, 78171-0005 (http://www.molex.com/pdm_docs/sd/781710002_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-EZmate side entry +0 +7 +6 +Connector_Molex +Molex_Pico-EZmate_Slim_202656-0021_1x02-1MP_P1.20mm_Vertical +Molex Pico-EZmate_Slim series connector, 202656-0021 (http://www.molex.com/pdm_docs/sd/2026560021_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-EZmate_Slim side entry +0 +4 +3 +Connector_Molex +Molex_Pico-Lock_504050-0491_1x04-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-0491 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +6 +5 +Connector_Molex +Molex_Pico-Lock_504050-0591_1x05-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-0591 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +7 +6 +Connector_Molex +Molex_Pico-Lock_504050-0691_1x06-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-0691 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +8 +7 +Connector_Molex +Molex_Pico-Lock_504050-0791_1x07-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-0791 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +9 +8 +Connector_Molex +Molex_Pico-Lock_504050-0891_1x08-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-0891 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +10 +9 +Connector_Molex +Molex_Pico-Lock_504050-1091_1x10-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-1091 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +12 +11 +Connector_Molex +Molex_Pico-Lock_504050-1291_1x12-1MP_P1.50mm_Horizontal +Molex Pico-Lock series connector, 504050-1291 (http://www.molex.com/pdm_docs/sd/5040500891_sd.pdf), generated with kicad-footprint-generator +connector Molex Pico-Lock top entry +0 +14 +13 +Connector_Molex +Molex_PicoBlade_53047-0210_1x02_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0210, 2 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +2 +2 +Connector_Molex +Molex_PicoBlade_53047-0310_1x03_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0310, 3 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +3 +3 +Connector_Molex +Molex_PicoBlade_53047-0410_1x04_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0410, 4 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +4 +4 +Connector_Molex +Molex_PicoBlade_53047-0510_1x05_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +5 +5 +Connector_Molex +Molex_PicoBlade_53047-0610_1x06_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0610, 6 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +6 +6 +Connector_Molex +Molex_PicoBlade_53047-0710_1x07_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0710, 7 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +7 +7 +Connector_Molex +Molex_PicoBlade_53047-0810_1x08_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0810, 8 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +8 +8 +Connector_Molex +Molex_PicoBlade_53047-0910_1x09_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-0910, 9 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +9 +9 +Connector_Molex +Molex_PicoBlade_53047-1010_1x10_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-1010, 10 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +10 +10 +Connector_Molex +Molex_PicoBlade_53047-1110_1x11_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-1110, 11 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +11 +11 +Connector_Molex +Molex_PicoBlade_53047-1210_1x12_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-1210, 12 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +12 +12 +Connector_Molex +Molex_PicoBlade_53047-1310_1x13_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-1310, 13 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +13 +13 +Connector_Molex +Molex_PicoBlade_53047-1410_1x14_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-1410, 14 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +14 +14 +Connector_Molex +Molex_PicoBlade_53047-1510_1x15_P1.25mm_Vertical +Molex PicoBlade Connector System, 53047-1510, 15 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +15 +15 +Connector_Molex +Molex_PicoBlade_53048-0210_1x02_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0210, 2 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +2 +2 +Connector_Molex +Molex_PicoBlade_53048-0310_1x03_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0310, 3 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +3 +3 +Connector_Molex +Molex_PicoBlade_53048-0410_1x04_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0410, 4 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +4 +4 +Connector_Molex +Molex_PicoBlade_53048-0510_1x05_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +5 +5 +Connector_Molex +Molex_PicoBlade_53048-0610_1x06_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0610, 6 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +6 +6 +Connector_Molex +Molex_PicoBlade_53048-0710_1x07_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0710, 7 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +7 +7 +Connector_Molex +Molex_PicoBlade_53048-0810_1x08_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0810, 8 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +8 +8 +Connector_Molex +Molex_PicoBlade_53048-0910_1x09_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-0910, 9 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +9 +9 +Connector_Molex +Molex_PicoBlade_53048-1010_1x10_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-1010, 10 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +10 +10 +Connector_Molex +Molex_PicoBlade_53048-1110_1x11_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-1110, 11 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +11 +11 +Connector_Molex +Molex_PicoBlade_53048-1210_1x12_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-1210, 12 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +12 +12 +Connector_Molex +Molex_PicoBlade_53048-1310_1x13_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-1310, 13 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +13 +13 +Connector_Molex +Molex_PicoBlade_53048-1410_1x14_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-1410, 14 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +14 +14 +Connector_Molex +Molex_PicoBlade_53048-1510_1x15_P1.25mm_Horizontal +Molex PicoBlade Connector System, 53048-1510, 15 Pins per row (http://www.molex.com/pdm_docs/sd/530480210_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +15 +15 +Connector_Molex +Molex_PicoBlade_53261-0271_1x02-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +4 +3 +Connector_Molex +Molex_PicoBlade_53261-0371_1x03-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0371 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +5 +4 +Connector_Molex +Molex_PicoBlade_53261-0471_1x04-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0471 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +6 +5 +Connector_Molex +Molex_PicoBlade_53261-0571_1x05-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0571 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +7 +6 +Connector_Molex +Molex_PicoBlade_53261-0671_1x06-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0671 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +8 +7 +Connector_Molex +Molex_PicoBlade_53261-0771_1x07-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +9 +8 +Connector_Molex +Molex_PicoBlade_53261-0871_1x08-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0871 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +10 +9 +Connector_Molex +Molex_PicoBlade_53261-0971_1x09-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-0971 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +11 +10 +Connector_Molex +Molex_PicoBlade_53261-1071_1x10-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1071 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +12 +11 +Connector_Molex +Molex_PicoBlade_53261-1171_1x11-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1171 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +13 +12 +Connector_Molex +Molex_PicoBlade_53261-1271_1x12-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +14 +13 +Connector_Molex +Molex_PicoBlade_53261-1371_1x13-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1371 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +15 +14 +Connector_Molex +Molex_PicoBlade_53261-1471_1x14-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1471 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +16 +15 +Connector_Molex +Molex_PicoBlade_53261-1571_1x15-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1571 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +17 +16 +Connector_Molex +Molex_PicoBlade_53261-1771_1x17-1MP_P1.25mm_Horizontal +Molex PicoBlade series connector, 53261-1771 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade top entry +0 +19 +18 +Connector_Molex +Molex_PicoBlade_53398-0271_1x02-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0271 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +4 +3 +Connector_Molex +Molex_PicoBlade_53398-0371_1x03-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0371 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +5 +4 +Connector_Molex +Molex_PicoBlade_53398-0471_1x04-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0471 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +6 +5 +Connector_Molex +Molex_PicoBlade_53398-0571_1x05-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +7 +6 +Connector_Molex +Molex_PicoBlade_53398-0671_1x06-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0671 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +8 +7 +Connector_Molex +Molex_PicoBlade_53398-0771_1x07-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0771 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +9 +8 +Connector_Molex +Molex_PicoBlade_53398-0871_1x08-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0871 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +10 +9 +Connector_Molex +Molex_PicoBlade_53398-0971_1x09-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-0971 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +11 +10 +Connector_Molex +Molex_PicoBlade_53398-1071_1x10-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-1071 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +12 +11 +Connector_Molex +Molex_PicoBlade_53398-1171_1x11-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-1171 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +13 +12 +Connector_Molex +Molex_PicoBlade_53398-1271_1x12-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-1271 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +14 +13 +Connector_Molex +Molex_PicoBlade_53398-1371_1x13-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-1371 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +15 +14 +Connector_Molex +Molex_PicoBlade_53398-1471_1x14-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-1471 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +16 +15 +Connector_Molex +Molex_PicoBlade_53398-1571_1x15-1MP_P1.25mm_Vertical +Molex PicoBlade series connector, 53398-1571 (http://www.molex.com/pdm_docs/sd/533980271_sd.pdf), generated with kicad-footprint-generator +connector Molex PicoBlade side entry +0 +17 +16 +Connector_Molex +Molex_Picoflex_90325-0004_2x02_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0004, 4 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +4 +4 +Connector_Molex +Molex_Picoflex_90325-0006_2x03_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0006, 6 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +6 +6 +Connector_Molex +Molex_Picoflex_90325-0008_2x04_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0008, 8 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +8 +8 +Connector_Molex +Molex_Picoflex_90325-0010_2x05_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0010, 10 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +10 +10 +Connector_Molex +Molex_Picoflex_90325-0012_2x06_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0012, 12 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +12 +12 +Connector_Molex +Molex_Picoflex_90325-0014_2x07_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +14 +14 +Connector_Molex +Molex_Picoflex_90325-0016_2x08_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0016, 16 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +16 +16 +Connector_Molex +Molex_Picoflex_90325-0018_2x09_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0018, 18 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +18 +18 +Connector_Molex +Molex_Picoflex_90325-0020_2x10_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0020, 20 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +20 +20 +Connector_Molex +Molex_Picoflex_90325-0022_2x11_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0022, 22 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +22 +22 +Connector_Molex +Molex_Picoflex_90325-0024_2x12_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0024, 24 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +24 +24 +Connector_Molex +Molex_Picoflex_90325-0026_2x13_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90325-0026, 26 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +26 +26 +Connector_Molex +Molex_Picoflex_90814-0004_2x02_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0004, 4 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +4 +4 +Connector_Molex +Molex_Picoflex_90814-0006_2x03_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0006, 6 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +6 +6 +Connector_Molex +Molex_Picoflex_90814-0008_2x04_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0008, 8 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +8 +8 +Connector_Molex +Molex_Picoflex_90814-0010_2x05_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0010, 10 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +10 +10 +Connector_Molex +Molex_Picoflex_90814-0012_2x06_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0012, 12 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +12 +12 +Connector_Molex +Molex_Picoflex_90814-0014_2x07_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +14 +14 +Connector_Molex +Molex_Picoflex_90814-0016_2x08_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0016, 16 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +16 +16 +Connector_Molex +Molex_Picoflex_90814-0018_2x09_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0018, 18 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +18 +18 +Connector_Molex +Molex_Picoflex_90814-0020_2x10_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0020, 20 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +20 +20 +Connector_Molex +Molex_Picoflex_90814-0022_2x11_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0022, 22 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +22 +22 +Connector_Molex +Molex_Picoflex_90814-0024_2x12_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0024, 24 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +24 +24 +Connector_Molex +Molex_Picoflex_90814-0026_2x13_P1.27mm_Vertical +Molex Picoflex Ribbon-Cable Connectors, 90814-0026, 26 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator +connector Molex Picoflex side entry +0 +26 +26 +Connector_Molex +Molex_SL_171971-0002_1x02_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0002 (compatible alternatives: 171971-0102, 171971-0202), 2 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +2 +2 +Connector_Molex +Molex_SL_171971-0003_1x03_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0003 (compatible alternatives: 171971-0103, 171971-0203), 3 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +3 +3 +Connector_Molex +Molex_SL_171971-0004_1x04_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0004 (compatible alternatives: 171971-0104, 171971-0204), 4 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +4 +4 +Connector_Molex +Molex_SL_171971-0005_1x05_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0005 (compatible alternatives: 171971-0105, 171971-0205), 5 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +5 +5 +Connector_Molex +Molex_SL_171971-0006_1x06_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0006 (compatible alternatives: 171971-0106, 171971-0206), 6 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +6 +6 +Connector_Molex +Molex_SL_171971-0007_1x07_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0007 (compatible alternatives: 171971-0107, 171971-0207), 7 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +7 +7 +Connector_Molex +Molex_SL_171971-0008_1x08_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0008 (compatible alternatives: 171971-0108, 171971-0208), 8 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +8 +8 +Connector_Molex +Molex_SL_171971-0009_1x09_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0009 (compatible alternatives: 171971-0109, 171971-0209), 9 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +9 +9 +Connector_Molex +Molex_SL_171971-0010_1x10_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0010 (compatible alternatives: 171971-0110, 171971-0210), 10 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +10 +10 +Connector_Molex +Molex_SL_171971-0011_1x11_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0011 (compatible alternatives: 171971-0111, 171971-0211), 11 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +11 +11 +Connector_Molex +Molex_SL_171971-0012_1x12_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0012 (compatible alternatives: 171971-0112, 171971-0212), 12 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +12 +12 +Connector_Molex +Molex_SL_171971-0013_1x13_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0013 (compatible alternatives: 171971-0113, 171971-0213), 13 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +13 +13 +Connector_Molex +Molex_SL_171971-0014_1x14_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0014 (compatible alternatives: 171971-0114, 171971-0214), 14 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +14 +14 +Connector_Molex +Molex_SL_171971-0015_1x15_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0015 (compatible alternatives: 171971-0115, 171971-0215), 15 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +15 +15 +Connector_Molex +Molex_SL_171971-0016_1x16_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0016 (compatible alternatives: 171971-0116, 171971-0216), 16 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +16 +16 +Connector_Molex +Molex_SL_171971-0017_1x17_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0017 (compatible alternatives: 171971-0117, 171971-0217), 17 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +17 +17 +Connector_Molex +Molex_SL_171971-0018_1x18_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0018 (compatible alternatives: 171971-0118, 171971-0218), 18 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +18 +18 +Connector_Molex +Molex_SL_171971-0019_1x19_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0019 (compatible alternatives: 171971-0119, 171971-0219), 19 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +19 +19 +Connector_Molex +Molex_SL_171971-0020_1x20_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0020 (compatible alternatives: 171971-0120, 171971-0220), 20 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +20 +20 +Connector_Molex +Molex_SL_171971-0021_1x21_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0021 (compatible alternatives: 171971-0121, 171971-0221), 21 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +21 +21 +Connector_Molex +Molex_SL_171971-0022_1x22_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0022 (compatible alternatives: 171971-0122, 171971-0222), 22 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +22 +22 +Connector_Molex +Molex_SL_171971-0023_1x23_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0023 (compatible alternatives: 171971-0123, 171971-0223), 23 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +23 +23 +Connector_Molex +Molex_SL_171971-0024_1x24_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0024 (compatible alternatives: 171971-0124, 171971-0224), 24 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +24 +24 +Connector_Molex +Molex_SL_171971-0025_1x25_P2.54mm_Vertical +Molex Stackable Linear Connector, 171971-0025 (compatible alternatives: 171971-0125, 171971-0225), 25 Pins per row (https://www.molex.com/pdm_docs/sd/1719710002_sd.pdf), generated with kicad-footprint-generator +connector Molex SL vertical +0 +25 +25 +Connector_Molex +Molex_SPOX_5267-02A_1x02_P2.50mm_Vertical +Molex SPOX Connector System, 5267-02A, 2 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +2 +2 +Connector_Molex +Molex_SPOX_5267-03A_1x03_P2.50mm_Vertical +Molex SPOX Connector System, 5267-03A, 3 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +3 +3 +Connector_Molex +Molex_SPOX_5267-04A_1x04_P2.50mm_Vertical +Molex SPOX Connector System, 5267-04A, 4 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +4 +4 +Connector_Molex +Molex_SPOX_5267-05A_1x05_P2.50mm_Vertical +Molex SPOX Connector System, 5267-05A, 5 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +5 +5 +Connector_Molex +Molex_SPOX_5267-06A_1x06_P2.50mm_Vertical +Molex SPOX Connector System, 5267-06A, 6 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +6 +6 +Connector_Molex +Molex_SPOX_5267-07A_1x07_P2.50mm_Vertical +Molex SPOX Connector System, 5267-07A, 7 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +7 +7 +Connector_Molex +Molex_SPOX_5267-08A_1x08_P2.50mm_Vertical +Molex SPOX Connector System, 5267-08A, 8 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +8 +8 +Connector_Molex +Molex_SPOX_5267-09A_1x09_P2.50mm_Vertical +Molex SPOX Connector System, 5267-09A, 9 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +9 +9 +Connector_Molex +Molex_SPOX_5267-10A_1x10_P2.50mm_Vertical +Molex SPOX Connector System, 5267-10A, 10 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +10 +10 +Connector_Molex +Molex_SPOX_5267-11A_1x11_P2.50mm_Vertical +Molex SPOX Connector System, 5267-11A, 11 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +11 +11 +Connector_Molex +Molex_SPOX_5267-12A_1x12_P2.50mm_Vertical +Molex SPOX Connector System, 5267-12A, 12 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +12 +12 +Connector_Molex +Molex_SPOX_5267-13A_1x13_P2.50mm_Vertical +Molex SPOX Connector System, 5267-13A, 13 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +13 +13 +Connector_Molex +Molex_SPOX_5267-14A_1x14_P2.50mm_Vertical +Molex SPOX Connector System, 5267-14A, 14 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +14 +14 +Connector_Molex +Molex_SPOX_5267-15A_1x15_P2.50mm_Vertical +Molex SPOX Connector System, 5267-15A, 15 Pins per row (http://www.molex.com/pdm_docs/sd/022035035_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX side entry +0 +15 +15 +Connector_Molex +Molex_SPOX_5268-02A_1x02_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-02A, 2 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +2 +2 +Connector_Molex +Molex_SPOX_5268-03A_1x03_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-03A, 3 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +3 +3 +Connector_Molex +Molex_SPOX_5268-04A_1x04_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-04A, 4 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +4 +4 +Connector_Molex +Molex_SPOX_5268-05A_1x05_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-05A, 5 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +5 +5 +Connector_Molex +Molex_SPOX_5268-06A_1x06_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-06A, 6 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +6 +6 +Connector_Molex +Molex_SPOX_5268-07A_1x07_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-07A, 7 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +7 +7 +Connector_Molex +Molex_SPOX_5268-08A_1x08_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-08A, 8 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +8 +8 +Connector_Molex +Molex_SPOX_5268-09A_1x09_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-09A, 9 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +9 +9 +Connector_Molex +Molex_SPOX_5268-10A_1x10_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-10A, 10 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +10 +10 +Connector_Molex +Molex_SPOX_5268-11A_1x11_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-11A, 11 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +11 +11 +Connector_Molex +Molex_SPOX_5268-12A_1x12_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-12A, 12 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +12 +12 +Connector_Molex +Molex_SPOX_5268-13A_1x13_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-13A, 13 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +13 +13 +Connector_Molex +Molex_SPOX_5268-14A_1x14_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-14A, 14 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +14 +14 +Connector_Molex +Molex_SPOX_5268-15A_1x15_P2.50mm_Horizontal +Molex SPOX Connector System, 5268-15A, 15 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator +connector Molex SPOX horizontal +0 +15 +15 +Connector_Molex +Molex_Sabre_43160-0102_1x02_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-0102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +4 +2 +Connector_Molex +Molex_Sabre_43160-0102_1x02_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-0102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +30 +2 +Connector_Molex +Molex_Sabre_43160-0103_1x03_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-0103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +6 +3 +Connector_Molex +Molex_Sabre_43160-0103_1x03_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-0103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +45 +3 +Connector_Molex +Molex_Sabre_43160-0104_1x04_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-0104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +8 +4 +Connector_Molex +Molex_Sabre_43160-0104_1x04_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-0104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +60 +4 +Connector_Molex +Molex_Sabre_43160-0105_1x05_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-0105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +10 +5 +Connector_Molex +Molex_Sabre_43160-0105_1x05_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-0105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +75 +5 +Connector_Molex +Molex_Sabre_43160-0106_1x06_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-0106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +12 +6 +Connector_Molex +Molex_Sabre_43160-0106_1x06_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-0106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431600105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +90 +6 +Connector_Molex +Molex_Sabre_43160-1102_1x02_P7.49mm_Horizontal +Molex Sabre Power Connector, 43160-1102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +6 +2 +Connector_Molex +Molex_Sabre_43160-1102_1x02_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 43160-1102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +32 +2 +Connector_Molex +Molex_Sabre_43160-1103_1x03_P7.49mm_Horizontal +Molex Sabre Power Connector, 43160-1103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +8 +3 +Connector_Molex +Molex_Sabre_43160-1103_1x03_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 43160-1103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +47 +3 +Connector_Molex +Molex_Sabre_43160-1104_1x04_P7.49mm_Horizontal +Molex Sabre Power Connector, 43160-1104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +10 +4 +Connector_Molex +Molex_Sabre_43160-1104_1x04_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 43160-1104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +62 +4 +Connector_Molex +Molex_Sabre_43160-1105_1x05_P7.49mm_Horizontal +Molex Sabre Power Connector, 43160-1105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +12 +5 +Connector_Molex +Molex_Sabre_43160-1105_1x05_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 43160-1105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +77 +5 +Connector_Molex +Molex_Sabre_43160-1106_1x06_P7.49mm_Horizontal +Molex Sabre Power Connector, 43160-1106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +14 +6 +Connector_Molex +Molex_Sabre_43160-1106_1x06_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 43160-1106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431605304_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +92 +6 +Connector_Molex +Molex_Sabre_43160-2102_1x02_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-2102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +6 +2 +Connector_Molex +Molex_Sabre_43160-2102_1x02_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-2102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +32 +2 +Connector_Molex +Molex_Sabre_43160-2103_1x03_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-2103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +8 +3 +Connector_Molex +Molex_Sabre_43160-2103_1x03_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-2103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +47 +3 +Connector_Molex +Molex_Sabre_43160-2104_1x04_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-2104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +10 +4 +Connector_Molex +Molex_Sabre_43160-2104_1x04_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-2104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +62 +4 +Connector_Molex +Molex_Sabre_43160-2105_1x05_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-2105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +12 +5 +Connector_Molex +Molex_Sabre_43160-2105_1x05_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-2105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +77 +5 +Connector_Molex +Molex_Sabre_43160-2106_1x06_P7.49mm_Vertical +Molex Sabre Power Connector, 43160-2106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +14 +6 +Connector_Molex +Molex_Sabre_43160-2106_1x06_P7.49mm_Vertical_ThermalVias +Molex Sabre Power Connector, 43160-2106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/431602102_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre side entry +0 +92 +6 +Connector_Molex +Molex_Sabre_46007-1102_1x02_P7.49mm_Horizontal +Molex Sabre Power Connector, 46007-1102, 2 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +4 +2 +Connector_Molex +Molex_Sabre_46007-1102_1x02_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 46007-1102, With thermal vias in pads, 2 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +30 +2 +Connector_Molex +Molex_Sabre_46007-1103_1x03_P7.49mm_Horizontal +Molex Sabre Power Connector, 46007-1103, 3 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +6 +3 +Connector_Molex +Molex_Sabre_46007-1103_1x03_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 46007-1103, With thermal vias in pads, 3 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +45 +3 +Connector_Molex +Molex_Sabre_46007-1104_1x04_P7.49mm_Horizontal +Molex Sabre Power Connector, 46007-1104, 4 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +8 +4 +Connector_Molex +Molex_Sabre_46007-1104_1x04_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 46007-1104, With thermal vias in pads, 4 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +60 +4 +Connector_Molex +Molex_Sabre_46007-1105_1x05_P7.49mm_Horizontal +Molex Sabre Power Connector, 46007-1105, 5 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +10 +5 +Connector_Molex +Molex_Sabre_46007-1105_1x05_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 46007-1105, With thermal vias in pads, 5 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +75 +5 +Connector_Molex +Molex_Sabre_46007-1106_1x06_P7.49mm_Horizontal +Molex Sabre Power Connector, 46007-1106, 6 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +12 +6 +Connector_Molex +Molex_Sabre_46007-1106_1x06_P7.49mm_Horizontal_ThermalVias +Molex Sabre Power Connector, 46007-1106, With thermal vias in pads, 6 Pins per row (http://www.molex.com/pdm_docs/sd/460071105_sd.pdf), generated with kicad-footprint-generator +connector Molex Sabre top entry +0 +90 +6 +Connector_Molex +Molex_SlimStack_52991-0208_2x10_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0208, 20 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +20 +20 +Connector_Molex +Molex_SlimStack_52991-0308_2x15_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0308, 30 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +30 +30 +Connector_Molex +Molex_SlimStack_52991-0408_2x20_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0408, 40 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +40 +40 +Connector_Molex +Molex_SlimStack_52991-0508_2x25_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0508, 50 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +50 +50 +Connector_Molex +Molex_SlimStack_52991-0608_2x30_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0608, 60 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +60 +60 +Connector_Molex +Molex_SlimStack_52991-0708_2x35_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0708, 70 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +70 +70 +Connector_Molex +Molex_SlimStack_52991-0808_2x40_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 52991-0808, 80 Pins (http://www.molex.com/pdm_docs/sd/529910308_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack vertical +0 +80 +80 +Connector_Molex +Molex_SlimStack_54722-0164_2x08_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0164, 16 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +16 +16 +Connector_Molex +Molex_SlimStack_54722-0204_2x10_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0204, 20 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +20 +20 +Connector_Molex +Molex_SlimStack_54722-0224_2x11_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0224, 22 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +22 +22 +Connector_Molex +Molex_SlimStack_54722-0244_2x12_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0244, 24 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +24 +24 +Connector_Molex +Molex_SlimStack_54722-0304_2x15_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0304, 30 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +30 +30 +Connector_Molex +Molex_SlimStack_54722-0344_2x17_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0344, 34 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +34 +34 +Connector_Molex +Molex_SlimStack_54722-0404_2x20_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0404, 40 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +40 +40 +Connector_Molex +Molex_SlimStack_54722-0504_2x25_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0504, 50 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +50 +50 +Connector_Molex +Molex_SlimStack_54722-0604_2x30_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0604, 60 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +60 +60 +Connector_Molex +Molex_SlimStack_54722-0804_2x40_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 54722-0804, 80 Pins (http://www.molex.com/pdm_docs/sd/547220804_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +80 +80 +Connector_Molex +Molex_SlimStack_55560-0161_2x08_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0161, 16 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +16 +16 +Connector_Molex +Molex_SlimStack_55560-0201_2x10_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0201, 20 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +20 +20 +Connector_Molex +Molex_SlimStack_55560-0221_2x11_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0221, 22 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +22 +22 +Connector_Molex +Molex_SlimStack_55560-0241_2x12_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0241, 24 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +24 +24 +Connector_Molex +Molex_SlimStack_55560-0301_2x15_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0301, 30 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +30 +30 +Connector_Molex +Molex_SlimStack_55560-0341_2x17_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0341, 34 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +34 +34 +Connector_Molex +Molex_SlimStack_55560-0401_2x20_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0401, 40 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +40 +40 +Connector_Molex +Molex_SlimStack_55560-0501_2x25_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0501, 50 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +50 +50 +Connector_Molex +Molex_SlimStack_55560-0601_2x30_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0601, 60 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +60 +60 +Connector_Molex +Molex_SlimStack_55560-0801_2x40_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 55560-0801, 80 Pins (http://www.molex.com/pdm_docs/sd/555600207_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +80 +80 +Connector_Molex +Molex_SlimStack_501920-3001_2x15_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-3001, 30 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +30 +30 +Connector_Molex +Molex_SlimStack_501920-4001_2x20_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-4001, 40 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +40 +40 +Connector_Molex +Molex_SlimStack_501920-5001_2x25_P0.50mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 501920-5001, 50 Pins (http://www.molex.com/pdm_docs/sd/5019204001_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +50 +50 +Connector_Molex +Molex_SlimStack_502426-0810_2x04_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-0810, 8 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +8 +8 +Connector_Molex +Molex_SlimStack_502426-1410_2x07_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-1410, 14 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +14 +14 +Connector_Molex +Molex_SlimStack_502426-2010_2x10_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2010, 20 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +20 +20 +Connector_Molex +Molex_SlimStack_502426-2210_2x11_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2210, 22 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +22 +22 +Connector_Molex +Molex_SlimStack_502426-2410_2x12_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2410, 24 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +24 +24 +Connector_Molex +Molex_SlimStack_502426-2610_2x13_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-2610, 26 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +26 +26 +Connector_Molex +Molex_SlimStack_502426-3010_2x15_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3010, 30 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +30 +30 +Connector_Molex +Molex_SlimStack_502426-3210_2x16_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3210, 32 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +32 +32 +Connector_Molex +Molex_SlimStack_502426-3410_2x17_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-3410, 34 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +34 +34 +Connector_Molex +Molex_SlimStack_502426-4010_2x20_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-4010, 40 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +40 +40 +Connector_Molex +Molex_SlimStack_502426-4410_2x22_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-4410, 44 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +44 +44 +Connector_Molex +Molex_SlimStack_502426-5010_2x25_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-5010, 50 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +50 +50 +Connector_Molex +Molex_SlimStack_502426-6010_2x30_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-6010, 60 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +60 +60 +Connector_Molex +Molex_SlimStack_502426-6410_2x32_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-6410, 64 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +64 +64 +Connector_Molex +Molex_SlimStack_502426-8010_2x40_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502426-8010, 80 Pins (http://www.molex.com/pdm_docs/sd/5024260810_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +80 +80 +Connector_Molex +Molex_SlimStack_502430-0820_2x04_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-0820, 8 Pins (http://www.molex.com/pdm_docs/sd/5024300820_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +8 +8 +Connector_Molex +Molex_SlimStack_502430-1410_2x07_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-1410, 14 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +14 +14 +Connector_Molex +Molex_SlimStack_502430-2010_2x10_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2010, 20 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +20 +20 +Connector_Molex +Molex_SlimStack_502430-2210_2x11_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2210, 22 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +22 +22 +Connector_Molex +Molex_SlimStack_502430-2410_2x12_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2410, 24 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +24 +24 +Connector_Molex +Molex_SlimStack_502430-2610_2x13_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-2610, 26 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +26 +26 +Connector_Molex +Molex_SlimStack_502430-3010_2x15_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3010, 30 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +30 +30 +Connector_Molex +Molex_SlimStack_502430-3210_2x16_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3210, 32 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +32 +32 +Connector_Molex +Molex_SlimStack_502430-3410_2x17_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-3410, 34 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +34 +34 +Connector_Molex +Molex_SlimStack_502430-4010_2x20_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-4010, 40 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +40 +40 +Connector_Molex +Molex_SlimStack_502430-4410_2x22_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-4410, 44 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +44 +44 +Connector_Molex +Molex_SlimStack_502430-5010_2x25_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-5010, 50 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +50 +50 +Connector_Molex +Molex_SlimStack_502430-6010_2x30_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-6010, 60 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +60 +60 +Connector_Molex +Molex_SlimStack_502430-6410_2x32_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-6410, 64 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +64 +64 +Connector_Molex +Molex_SlimStack_502430-8010_2x40_P0.40mm_Vertical +Molex SlimStack Fine-Pitch SMT Board-to-Board Connectors, 502430-8010, 80 Pins (http://www.molex.com/pdm_docs/sd/5024301410_sd.pdf), generated with kicad-footprint-generator +connector Molex SlimStack side entry +0 +80 +80 +Connector_Multicomp +Multicomp_MC9A12-1034_2x05_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +10 +10 +Connector_Multicomp +Multicomp_MC9A12-1434_2x07_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +14 +14 +Connector_Multicomp +Multicomp_MC9A12-1634_2x08_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +16 +16 +Connector_Multicomp +Multicomp_MC9A12-2034_2x10_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +20 +20 +Connector_Multicomp +Multicomp_MC9A12-2634_2x13_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +26 +26 +Connector_Multicomp +Multicomp_MC9A12-3434_2x17_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +34 +34 +Connector_Multicomp +Multicomp_MC9A12-4034_2x20_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +40 +40 +Connector_Multicomp +Multicomp_MC9A12-5034_2x25_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +50 +50 +Connector_Multicomp +Multicomp_MC9A12-6034_2x30_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +60 +60 +Connector_Multicomp +Multicomp_MC9A12-6434_2x32_P2.54mm_Vertical +http://www.farnell.com/datasheets/1520732.pdf +connector multicomp MC9A MC9A12 +0 +64 +64 +Connector_Multicomp +Multicomp_MC9A22-1034_2x05_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +10 +10 +Connector_Multicomp +Multicomp_MC9A22-1434_2x07_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +14 +14 +Connector_Multicomp +Multicomp_MC9A22-1634_2x08_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +16 +16 +Connector_Multicomp +Multicomp_MC9A22-2034_2x10_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +20 +20 +Connector_Multicomp +Multicomp_MC9A22-2634_2x13_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +26 +26 +Connector_Multicomp +Multicomp_MC9A22-3434_2x17_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +34 +34 +Connector_Multicomp +Multicomp_MC9A22-4034_2x20_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +40 +40 +Connector_Multicomp +Multicomp_MC9A22-5034_2x25_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +50 +50 +Connector_Multicomp +Multicomp_MC9A22-6034_2x30_P2.54mm_Horizontal +http://www.farnell.com/cad/360651.pdf +connector multicomp MC9A MC9A22 +0 +60 +60 +Connector_PCBEdge +4UCON_10156_2x40_P1.27mm_Socket_Horizontal +4UCON 10156 Card edge socket with 80 contacts (40 each side), through-hole, http://www.4uconnector.com/online/object/4udrawing/10156.pdf +4UCON 10156 Card edge socket with 80 contacts +0 +80 +80 +Connector_PCBEdge +BUS_AT +AT ISA 16 bits Bus Edge Connector +BUS ISA AT Edge connector +0 +98 +98 +Connector_PCBEdge +BUS_PCI +PCI bus Edge Connector +PCI bus Edge Connector +0 +240 +120 +Connector_PCBEdge +BUS_PCIexpress_x1 +PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 +PCIe +0 +36 +36 +Connector_PCBEdge +BUS_PCIexpress_x4 +PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 +PCIe +0 +64 +64 +Connector_PCBEdge +BUS_PCIexpress_x8 +PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 +PCIe +0 +98 +98 +Connector_PCBEdge +BUS_PCIexpress_x16 +PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70 +PCIe +0 +164 +164 +Connector_PCBEdge +Samtec_MECF-05-0_-L-DV_2x05_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 05 contacts (polarized) +conn samtec card-edge high-speed +0 +8 +8 +Connector_PCBEdge +Samtec_MECF-05-0_-NP-L-DV_2x05_P1.27mm_Edge +Highspeed card edge connector for PCB's with 05 contacts (not polarized) +conn samtec card-edge high-speed +0 +10 +10 +Connector_PCBEdge +Samtec_MECF-05-01-L-DV-WT_2x05_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 05 contacts (polarized) +conn samtec card-edge high-speed +0 +10 +8 +Connector_PCBEdge +Samtec_MECF-05-01-L-DV_2x05_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 05 contacts (polarized) +conn samtec card-edge high-speed +0 +8 +8 +Connector_PCBEdge +Samtec_MECF-05-01-NP-L-DV-WT_2x05_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 05 contacts (not polarized) +conn samtec card-edge high-speed +0 +12 +10 +Connector_PCBEdge +Samtec_MECF-05-01-NP-L-DV_2x05_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 05 contacts (not polarized) +conn samtec card-edge high-speed +0 +10 +10 +Connector_PCBEdge +Samtec_MECF-05-02-L-DV-WT_2x05_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized) +conn samtec card-edge high-speed +0 +10 +8 +Connector_PCBEdge +Samtec_MECF-05-02-L-DV_2x05_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 05 contacts (polarized) +conn samtec card-edge high-speed +0 +8 +8 +Connector_PCBEdge +Samtec_MECF-05-02-NP-L-DV-WT_2x05_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 05 contacts (not polarized) +conn samtec card-edge high-speed +0 +12 +10 +Connector_PCBEdge +Samtec_MECF-05-02-NP-L-DV_2x05_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 05 contacts (not polarized) +conn samtec card-edge high-speed +0 +10 +10 +Connector_PCBEdge +Samtec_MECF-08-0_-L-DV_2x08_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 08 contacts (polarized) +conn samtec card-edge high-speed +0 +14 +14 +Connector_PCBEdge +Samtec_MECF-08-0_-NP-L-DV_2x08_P1.27mm_Edge +Highspeed card edge connector for PCB's with 08 contacts (not polarized) +conn samtec card-edge high-speed +0 +16 +16 +Connector_PCBEdge +Samtec_MECF-08-01-L-DV-WT_2x08_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 08 contacts (polarized) +conn samtec card-edge high-speed +0 +16 +14 +Connector_PCBEdge +Samtec_MECF-08-01-L-DV_2x08_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 08 contacts (polarized) +conn samtec card-edge high-speed +0 +14 +14 +Connector_PCBEdge +Samtec_MECF-08-01-NP-L-DV-WT_2x08_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 08 contacts (not polarized) +conn samtec card-edge high-speed +0 +18 +16 +Connector_PCBEdge +Samtec_MECF-08-01-NP-L-DV_2x08_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 08 contacts (not polarized) +conn samtec card-edge high-speed +0 +16 +16 +Connector_PCBEdge +Samtec_MECF-08-02-L-DV-WT_2x08_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 08 contacts (polarized) +conn samtec card-edge high-speed +0 +16 +14 +Connector_PCBEdge +Samtec_MECF-08-02-L-DV_2x08_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 08 contacts (polarized) +conn samtec card-edge high-speed +0 +14 +14 +Connector_PCBEdge +Samtec_MECF-08-02-NP-L-DV-WT_2x08_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized) +conn samtec card-edge high-speed +0 +18 +16 +Connector_PCBEdge +Samtec_MECF-08-02-NP-L-DV_2x08_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized) +conn samtec card-edge high-speed +0 +16 +16 +Connector_PCBEdge +Samtec_MECF-20-0_-L-DV_2x20_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 20 contacts (polarized) +conn samtec card-edge high-speed +0 +38 +38 +Connector_PCBEdge +Samtec_MECF-20-0_-NP-L-DV_2x20_P1.27mm_Edge +Highspeed card edge connector for PCB's with 20 contacts (not polarized) +conn samtec card-edge high-speed +0 +40 +40 +Connector_PCBEdge +Samtec_MECF-20-01-L-DV-WT_2x20_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 20 contacts (polarized) +conn samtec card-edge high-speed +0 +40 +38 +Connector_PCBEdge +Samtec_MECF-20-01-L-DV_2x20_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 20 contacts (polarized) +conn samtec card-edge high-speed +0 +38 +38 +Connector_PCBEdge +Samtec_MECF-20-01-NP-L-DV-WT_2x20_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 20 contacts (not polarized) +conn samtec card-edge high-speed +0 +42 +40 +Connector_PCBEdge +Samtec_MECF-20-01-NP-L-DV_2x20_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 20 contacts (not polarized) +conn samtec card-edge high-speed +0 +40 +40 +Connector_PCBEdge +Samtec_MECF-20-02-L-DV-WT_2x20_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 20 contacts (polarized) +conn samtec card-edge high-speed +0 +40 +38 +Connector_PCBEdge +Samtec_MECF-20-02-L-DV_2x20_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 20 contacts (polarized) +conn samtec card-edge high-speed +0 +38 +38 +Connector_PCBEdge +Samtec_MECF-20-02-NP-L-DV-WT_2x20_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 20 contacts (not polarized) +conn samtec card-edge high-speed +0 +42 +40 +Connector_PCBEdge +Samtec_MECF-20-02-NP-L-DV_2x20_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 20 contacts (not polarized) +conn samtec card-edge high-speed +0 +40 +40 +Connector_PCBEdge +Samtec_MECF-30-0_-L-DV_2x30_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 30 contacts (polarized) +conn samtec card-edge high-speed +0 +58 +58 +Connector_PCBEdge +Samtec_MECF-30-0_-NP-L-DV_2x30_P1.27mm_Edge +Highspeed card edge connector for PCB's with 30 contacts (not polarized) +conn samtec card-edge high-speed +0 +60 +60 +Connector_PCBEdge +Samtec_MECF-30-01-L-DV-WT_2x30_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized) +conn samtec card-edge high-speed +0 +60 +58 +Connector_PCBEdge +Samtec_MECF-30-01-L-DV_2x30_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 30 contacts (polarized) +conn samtec card-edge high-speed +0 +58 +58 +Connector_PCBEdge +Samtec_MECF-30-01-NP-L-DV-WT_2x30_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized) +conn samtec card-edge high-speed +0 +62 +60 +Connector_PCBEdge +Samtec_MECF-30-01-NP-L-DV_2x30_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized) +conn samtec card-edge high-speed +0 +60 +60 +Connector_PCBEdge +Samtec_MECF-30-02-L-DV-WT_2x30_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 30 contacts (polarized) +conn samtec card-edge high-speed +0 +60 +58 +Connector_PCBEdge +Samtec_MECF-30-02-L-DV_2x30_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 30 contacts (polarized) +conn samtec card-edge high-speed +0 +58 +58 +Connector_PCBEdge +Samtec_MECF-30-02-NP-L-DV-WT_2x30_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized) +conn samtec card-edge high-speed +0 +62 +60 +Connector_PCBEdge +Samtec_MECF-30-02-NP-L-DV_2x30_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 30 contacts (not polarized) +conn samtec card-edge high-speed +0 +60 +60 +Connector_PCBEdge +Samtec_MECF-40-0_-L-DV_2x40_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 40 contacts (polarized) +conn samtec card-edge high-speed +0 +78 +78 +Connector_PCBEdge +Samtec_MECF-40-0_-NP-L-DV_2x40_P1.27mm_Edge +Highspeed card edge connector for PCB's with 40 contacts (not polarized) +conn samtec card-edge high-speed +0 +80 +80 +Connector_PCBEdge +Samtec_MECF-40-01-L-DV-WT_2x40_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 40 contacts (polarized) +conn samtec card-edge high-speed +0 +80 +78 +Connector_PCBEdge +Samtec_MECF-40-01-L-DV_2x40_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 40 contacts (polarized) +conn samtec card-edge high-speed +0 +78 +78 +Connector_PCBEdge +Samtec_MECF-40-01-NP-L-DV-WT_2x40_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 40 contacts (not polarized) +conn samtec card-edge high-speed +0 +82 +80 +Connector_PCBEdge +Samtec_MECF-40-01-NP-L-DV_2x40_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 40 contacts (not polarized) +conn samtec card-edge high-speed +0 +80 +80 +Connector_PCBEdge +Samtec_MECF-40-02-L-DV-WT_2x40_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 40 contacts (polarized) +conn samtec card-edge high-speed +0 +80 +78 +Connector_PCBEdge +Samtec_MECF-40-02-L-DV_2x40_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 40 contacts (polarized) +conn samtec card-edge high-speed +0 +78 +78 +Connector_PCBEdge +Samtec_MECF-40-02-NP-L-DV-WT_2x40_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized) +conn samtec card-edge high-speed +0 +82 +80 +Connector_PCBEdge +Samtec_MECF-40-02-NP-L-DV_2x40_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 40 contacts (not polarized) +conn samtec card-edge high-speed +0 +80 +80 +Connector_PCBEdge +Samtec_MECF-50-0_-L-DV_2x50_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 50 contacts (polarized) +conn samtec card-edge high-speed +0 +98 +98 +Connector_PCBEdge +Samtec_MECF-50-0_-NP-L-DV_2x50_P1.27mm_Edge +Highspeed card edge connector for PCB's with 50 contacts (not polarized) +conn samtec card-edge high-speed +0 +100 +100 +Connector_PCBEdge +Samtec_MECF-50-01-L-DV-WT_2x50_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized) +conn samtec card-edge high-speed +0 +100 +98 +Connector_PCBEdge +Samtec_MECF-50-01-L-DV_2x50_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 50 contacts (polarized) +conn samtec card-edge high-speed +0 +98 +98 +Connector_PCBEdge +Samtec_MECF-50-01-NP-L-DV-WT_2x50_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 50 contacts (not polarized) +conn samtec card-edge high-speed +0 +102 +100 +Connector_PCBEdge +Samtec_MECF-50-01-NP-L-DV_2x50_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 50 contacts (not polarized) +conn samtec card-edge high-speed +0 +100 +100 +Connector_PCBEdge +Samtec_MECF-50-02-L-DV-WT_2x50_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 50 contacts (polarized) +conn samtec card-edge high-speed +0 +100 +98 +Connector_PCBEdge +Samtec_MECF-50-02-L-DV_2x50_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 50 contacts (polarized) +conn samtec card-edge high-speed +0 +98 +98 +Connector_PCBEdge +Samtec_MECF-50-02-NP-L-DV-WT_2x50_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 50 contacts (not polarized) +conn samtec card-edge high-speed +0 +102 +100 +Connector_PCBEdge +Samtec_MECF-50-02-NP-L-DV_2x50_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 50 contacts (not polarized) +conn samtec card-edge high-speed +0 +100 +100 +Connector_PCBEdge +Samtec_MECF-60-0_-L-DV_2x60_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 60 contacts (polarized) +conn samtec card-edge high-speed +0 +116 +116 +Connector_PCBEdge +Samtec_MECF-60-0_-NP-L-DV_2x60_P1.27mm_Edge +Highspeed card edge connector for PCB's with 60 contacts (not polarized) +conn samtec card-edge high-speed +0 +120 +120 +Connector_PCBEdge +Samtec_MECF-60-01-L-DV-WT_2x60_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 60 contacts (polarized) +conn samtec card-edge high-speed +0 +118 +116 +Connector_PCBEdge +Samtec_MECF-60-01-L-DV_2x60_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 60 contacts (polarized) +conn samtec card-edge high-speed +0 +116 +116 +Connector_PCBEdge +Samtec_MECF-60-01-NP-L-DV-WT_2x60_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 60 contacts (not polarized) +conn samtec card-edge high-speed +0 +122 +120 +Connector_PCBEdge +Samtec_MECF-60-01-NP-L-DV_2x60_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 60 contacts (not polarized) +conn samtec card-edge high-speed +0 +120 +120 +Connector_PCBEdge +Samtec_MECF-60-02-L-DV-WT_2x60_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 60 contacts (polarized) +conn samtec card-edge high-speed +0 +118 +116 +Connector_PCBEdge +Samtec_MECF-60-02-L-DV_2x60_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 60 contacts (polarized) +conn samtec card-edge high-speed +0 +116 +116 +Connector_PCBEdge +Samtec_MECF-60-02-NP-L-DV-WT_2x60_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 60 contacts (not polarized) +conn samtec card-edge high-speed +0 +122 +120 +Connector_PCBEdge +Samtec_MECF-60-02-NP-L-DV_2x60_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 60 contacts (not polarized) +conn samtec card-edge high-speed +0 +120 +120 +Connector_PCBEdge +Samtec_MECF-70-0_-L-DV_2x70_P1.27mm_Polarized_Edge +Highspeed card edge connector for PCB's with 70 contacts (polarized) +conn samtec card-edge high-speed +0 +136 +136 +Connector_PCBEdge +Samtec_MECF-70-0_-NP-L-DV_2x70_P1.27mm_Edge +Highspeed card edge connector for PCB's with 70 contacts (not polarized) +conn samtec card-edge high-speed +0 +140 +140 +Connector_PCBEdge +Samtec_MECF-70-01-L-DV-WT_2x70_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 70 contacts (polarized) +conn samtec card-edge high-speed +0 +138 +136 +Connector_PCBEdge +Samtec_MECF-70-01-L-DV_2x70_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 70 contacts (polarized) +conn samtec card-edge high-speed +0 +136 +136 +Connector_PCBEdge +Samtec_MECF-70-01-NP-L-DV-WT_2x70_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 70 contacts (not polarized) +conn samtec card-edge high-speed +0 +142 +140 +Connector_PCBEdge +Samtec_MECF-70-01-NP-L-DV_2x70_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 1.6mm PCB's with 70 contacts (not polarized) +conn samtec card-edge high-speed +0 +140 +140 +Connector_PCBEdge +Samtec_MECF-70-02-L-DV-WT_2x70_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 70 contacts (polarized) +conn samtec card-edge high-speed +0 +138 +136 +Connector_PCBEdge +Samtec_MECF-70-02-L-DV_2x70_P1.27mm_Polarized_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 70 contacts (polarized) +conn samtec card-edge high-speed +0 +136 +136 +Connector_PCBEdge +Samtec_MECF-70-02-NP-L-DV-WT_2x70_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 70 contacts (not polarized) +conn samtec card-edge high-speed +0 +142 +140 +Connector_PCBEdge +Samtec_MECF-70-02-NP-L-DV_2x70_P1.27mm_Socket_Horizontal +Highspeed card edge connector for 2.4mm PCB's with 70 contacts (not polarized) +conn samtec card-edge high-speed +0 +140 +140 +Connector_PCBEdge +molex_EDGELOCK_2-CKT +https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf +Connector PCBEdge molex EDGELOCK +0 +2 +2 +Connector_PCBEdge +molex_EDGELOCK_4-CKT +https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf +Connector PCBEdge molex EDGELOCK +0 +4 +4 +Connector_PCBEdge +molex_EDGELOCK_6-CKT +https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf +Connector PCBEdge molex EDGELOCK +0 +6 +6 +Connector_PCBEdge +molex_EDGELOCK_8-CKT +https://www.molex.com/pdm_docs/sd/2008900106_sd.pdf +Connector PCBEdge molex EDGELOCK +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_2-G-7,62_1x02_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/2-G-7,62; number of pins: 02; pin pitch: 7.62mm; Angled || order number: 1766233 12A 630V +phoenix_contact connector GMSTBA_01x02_G_7.62mm +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_2-G_1x02_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/2-G; number of pins: 02; pin pitch: 7.50mm; Angled || order number: 1766343 12A 630V +phoenix_contact connector GMSTBA_01x02_G_7.50mm +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_3-G-7,62_1x03_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/3-G-7,62; number of pins: 03; pin pitch: 7.62mm; Angled || order number: 1766246 12A 630V +phoenix_contact connector GMSTBA_01x03_G_7.62mm +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_3-G_1x03_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/3-G; number of pins: 03; pin pitch: 7.50mm; Angled || order number: 1766356 12A 630V +phoenix_contact connector GMSTBA_01x03_G_7.50mm +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_4-G-7,62_1x04_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/4-G-7,62; number of pins: 04; pin pitch: 7.62mm; Angled || order number: 1766259 12A 630V +phoenix_contact connector GMSTBA_01x04_G_7.62mm +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_4-G_1x04_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/4-G; number of pins: 04; pin pitch: 7.50mm; Angled || order number: 1766369 12A 630V +phoenix_contact connector GMSTBA_01x04_G_7.50mm +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_5-G-7,62_1x05_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/5-G-7,62; number of pins: 05; pin pitch: 7.62mm; Angled || order number: 1766262 12A 630V +phoenix_contact connector GMSTBA_01x05_G_7.62mm +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_5-G_1x05_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/5-G; number of pins: 05; pin pitch: 7.50mm; Angled || order number: 1766372 12A 630V +phoenix_contact connector GMSTBA_01x05_G_7.50mm +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_6-G-7,62_1x06_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/6-G-7,62; number of pins: 06; pin pitch: 7.62mm; Angled || order number: 1766275 12A 630V +phoenix_contact connector GMSTBA_01x06_G_7.62mm +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_6-G_1x06_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/6-G; number of pins: 06; pin pitch: 7.50mm; Angled || order number: 1766385 12A 630V +phoenix_contact connector GMSTBA_01x06_G_7.50mm +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_7-G-7,62_1x07_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/7-G-7,62; number of pins: 07; pin pitch: 7.62mm; Angled || order number: 1766288 12A 630V +phoenix_contact connector GMSTBA_01x07_G_7.62mm +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_7-G_1x07_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/7-G; number of pins: 07; pin pitch: 7.50mm; Angled || order number: 1766398 12A 630V +phoenix_contact connector GMSTBA_01x07_G_7.50mm +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_8-G-7,62_1x08_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/8-G-7,62; number of pins: 08; pin pitch: 7.62mm; Angled || order number: 1766291 12A 630V +phoenix_contact connector GMSTBA_01x08_G_7.62mm +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_8-G_1x08_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/8-G; number of pins: 08; pin pitch: 7.50mm; Angled || order number: 1766408 12A 630V +phoenix_contact connector GMSTBA_01x08_G_7.50mm +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_9-G-7,62_1x09_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/9-G-7,62; number of pins: 09; pin pitch: 7.62mm; Angled || order number: 1766301 12A 630V +phoenix_contact connector GMSTBA_01x09_G_7.62mm +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_9-G_1x09_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/9-G; number of pins: 09; pin pitch: 7.50mm; Angled || order number: 1766411 12A 630V +phoenix_contact connector GMSTBA_01x09_G_7.50mm +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_10-G-7,62_1x10_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/10-G-7,62; number of pins: 10; pin pitch: 7.62mm; Angled || order number: 1766314 12A 630V +phoenix_contact connector GMSTBA_01x10_G_7.62mm +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_10-G_1x10_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/10-G; number of pins: 10; pin pitch: 7.50mm; Angled || order number: 1766424 12A 630V +phoenix_contact connector GMSTBA_01x10_G_7.50mm +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_11-G-7,62_1x11_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/11-G-7,62; number of pins: 11; pin pitch: 7.62mm; Angled || order number: 1766327 12A 630V +phoenix_contact connector GMSTBA_01x11_G_7.62mm +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_11-G_1x11_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/11-G; number of pins: 11; pin pitch: 7.50mm; Angled || order number: 1766437 12A 630V +phoenix_contact connector GMSTBA_01x11_G_7.50mm +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_12-G-7,62_1x12_P7.62mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/12-G-7,62; number of pins: 12; pin pitch: 7.62mm; Angled || order number: 1766330 12A 630V +phoenix_contact connector GMSTBA_01x12_G_7.62mm +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBA_2,5_12-G_1x12_P7.50mm_Horizontal +Generic Phoenix Contact connector footprint for: GMSTBA_2,5/12-G; number of pins: 12; pin pitch: 7.50mm; Angled || order number: 1766440 12A 630V +phoenix_contact connector GMSTBA_01x12_G_7.50mm +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_2-G-7,62_1x02_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/2-G-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical || order number: 1766770 12A 630V +phoenix_contact connector GMSTBVA_01x02_G_7.62mm +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_2-G_1x02_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/2-G; number of pins: 02; pin pitch: 7.50mm; Vertical || order number: 1766660 12A 630V +phoenix_contact connector GMSTBVA_01x02_G_7.50mm +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_3-G-7,62_1x03_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/3-G-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical || order number: 1766783 12A 630V +phoenix_contact connector GMSTBVA_01x03_G_7.62mm +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_3-G_1x03_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/3-G; number of pins: 03; pin pitch: 7.50mm; Vertical || order number: 1766673 12A 630V +phoenix_contact connector GMSTBVA_01x03_G_7.50mm +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_4-G-7,62_1x04_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/4-G-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical || order number: 1766796 12A 630V +phoenix_contact connector GMSTBVA_01x04_G_7.62mm +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_4-G_1x04_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/4-G; number of pins: 04; pin pitch: 7.50mm; Vertical || order number: 1766686 12A 630V +phoenix_contact connector GMSTBVA_01x04_G_7.50mm +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_5-G-7,62_1x05_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/5-G-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical || order number: 1766806 12A 630V +phoenix_contact connector GMSTBVA_01x05_G_7.62mm +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_5-G_1x05_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/5-G; number of pins: 05; pin pitch: 7.50mm; Vertical || order number: 1766699 12A 630V +phoenix_contact connector GMSTBVA_01x05_G_7.50mm +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_6-G-7,62_1x06_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/6-G-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical || order number: 1766819 12A 630V +phoenix_contact connector GMSTBVA_01x06_G_7.62mm +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_6-G_1x06_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/6-G; number of pins: 06; pin pitch: 7.50mm; Vertical || order number: 1766709 12A 630V +phoenix_contact connector GMSTBVA_01x06_G_7.50mm +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_7-G-7,62_1x07_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/7-G-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical || order number: 1766822 12A 630V +phoenix_contact connector GMSTBVA_01x07_G_7.62mm +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_7-G_1x07_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/7-G; number of pins: 07; pin pitch: 7.50mm; Vertical || order number: 1766712 12A 630V +phoenix_contact connector GMSTBVA_01x07_G_7.50mm +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_8-G-7,62_1x08_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/8-G-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical || order number: 1766835 12A 630V +phoenix_contact connector GMSTBVA_01x08_G_7.62mm +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_8-G_1x08_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/8-G; number of pins: 08; pin pitch: 7.50mm; Vertical || order number: 1766725 12A 630V +phoenix_contact connector GMSTBVA_01x08_G_7.50mm +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_9-G-7,62_1x09_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/9-G-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical || order number: 1766848 12A 630V +phoenix_contact connector GMSTBVA_01x09_G_7.62mm +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_9-G_1x09_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/9-G; number of pins: 09; pin pitch: 7.50mm; Vertical || order number: 1766738 12A 630V +phoenix_contact connector GMSTBVA_01x09_G_7.50mm +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_10-G-7,62_1x10_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/10-G-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical || order number: 1766851 12A 630V +phoenix_contact connector GMSTBVA_01x10_G_7.62mm +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_10-G_1x10_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/10-G; number of pins: 10; pin pitch: 7.50mm; Vertical || order number: 1766741 12A 630V +phoenix_contact connector GMSTBVA_01x10_G_7.50mm +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_11-G-7,62_1x11_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/11-G-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical || order number: 1766864 12A 630V +phoenix_contact connector GMSTBVA_01x11_G_7.62mm +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_11-G_1x11_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/11-G; number of pins: 11; pin pitch: 7.50mm; Vertical || order number: 1766754 12A 630V +phoenix_contact connector GMSTBVA_01x11_G_7.50mm +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_12-G-7,62_1x12_P7.62mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/12-G-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical || order number: 1766877 12A 630V +phoenix_contact connector GMSTBVA_01x12_G_7.62mm +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBVA_2,5_12-G_1x12_P7.50mm_Vertical +Generic Phoenix Contact connector footprint for: GMSTBVA_2,5/12-G; number of pins: 12; pin pitch: 7.50mm; Vertical || order number: 1766767 12A 630V +phoenix_contact connector GMSTBVA_01x12_G_7.50mm +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_2-GF-7,62_1x02_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829154 12A 630V +phoenix_contact connector GMSTBV_01x02_GF_7.62mm +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_2-GF-7,62_1x02_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829154 12A 630V +phoenix_contact connector GMSTBV_01x02_GF_7.62mm_MH +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_3-GF-7,62_1x03_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829167 12A 630V +phoenix_contact connector GMSTBV_01x03_GF_7.62mm +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_3-GF-7,62_1x03_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829167 12A 630V +phoenix_contact connector GMSTBV_01x03_GF_7.62mm_MH +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_4-GF-7,62_1x04_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829170 12A 630V +phoenix_contact connector GMSTBV_01x04_GF_7.62mm +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_4-GF-7,62_1x04_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829170 12A 630V +phoenix_contact connector GMSTBV_01x04_GF_7.62mm_MH +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_5-GF-7,62_1x05_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829183 12A 630V +phoenix_contact connector GMSTBV_01x05_GF_7.62mm +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_5-GF-7,62_1x05_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829183 12A 630V +phoenix_contact connector GMSTBV_01x05_GF_7.62mm_MH +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_6-GF-7,62_1x06_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829196 12A 630V +phoenix_contact connector GMSTBV_01x06_GF_7.62mm +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_6-GF-7,62_1x06_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829196 12A 630V +phoenix_contact connector GMSTBV_01x06_GF_7.62mm_MH +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_7-GF-7,62_1x07_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829206 12A 630V +phoenix_contact connector GMSTBV_01x07_GF_7.62mm +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_7-GF-7,62_1x07_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829206 12A 630V +phoenix_contact connector GMSTBV_01x07_GF_7.62mm_MH +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_8-GF-7,62_1x08_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829219 12A 630V +phoenix_contact connector GMSTBV_01x08_GF_7.62mm +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_8-GF-7,62_1x08_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829219 12A 630V +phoenix_contact connector GMSTBV_01x08_GF_7.62mm_MH +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_9-GF-7,62_1x09_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829222 12A 630V +phoenix_contact connector GMSTBV_01x09_GF_7.62mm +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_9-GF-7,62_1x09_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829222 12A 630V +phoenix_contact connector GMSTBV_01x09_GF_7.62mm_MH +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_10-GF-7,62_1x10_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829235 12A 630V +phoenix_contact connector GMSTBV_01x10_GF_7.62mm +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_10-GF-7,62_1x10_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829235 12A 630V +phoenix_contact connector GMSTBV_01x10_GF_7.62mm_MH +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_11-GF-7,62_1x11_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829248 12A 630V +phoenix_contact connector GMSTBV_01x11_GF_7.62mm +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_11-GF-7,62_1x11_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829248 12A 630V +phoenix_contact connector GMSTBV_01x11_GF_7.62mm_MH +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_12-GF-7,62_1x12_P7.62mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical; threaded flange || order number: 1829251 12A 630V +phoenix_contact connector GMSTBV_01x12_GF_7.62mm +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTBV_2,5_12-GF-7,62_1x12_P7.62mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTBV_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1829251 12A 630V +phoenix_contact connector GMSTBV_01x12_GF_7.62mm_MH +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_2-GF-7,62_1x02_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806229 12A 630V +phoenix_contact connector GMSTB_01x02_GF_7.62mm +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_2-GF-7,62_1x02_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/2-GF-7,62; number of pins: 02; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806229 12A 630V +phoenix_contact connector GMSTB_01x02_GF_7.62mm_MH +0 +2 +2 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_3-GF-7,62_1x03_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806232 12A 630V +phoenix_contact connector GMSTB_01x03_GF_7.62mm +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_3-GF-7,62_1x03_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/3-GF-7,62; number of pins: 03; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806232 12A 630V +phoenix_contact connector GMSTB_01x03_GF_7.62mm_MH +0 +3 +3 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_4-GF-7,62_1x04_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806245 12A 630V +phoenix_contact connector GMSTB_01x04_GF_7.62mm +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_4-GF-7,62_1x04_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/4-GF-7,62; number of pins: 04; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806245 12A 630V +phoenix_contact connector GMSTB_01x04_GF_7.62mm_MH +0 +4 +4 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_5-GF-7,62_1x05_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806258 12A 630V +phoenix_contact connector GMSTB_01x05_GF_7.62mm +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_5-GF-7,62_1x05_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/5-GF-7,62; number of pins: 05; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806258 12A 630V +phoenix_contact connector GMSTB_01x05_GF_7.62mm_MH +0 +5 +5 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_6-GF-7,62_1x06_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806261 12A 630V +phoenix_contact connector GMSTB_01x06_GF_7.62mm +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_6-GF-7,62_1x06_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/6-GF-7,62; number of pins: 06; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806261 12A 630V +phoenix_contact connector GMSTB_01x06_GF_7.62mm_MH +0 +6 +6 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_7-GF-7,62_1x07_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806274 12A 630V +phoenix_contact connector GMSTB_01x07_GF_7.62mm +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_7-GF-7,62_1x07_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/7-GF-7,62; number of pins: 07; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806274 12A 630V +phoenix_contact connector GMSTB_01x07_GF_7.62mm_MH +0 +7 +7 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_8-GF-7,62_1x08_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806287 12A 630V +phoenix_contact connector GMSTB_01x08_GF_7.62mm +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_8-GF-7,62_1x08_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/8-GF-7,62; number of pins: 08; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806287 12A 630V +phoenix_contact connector GMSTB_01x08_GF_7.62mm_MH +0 +8 +8 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_9-GF-7,62_1x09_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806290 12A 630V +phoenix_contact connector GMSTB_01x09_GF_7.62mm +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_9-GF-7,62_1x09_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/9-GF-7,62; number of pins: 09; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806290 12A 630V +phoenix_contact connector GMSTB_01x09_GF_7.62mm_MH +0 +9 +9 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_10-GF-7,62_1x10_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806300 12A 630V +phoenix_contact connector GMSTB_01x10_GF_7.62mm +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_10-GF-7,62_1x10_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/10-GF-7,62; number of pins: 10; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806300 12A 630V +phoenix_contact connector GMSTB_01x10_GF_7.62mm_MH +0 +10 +10 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_11-GF-7,62_1x11_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806313 12A 630V +phoenix_contact connector GMSTB_01x11_GF_7.62mm +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_11-GF-7,62_1x11_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/11-GF-7,62; number of pins: 11; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806313 12A 630V +phoenix_contact connector GMSTB_01x11_GF_7.62mm_MH +0 +11 +11 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_12-GF-7,62_1x12_P7.62mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: GMSTB_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Angled; threaded flange || order number: 1806326 12A 630V +phoenix_contact connector GMSTB_01x12_GF_7.62mm +0 +12 +12 +Connector_Phoenix_GMSTB +PhoenixContact_GMSTB_2,5_12-GF-7,62_1x12_P7.62mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: GMSTB_2,5/12-GF-7,62; number of pins: 12; pin pitch: 7.62mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1806326 12A 630V +phoenix_contact connector GMSTB_01x12_GF_7.62mm_MH +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_2-G-3.5_1x02_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical || order number: 1843606 8A 160V +phoenix_contact connector MCV_01x02_G_3.5mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_2-G-3.81_1x02_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical || order number: 1803426 8A 160V +phoenix_contact connector MCV_01x02_G_3.81mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_2-GF-3.5_1x02_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843224 8A 160V +phoenix_contact connector MCV_01x02_GF_3.5mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_2-GF-3.5_1x02_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843224 8A 160V +phoenix_contact connector MCV_01x02_GF_3.5mm_MH +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_2-GF-3.81_1x02_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830596 8A 160V +phoenix_contact connector MCV_01x02_GF_3.81mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_2-GF-3.81_1x02_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830596 8A 160V +phoenix_contact connector MCV_01x02_GF_3.81mm_MH +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_3-G-3.5_1x03_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical || order number: 1843619 8A 160V +phoenix_contact connector MCV_01x03_G_3.5mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_3-G-3.81_1x03_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical || order number: 1803439 8A 160V +phoenix_contact connector MCV_01x03_G_3.81mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_3-GF-3.5_1x03_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843237 8A 160V +phoenix_contact connector MCV_01x03_GF_3.5mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_3-GF-3.5_1x03_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843237 8A 160V +phoenix_contact connector MCV_01x03_GF_3.5mm_MH +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_3-GF-3.81_1x03_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830606 8A 160V +phoenix_contact connector MCV_01x03_GF_3.81mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_3-GF-3.81_1x03_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830606 8A 160V +phoenix_contact connector MCV_01x03_GF_3.81mm_MH +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_4-G-3.5_1x04_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical || order number: 1843622 8A 160V +phoenix_contact connector MCV_01x04_G_3.5mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_4-G-3.81_1x04_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical || order number: 1803442 8A 160V +phoenix_contact connector MCV_01x04_G_3.81mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_4-GF-3.5_1x04_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843240 8A 160V +phoenix_contact connector MCV_01x04_GF_3.5mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_4-GF-3.5_1x04_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843240 8A 160V +phoenix_contact connector MCV_01x04_GF_3.5mm_MH +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_4-GF-3.81_1x04_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830619 8A 160V +phoenix_contact connector MCV_01x04_GF_3.81mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_4-GF-3.81_1x04_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830619 8A 160V +phoenix_contact connector MCV_01x04_GF_3.81mm_MH +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_5-G-3.5_1x05_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical || order number: 1843635 8A 160V +phoenix_contact connector MCV_01x05_G_3.5mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_5-G-3.81_1x05_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical || order number: 1803455 8A 160V +phoenix_contact connector MCV_01x05_G_3.81mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_5-GF-3.5_1x05_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843253 8A 160V +phoenix_contact connector MCV_01x05_GF_3.5mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_5-GF-3.5_1x05_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843253 8A 160V +phoenix_contact connector MCV_01x05_GF_3.5mm_MH +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_5-GF-3.81_1x05_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830622 8A 160V +phoenix_contact connector MCV_01x05_GF_3.81mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_5-GF-3.81_1x05_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830622 8A 160V +phoenix_contact connector MCV_01x05_GF_3.81mm_MH +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_6-G-3.5_1x06_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical || order number: 1843648 8A 160V +phoenix_contact connector MCV_01x06_G_3.5mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_6-G-3.81_1x06_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical || order number: 1803468 8A 160V +phoenix_contact connector MCV_01x06_G_3.81mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_6-GF-3.5_1x06_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843266 8A 160V +phoenix_contact connector MCV_01x06_GF_3.5mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_6-GF-3.5_1x06_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843266 8A 160V +phoenix_contact connector MCV_01x06_GF_3.5mm_MH +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_6-GF-3.81_1x06_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830635 8A 160V +phoenix_contact connector MCV_01x06_GF_3.81mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_6-GF-3.81_1x06_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830635 8A 160V +phoenix_contact connector MCV_01x06_GF_3.81mm_MH +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_7-G-3.5_1x07_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical || order number: 1843651 8A 160V +phoenix_contact connector MCV_01x07_G_3.5mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_7-G-3.81_1x07_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical || order number: 1803471 8A 160V +phoenix_contact connector MCV_01x07_G_3.81mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_7-GF-3.5_1x07_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843279 8A 160V +phoenix_contact connector MCV_01x07_GF_3.5mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_7-GF-3.5_1x07_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843279 8A 160V +phoenix_contact connector MCV_01x07_GF_3.5mm_MH +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_7-GF-3.81_1x07_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830648 8A 160V +phoenix_contact connector MCV_01x07_GF_3.81mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_7-GF-3.81_1x07_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830648 8A 160V +phoenix_contact connector MCV_01x07_GF_3.81mm_MH +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_8-G-3.5_1x08_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical || order number: 1843664 8A 160V +phoenix_contact connector MCV_01x08_G_3.5mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_8-G-3.81_1x08_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical || order number: 1803484 8A 160V +phoenix_contact connector MCV_01x08_G_3.81mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_8-GF-3.5_1x08_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843282 8A 160V +phoenix_contact connector MCV_01x08_GF_3.5mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_8-GF-3.5_1x08_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843282 8A 160V +phoenix_contact connector MCV_01x08_GF_3.5mm_MH +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_8-GF-3.81_1x08_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830651 8A 160V +phoenix_contact connector MCV_01x08_GF_3.81mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_8-GF-3.81_1x08_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830651 8A 160V +phoenix_contact connector MCV_01x08_GF_3.81mm_MH +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_9-G-3.5_1x09_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical || order number: 1843677 8A 160V +phoenix_contact connector MCV_01x09_G_3.5mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_9-G-3.81_1x09_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical || order number: 1803497 8A 160V +phoenix_contact connector MCV_01x09_G_3.81mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_9-GF-3.5_1x09_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843295 8A 160V +phoenix_contact connector MCV_01x09_GF_3.5mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_9-GF-3.5_1x09_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843295 8A 160V +phoenix_contact connector MCV_01x09_GF_3.5mm_MH +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_9-GF-3.81_1x09_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830664 8A 160V +phoenix_contact connector MCV_01x09_GF_3.81mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_9-GF-3.81_1x09_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830664 8A 160V +phoenix_contact connector MCV_01x09_GF_3.81mm_MH +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_10-G-3.5_1x10_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical || order number: 1843680 8A 160V +phoenix_contact connector MCV_01x10_G_3.5mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_10-G-3.81_1x10_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical || order number: 1803507 8A 160V +phoenix_contact connector MCV_01x10_G_3.81mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_10-GF-3.5_1x10_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843305 8A 160V +phoenix_contact connector MCV_01x10_GF_3.5mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_10-GF-3.5_1x10_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843305 8A 160V +phoenix_contact connector MCV_01x10_GF_3.5mm_MH +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_10-GF-3.81_1x10_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830677 8A 160V +phoenix_contact connector MCV_01x10_GF_3.81mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_10-GF-3.81_1x10_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830677 8A 160V +phoenix_contact connector MCV_01x10_GF_3.81mm_MH +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_11-G-3.5_1x11_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical || order number: 1843693 8A 160V +phoenix_contact connector MCV_01x11_G_3.5mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_11-G-3.81_1x11_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical || order number: 1803510 8A 160V +phoenix_contact connector MCV_01x11_G_3.81mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_11-GF-3.5_1x11_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843318 8A 160V +phoenix_contact connector MCV_01x11_GF_3.5mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_11-GF-3.5_1x11_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843318 8A 160V +phoenix_contact connector MCV_01x11_GF_3.5mm_MH +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_11-GF-3.81_1x11_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830680 8A 160V +phoenix_contact connector MCV_01x11_GF_3.81mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_11-GF-3.81_1x11_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830680 8A 160V +phoenix_contact connector MCV_01x11_GF_3.81mm_MH +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_12-G-3.5_1x12_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical || order number: 1843703 8A 160V +phoenix_contact connector MCV_01x12_G_3.5mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_12-G-3.81_1x12_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical || order number: 1803523 8A 160V +phoenix_contact connector MCV_01x12_G_3.81mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_12-GF-3.5_1x12_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843321 8A 160V +phoenix_contact connector MCV_01x12_GF_3.5mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_12-GF-3.5_1x12_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843321 8A 160V +phoenix_contact connector MCV_01x12_GF_3.5mm_MH +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_12-GF-3.81_1x12_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830693 8A 160V +phoenix_contact connector MCV_01x12_GF_3.81mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_12-GF-3.81_1x12_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830693 8A 160V +phoenix_contact connector MCV_01x12_GF_3.81mm_MH +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_13-G-3.5_1x13_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/13-G-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical || order number: 1843716 8A 160V +phoenix_contact connector MCV_01x13_G_3.5mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_13-G-3.81_1x13_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/13-G-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical || order number: 1803536 8A 160V +phoenix_contact connector MCV_01x13_G_3.81mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_13-GF-3.5_1x13_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843334 8A 160V +phoenix_contact connector MCV_01x13_GF_3.5mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_13-GF-3.5_1x13_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843334 8A 160V +phoenix_contact connector MCV_01x13_GF_3.5mm_MH +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_13-GF-3.81_1x13_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830703 8A 160V +phoenix_contact connector MCV_01x13_GF_3.81mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_13-GF-3.81_1x13_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830703 8A 160V +phoenix_contact connector MCV_01x13_GF_3.81mm_MH +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_14-G-3.5_1x14_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/14-G-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical || order number: 1843729 8A 160V +phoenix_contact connector MCV_01x14_G_3.5mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_14-G-3.81_1x14_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/14-G-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical || order number: 1803549 8A 160V +phoenix_contact connector MCV_01x14_G_3.81mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_14-GF-3.5_1x14_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843347 8A 160V +phoenix_contact connector MCV_01x14_GF_3.5mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_14-GF-3.5_1x14_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843347 8A 160V +phoenix_contact connector MCV_01x14_GF_3.5mm_MH +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_14-GF-3.81_1x14_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830716 8A 160V +phoenix_contact connector MCV_01x14_GF_3.81mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_14-GF-3.81_1x14_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830716 8A 160V +phoenix_contact connector MCV_01x14_GF_3.81mm_MH +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_15-G-3.5_1x15_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/15-G-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical || order number: 1843732 8A 160V +phoenix_contact connector MCV_01x15_G_3.5mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_15-G-3.81_1x15_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/15-G-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical || order number: 1803552 8A 160V +phoenix_contact connector MCV_01x15_G_3.81mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_15-GF-3.5_1x15_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843350 8A 160V +phoenix_contact connector MCV_01x15_GF_3.5mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_15-GF-3.5_1x15_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843350 8A 160V +phoenix_contact connector MCV_01x15_GF_3.5mm_MH +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_15-GF-3.81_1x15_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830729 8A 160V +phoenix_contact connector MCV_01x15_GF_3.81mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_15-GF-3.81_1x15_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830729 8A 160V +phoenix_contact connector MCV_01x15_GF_3.81mm_MH +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_16-G-3.5_1x16_P3.50mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/16-G-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical || order number: 1843745 8A 160V +phoenix_contact connector MCV_01x16_G_3.5mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_16-G-3.81_1x16_P3.81mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/16-G-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical || order number: 1803565 8A 160V +phoenix_contact connector MCV_01x16_G_3.81mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_16-GF-3.5_1x16_P3.50mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical; threaded flange || order number: 1843363 8A 160V +phoenix_contact connector MCV_01x16_GF_3.5mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_16-GF-3.5_1x16_P3.50mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843363 8A 160V +phoenix_contact connector MCV_01x16_GF_3.5mm_MH +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_16-GF-3.81_1x16_P3.81mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical; threaded flange || order number: 1830732 8A 160V +phoenix_contact connector MCV_01x16_GF_3.81mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MCV_1,5_16-GF-3.81_1x16_P3.81mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1830732 8A 160V +phoenix_contact connector MCV_01x16_GF_3.81mm_MH +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_2-G-3.5_1x02_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/2-G-3.5; number of pins: 02; pin pitch: 3.50mm; Angled || order number: 1844210 8A 160V +phoenix_contact connector MC_01x02_G_3.5mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_2-G-3.81_1x02_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/2-G-3.81; number of pins: 02; pin pitch: 3.81mm; Angled || order number: 1803277 8A 160V +phoenix_contact connector MC_01x02_G_3.81mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_2-GF-3.5_1x02_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843790 8A 160V +phoenix_contact connector MC_01x02_GF_3.5mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_2-GF-3.5_1x02_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.5; number of pins: 02; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843790 8A 160V +phoenix_contact connector MC_01x02_GF_3.5mm_MH +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_2-GF-3.81_1x02_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827868 8A 160V +phoenix_contact connector MC_01x02_GF_3.81mm +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_2-GF-3.81_1x02_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-3.81; number of pins: 02; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827868 8A 160V +phoenix_contact connector MC_01x02_GF_3.81mm_MH +0 +2 +2 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_3-G-3.5_1x03_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/3-G-3.5; number of pins: 03; pin pitch: 3.50mm; Angled || order number: 1844223 8A 160V +phoenix_contact connector MC_01x03_G_3.5mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_3-G-3.81_1x03_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/3-G-3.81; number of pins: 03; pin pitch: 3.81mm; Angled || order number: 1803280 8A 160V +phoenix_contact connector MC_01x03_G_3.81mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_3-GF-3.5_1x03_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843800 8A 160V +phoenix_contact connector MC_01x03_GF_3.5mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_3-GF-3.5_1x03_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.5; number of pins: 03; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843800 8A 160V +phoenix_contact connector MC_01x03_GF_3.5mm_MH +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_3-GF-3.81_1x03_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827871 8A 160V +phoenix_contact connector MC_01x03_GF_3.81mm +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_3-GF-3.81_1x03_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-3.81; number of pins: 03; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827871 8A 160V +phoenix_contact connector MC_01x03_GF_3.81mm_MH +0 +3 +3 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_4-G-3.5_1x04_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/4-G-3.5; number of pins: 04; pin pitch: 3.50mm; Angled || order number: 1844236 8A 160V +phoenix_contact connector MC_01x04_G_3.5mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_4-G-3.81_1x04_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/4-G-3.81; number of pins: 04; pin pitch: 3.81mm; Angled || order number: 1803293 8A 160V +phoenix_contact connector MC_01x04_G_3.81mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_4-GF-3.5_1x04_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843813 8A 160V +phoenix_contact connector MC_01x04_GF_3.5mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_4-GF-3.5_1x04_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.5; number of pins: 04; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843813 8A 160V +phoenix_contact connector MC_01x04_GF_3.5mm_MH +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_4-GF-3.81_1x04_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827884 8A 160V +phoenix_contact connector MC_01x04_GF_3.81mm +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_4-GF-3.81_1x04_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-3.81; number of pins: 04; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827884 8A 160V +phoenix_contact connector MC_01x04_GF_3.81mm_MH +0 +4 +4 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_5-G-3.5_1x05_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/5-G-3.5; number of pins: 05; pin pitch: 3.50mm; Angled || order number: 1844249 8A 160V +phoenix_contact connector MC_01x05_G_3.5mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_5-G-3.81_1x05_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/5-G-3.81; number of pins: 05; pin pitch: 3.81mm; Angled || order number: 1803303 8A 160V +phoenix_contact connector MC_01x05_G_3.81mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_5-GF-3.5_1x05_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843826 8A 160V +phoenix_contact connector MC_01x05_GF_3.5mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_5-GF-3.5_1x05_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.5; number of pins: 05; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843826 8A 160V +phoenix_contact connector MC_01x05_GF_3.5mm_MH +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_5-GF-3.81_1x05_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827897 8A 160V +phoenix_contact connector MC_01x05_GF_3.81mm +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_5-GF-3.81_1x05_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-3.81; number of pins: 05; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827897 8A 160V +phoenix_contact connector MC_01x05_GF_3.81mm_MH +0 +5 +5 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_6-G-3.5_1x06_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/6-G-3.5; number of pins: 06; pin pitch: 3.50mm; Angled || order number: 1844252 8A 160V +phoenix_contact connector MC_01x06_G_3.5mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_6-G-3.81_1x06_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/6-G-3.81; number of pins: 06; pin pitch: 3.81mm; Angled || order number: 1803316 8A 160V +phoenix_contact connector MC_01x06_G_3.81mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_6-GF-3.5_1x06_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843839 8A 160V +phoenix_contact connector MC_01x06_GF_3.5mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_6-GF-3.5_1x06_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.5; number of pins: 06; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843839 8A 160V +phoenix_contact connector MC_01x06_GF_3.5mm_MH +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_6-GF-3.81_1x06_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827907 8A 160V +phoenix_contact connector MC_01x06_GF_3.81mm +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_6-GF-3.81_1x06_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-3.81; number of pins: 06; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827907 8A 160V +phoenix_contact connector MC_01x06_GF_3.81mm_MH +0 +6 +6 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_7-G-3.5_1x07_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/7-G-3.5; number of pins: 07; pin pitch: 3.50mm; Angled || order number: 1844265 8A 160V +phoenix_contact connector MC_01x07_G_3.5mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_7-G-3.81_1x07_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/7-G-3.81; number of pins: 07; pin pitch: 3.81mm; Angled || order number: 1803329 8A 160V +phoenix_contact connector MC_01x07_G_3.81mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_7-GF-3.5_1x07_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843842 8A 160V +phoenix_contact connector MC_01x07_GF_3.5mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_7-GF-3.5_1x07_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.5; number of pins: 07; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843842 8A 160V +phoenix_contact connector MC_01x07_GF_3.5mm_MH +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_7-GF-3.81_1x07_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827910 8A 160V +phoenix_contact connector MC_01x07_GF_3.81mm +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_7-GF-3.81_1x07_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-3.81; number of pins: 07; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827910 8A 160V +phoenix_contact connector MC_01x07_GF_3.81mm_MH +0 +7 +7 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_8-G-3.5_1x08_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/8-G-3.5; number of pins: 08; pin pitch: 3.50mm; Angled || order number: 1844278 8A 160V +phoenix_contact connector MC_01x08_G_3.5mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_8-G-3.81_1x08_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/8-G-3.81; number of pins: 08; pin pitch: 3.81mm; Angled || order number: 1803332 8A 160V +phoenix_contact connector MC_01x08_G_3.81mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_8-GF-3.5_1x08_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843855 8A 160V +phoenix_contact connector MC_01x08_GF_3.5mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_8-GF-3.5_1x08_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.5; number of pins: 08; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843855 8A 160V +phoenix_contact connector MC_01x08_GF_3.5mm_MH +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_8-GF-3.81_1x08_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827923 8A 160V +phoenix_contact connector MC_01x08_GF_3.81mm +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_8-GF-3.81_1x08_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-3.81; number of pins: 08; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827923 8A 160V +phoenix_contact connector MC_01x08_GF_3.81mm_MH +0 +8 +8 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_9-G-3.5_1x09_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/9-G-3.5; number of pins: 09; pin pitch: 3.50mm; Angled || order number: 1844281 8A 160V +phoenix_contact connector MC_01x09_G_3.5mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_9-G-3.81_1x09_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/9-G-3.81; number of pins: 09; pin pitch: 3.81mm; Angled || order number: 1803345 8A 160V +phoenix_contact connector MC_01x09_G_3.81mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_9-GF-3.5_1x09_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843868 8A 160V +phoenix_contact connector MC_01x09_GF_3.5mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_9-GF-3.5_1x09_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.5; number of pins: 09; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843868 8A 160V +phoenix_contact connector MC_01x09_GF_3.5mm_MH +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_9-GF-3.81_1x09_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827936 8A 160V +phoenix_contact connector MC_01x09_GF_3.81mm +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_9-GF-3.81_1x09_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-3.81; number of pins: 09; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827936 8A 160V +phoenix_contact connector MC_01x09_GF_3.81mm_MH +0 +9 +9 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_10-G-3.5_1x10_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/10-G-3.5; number of pins: 10; pin pitch: 3.50mm; Angled || order number: 1844294 8A 160V +phoenix_contact connector MC_01x10_G_3.5mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_10-G-3.81_1x10_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/10-G-3.81; number of pins: 10; pin pitch: 3.81mm; Angled || order number: 1803358 8A 160V +phoenix_contact connector MC_01x10_G_3.81mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_10-GF-3.5_1x10_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843871 8A 160V +phoenix_contact connector MC_01x10_GF_3.5mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_10-GF-3.5_1x10_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.5; number of pins: 10; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843871 8A 160V +phoenix_contact connector MC_01x10_GF_3.5mm_MH +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_10-GF-3.81_1x10_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827949 8A 160V +phoenix_contact connector MC_01x10_GF_3.81mm +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_10-GF-3.81_1x10_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-3.81; number of pins: 10; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827949 8A 160V +phoenix_contact connector MC_01x10_GF_3.81mm_MH +0 +10 +10 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_11-G-3.5_1x11_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/11-G-3.5; number of pins: 11; pin pitch: 3.50mm; Angled || order number: 1844304 8A 160V +phoenix_contact connector MC_01x11_G_3.5mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_11-G-3.81_1x11_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/11-G-3.81; number of pins: 11; pin pitch: 3.81mm; Angled || order number: 1803361 8A 160V +phoenix_contact connector MC_01x11_G_3.81mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_11-GF-3.5_1x11_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843884 8A 160V +phoenix_contact connector MC_01x11_GF_3.5mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_11-GF-3.5_1x11_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.5; number of pins: 11; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843884 8A 160V +phoenix_contact connector MC_01x11_GF_3.5mm_MH +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_11-GF-3.81_1x11_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827952 8A 160V +phoenix_contact connector MC_01x11_GF_3.81mm +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_11-GF-3.81_1x11_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-3.81; number of pins: 11; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827952 8A 160V +phoenix_contact connector MC_01x11_GF_3.81mm_MH +0 +11 +11 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_12-G-3.5_1x12_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/12-G-3.5; number of pins: 12; pin pitch: 3.50mm; Angled || order number: 1844317 8A 160V +phoenix_contact connector MC_01x12_G_3.5mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_12-G-3.81_1x12_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/12-G-3.81; number of pins: 12; pin pitch: 3.81mm; Angled || order number: 1803374 8A 160V +phoenix_contact connector MC_01x12_G_3.81mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_12-GF-3.5_1x12_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843897 8A 160V +phoenix_contact connector MC_01x12_GF_3.5mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_12-GF-3.5_1x12_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.5; number of pins: 12; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843897 8A 160V +phoenix_contact connector MC_01x12_GF_3.5mm_MH +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_12-GF-3.81_1x12_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827965 8A 160V +phoenix_contact connector MC_01x12_GF_3.81mm +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_12-GF-3.81_1x12_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-3.81; number of pins: 12; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827965 8A 160V +phoenix_contact connector MC_01x12_GF_3.81mm_MH +0 +12 +12 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_13-G-3.5_1x13_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/13-G-3.5; number of pins: 13; pin pitch: 3.50mm; Angled || order number: 1844320 8A 160V +phoenix_contact connector MC_01x13_G_3.5mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_13-G-3.81_1x13_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/13-G-3.81; number of pins: 13; pin pitch: 3.81mm; Angled || order number: 1803387 8A 160V +phoenix_contact connector MC_01x13_G_3.81mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_13-GF-3.5_1x13_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843907 8A 160V +phoenix_contact connector MC_01x13_GF_3.5mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_13-GF-3.5_1x13_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.5; number of pins: 13; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843907 8A 160V +phoenix_contact connector MC_01x13_GF_3.5mm_MH +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_13-GF-3.81_1x13_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827978 8A 160V +phoenix_contact connector MC_01x13_GF_3.81mm +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_13-GF-3.81_1x13_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/13-GF-3.81; number of pins: 13; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827978 8A 160V +phoenix_contact connector MC_01x13_GF_3.81mm_MH +0 +13 +13 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_14-G-3.5_1x14_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/14-G-3.5; number of pins: 14; pin pitch: 3.50mm; Angled || order number: 1844333 8A 160V +phoenix_contact connector MC_01x14_G_3.5mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_14-G-3.81_1x14_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/14-G-3.81; number of pins: 14; pin pitch: 3.81mm; Angled || order number: 1803390 8A 160V +phoenix_contact connector MC_01x14_G_3.81mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_14-GF-3.5_1x14_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843910 8A 160V +phoenix_contact connector MC_01x14_GF_3.5mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_14-GF-3.5_1x14_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.5; number of pins: 14; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843910 8A 160V +phoenix_contact connector MC_01x14_GF_3.5mm_MH +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_14-GF-3.81_1x14_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827981 8A 160V +phoenix_contact connector MC_01x14_GF_3.81mm +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_14-GF-3.81_1x14_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/14-GF-3.81; number of pins: 14; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827981 8A 160V +phoenix_contact connector MC_01x14_GF_3.81mm_MH +0 +14 +14 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_15-G-3.5_1x15_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/15-G-3.5; number of pins: 15; pin pitch: 3.50mm; Angled || order number: 1844346 8A 160V +phoenix_contact connector MC_01x15_G_3.5mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_15-G-3.81_1x15_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/15-G-3.81; number of pins: 15; pin pitch: 3.81mm; Angled || order number: 1803400 8A 160V +phoenix_contact connector MC_01x15_G_3.81mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_15-GF-3.5_1x15_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843923 8A 160V +phoenix_contact connector MC_01x15_GF_3.5mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_15-GF-3.5_1x15_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.5; number of pins: 15; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843923 8A 160V +phoenix_contact connector MC_01x15_GF_3.5mm_MH +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_15-GF-3.81_1x15_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Angled; threaded flange || order number: 1827994 8A 160V +phoenix_contact connector MC_01x15_GF_3.81mm +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_15-GF-3.81_1x15_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/15-GF-3.81; number of pins: 15; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1827994 8A 160V +phoenix_contact connector MC_01x15_GF_3.81mm_MH +0 +15 +15 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_16-G-3.5_1x16_P3.50mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/16-G-3.5; number of pins: 16; pin pitch: 3.50mm; Angled || order number: 1844359 8A 160V +phoenix_contact connector MC_01x16_G_3.5mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_16-G-3.81_1x16_P3.81mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/16-G-3.81; number of pins: 16; pin pitch: 3.81mm; Angled || order number: 1803413 8A 160V +phoenix_contact connector MC_01x16_G_3.81mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_16-GF-3.5_1x16_P3.50mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Angled; threaded flange || order number: 1843936 8A 160V +phoenix_contact connector MC_01x16_GF_3.5mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_16-GF-3.5_1x16_P3.50mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.5; number of pins: 16; pin pitch: 3.50mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1843936 8A 160V +phoenix_contact connector MC_01x16_GF_3.5mm_MH +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_16-GF-3.81_1x16_P3.81mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Angled; threaded flange || order number: 1828003 8A 160V +phoenix_contact connector MC_01x16_GF_3.81mm +0 +16 +16 +Connector_Phoenix_MC +PhoenixContact_MC_1,5_16-GF-3.81_1x16_P3.81mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/16-GF-3.81; number of pins: 16; pin pitch: 3.81mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1828003 8A 160V +phoenix_contact connector MC_01x16_GF_3.81mm_MH +0 +16 +16 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_2-G-5.08_1x02_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/2-G-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical || order number: 1836299 8A 320V +phoenix_contact connector MCV_01x02_G_5.08mm +0 +2 +2 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_2-GF-5.08_1x02_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847615 8A 320V +phoenix_contact connector MCV_01x02_GF_5.08mm +0 +2 +2 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_2-GF-5.08_1x02_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847615 8A 320V +phoenix_contact connector MCV_01x02_GF_5.08mm_MH +0 +2 +2 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_3-G-5.08_1x03_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/3-G-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical || order number: 1836309 8A 320V +phoenix_contact connector MCV_01x03_G_5.08mm +0 +3 +3 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_3-GF-5.08_1x03_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847628 8A 320V +phoenix_contact connector MCV_01x03_GF_5.08mm +0 +3 +3 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_3-GF-5.08_1x03_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847628 8A 320V +phoenix_contact connector MCV_01x03_GF_5.08mm_MH +0 +3 +3 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_4-G-5.08_1x04_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/4-G-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical || order number: 1836312 8A 320V +phoenix_contact connector MCV_01x04_G_5.08mm +0 +4 +4 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_4-GF-5.08_1x04_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847631 8A 320V +phoenix_contact connector MCV_01x04_GF_5.08mm +0 +4 +4 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_4-GF-5.08_1x04_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847631 8A 320V +phoenix_contact connector MCV_01x04_GF_5.08mm_MH +0 +4 +4 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_5-G-5.08_1x05_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/5-G-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical || order number: 1836325 8A 320V +phoenix_contact connector MCV_01x05_G_5.08mm +0 +5 +5 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_5-GF-5.08_1x05_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847644 8A 320V +phoenix_contact connector MCV_01x05_GF_5.08mm +0 +5 +5 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_5-GF-5.08_1x05_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847644 8A 320V +phoenix_contact connector MCV_01x05_GF_5.08mm_MH +0 +5 +5 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_6-G-5.08_1x06_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/6-G-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical || order number: 1836338 8A 320V +phoenix_contact connector MCV_01x06_G_5.08mm +0 +6 +6 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_6-GF-5.08_1x06_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847657 8A 320V +phoenix_contact connector MCV_01x06_GF_5.08mm +0 +6 +6 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_6-GF-5.08_1x06_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847657 8A 320V +phoenix_contact connector MCV_01x06_GF_5.08mm_MH +0 +6 +6 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_7-G-5.08_1x07_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/7-G-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical || order number: 1836341 8A 320V +phoenix_contact connector MCV_01x07_G_5.08mm +0 +7 +7 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_7-GF-5.08_1x07_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847660 8A 320V +phoenix_contact connector MCV_01x07_GF_5.08mm +0 +7 +7 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_7-GF-5.08_1x07_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847660 8A 320V +phoenix_contact connector MCV_01x07_GF_5.08mm_MH +0 +7 +7 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_8-G-5.08_1x08_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/8-G-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical || order number: 1836354 8A 320V +phoenix_contact connector MCV_01x08_G_5.08mm +0 +8 +8 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_8-GF-5.08_1x08_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847673 8A 320V +phoenix_contact connector MCV_01x08_GF_5.08mm +0 +8 +8 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_8-GF-5.08_1x08_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847673 8A 320V +phoenix_contact connector MCV_01x08_GF_5.08mm_MH +0 +8 +8 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_9-G-5.08_1x09_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/9-G-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical || order number: 1836367 8A 320V +phoenix_contact connector MCV_01x09_G_5.08mm +0 +9 +9 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_9-GF-5.08_1x09_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847686 8A 320V +phoenix_contact connector MCV_01x09_GF_5.08mm +0 +9 +9 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_9-GF-5.08_1x09_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847686 8A 320V +phoenix_contact connector MCV_01x09_GF_5.08mm_MH +0 +9 +9 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_10-G-5.08_1x10_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/10-G-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical || order number: 1836370 8A 320V +phoenix_contact connector MCV_01x10_G_5.08mm +0 +10 +10 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_10-GF-5.08_1x10_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847699 8A 320V +phoenix_contact connector MCV_01x10_GF_5.08mm +0 +10 +10 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_10-GF-5.08_1x10_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847699 8A 320V +phoenix_contact connector MCV_01x10_GF_5.08mm_MH +0 +10 +10 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_11-G-5.08_1x11_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/11-G-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical || order number: 1836383 8A 320V +phoenix_contact connector MCV_01x11_G_5.08mm +0 +11 +11 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_11-GF-5.08_1x11_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847709 8A 320V +phoenix_contact connector MCV_01x11_GF_5.08mm +0 +11 +11 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_11-GF-5.08_1x11_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847709 8A 320V +phoenix_contact connector MCV_01x11_GF_5.08mm_MH +0 +11 +11 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_12-G-5.08_1x12_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MCV_1,5/12-G-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical || order number: 1836396 8A 320V +phoenix_contact connector MCV_01x12_G_5.08mm +0 +12 +12 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_12-GF-5.08_1x12_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1847712 8A 320V +phoenix_contact connector MCV_01x12_GF_5.08mm +0 +12 +12 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MCV_1,5_12-GF-5.08_1x12_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MCV_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847712 8A 320V +phoenix_contact connector MCV_01x12_GF_5.08mm_MH +0 +12 +12 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_2-G-5.08_1x02_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/2-G-5.08; number of pins: 02; pin pitch: 5.08mm; Angled || order number: 1836189 8A 320V +phoenix_contact connector MC_01x02_G_5.08mm +0 +2 +2 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_2-GF-5.08_1x02_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847466 8A 320V +phoenix_contact connector MC_01x02_GF_5.08mm +0 +2 +2 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_2-GF-5.08_1x02_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/2-GF-5.08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847466 8A 320V +phoenix_contact connector MC_01x02_GF_5.08mm_MH +0 +2 +2 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_3-G-5.08_1x03_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/3-G-5.08; number of pins: 03; pin pitch: 5.08mm; Angled || order number: 1836192 8A 320V +phoenix_contact connector MC_01x03_G_5.08mm +0 +3 +3 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_3-GF-5.08_1x03_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847479 8A 320V +phoenix_contact connector MC_01x03_GF_5.08mm +0 +3 +3 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_3-GF-5.08_1x03_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/3-GF-5.08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847479 8A 320V +phoenix_contact connector MC_01x03_GF_5.08mm_MH +0 +3 +3 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_4-G-5.08_1x04_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/4-G-5.08; number of pins: 04; pin pitch: 5.08mm; Angled || order number: 1836202 8A 320V +phoenix_contact connector MC_01x04_G_5.08mm +0 +4 +4 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_4-GF-5.08_1x04_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847482 8A 320V +phoenix_contact connector MC_01x04_GF_5.08mm +0 +4 +4 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_4-GF-5.08_1x04_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/4-GF-5.08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847482 8A 320V +phoenix_contact connector MC_01x04_GF_5.08mm_MH +0 +4 +4 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_5-G-5.08_1x05_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/5-G-5.08; number of pins: 05; pin pitch: 5.08mm; Angled || order number: 1836215 8A 320V +phoenix_contact connector MC_01x05_G_5.08mm +0 +5 +5 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_5-GF-5.08_1x05_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847495 8A 320V +phoenix_contact connector MC_01x05_GF_5.08mm +0 +5 +5 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_5-GF-5.08_1x05_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/5-GF-5.08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847495 8A 320V +phoenix_contact connector MC_01x05_GF_5.08mm_MH +0 +5 +5 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_6-G-5.08_1x06_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/6-G-5.08; number of pins: 06; pin pitch: 5.08mm; Angled || order number: 1836228 8A 320V +phoenix_contact connector MC_01x06_G_5.08mm +0 +6 +6 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_6-GF-5.08_1x06_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847505 8A 320V +phoenix_contact connector MC_01x06_GF_5.08mm +0 +6 +6 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_6-GF-5.08_1x06_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/6-GF-5.08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847505 8A 320V +phoenix_contact connector MC_01x06_GF_5.08mm_MH +0 +6 +6 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_7-G-5.08_1x07_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/7-G-5.08; number of pins: 07; pin pitch: 5.08mm; Angled || order number: 1836231 8A 320V +phoenix_contact connector MC_01x07_G_5.08mm +0 +7 +7 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_7-GF-5.08_1x07_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847518 8A 320V +phoenix_contact connector MC_01x07_GF_5.08mm +0 +7 +7 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_7-GF-5.08_1x07_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/7-GF-5.08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847518 8A 320V +phoenix_contact connector MC_01x07_GF_5.08mm_MH +0 +7 +7 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_8-G-5.08_1x08_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/8-G-5.08; number of pins: 08; pin pitch: 5.08mm; Angled || order number: 1836244 8A 320V +phoenix_contact connector MC_01x08_G_5.08mm +0 +8 +8 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_8-GF-5.08_1x08_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847521 8A 320V +phoenix_contact connector MC_01x08_GF_5.08mm +0 +8 +8 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_8-GF-5.08_1x08_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/8-GF-5.08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847521 8A 320V +phoenix_contact connector MC_01x08_GF_5.08mm_MH +0 +8 +8 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_9-G-5.08_1x09_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/9-G-5.08; number of pins: 09; pin pitch: 5.08mm; Angled || order number: 1836257 8A 320V +phoenix_contact connector MC_01x09_G_5.08mm +0 +9 +9 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_9-GF-5.08_1x09_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847534 8A 320V +phoenix_contact connector MC_01x09_GF_5.08mm +0 +9 +9 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_9-GF-5.08_1x09_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/9-GF-5.08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847534 8A 320V +phoenix_contact connector MC_01x09_GF_5.08mm_MH +0 +9 +9 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_10-G-5.08_1x10_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/10-G-5.08; number of pins: 10; pin pitch: 5.08mm; Angled || order number: 1836260 8A 320V +phoenix_contact connector MC_01x10_G_5.08mm +0 +10 +10 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_10-GF-5.08_1x10_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847547 8A 320V +phoenix_contact connector MC_01x10_GF_5.08mm +0 +10 +10 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_10-GF-5.08_1x10_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/10-GF-5.08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847547 8A 320V +phoenix_contact connector MC_01x10_GF_5.08mm_MH +0 +10 +10 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_11-G-5.08_1x11_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/11-G-5.08; number of pins: 11; pin pitch: 5.08mm; Angled || order number: 1836273 8A 320V +phoenix_contact connector MC_01x11_G_5.08mm +0 +11 +11 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_11-GF-5.08_1x11_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847550 8A 320V +phoenix_contact connector MC_01x11_GF_5.08mm +0 +11 +11 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_11-GF-5.08_1x11_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/11-GF-5.08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847550 8A 320V +phoenix_contact connector MC_01x11_GF_5.08mm_MH +0 +11 +11 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_12-G-5.08_1x12_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MC_1,5/12-G-5.08; number of pins: 12; pin pitch: 5.08mm; Angled || order number: 1836286 8A 320V +phoenix_contact connector MC_01x12_G_5.08mm +0 +12 +12 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_12-GF-5.08_1x12_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange || order number: 1847563 8A 320V +phoenix_contact connector MC_01x12_GF_5.08mm +0 +12 +12 +Connector_Phoenix_MC_HighVoltage +PhoenixContact_MC_1,5_12-GF-5.08_1x12_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MC_1,5/12-GF-5.08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x4.5 C or ISO 7049-ST 2.2x4.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1847563 8A 320V +phoenix_contact connector MC_01x12_GF_5.08mm_MH +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_2-G-5,08_1x02_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/2-G-5,08; number of pins: 02; pin pitch: 5.08mm; Angled || order number: 1757242 12A || order number: 1923869 16A (HC) +phoenix_contact connector MSTBA_01x02_G_5.08mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_2-G_1x02_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Angled || order number: 1757475 12A || order number: 1923759 16A (HC) +phoenix_contact connector MSTBA_01x02_G_5.00mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_3-G-5,08_1x03_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/3-G-5,08; number of pins: 03; pin pitch: 5.08mm; Angled || order number: 1757255 12A || order number: 1923872 16A (HC) +phoenix_contact connector MSTBA_01x03_G_5.08mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_3-G_1x03_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/3-G; number of pins: 03; pin pitch: 5.00mm; Angled || order number: 1757488 12A || order number: 1923762 16A (HC) +phoenix_contact connector MSTBA_01x03_G_5.00mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_4-G-5,08_1x04_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/4-G-5,08; number of pins: 04; pin pitch: 5.08mm; Angled || order number: 1757268 12A || order number: 1923885 16A (HC) +phoenix_contact connector MSTBA_01x04_G_5.08mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_4-G_1x04_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Angled || order number: 1757491 12A || order number: 1923775 16A (HC) +phoenix_contact connector MSTBA_01x04_G_5.00mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_5-G-5,08_1x05_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/5-G-5,08; number of pins: 05; pin pitch: 5.08mm; Angled || order number: 1757271 12A || order number: 1923898 16A (HC) +phoenix_contact connector MSTBA_01x05_G_5.08mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_5-G_1x05_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/5-G; number of pins: 05; pin pitch: 5.00mm; Angled || order number: 1757501 12A || order number: 1923788 16A (HC) +phoenix_contact connector MSTBA_01x05_G_5.00mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_6-G-5,08_1x06_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/6-G-5,08; number of pins: 06; pin pitch: 5.08mm; Angled || order number: 1757284 12A || order number: 1923908 16A (HC) +phoenix_contact connector MSTBA_01x06_G_5.08mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_6-G_1x06_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/6-G; number of pins: 06; pin pitch: 5.00mm; Angled || order number: 1757514 12A || order number: 1923791 16A (HC) +phoenix_contact connector MSTBA_01x06_G_5.00mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_7-G-5,08_1x07_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/7-G-5,08; number of pins: 07; pin pitch: 5.08mm; Angled || order number: 1757297 12A || order number: 1923911 16A (HC) +phoenix_contact connector MSTBA_01x07_G_5.08mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_7-G_1x07_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/7-G; number of pins: 07; pin pitch: 5.00mm; Angled || order number: 1757493 12A || order number: 1923801 16A (HC) +phoenix_contact connector MSTBA_01x07_G_5.00mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_8-G-5,08_1x08_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/8-G-5,08; number of pins: 08; pin pitch: 5.08mm; Angled || order number: 1757307 12A || order number: 1923924 16A (HC) +phoenix_contact connector MSTBA_01x08_G_5.08mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_8-G_1x08_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/8-G; number of pins: 08; pin pitch: 5.00mm; Angled || order number: 1757527 12A || order number: 1923814 16A (HC) +phoenix_contact connector MSTBA_01x08_G_5.00mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_9-G-5,08_1x09_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/9-G-5,08; number of pins: 09; pin pitch: 5.08mm; Angled || order number: 1757310 12A || order number: 1923937 16A (HC) +phoenix_contact connector MSTBA_01x09_G_5.08mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_9-G_1x09_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/9-G; number of pins: 09; pin pitch: 5.00mm; Angled || order number: 1757530 12A || order number: 1923827 16A (HC) +phoenix_contact connector MSTBA_01x09_G_5.00mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_10-G-5,08_1x10_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/10-G-5,08; number of pins: 10; pin pitch: 5.08mm; Angled || order number: 1757323 12A || order number: 1923940 16A (HC) +phoenix_contact connector MSTBA_01x10_G_5.08mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_10-G_1x10_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/10-G; number of pins: 10; pin pitch: 5.00mm; Angled || order number: 1757543 12A || order number: 1923830 16A (HC) +phoenix_contact connector MSTBA_01x10_G_5.00mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_11-G-5,08_1x11_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/11-G-5,08; number of pins: 11; pin pitch: 5.08mm; Angled || order number: 1757336 12A || order number: 1923953 16A (HC) +phoenix_contact connector MSTBA_01x11_G_5.08mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_11-G_1x11_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/11-G; number of pins: 11; pin pitch: 5.00mm; Angled || order number: 1757556 12A || order number: 1923843 16A (HC) +phoenix_contact connector MSTBA_01x11_G_5.00mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_12-G-5,08_1x12_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/12-G-5,08; number of pins: 12; pin pitch: 5.08mm; Angled || order number: 1757349 12A || order number: 1923966 16A (HC) +phoenix_contact connector MSTBA_01x12_G_5.08mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_12-G_1x12_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/12-G; number of pins: 12; pin pitch: 5.00mm; Angled || order number: 1757569 12A || order number: 1923856 16A (HC) +phoenix_contact connector MSTBA_01x12_G_5.00mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_13-G-5,08_1x13_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/13-G-5,08; number of pins: 13; pin pitch: 5.08mm; Angled || order number: 1757352 12A +phoenix_contact connector MSTBA_01x13_G_5.08mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_13-G_1x13_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/13-G; number of pins: 13; pin pitch: 5.00mm; Angled || order number: 1757572 12A +phoenix_contact connector MSTBA_01x13_G_5.00mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_14-G-5,08_1x14_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/14-G-5,08; number of pins: 14; pin pitch: 5.08mm; Angled || order number: 1757365 12A +phoenix_contact connector MSTBA_01x14_G_5.08mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_14-G_1x14_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/14-G; number of pins: 14; pin pitch: 5.00mm; Angled || order number: 1757585 12A +phoenix_contact connector MSTBA_01x14_G_5.00mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_15-G-5,08_1x15_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/15-G-5,08; number of pins: 15; pin pitch: 5.08mm; Angled || order number: 1757378 12A +phoenix_contact connector MSTBA_01x15_G_5.08mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_15-G_1x15_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/15-G; number of pins: 15; pin pitch: 5.00mm; Angled || order number: 1757598 12A +phoenix_contact connector MSTBA_01x15_G_5.00mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_16-G-5,08_1x16_P5.08mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/16-G-5,08; number of pins: 16; pin pitch: 5.08mm; Angled || order number: 1757381 12A +phoenix_contact connector MSTBA_01x16_G_5.08mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBA_2,5_16-G_1x16_P5.00mm_Horizontal +Generic Phoenix Contact connector footprint for: MSTBA_2,5/16-G; number of pins: 16; pin pitch: 5.00mm; Angled || order number: 1757608 12A +phoenix_contact connector MSTBA_01x16_G_5.00mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_2-G-5,08_1x02_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical || order number: 1755736 12A || order number: 1924305 16A (HC) +phoenix_contact connector MSTBVA_01x02_G_5.08mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_2-G_1x02_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Vertical || order number: 1755516 12A || order number: 1924198 16A (HC) +phoenix_contact connector MSTBVA_01x02_G_5.00mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_3-G-5,08_1x03_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/3-G-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical || order number: 1755749 12A || order number: 1924318 16A (HC) +phoenix_contact connector MSTBVA_01x03_G_5.08mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_3-G_1x03_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/3-G; number of pins: 03; pin pitch: 5.00mm; Vertical || order number: 1755529 12A || order number: 1924208 16A (HC) +phoenix_contact connector MSTBVA_01x03_G_5.00mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_4-G-5,08_1x04_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical || order number: 1755752 12A || order number: 1924321 16A (HC) +phoenix_contact connector MSTBVA_01x04_G_5.08mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_4-G_1x04_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Vertical || order number: 1755532 12A || order number: 1924211 16A (HC) +phoenix_contact connector MSTBVA_01x04_G_5.00mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_5-G-5,08_1x05_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/5-G-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical || order number: 1755765 12A || order number: 1924334 16A (HC) +phoenix_contact connector MSTBVA_01x05_G_5.08mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_5-G_1x05_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/5-G; number of pins: 05; pin pitch: 5.00mm; Vertical || order number: 1755545 12A || order number: 1924224 16A (HC) +phoenix_contact connector MSTBVA_01x05_G_5.00mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_6-G-5,08_1x06_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/6-G-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical || order number: 1755778 12A || order number: 1924347 16A (HC) +phoenix_contact connector MSTBVA_01x06_G_5.08mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_6-G_1x06_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/6-G; number of pins: 06; pin pitch: 5.00mm; Vertical || order number: 1755558 12A || order number: 1924237 16A (HC) +phoenix_contact connector MSTBVA_01x06_G_5.00mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_7-G-5,08_1x07_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/7-G-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical || order number: 1755781 12A || order number: 1924350 16A (HC) +phoenix_contact connector MSTBVA_01x07_G_5.08mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_7-G_1x07_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/7-G; number of pins: 07; pin pitch: 5.00mm; Vertical || order number: 1755561 12A || order number: 1924240 16A (HC) +phoenix_contact connector MSTBVA_01x07_G_5.00mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_8-G-5,08_1x08_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/8-G-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical || order number: 1755794 12A || order number: 1924363 16A (HC) +phoenix_contact connector MSTBVA_01x08_G_5.08mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_8-G_1x08_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/8-G; number of pins: 08; pin pitch: 5.00mm; Vertical || order number: 1755574 12A || order number: 1924253 16A (HC) +phoenix_contact connector MSTBVA_01x08_G_5.00mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_9-G-5,08_1x09_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/9-G-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical || order number: 1755804 12A || order number: 1924376 16A (HC) +phoenix_contact connector MSTBVA_01x09_G_5.08mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_9-G_1x09_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/9-G; number of pins: 09; pin pitch: 5.00mm; Vertical || order number: 1755587 12A || order number: 1924266 16A (HC) +phoenix_contact connector MSTBVA_01x09_G_5.00mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_10-G-5,08_1x10_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/10-G-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical || order number: 1755817 12A || order number: 1924389 16A (HC) +phoenix_contact connector MSTBVA_01x10_G_5.08mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_10-G_1x10_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/10-G; number of pins: 10; pin pitch: 5.00mm; Vertical || order number: 1755503 12A || order number: 1924279 16A (HC) +phoenix_contact connector MSTBVA_01x10_G_5.00mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_11-G-5,08_1x11_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/11-G-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical || order number: 1755820 12A || order number: 1924392 16A (HC) +phoenix_contact connector MSTBVA_01x11_G_5.08mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_11-G_1x11_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/11-G; number of pins: 11; pin pitch: 5.00mm; Vertical || order number: 1755590 12A || order number: 1924282 16A (HC) +phoenix_contact connector MSTBVA_01x11_G_5.00mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_12-G-5,08_1x12_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/12-G-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical || order number: 1755833 12A || order number: 1924402 16A (HC) +phoenix_contact connector MSTBVA_01x12_G_5.08mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_12-G_1x12_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/12-G; number of pins: 12; pin pitch: 5.00mm; Vertical || order number: 1755600 12A || order number: 1924295 16A (HC) +phoenix_contact connector MSTBVA_01x12_G_5.00mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_13-G-5,08_1x13_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/13-G-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical || order number: 1755846 12A +phoenix_contact connector MSTBVA_01x13_G_5.08mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_13-G_1x13_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/13-G; number of pins: 13; pin pitch: 5.00mm; Vertical || order number: 1755613 12A +phoenix_contact connector MSTBVA_01x13_G_5.00mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_14-G-5,08_1x14_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/14-G-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical || order number: 1755859 12A +phoenix_contact connector MSTBVA_01x14_G_5.08mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_14-G_1x14_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/14-G; number of pins: 14; pin pitch: 5.00mm; Vertical || order number: 1755626 12A +phoenix_contact connector MSTBVA_01x14_G_5.00mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_15-G-5,08_1x15_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/15-G-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical || order number: 1755862 12A +phoenix_contact connector MSTBVA_01x15_G_5.08mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_15-G_1x15_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/15-G; number of pins: 15; pin pitch: 5.00mm; Vertical || order number: 1755639 12A +phoenix_contact connector MSTBVA_01x15_G_5.00mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_16-G-5,08_1x16_P5.08mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/16-G-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical || order number: 1755875 12A +phoenix_contact connector MSTBVA_01x16_G_5.08mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBVA_2,5_16-G_1x16_P5.00mm_Vertical +Generic Phoenix Contact connector footprint for: MSTBVA_2,5/16-G; number of pins: 16; pin pitch: 5.00mm; Vertical || order number: 1755642 12A +phoenix_contact connector MSTBVA_01x16_G_5.00mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_2-GF-5,08_1x02_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777073 12A || order number: 1924525 16A (HC) +phoenix_contact connector MSTBV_01x02_GF_5.08mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_2-GF-5,08_1x02_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777073 12A || order number: 1924525 16A (HC) +phoenix_contact connector MSTBV_01x02_GF_5.08mm_MH +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_2-GF_1x02_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776883 12A || order number: 1924415 16A (HC) +phoenix_contact connector MSTBV_01x02_GF_5.00mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_2-GF_1x02_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776883 12A || order number: 1924415 16A (HC) +phoenix_contact connector MSTBV_01x02_GF_5.00mm_MH +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_3-GF-5,08_1x03_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777086 12A || order number: 1924538 16A (HC) +phoenix_contact connector MSTBV_01x03_GF_5.08mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_3-GF-5,08_1x03_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777086 12A || order number: 1924538 16A (HC) +phoenix_contact connector MSTBV_01x03_GF_5.08mm_MH +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_3-GF_1x03_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776896 12A || order number: 1924428 16A (HC) +phoenix_contact connector MSTBV_01x03_GF_5.00mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_3-GF_1x03_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776896 12A || order number: 1924428 16A (HC) +phoenix_contact connector MSTBV_01x03_GF_5.00mm_MH +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_4-GF-5,08_1x04_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777099 12A || order number: 1924541 16A (HC) +phoenix_contact connector MSTBV_01x04_GF_5.08mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_4-GF-5,08_1x04_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777099 12A || order number: 1924541 16A (HC) +phoenix_contact connector MSTBV_01x04_GF_5.08mm_MH +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_4-GF_1x04_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776906 12A || order number: 1924431 16A (HC) +phoenix_contact connector MSTBV_01x04_GF_5.00mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_4-GF_1x04_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776906 12A || order number: 1924431 16A (HC) +phoenix_contact connector MSTBV_01x04_GF_5.00mm_MH +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_5-GF-5,08_1x05_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777109 12A || order number: 1924554 16A (HC) +phoenix_contact connector MSTBV_01x05_GF_5.08mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_5-GF-5,08_1x05_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777109 12A || order number: 1924554 16A (HC) +phoenix_contact connector MSTBV_01x05_GF_5.08mm_MH +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_5-GF_1x05_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776919 12A || order number: 1924444 16A (HC) +phoenix_contact connector MSTBV_01x05_GF_5.00mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_5-GF_1x05_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776919 12A || order number: 1924444 16A (HC) +phoenix_contact connector MSTBV_01x05_GF_5.00mm_MH +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_6-GF-5,08_1x06_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777112 12A || order number: 1924567 16A (HC) +phoenix_contact connector MSTBV_01x06_GF_5.08mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_6-GF-5,08_1x06_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777112 12A || order number: 1924567 16A (HC) +phoenix_contact connector MSTBV_01x06_GF_5.08mm_MH +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_6-GF_1x06_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776922 12A || order number: 1924457 16A (HC) +phoenix_contact connector MSTBV_01x06_GF_5.00mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_6-GF_1x06_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776922 12A || order number: 1924457 16A (HC) +phoenix_contact connector MSTBV_01x06_GF_5.00mm_MH +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_7-GF-5,08_1x07_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777125 12A || order number: 1924570 16A (HC) +phoenix_contact connector MSTBV_01x07_GF_5.08mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_7-GF-5,08_1x07_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777125 12A || order number: 1924570 16A (HC) +phoenix_contact connector MSTBV_01x07_GF_5.08mm_MH +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_7-GF_1x07_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776935 12A || order number: 1924460 16A (HC) +phoenix_contact connector MSTBV_01x07_GF_5.00mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_7-GF_1x07_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776935 12A || order number: 1924460 16A (HC) +phoenix_contact connector MSTBV_01x07_GF_5.00mm_MH +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_8-GF-5,08_1x08_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777138 12A || order number: 1924583 16A (HC) +phoenix_contact connector MSTBV_01x08_GF_5.08mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_8-GF-5,08_1x08_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777138 12A || order number: 1924583 16A (HC) +phoenix_contact connector MSTBV_01x08_GF_5.08mm_MH +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_8-GF_1x08_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776948 12A || order number: 1924473 16A (HC) +phoenix_contact connector MSTBV_01x08_GF_5.00mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_8-GF_1x08_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776948 12A || order number: 1924473 16A (HC) +phoenix_contact connector MSTBV_01x08_GF_5.00mm_MH +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_9-GF-5,08_1x09_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777141 12A || order number: 1924596 16A (HC) +phoenix_contact connector MSTBV_01x09_GF_5.08mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_9-GF-5,08_1x09_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777141 12A || order number: 1924596 16A (HC) +phoenix_contact connector MSTBV_01x09_GF_5.08mm_MH +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_9-GF_1x09_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776951 12A || order number: 1924486 16A (HC) +phoenix_contact connector MSTBV_01x09_GF_5.00mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_9-GF_1x09_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776951 12A || order number: 1924486 16A (HC) +phoenix_contact connector MSTBV_01x09_GF_5.00mm_MH +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_10-GF-5,08_1x10_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777154 12A || order number: 1924606 16A (HC) +phoenix_contact connector MSTBV_01x10_GF_5.08mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_10-GF-5,08_1x10_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777154 12A || order number: 1924606 16A (HC) +phoenix_contact connector MSTBV_01x10_GF_5.08mm_MH +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_10-GF_1x10_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776964 12A || order number: 1924499 16A (HC) +phoenix_contact connector MSTBV_01x10_GF_5.00mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_10-GF_1x10_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776964 12A || order number: 1924499 16A (HC) +phoenix_contact connector MSTBV_01x10_GF_5.00mm_MH +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_11-GF-5,08_1x11_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777167 12A || order number: 1924619 16A (HC) +phoenix_contact connector MSTBV_01x11_GF_5.08mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_11-GF-5,08_1x11_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777167 12A || order number: 1924619 16A (HC) +phoenix_contact connector MSTBV_01x11_GF_5.08mm_MH +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_11-GF_1x11_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776977 12A || order number: 1924509 16A (HC) +phoenix_contact connector MSTBV_01x11_GF_5.00mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_11-GF_1x11_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776977 12A || order number: 1924509 16A (HC) +phoenix_contact connector MSTBV_01x11_GF_5.00mm_MH +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_12-GF-5,08_1x12_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777170 12A || order number: 1924622 16A (HC) +phoenix_contact connector MSTBV_01x12_GF_5.08mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_12-GF-5,08_1x12_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777170 12A || order number: 1924622 16A (HC) +phoenix_contact connector MSTBV_01x12_GF_5.08mm_MH +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_12-GF_1x12_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776980 12A || order number: 1924512 16A (HC) +phoenix_contact connector MSTBV_01x12_GF_5.00mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_12-GF_1x12_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776980 12A || order number: 1924512 16A (HC) +phoenix_contact connector MSTBV_01x12_GF_5.00mm_MH +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_13-GF-5,08_1x13_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777183 12A +phoenix_contact connector MSTBV_01x13_GF_5.08mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_13-GF-5,08_1x13_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777183 12A +phoenix_contact connector MSTBV_01x13_GF_5.08mm_MH +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_13-GF_1x13_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776993 12A +phoenix_contact connector MSTBV_01x13_GF_5.00mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_13-GF_1x13_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776993 12A +phoenix_contact connector MSTBV_01x13_GF_5.00mm_MH +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_14-GF-5,08_1x14_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777196 12A +phoenix_contact connector MSTBV_01x14_GF_5.08mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_14-GF-5,08_1x14_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777196 12A +phoenix_contact connector MSTBV_01x14_GF_5.08mm_MH +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_14-GF_1x14_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776002 12A +phoenix_contact connector MSTBV_01x14_GF_5.00mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_14-GF_1x14_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776002 12A +phoenix_contact connector MSTBV_01x14_GF_5.00mm_MH +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_15-GF-5,08_1x15_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777206 12A +phoenix_contact connector MSTBV_01x15_GF_5.08mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_15-GF-5,08_1x15_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777206 12A +phoenix_contact connector MSTBV_01x15_GF_5.08mm_MH +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_15-GF_1x15_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776015 12A +phoenix_contact connector MSTBV_01x15_GF_5.00mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_15-GF_1x15_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776015 12A +phoenix_contact connector MSTBV_01x15_GF_5.00mm_MH +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_16-GF-5,08_1x16_P5.08mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical; threaded flange || order number: 1777219 12A +phoenix_contact connector MSTBV_01x16_GF_5.08mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_16-GF-5,08_1x16_P5.08mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1777219 12A +phoenix_contact connector MSTBV_01x16_GF_5.08mm_MH +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_16-GF_1x16_P5.00mm_Vertical_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Vertical; threaded flange || order number: 1776028 12A +phoenix_contact connector MSTBV_01x16_GF_5.00mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTBV_2,5_16-GF_1x16_P5.00mm_Vertical_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTBV_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Vertical; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776028 12A +phoenix_contact connector MSTBV_01x16_GF_5.00mm_MH +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_2-GF-5,08_1x02_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776508 12A || order number: 1924088 16A (HC) +phoenix_contact connector MSTB_01x02_GF_5.08mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_2-GF-5,08_1x02_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF-5,08; number of pins: 02; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776508 12A || order number: 1924088 16A (HC) +phoenix_contact connector MSTB_01x02_GF_5.08mm_MH +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_2-GF_1x02_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776692 12A || order number: 1923979 16A (HC) +phoenix_contact connector MSTB_01x02_GF_5.00mm +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_2-GF_1x02_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/2-GF; number of pins: 02; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776692 12A || order number: 1923979 16A (HC) +phoenix_contact connector MSTB_01x02_GF_5.00mm_MH +0 +2 +2 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_3-GF-5,08_1x03_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776511 12A || order number: 1924091 16A (HC) +phoenix_contact connector MSTB_01x03_GF_5.08mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_3-GF-5,08_1x03_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF-5,08; number of pins: 03; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776511 12A || order number: 1924091 16A (HC) +phoenix_contact connector MSTB_01x03_GF_5.08mm_MH +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_3-GF_1x03_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776702 12A || order number: 1923982 16A (HC) +phoenix_contact connector MSTB_01x03_GF_5.00mm +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_3-GF_1x03_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/3-GF; number of pins: 03; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776702 12A || order number: 1923982 16A (HC) +phoenix_contact connector MSTB_01x03_GF_5.00mm_MH +0 +3 +3 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_4-GF-5,08_1x04_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776524 12A || order number: 1924101 16A (HC) +phoenix_contact connector MSTB_01x04_GF_5.08mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_4-GF-5,08_1x04_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF-5,08; number of pins: 04; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776524 12A || order number: 1924101 16A (HC) +phoenix_contact connector MSTB_01x04_GF_5.08mm_MH +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_4-GF_1x04_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776715 12A || order number: 1923995 16A (HC) +phoenix_contact connector MSTB_01x04_GF_5.00mm +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_4-GF_1x04_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/4-GF; number of pins: 04; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776715 12A || order number: 1923995 16A (HC) +phoenix_contact connector MSTB_01x04_GF_5.00mm_MH +0 +4 +4 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_5-GF-5,08_1x05_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776537 12A || order number: 1924114 16A (HC) +phoenix_contact connector MSTB_01x05_GF_5.08mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_5-GF-5,08_1x05_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF-5,08; number of pins: 05; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776537 12A || order number: 1924114 16A (HC) +phoenix_contact connector MSTB_01x05_GF_5.08mm_MH +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_5-GF_1x05_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776728 12A || order number: 1924004 16A (HC) +phoenix_contact connector MSTB_01x05_GF_5.00mm +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_5-GF_1x05_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/5-GF; number of pins: 05; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776728 12A || order number: 1924004 16A (HC) +phoenix_contact connector MSTB_01x05_GF_5.00mm_MH +0 +5 +5 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_6-GF-5,08_1x06_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776540 12A || order number: 1924127 16A (HC) +phoenix_contact connector MSTB_01x06_GF_5.08mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_6-GF-5,08_1x06_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF-5,08; number of pins: 06; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776540 12A || order number: 1924127 16A (HC) +phoenix_contact connector MSTB_01x06_GF_5.08mm_MH +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_6-GF_1x06_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776731 12A || order number: 1924017 16A (HC) +phoenix_contact connector MSTB_01x06_GF_5.00mm +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_6-GF_1x06_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/6-GF; number of pins: 06; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776731 12A || order number: 1924017 16A (HC) +phoenix_contact connector MSTB_01x06_GF_5.00mm_MH +0 +6 +6 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_7-GF-5,08_1x07_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776553 12A || order number: 1924130 16A (HC) +phoenix_contact connector MSTB_01x07_GF_5.08mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_7-GF-5,08_1x07_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF-5,08; number of pins: 07; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776553 12A || order number: 1924130 16A (HC) +phoenix_contact connector MSTB_01x07_GF_5.08mm_MH +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_7-GF_1x07_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776744 12A || order number: 1924020 16A (HC) +phoenix_contact connector MSTB_01x07_GF_5.00mm +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_7-GF_1x07_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/7-GF; number of pins: 07; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776744 12A || order number: 1924020 16A (HC) +phoenix_contact connector MSTB_01x07_GF_5.00mm_MH +0 +7 +7 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_8-GF-5,08_1x08_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776566 12A || order number: 1924143 16A (HC) +phoenix_contact connector MSTB_01x08_GF_5.08mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_8-GF-5,08_1x08_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF-5,08; number of pins: 08; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776566 12A || order number: 1924143 16A (HC) +phoenix_contact connector MSTB_01x08_GF_5.08mm_MH +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_8-GF_1x08_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776757 12A || order number: 1924033 16A (HC) +phoenix_contact connector MSTB_01x08_GF_5.00mm +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_8-GF_1x08_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/8-GF; number of pins: 08; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776757 12A || order number: 1924033 16A (HC) +phoenix_contact connector MSTB_01x08_GF_5.00mm_MH +0 +8 +8 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_9-GF-5,08_1x09_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776579 12A || order number: 1924156 16A (HC) +phoenix_contact connector MSTB_01x09_GF_5.08mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_9-GF-5,08_1x09_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF-5,08; number of pins: 09; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776579 12A || order number: 1924156 16A (HC) +phoenix_contact connector MSTB_01x09_GF_5.08mm_MH +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_9-GF_1x09_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776760 12A || order number: 1924046 16A (HC) +phoenix_contact connector MSTB_01x09_GF_5.00mm +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_9-GF_1x09_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/9-GF; number of pins: 09; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776760 12A || order number: 1924046 16A (HC) +phoenix_contact connector MSTB_01x09_GF_5.00mm_MH +0 +9 +9 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_10-GF-5,08_1x10_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776582 12A || order number: 1924169 16A (HC) +phoenix_contact connector MSTB_01x10_GF_5.08mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_10-GF-5,08_1x10_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF-5,08; number of pins: 10; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776582 12A || order number: 1924169 16A (HC) +phoenix_contact connector MSTB_01x10_GF_5.08mm_MH +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_10-GF_1x10_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776773 12A || order number: 1924059 16A (HC) +phoenix_contact connector MSTB_01x10_GF_5.00mm +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_10-GF_1x10_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/10-GF; number of pins: 10; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776773 12A || order number: 1924059 16A (HC) +phoenix_contact connector MSTB_01x10_GF_5.00mm_MH +0 +10 +10 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_11-GF-5,08_1x11_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776595 12A || order number: 1924172 16A (HC) +phoenix_contact connector MSTB_01x11_GF_5.08mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_11-GF-5,08_1x11_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF-5,08; number of pins: 11; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776595 12A || order number: 1924172 16A (HC) +phoenix_contact connector MSTB_01x11_GF_5.08mm_MH +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_11-GF_1x11_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776786 12A || order number: 1924062 16A (HC) +phoenix_contact connector MSTB_01x11_GF_5.00mm +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_11-GF_1x11_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/11-GF; number of pins: 11; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776786 12A || order number: 1924062 16A (HC) +phoenix_contact connector MSTB_01x11_GF_5.00mm_MH +0 +11 +11 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_12-GF-5,08_1x12_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776605 12A || order number: 1924185 16A (HC) +phoenix_contact connector MSTB_01x12_GF_5.08mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_12-GF-5,08_1x12_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF-5,08; number of pins: 12; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776605 12A || order number: 1924185 16A (HC) +phoenix_contact connector MSTB_01x12_GF_5.08mm_MH +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_12-GF_1x12_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776799 12A || order number: 1924075 16A (HC) +phoenix_contact connector MSTB_01x12_GF_5.00mm +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_12-GF_1x12_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/12-GF; number of pins: 12; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776799 12A || order number: 1924075 16A (HC) +phoenix_contact connector MSTB_01x12_GF_5.00mm_MH +0 +12 +12 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_13-GF-5,08_1x13_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776618 12A +phoenix_contact connector MSTB_01x13_GF_5.08mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_13-GF-5,08_1x13_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF-5,08; number of pins: 13; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776618 12A +phoenix_contact connector MSTB_01x13_GF_5.08mm_MH +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_13-GF_1x13_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776809 12A +phoenix_contact connector MSTB_01x13_GF_5.00mm +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_13-GF_1x13_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/13-GF; number of pins: 13; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776809 12A +phoenix_contact connector MSTB_01x13_GF_5.00mm_MH +0 +13 +13 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_14-GF-5,08_1x14_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776621 12A +phoenix_contact connector MSTB_01x14_GF_5.08mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_14-GF-5,08_1x14_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF-5,08; number of pins: 14; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776621 12A +phoenix_contact connector MSTB_01x14_GF_5.08mm_MH +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_14-GF_1x14_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776812 12A +phoenix_contact connector MSTB_01x14_GF_5.00mm +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_14-GF_1x14_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/14-GF; number of pins: 14; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776812 12A +phoenix_contact connector MSTB_01x14_GF_5.00mm_MH +0 +14 +14 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_15-GF-5,08_1x15_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776634 12A +phoenix_contact connector MSTB_01x15_GF_5.08mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_15-GF-5,08_1x15_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF-5,08; number of pins: 15; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776634 12A +phoenix_contact connector MSTB_01x15_GF_5.08mm_MH +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_15-GF_1x15_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776825 12A +phoenix_contact connector MSTB_01x15_GF_5.00mm +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_15-GF_1x15_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/15-GF; number of pins: 15; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776825 12A +phoenix_contact connector MSTB_01x15_GF_5.00mm_MH +0 +15 +15 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_16-GF-5,08_1x16_P5.08mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Angled; threaded flange || order number: 1776647 12A +phoenix_contact connector MSTB_01x16_GF_5.08mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_16-GF-5,08_1x16_P5.08mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF-5,08; number of pins: 16; pin pitch: 5.08mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776647 12A +phoenix_contact connector MSTB_01x16_GF_5.08mm_MH +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_16-GF_1x16_P5.00mm_Horizontal_ThreadedFlange +Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Angled; threaded flange || order number: 1776838 12A +phoenix_contact connector MSTB_01x16_GF_5.00mm +0 +16 +16 +Connector_Phoenix_MSTB +PhoenixContact_MSTB_2,5_16-GF_1x16_P5.00mm_Horizontal_ThreadedFlange_MountHole +Generic Phoenix Contact connector footprint for: MSTB_2,5/16-GF; number of pins: 16; pin pitch: 5.00mm; Angled; threaded flange; footprint includes mount hole for mounting screw: ISO 1481-ST 2.2x6.5 C or ISO 7049-ST 2.2x6.5 C (http://www.fasteners.eu/standards/ISO/7049/) || order number: 1776838 12A +phoenix_contact connector MSTB_01x16_GF_5.00mm_MH +0 +16 +16 +Connector_Pin +Pin_D0.7mm_L6.5mm_W1.8mm_FlatFork +solder Pin_ with flat fork, hole diameter 0.7mm, length 6.5mm, width 1.8mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D0.9mm_L10.0mm_W2.4mm_FlatFork +solder Pin_ with flat fork, hole diameter 0.9mm, length 10.0mm, width 2.4mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.0mm_L10.0mm +solder Pin_ diameter 1.0mm, hole diameter 1.0mm (press fit), length 10.0mm +solder Pin_ press fit +0 +1 +1 +Connector_Pin +Pin_D1.0mm_L10.0mm_LooseFit +solder Pin_ diameter 1.0mm, hole diameter 1.2mm (loose fit), length 10.0mm +solder Pin_ loose fit +0 +1 +1 +Connector_Pin +Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork +solder Pin_ with flat fork, hole diameter 1.1mm, length 8.5mm, width 2.5mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.1mm_L10.2mm_W3.5mm_Flat +solder Pin_ with flat with hole, hole diameter 1.1mm, length 10.2mm, width 3.5mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.2mm_L10.2mm_W2.9mm_FlatFork +solder Pin_ with flat with fork, hole diameter 1.2mm, length 11.3mm, width 3.0mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.2mm_L11.3mm_W3.0mm_Flat +solder Pin_ with flat with hole, hole diameter 1.2mm, length 11.3mm, width 3.0mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.3mm_L10.0mm_W3.5mm_Flat +solder Pin_ with flat with hole, hole diameter 1.3mm, length 10.0mm, width 3.5mm, e.g. Ettinger 13.13.865, https://katalog.ettinger.de/#p=434 +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.3mm_L11.0mm +solder Pin_ diameter 1.3mm, hole diameter 1.3mm, length 11.0mm +solder Pin_ pressfit +0 +1 +1 +Connector_Pin +Pin_D1.3mm_L11.0mm_LooseFit +solder Pin_ diameter 1.3mm, hole diameter 1.5mm (loose fit), length 11.0mm +solder Pin_ loose fit +0 +1 +1 +Connector_Pin +Pin_D1.3mm_L11.3mm_W2.8mm_Flat +solder Pin_ with flat with hole, hole diameter 1.3mm, length 11.3mm, width 2.8mm +solder Pin_ with flat fork +0 +1 +1 +Connector_Pin +Pin_D1.4mm_L8.5mm_W2.8mm_FlatFork +solder Pin_ with flat with fork, hole diameter 1.4mm, length 8.5mm, width 2.8mm, e.g. Ettinger 13.13.890, https://katalog.ettinger.de/#p=434 +solder Pin_ with flat fork +0 +1 +1 +Connector_PinHeader_1.00mm +PinHeader_1x01_P1.00mm_Horizontal +Through hole angled pin header, 1x01, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x01 1.00mm single row +0 +1 +1 +Connector_PinHeader_1.00mm +PinHeader_1x01_P1.00mm_Vertical +Through hole straight pin header, 1x01, 1.00mm pitch, single row +Through hole pin header THT 1x01 1.00mm single row +0 +1 +1 +Connector_PinHeader_1.00mm +PinHeader_1x02_P1.00mm_Horizontal +Through hole angled pin header, 1x02, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x02 1.00mm single row +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_1x02_P1.00mm_Vertical +Through hole straight pin header, 1x02, 1.00mm pitch, single row +Through hole pin header THT 1x02 1.00mm single row +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_1x02_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x02, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x02 1.00mm single row style1 pin1 left +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_1x02_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x02, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x02 1.00mm single row style2 pin1 right +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_1x03_P1.00mm_Horizontal +Through hole angled pin header, 1x03, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x03 1.00mm single row +0 +3 +3 +Connector_PinHeader_1.00mm +PinHeader_1x03_P1.00mm_Vertical +Through hole straight pin header, 1x03, 1.00mm pitch, single row +Through hole pin header THT 1x03 1.00mm single row +0 +3 +3 +Connector_PinHeader_1.00mm +PinHeader_1x03_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x03, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x03 1.00mm single row style1 pin1 left +0 +3 +3 +Connector_PinHeader_1.00mm +PinHeader_1x03_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x03, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x03 1.00mm single row style2 pin1 right +0 +3 +3 +Connector_PinHeader_1.00mm +PinHeader_1x04_P1.00mm_Horizontal +Through hole angled pin header, 1x04, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x04 1.00mm single row +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_1x04_P1.00mm_Vertical +Through hole straight pin header, 1x04, 1.00mm pitch, single row +Through hole pin header THT 1x04 1.00mm single row +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_1x04_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x04, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x04 1.00mm single row style1 pin1 left +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_1x04_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x04, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x04 1.00mm single row style2 pin1 right +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_1x05_P1.00mm_Horizontal +Through hole angled pin header, 1x05, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x05 1.00mm single row +0 +5 +5 +Connector_PinHeader_1.00mm +PinHeader_1x05_P1.00mm_Vertical +Through hole straight pin header, 1x05, 1.00mm pitch, single row +Through hole pin header THT 1x05 1.00mm single row +0 +5 +5 +Connector_PinHeader_1.00mm +PinHeader_1x05_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x05, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x05 1.00mm single row style1 pin1 left +0 +5 +5 +Connector_PinHeader_1.00mm +PinHeader_1x05_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x05, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x05 1.00mm single row style2 pin1 right +0 +5 +5 +Connector_PinHeader_1.00mm +PinHeader_1x06_P1.00mm_Horizontal +Through hole angled pin header, 1x06, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x06 1.00mm single row +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_1x06_P1.00mm_Vertical +Through hole straight pin header, 1x06, 1.00mm pitch, single row +Through hole pin header THT 1x06 1.00mm single row +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_1x06_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x06, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x06 1.00mm single row style1 pin1 left +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_1x06_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x06, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x06 1.00mm single row style2 pin1 right +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_1x07_P1.00mm_Horizontal +Through hole angled pin header, 1x07, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x07 1.00mm single row +0 +7 +7 +Connector_PinHeader_1.00mm +PinHeader_1x07_P1.00mm_Vertical +Through hole straight pin header, 1x07, 1.00mm pitch, single row +Through hole pin header THT 1x07 1.00mm single row +0 +7 +7 +Connector_PinHeader_1.00mm +PinHeader_1x07_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x07, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x07 1.00mm single row style1 pin1 left +0 +7 +7 +Connector_PinHeader_1.00mm +PinHeader_1x07_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x07, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x07 1.00mm single row style2 pin1 right +0 +7 +7 +Connector_PinHeader_1.00mm +PinHeader_1x08_P1.00mm_Horizontal +Through hole angled pin header, 1x08, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x08 1.00mm single row +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_1x08_P1.00mm_Vertical +Through hole straight pin header, 1x08, 1.00mm pitch, single row +Through hole pin header THT 1x08 1.00mm single row +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_1x08_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x08, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x08 1.00mm single row style1 pin1 left +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_1x08_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x08, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x08 1.00mm single row style2 pin1 right +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_1x09_P1.00mm_Horizontal +Through hole angled pin header, 1x09, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x09 1.00mm single row +0 +9 +9 +Connector_PinHeader_1.00mm +PinHeader_1x09_P1.00mm_Vertical +Through hole straight pin header, 1x09, 1.00mm pitch, single row +Through hole pin header THT 1x09 1.00mm single row +0 +9 +9 +Connector_PinHeader_1.00mm +PinHeader_1x09_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x09, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x09 1.00mm single row style1 pin1 left +0 +9 +9 +Connector_PinHeader_1.00mm +PinHeader_1x09_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x09, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x09 1.00mm single row style2 pin1 right +0 +9 +9 +Connector_PinHeader_1.00mm +PinHeader_1x10_P1.00mm_Horizontal +Through hole angled pin header, 1x10, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x10 1.00mm single row +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_1x10_P1.00mm_Vertical +Through hole straight pin header, 1x10, 1.00mm pitch, single row +Through hole pin header THT 1x10 1.00mm single row +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_1x10_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x10, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x10 1.00mm single row style1 pin1 left +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_1x10_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x10, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x10 1.00mm single row style2 pin1 right +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_1x11_P1.00mm_Horizontal +Through hole angled pin header, 1x11, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x11 1.00mm single row +0 +11 +11 +Connector_PinHeader_1.00mm +PinHeader_1x11_P1.00mm_Vertical +Through hole straight pin header, 1x11, 1.00mm pitch, single row +Through hole pin header THT 1x11 1.00mm single row +0 +11 +11 +Connector_PinHeader_1.00mm +PinHeader_1x11_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x11, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x11 1.00mm single row style1 pin1 left +0 +11 +11 +Connector_PinHeader_1.00mm +PinHeader_1x11_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x11, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x11 1.00mm single row style2 pin1 right +0 +11 +11 +Connector_PinHeader_1.00mm +PinHeader_1x12_P1.00mm_Horizontal +Through hole angled pin header, 1x12, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x12 1.00mm single row +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_1x12_P1.00mm_Vertical +Through hole straight pin header, 1x12, 1.00mm pitch, single row +Through hole pin header THT 1x12 1.00mm single row +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_1x12_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x12, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x12 1.00mm single row style1 pin1 left +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_1x12_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x12, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x12 1.00mm single row style2 pin1 right +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_1x13_P1.00mm_Horizontal +Through hole angled pin header, 1x13, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x13 1.00mm single row +0 +13 +13 +Connector_PinHeader_1.00mm +PinHeader_1x13_P1.00mm_Vertical +Through hole straight pin header, 1x13, 1.00mm pitch, single row +Through hole pin header THT 1x13 1.00mm single row +0 +13 +13 +Connector_PinHeader_1.00mm +PinHeader_1x13_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x13, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x13 1.00mm single row style1 pin1 left +0 +13 +13 +Connector_PinHeader_1.00mm +PinHeader_1x13_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x13, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x13 1.00mm single row style2 pin1 right +0 +13 +13 +Connector_PinHeader_1.00mm +PinHeader_1x14_P1.00mm_Horizontal +Through hole angled pin header, 1x14, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x14 1.00mm single row +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_1x14_P1.00mm_Vertical +Through hole straight pin header, 1x14, 1.00mm pitch, single row +Through hole pin header THT 1x14 1.00mm single row +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_1x14_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x14, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x14 1.00mm single row style1 pin1 left +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_1x14_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x14, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x14 1.00mm single row style2 pin1 right +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_1x15_P1.00mm_Horizontal +Through hole angled pin header, 1x15, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x15 1.00mm single row +0 +15 +15 +Connector_PinHeader_1.00mm +PinHeader_1x15_P1.00mm_Vertical +Through hole straight pin header, 1x15, 1.00mm pitch, single row +Through hole pin header THT 1x15 1.00mm single row +0 +15 +15 +Connector_PinHeader_1.00mm +PinHeader_1x15_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x15, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x15 1.00mm single row style1 pin1 left +0 +15 +15 +Connector_PinHeader_1.00mm +PinHeader_1x15_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x15, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x15 1.00mm single row style2 pin1 right +0 +15 +15 +Connector_PinHeader_1.00mm +PinHeader_1x16_P1.00mm_Horizontal +Through hole angled pin header, 1x16, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x16 1.00mm single row +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_1x16_P1.00mm_Vertical +Through hole straight pin header, 1x16, 1.00mm pitch, single row +Through hole pin header THT 1x16 1.00mm single row +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_1x16_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x16, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x16 1.00mm single row style1 pin1 left +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_1x16_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x16, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x16 1.00mm single row style2 pin1 right +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_1x17_P1.00mm_Horizontal +Through hole angled pin header, 1x17, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x17 1.00mm single row +0 +17 +17 +Connector_PinHeader_1.00mm +PinHeader_1x17_P1.00mm_Vertical +Through hole straight pin header, 1x17, 1.00mm pitch, single row +Through hole pin header THT 1x17 1.00mm single row +0 +17 +17 +Connector_PinHeader_1.00mm +PinHeader_1x17_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x17, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x17 1.00mm single row style1 pin1 left +0 +17 +17 +Connector_PinHeader_1.00mm +PinHeader_1x17_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x17, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x17 1.00mm single row style2 pin1 right +0 +17 +17 +Connector_PinHeader_1.00mm +PinHeader_1x18_P1.00mm_Horizontal +Through hole angled pin header, 1x18, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x18 1.00mm single row +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_1x18_P1.00mm_Vertical +Through hole straight pin header, 1x18, 1.00mm pitch, single row +Through hole pin header THT 1x18 1.00mm single row +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_1x18_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x18, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x18 1.00mm single row style1 pin1 left +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_1x18_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x18, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x18 1.00mm single row style2 pin1 right +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_1x19_P1.00mm_Horizontal +Through hole angled pin header, 1x19, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x19 1.00mm single row +0 +19 +19 +Connector_PinHeader_1.00mm +PinHeader_1x19_P1.00mm_Vertical +Through hole straight pin header, 1x19, 1.00mm pitch, single row +Through hole pin header THT 1x19 1.00mm single row +0 +19 +19 +Connector_PinHeader_1.00mm +PinHeader_1x19_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x19, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x19 1.00mm single row style1 pin1 left +0 +19 +19 +Connector_PinHeader_1.00mm +PinHeader_1x19_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x19, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x19 1.00mm single row style2 pin1 right +0 +19 +19 +Connector_PinHeader_1.00mm +PinHeader_1x20_P1.00mm_Horizontal +Through hole angled pin header, 1x20, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x20 1.00mm single row +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_1x20_P1.00mm_Vertical +Through hole straight pin header, 1x20, 1.00mm pitch, single row +Through hole pin header THT 1x20 1.00mm single row +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_1x20_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x20, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x20 1.00mm single row style1 pin1 left +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_1x20_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x20, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x20 1.00mm single row style2 pin1 right +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_1x21_P1.00mm_Horizontal +Through hole angled pin header, 1x21, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x21 1.00mm single row +0 +21 +21 +Connector_PinHeader_1.00mm +PinHeader_1x21_P1.00mm_Vertical +Through hole straight pin header, 1x21, 1.00mm pitch, single row +Through hole pin header THT 1x21 1.00mm single row +0 +21 +21 +Connector_PinHeader_1.00mm +PinHeader_1x21_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x21, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x21 1.00mm single row style1 pin1 left +0 +21 +21 +Connector_PinHeader_1.00mm +PinHeader_1x21_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x21, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x21 1.00mm single row style2 pin1 right +0 +21 +21 +Connector_PinHeader_1.00mm +PinHeader_1x22_P1.00mm_Horizontal +Through hole angled pin header, 1x22, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x22 1.00mm single row +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_1x22_P1.00mm_Vertical +Through hole straight pin header, 1x22, 1.00mm pitch, single row +Through hole pin header THT 1x22 1.00mm single row +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_1x22_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x22, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x22 1.00mm single row style1 pin1 left +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_1x22_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x22, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x22 1.00mm single row style2 pin1 right +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_1x23_P1.00mm_Horizontal +Through hole angled pin header, 1x23, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x23 1.00mm single row +0 +23 +23 +Connector_PinHeader_1.00mm +PinHeader_1x23_P1.00mm_Vertical +Through hole straight pin header, 1x23, 1.00mm pitch, single row +Through hole pin header THT 1x23 1.00mm single row +0 +23 +23 +Connector_PinHeader_1.00mm +PinHeader_1x23_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x23, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x23 1.00mm single row style1 pin1 left +0 +23 +23 +Connector_PinHeader_1.00mm +PinHeader_1x23_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x23, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x23 1.00mm single row style2 pin1 right +0 +23 +23 +Connector_PinHeader_1.00mm +PinHeader_1x24_P1.00mm_Horizontal +Through hole angled pin header, 1x24, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x24 1.00mm single row +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_1x24_P1.00mm_Vertical +Through hole straight pin header, 1x24, 1.00mm pitch, single row +Through hole pin header THT 1x24 1.00mm single row +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_1x24_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x24, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x24 1.00mm single row style1 pin1 left +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_1x24_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x24, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x24 1.00mm single row style2 pin1 right +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_1x25_P1.00mm_Horizontal +Through hole angled pin header, 1x25, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x25 1.00mm single row +0 +25 +25 +Connector_PinHeader_1.00mm +PinHeader_1x25_P1.00mm_Vertical +Through hole straight pin header, 1x25, 1.00mm pitch, single row +Through hole pin header THT 1x25 1.00mm single row +0 +25 +25 +Connector_PinHeader_1.00mm +PinHeader_1x25_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x25, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x25 1.00mm single row style1 pin1 left +0 +25 +25 +Connector_PinHeader_1.00mm +PinHeader_1x25_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x25, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x25 1.00mm single row style2 pin1 right +0 +25 +25 +Connector_PinHeader_1.00mm +PinHeader_1x26_P1.00mm_Horizontal +Through hole angled pin header, 1x26, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x26 1.00mm single row +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_1x26_P1.00mm_Vertical +Through hole straight pin header, 1x26, 1.00mm pitch, single row +Through hole pin header THT 1x26 1.00mm single row +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_1x26_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x26, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x26 1.00mm single row style1 pin1 left +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_1x26_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x26, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x26 1.00mm single row style2 pin1 right +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_1x27_P1.00mm_Horizontal +Through hole angled pin header, 1x27, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x27 1.00mm single row +0 +27 +27 +Connector_PinHeader_1.00mm +PinHeader_1x27_P1.00mm_Vertical +Through hole straight pin header, 1x27, 1.00mm pitch, single row +Through hole pin header THT 1x27 1.00mm single row +0 +27 +27 +Connector_PinHeader_1.00mm +PinHeader_1x27_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x27, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x27 1.00mm single row style1 pin1 left +0 +27 +27 +Connector_PinHeader_1.00mm +PinHeader_1x27_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x27, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x27 1.00mm single row style2 pin1 right +0 +27 +27 +Connector_PinHeader_1.00mm +PinHeader_1x28_P1.00mm_Horizontal +Through hole angled pin header, 1x28, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x28 1.00mm single row +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_1x28_P1.00mm_Vertical +Through hole straight pin header, 1x28, 1.00mm pitch, single row +Through hole pin header THT 1x28 1.00mm single row +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_1x28_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x28, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x28 1.00mm single row style1 pin1 left +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_1x28_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x28, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x28 1.00mm single row style2 pin1 right +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_1x29_P1.00mm_Horizontal +Through hole angled pin header, 1x29, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x29 1.00mm single row +0 +29 +29 +Connector_PinHeader_1.00mm +PinHeader_1x29_P1.00mm_Vertical +Through hole straight pin header, 1x29, 1.00mm pitch, single row +Through hole pin header THT 1x29 1.00mm single row +0 +29 +29 +Connector_PinHeader_1.00mm +PinHeader_1x29_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x29, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x29 1.00mm single row style1 pin1 left +0 +29 +29 +Connector_PinHeader_1.00mm +PinHeader_1x29_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x29, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x29 1.00mm single row style2 pin1 right +0 +29 +29 +Connector_PinHeader_1.00mm +PinHeader_1x30_P1.00mm_Horizontal +Through hole angled pin header, 1x30, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x30 1.00mm single row +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_1x30_P1.00mm_Vertical +Through hole straight pin header, 1x30, 1.00mm pitch, single row +Through hole pin header THT 1x30 1.00mm single row +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_1x30_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x30, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x30 1.00mm single row style1 pin1 left +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_1x30_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x30, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x30 1.00mm single row style2 pin1 right +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_1x31_P1.00mm_Horizontal +Through hole angled pin header, 1x31, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x31 1.00mm single row +0 +31 +31 +Connector_PinHeader_1.00mm +PinHeader_1x31_P1.00mm_Vertical +Through hole straight pin header, 1x31, 1.00mm pitch, single row +Through hole pin header THT 1x31 1.00mm single row +0 +31 +31 +Connector_PinHeader_1.00mm +PinHeader_1x31_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x31, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x31 1.00mm single row style1 pin1 left +0 +31 +31 +Connector_PinHeader_1.00mm +PinHeader_1x31_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x31, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x31 1.00mm single row style2 pin1 right +0 +31 +31 +Connector_PinHeader_1.00mm +PinHeader_1x32_P1.00mm_Horizontal +Through hole angled pin header, 1x32, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x32 1.00mm single row +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_1x32_P1.00mm_Vertical +Through hole straight pin header, 1x32, 1.00mm pitch, single row +Through hole pin header THT 1x32 1.00mm single row +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_1x32_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x32, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x32 1.00mm single row style1 pin1 left +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_1x32_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x32, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x32 1.00mm single row style2 pin1 right +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_1x33_P1.00mm_Horizontal +Through hole angled pin header, 1x33, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x33 1.00mm single row +0 +33 +33 +Connector_PinHeader_1.00mm +PinHeader_1x33_P1.00mm_Vertical +Through hole straight pin header, 1x33, 1.00mm pitch, single row +Through hole pin header THT 1x33 1.00mm single row +0 +33 +33 +Connector_PinHeader_1.00mm +PinHeader_1x33_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x33, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x33 1.00mm single row style1 pin1 left +0 +33 +33 +Connector_PinHeader_1.00mm +PinHeader_1x33_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x33, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x33 1.00mm single row style2 pin1 right +0 +33 +33 +Connector_PinHeader_1.00mm +PinHeader_1x34_P1.00mm_Horizontal +Through hole angled pin header, 1x34, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x34 1.00mm single row +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_1x34_P1.00mm_Vertical +Through hole straight pin header, 1x34, 1.00mm pitch, single row +Through hole pin header THT 1x34 1.00mm single row +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_1x34_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x34, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x34 1.00mm single row style1 pin1 left +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_1x34_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x34, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x34 1.00mm single row style2 pin1 right +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_1x35_P1.00mm_Horizontal +Through hole angled pin header, 1x35, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x35 1.00mm single row +0 +35 +35 +Connector_PinHeader_1.00mm +PinHeader_1x35_P1.00mm_Vertical +Through hole straight pin header, 1x35, 1.00mm pitch, single row +Through hole pin header THT 1x35 1.00mm single row +0 +35 +35 +Connector_PinHeader_1.00mm +PinHeader_1x35_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x35, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x35 1.00mm single row style1 pin1 left +0 +35 +35 +Connector_PinHeader_1.00mm +PinHeader_1x35_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x35, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x35 1.00mm single row style2 pin1 right +0 +35 +35 +Connector_PinHeader_1.00mm +PinHeader_1x36_P1.00mm_Horizontal +Through hole angled pin header, 1x36, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x36 1.00mm single row +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_1x36_P1.00mm_Vertical +Through hole straight pin header, 1x36, 1.00mm pitch, single row +Through hole pin header THT 1x36 1.00mm single row +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_1x36_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x36, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x36 1.00mm single row style1 pin1 left +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_1x36_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x36, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x36 1.00mm single row style2 pin1 right +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_1x37_P1.00mm_Horizontal +Through hole angled pin header, 1x37, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x37 1.00mm single row +0 +37 +37 +Connector_PinHeader_1.00mm +PinHeader_1x37_P1.00mm_Vertical +Through hole straight pin header, 1x37, 1.00mm pitch, single row +Through hole pin header THT 1x37 1.00mm single row +0 +37 +37 +Connector_PinHeader_1.00mm +PinHeader_1x37_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x37, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x37 1.00mm single row style1 pin1 left +0 +37 +37 +Connector_PinHeader_1.00mm +PinHeader_1x37_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x37, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x37 1.00mm single row style2 pin1 right +0 +37 +37 +Connector_PinHeader_1.00mm +PinHeader_1x38_P1.00mm_Horizontal +Through hole angled pin header, 1x38, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x38 1.00mm single row +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_1x38_P1.00mm_Vertical +Through hole straight pin header, 1x38, 1.00mm pitch, single row +Through hole pin header THT 1x38 1.00mm single row +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_1x38_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x38, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x38 1.00mm single row style1 pin1 left +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_1x38_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x38, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x38 1.00mm single row style2 pin1 right +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_1x39_P1.00mm_Horizontal +Through hole angled pin header, 1x39, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x39 1.00mm single row +0 +39 +39 +Connector_PinHeader_1.00mm +PinHeader_1x39_P1.00mm_Vertical +Through hole straight pin header, 1x39, 1.00mm pitch, single row +Through hole pin header THT 1x39 1.00mm single row +0 +39 +39 +Connector_PinHeader_1.00mm +PinHeader_1x39_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x39, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x39 1.00mm single row style1 pin1 left +0 +39 +39 +Connector_PinHeader_1.00mm +PinHeader_1x39_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x39, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x39 1.00mm single row style2 pin1 right +0 +39 +39 +Connector_PinHeader_1.00mm +PinHeader_1x40_P1.00mm_Horizontal +Through hole angled pin header, 1x40, 1.00mm pitch, 2.0mm pin length, single row +Through hole angled pin header THT 1x40 1.00mm single row +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_1x40_P1.00mm_Vertical +Through hole straight pin header, 1x40, 1.00mm pitch, single row +Through hole pin header THT 1x40 1.00mm single row +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_1x40_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x40, 1.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x40 1.00mm single row style1 pin1 left +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_1x40_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x40, 1.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x40 1.00mm single row style2 pin1 right +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_2x01_P1.00mm_Horizontal +Through hole angled pin header, 2x01, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x01 1.00mm double row +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_2x01_P1.00mm_Vertical +Through hole straight pin header, 2x01, 1.00mm pitch, double rows +Through hole pin header THT 2x01 1.00mm double row +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_2x01_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x01, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x01 1.00mm double row +0 +2 +2 +Connector_PinHeader_1.00mm +PinHeader_2x02_P1.00mm_Horizontal +Through hole angled pin header, 2x02, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x02 1.00mm double row +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_2x02_P1.00mm_Vertical +Through hole straight pin header, 2x02, 1.00mm pitch, double rows +Through hole pin header THT 2x02 1.00mm double row +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_2x02_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x02, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x02 1.00mm double row +0 +4 +4 +Connector_PinHeader_1.00mm +PinHeader_2x03_P1.00mm_Horizontal +Through hole angled pin header, 2x03, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x03 1.00mm double row +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_2x03_P1.00mm_Vertical +Through hole straight pin header, 2x03, 1.00mm pitch, double rows +Through hole pin header THT 2x03 1.00mm double row +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_2x03_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x03, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x03 1.00mm double row +0 +6 +6 +Connector_PinHeader_1.00mm +PinHeader_2x04_P1.00mm_Horizontal +Through hole angled pin header, 2x04, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x04 1.00mm double row +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_2x04_P1.00mm_Vertical +Through hole straight pin header, 2x04, 1.00mm pitch, double rows +Through hole pin header THT 2x04 1.00mm double row +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_2x04_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x04, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x04 1.00mm double row +0 +8 +8 +Connector_PinHeader_1.00mm +PinHeader_2x05_P1.00mm_Horizontal +Through hole angled pin header, 2x05, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x05 1.00mm double row +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_2x05_P1.00mm_Vertical +Through hole straight pin header, 2x05, 1.00mm pitch, double rows +Through hole pin header THT 2x05 1.00mm double row +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_2x05_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x05, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x05 1.00mm double row +0 +10 +10 +Connector_PinHeader_1.00mm +PinHeader_2x06_P1.00mm_Horizontal +Through hole angled pin header, 2x06, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x06 1.00mm double row +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_2x06_P1.00mm_Vertical +Through hole straight pin header, 2x06, 1.00mm pitch, double rows +Through hole pin header THT 2x06 1.00mm double row +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_2x06_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x06, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x06 1.00mm double row +0 +12 +12 +Connector_PinHeader_1.00mm +PinHeader_2x07_P1.00mm_Horizontal +Through hole angled pin header, 2x07, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x07 1.00mm double row +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_2x07_P1.00mm_Vertical +Through hole straight pin header, 2x07, 1.00mm pitch, double rows +Through hole pin header THT 2x07 1.00mm double row +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_2x07_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x07, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x07 1.00mm double row +0 +14 +14 +Connector_PinHeader_1.00mm +PinHeader_2x08_P1.00mm_Horizontal +Through hole angled pin header, 2x08, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x08 1.00mm double row +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_2x08_P1.00mm_Vertical +Through hole straight pin header, 2x08, 1.00mm pitch, double rows +Through hole pin header THT 2x08 1.00mm double row +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_2x08_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x08, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x08 1.00mm double row +0 +16 +16 +Connector_PinHeader_1.00mm +PinHeader_2x09_P1.00mm_Horizontal +Through hole angled pin header, 2x09, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x09 1.00mm double row +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_2x09_P1.00mm_Vertical +Through hole straight pin header, 2x09, 1.00mm pitch, double rows +Through hole pin header THT 2x09 1.00mm double row +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_2x09_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x09, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x09 1.00mm double row +0 +18 +18 +Connector_PinHeader_1.00mm +PinHeader_2x10_P1.00mm_Horizontal +Through hole angled pin header, 2x10, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x10 1.00mm double row +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_2x10_P1.00mm_Vertical +Through hole straight pin header, 2x10, 1.00mm pitch, double rows +Through hole pin header THT 2x10 1.00mm double row +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_2x10_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x10, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x10 1.00mm double row +0 +20 +20 +Connector_PinHeader_1.00mm +PinHeader_2x11_P1.00mm_Horizontal +Through hole angled pin header, 2x11, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x11 1.00mm double row +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_2x11_P1.00mm_Vertical +Through hole straight pin header, 2x11, 1.00mm pitch, double rows +Through hole pin header THT 2x11 1.00mm double row +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_2x11_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x11, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x11 1.00mm double row +0 +22 +22 +Connector_PinHeader_1.00mm +PinHeader_2x12_P1.00mm_Horizontal +Through hole angled pin header, 2x12, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x12 1.00mm double row +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_2x12_P1.00mm_Vertical +Through hole straight pin header, 2x12, 1.00mm pitch, double rows +Through hole pin header THT 2x12 1.00mm double row +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_2x12_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x12, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x12 1.00mm double row +0 +24 +24 +Connector_PinHeader_1.00mm +PinHeader_2x13_P1.00mm_Horizontal +Through hole angled pin header, 2x13, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x13 1.00mm double row +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_2x13_P1.00mm_Vertical +Through hole straight pin header, 2x13, 1.00mm pitch, double rows +Through hole pin header THT 2x13 1.00mm double row +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_2x13_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x13, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x13 1.00mm double row +0 +26 +26 +Connector_PinHeader_1.00mm +PinHeader_2x14_P1.00mm_Horizontal +Through hole angled pin header, 2x14, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x14 1.00mm double row +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_2x14_P1.00mm_Vertical +Through hole straight pin header, 2x14, 1.00mm pitch, double rows +Through hole pin header THT 2x14 1.00mm double row +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_2x14_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x14, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x14 1.00mm double row +0 +28 +28 +Connector_PinHeader_1.00mm +PinHeader_2x15_P1.00mm_Horizontal +Through hole angled pin header, 2x15, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x15 1.00mm double row +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_2x15_P1.00mm_Vertical +Through hole straight pin header, 2x15, 1.00mm pitch, double rows +Through hole pin header THT 2x15 1.00mm double row +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_2x15_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x15, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x15 1.00mm double row +0 +30 +30 +Connector_PinHeader_1.00mm +PinHeader_2x16_P1.00mm_Horizontal +Through hole angled pin header, 2x16, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x16 1.00mm double row +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_2x16_P1.00mm_Vertical +Through hole straight pin header, 2x16, 1.00mm pitch, double rows +Through hole pin header THT 2x16 1.00mm double row +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_2x16_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x16, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x16 1.00mm double row +0 +32 +32 +Connector_PinHeader_1.00mm +PinHeader_2x17_P1.00mm_Horizontal +Through hole angled pin header, 2x17, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x17 1.00mm double row +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_2x17_P1.00mm_Vertical +Through hole straight pin header, 2x17, 1.00mm pitch, double rows +Through hole pin header THT 2x17 1.00mm double row +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_2x17_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x17, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x17 1.00mm double row +0 +34 +34 +Connector_PinHeader_1.00mm +PinHeader_2x18_P1.00mm_Horizontal +Through hole angled pin header, 2x18, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x18 1.00mm double row +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_2x18_P1.00mm_Vertical +Through hole straight pin header, 2x18, 1.00mm pitch, double rows +Through hole pin header THT 2x18 1.00mm double row +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_2x18_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x18, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x18 1.00mm double row +0 +36 +36 +Connector_PinHeader_1.00mm +PinHeader_2x19_P1.00mm_Horizontal +Through hole angled pin header, 2x19, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x19 1.00mm double row +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_2x19_P1.00mm_Vertical +Through hole straight pin header, 2x19, 1.00mm pitch, double rows +Through hole pin header THT 2x19 1.00mm double row +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_2x19_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x19, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x19 1.00mm double row +0 +38 +38 +Connector_PinHeader_1.00mm +PinHeader_2x20_P1.00mm_Horizontal +Through hole angled pin header, 2x20, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x20 1.00mm double row +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_2x20_P1.00mm_Vertical +Through hole straight pin header, 2x20, 1.00mm pitch, double rows +Through hole pin header THT 2x20 1.00mm double row +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_2x20_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x20, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x20 1.00mm double row +0 +40 +40 +Connector_PinHeader_1.00mm +PinHeader_2x21_P1.00mm_Horizontal +Through hole angled pin header, 2x21, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x21 1.00mm double row +0 +42 +42 +Connector_PinHeader_1.00mm +PinHeader_2x21_P1.00mm_Vertical +Through hole straight pin header, 2x21, 1.00mm pitch, double rows +Through hole pin header THT 2x21 1.00mm double row +0 +42 +42 +Connector_PinHeader_1.00mm +PinHeader_2x21_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x21, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x21 1.00mm double row +0 +42 +42 +Connector_PinHeader_1.00mm +PinHeader_2x22_P1.00mm_Horizontal +Through hole angled pin header, 2x22, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x22 1.00mm double row +0 +44 +44 +Connector_PinHeader_1.00mm +PinHeader_2x22_P1.00mm_Vertical +Through hole straight pin header, 2x22, 1.00mm pitch, double rows +Through hole pin header THT 2x22 1.00mm double row +0 +44 +44 +Connector_PinHeader_1.00mm +PinHeader_2x22_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x22, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x22 1.00mm double row +0 +44 +44 +Connector_PinHeader_1.00mm +PinHeader_2x23_P1.00mm_Horizontal +Through hole angled pin header, 2x23, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x23 1.00mm double row +0 +46 +46 +Connector_PinHeader_1.00mm +PinHeader_2x23_P1.00mm_Vertical +Through hole straight pin header, 2x23, 1.00mm pitch, double rows +Through hole pin header THT 2x23 1.00mm double row +0 +46 +46 +Connector_PinHeader_1.00mm +PinHeader_2x23_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x23, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x23 1.00mm double row +0 +46 +46 +Connector_PinHeader_1.00mm +PinHeader_2x24_P1.00mm_Horizontal +Through hole angled pin header, 2x24, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x24 1.00mm double row +0 +48 +48 +Connector_PinHeader_1.00mm +PinHeader_2x24_P1.00mm_Vertical +Through hole straight pin header, 2x24, 1.00mm pitch, double rows +Through hole pin header THT 2x24 1.00mm double row +0 +48 +48 +Connector_PinHeader_1.00mm +PinHeader_2x24_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x24, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x24 1.00mm double row +0 +48 +48 +Connector_PinHeader_1.00mm +PinHeader_2x25_P1.00mm_Horizontal +Through hole angled pin header, 2x25, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x25 1.00mm double row +0 +50 +50 +Connector_PinHeader_1.00mm +PinHeader_2x25_P1.00mm_Vertical +Through hole straight pin header, 2x25, 1.00mm pitch, double rows +Through hole pin header THT 2x25 1.00mm double row +0 +50 +50 +Connector_PinHeader_1.00mm +PinHeader_2x25_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x25, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x25 1.00mm double row +0 +50 +50 +Connector_PinHeader_1.00mm +PinHeader_2x26_P1.00mm_Horizontal +Through hole angled pin header, 2x26, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x26 1.00mm double row +0 +52 +52 +Connector_PinHeader_1.00mm +PinHeader_2x26_P1.00mm_Vertical +Through hole straight pin header, 2x26, 1.00mm pitch, double rows +Through hole pin header THT 2x26 1.00mm double row +0 +52 +52 +Connector_PinHeader_1.00mm +PinHeader_2x26_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x26, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x26 1.00mm double row +0 +52 +52 +Connector_PinHeader_1.00mm +PinHeader_2x27_P1.00mm_Horizontal +Through hole angled pin header, 2x27, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x27 1.00mm double row +0 +54 +54 +Connector_PinHeader_1.00mm +PinHeader_2x27_P1.00mm_Vertical +Through hole straight pin header, 2x27, 1.00mm pitch, double rows +Through hole pin header THT 2x27 1.00mm double row +0 +54 +54 +Connector_PinHeader_1.00mm +PinHeader_2x27_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x27, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x27 1.00mm double row +0 +54 +54 +Connector_PinHeader_1.00mm +PinHeader_2x28_P1.00mm_Horizontal +Through hole angled pin header, 2x28, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x28 1.00mm double row +0 +56 +56 +Connector_PinHeader_1.00mm +PinHeader_2x28_P1.00mm_Vertical +Through hole straight pin header, 2x28, 1.00mm pitch, double rows +Through hole pin header THT 2x28 1.00mm double row +0 +56 +56 +Connector_PinHeader_1.00mm +PinHeader_2x28_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x28, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x28 1.00mm double row +0 +56 +56 +Connector_PinHeader_1.00mm +PinHeader_2x29_P1.00mm_Horizontal +Through hole angled pin header, 2x29, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x29 1.00mm double row +0 +58 +58 +Connector_PinHeader_1.00mm +PinHeader_2x29_P1.00mm_Vertical +Through hole straight pin header, 2x29, 1.00mm pitch, double rows +Through hole pin header THT 2x29 1.00mm double row +0 +58 +58 +Connector_PinHeader_1.00mm +PinHeader_2x29_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x29, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x29 1.00mm double row +0 +58 +58 +Connector_PinHeader_1.00mm +PinHeader_2x30_P1.00mm_Horizontal +Through hole angled pin header, 2x30, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x30 1.00mm double row +0 +60 +60 +Connector_PinHeader_1.00mm +PinHeader_2x30_P1.00mm_Vertical +Through hole straight pin header, 2x30, 1.00mm pitch, double rows +Through hole pin header THT 2x30 1.00mm double row +0 +60 +60 +Connector_PinHeader_1.00mm +PinHeader_2x30_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x30, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x30 1.00mm double row +0 +60 +60 +Connector_PinHeader_1.00mm +PinHeader_2x31_P1.00mm_Horizontal +Through hole angled pin header, 2x31, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x31 1.00mm double row +0 +62 +62 +Connector_PinHeader_1.00mm +PinHeader_2x31_P1.00mm_Vertical +Through hole straight pin header, 2x31, 1.00mm pitch, double rows +Through hole pin header THT 2x31 1.00mm double row +0 +62 +62 +Connector_PinHeader_1.00mm +PinHeader_2x31_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x31, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x31 1.00mm double row +0 +62 +62 +Connector_PinHeader_1.00mm +PinHeader_2x32_P1.00mm_Horizontal +Through hole angled pin header, 2x32, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x32 1.00mm double row +0 +64 +64 +Connector_PinHeader_1.00mm +PinHeader_2x32_P1.00mm_Vertical +Through hole straight pin header, 2x32, 1.00mm pitch, double rows +Through hole pin header THT 2x32 1.00mm double row +0 +64 +64 +Connector_PinHeader_1.00mm +PinHeader_2x32_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x32, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x32 1.00mm double row +0 +64 +64 +Connector_PinHeader_1.00mm +PinHeader_2x33_P1.00mm_Horizontal +Through hole angled pin header, 2x33, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x33 1.00mm double row +0 +66 +66 +Connector_PinHeader_1.00mm +PinHeader_2x33_P1.00mm_Vertical +Through hole straight pin header, 2x33, 1.00mm pitch, double rows +Through hole pin header THT 2x33 1.00mm double row +0 +66 +66 +Connector_PinHeader_1.00mm +PinHeader_2x33_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x33, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x33 1.00mm double row +0 +66 +66 +Connector_PinHeader_1.00mm +PinHeader_2x34_P1.00mm_Horizontal +Through hole angled pin header, 2x34, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x34 1.00mm double row +0 +68 +68 +Connector_PinHeader_1.00mm +PinHeader_2x34_P1.00mm_Vertical +Through hole straight pin header, 2x34, 1.00mm pitch, double rows +Through hole pin header THT 2x34 1.00mm double row +0 +68 +68 +Connector_PinHeader_1.00mm +PinHeader_2x34_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x34, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x34 1.00mm double row +0 +68 +68 +Connector_PinHeader_1.00mm +PinHeader_2x35_P1.00mm_Horizontal +Through hole angled pin header, 2x35, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x35 1.00mm double row +0 +70 +70 +Connector_PinHeader_1.00mm +PinHeader_2x35_P1.00mm_Vertical +Through hole straight pin header, 2x35, 1.00mm pitch, double rows +Through hole pin header THT 2x35 1.00mm double row +0 +70 +70 +Connector_PinHeader_1.00mm +PinHeader_2x35_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x35, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x35 1.00mm double row +0 +70 +70 +Connector_PinHeader_1.00mm +PinHeader_2x36_P1.00mm_Horizontal +Through hole angled pin header, 2x36, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x36 1.00mm double row +0 +72 +72 +Connector_PinHeader_1.00mm +PinHeader_2x36_P1.00mm_Vertical +Through hole straight pin header, 2x36, 1.00mm pitch, double rows +Through hole pin header THT 2x36 1.00mm double row +0 +72 +72 +Connector_PinHeader_1.00mm +PinHeader_2x36_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x36, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x36 1.00mm double row +0 +72 +72 +Connector_PinHeader_1.00mm +PinHeader_2x37_P1.00mm_Horizontal +Through hole angled pin header, 2x37, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x37 1.00mm double row +0 +74 +74 +Connector_PinHeader_1.00mm +PinHeader_2x37_P1.00mm_Vertical +Through hole straight pin header, 2x37, 1.00mm pitch, double rows +Through hole pin header THT 2x37 1.00mm double row +0 +74 +74 +Connector_PinHeader_1.00mm +PinHeader_2x37_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x37, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x37 1.00mm double row +0 +74 +74 +Connector_PinHeader_1.00mm +PinHeader_2x38_P1.00mm_Horizontal +Through hole angled pin header, 2x38, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x38 1.00mm double row +0 +76 +76 +Connector_PinHeader_1.00mm +PinHeader_2x38_P1.00mm_Vertical +Through hole straight pin header, 2x38, 1.00mm pitch, double rows +Through hole pin header THT 2x38 1.00mm double row +0 +76 +76 +Connector_PinHeader_1.00mm +PinHeader_2x38_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x38, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x38 1.00mm double row +0 +76 +76 +Connector_PinHeader_1.00mm +PinHeader_2x39_P1.00mm_Horizontal +Through hole angled pin header, 2x39, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x39 1.00mm double row +0 +78 +78 +Connector_PinHeader_1.00mm +PinHeader_2x39_P1.00mm_Vertical +Through hole straight pin header, 2x39, 1.00mm pitch, double rows +Through hole pin header THT 2x39 1.00mm double row +0 +78 +78 +Connector_PinHeader_1.00mm +PinHeader_2x39_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x39, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x39 1.00mm double row +0 +78 +78 +Connector_PinHeader_1.00mm +PinHeader_2x40_P1.00mm_Horizontal +Through hole angled pin header, 2x40, 1.00mm pitch, 2.0mm pin length, double rows +Through hole angled pin header THT 2x40 1.00mm double row +0 +80 +80 +Connector_PinHeader_1.00mm +PinHeader_2x40_P1.00mm_Vertical +Through hole straight pin header, 2x40, 1.00mm pitch, double rows +Through hole pin header THT 2x40 1.00mm double row +0 +80 +80 +Connector_PinHeader_1.00mm +PinHeader_2x40_P1.00mm_Vertical_SMD +surface-mounted straight pin header, 2x40, 1.00mm pitch, double rows +Surface mounted pin header SMD 2x40 1.00mm double row +0 +80 +80 +Connector_PinHeader_1.27mm +PinHeader_1x01_P1.27mm_Horizontal +Through hole angled pin header, 1x01, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x01 1.27mm single row +0 +1 +1 +Connector_PinHeader_1.27mm +PinHeader_1x01_P1.27mm_Vertical +Through hole straight pin header, 1x01, 1.27mm pitch, single row +Through hole pin header THT 1x01 1.27mm single row +0 +1 +1 +Connector_PinHeader_1.27mm +PinHeader_1x02_P1.27mm_Horizontal +Through hole angled pin header, 1x02, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x02 1.27mm single row +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_1x02_P1.27mm_Vertical +Through hole straight pin header, 1x02, 1.27mm pitch, single row +Through hole pin header THT 1x02 1.27mm single row +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_1x02_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x02, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x02 1.27mm single row style1 pin1 left +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_1x02_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x02, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x02 1.27mm single row style2 pin1 right +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_1x03_P1.27mm_Horizontal +Through hole angled pin header, 1x03, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x03 1.27mm single row +0 +3 +3 +Connector_PinHeader_1.27mm +PinHeader_1x03_P1.27mm_Vertical +Through hole straight pin header, 1x03, 1.27mm pitch, single row +Through hole pin header THT 1x03 1.27mm single row +0 +3 +3 +Connector_PinHeader_1.27mm +PinHeader_1x03_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x03, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x03 1.27mm single row style1 pin1 left +0 +3 +3 +Connector_PinHeader_1.27mm +PinHeader_1x03_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x03, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x03 1.27mm single row style2 pin1 right +0 +3 +3 +Connector_PinHeader_1.27mm +PinHeader_1x04_P1.27mm_Horizontal +Through hole angled pin header, 1x04, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x04 1.27mm single row +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_1x04_P1.27mm_Vertical +Through hole straight pin header, 1x04, 1.27mm pitch, single row +Through hole pin header THT 1x04 1.27mm single row +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_1x04_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x04, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x04 1.27mm single row style1 pin1 left +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_1x04_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x04, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x04 1.27mm single row style2 pin1 right +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_1x05_P1.27mm_Horizontal +Through hole angled pin header, 1x05, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x05 1.27mm single row +0 +5 +5 +Connector_PinHeader_1.27mm +PinHeader_1x05_P1.27mm_Vertical +Through hole straight pin header, 1x05, 1.27mm pitch, single row +Through hole pin header THT 1x05 1.27mm single row +0 +5 +5 +Connector_PinHeader_1.27mm +PinHeader_1x05_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x05, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x05 1.27mm single row style1 pin1 left +0 +5 +5 +Connector_PinHeader_1.27mm +PinHeader_1x05_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x05, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x05 1.27mm single row style2 pin1 right +0 +5 +5 +Connector_PinHeader_1.27mm +PinHeader_1x06_P1.27mm_Horizontal +Through hole angled pin header, 1x06, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x06 1.27mm single row +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_1x06_P1.27mm_Vertical +Through hole straight pin header, 1x06, 1.27mm pitch, single row +Through hole pin header THT 1x06 1.27mm single row +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_1x06_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x06, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x06 1.27mm single row style1 pin1 left +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_1x06_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x06, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x06 1.27mm single row style2 pin1 right +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_1x07_P1.27mm_Horizontal +Through hole angled pin header, 1x07, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x07 1.27mm single row +0 +7 +7 +Connector_PinHeader_1.27mm +PinHeader_1x07_P1.27mm_Vertical +Through hole straight pin header, 1x07, 1.27mm pitch, single row +Through hole pin header THT 1x07 1.27mm single row +0 +7 +7 +Connector_PinHeader_1.27mm +PinHeader_1x07_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x07, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x07 1.27mm single row style1 pin1 left +0 +7 +7 +Connector_PinHeader_1.27mm +PinHeader_1x07_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x07, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x07 1.27mm single row style2 pin1 right +0 +7 +7 +Connector_PinHeader_1.27mm +PinHeader_1x08_P1.27mm_Horizontal +Through hole angled pin header, 1x08, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x08 1.27mm single row +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_1x08_P1.27mm_Vertical +Through hole straight pin header, 1x08, 1.27mm pitch, single row +Through hole pin header THT 1x08 1.27mm single row +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_1x08_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x08, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x08 1.27mm single row style1 pin1 left +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_1x08_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x08, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x08 1.27mm single row style2 pin1 right +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_1x09_P1.27mm_Horizontal +Through hole angled pin header, 1x09, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x09 1.27mm single row +0 +9 +9 +Connector_PinHeader_1.27mm +PinHeader_1x09_P1.27mm_Vertical +Through hole straight pin header, 1x09, 1.27mm pitch, single row +Through hole pin header THT 1x09 1.27mm single row +0 +9 +9 +Connector_PinHeader_1.27mm +PinHeader_1x09_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x09, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x09 1.27mm single row style1 pin1 left +0 +9 +9 +Connector_PinHeader_1.27mm +PinHeader_1x09_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x09, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x09 1.27mm single row style2 pin1 right +0 +9 +9 +Connector_PinHeader_1.27mm +PinHeader_1x10_P1.27mm_Horizontal +Through hole angled pin header, 1x10, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x10 1.27mm single row +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_1x10_P1.27mm_Vertical +Through hole straight pin header, 1x10, 1.27mm pitch, single row +Through hole pin header THT 1x10 1.27mm single row +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_1x10_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x10, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x10 1.27mm single row style1 pin1 left +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_1x10_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x10, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x10 1.27mm single row style2 pin1 right +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_1x11_P1.27mm_Horizontal +Through hole angled pin header, 1x11, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x11 1.27mm single row +0 +11 +11 +Connector_PinHeader_1.27mm +PinHeader_1x11_P1.27mm_Vertical +Through hole straight pin header, 1x11, 1.27mm pitch, single row +Through hole pin header THT 1x11 1.27mm single row +0 +11 +11 +Connector_PinHeader_1.27mm +PinHeader_1x11_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x11, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x11 1.27mm single row style1 pin1 left +0 +11 +11 +Connector_PinHeader_1.27mm +PinHeader_1x11_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x11, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x11 1.27mm single row style2 pin1 right +0 +11 +11 +Connector_PinHeader_1.27mm +PinHeader_1x12_P1.27mm_Horizontal +Through hole angled pin header, 1x12, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x12 1.27mm single row +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_1x12_P1.27mm_Vertical +Through hole straight pin header, 1x12, 1.27mm pitch, single row +Through hole pin header THT 1x12 1.27mm single row +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_1x12_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x12, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x12 1.27mm single row style1 pin1 left +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_1x12_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x12, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x12 1.27mm single row style2 pin1 right +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_1x13_P1.27mm_Horizontal +Through hole angled pin header, 1x13, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x13 1.27mm single row +0 +13 +13 +Connector_PinHeader_1.27mm +PinHeader_1x13_P1.27mm_Vertical +Through hole straight pin header, 1x13, 1.27mm pitch, single row +Through hole pin header THT 1x13 1.27mm single row +0 +13 +13 +Connector_PinHeader_1.27mm +PinHeader_1x13_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x13, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x13 1.27mm single row style1 pin1 left +0 +13 +13 +Connector_PinHeader_1.27mm +PinHeader_1x13_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x13, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x13 1.27mm single row style2 pin1 right +0 +13 +13 +Connector_PinHeader_1.27mm +PinHeader_1x14_P1.27mm_Horizontal +Through hole angled pin header, 1x14, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x14 1.27mm single row +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_1x14_P1.27mm_Vertical +Through hole straight pin header, 1x14, 1.27mm pitch, single row +Through hole pin header THT 1x14 1.27mm single row +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_1x14_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x14, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x14 1.27mm single row style1 pin1 left +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_1x14_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x14, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x14 1.27mm single row style2 pin1 right +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_1x15_P1.27mm_Horizontal +Through hole angled pin header, 1x15, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x15 1.27mm single row +0 +15 +15 +Connector_PinHeader_1.27mm +PinHeader_1x15_P1.27mm_Vertical +Through hole straight pin header, 1x15, 1.27mm pitch, single row +Through hole pin header THT 1x15 1.27mm single row +0 +15 +15 +Connector_PinHeader_1.27mm +PinHeader_1x15_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x15, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x15 1.27mm single row style1 pin1 left +0 +15 +15 +Connector_PinHeader_1.27mm +PinHeader_1x15_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x15, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x15 1.27mm single row style2 pin1 right +0 +15 +15 +Connector_PinHeader_1.27mm +PinHeader_1x16_P1.27mm_Horizontal +Through hole angled pin header, 1x16, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x16 1.27mm single row +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_1x16_P1.27mm_Vertical +Through hole straight pin header, 1x16, 1.27mm pitch, single row +Through hole pin header THT 1x16 1.27mm single row +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_1x16_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x16, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x16 1.27mm single row style1 pin1 left +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_1x16_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x16, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x16 1.27mm single row style2 pin1 right +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_1x17_P1.27mm_Horizontal +Through hole angled pin header, 1x17, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x17 1.27mm single row +0 +17 +17 +Connector_PinHeader_1.27mm +PinHeader_1x17_P1.27mm_Vertical +Through hole straight pin header, 1x17, 1.27mm pitch, single row +Through hole pin header THT 1x17 1.27mm single row +0 +17 +17 +Connector_PinHeader_1.27mm +PinHeader_1x17_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x17, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x17 1.27mm single row style1 pin1 left +0 +17 +17 +Connector_PinHeader_1.27mm +PinHeader_1x17_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x17, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x17 1.27mm single row style2 pin1 right +0 +17 +17 +Connector_PinHeader_1.27mm +PinHeader_1x18_P1.27mm_Horizontal +Through hole angled pin header, 1x18, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x18 1.27mm single row +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_1x18_P1.27mm_Vertical +Through hole straight pin header, 1x18, 1.27mm pitch, single row +Through hole pin header THT 1x18 1.27mm single row +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_1x18_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x18, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x18 1.27mm single row style1 pin1 left +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_1x18_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x18, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x18 1.27mm single row style2 pin1 right +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_1x19_P1.27mm_Horizontal +Through hole angled pin header, 1x19, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x19 1.27mm single row +0 +19 +19 +Connector_PinHeader_1.27mm +PinHeader_1x19_P1.27mm_Vertical +Through hole straight pin header, 1x19, 1.27mm pitch, single row +Through hole pin header THT 1x19 1.27mm single row +0 +19 +19 +Connector_PinHeader_1.27mm +PinHeader_1x19_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x19, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x19 1.27mm single row style1 pin1 left +0 +19 +19 +Connector_PinHeader_1.27mm +PinHeader_1x19_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x19, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x19 1.27mm single row style2 pin1 right +0 +19 +19 +Connector_PinHeader_1.27mm +PinHeader_1x20_P1.27mm_Horizontal +Through hole angled pin header, 1x20, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x20 1.27mm single row +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_1x20_P1.27mm_Vertical +Through hole straight pin header, 1x20, 1.27mm pitch, single row +Through hole pin header THT 1x20 1.27mm single row +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_1x20_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x20, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x20 1.27mm single row style1 pin1 left +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_1x20_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x20, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x20 1.27mm single row style2 pin1 right +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_1x21_P1.27mm_Horizontal +Through hole angled pin header, 1x21, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x21 1.27mm single row +0 +21 +21 +Connector_PinHeader_1.27mm +PinHeader_1x21_P1.27mm_Vertical +Through hole straight pin header, 1x21, 1.27mm pitch, single row +Through hole pin header THT 1x21 1.27mm single row +0 +21 +21 +Connector_PinHeader_1.27mm +PinHeader_1x21_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x21, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x21 1.27mm single row style1 pin1 left +0 +21 +21 +Connector_PinHeader_1.27mm +PinHeader_1x21_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x21, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x21 1.27mm single row style2 pin1 right +0 +21 +21 +Connector_PinHeader_1.27mm +PinHeader_1x22_P1.27mm_Horizontal +Through hole angled pin header, 1x22, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x22 1.27mm single row +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_1x22_P1.27mm_Vertical +Through hole straight pin header, 1x22, 1.27mm pitch, single row +Through hole pin header THT 1x22 1.27mm single row +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_1x22_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x22, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x22 1.27mm single row style1 pin1 left +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_1x22_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x22, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x22 1.27mm single row style2 pin1 right +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_1x23_P1.27mm_Horizontal +Through hole angled pin header, 1x23, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x23 1.27mm single row +0 +23 +23 +Connector_PinHeader_1.27mm +PinHeader_1x23_P1.27mm_Vertical +Through hole straight pin header, 1x23, 1.27mm pitch, single row +Through hole pin header THT 1x23 1.27mm single row +0 +23 +23 +Connector_PinHeader_1.27mm +PinHeader_1x23_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x23, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x23 1.27mm single row style1 pin1 left +0 +23 +23 +Connector_PinHeader_1.27mm +PinHeader_1x23_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x23, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x23 1.27mm single row style2 pin1 right +0 +23 +23 +Connector_PinHeader_1.27mm +PinHeader_1x24_P1.27mm_Horizontal +Through hole angled pin header, 1x24, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x24 1.27mm single row +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_1x24_P1.27mm_Vertical +Through hole straight pin header, 1x24, 1.27mm pitch, single row +Through hole pin header THT 1x24 1.27mm single row +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_1x24_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x24, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x24 1.27mm single row style1 pin1 left +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_1x24_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x24, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x24 1.27mm single row style2 pin1 right +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_1x25_P1.27mm_Horizontal +Through hole angled pin header, 1x25, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x25 1.27mm single row +0 +25 +25 +Connector_PinHeader_1.27mm +PinHeader_1x25_P1.27mm_Vertical +Through hole straight pin header, 1x25, 1.27mm pitch, single row +Through hole pin header THT 1x25 1.27mm single row +0 +25 +25 +Connector_PinHeader_1.27mm +PinHeader_1x25_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x25, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x25 1.27mm single row style1 pin1 left +0 +25 +25 +Connector_PinHeader_1.27mm +PinHeader_1x25_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x25, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x25 1.27mm single row style2 pin1 right +0 +25 +25 +Connector_PinHeader_1.27mm +PinHeader_1x26_P1.27mm_Horizontal +Through hole angled pin header, 1x26, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x26 1.27mm single row +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_1x26_P1.27mm_Vertical +Through hole straight pin header, 1x26, 1.27mm pitch, single row +Through hole pin header THT 1x26 1.27mm single row +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_1x26_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x26, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x26 1.27mm single row style1 pin1 left +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_1x26_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x26, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x26 1.27mm single row style2 pin1 right +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_1x27_P1.27mm_Horizontal +Through hole angled pin header, 1x27, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x27 1.27mm single row +0 +27 +27 +Connector_PinHeader_1.27mm +PinHeader_1x27_P1.27mm_Vertical +Through hole straight pin header, 1x27, 1.27mm pitch, single row +Through hole pin header THT 1x27 1.27mm single row +0 +27 +27 +Connector_PinHeader_1.27mm +PinHeader_1x27_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x27, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x27 1.27mm single row style1 pin1 left +0 +27 +27 +Connector_PinHeader_1.27mm +PinHeader_1x27_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x27, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x27 1.27mm single row style2 pin1 right +0 +27 +27 +Connector_PinHeader_1.27mm +PinHeader_1x28_P1.27mm_Horizontal +Through hole angled pin header, 1x28, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x28 1.27mm single row +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_1x28_P1.27mm_Vertical +Through hole straight pin header, 1x28, 1.27mm pitch, single row +Through hole pin header THT 1x28 1.27mm single row +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_1x28_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x28, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x28 1.27mm single row style1 pin1 left +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_1x28_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x28, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x28 1.27mm single row style2 pin1 right +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_1x29_P1.27mm_Horizontal +Through hole angled pin header, 1x29, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x29 1.27mm single row +0 +29 +29 +Connector_PinHeader_1.27mm +PinHeader_1x29_P1.27mm_Vertical +Through hole straight pin header, 1x29, 1.27mm pitch, single row +Through hole pin header THT 1x29 1.27mm single row +0 +29 +29 +Connector_PinHeader_1.27mm +PinHeader_1x29_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x29, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x29 1.27mm single row style1 pin1 left +0 +29 +29 +Connector_PinHeader_1.27mm +PinHeader_1x29_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x29, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x29 1.27mm single row style2 pin1 right +0 +29 +29 +Connector_PinHeader_1.27mm +PinHeader_1x30_P1.27mm_Horizontal +Through hole angled pin header, 1x30, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x30 1.27mm single row +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_1x30_P1.27mm_Vertical +Through hole straight pin header, 1x30, 1.27mm pitch, single row +Through hole pin header THT 1x30 1.27mm single row +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_1x30_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x30, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x30 1.27mm single row style1 pin1 left +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_1x30_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x30, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x30 1.27mm single row style2 pin1 right +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_1x31_P1.27mm_Horizontal +Through hole angled pin header, 1x31, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x31 1.27mm single row +0 +31 +31 +Connector_PinHeader_1.27mm +PinHeader_1x31_P1.27mm_Vertical +Through hole straight pin header, 1x31, 1.27mm pitch, single row +Through hole pin header THT 1x31 1.27mm single row +0 +31 +31 +Connector_PinHeader_1.27mm +PinHeader_1x31_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x31, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x31 1.27mm single row style1 pin1 left +0 +31 +31 +Connector_PinHeader_1.27mm +PinHeader_1x31_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x31, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x31 1.27mm single row style2 pin1 right +0 +31 +31 +Connector_PinHeader_1.27mm +PinHeader_1x32_P1.27mm_Horizontal +Through hole angled pin header, 1x32, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x32 1.27mm single row +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_1x32_P1.27mm_Vertical +Through hole straight pin header, 1x32, 1.27mm pitch, single row +Through hole pin header THT 1x32 1.27mm single row +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_1x32_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x32, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x32 1.27mm single row style1 pin1 left +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_1x32_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x32, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x32 1.27mm single row style2 pin1 right +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_1x33_P1.27mm_Horizontal +Through hole angled pin header, 1x33, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x33 1.27mm single row +0 +33 +33 +Connector_PinHeader_1.27mm +PinHeader_1x33_P1.27mm_Vertical +Through hole straight pin header, 1x33, 1.27mm pitch, single row +Through hole pin header THT 1x33 1.27mm single row +0 +33 +33 +Connector_PinHeader_1.27mm +PinHeader_1x33_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x33, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x33 1.27mm single row style1 pin1 left +0 +33 +33 +Connector_PinHeader_1.27mm +PinHeader_1x33_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x33, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x33 1.27mm single row style2 pin1 right +0 +33 +33 +Connector_PinHeader_1.27mm +PinHeader_1x34_P1.27mm_Horizontal +Through hole angled pin header, 1x34, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x34 1.27mm single row +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_1x34_P1.27mm_Vertical +Through hole straight pin header, 1x34, 1.27mm pitch, single row +Through hole pin header THT 1x34 1.27mm single row +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_1x34_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x34, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x34 1.27mm single row style1 pin1 left +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_1x34_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x34, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x34 1.27mm single row style2 pin1 right +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_1x35_P1.27mm_Horizontal +Through hole angled pin header, 1x35, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x35 1.27mm single row +0 +35 +35 +Connector_PinHeader_1.27mm +PinHeader_1x35_P1.27mm_Vertical +Through hole straight pin header, 1x35, 1.27mm pitch, single row +Through hole pin header THT 1x35 1.27mm single row +0 +35 +35 +Connector_PinHeader_1.27mm +PinHeader_1x35_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x35, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x35 1.27mm single row style1 pin1 left +0 +35 +35 +Connector_PinHeader_1.27mm +PinHeader_1x35_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x35, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x35 1.27mm single row style2 pin1 right +0 +35 +35 +Connector_PinHeader_1.27mm +PinHeader_1x36_P1.27mm_Horizontal +Through hole angled pin header, 1x36, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x36 1.27mm single row +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_1x36_P1.27mm_Vertical +Through hole straight pin header, 1x36, 1.27mm pitch, single row +Through hole pin header THT 1x36 1.27mm single row +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_1x36_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x36, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x36 1.27mm single row style1 pin1 left +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_1x36_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x36, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x36 1.27mm single row style2 pin1 right +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_1x37_P1.27mm_Horizontal +Through hole angled pin header, 1x37, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x37 1.27mm single row +0 +37 +37 +Connector_PinHeader_1.27mm +PinHeader_1x37_P1.27mm_Vertical +Through hole straight pin header, 1x37, 1.27mm pitch, single row +Through hole pin header THT 1x37 1.27mm single row +0 +37 +37 +Connector_PinHeader_1.27mm +PinHeader_1x37_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x37, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x37 1.27mm single row style1 pin1 left +0 +37 +37 +Connector_PinHeader_1.27mm +PinHeader_1x37_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x37, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x37 1.27mm single row style2 pin1 right +0 +37 +37 +Connector_PinHeader_1.27mm +PinHeader_1x38_P1.27mm_Horizontal +Through hole angled pin header, 1x38, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x38 1.27mm single row +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_1x38_P1.27mm_Vertical +Through hole straight pin header, 1x38, 1.27mm pitch, single row +Through hole pin header THT 1x38 1.27mm single row +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_1x38_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x38, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x38 1.27mm single row style1 pin1 left +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_1x38_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x38, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x38 1.27mm single row style2 pin1 right +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_1x39_P1.27mm_Horizontal +Through hole angled pin header, 1x39, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x39 1.27mm single row +0 +39 +39 +Connector_PinHeader_1.27mm +PinHeader_1x39_P1.27mm_Vertical +Through hole straight pin header, 1x39, 1.27mm pitch, single row +Through hole pin header THT 1x39 1.27mm single row +0 +39 +39 +Connector_PinHeader_1.27mm +PinHeader_1x39_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x39, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x39 1.27mm single row style1 pin1 left +0 +39 +39 +Connector_PinHeader_1.27mm +PinHeader_1x39_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x39, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x39 1.27mm single row style2 pin1 right +0 +39 +39 +Connector_PinHeader_1.27mm +PinHeader_1x40_P1.27mm_Horizontal +Through hole angled pin header, 1x40, 1.27mm pitch, 4.0mm pin length, single row +Through hole angled pin header THT 1x40 1.27mm single row +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_1x40_P1.27mm_Vertical +Through hole straight pin header, 1x40, 1.27mm pitch, single row +Through hole pin header THT 1x40 1.27mm single row +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_1x40_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x40, 1.27mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x40 1.27mm single row style1 pin1 left +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_1x40_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x40, 1.27mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x40 1.27mm single row style2 pin1 right +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_2x01_P1.27mm_Horizontal +Through hole angled pin header, 2x01, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x01 1.27mm double row +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_2x01_P1.27mm_Vertical +Through hole straight pin header, 2x01, 1.27mm pitch, double rows +Through hole pin header THT 2x01 1.27mm double row +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_2x01_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x01, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x01 1.27mm double row +0 +2 +2 +Connector_PinHeader_1.27mm +PinHeader_2x02_P1.27mm_Horizontal +Through hole angled pin header, 2x02, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x02 1.27mm double row +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_2x02_P1.27mm_Vertical +Through hole straight pin header, 2x02, 1.27mm pitch, double rows +Through hole pin header THT 2x02 1.27mm double row +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_2x02_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x02, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x02 1.27mm double row +0 +4 +4 +Connector_PinHeader_1.27mm +PinHeader_2x03_P1.27mm_Horizontal +Through hole angled pin header, 2x03, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x03 1.27mm double row +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_2x03_P1.27mm_Vertical +Through hole straight pin header, 2x03, 1.27mm pitch, double rows +Through hole pin header THT 2x03 1.27mm double row +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_2x03_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x03, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x03 1.27mm double row +0 +6 +6 +Connector_PinHeader_1.27mm +PinHeader_2x04_P1.27mm_Horizontal +Through hole angled pin header, 2x04, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x04 1.27mm double row +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_2x04_P1.27mm_Vertical +Through hole straight pin header, 2x04, 1.27mm pitch, double rows +Through hole pin header THT 2x04 1.27mm double row +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_2x04_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x04, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x04 1.27mm double row +0 +8 +8 +Connector_PinHeader_1.27mm +PinHeader_2x05_P1.27mm_Horizontal +Through hole angled pin header, 2x05, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x05 1.27mm double row +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_2x05_P1.27mm_Vertical +Through hole straight pin header, 2x05, 1.27mm pitch, double rows +Through hole pin header THT 2x05 1.27mm double row +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_2x05_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x05, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x05 1.27mm double row +0 +10 +10 +Connector_PinHeader_1.27mm +PinHeader_2x06_P1.27mm_Horizontal +Through hole angled pin header, 2x06, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x06 1.27mm double row +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_2x06_P1.27mm_Vertical +Through hole straight pin header, 2x06, 1.27mm pitch, double rows +Through hole pin header THT 2x06 1.27mm double row +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_2x06_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x06, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x06 1.27mm double row +0 +12 +12 +Connector_PinHeader_1.27mm +PinHeader_2x07_P1.27mm_Horizontal +Through hole angled pin header, 2x07, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x07 1.27mm double row +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_2x07_P1.27mm_Vertical +Through hole straight pin header, 2x07, 1.27mm pitch, double rows +Through hole pin header THT 2x07 1.27mm double row +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_2x07_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x07, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x07 1.27mm double row +0 +14 +14 +Connector_PinHeader_1.27mm +PinHeader_2x08_P1.27mm_Horizontal +Through hole angled pin header, 2x08, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x08 1.27mm double row +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_2x08_P1.27mm_Vertical +Through hole straight pin header, 2x08, 1.27mm pitch, double rows +Through hole pin header THT 2x08 1.27mm double row +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_2x08_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x08, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x08 1.27mm double row +0 +16 +16 +Connector_PinHeader_1.27mm +PinHeader_2x09_P1.27mm_Horizontal +Through hole angled pin header, 2x09, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x09 1.27mm double row +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_2x09_P1.27mm_Vertical +Through hole straight pin header, 2x09, 1.27mm pitch, double rows +Through hole pin header THT 2x09 1.27mm double row +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_2x09_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x09, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x09 1.27mm double row +0 +18 +18 +Connector_PinHeader_1.27mm +PinHeader_2x10_P1.27mm_Horizontal +Through hole angled pin header, 2x10, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x10 1.27mm double row +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_2x10_P1.27mm_Vertical +Through hole straight pin header, 2x10, 1.27mm pitch, double rows +Through hole pin header THT 2x10 1.27mm double row +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_2x10_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x10, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x10 1.27mm double row +0 +20 +20 +Connector_PinHeader_1.27mm +PinHeader_2x11_P1.27mm_Horizontal +Through hole angled pin header, 2x11, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x11 1.27mm double row +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_2x11_P1.27mm_Vertical +Through hole straight pin header, 2x11, 1.27mm pitch, double rows +Through hole pin header THT 2x11 1.27mm double row +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_2x11_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x11, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x11 1.27mm double row +0 +22 +22 +Connector_PinHeader_1.27mm +PinHeader_2x12_P1.27mm_Horizontal +Through hole angled pin header, 2x12, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x12 1.27mm double row +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_2x12_P1.27mm_Vertical +Through hole straight pin header, 2x12, 1.27mm pitch, double rows +Through hole pin header THT 2x12 1.27mm double row +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_2x12_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x12, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x12 1.27mm double row +0 +24 +24 +Connector_PinHeader_1.27mm +PinHeader_2x13_P1.27mm_Horizontal +Through hole angled pin header, 2x13, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x13 1.27mm double row +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_2x13_P1.27mm_Vertical +Through hole straight pin header, 2x13, 1.27mm pitch, double rows +Through hole pin header THT 2x13 1.27mm double row +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_2x13_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x13, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x13 1.27mm double row +0 +26 +26 +Connector_PinHeader_1.27mm +PinHeader_2x14_P1.27mm_Horizontal +Through hole angled pin header, 2x14, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x14 1.27mm double row +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_2x14_P1.27mm_Vertical +Through hole straight pin header, 2x14, 1.27mm pitch, double rows +Through hole pin header THT 2x14 1.27mm double row +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_2x14_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x14, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x14 1.27mm double row +0 +28 +28 +Connector_PinHeader_1.27mm +PinHeader_2x15_P1.27mm_Horizontal +Through hole angled pin header, 2x15, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x15 1.27mm double row +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_2x15_P1.27mm_Vertical +Through hole straight pin header, 2x15, 1.27mm pitch, double rows +Through hole pin header THT 2x15 1.27mm double row +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_2x15_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x15, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x15 1.27mm double row +0 +30 +30 +Connector_PinHeader_1.27mm +PinHeader_2x16_P1.27mm_Horizontal +Through hole angled pin header, 2x16, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x16 1.27mm double row +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_2x16_P1.27mm_Vertical +Through hole straight pin header, 2x16, 1.27mm pitch, double rows +Through hole pin header THT 2x16 1.27mm double row +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_2x16_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x16, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x16 1.27mm double row +0 +32 +32 +Connector_PinHeader_1.27mm +PinHeader_2x17_P1.27mm_Horizontal +Through hole angled pin header, 2x17, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x17 1.27mm double row +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_2x17_P1.27mm_Vertical +Through hole straight pin header, 2x17, 1.27mm pitch, double rows +Through hole pin header THT 2x17 1.27mm double row +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_2x17_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x17, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x17 1.27mm double row +0 +34 +34 +Connector_PinHeader_1.27mm +PinHeader_2x18_P1.27mm_Horizontal +Through hole angled pin header, 2x18, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x18 1.27mm double row +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_2x18_P1.27mm_Vertical +Through hole straight pin header, 2x18, 1.27mm pitch, double rows +Through hole pin header THT 2x18 1.27mm double row +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_2x18_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x18, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x18 1.27mm double row +0 +36 +36 +Connector_PinHeader_1.27mm +PinHeader_2x19_P1.27mm_Horizontal +Through hole angled pin header, 2x19, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x19 1.27mm double row +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_2x19_P1.27mm_Vertical +Through hole straight pin header, 2x19, 1.27mm pitch, double rows +Through hole pin header THT 2x19 1.27mm double row +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_2x19_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x19, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x19 1.27mm double row +0 +38 +38 +Connector_PinHeader_1.27mm +PinHeader_2x20_P1.27mm_Horizontal +Through hole angled pin header, 2x20, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x20 1.27mm double row +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_2x20_P1.27mm_Vertical +Through hole straight pin header, 2x20, 1.27mm pitch, double rows +Through hole pin header THT 2x20 1.27mm double row +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_2x20_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x20, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x20 1.27mm double row +0 +40 +40 +Connector_PinHeader_1.27mm +PinHeader_2x21_P1.27mm_Horizontal +Through hole angled pin header, 2x21, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x21 1.27mm double row +0 +42 +42 +Connector_PinHeader_1.27mm +PinHeader_2x21_P1.27mm_Vertical +Through hole straight pin header, 2x21, 1.27mm pitch, double rows +Through hole pin header THT 2x21 1.27mm double row +0 +42 +42 +Connector_PinHeader_1.27mm +PinHeader_2x21_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x21, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x21 1.27mm double row +0 +42 +42 +Connector_PinHeader_1.27mm +PinHeader_2x22_P1.27mm_Horizontal +Through hole angled pin header, 2x22, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x22 1.27mm double row +0 +44 +44 +Connector_PinHeader_1.27mm +PinHeader_2x22_P1.27mm_Vertical +Through hole straight pin header, 2x22, 1.27mm pitch, double rows +Through hole pin header THT 2x22 1.27mm double row +0 +44 +44 +Connector_PinHeader_1.27mm +PinHeader_2x22_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x22, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x22 1.27mm double row +0 +44 +44 +Connector_PinHeader_1.27mm +PinHeader_2x23_P1.27mm_Horizontal +Through hole angled pin header, 2x23, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x23 1.27mm double row +0 +46 +46 +Connector_PinHeader_1.27mm +PinHeader_2x23_P1.27mm_Vertical +Through hole straight pin header, 2x23, 1.27mm pitch, double rows +Through hole pin header THT 2x23 1.27mm double row +0 +46 +46 +Connector_PinHeader_1.27mm +PinHeader_2x23_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x23, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x23 1.27mm double row +0 +46 +46 +Connector_PinHeader_1.27mm +PinHeader_2x24_P1.27mm_Horizontal +Through hole angled pin header, 2x24, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x24 1.27mm double row +0 +48 +48 +Connector_PinHeader_1.27mm +PinHeader_2x24_P1.27mm_Vertical +Through hole straight pin header, 2x24, 1.27mm pitch, double rows +Through hole pin header THT 2x24 1.27mm double row +0 +48 +48 +Connector_PinHeader_1.27mm +PinHeader_2x24_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x24, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x24 1.27mm double row +0 +48 +48 +Connector_PinHeader_1.27mm +PinHeader_2x25_P1.27mm_Horizontal +Through hole angled pin header, 2x25, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x25 1.27mm double row +0 +50 +50 +Connector_PinHeader_1.27mm +PinHeader_2x25_P1.27mm_Vertical +Through hole straight pin header, 2x25, 1.27mm pitch, double rows +Through hole pin header THT 2x25 1.27mm double row +0 +50 +50 +Connector_PinHeader_1.27mm +PinHeader_2x25_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x25, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x25 1.27mm double row +0 +50 +50 +Connector_PinHeader_1.27mm +PinHeader_2x26_P1.27mm_Horizontal +Through hole angled pin header, 2x26, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x26 1.27mm double row +0 +52 +52 +Connector_PinHeader_1.27mm +PinHeader_2x26_P1.27mm_Vertical +Through hole straight pin header, 2x26, 1.27mm pitch, double rows +Through hole pin header THT 2x26 1.27mm double row +0 +52 +52 +Connector_PinHeader_1.27mm +PinHeader_2x26_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x26, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x26 1.27mm double row +0 +52 +52 +Connector_PinHeader_1.27mm +PinHeader_2x27_P1.27mm_Horizontal +Through hole angled pin header, 2x27, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x27 1.27mm double row +0 +54 +54 +Connector_PinHeader_1.27mm +PinHeader_2x27_P1.27mm_Vertical +Through hole straight pin header, 2x27, 1.27mm pitch, double rows +Through hole pin header THT 2x27 1.27mm double row +0 +54 +54 +Connector_PinHeader_1.27mm +PinHeader_2x27_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x27, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x27 1.27mm double row +0 +54 +54 +Connector_PinHeader_1.27mm +PinHeader_2x28_P1.27mm_Horizontal +Through hole angled pin header, 2x28, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x28 1.27mm double row +0 +56 +56 +Connector_PinHeader_1.27mm +PinHeader_2x28_P1.27mm_Vertical +Through hole straight pin header, 2x28, 1.27mm pitch, double rows +Through hole pin header THT 2x28 1.27mm double row +0 +56 +56 +Connector_PinHeader_1.27mm +PinHeader_2x28_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x28, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x28 1.27mm double row +0 +56 +56 +Connector_PinHeader_1.27mm +PinHeader_2x29_P1.27mm_Horizontal +Through hole angled pin header, 2x29, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x29 1.27mm double row +0 +58 +58 +Connector_PinHeader_1.27mm +PinHeader_2x29_P1.27mm_Vertical +Through hole straight pin header, 2x29, 1.27mm pitch, double rows +Through hole pin header THT 2x29 1.27mm double row +0 +58 +58 +Connector_PinHeader_1.27mm +PinHeader_2x29_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x29, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x29 1.27mm double row +0 +58 +58 +Connector_PinHeader_1.27mm +PinHeader_2x30_P1.27mm_Horizontal +Through hole angled pin header, 2x30, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x30 1.27mm double row +0 +60 +60 +Connector_PinHeader_1.27mm +PinHeader_2x30_P1.27mm_Vertical +Through hole straight pin header, 2x30, 1.27mm pitch, double rows +Through hole pin header THT 2x30 1.27mm double row +0 +60 +60 +Connector_PinHeader_1.27mm +PinHeader_2x30_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x30, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x30 1.27mm double row +0 +60 +60 +Connector_PinHeader_1.27mm +PinHeader_2x31_P1.27mm_Horizontal +Through hole angled pin header, 2x31, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x31 1.27mm double row +0 +62 +62 +Connector_PinHeader_1.27mm +PinHeader_2x31_P1.27mm_Vertical +Through hole straight pin header, 2x31, 1.27mm pitch, double rows +Through hole pin header THT 2x31 1.27mm double row +0 +62 +62 +Connector_PinHeader_1.27mm +PinHeader_2x31_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x31, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x31 1.27mm double row +0 +62 +62 +Connector_PinHeader_1.27mm +PinHeader_2x32_P1.27mm_Horizontal +Through hole angled pin header, 2x32, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x32 1.27mm double row +0 +64 +64 +Connector_PinHeader_1.27mm +PinHeader_2x32_P1.27mm_Vertical +Through hole straight pin header, 2x32, 1.27mm pitch, double rows +Through hole pin header THT 2x32 1.27mm double row +0 +64 +64 +Connector_PinHeader_1.27mm +PinHeader_2x32_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x32, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x32 1.27mm double row +0 +64 +64 +Connector_PinHeader_1.27mm +PinHeader_2x33_P1.27mm_Horizontal +Through hole angled pin header, 2x33, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x33 1.27mm double row +0 +66 +66 +Connector_PinHeader_1.27mm +PinHeader_2x33_P1.27mm_Vertical +Through hole straight pin header, 2x33, 1.27mm pitch, double rows +Through hole pin header THT 2x33 1.27mm double row +0 +66 +66 +Connector_PinHeader_1.27mm +PinHeader_2x33_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x33, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x33 1.27mm double row +0 +66 +66 +Connector_PinHeader_1.27mm +PinHeader_2x34_P1.27mm_Horizontal +Through hole angled pin header, 2x34, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x34 1.27mm double row +0 +68 +68 +Connector_PinHeader_1.27mm +PinHeader_2x34_P1.27mm_Vertical +Through hole straight pin header, 2x34, 1.27mm pitch, double rows +Through hole pin header THT 2x34 1.27mm double row +0 +68 +68 +Connector_PinHeader_1.27mm +PinHeader_2x34_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x34, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x34 1.27mm double row +0 +68 +68 +Connector_PinHeader_1.27mm +PinHeader_2x35_P1.27mm_Horizontal +Through hole angled pin header, 2x35, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x35 1.27mm double row +0 +70 +70 +Connector_PinHeader_1.27mm +PinHeader_2x35_P1.27mm_Vertical +Through hole straight pin header, 2x35, 1.27mm pitch, double rows +Through hole pin header THT 2x35 1.27mm double row +0 +70 +70 +Connector_PinHeader_1.27mm +PinHeader_2x35_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x35, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x35 1.27mm double row +0 +70 +70 +Connector_PinHeader_1.27mm +PinHeader_2x36_P1.27mm_Horizontal +Through hole angled pin header, 2x36, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x36 1.27mm double row +0 +72 +72 +Connector_PinHeader_1.27mm +PinHeader_2x36_P1.27mm_Vertical +Through hole straight pin header, 2x36, 1.27mm pitch, double rows +Through hole pin header THT 2x36 1.27mm double row +0 +72 +72 +Connector_PinHeader_1.27mm +PinHeader_2x36_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x36, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x36 1.27mm double row +0 +72 +72 +Connector_PinHeader_1.27mm +PinHeader_2x37_P1.27mm_Horizontal +Through hole angled pin header, 2x37, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x37 1.27mm double row +0 +74 +74 +Connector_PinHeader_1.27mm +PinHeader_2x37_P1.27mm_Vertical +Through hole straight pin header, 2x37, 1.27mm pitch, double rows +Through hole pin header THT 2x37 1.27mm double row +0 +74 +74 +Connector_PinHeader_1.27mm +PinHeader_2x37_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x37, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x37 1.27mm double row +0 +74 +74 +Connector_PinHeader_1.27mm +PinHeader_2x38_P1.27mm_Horizontal +Through hole angled pin header, 2x38, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x38 1.27mm double row +0 +76 +76 +Connector_PinHeader_1.27mm +PinHeader_2x38_P1.27mm_Vertical +Through hole straight pin header, 2x38, 1.27mm pitch, double rows +Through hole pin header THT 2x38 1.27mm double row +0 +76 +76 +Connector_PinHeader_1.27mm +PinHeader_2x38_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x38, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x38 1.27mm double row +0 +76 +76 +Connector_PinHeader_1.27mm +PinHeader_2x39_P1.27mm_Horizontal +Through hole angled pin header, 2x39, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x39 1.27mm double row +0 +78 +78 +Connector_PinHeader_1.27mm +PinHeader_2x39_P1.27mm_Vertical +Through hole straight pin header, 2x39, 1.27mm pitch, double rows +Through hole pin header THT 2x39 1.27mm double row +0 +78 +78 +Connector_PinHeader_1.27mm +PinHeader_2x39_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x39, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x39 1.27mm double row +0 +78 +78 +Connector_PinHeader_1.27mm +PinHeader_2x40_P1.27mm_Horizontal +Through hole angled pin header, 2x40, 1.27mm pitch, 4.0mm pin length, double rows +Through hole angled pin header THT 2x40 1.27mm double row +0 +80 +80 +Connector_PinHeader_1.27mm +PinHeader_2x40_P1.27mm_Vertical +Through hole straight pin header, 2x40, 1.27mm pitch, double rows +Through hole pin header THT 2x40 1.27mm double row +0 +80 +80 +Connector_PinHeader_1.27mm +PinHeader_2x40_P1.27mm_Vertical_SMD +surface-mounted straight pin header, 2x40, 1.27mm pitch, double rows +Surface mounted pin header SMD 2x40 1.27mm double row +0 +80 +80 +Connector_PinHeader_2.00mm +PinHeader_1x01_P2.00mm_Horizontal +Through hole angled pin header, 1x01, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x01 2.00mm single row +0 +1 +1 +Connector_PinHeader_2.00mm +PinHeader_1x01_P2.00mm_Vertical +Through hole straight pin header, 1x01, 2.00mm pitch, single row +Through hole pin header THT 1x01 2.00mm single row +0 +1 +1 +Connector_PinHeader_2.00mm +PinHeader_1x02_P2.00mm_Horizontal +Through hole angled pin header, 1x02, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x02 2.00mm single row +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_1x02_P2.00mm_Vertical +Through hole straight pin header, 1x02, 2.00mm pitch, single row +Through hole pin header THT 1x02 2.00mm single row +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_1x02_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x02, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x02 2.00mm single row style1 pin1 left +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_1x02_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x02, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x02 2.00mm single row style2 pin1 right +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_1x03_P2.00mm_Horizontal +Through hole angled pin header, 1x03, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x03 2.00mm single row +0 +3 +3 +Connector_PinHeader_2.00mm +PinHeader_1x03_P2.00mm_Vertical +Through hole straight pin header, 1x03, 2.00mm pitch, single row +Through hole pin header THT 1x03 2.00mm single row +0 +3 +3 +Connector_PinHeader_2.00mm +PinHeader_1x03_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x03, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x03 2.00mm single row style1 pin1 left +0 +3 +3 +Connector_PinHeader_2.00mm +PinHeader_1x03_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x03, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x03 2.00mm single row style2 pin1 right +0 +3 +3 +Connector_PinHeader_2.00mm +PinHeader_1x04_P2.00mm_Horizontal +Through hole angled pin header, 1x04, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x04 2.00mm single row +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_1x04_P2.00mm_Vertical +Through hole straight pin header, 1x04, 2.00mm pitch, single row +Through hole pin header THT 1x04 2.00mm single row +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_1x04_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x04, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x04 2.00mm single row style1 pin1 left +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_1x04_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x04, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x04 2.00mm single row style2 pin1 right +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_1x05_P2.00mm_Horizontal +Through hole angled pin header, 1x05, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x05 2.00mm single row +0 +5 +5 +Connector_PinHeader_2.00mm +PinHeader_1x05_P2.00mm_Vertical +Through hole straight pin header, 1x05, 2.00mm pitch, single row +Through hole pin header THT 1x05 2.00mm single row +0 +5 +5 +Connector_PinHeader_2.00mm +PinHeader_1x05_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x05, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x05 2.00mm single row style1 pin1 left +0 +5 +5 +Connector_PinHeader_2.00mm +PinHeader_1x05_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x05, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x05 2.00mm single row style2 pin1 right +0 +5 +5 +Connector_PinHeader_2.00mm +PinHeader_1x06_P2.00mm_Horizontal +Through hole angled pin header, 1x06, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x06 2.00mm single row +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_1x06_P2.00mm_Vertical +Through hole straight pin header, 1x06, 2.00mm pitch, single row +Through hole pin header THT 1x06 2.00mm single row +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_1x06_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x06, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x06 2.00mm single row style1 pin1 left +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_1x06_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x06, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x06 2.00mm single row style2 pin1 right +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_1x07_P2.00mm_Horizontal +Through hole angled pin header, 1x07, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x07 2.00mm single row +0 +7 +7 +Connector_PinHeader_2.00mm +PinHeader_1x07_P2.00mm_Vertical +Through hole straight pin header, 1x07, 2.00mm pitch, single row +Through hole pin header THT 1x07 2.00mm single row +0 +7 +7 +Connector_PinHeader_2.00mm +PinHeader_1x07_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x07, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x07 2.00mm single row style1 pin1 left +0 +7 +7 +Connector_PinHeader_2.00mm +PinHeader_1x07_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x07, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x07 2.00mm single row style2 pin1 right +0 +7 +7 +Connector_PinHeader_2.00mm +PinHeader_1x08_P2.00mm_Horizontal +Through hole angled pin header, 1x08, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x08 2.00mm single row +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_1x08_P2.00mm_Vertical +Through hole straight pin header, 1x08, 2.00mm pitch, single row +Through hole pin header THT 1x08 2.00mm single row +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_1x08_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x08, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x08 2.00mm single row style1 pin1 left +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_1x08_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x08, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x08 2.00mm single row style2 pin1 right +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_1x09_P2.00mm_Horizontal +Through hole angled pin header, 1x09, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x09 2.00mm single row +0 +9 +9 +Connector_PinHeader_2.00mm +PinHeader_1x09_P2.00mm_Vertical +Through hole straight pin header, 1x09, 2.00mm pitch, single row +Through hole pin header THT 1x09 2.00mm single row +0 +9 +9 +Connector_PinHeader_2.00mm +PinHeader_1x09_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x09, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x09 2.00mm single row style1 pin1 left +0 +9 +9 +Connector_PinHeader_2.00mm +PinHeader_1x09_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x09, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x09 2.00mm single row style2 pin1 right +0 +9 +9 +Connector_PinHeader_2.00mm +PinHeader_1x10_P2.00mm_Horizontal +Through hole angled pin header, 1x10, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x10 2.00mm single row +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_1x10_P2.00mm_Vertical +Through hole straight pin header, 1x10, 2.00mm pitch, single row +Through hole pin header THT 1x10 2.00mm single row +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_1x10_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x10, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x10 2.00mm single row style1 pin1 left +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_1x10_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x10, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x10 2.00mm single row style2 pin1 right +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_1x11_P2.00mm_Horizontal +Through hole angled pin header, 1x11, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x11 2.00mm single row +0 +11 +11 +Connector_PinHeader_2.00mm +PinHeader_1x11_P2.00mm_Vertical +Through hole straight pin header, 1x11, 2.00mm pitch, single row +Through hole pin header THT 1x11 2.00mm single row +0 +11 +11 +Connector_PinHeader_2.00mm +PinHeader_1x11_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x11, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x11 2.00mm single row style1 pin1 left +0 +11 +11 +Connector_PinHeader_2.00mm +PinHeader_1x11_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x11, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x11 2.00mm single row style2 pin1 right +0 +11 +11 +Connector_PinHeader_2.00mm +PinHeader_1x12_P2.00mm_Horizontal +Through hole angled pin header, 1x12, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x12 2.00mm single row +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_1x12_P2.00mm_Vertical +Through hole straight pin header, 1x12, 2.00mm pitch, single row +Through hole pin header THT 1x12 2.00mm single row +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_1x12_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x12, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x12 2.00mm single row style1 pin1 left +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_1x12_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x12, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x12 2.00mm single row style2 pin1 right +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_1x13_P2.00mm_Horizontal +Through hole angled pin header, 1x13, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x13 2.00mm single row +0 +13 +13 +Connector_PinHeader_2.00mm +PinHeader_1x13_P2.00mm_Vertical +Through hole straight pin header, 1x13, 2.00mm pitch, single row +Through hole pin header THT 1x13 2.00mm single row +0 +13 +13 +Connector_PinHeader_2.00mm +PinHeader_1x13_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x13, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x13 2.00mm single row style1 pin1 left +0 +13 +13 +Connector_PinHeader_2.00mm +PinHeader_1x13_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x13, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x13 2.00mm single row style2 pin1 right +0 +13 +13 +Connector_PinHeader_2.00mm +PinHeader_1x14_P2.00mm_Horizontal +Through hole angled pin header, 1x14, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x14 2.00mm single row +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_1x14_P2.00mm_Vertical +Through hole straight pin header, 1x14, 2.00mm pitch, single row +Through hole pin header THT 1x14 2.00mm single row +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_1x14_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x14, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x14 2.00mm single row style1 pin1 left +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_1x14_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x14, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x14 2.00mm single row style2 pin1 right +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_1x15_P2.00mm_Horizontal +Through hole angled pin header, 1x15, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x15 2.00mm single row +0 +15 +15 +Connector_PinHeader_2.00mm +PinHeader_1x15_P2.00mm_Vertical +Through hole straight pin header, 1x15, 2.00mm pitch, single row +Through hole pin header THT 1x15 2.00mm single row +0 +15 +15 +Connector_PinHeader_2.00mm +PinHeader_1x15_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x15, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x15 2.00mm single row style1 pin1 left +0 +15 +15 +Connector_PinHeader_2.00mm +PinHeader_1x15_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x15, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x15 2.00mm single row style2 pin1 right +0 +15 +15 +Connector_PinHeader_2.00mm +PinHeader_1x16_P2.00mm_Horizontal +Through hole angled pin header, 1x16, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x16 2.00mm single row +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_1x16_P2.00mm_Vertical +Through hole straight pin header, 1x16, 2.00mm pitch, single row +Through hole pin header THT 1x16 2.00mm single row +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_1x16_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x16, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x16 2.00mm single row style1 pin1 left +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_1x16_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x16, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x16 2.00mm single row style2 pin1 right +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_1x17_P2.00mm_Horizontal +Through hole angled pin header, 1x17, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x17 2.00mm single row +0 +17 +17 +Connector_PinHeader_2.00mm +PinHeader_1x17_P2.00mm_Vertical +Through hole straight pin header, 1x17, 2.00mm pitch, single row +Through hole pin header THT 1x17 2.00mm single row +0 +17 +17 +Connector_PinHeader_2.00mm +PinHeader_1x17_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x17, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x17 2.00mm single row style1 pin1 left +0 +17 +17 +Connector_PinHeader_2.00mm +PinHeader_1x17_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x17, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x17 2.00mm single row style2 pin1 right +0 +17 +17 +Connector_PinHeader_2.00mm +PinHeader_1x18_P2.00mm_Horizontal +Through hole angled pin header, 1x18, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x18 2.00mm single row +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_1x18_P2.00mm_Vertical +Through hole straight pin header, 1x18, 2.00mm pitch, single row +Through hole pin header THT 1x18 2.00mm single row +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_1x18_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x18, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x18 2.00mm single row style1 pin1 left +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_1x18_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x18, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x18 2.00mm single row style2 pin1 right +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_1x19_P2.00mm_Horizontal +Through hole angled pin header, 1x19, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x19 2.00mm single row +0 +19 +19 +Connector_PinHeader_2.00mm +PinHeader_1x19_P2.00mm_Vertical +Through hole straight pin header, 1x19, 2.00mm pitch, single row +Through hole pin header THT 1x19 2.00mm single row +0 +19 +19 +Connector_PinHeader_2.00mm +PinHeader_1x19_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x19, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x19 2.00mm single row style1 pin1 left +0 +19 +19 +Connector_PinHeader_2.00mm +PinHeader_1x19_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x19, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x19 2.00mm single row style2 pin1 right +0 +19 +19 +Connector_PinHeader_2.00mm +PinHeader_1x20_P2.00mm_Horizontal +Through hole angled pin header, 1x20, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x20 2.00mm single row +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_1x20_P2.00mm_Vertical +Through hole straight pin header, 1x20, 2.00mm pitch, single row +Through hole pin header THT 1x20 2.00mm single row +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_1x20_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x20, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x20 2.00mm single row style1 pin1 left +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_1x20_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x20, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x20 2.00mm single row style2 pin1 right +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_1x21_P2.00mm_Horizontal +Through hole angled pin header, 1x21, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x21 2.00mm single row +0 +21 +21 +Connector_PinHeader_2.00mm +PinHeader_1x21_P2.00mm_Vertical +Through hole straight pin header, 1x21, 2.00mm pitch, single row +Through hole pin header THT 1x21 2.00mm single row +0 +21 +21 +Connector_PinHeader_2.00mm +PinHeader_1x21_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x21, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x21 2.00mm single row style1 pin1 left +0 +21 +21 +Connector_PinHeader_2.00mm +PinHeader_1x21_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x21, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x21 2.00mm single row style2 pin1 right +0 +21 +21 +Connector_PinHeader_2.00mm +PinHeader_1x22_P2.00mm_Horizontal +Through hole angled pin header, 1x22, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x22 2.00mm single row +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_1x22_P2.00mm_Vertical +Through hole straight pin header, 1x22, 2.00mm pitch, single row +Through hole pin header THT 1x22 2.00mm single row +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_1x22_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x22, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x22 2.00mm single row style1 pin1 left +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_1x22_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x22, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x22 2.00mm single row style2 pin1 right +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_1x23_P2.00mm_Horizontal +Through hole angled pin header, 1x23, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x23 2.00mm single row +0 +23 +23 +Connector_PinHeader_2.00mm +PinHeader_1x23_P2.00mm_Vertical +Through hole straight pin header, 1x23, 2.00mm pitch, single row +Through hole pin header THT 1x23 2.00mm single row +0 +23 +23 +Connector_PinHeader_2.00mm +PinHeader_1x23_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x23, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x23 2.00mm single row style1 pin1 left +0 +23 +23 +Connector_PinHeader_2.00mm +PinHeader_1x23_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x23, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x23 2.00mm single row style2 pin1 right +0 +23 +23 +Connector_PinHeader_2.00mm +PinHeader_1x24_P2.00mm_Horizontal +Through hole angled pin header, 1x24, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x24 2.00mm single row +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_1x24_P2.00mm_Vertical +Through hole straight pin header, 1x24, 2.00mm pitch, single row +Through hole pin header THT 1x24 2.00mm single row +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_1x24_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x24, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x24 2.00mm single row style1 pin1 left +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_1x24_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x24, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x24 2.00mm single row style2 pin1 right +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_1x25_P2.00mm_Horizontal +Through hole angled pin header, 1x25, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x25 2.00mm single row +0 +25 +25 +Connector_PinHeader_2.00mm +PinHeader_1x25_P2.00mm_Vertical +Through hole straight pin header, 1x25, 2.00mm pitch, single row +Through hole pin header THT 1x25 2.00mm single row +0 +25 +25 +Connector_PinHeader_2.00mm +PinHeader_1x25_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x25, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x25 2.00mm single row style1 pin1 left +0 +25 +25 +Connector_PinHeader_2.00mm +PinHeader_1x25_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x25, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x25 2.00mm single row style2 pin1 right +0 +25 +25 +Connector_PinHeader_2.00mm +PinHeader_1x26_P2.00mm_Horizontal +Through hole angled pin header, 1x26, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x26 2.00mm single row +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_1x26_P2.00mm_Vertical +Through hole straight pin header, 1x26, 2.00mm pitch, single row +Through hole pin header THT 1x26 2.00mm single row +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_1x26_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x26, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x26 2.00mm single row style1 pin1 left +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_1x26_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x26, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x26 2.00mm single row style2 pin1 right +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_1x27_P2.00mm_Horizontal +Through hole angled pin header, 1x27, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x27 2.00mm single row +0 +27 +27 +Connector_PinHeader_2.00mm +PinHeader_1x27_P2.00mm_Vertical +Through hole straight pin header, 1x27, 2.00mm pitch, single row +Through hole pin header THT 1x27 2.00mm single row +0 +27 +27 +Connector_PinHeader_2.00mm +PinHeader_1x27_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x27, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x27 2.00mm single row style1 pin1 left +0 +27 +27 +Connector_PinHeader_2.00mm +PinHeader_1x27_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x27, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x27 2.00mm single row style2 pin1 right +0 +27 +27 +Connector_PinHeader_2.00mm +PinHeader_1x28_P2.00mm_Horizontal +Through hole angled pin header, 1x28, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x28 2.00mm single row +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_1x28_P2.00mm_Vertical +Through hole straight pin header, 1x28, 2.00mm pitch, single row +Through hole pin header THT 1x28 2.00mm single row +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_1x28_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x28, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x28 2.00mm single row style1 pin1 left +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_1x28_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x28, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x28 2.00mm single row style2 pin1 right +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_1x29_P2.00mm_Horizontal +Through hole angled pin header, 1x29, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x29 2.00mm single row +0 +29 +29 +Connector_PinHeader_2.00mm +PinHeader_1x29_P2.00mm_Vertical +Through hole straight pin header, 1x29, 2.00mm pitch, single row +Through hole pin header THT 1x29 2.00mm single row +0 +29 +29 +Connector_PinHeader_2.00mm +PinHeader_1x29_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x29, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x29 2.00mm single row style1 pin1 left +0 +29 +29 +Connector_PinHeader_2.00mm +PinHeader_1x29_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x29, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x29 2.00mm single row style2 pin1 right +0 +29 +29 +Connector_PinHeader_2.00mm +PinHeader_1x30_P2.00mm_Horizontal +Through hole angled pin header, 1x30, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x30 2.00mm single row +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_1x30_P2.00mm_Vertical +Through hole straight pin header, 1x30, 2.00mm pitch, single row +Through hole pin header THT 1x30 2.00mm single row +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_1x30_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x30, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x30 2.00mm single row style1 pin1 left +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_1x30_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x30, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x30 2.00mm single row style2 pin1 right +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_1x31_P2.00mm_Horizontal +Through hole angled pin header, 1x31, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x31 2.00mm single row +0 +31 +31 +Connector_PinHeader_2.00mm +PinHeader_1x31_P2.00mm_Vertical +Through hole straight pin header, 1x31, 2.00mm pitch, single row +Through hole pin header THT 1x31 2.00mm single row +0 +31 +31 +Connector_PinHeader_2.00mm +PinHeader_1x31_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x31, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x31 2.00mm single row style1 pin1 left +0 +31 +31 +Connector_PinHeader_2.00mm +PinHeader_1x31_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x31, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x31 2.00mm single row style2 pin1 right +0 +31 +31 +Connector_PinHeader_2.00mm +PinHeader_1x32_P2.00mm_Horizontal +Through hole angled pin header, 1x32, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x32 2.00mm single row +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_1x32_P2.00mm_Vertical +Through hole straight pin header, 1x32, 2.00mm pitch, single row +Through hole pin header THT 1x32 2.00mm single row +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_1x32_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x32, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x32 2.00mm single row style1 pin1 left +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_1x32_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x32, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x32 2.00mm single row style2 pin1 right +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_1x33_P2.00mm_Horizontal +Through hole angled pin header, 1x33, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x33 2.00mm single row +0 +33 +33 +Connector_PinHeader_2.00mm +PinHeader_1x33_P2.00mm_Vertical +Through hole straight pin header, 1x33, 2.00mm pitch, single row +Through hole pin header THT 1x33 2.00mm single row +0 +33 +33 +Connector_PinHeader_2.00mm +PinHeader_1x33_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x33, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x33 2.00mm single row style1 pin1 left +0 +33 +33 +Connector_PinHeader_2.00mm +PinHeader_1x33_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x33, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x33 2.00mm single row style2 pin1 right +0 +33 +33 +Connector_PinHeader_2.00mm +PinHeader_1x34_P2.00mm_Horizontal +Through hole angled pin header, 1x34, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x34 2.00mm single row +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_1x34_P2.00mm_Vertical +Through hole straight pin header, 1x34, 2.00mm pitch, single row +Through hole pin header THT 1x34 2.00mm single row +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_1x34_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x34, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x34 2.00mm single row style1 pin1 left +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_1x34_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x34, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x34 2.00mm single row style2 pin1 right +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_1x35_P2.00mm_Horizontal +Through hole angled pin header, 1x35, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x35 2.00mm single row +0 +35 +35 +Connector_PinHeader_2.00mm +PinHeader_1x35_P2.00mm_Vertical +Through hole straight pin header, 1x35, 2.00mm pitch, single row +Through hole pin header THT 1x35 2.00mm single row +0 +35 +35 +Connector_PinHeader_2.00mm +PinHeader_1x35_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x35, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x35 2.00mm single row style1 pin1 left +0 +35 +35 +Connector_PinHeader_2.00mm +PinHeader_1x35_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x35, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x35 2.00mm single row style2 pin1 right +0 +35 +35 +Connector_PinHeader_2.00mm +PinHeader_1x36_P2.00mm_Horizontal +Through hole angled pin header, 1x36, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x36 2.00mm single row +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_1x36_P2.00mm_Vertical +Through hole straight pin header, 1x36, 2.00mm pitch, single row +Through hole pin header THT 1x36 2.00mm single row +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_1x36_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x36, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x36 2.00mm single row style1 pin1 left +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_1x36_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x36, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x36 2.00mm single row style2 pin1 right +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_1x37_P2.00mm_Horizontal +Through hole angled pin header, 1x37, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x37 2.00mm single row +0 +37 +37 +Connector_PinHeader_2.00mm +PinHeader_1x37_P2.00mm_Vertical +Through hole straight pin header, 1x37, 2.00mm pitch, single row +Through hole pin header THT 1x37 2.00mm single row +0 +37 +37 +Connector_PinHeader_2.00mm +PinHeader_1x37_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x37, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x37 2.00mm single row style1 pin1 left +0 +37 +37 +Connector_PinHeader_2.00mm +PinHeader_1x37_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x37, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x37 2.00mm single row style2 pin1 right +0 +37 +37 +Connector_PinHeader_2.00mm +PinHeader_1x38_P2.00mm_Horizontal +Through hole angled pin header, 1x38, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x38 2.00mm single row +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_1x38_P2.00mm_Vertical +Through hole straight pin header, 1x38, 2.00mm pitch, single row +Through hole pin header THT 1x38 2.00mm single row +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_1x38_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x38, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x38 2.00mm single row style1 pin1 left +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_1x38_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x38, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x38 2.00mm single row style2 pin1 right +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_1x39_P2.00mm_Horizontal +Through hole angled pin header, 1x39, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x39 2.00mm single row +0 +39 +39 +Connector_PinHeader_2.00mm +PinHeader_1x39_P2.00mm_Vertical +Through hole straight pin header, 1x39, 2.00mm pitch, single row +Through hole pin header THT 1x39 2.00mm single row +0 +39 +39 +Connector_PinHeader_2.00mm +PinHeader_1x39_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x39, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x39 2.00mm single row style1 pin1 left +0 +39 +39 +Connector_PinHeader_2.00mm +PinHeader_1x39_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x39, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x39 2.00mm single row style2 pin1 right +0 +39 +39 +Connector_PinHeader_2.00mm +PinHeader_1x40_P2.00mm_Horizontal +Through hole angled pin header, 1x40, 2.00mm pitch, 4.2mm pin length, single row +Through hole angled pin header THT 1x40 2.00mm single row +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_1x40_P2.00mm_Vertical +Through hole straight pin header, 1x40, 2.00mm pitch, single row +Through hole pin header THT 1x40 2.00mm single row +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_1x40_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x40, 2.00mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x40 2.00mm single row style1 pin1 left +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_1x40_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x40, 2.00mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x40 2.00mm single row style2 pin1 right +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_2x01_P2.00mm_Horizontal +Through hole angled pin header, 2x01, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x01 2.00mm double row +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_2x01_P2.00mm_Vertical +Through hole straight pin header, 2x01, 2.00mm pitch, double rows +Through hole pin header THT 2x01 2.00mm double row +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_2x01_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x01, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x01 2.00mm double row +0 +2 +2 +Connector_PinHeader_2.00mm +PinHeader_2x02_P2.00mm_Horizontal +Through hole angled pin header, 2x02, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x02 2.00mm double row +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_2x02_P2.00mm_Vertical +Through hole straight pin header, 2x02, 2.00mm pitch, double rows +Through hole pin header THT 2x02 2.00mm double row +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_2x02_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x02, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x02 2.00mm double row +0 +4 +4 +Connector_PinHeader_2.00mm +PinHeader_2x03_P2.00mm_Horizontal +Through hole angled pin header, 2x03, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x03 2.00mm double row +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_2x03_P2.00mm_Vertical +Through hole straight pin header, 2x03, 2.00mm pitch, double rows +Through hole pin header THT 2x03 2.00mm double row +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_2x03_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x03, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x03 2.00mm double row +0 +6 +6 +Connector_PinHeader_2.00mm +PinHeader_2x04_P2.00mm_Horizontal +Through hole angled pin header, 2x04, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x04 2.00mm double row +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_2x04_P2.00mm_Vertical +Through hole straight pin header, 2x04, 2.00mm pitch, double rows +Through hole pin header THT 2x04 2.00mm double row +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_2x04_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x04, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x04 2.00mm double row +0 +8 +8 +Connector_PinHeader_2.00mm +PinHeader_2x05_P2.00mm_Horizontal +Through hole angled pin header, 2x05, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x05 2.00mm double row +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_2x05_P2.00mm_Vertical +Through hole straight pin header, 2x05, 2.00mm pitch, double rows +Through hole pin header THT 2x05 2.00mm double row +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_2x05_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x05, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x05 2.00mm double row +0 +10 +10 +Connector_PinHeader_2.00mm +PinHeader_2x06_P2.00mm_Horizontal +Through hole angled pin header, 2x06, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x06 2.00mm double row +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_2x06_P2.00mm_Vertical +Through hole straight pin header, 2x06, 2.00mm pitch, double rows +Through hole pin header THT 2x06 2.00mm double row +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_2x06_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x06, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x06 2.00mm double row +0 +12 +12 +Connector_PinHeader_2.00mm +PinHeader_2x07_P2.00mm_Horizontal +Through hole angled pin header, 2x07, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x07 2.00mm double row +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_2x07_P2.00mm_Vertical +Through hole straight pin header, 2x07, 2.00mm pitch, double rows +Through hole pin header THT 2x07 2.00mm double row +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_2x07_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x07, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x07 2.00mm double row +0 +14 +14 +Connector_PinHeader_2.00mm +PinHeader_2x08_P2.00mm_Horizontal +Through hole angled pin header, 2x08, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x08 2.00mm double row +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_2x08_P2.00mm_Vertical +Through hole straight pin header, 2x08, 2.00mm pitch, double rows +Through hole pin header THT 2x08 2.00mm double row +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_2x08_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x08, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x08 2.00mm double row +0 +16 +16 +Connector_PinHeader_2.00mm +PinHeader_2x09_P2.00mm_Horizontal +Through hole angled pin header, 2x09, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x09 2.00mm double row +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_2x09_P2.00mm_Vertical +Through hole straight pin header, 2x09, 2.00mm pitch, double rows +Through hole pin header THT 2x09 2.00mm double row +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_2x09_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x09, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x09 2.00mm double row +0 +18 +18 +Connector_PinHeader_2.00mm +PinHeader_2x10_P2.00mm_Horizontal +Through hole angled pin header, 2x10, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x10 2.00mm double row +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_2x10_P2.00mm_Vertical +Through hole straight pin header, 2x10, 2.00mm pitch, double rows +Through hole pin header THT 2x10 2.00mm double row +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_2x10_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x10, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x10 2.00mm double row +0 +20 +20 +Connector_PinHeader_2.00mm +PinHeader_2x11_P2.00mm_Horizontal +Through hole angled pin header, 2x11, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x11 2.00mm double row +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_2x11_P2.00mm_Vertical +Through hole straight pin header, 2x11, 2.00mm pitch, double rows +Through hole pin header THT 2x11 2.00mm double row +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_2x11_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x11, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x11 2.00mm double row +0 +22 +22 +Connector_PinHeader_2.00mm +PinHeader_2x12_P2.00mm_Horizontal +Through hole angled pin header, 2x12, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x12 2.00mm double row +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_2x12_P2.00mm_Vertical +Through hole straight pin header, 2x12, 2.00mm pitch, double rows +Through hole pin header THT 2x12 2.00mm double row +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_2x12_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x12, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x12 2.00mm double row +0 +24 +24 +Connector_PinHeader_2.00mm +PinHeader_2x13_P2.00mm_Horizontal +Through hole angled pin header, 2x13, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x13 2.00mm double row +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_2x13_P2.00mm_Vertical +Through hole straight pin header, 2x13, 2.00mm pitch, double rows +Through hole pin header THT 2x13 2.00mm double row +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_2x13_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x13, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x13 2.00mm double row +0 +26 +26 +Connector_PinHeader_2.00mm +PinHeader_2x14_P2.00mm_Horizontal +Through hole angled pin header, 2x14, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x14 2.00mm double row +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_2x14_P2.00mm_Vertical +Through hole straight pin header, 2x14, 2.00mm pitch, double rows +Through hole pin header THT 2x14 2.00mm double row +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_2x14_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x14, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x14 2.00mm double row +0 +28 +28 +Connector_PinHeader_2.00mm +PinHeader_2x15_P2.00mm_Horizontal +Through hole angled pin header, 2x15, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x15 2.00mm double row +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_2x15_P2.00mm_Vertical +Through hole straight pin header, 2x15, 2.00mm pitch, double rows +Through hole pin header THT 2x15 2.00mm double row +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_2x15_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x15, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x15 2.00mm double row +0 +30 +30 +Connector_PinHeader_2.00mm +PinHeader_2x16_P2.00mm_Horizontal +Through hole angled pin header, 2x16, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x16 2.00mm double row +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_2x16_P2.00mm_Vertical +Through hole straight pin header, 2x16, 2.00mm pitch, double rows +Through hole pin header THT 2x16 2.00mm double row +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_2x16_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x16, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x16 2.00mm double row +0 +32 +32 +Connector_PinHeader_2.00mm +PinHeader_2x17_P2.00mm_Horizontal +Through hole angled pin header, 2x17, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x17 2.00mm double row +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_2x17_P2.00mm_Vertical +Through hole straight pin header, 2x17, 2.00mm pitch, double rows +Through hole pin header THT 2x17 2.00mm double row +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_2x17_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x17, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x17 2.00mm double row +0 +34 +34 +Connector_PinHeader_2.00mm +PinHeader_2x18_P2.00mm_Horizontal +Through hole angled pin header, 2x18, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x18 2.00mm double row +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_2x18_P2.00mm_Vertical +Through hole straight pin header, 2x18, 2.00mm pitch, double rows +Through hole pin header THT 2x18 2.00mm double row +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_2x18_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x18, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x18 2.00mm double row +0 +36 +36 +Connector_PinHeader_2.00mm +PinHeader_2x19_P2.00mm_Horizontal +Through hole angled pin header, 2x19, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x19 2.00mm double row +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_2x19_P2.00mm_Vertical +Through hole straight pin header, 2x19, 2.00mm pitch, double rows +Through hole pin header THT 2x19 2.00mm double row +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_2x19_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x19, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x19 2.00mm double row +0 +38 +38 +Connector_PinHeader_2.00mm +PinHeader_2x20_P2.00mm_Horizontal +Through hole angled pin header, 2x20, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x20 2.00mm double row +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_2x20_P2.00mm_Vertical +Through hole straight pin header, 2x20, 2.00mm pitch, double rows +Through hole pin header THT 2x20 2.00mm double row +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_2x20_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x20, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x20 2.00mm double row +0 +40 +40 +Connector_PinHeader_2.00mm +PinHeader_2x21_P2.00mm_Horizontal +Through hole angled pin header, 2x21, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x21 2.00mm double row +0 +42 +42 +Connector_PinHeader_2.00mm +PinHeader_2x21_P2.00mm_Vertical +Through hole straight pin header, 2x21, 2.00mm pitch, double rows +Through hole pin header THT 2x21 2.00mm double row +0 +42 +42 +Connector_PinHeader_2.00mm +PinHeader_2x21_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x21, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x21 2.00mm double row +0 +42 +42 +Connector_PinHeader_2.00mm +PinHeader_2x22_P2.00mm_Horizontal +Through hole angled pin header, 2x22, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x22 2.00mm double row +0 +44 +44 +Connector_PinHeader_2.00mm +PinHeader_2x22_P2.00mm_Vertical +Through hole straight pin header, 2x22, 2.00mm pitch, double rows +Through hole pin header THT 2x22 2.00mm double row +0 +44 +44 +Connector_PinHeader_2.00mm +PinHeader_2x22_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x22, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x22 2.00mm double row +0 +44 +44 +Connector_PinHeader_2.00mm +PinHeader_2x23_P2.00mm_Horizontal +Through hole angled pin header, 2x23, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x23 2.00mm double row +0 +46 +46 +Connector_PinHeader_2.00mm +PinHeader_2x23_P2.00mm_Vertical +Through hole straight pin header, 2x23, 2.00mm pitch, double rows +Through hole pin header THT 2x23 2.00mm double row +0 +46 +46 +Connector_PinHeader_2.00mm +PinHeader_2x23_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x23, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x23 2.00mm double row +0 +46 +46 +Connector_PinHeader_2.00mm +PinHeader_2x24_P2.00mm_Horizontal +Through hole angled pin header, 2x24, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x24 2.00mm double row +0 +48 +48 +Connector_PinHeader_2.00mm +PinHeader_2x24_P2.00mm_Vertical +Through hole straight pin header, 2x24, 2.00mm pitch, double rows +Through hole pin header THT 2x24 2.00mm double row +0 +48 +48 +Connector_PinHeader_2.00mm +PinHeader_2x24_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x24, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x24 2.00mm double row +0 +48 +48 +Connector_PinHeader_2.00mm +PinHeader_2x25_P2.00mm_Horizontal +Through hole angled pin header, 2x25, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x25 2.00mm double row +0 +50 +50 +Connector_PinHeader_2.00mm +PinHeader_2x25_P2.00mm_Vertical +Through hole straight pin header, 2x25, 2.00mm pitch, double rows +Through hole pin header THT 2x25 2.00mm double row +0 +50 +50 +Connector_PinHeader_2.00mm +PinHeader_2x25_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x25, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x25 2.00mm double row +0 +50 +50 +Connector_PinHeader_2.00mm +PinHeader_2x26_P2.00mm_Horizontal +Through hole angled pin header, 2x26, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x26 2.00mm double row +0 +52 +52 +Connector_PinHeader_2.00mm +PinHeader_2x26_P2.00mm_Vertical +Through hole straight pin header, 2x26, 2.00mm pitch, double rows +Through hole pin header THT 2x26 2.00mm double row +0 +52 +52 +Connector_PinHeader_2.00mm +PinHeader_2x26_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x26, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x26 2.00mm double row +0 +52 +52 +Connector_PinHeader_2.00mm +PinHeader_2x27_P2.00mm_Horizontal +Through hole angled pin header, 2x27, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x27 2.00mm double row +0 +54 +54 +Connector_PinHeader_2.00mm +PinHeader_2x27_P2.00mm_Vertical +Through hole straight pin header, 2x27, 2.00mm pitch, double rows +Through hole pin header THT 2x27 2.00mm double row +0 +54 +54 +Connector_PinHeader_2.00mm +PinHeader_2x27_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x27, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x27 2.00mm double row +0 +54 +54 +Connector_PinHeader_2.00mm +PinHeader_2x28_P2.00mm_Horizontal +Through hole angled pin header, 2x28, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x28 2.00mm double row +0 +56 +56 +Connector_PinHeader_2.00mm +PinHeader_2x28_P2.00mm_Vertical +Through hole straight pin header, 2x28, 2.00mm pitch, double rows +Through hole pin header THT 2x28 2.00mm double row +0 +56 +56 +Connector_PinHeader_2.00mm +PinHeader_2x28_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x28, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x28 2.00mm double row +0 +56 +56 +Connector_PinHeader_2.00mm +PinHeader_2x29_P2.00mm_Horizontal +Through hole angled pin header, 2x29, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x29 2.00mm double row +0 +58 +58 +Connector_PinHeader_2.00mm +PinHeader_2x29_P2.00mm_Vertical +Through hole straight pin header, 2x29, 2.00mm pitch, double rows +Through hole pin header THT 2x29 2.00mm double row +0 +58 +58 +Connector_PinHeader_2.00mm +PinHeader_2x29_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x29, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x29 2.00mm double row +0 +58 +58 +Connector_PinHeader_2.00mm +PinHeader_2x30_P2.00mm_Horizontal +Through hole angled pin header, 2x30, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x30 2.00mm double row +0 +60 +60 +Connector_PinHeader_2.00mm +PinHeader_2x30_P2.00mm_Vertical +Through hole straight pin header, 2x30, 2.00mm pitch, double rows +Through hole pin header THT 2x30 2.00mm double row +0 +60 +60 +Connector_PinHeader_2.00mm +PinHeader_2x30_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x30, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x30 2.00mm double row +0 +60 +60 +Connector_PinHeader_2.00mm +PinHeader_2x31_P2.00mm_Horizontal +Through hole angled pin header, 2x31, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x31 2.00mm double row +0 +62 +62 +Connector_PinHeader_2.00mm +PinHeader_2x31_P2.00mm_Vertical +Through hole straight pin header, 2x31, 2.00mm pitch, double rows +Through hole pin header THT 2x31 2.00mm double row +0 +62 +62 +Connector_PinHeader_2.00mm +PinHeader_2x31_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x31, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x31 2.00mm double row +0 +62 +62 +Connector_PinHeader_2.00mm +PinHeader_2x32_P2.00mm_Horizontal +Through hole angled pin header, 2x32, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x32 2.00mm double row +0 +64 +64 +Connector_PinHeader_2.00mm +PinHeader_2x32_P2.00mm_Vertical +Through hole straight pin header, 2x32, 2.00mm pitch, double rows +Through hole pin header THT 2x32 2.00mm double row +0 +64 +64 +Connector_PinHeader_2.00mm +PinHeader_2x32_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x32, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x32 2.00mm double row +0 +64 +64 +Connector_PinHeader_2.00mm +PinHeader_2x33_P2.00mm_Horizontal +Through hole angled pin header, 2x33, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x33 2.00mm double row +0 +66 +66 +Connector_PinHeader_2.00mm +PinHeader_2x33_P2.00mm_Vertical +Through hole straight pin header, 2x33, 2.00mm pitch, double rows +Through hole pin header THT 2x33 2.00mm double row +0 +66 +66 +Connector_PinHeader_2.00mm +PinHeader_2x33_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x33, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x33 2.00mm double row +0 +66 +66 +Connector_PinHeader_2.00mm +PinHeader_2x34_P2.00mm_Horizontal +Through hole angled pin header, 2x34, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x34 2.00mm double row +0 +68 +68 +Connector_PinHeader_2.00mm +PinHeader_2x34_P2.00mm_Vertical +Through hole straight pin header, 2x34, 2.00mm pitch, double rows +Through hole pin header THT 2x34 2.00mm double row +0 +68 +68 +Connector_PinHeader_2.00mm +PinHeader_2x34_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x34, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x34 2.00mm double row +0 +68 +68 +Connector_PinHeader_2.00mm +PinHeader_2x35_P2.00mm_Horizontal +Through hole angled pin header, 2x35, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x35 2.00mm double row +0 +70 +70 +Connector_PinHeader_2.00mm +PinHeader_2x35_P2.00mm_Vertical +Through hole straight pin header, 2x35, 2.00mm pitch, double rows +Through hole pin header THT 2x35 2.00mm double row +0 +70 +70 +Connector_PinHeader_2.00mm +PinHeader_2x35_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x35, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x35 2.00mm double row +0 +70 +70 +Connector_PinHeader_2.00mm +PinHeader_2x36_P2.00mm_Horizontal +Through hole angled pin header, 2x36, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x36 2.00mm double row +0 +72 +72 +Connector_PinHeader_2.00mm +PinHeader_2x36_P2.00mm_Vertical +Through hole straight pin header, 2x36, 2.00mm pitch, double rows +Through hole pin header THT 2x36 2.00mm double row +0 +72 +72 +Connector_PinHeader_2.00mm +PinHeader_2x36_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x36, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x36 2.00mm double row +0 +72 +72 +Connector_PinHeader_2.00mm +PinHeader_2x37_P2.00mm_Horizontal +Through hole angled pin header, 2x37, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x37 2.00mm double row +0 +74 +74 +Connector_PinHeader_2.00mm +PinHeader_2x37_P2.00mm_Vertical +Through hole straight pin header, 2x37, 2.00mm pitch, double rows +Through hole pin header THT 2x37 2.00mm double row +0 +74 +74 +Connector_PinHeader_2.00mm +PinHeader_2x37_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x37, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x37 2.00mm double row +0 +74 +74 +Connector_PinHeader_2.00mm +PinHeader_2x38_P2.00mm_Horizontal +Through hole angled pin header, 2x38, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x38 2.00mm double row +0 +76 +76 +Connector_PinHeader_2.00mm +PinHeader_2x38_P2.00mm_Vertical +Through hole straight pin header, 2x38, 2.00mm pitch, double rows +Through hole pin header THT 2x38 2.00mm double row +0 +76 +76 +Connector_PinHeader_2.00mm +PinHeader_2x38_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x38, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x38 2.00mm double row +0 +76 +76 +Connector_PinHeader_2.00mm +PinHeader_2x39_P2.00mm_Horizontal +Through hole angled pin header, 2x39, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x39 2.00mm double row +0 +78 +78 +Connector_PinHeader_2.00mm +PinHeader_2x39_P2.00mm_Vertical +Through hole straight pin header, 2x39, 2.00mm pitch, double rows +Through hole pin header THT 2x39 2.00mm double row +0 +78 +78 +Connector_PinHeader_2.00mm +PinHeader_2x39_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x39, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x39 2.00mm double row +0 +78 +78 +Connector_PinHeader_2.00mm +PinHeader_2x40_P2.00mm_Horizontal +Through hole angled pin header, 2x40, 2.00mm pitch, 4.2mm pin length, double rows +Through hole angled pin header THT 2x40 2.00mm double row +0 +80 +80 +Connector_PinHeader_2.00mm +PinHeader_2x40_P2.00mm_Vertical +Through hole straight pin header, 2x40, 2.00mm pitch, double rows +Through hole pin header THT 2x40 2.00mm double row +0 +80 +80 +Connector_PinHeader_2.00mm +PinHeader_2x40_P2.00mm_Vertical_SMD +surface-mounted straight pin header, 2x40, 2.00mm pitch, double rows +Surface mounted pin header SMD 2x40 2.00mm double row +0 +80 +80 +Connector_PinHeader_2.54mm +PinHeader_1x01_P2.54mm_Horizontal +Through hole angled pin header, 1x01, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x01 2.54mm single row +0 +1 +1 +Connector_PinHeader_2.54mm +PinHeader_1x01_P2.54mm_Vertical +Through hole straight pin header, 1x01, 2.54mm pitch, single row +Through hole pin header THT 1x01 2.54mm single row +0 +1 +1 +Connector_PinHeader_2.54mm +PinHeader_1x02_P2.54mm_Horizontal +Through hole angled pin header, 1x02, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x02 2.54mm single row +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_1x02_P2.54mm_Vertical +Through hole straight pin header, 1x02, 2.54mm pitch, single row +Through hole pin header THT 1x02 2.54mm single row +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x02 2.54mm single row style1 pin1 left +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_1x02_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x02 2.54mm single row style2 pin1 right +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_1x03_P2.54mm_Horizontal +Through hole angled pin header, 1x03, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x03 2.54mm single row +0 +3 +3 +Connector_PinHeader_2.54mm +PinHeader_1x03_P2.54mm_Vertical +Through hole straight pin header, 1x03, 2.54mm pitch, single row +Through hole pin header THT 1x03 2.54mm single row +0 +3 +3 +Connector_PinHeader_2.54mm +PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left +0 +3 +3 +Connector_PinHeader_2.54mm +PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x03 2.54mm single row style2 pin1 right +0 +3 +3 +Connector_PinHeader_2.54mm +PinHeader_1x04_P2.54mm_Horizontal +Through hole angled pin header, 1x04, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x04 2.54mm single row +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_1x04_P2.54mm_Vertical +Through hole straight pin header, 1x04, 2.54mm pitch, single row +Through hole pin header THT 1x04 2.54mm single row +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x04 2.54mm single row style1 pin1 left +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x04 2.54mm single row style2 pin1 right +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_1x05_P2.54mm_Horizontal +Through hole angled pin header, 1x05, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x05 2.54mm single row +0 +5 +5 +Connector_PinHeader_2.54mm +PinHeader_1x05_P2.54mm_Vertical +Through hole straight pin header, 1x05, 2.54mm pitch, single row +Through hole pin header THT 1x05 2.54mm single row +0 +5 +5 +Connector_PinHeader_2.54mm +PinHeader_1x05_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x05 2.54mm single row style1 pin1 left +0 +5 +5 +Connector_PinHeader_2.54mm +PinHeader_1x05_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x05 2.54mm single row style2 pin1 right +0 +5 +5 +Connector_PinHeader_2.54mm +PinHeader_1x06_P2.54mm_Horizontal +Through hole angled pin header, 1x06, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x06 2.54mm single row +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_1x06_P2.54mm_Vertical +Through hole straight pin header, 1x06, 2.54mm pitch, single row +Through hole pin header THT 1x06 2.54mm single row +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x06 2.54mm single row style1 pin1 left +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_1x06_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x06 2.54mm single row style2 pin1 right +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_1x07_P2.54mm_Horizontal +Through hole angled pin header, 1x07, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x07 2.54mm single row +0 +7 +7 +Connector_PinHeader_2.54mm +PinHeader_1x07_P2.54mm_Vertical +Through hole straight pin header, 1x07, 2.54mm pitch, single row +Through hole pin header THT 1x07 2.54mm single row +0 +7 +7 +Connector_PinHeader_2.54mm +PinHeader_1x07_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x07 2.54mm single row style1 pin1 left +0 +7 +7 +Connector_PinHeader_2.54mm +PinHeader_1x07_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x07 2.54mm single row style2 pin1 right +0 +7 +7 +Connector_PinHeader_2.54mm +PinHeader_1x08_P2.54mm_Horizontal +Through hole angled pin header, 1x08, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x08 2.54mm single row +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_1x08_P2.54mm_Vertical +Through hole straight pin header, 1x08, 2.54mm pitch, single row +Through hole pin header THT 1x08 2.54mm single row +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_1x08_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x08 2.54mm single row style1 pin1 left +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_1x08_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x08 2.54mm single row style2 pin1 right +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_1x09_P2.54mm_Horizontal +Through hole angled pin header, 1x09, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x09 2.54mm single row +0 +9 +9 +Connector_PinHeader_2.54mm +PinHeader_1x09_P2.54mm_Vertical +Through hole straight pin header, 1x09, 2.54mm pitch, single row +Through hole pin header THT 1x09 2.54mm single row +0 +9 +9 +Connector_PinHeader_2.54mm +PinHeader_1x09_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x09 2.54mm single row style1 pin1 left +0 +9 +9 +Connector_PinHeader_2.54mm +PinHeader_1x09_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x09 2.54mm single row style2 pin1 right +0 +9 +9 +Connector_PinHeader_2.54mm +PinHeader_1x10_P2.54mm_Horizontal +Through hole angled pin header, 1x10, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x10 2.54mm single row +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_1x10_P2.54mm_Vertical +Through hole straight pin header, 1x10, 2.54mm pitch, single row +Through hole pin header THT 1x10 2.54mm single row +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_1x10_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x10 2.54mm single row style1 pin1 left +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_1x10_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x10 2.54mm single row style2 pin1 right +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_1x11_P2.54mm_Horizontal +Through hole angled pin header, 1x11, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x11 2.54mm single row +0 +11 +11 +Connector_PinHeader_2.54mm +PinHeader_1x11_P2.54mm_Vertical +Through hole straight pin header, 1x11, 2.54mm pitch, single row +Through hole pin header THT 1x11 2.54mm single row +0 +11 +11 +Connector_PinHeader_2.54mm +PinHeader_1x11_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x11 2.54mm single row style1 pin1 left +0 +11 +11 +Connector_PinHeader_2.54mm +PinHeader_1x11_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x11 2.54mm single row style2 pin1 right +0 +11 +11 +Connector_PinHeader_2.54mm +PinHeader_1x12_P2.54mm_Horizontal +Through hole angled pin header, 1x12, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x12 2.54mm single row +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_1x12_P2.54mm_Vertical +Through hole straight pin header, 1x12, 2.54mm pitch, single row +Through hole pin header THT 1x12 2.54mm single row +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_1x12_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x12 2.54mm single row style1 pin1 left +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_1x12_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x12 2.54mm single row style2 pin1 right +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_1x13_P2.54mm_Horizontal +Through hole angled pin header, 1x13, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x13 2.54mm single row +0 +13 +13 +Connector_PinHeader_2.54mm +PinHeader_1x13_P2.54mm_Vertical +Through hole straight pin header, 1x13, 2.54mm pitch, single row +Through hole pin header THT 1x13 2.54mm single row +0 +13 +13 +Connector_PinHeader_2.54mm +PinHeader_1x13_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x13 2.54mm single row style1 pin1 left +0 +13 +13 +Connector_PinHeader_2.54mm +PinHeader_1x13_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x13 2.54mm single row style2 pin1 right +0 +13 +13 +Connector_PinHeader_2.54mm +PinHeader_1x14_P2.54mm_Horizontal +Through hole angled pin header, 1x14, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x14 2.54mm single row +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_1x14_P2.54mm_Vertical +Through hole straight pin header, 1x14, 2.54mm pitch, single row +Through hole pin header THT 1x14 2.54mm single row +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_1x14_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x14 2.54mm single row style1 pin1 left +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_1x14_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x14 2.54mm single row style2 pin1 right +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_1x15_P2.54mm_Horizontal +Through hole angled pin header, 1x15, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x15 2.54mm single row +0 +15 +15 +Connector_PinHeader_2.54mm +PinHeader_1x15_P2.54mm_Vertical +Through hole straight pin header, 1x15, 2.54mm pitch, single row +Through hole pin header THT 1x15 2.54mm single row +0 +15 +15 +Connector_PinHeader_2.54mm +PinHeader_1x15_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x15 2.54mm single row style1 pin1 left +0 +15 +15 +Connector_PinHeader_2.54mm +PinHeader_1x15_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x15 2.54mm single row style2 pin1 right +0 +15 +15 +Connector_PinHeader_2.54mm +PinHeader_1x16_P2.54mm_Horizontal +Through hole angled pin header, 1x16, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x16 2.54mm single row +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_1x16_P2.54mm_Vertical +Through hole straight pin header, 1x16, 2.54mm pitch, single row +Through hole pin header THT 1x16 2.54mm single row +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_1x16_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x16 2.54mm single row style1 pin1 left +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_1x16_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x16 2.54mm single row style2 pin1 right +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_1x17_P2.54mm_Horizontal +Through hole angled pin header, 1x17, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x17 2.54mm single row +0 +17 +17 +Connector_PinHeader_2.54mm +PinHeader_1x17_P2.54mm_Vertical +Through hole straight pin header, 1x17, 2.54mm pitch, single row +Through hole pin header THT 1x17 2.54mm single row +0 +17 +17 +Connector_PinHeader_2.54mm +PinHeader_1x17_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x17 2.54mm single row style1 pin1 left +0 +17 +17 +Connector_PinHeader_2.54mm +PinHeader_1x17_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x17 2.54mm single row style2 pin1 right +0 +17 +17 +Connector_PinHeader_2.54mm +PinHeader_1x18_P2.54mm_Horizontal +Through hole angled pin header, 1x18, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x18 2.54mm single row +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_1x18_P2.54mm_Vertical +Through hole straight pin header, 1x18, 2.54mm pitch, single row +Through hole pin header THT 1x18 2.54mm single row +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_1x18_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x18 2.54mm single row style1 pin1 left +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_1x18_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x18 2.54mm single row style2 pin1 right +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_1x19_P2.54mm_Horizontal +Through hole angled pin header, 1x19, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x19 2.54mm single row +0 +19 +19 +Connector_PinHeader_2.54mm +PinHeader_1x19_P2.54mm_Vertical +Through hole straight pin header, 1x19, 2.54mm pitch, single row +Through hole pin header THT 1x19 2.54mm single row +0 +19 +19 +Connector_PinHeader_2.54mm +PinHeader_1x19_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x19 2.54mm single row style1 pin1 left +0 +19 +19 +Connector_PinHeader_2.54mm +PinHeader_1x19_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x19 2.54mm single row style2 pin1 right +0 +19 +19 +Connector_PinHeader_2.54mm +PinHeader_1x20_P2.54mm_Horizontal +Through hole angled pin header, 1x20, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x20 2.54mm single row +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_1x20_P2.54mm_Vertical +Through hole straight pin header, 1x20, 2.54mm pitch, single row +Through hole pin header THT 1x20 2.54mm single row +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_1x20_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x20 2.54mm single row style1 pin1 left +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_1x20_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x20 2.54mm single row style2 pin1 right +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_1x21_P2.54mm_Horizontal +Through hole angled pin header, 1x21, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x21 2.54mm single row +0 +21 +21 +Connector_PinHeader_2.54mm +PinHeader_1x21_P2.54mm_Vertical +Through hole straight pin header, 1x21, 2.54mm pitch, single row +Through hole pin header THT 1x21 2.54mm single row +0 +21 +21 +Connector_PinHeader_2.54mm +PinHeader_1x21_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x21 2.54mm single row style1 pin1 left +0 +21 +21 +Connector_PinHeader_2.54mm +PinHeader_1x21_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x21 2.54mm single row style2 pin1 right +0 +21 +21 +Connector_PinHeader_2.54mm +PinHeader_1x22_P2.54mm_Horizontal +Through hole angled pin header, 1x22, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x22 2.54mm single row +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_1x22_P2.54mm_Vertical +Through hole straight pin header, 1x22, 2.54mm pitch, single row +Through hole pin header THT 1x22 2.54mm single row +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_1x22_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x22 2.54mm single row style1 pin1 left +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_1x22_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x22 2.54mm single row style2 pin1 right +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_1x23_P2.54mm_Horizontal +Through hole angled pin header, 1x23, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x23 2.54mm single row +0 +23 +23 +Connector_PinHeader_2.54mm +PinHeader_1x23_P2.54mm_Vertical +Through hole straight pin header, 1x23, 2.54mm pitch, single row +Through hole pin header THT 1x23 2.54mm single row +0 +23 +23 +Connector_PinHeader_2.54mm +PinHeader_1x23_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x23 2.54mm single row style1 pin1 left +0 +23 +23 +Connector_PinHeader_2.54mm +PinHeader_1x23_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x23 2.54mm single row style2 pin1 right +0 +23 +23 +Connector_PinHeader_2.54mm +PinHeader_1x24_P2.54mm_Horizontal +Through hole angled pin header, 1x24, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x24 2.54mm single row +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_1x24_P2.54mm_Vertical +Through hole straight pin header, 1x24, 2.54mm pitch, single row +Through hole pin header THT 1x24 2.54mm single row +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_1x24_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x24 2.54mm single row style1 pin1 left +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_1x24_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x24 2.54mm single row style2 pin1 right +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_1x25_P2.54mm_Horizontal +Through hole angled pin header, 1x25, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x25 2.54mm single row +0 +25 +25 +Connector_PinHeader_2.54mm +PinHeader_1x25_P2.54mm_Vertical +Through hole straight pin header, 1x25, 2.54mm pitch, single row +Through hole pin header THT 1x25 2.54mm single row +0 +25 +25 +Connector_PinHeader_2.54mm +PinHeader_1x25_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x25 2.54mm single row style1 pin1 left +0 +25 +25 +Connector_PinHeader_2.54mm +PinHeader_1x25_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x25 2.54mm single row style2 pin1 right +0 +25 +25 +Connector_PinHeader_2.54mm +PinHeader_1x26_P2.54mm_Horizontal +Through hole angled pin header, 1x26, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x26 2.54mm single row +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_1x26_P2.54mm_Vertical +Through hole straight pin header, 1x26, 2.54mm pitch, single row +Through hole pin header THT 1x26 2.54mm single row +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_1x26_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x26 2.54mm single row style1 pin1 left +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_1x26_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x26 2.54mm single row style2 pin1 right +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_1x27_P2.54mm_Horizontal +Through hole angled pin header, 1x27, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x27 2.54mm single row +0 +27 +27 +Connector_PinHeader_2.54mm +PinHeader_1x27_P2.54mm_Vertical +Through hole straight pin header, 1x27, 2.54mm pitch, single row +Through hole pin header THT 1x27 2.54mm single row +0 +27 +27 +Connector_PinHeader_2.54mm +PinHeader_1x27_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x27 2.54mm single row style1 pin1 left +0 +27 +27 +Connector_PinHeader_2.54mm +PinHeader_1x27_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x27 2.54mm single row style2 pin1 right +0 +27 +27 +Connector_PinHeader_2.54mm +PinHeader_1x28_P2.54mm_Horizontal +Through hole angled pin header, 1x28, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x28 2.54mm single row +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_1x28_P2.54mm_Vertical +Through hole straight pin header, 1x28, 2.54mm pitch, single row +Through hole pin header THT 1x28 2.54mm single row +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_1x28_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x28 2.54mm single row style1 pin1 left +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_1x28_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x28 2.54mm single row style2 pin1 right +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_1x29_P2.54mm_Horizontal +Through hole angled pin header, 1x29, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x29 2.54mm single row +0 +29 +29 +Connector_PinHeader_2.54mm +PinHeader_1x29_P2.54mm_Vertical +Through hole straight pin header, 1x29, 2.54mm pitch, single row +Through hole pin header THT 1x29 2.54mm single row +0 +29 +29 +Connector_PinHeader_2.54mm +PinHeader_1x29_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x29 2.54mm single row style1 pin1 left +0 +29 +29 +Connector_PinHeader_2.54mm +PinHeader_1x29_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x29 2.54mm single row style2 pin1 right +0 +29 +29 +Connector_PinHeader_2.54mm +PinHeader_1x30_P2.54mm_Horizontal +Through hole angled pin header, 1x30, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x30 2.54mm single row +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_1x30_P2.54mm_Vertical +Through hole straight pin header, 1x30, 2.54mm pitch, single row +Through hole pin header THT 1x30 2.54mm single row +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_1x30_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x30 2.54mm single row style1 pin1 left +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_1x30_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x30 2.54mm single row style2 pin1 right +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_1x31_P2.54mm_Horizontal +Through hole angled pin header, 1x31, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x31 2.54mm single row +0 +31 +31 +Connector_PinHeader_2.54mm +PinHeader_1x31_P2.54mm_Vertical +Through hole straight pin header, 1x31, 2.54mm pitch, single row +Through hole pin header THT 1x31 2.54mm single row +0 +31 +31 +Connector_PinHeader_2.54mm +PinHeader_1x31_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x31 2.54mm single row style1 pin1 left +0 +31 +31 +Connector_PinHeader_2.54mm +PinHeader_1x31_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x31 2.54mm single row style2 pin1 right +0 +31 +31 +Connector_PinHeader_2.54mm +PinHeader_1x32_P2.54mm_Horizontal +Through hole angled pin header, 1x32, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x32 2.54mm single row +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_1x32_P2.54mm_Vertical +Through hole straight pin header, 1x32, 2.54mm pitch, single row +Through hole pin header THT 1x32 2.54mm single row +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_1x32_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x32 2.54mm single row style1 pin1 left +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_1x32_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x32 2.54mm single row style2 pin1 right +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_1x33_P2.54mm_Horizontal +Through hole angled pin header, 1x33, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x33 2.54mm single row +0 +33 +33 +Connector_PinHeader_2.54mm +PinHeader_1x33_P2.54mm_Vertical +Through hole straight pin header, 1x33, 2.54mm pitch, single row +Through hole pin header THT 1x33 2.54mm single row +0 +33 +33 +Connector_PinHeader_2.54mm +PinHeader_1x33_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x33 2.54mm single row style1 pin1 left +0 +33 +33 +Connector_PinHeader_2.54mm +PinHeader_1x33_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x33 2.54mm single row style2 pin1 right +0 +33 +33 +Connector_PinHeader_2.54mm +PinHeader_1x34_P2.54mm_Horizontal +Through hole angled pin header, 1x34, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x34 2.54mm single row +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_1x34_P2.54mm_Vertical +Through hole straight pin header, 1x34, 2.54mm pitch, single row +Through hole pin header THT 1x34 2.54mm single row +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_1x34_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x34 2.54mm single row style1 pin1 left +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_1x34_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x34 2.54mm single row style2 pin1 right +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_1x35_P2.54mm_Horizontal +Through hole angled pin header, 1x35, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x35 2.54mm single row +0 +35 +35 +Connector_PinHeader_2.54mm +PinHeader_1x35_P2.54mm_Vertical +Through hole straight pin header, 1x35, 2.54mm pitch, single row +Through hole pin header THT 1x35 2.54mm single row +0 +35 +35 +Connector_PinHeader_2.54mm +PinHeader_1x35_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x35 2.54mm single row style1 pin1 left +0 +35 +35 +Connector_PinHeader_2.54mm +PinHeader_1x35_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x35 2.54mm single row style2 pin1 right +0 +35 +35 +Connector_PinHeader_2.54mm +PinHeader_1x36_P2.54mm_Horizontal +Through hole angled pin header, 1x36, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x36 2.54mm single row +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_1x36_P2.54mm_Vertical +Through hole straight pin header, 1x36, 2.54mm pitch, single row +Through hole pin header THT 1x36 2.54mm single row +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_1x36_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x36 2.54mm single row style1 pin1 left +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_1x36_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x36 2.54mm single row style2 pin1 right +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_1x37_P2.54mm_Horizontal +Through hole angled pin header, 1x37, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x37 2.54mm single row +0 +37 +37 +Connector_PinHeader_2.54mm +PinHeader_1x37_P2.54mm_Vertical +Through hole straight pin header, 1x37, 2.54mm pitch, single row +Through hole pin header THT 1x37 2.54mm single row +0 +37 +37 +Connector_PinHeader_2.54mm +PinHeader_1x37_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x37 2.54mm single row style1 pin1 left +0 +37 +37 +Connector_PinHeader_2.54mm +PinHeader_1x37_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x37 2.54mm single row style2 pin1 right +0 +37 +37 +Connector_PinHeader_2.54mm +PinHeader_1x38_P2.54mm_Horizontal +Through hole angled pin header, 1x38, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x38 2.54mm single row +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_1x38_P2.54mm_Vertical +Through hole straight pin header, 1x38, 2.54mm pitch, single row +Through hole pin header THT 1x38 2.54mm single row +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_1x38_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x38 2.54mm single row style1 pin1 left +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_1x38_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x38 2.54mm single row style2 pin1 right +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_1x39_P2.54mm_Horizontal +Through hole angled pin header, 1x39, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x39 2.54mm single row +0 +39 +39 +Connector_PinHeader_2.54mm +PinHeader_1x39_P2.54mm_Vertical +Through hole straight pin header, 1x39, 2.54mm pitch, single row +Through hole pin header THT 1x39 2.54mm single row +0 +39 +39 +Connector_PinHeader_2.54mm +PinHeader_1x39_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x39 2.54mm single row style1 pin1 left +0 +39 +39 +Connector_PinHeader_2.54mm +PinHeader_1x39_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x39 2.54mm single row style2 pin1 right +0 +39 +39 +Connector_PinHeader_2.54mm +PinHeader_1x40_P2.54mm_Horizontal +Through hole angled pin header, 1x40, 2.54mm pitch, 6mm pin length, single row +Through hole angled pin header THT 1x40 2.54mm single row +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_1x40_P2.54mm_Vertical +Through hole straight pin header, 1x40, 2.54mm pitch, single row +Through hole pin header THT 1x40 2.54mm single row +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_1x40_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight pin header, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left) +Surface mounted pin header SMD 1x40 2.54mm single row style1 pin1 left +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_1x40_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight pin header, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right) +Surface mounted pin header SMD 1x40 2.54mm single row style2 pin1 right +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_2x01_P2.54mm_Horizontal +Through hole angled pin header, 2x01, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x01 2.54mm double row +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_2x01_P2.54mm_Vertical +Through hole straight pin header, 2x01, 2.54mm pitch, double rows +Through hole pin header THT 2x01 2.54mm double row +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_2x01_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x01, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x01 2.54mm double row +0 +2 +2 +Connector_PinHeader_2.54mm +PinHeader_2x02_P2.54mm_Horizontal +Through hole angled pin header, 2x02, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x02 2.54mm double row +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_2x02_P2.54mm_Vertical +Through hole straight pin header, 2x02, 2.54mm pitch, double rows +Through hole pin header THT 2x02 2.54mm double row +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_2x02_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x02, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x02 2.54mm double row +0 +4 +4 +Connector_PinHeader_2.54mm +PinHeader_2x03_P2.54mm_Horizontal +Through hole angled pin header, 2x03, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x03 2.54mm double row +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_2x03_P2.54mm_Vertical +Through hole straight pin header, 2x03, 2.54mm pitch, double rows +Through hole pin header THT 2x03 2.54mm double row +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_2x03_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x03, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x03 2.54mm double row +0 +6 +6 +Connector_PinHeader_2.54mm +PinHeader_2x04_P2.54mm_Horizontal +Through hole angled pin header, 2x04, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x04 2.54mm double row +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_2x04_P2.54mm_Vertical +Through hole straight pin header, 2x04, 2.54mm pitch, double rows +Through hole pin header THT 2x04 2.54mm double row +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_2x04_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x04, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x04 2.54mm double row +0 +8 +8 +Connector_PinHeader_2.54mm +PinHeader_2x05_P2.54mm_Horizontal +Through hole angled pin header, 2x05, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x05 2.54mm double row +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_2x05_P2.54mm_Vertical +Through hole straight pin header, 2x05, 2.54mm pitch, double rows +Through hole pin header THT 2x05 2.54mm double row +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_2x05_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x05, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x05 2.54mm double row +0 +10 +10 +Connector_PinHeader_2.54mm +PinHeader_2x06_P2.54mm_Horizontal +Through hole angled pin header, 2x06, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x06 2.54mm double row +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_2x06_P2.54mm_Vertical +Through hole straight pin header, 2x06, 2.54mm pitch, double rows +Through hole pin header THT 2x06 2.54mm double row +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_2x06_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x06, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x06 2.54mm double row +0 +12 +12 +Connector_PinHeader_2.54mm +PinHeader_2x07_P2.54mm_Horizontal +Through hole angled pin header, 2x07, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x07 2.54mm double row +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_2x07_P2.54mm_Vertical +Through hole straight pin header, 2x07, 2.54mm pitch, double rows +Through hole pin header THT 2x07 2.54mm double row +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_2x07_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x07, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x07 2.54mm double row +0 +14 +14 +Connector_PinHeader_2.54mm +PinHeader_2x08_P2.54mm_Horizontal +Through hole angled pin header, 2x08, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x08 2.54mm double row +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_2x08_P2.54mm_Vertical +Through hole straight pin header, 2x08, 2.54mm pitch, double rows +Through hole pin header THT 2x08 2.54mm double row +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_2x08_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x08, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x08 2.54mm double row +0 +16 +16 +Connector_PinHeader_2.54mm +PinHeader_2x09_P2.54mm_Horizontal +Through hole angled pin header, 2x09, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x09 2.54mm double row +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_2x09_P2.54mm_Vertical +Through hole straight pin header, 2x09, 2.54mm pitch, double rows +Through hole pin header THT 2x09 2.54mm double row +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_2x09_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x09, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x09 2.54mm double row +0 +18 +18 +Connector_PinHeader_2.54mm +PinHeader_2x10_P2.54mm_Horizontal +Through hole angled pin header, 2x10, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x10 2.54mm double row +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_2x10_P2.54mm_Vertical +Through hole straight pin header, 2x10, 2.54mm pitch, double rows +Through hole pin header THT 2x10 2.54mm double row +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_2x10_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x10, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x10 2.54mm double row +0 +20 +20 +Connector_PinHeader_2.54mm +PinHeader_2x11_P2.54mm_Horizontal +Through hole angled pin header, 2x11, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x11 2.54mm double row +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_2x11_P2.54mm_Vertical +Through hole straight pin header, 2x11, 2.54mm pitch, double rows +Through hole pin header THT 2x11 2.54mm double row +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_2x11_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x11, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x11 2.54mm double row +0 +22 +22 +Connector_PinHeader_2.54mm +PinHeader_2x12_P2.54mm_Horizontal +Through hole angled pin header, 2x12, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x12 2.54mm double row +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_2x12_P2.54mm_Vertical +Through hole straight pin header, 2x12, 2.54mm pitch, double rows +Through hole pin header THT 2x12 2.54mm double row +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_2x12_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x12, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x12 2.54mm double row +0 +24 +24 +Connector_PinHeader_2.54mm +PinHeader_2x13_P2.54mm_Horizontal +Through hole angled pin header, 2x13, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x13 2.54mm double row +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_2x13_P2.54mm_Vertical +Through hole straight pin header, 2x13, 2.54mm pitch, double rows +Through hole pin header THT 2x13 2.54mm double row +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_2x13_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x13, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x13 2.54mm double row +0 +26 +26 +Connector_PinHeader_2.54mm +PinHeader_2x14_P2.54mm_Horizontal +Through hole angled pin header, 2x14, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x14 2.54mm double row +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_2x14_P2.54mm_Vertical +Through hole straight pin header, 2x14, 2.54mm pitch, double rows +Through hole pin header THT 2x14 2.54mm double row +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_2x14_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x14, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x14 2.54mm double row +0 +28 +28 +Connector_PinHeader_2.54mm +PinHeader_2x15_P2.54mm_Horizontal +Through hole angled pin header, 2x15, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x15 2.54mm double row +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_2x15_P2.54mm_Vertical +Through hole straight pin header, 2x15, 2.54mm pitch, double rows +Through hole pin header THT 2x15 2.54mm double row +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_2x15_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x15, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x15 2.54mm double row +0 +30 +30 +Connector_PinHeader_2.54mm +PinHeader_2x16_P2.54mm_Horizontal +Through hole angled pin header, 2x16, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x16 2.54mm double row +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_2x16_P2.54mm_Vertical +Through hole straight pin header, 2x16, 2.54mm pitch, double rows +Through hole pin header THT 2x16 2.54mm double row +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_2x16_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x16, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x16 2.54mm double row +0 +32 +32 +Connector_PinHeader_2.54mm +PinHeader_2x17_P2.54mm_Horizontal +Through hole angled pin header, 2x17, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x17 2.54mm double row +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_2x17_P2.54mm_Vertical +Through hole straight pin header, 2x17, 2.54mm pitch, double rows +Through hole pin header THT 2x17 2.54mm double row +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_2x17_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x17, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x17 2.54mm double row +0 +34 +34 +Connector_PinHeader_2.54mm +PinHeader_2x18_P2.54mm_Horizontal +Through hole angled pin header, 2x18, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x18 2.54mm double row +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_2x18_P2.54mm_Vertical +Through hole straight pin header, 2x18, 2.54mm pitch, double rows +Through hole pin header THT 2x18 2.54mm double row +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_2x18_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x18, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x18 2.54mm double row +0 +36 +36 +Connector_PinHeader_2.54mm +PinHeader_2x19_P2.54mm_Horizontal +Through hole angled pin header, 2x19, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x19 2.54mm double row +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_2x19_P2.54mm_Vertical +Through hole straight pin header, 2x19, 2.54mm pitch, double rows +Through hole pin header THT 2x19 2.54mm double row +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_2x19_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x19, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x19 2.54mm double row +0 +38 +38 +Connector_PinHeader_2.54mm +PinHeader_2x20_P2.54mm_Horizontal +Through hole angled pin header, 2x20, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x20 2.54mm double row +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_2x20_P2.54mm_Vertical +Through hole straight pin header, 2x20, 2.54mm pitch, double rows +Through hole pin header THT 2x20 2.54mm double row +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_2x20_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x20, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x20 2.54mm double row +0 +40 +40 +Connector_PinHeader_2.54mm +PinHeader_2x21_P2.54mm_Horizontal +Through hole angled pin header, 2x21, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x21 2.54mm double row +0 +42 +42 +Connector_PinHeader_2.54mm +PinHeader_2x21_P2.54mm_Vertical +Through hole straight pin header, 2x21, 2.54mm pitch, double rows +Through hole pin header THT 2x21 2.54mm double row +0 +42 +42 +Connector_PinHeader_2.54mm +PinHeader_2x21_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x21, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x21 2.54mm double row +0 +42 +42 +Connector_PinHeader_2.54mm +PinHeader_2x22_P2.54mm_Horizontal +Through hole angled pin header, 2x22, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x22 2.54mm double row +0 +44 +44 +Connector_PinHeader_2.54mm +PinHeader_2x22_P2.54mm_Vertical +Through hole straight pin header, 2x22, 2.54mm pitch, double rows +Through hole pin header THT 2x22 2.54mm double row +0 +44 +44 +Connector_PinHeader_2.54mm +PinHeader_2x22_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x22, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x22 2.54mm double row +0 +44 +44 +Connector_PinHeader_2.54mm +PinHeader_2x23_P2.54mm_Horizontal +Through hole angled pin header, 2x23, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x23 2.54mm double row +0 +46 +46 +Connector_PinHeader_2.54mm +PinHeader_2x23_P2.54mm_Vertical +Through hole straight pin header, 2x23, 2.54mm pitch, double rows +Through hole pin header THT 2x23 2.54mm double row +0 +46 +46 +Connector_PinHeader_2.54mm +PinHeader_2x23_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x23, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x23 2.54mm double row +0 +46 +46 +Connector_PinHeader_2.54mm +PinHeader_2x24_P2.54mm_Horizontal +Through hole angled pin header, 2x24, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x24 2.54mm double row +0 +48 +48 +Connector_PinHeader_2.54mm +PinHeader_2x24_P2.54mm_Vertical +Through hole straight pin header, 2x24, 2.54mm pitch, double rows +Through hole pin header THT 2x24 2.54mm double row +0 +48 +48 +Connector_PinHeader_2.54mm +PinHeader_2x24_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x24, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x24 2.54mm double row +0 +48 +48 +Connector_PinHeader_2.54mm +PinHeader_2x25_P2.54mm_Horizontal +Through hole angled pin header, 2x25, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x25 2.54mm double row +0 +50 +50 +Connector_PinHeader_2.54mm +PinHeader_2x25_P2.54mm_Vertical +Through hole straight pin header, 2x25, 2.54mm pitch, double rows +Through hole pin header THT 2x25 2.54mm double row +0 +50 +50 +Connector_PinHeader_2.54mm +PinHeader_2x25_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x25, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x25 2.54mm double row +0 +50 +50 +Connector_PinHeader_2.54mm +PinHeader_2x26_P2.54mm_Horizontal +Through hole angled pin header, 2x26, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x26 2.54mm double row +0 +52 +52 +Connector_PinHeader_2.54mm +PinHeader_2x26_P2.54mm_Vertical +Through hole straight pin header, 2x26, 2.54mm pitch, double rows +Through hole pin header THT 2x26 2.54mm double row +0 +52 +52 +Connector_PinHeader_2.54mm +PinHeader_2x26_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x26, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x26 2.54mm double row +0 +52 +52 +Connector_PinHeader_2.54mm +PinHeader_2x27_P2.54mm_Horizontal +Through hole angled pin header, 2x27, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x27 2.54mm double row +0 +54 +54 +Connector_PinHeader_2.54mm +PinHeader_2x27_P2.54mm_Vertical +Through hole straight pin header, 2x27, 2.54mm pitch, double rows +Through hole pin header THT 2x27 2.54mm double row +0 +54 +54 +Connector_PinHeader_2.54mm +PinHeader_2x27_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x27, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x27 2.54mm double row +0 +54 +54 +Connector_PinHeader_2.54mm +PinHeader_2x28_P2.54mm_Horizontal +Through hole angled pin header, 2x28, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x28 2.54mm double row +0 +56 +56 +Connector_PinHeader_2.54mm +PinHeader_2x28_P2.54mm_Vertical +Through hole straight pin header, 2x28, 2.54mm pitch, double rows +Through hole pin header THT 2x28 2.54mm double row +0 +56 +56 +Connector_PinHeader_2.54mm +PinHeader_2x28_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x28, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x28 2.54mm double row +0 +56 +56 +Connector_PinHeader_2.54mm +PinHeader_2x29_P2.54mm_Horizontal +Through hole angled pin header, 2x29, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x29 2.54mm double row +0 +58 +58 +Connector_PinHeader_2.54mm +PinHeader_2x29_P2.54mm_Vertical +Through hole straight pin header, 2x29, 2.54mm pitch, double rows +Through hole pin header THT 2x29 2.54mm double row +0 +58 +58 +Connector_PinHeader_2.54mm +PinHeader_2x29_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x29, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x29 2.54mm double row +0 +58 +58 +Connector_PinHeader_2.54mm +PinHeader_2x30_P2.54mm_Horizontal +Through hole angled pin header, 2x30, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x30 2.54mm double row +0 +60 +60 +Connector_PinHeader_2.54mm +PinHeader_2x30_P2.54mm_Vertical +Through hole straight pin header, 2x30, 2.54mm pitch, double rows +Through hole pin header THT 2x30 2.54mm double row +0 +60 +60 +Connector_PinHeader_2.54mm +PinHeader_2x30_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x30, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x30 2.54mm double row +0 +60 +60 +Connector_PinHeader_2.54mm +PinHeader_2x31_P2.54mm_Horizontal +Through hole angled pin header, 2x31, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x31 2.54mm double row +0 +62 +62 +Connector_PinHeader_2.54mm +PinHeader_2x31_P2.54mm_Vertical +Through hole straight pin header, 2x31, 2.54mm pitch, double rows +Through hole pin header THT 2x31 2.54mm double row +0 +62 +62 +Connector_PinHeader_2.54mm +PinHeader_2x31_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x31, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x31 2.54mm double row +0 +62 +62 +Connector_PinHeader_2.54mm +PinHeader_2x32_P2.54mm_Horizontal +Through hole angled pin header, 2x32, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x32 2.54mm double row +0 +64 +64 +Connector_PinHeader_2.54mm +PinHeader_2x32_P2.54mm_Vertical +Through hole straight pin header, 2x32, 2.54mm pitch, double rows +Through hole pin header THT 2x32 2.54mm double row +0 +64 +64 +Connector_PinHeader_2.54mm +PinHeader_2x32_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x32, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x32 2.54mm double row +0 +64 +64 +Connector_PinHeader_2.54mm +PinHeader_2x33_P2.54mm_Horizontal +Through hole angled pin header, 2x33, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x33 2.54mm double row +0 +66 +66 +Connector_PinHeader_2.54mm +PinHeader_2x33_P2.54mm_Vertical +Through hole straight pin header, 2x33, 2.54mm pitch, double rows +Through hole pin header THT 2x33 2.54mm double row +0 +66 +66 +Connector_PinHeader_2.54mm +PinHeader_2x33_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x33, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x33 2.54mm double row +0 +66 +66 +Connector_PinHeader_2.54mm +PinHeader_2x34_P2.54mm_Horizontal +Through hole angled pin header, 2x34, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x34 2.54mm double row +0 +68 +68 +Connector_PinHeader_2.54mm +PinHeader_2x34_P2.54mm_Vertical +Through hole straight pin header, 2x34, 2.54mm pitch, double rows +Through hole pin header THT 2x34 2.54mm double row +0 +68 +68 +Connector_PinHeader_2.54mm +PinHeader_2x34_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x34, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x34 2.54mm double row +0 +68 +68 +Connector_PinHeader_2.54mm +PinHeader_2x35_P2.54mm_Horizontal +Through hole angled pin header, 2x35, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x35 2.54mm double row +0 +70 +70 +Connector_PinHeader_2.54mm +PinHeader_2x35_P2.54mm_Vertical +Through hole straight pin header, 2x35, 2.54mm pitch, double rows +Through hole pin header THT 2x35 2.54mm double row +0 +70 +70 +Connector_PinHeader_2.54mm +PinHeader_2x35_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x35, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x35 2.54mm double row +0 +70 +70 +Connector_PinHeader_2.54mm +PinHeader_2x36_P2.54mm_Horizontal +Through hole angled pin header, 2x36, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x36 2.54mm double row +0 +72 +72 +Connector_PinHeader_2.54mm +PinHeader_2x36_P2.54mm_Vertical +Through hole straight pin header, 2x36, 2.54mm pitch, double rows +Through hole pin header THT 2x36 2.54mm double row +0 +72 +72 +Connector_PinHeader_2.54mm +PinHeader_2x36_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x36, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x36 2.54mm double row +0 +72 +72 +Connector_PinHeader_2.54mm +PinHeader_2x37_P2.54mm_Horizontal +Through hole angled pin header, 2x37, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x37 2.54mm double row +0 +74 +74 +Connector_PinHeader_2.54mm +PinHeader_2x37_P2.54mm_Vertical +Through hole straight pin header, 2x37, 2.54mm pitch, double rows +Through hole pin header THT 2x37 2.54mm double row +0 +74 +74 +Connector_PinHeader_2.54mm +PinHeader_2x37_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x37, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x37 2.54mm double row +0 +74 +74 +Connector_PinHeader_2.54mm +PinHeader_2x38_P2.54mm_Horizontal +Through hole angled pin header, 2x38, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x38 2.54mm double row +0 +76 +76 +Connector_PinHeader_2.54mm +PinHeader_2x38_P2.54mm_Vertical +Through hole straight pin header, 2x38, 2.54mm pitch, double rows +Through hole pin header THT 2x38 2.54mm double row +0 +76 +76 +Connector_PinHeader_2.54mm +PinHeader_2x38_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x38, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x38 2.54mm double row +0 +76 +76 +Connector_PinHeader_2.54mm +PinHeader_2x39_P2.54mm_Horizontal +Through hole angled pin header, 2x39, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x39 2.54mm double row +0 +78 +78 +Connector_PinHeader_2.54mm +PinHeader_2x39_P2.54mm_Vertical +Through hole straight pin header, 2x39, 2.54mm pitch, double rows +Through hole pin header THT 2x39 2.54mm double row +0 +78 +78 +Connector_PinHeader_2.54mm +PinHeader_2x39_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x39, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x39 2.54mm double row +0 +78 +78 +Connector_PinHeader_2.54mm +PinHeader_2x40_P2.54mm_Horizontal +Through hole angled pin header, 2x40, 2.54mm pitch, 6mm pin length, double rows +Through hole angled pin header THT 2x40 2.54mm double row +0 +80 +80 +Connector_PinHeader_2.54mm +PinHeader_2x40_P2.54mm_Vertical +Through hole straight pin header, 2x40, 2.54mm pitch, double rows +Through hole pin header THT 2x40 2.54mm double row +0 +80 +80 +Connector_PinHeader_2.54mm +PinHeader_2x40_P2.54mm_Vertical_SMD +surface-mounted straight pin header, 2x40, 2.54mm pitch, double rows +Surface mounted pin header SMD 2x40 2.54mm double row +0 +80 +80 +Connector_PinSocket_1.00mm +PinSocket_1x02_P1.00mm_Vertical +Through hole straight socket strip, 1x02, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x02 1.00mm single row +0 +2 +2 +Connector_PinSocket_1.00mm +PinSocket_1x02_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x02, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x02 1.00mm single row style1 pin1 left +0 +2 +2 +Connector_PinSocket_1.00mm +PinSocket_1x02_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x02, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x02 1.00mm single row style2 pin1 right +0 +2 +2 +Connector_PinSocket_1.00mm +PinSocket_1x03_P1.00mm_Vertical +Through hole straight socket strip, 1x03, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x03 1.00mm single row +0 +3 +3 +Connector_PinSocket_1.00mm +PinSocket_1x03_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x03, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x03 1.00mm single row style1 pin1 left +0 +3 +3 +Connector_PinSocket_1.00mm +PinSocket_1x03_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x03, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x03 1.00mm single row style2 pin1 right +0 +3 +3 +Connector_PinSocket_1.00mm +PinSocket_1x04_P1.00mm_Vertical +Through hole straight socket strip, 1x04, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x04 1.00mm single row +0 +4 +4 +Connector_PinSocket_1.00mm +PinSocket_1x04_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x04, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x04 1.00mm single row style1 pin1 left +0 +4 +4 +Connector_PinSocket_1.00mm +PinSocket_1x04_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x04, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x04 1.00mm single row style2 pin1 right +0 +4 +4 +Connector_PinSocket_1.00mm +PinSocket_1x05_P1.00mm_Vertical +Through hole straight socket strip, 1x05, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x05 1.00mm single row +0 +5 +5 +Connector_PinSocket_1.00mm +PinSocket_1x05_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x05, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x05 1.00mm single row style1 pin1 left +0 +5 +5 +Connector_PinSocket_1.00mm +PinSocket_1x05_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x05, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x05 1.00mm single row style2 pin1 right +0 +5 +5 +Connector_PinSocket_1.00mm +PinSocket_1x06_P1.00mm_Vertical +Through hole straight socket strip, 1x06, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x06 1.00mm single row +0 +6 +6 +Connector_PinSocket_1.00mm +PinSocket_1x06_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x06, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x06 1.00mm single row style1 pin1 left +0 +6 +6 +Connector_PinSocket_1.00mm +PinSocket_1x06_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x06, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x06 1.00mm single row style2 pin1 right +0 +6 +6 +Connector_PinSocket_1.00mm +PinSocket_1x07_P1.00mm_Vertical +Through hole straight socket strip, 1x07, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x07 1.00mm single row +0 +7 +7 +Connector_PinSocket_1.00mm +PinSocket_1x07_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x07, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x07 1.00mm single row style1 pin1 left +0 +7 +7 +Connector_PinSocket_1.00mm +PinSocket_1x07_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x07, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x07 1.00mm single row style2 pin1 right +0 +7 +7 +Connector_PinSocket_1.00mm +PinSocket_1x08_P1.00mm_Vertical +Through hole straight socket strip, 1x08, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x08 1.00mm single row +0 +8 +8 +Connector_PinSocket_1.00mm +PinSocket_1x08_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x08, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x08 1.00mm single row style1 pin1 left +0 +8 +8 +Connector_PinSocket_1.00mm +PinSocket_1x08_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x08, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x08 1.00mm single row style2 pin1 right +0 +8 +8 +Connector_PinSocket_1.00mm +PinSocket_1x09_P1.00mm_Vertical +Through hole straight socket strip, 1x09, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x09 1.00mm single row +0 +9 +9 +Connector_PinSocket_1.00mm +PinSocket_1x09_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x09, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x09 1.00mm single row style1 pin1 left +0 +9 +9 +Connector_PinSocket_1.00mm +PinSocket_1x09_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x09, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x09 1.00mm single row style2 pin1 right +0 +9 +9 +Connector_PinSocket_1.00mm +PinSocket_1x10_P1.00mm_Vertical +Through hole straight socket strip, 1x10, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x10 1.00mm single row +0 +10 +10 +Connector_PinSocket_1.00mm +PinSocket_1x10_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x10, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x10 1.00mm single row style1 pin1 left +0 +10 +10 +Connector_PinSocket_1.00mm +PinSocket_1x10_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x10, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x10 1.00mm single row style2 pin1 right +0 +10 +10 +Connector_PinSocket_1.00mm +PinSocket_1x11_P1.00mm_Vertical +Through hole straight socket strip, 1x11, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x11 1.00mm single row +0 +11 +11 +Connector_PinSocket_1.00mm +PinSocket_1x11_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x11, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x11 1.00mm single row style1 pin1 left +0 +11 +11 +Connector_PinSocket_1.00mm +PinSocket_1x11_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x11, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x11 1.00mm single row style2 pin1 right +0 +11 +11 +Connector_PinSocket_1.00mm +PinSocket_1x12_P1.00mm_Vertical +Through hole straight socket strip, 1x12, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x12 1.00mm single row +0 +12 +12 +Connector_PinSocket_1.00mm +PinSocket_1x12_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x12, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x12 1.00mm single row style1 pin1 left +0 +12 +12 +Connector_PinSocket_1.00mm +PinSocket_1x12_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x12, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x12 1.00mm single row style2 pin1 right +0 +12 +12 +Connector_PinSocket_1.00mm +PinSocket_1x13_P1.00mm_Vertical +Through hole straight socket strip, 1x13, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x13 1.00mm single row +0 +13 +13 +Connector_PinSocket_1.00mm +PinSocket_1x13_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x13, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x13 1.00mm single row style1 pin1 left +0 +13 +13 +Connector_PinSocket_1.00mm +PinSocket_1x13_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x13, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x13 1.00mm single row style2 pin1 right +0 +13 +13 +Connector_PinSocket_1.00mm +PinSocket_1x14_P1.00mm_Vertical +Through hole straight socket strip, 1x14, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x14 1.00mm single row +0 +14 +14 +Connector_PinSocket_1.00mm +PinSocket_1x14_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x14, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x14 1.00mm single row style1 pin1 left +0 +14 +14 +Connector_PinSocket_1.00mm +PinSocket_1x14_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x14, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x14 1.00mm single row style2 pin1 right +0 +14 +14 +Connector_PinSocket_1.00mm +PinSocket_1x15_P1.00mm_Vertical +Through hole straight socket strip, 1x15, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x15 1.00mm single row +0 +15 +15 +Connector_PinSocket_1.00mm +PinSocket_1x15_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x15, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x15 1.00mm single row style1 pin1 left +0 +15 +15 +Connector_PinSocket_1.00mm +PinSocket_1x15_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x15, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x15 1.00mm single row style2 pin1 right +0 +15 +15 +Connector_PinSocket_1.00mm +PinSocket_1x16_P1.00mm_Vertical +Through hole straight socket strip, 1x16, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x16 1.00mm single row +0 +16 +16 +Connector_PinSocket_1.00mm +PinSocket_1x16_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x16, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x16 1.00mm single row style1 pin1 left +0 +16 +16 +Connector_PinSocket_1.00mm +PinSocket_1x16_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x16, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x16 1.00mm single row style2 pin1 right +0 +16 +16 +Connector_PinSocket_1.00mm +PinSocket_1x17_P1.00mm_Vertical +Through hole straight socket strip, 1x17, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x17 1.00mm single row +0 +17 +17 +Connector_PinSocket_1.00mm +PinSocket_1x17_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x17, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x17 1.00mm single row style1 pin1 left +0 +17 +17 +Connector_PinSocket_1.00mm +PinSocket_1x17_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x17, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x17 1.00mm single row style2 pin1 right +0 +17 +17 +Connector_PinSocket_1.00mm +PinSocket_1x18_P1.00mm_Vertical +Through hole straight socket strip, 1x18, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x18 1.00mm single row +0 +18 +18 +Connector_PinSocket_1.00mm +PinSocket_1x18_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x18, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x18 1.00mm single row style1 pin1 left +0 +18 +18 +Connector_PinSocket_1.00mm +PinSocket_1x18_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x18, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x18 1.00mm single row style2 pin1 right +0 +18 +18 +Connector_PinSocket_1.00mm +PinSocket_1x19_P1.00mm_Vertical +Through hole straight socket strip, 1x19, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x19 1.00mm single row +0 +19 +19 +Connector_PinSocket_1.00mm +PinSocket_1x19_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x19, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x19 1.00mm single row style1 pin1 left +0 +19 +19 +Connector_PinSocket_1.00mm +PinSocket_1x19_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x19, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x19 1.00mm single row style2 pin1 right +0 +19 +19 +Connector_PinSocket_1.00mm +PinSocket_1x20_P1.00mm_Vertical +Through hole straight socket strip, 1x20, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x20 1.00mm single row +0 +20 +20 +Connector_PinSocket_1.00mm +PinSocket_1x20_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x20, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x20 1.00mm single row style1 pin1 left +0 +20 +20 +Connector_PinSocket_1.00mm +PinSocket_1x20_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x20, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x20 1.00mm single row style2 pin1 right +0 +20 +20 +Connector_PinSocket_1.00mm +PinSocket_1x21_P1.00mm_Vertical +Through hole straight socket strip, 1x21, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x21 1.00mm single row +0 +21 +21 +Connector_PinSocket_1.00mm +PinSocket_1x21_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x21, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x21 1.00mm single row style1 pin1 left +0 +21 +21 +Connector_PinSocket_1.00mm +PinSocket_1x21_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x21, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x21 1.00mm single row style2 pin1 right +0 +21 +21 +Connector_PinSocket_1.00mm +PinSocket_1x22_P1.00mm_Vertical +Through hole straight socket strip, 1x22, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x22 1.00mm single row +0 +22 +22 +Connector_PinSocket_1.00mm +PinSocket_1x22_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x22, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x22 1.00mm single row style1 pin1 left +0 +22 +22 +Connector_PinSocket_1.00mm +PinSocket_1x22_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x22, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x22 1.00mm single row style2 pin1 right +0 +22 +22 +Connector_PinSocket_1.00mm +PinSocket_1x23_P1.00mm_Vertical +Through hole straight socket strip, 1x23, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x23 1.00mm single row +0 +23 +23 +Connector_PinSocket_1.00mm +PinSocket_1x23_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x23, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x23 1.00mm single row style1 pin1 left +0 +23 +23 +Connector_PinSocket_1.00mm +PinSocket_1x23_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x23, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x23 1.00mm single row style2 pin1 right +0 +23 +23 +Connector_PinSocket_1.00mm +PinSocket_1x24_P1.00mm_Vertical +Through hole straight socket strip, 1x24, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x24 1.00mm single row +0 +24 +24 +Connector_PinSocket_1.00mm +PinSocket_1x24_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x24, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x24 1.00mm single row style1 pin1 left +0 +24 +24 +Connector_PinSocket_1.00mm +PinSocket_1x24_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x24, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x24 1.00mm single row style2 pin1 right +0 +24 +24 +Connector_PinSocket_1.00mm +PinSocket_1x25_P1.00mm_Vertical +Through hole straight socket strip, 1x25, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x25 1.00mm single row +0 +25 +25 +Connector_PinSocket_1.00mm +PinSocket_1x25_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x25, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x25 1.00mm single row style1 pin1 left +0 +25 +25 +Connector_PinSocket_1.00mm +PinSocket_1x25_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x25, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x25 1.00mm single row style2 pin1 right +0 +25 +25 +Connector_PinSocket_1.00mm +PinSocket_1x26_P1.00mm_Vertical +Through hole straight socket strip, 1x26, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x26 1.00mm single row +0 +26 +26 +Connector_PinSocket_1.00mm +PinSocket_1x26_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x26, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x26 1.00mm single row style1 pin1 left +0 +26 +26 +Connector_PinSocket_1.00mm +PinSocket_1x26_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x26, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x26 1.00mm single row style2 pin1 right +0 +26 +26 +Connector_PinSocket_1.00mm +PinSocket_1x27_P1.00mm_Vertical +Through hole straight socket strip, 1x27, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x27 1.00mm single row +0 +27 +27 +Connector_PinSocket_1.00mm +PinSocket_1x27_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x27, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x27 1.00mm single row style1 pin1 left +0 +27 +27 +Connector_PinSocket_1.00mm +PinSocket_1x27_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x27, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x27 1.00mm single row style2 pin1 right +0 +27 +27 +Connector_PinSocket_1.00mm +PinSocket_1x28_P1.00mm_Vertical +Through hole straight socket strip, 1x28, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x28 1.00mm single row +0 +28 +28 +Connector_PinSocket_1.00mm +PinSocket_1x28_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x28, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x28 1.00mm single row style1 pin1 left +0 +28 +28 +Connector_PinSocket_1.00mm +PinSocket_1x28_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x28, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x28 1.00mm single row style2 pin1 right +0 +28 +28 +Connector_PinSocket_1.00mm +PinSocket_1x29_P1.00mm_Vertical +Through hole straight socket strip, 1x29, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x29 1.00mm single row +0 +29 +29 +Connector_PinSocket_1.00mm +PinSocket_1x29_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x29, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x29 1.00mm single row style1 pin1 left +0 +29 +29 +Connector_PinSocket_1.00mm +PinSocket_1x29_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x29, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x29 1.00mm single row style2 pin1 right +0 +29 +29 +Connector_PinSocket_1.00mm +PinSocket_1x30_P1.00mm_Vertical +Through hole straight socket strip, 1x30, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x30 1.00mm single row +0 +30 +30 +Connector_PinSocket_1.00mm +PinSocket_1x30_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x30, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x30 1.00mm single row style1 pin1 left +0 +30 +30 +Connector_PinSocket_1.00mm +PinSocket_1x30_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x30, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x30 1.00mm single row style2 pin1 right +0 +30 +30 +Connector_PinSocket_1.00mm +PinSocket_1x31_P1.00mm_Vertical +Through hole straight socket strip, 1x31, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x31 1.00mm single row +0 +31 +31 +Connector_PinSocket_1.00mm +PinSocket_1x31_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x31, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x31 1.00mm single row style1 pin1 left +0 +31 +31 +Connector_PinSocket_1.00mm +PinSocket_1x31_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x31, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x31 1.00mm single row style2 pin1 right +0 +31 +31 +Connector_PinSocket_1.00mm +PinSocket_1x32_P1.00mm_Vertical +Through hole straight socket strip, 1x32, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x32 1.00mm single row +0 +32 +32 +Connector_PinSocket_1.00mm +PinSocket_1x32_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x32, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x32 1.00mm single row style1 pin1 left +0 +32 +32 +Connector_PinSocket_1.00mm +PinSocket_1x32_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x32, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x32 1.00mm single row style2 pin1 right +0 +32 +32 +Connector_PinSocket_1.00mm +PinSocket_1x33_P1.00mm_Vertical +Through hole straight socket strip, 1x33, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x33 1.00mm single row +0 +33 +33 +Connector_PinSocket_1.00mm +PinSocket_1x33_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x33, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x33 1.00mm single row style1 pin1 left +0 +33 +33 +Connector_PinSocket_1.00mm +PinSocket_1x33_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x33, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x33 1.00mm single row style2 pin1 right +0 +33 +33 +Connector_PinSocket_1.00mm +PinSocket_1x34_P1.00mm_Vertical +Through hole straight socket strip, 1x34, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x34 1.00mm single row +0 +34 +34 +Connector_PinSocket_1.00mm +PinSocket_1x34_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x34, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x34 1.00mm single row style1 pin1 left +0 +34 +34 +Connector_PinSocket_1.00mm +PinSocket_1x34_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x34, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x34 1.00mm single row style2 pin1 right +0 +34 +34 +Connector_PinSocket_1.00mm +PinSocket_1x35_P1.00mm_Vertical +Through hole straight socket strip, 1x35, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x35 1.00mm single row +0 +35 +35 +Connector_PinSocket_1.00mm +PinSocket_1x35_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x35, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x35 1.00mm single row style1 pin1 left +0 +35 +35 +Connector_PinSocket_1.00mm +PinSocket_1x35_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x35, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x35 1.00mm single row style2 pin1 right +0 +35 +35 +Connector_PinSocket_1.00mm +PinSocket_1x36_P1.00mm_Vertical +Through hole straight socket strip, 1x36, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x36 1.00mm single row +0 +36 +36 +Connector_PinSocket_1.00mm +PinSocket_1x36_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x36, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x36 1.00mm single row style1 pin1 left +0 +36 +36 +Connector_PinSocket_1.00mm +PinSocket_1x36_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x36, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x36 1.00mm single row style2 pin1 right +0 +36 +36 +Connector_PinSocket_1.00mm +PinSocket_1x37_P1.00mm_Vertical +Through hole straight socket strip, 1x37, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x37 1.00mm single row +0 +37 +37 +Connector_PinSocket_1.00mm +PinSocket_1x37_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x37, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x37 1.00mm single row style1 pin1 left +0 +37 +37 +Connector_PinSocket_1.00mm +PinSocket_1x37_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x37, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x37 1.00mm single row style2 pin1 right +0 +37 +37 +Connector_PinSocket_1.00mm +PinSocket_1x38_P1.00mm_Vertical +Through hole straight socket strip, 1x38, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x38 1.00mm single row +0 +38 +38 +Connector_PinSocket_1.00mm +PinSocket_1x38_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x38, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x38 1.00mm single row style1 pin1 left +0 +38 +38 +Connector_PinSocket_1.00mm +PinSocket_1x38_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x38, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x38 1.00mm single row style2 pin1 right +0 +38 +38 +Connector_PinSocket_1.00mm +PinSocket_1x39_P1.00mm_Vertical +Through hole straight socket strip, 1x39, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x39 1.00mm single row +0 +39 +39 +Connector_PinSocket_1.00mm +PinSocket_1x39_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x39, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x39 1.00mm single row style1 pin1 left +0 +39 +39 +Connector_PinSocket_1.00mm +PinSocket_1x39_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x39, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x39 1.00mm single row style2 pin1 right +0 +39 +39 +Connector_PinSocket_1.00mm +PinSocket_1x40_P1.00mm_Vertical +Through hole straight socket strip, 1x40, 1.00mm pitch, single row (https://gct.co/files/drawings/bc065.pdf), script generated +Through hole socket strip THT 1x40 1.00mm single row +0 +40 +40 +Connector_PinSocket_1.00mm +PinSocket_1x40_P1.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x40, 1.00mm pitch, single row, style 1 (pin 1 left) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x40 1.00mm single row style1 pin1 left +0 +40 +40 +Connector_PinSocket_1.00mm +PinSocket_1x40_P1.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x40, 1.00mm pitch, single row, style 2 (pin 1 right) (https://gct.co/files/drawings/bc070.pdf), script generated +Surface mounted socket strip SMD 1x40 1.00mm single row style2 pin1 right +0 +40 +40 +Connector_PinSocket_1.00mm +PinSocket_2x02_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x02, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x02 1.00mm double row +0 +4 +4 +Connector_PinSocket_1.00mm +PinSocket_2x03_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x03, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x03 1.00mm double row +0 +6 +6 +Connector_PinSocket_1.00mm +PinSocket_2x04_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x04, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x04 1.00mm double row +0 +8 +8 +Connector_PinSocket_1.00mm +PinSocket_2x05_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x05, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x05 1.00mm double row +0 +10 +10 +Connector_PinSocket_1.00mm +PinSocket_2x06_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x06, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x06 1.00mm double row +0 +12 +12 +Connector_PinSocket_1.00mm +PinSocket_2x07_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x07, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x07 1.00mm double row +0 +14 +14 +Connector_PinSocket_1.00mm +PinSocket_2x08_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x08, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x08 1.00mm double row +0 +16 +16 +Connector_PinSocket_1.00mm +PinSocket_2x09_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x09, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x09 1.00mm double row +0 +18 +18 +Connector_PinSocket_1.00mm +PinSocket_2x10_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x10, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x10 1.00mm double row +0 +20 +20 +Connector_PinSocket_1.00mm +PinSocket_2x11_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x11, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x11 1.00mm double row +0 +22 +22 +Connector_PinSocket_1.00mm +PinSocket_2x12_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x12, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x12 1.00mm double row +0 +24 +24 +Connector_PinSocket_1.00mm +PinSocket_2x13_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x13, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x13 1.00mm double row +0 +26 +26 +Connector_PinSocket_1.00mm +PinSocket_2x14_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x14, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x14 1.00mm double row +0 +28 +28 +Connector_PinSocket_1.00mm +PinSocket_2x15_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x15, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x15 1.00mm double row +0 +30 +30 +Connector_PinSocket_1.00mm +PinSocket_2x16_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x16, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x16 1.00mm double row +0 +32 +32 +Connector_PinSocket_1.00mm +PinSocket_2x17_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x17, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x17 1.00mm double row +0 +34 +34 +Connector_PinSocket_1.00mm +PinSocket_2x18_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x18, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x18 1.00mm double row +0 +36 +36 +Connector_PinSocket_1.00mm +PinSocket_2x19_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x19, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x19 1.00mm double row +0 +38 +38 +Connector_PinSocket_1.00mm +PinSocket_2x20_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x20, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x20 1.00mm double row +0 +40 +40 +Connector_PinSocket_1.00mm +PinSocket_2x21_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x21, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x21 1.00mm double row +0 +42 +42 +Connector_PinSocket_1.00mm +PinSocket_2x22_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x22, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x22 1.00mm double row +0 +44 +44 +Connector_PinSocket_1.00mm +PinSocket_2x23_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x23, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x23 1.00mm double row +0 +46 +46 +Connector_PinSocket_1.00mm +PinSocket_2x24_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x24, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x24 1.00mm double row +0 +48 +48 +Connector_PinSocket_1.00mm +PinSocket_2x25_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x25, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x25 1.00mm double row +0 +50 +50 +Connector_PinSocket_1.00mm +PinSocket_2x26_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x26, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x26 1.00mm double row +0 +52 +52 +Connector_PinSocket_1.00mm +PinSocket_2x27_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x27, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x27 1.00mm double row +0 +54 +54 +Connector_PinSocket_1.00mm +PinSocket_2x28_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x28, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x28 1.00mm double row +0 +56 +56 +Connector_PinSocket_1.00mm +PinSocket_2x29_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x29, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x29 1.00mm double row +0 +58 +58 +Connector_PinSocket_1.00mm +PinSocket_2x30_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x30, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x30 1.00mm double row +0 +60 +60 +Connector_PinSocket_1.00mm +PinSocket_2x31_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x31, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x31 1.00mm double row +0 +62 +62 +Connector_PinSocket_1.00mm +PinSocket_2x32_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x32, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x32 1.00mm double row +0 +64 +64 +Connector_PinSocket_1.00mm +PinSocket_2x33_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x33, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x33 1.00mm double row +0 +66 +66 +Connector_PinSocket_1.00mm +PinSocket_2x34_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x34, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x34 1.00mm double row +0 +68 +68 +Connector_PinSocket_1.00mm +PinSocket_2x35_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x35, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x35 1.00mm double row +0 +70 +70 +Connector_PinSocket_1.00mm +PinSocket_2x36_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x36, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x36 1.00mm double row +0 +72 +72 +Connector_PinSocket_1.00mm +PinSocket_2x37_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x37, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x37 1.00mm double row +0 +74 +74 +Connector_PinSocket_1.00mm +PinSocket_2x38_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x38, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x38 1.00mm double row +0 +76 +76 +Connector_PinSocket_1.00mm +PinSocket_2x39_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x39, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x39 1.00mm double row +0 +78 +78 +Connector_PinSocket_1.00mm +PinSocket_2x40_P1.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x40, 1.00mm pitch, double cols (https://gct.co/files/drawings/bc085.pdf), script generated +Surface mounted socket strip SMD 2x40 1.00mm double row +0 +80 +80 +Connector_PinSocket_1.27mm +PinSocket_1x01_P1.27mm_Vertical +Through hole straight socket strip, 1x01, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x01 1.27mm single row +0 +1 +1 +Connector_PinSocket_1.27mm +PinSocket_1x02_P1.27mm_Vertical +Through hole straight socket strip, 1x02, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x02 1.27mm single row +0 +2 +2 +Connector_PinSocket_1.27mm +PinSocket_1x02_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x02, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x02 1.27mm single row style1 pin1 left +0 +2 +2 +Connector_PinSocket_1.27mm +PinSocket_1x02_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x02, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x02 1.27mm single row style2 pin1 right +0 +2 +2 +Connector_PinSocket_1.27mm +PinSocket_1x03_P1.27mm_Vertical +Through hole straight socket strip, 1x03, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x03 1.27mm single row +0 +3 +3 +Connector_PinSocket_1.27mm +PinSocket_1x03_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x03, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x03 1.27mm single row style1 pin1 left +0 +3 +3 +Connector_PinSocket_1.27mm +PinSocket_1x03_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x03, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x03 1.27mm single row style2 pin1 right +0 +3 +3 +Connector_PinSocket_1.27mm +PinSocket_1x04_P1.27mm_Vertical +Through hole straight socket strip, 1x04, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x04 1.27mm single row +0 +4 +4 +Connector_PinSocket_1.27mm +PinSocket_1x04_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x04, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x04 1.27mm single row style1 pin1 left +0 +4 +4 +Connector_PinSocket_1.27mm +PinSocket_1x04_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x04, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x04 1.27mm single row style2 pin1 right +0 +4 +4 +Connector_PinSocket_1.27mm +PinSocket_1x05_P1.27mm_Vertical +Through hole straight socket strip, 1x05, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x05 1.27mm single row +0 +5 +5 +Connector_PinSocket_1.27mm +PinSocket_1x05_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x05, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x05 1.27mm single row style1 pin1 left +0 +5 +5 +Connector_PinSocket_1.27mm +PinSocket_1x05_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x05, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x05 1.27mm single row style2 pin1 right +0 +5 +5 +Connector_PinSocket_1.27mm +PinSocket_1x06_P1.27mm_Vertical +Through hole straight socket strip, 1x06, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x06 1.27mm single row +0 +6 +6 +Connector_PinSocket_1.27mm +PinSocket_1x06_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x06, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x06 1.27mm single row style1 pin1 left +0 +6 +6 +Connector_PinSocket_1.27mm +PinSocket_1x06_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x06, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x06 1.27mm single row style2 pin1 right +0 +6 +6 +Connector_PinSocket_1.27mm +PinSocket_1x07_P1.27mm_Vertical +Through hole straight socket strip, 1x07, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x07 1.27mm single row +0 +7 +7 +Connector_PinSocket_1.27mm +PinSocket_1x07_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x07, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x07 1.27mm single row style1 pin1 left +0 +7 +7 +Connector_PinSocket_1.27mm +PinSocket_1x07_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x07, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x07 1.27mm single row style2 pin1 right +0 +7 +7 +Connector_PinSocket_1.27mm +PinSocket_1x08_P1.27mm_Vertical +Through hole straight socket strip, 1x08, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x08 1.27mm single row +0 +8 +8 +Connector_PinSocket_1.27mm +PinSocket_1x08_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x08, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x08 1.27mm single row style1 pin1 left +0 +8 +8 +Connector_PinSocket_1.27mm +PinSocket_1x08_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x08, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x08 1.27mm single row style2 pin1 right +0 +8 +8 +Connector_PinSocket_1.27mm +PinSocket_1x09_P1.27mm_Vertical +Through hole straight socket strip, 1x09, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x09 1.27mm single row +0 +9 +9 +Connector_PinSocket_1.27mm +PinSocket_1x09_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x09, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x09 1.27mm single row style1 pin1 left +0 +9 +9 +Connector_PinSocket_1.27mm +PinSocket_1x09_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x09, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x09 1.27mm single row style2 pin1 right +0 +9 +9 +Connector_PinSocket_1.27mm +PinSocket_1x10_P1.27mm_Vertical +Through hole straight socket strip, 1x10, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x10 1.27mm single row +0 +10 +10 +Connector_PinSocket_1.27mm +PinSocket_1x10_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x10, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x10 1.27mm single row style1 pin1 left +0 +10 +10 +Connector_PinSocket_1.27mm +PinSocket_1x10_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x10, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x10 1.27mm single row style2 pin1 right +0 +10 +10 +Connector_PinSocket_1.27mm +PinSocket_1x11_P1.27mm_Vertical +Through hole straight socket strip, 1x11, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x11 1.27mm single row +0 +11 +11 +Connector_PinSocket_1.27mm +PinSocket_1x11_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x11, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x11 1.27mm single row style1 pin1 left +0 +11 +11 +Connector_PinSocket_1.27mm +PinSocket_1x11_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x11, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x11 1.27mm single row style2 pin1 right +0 +11 +11 +Connector_PinSocket_1.27mm +PinSocket_1x12_P1.27mm_Vertical +Through hole straight socket strip, 1x12, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x12 1.27mm single row +0 +12 +12 +Connector_PinSocket_1.27mm +PinSocket_1x12_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x12, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x12 1.27mm single row style1 pin1 left +0 +12 +12 +Connector_PinSocket_1.27mm +PinSocket_1x12_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x12, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x12 1.27mm single row style2 pin1 right +0 +12 +12 +Connector_PinSocket_1.27mm +PinSocket_1x13_P1.27mm_Vertical +Through hole straight socket strip, 1x13, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x13 1.27mm single row +0 +13 +13 +Connector_PinSocket_1.27mm +PinSocket_1x13_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x13, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x13 1.27mm single row style1 pin1 left +0 +13 +13 +Connector_PinSocket_1.27mm +PinSocket_1x13_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x13, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x13 1.27mm single row style2 pin1 right +0 +13 +13 +Connector_PinSocket_1.27mm +PinSocket_1x14_P1.27mm_Vertical +Through hole straight socket strip, 1x14, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x14 1.27mm single row +0 +14 +14 +Connector_PinSocket_1.27mm +PinSocket_1x14_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x14, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x14 1.27mm single row style1 pin1 left +0 +14 +14 +Connector_PinSocket_1.27mm +PinSocket_1x14_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x14, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x14 1.27mm single row style2 pin1 right +0 +14 +14 +Connector_PinSocket_1.27mm +PinSocket_1x15_P1.27mm_Vertical +Through hole straight socket strip, 1x15, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x15 1.27mm single row +0 +15 +15 +Connector_PinSocket_1.27mm +PinSocket_1x15_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x15, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x15 1.27mm single row style1 pin1 left +0 +15 +15 +Connector_PinSocket_1.27mm +PinSocket_1x15_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x15, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x15 1.27mm single row style2 pin1 right +0 +15 +15 +Connector_PinSocket_1.27mm +PinSocket_1x16_P1.27mm_Vertical +Through hole straight socket strip, 1x16, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x16 1.27mm single row +0 +16 +16 +Connector_PinSocket_1.27mm +PinSocket_1x16_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x16, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x16 1.27mm single row style1 pin1 left +0 +16 +16 +Connector_PinSocket_1.27mm +PinSocket_1x16_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x16, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x16 1.27mm single row style2 pin1 right +0 +16 +16 +Connector_PinSocket_1.27mm +PinSocket_1x17_P1.27mm_Vertical +Through hole straight socket strip, 1x17, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x17 1.27mm single row +0 +17 +17 +Connector_PinSocket_1.27mm +PinSocket_1x17_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x17, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x17 1.27mm single row style1 pin1 left +0 +17 +17 +Connector_PinSocket_1.27mm +PinSocket_1x17_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x17, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x17 1.27mm single row style2 pin1 right +0 +17 +17 +Connector_PinSocket_1.27mm +PinSocket_1x18_P1.27mm_Vertical +Through hole straight socket strip, 1x18, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x18 1.27mm single row +0 +18 +18 +Connector_PinSocket_1.27mm +PinSocket_1x18_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x18, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x18 1.27mm single row style1 pin1 left +0 +18 +18 +Connector_PinSocket_1.27mm +PinSocket_1x18_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x18, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x18 1.27mm single row style2 pin1 right +0 +18 +18 +Connector_PinSocket_1.27mm +PinSocket_1x19_P1.27mm_Vertical +Through hole straight socket strip, 1x19, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x19 1.27mm single row +0 +19 +19 +Connector_PinSocket_1.27mm +PinSocket_1x19_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x19, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x19 1.27mm single row style1 pin1 left +0 +19 +19 +Connector_PinSocket_1.27mm +PinSocket_1x19_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x19, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x19 1.27mm single row style2 pin1 right +0 +19 +19 +Connector_PinSocket_1.27mm +PinSocket_1x20_P1.27mm_Vertical +Through hole straight socket strip, 1x20, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x20 1.27mm single row +0 +20 +20 +Connector_PinSocket_1.27mm +PinSocket_1x20_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x20, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x20 1.27mm single row style1 pin1 left +0 +20 +20 +Connector_PinSocket_1.27mm +PinSocket_1x20_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x20, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x20 1.27mm single row style2 pin1 right +0 +20 +20 +Connector_PinSocket_1.27mm +PinSocket_1x21_P1.27mm_Vertical +Through hole straight socket strip, 1x21, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x21 1.27mm single row +0 +21 +21 +Connector_PinSocket_1.27mm +PinSocket_1x21_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x21, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x21 1.27mm single row style1 pin1 left +0 +21 +21 +Connector_PinSocket_1.27mm +PinSocket_1x21_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x21, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x21 1.27mm single row style2 pin1 right +0 +21 +21 +Connector_PinSocket_1.27mm +PinSocket_1x22_P1.27mm_Vertical +Through hole straight socket strip, 1x22, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x22 1.27mm single row +0 +22 +22 +Connector_PinSocket_1.27mm +PinSocket_1x22_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x22, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x22 1.27mm single row style1 pin1 left +0 +22 +22 +Connector_PinSocket_1.27mm +PinSocket_1x22_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x22, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x22 1.27mm single row style2 pin1 right +0 +22 +22 +Connector_PinSocket_1.27mm +PinSocket_1x23_P1.27mm_Vertical +Through hole straight socket strip, 1x23, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x23 1.27mm single row +0 +23 +23 +Connector_PinSocket_1.27mm +PinSocket_1x23_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x23, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x23 1.27mm single row style1 pin1 left +0 +23 +23 +Connector_PinSocket_1.27mm +PinSocket_1x23_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x23, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x23 1.27mm single row style2 pin1 right +0 +23 +23 +Connector_PinSocket_1.27mm +PinSocket_1x24_P1.27mm_Vertical +Through hole straight socket strip, 1x24, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x24 1.27mm single row +0 +24 +24 +Connector_PinSocket_1.27mm +PinSocket_1x24_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x24, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x24 1.27mm single row style1 pin1 left +0 +24 +24 +Connector_PinSocket_1.27mm +PinSocket_1x24_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x24, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x24 1.27mm single row style2 pin1 right +0 +24 +24 +Connector_PinSocket_1.27mm +PinSocket_1x25_P1.27mm_Vertical +Through hole straight socket strip, 1x25, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x25 1.27mm single row +0 +25 +25 +Connector_PinSocket_1.27mm +PinSocket_1x25_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x25, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x25 1.27mm single row style1 pin1 left +0 +25 +25 +Connector_PinSocket_1.27mm +PinSocket_1x25_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x25, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x25 1.27mm single row style2 pin1 right +0 +25 +25 +Connector_PinSocket_1.27mm +PinSocket_1x26_P1.27mm_Vertical +Through hole straight socket strip, 1x26, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x26 1.27mm single row +0 +26 +26 +Connector_PinSocket_1.27mm +PinSocket_1x26_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x26, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x26 1.27mm single row style1 pin1 left +0 +26 +26 +Connector_PinSocket_1.27mm +PinSocket_1x26_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x26, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x26 1.27mm single row style2 pin1 right +0 +26 +26 +Connector_PinSocket_1.27mm +PinSocket_1x27_P1.27mm_Vertical +Through hole straight socket strip, 1x27, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x27 1.27mm single row +0 +27 +27 +Connector_PinSocket_1.27mm +PinSocket_1x27_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x27, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x27 1.27mm single row style1 pin1 left +0 +27 +27 +Connector_PinSocket_1.27mm +PinSocket_1x27_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x27, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x27 1.27mm single row style2 pin1 right +0 +27 +27 +Connector_PinSocket_1.27mm +PinSocket_1x28_P1.27mm_Vertical +Through hole straight socket strip, 1x28, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x28 1.27mm single row +0 +28 +28 +Connector_PinSocket_1.27mm +PinSocket_1x28_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x28, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x28 1.27mm single row style1 pin1 left +0 +28 +28 +Connector_PinSocket_1.27mm +PinSocket_1x28_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x28, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x28 1.27mm single row style2 pin1 right +0 +28 +28 +Connector_PinSocket_1.27mm +PinSocket_1x29_P1.27mm_Vertical +Through hole straight socket strip, 1x29, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x29 1.27mm single row +0 +29 +29 +Connector_PinSocket_1.27mm +PinSocket_1x29_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x29, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x29 1.27mm single row style1 pin1 left +0 +29 +29 +Connector_PinSocket_1.27mm +PinSocket_1x29_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x29, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x29 1.27mm single row style2 pin1 right +0 +29 +29 +Connector_PinSocket_1.27mm +PinSocket_1x30_P1.27mm_Vertical +Through hole straight socket strip, 1x30, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x30 1.27mm single row +0 +30 +30 +Connector_PinSocket_1.27mm +PinSocket_1x30_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x30, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x30 1.27mm single row style1 pin1 left +0 +30 +30 +Connector_PinSocket_1.27mm +PinSocket_1x30_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x30, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x30 1.27mm single row style2 pin1 right +0 +30 +30 +Connector_PinSocket_1.27mm +PinSocket_1x31_P1.27mm_Vertical +Through hole straight socket strip, 1x31, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x31 1.27mm single row +0 +31 +31 +Connector_PinSocket_1.27mm +PinSocket_1x31_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x31, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x31 1.27mm single row style1 pin1 left +0 +31 +31 +Connector_PinSocket_1.27mm +PinSocket_1x31_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x31, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x31 1.27mm single row style2 pin1 right +0 +31 +31 +Connector_PinSocket_1.27mm +PinSocket_1x32_P1.27mm_Vertical +Through hole straight socket strip, 1x32, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x32 1.27mm single row +0 +32 +32 +Connector_PinSocket_1.27mm +PinSocket_1x32_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x32, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x32 1.27mm single row style1 pin1 left +0 +32 +32 +Connector_PinSocket_1.27mm +PinSocket_1x32_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x32, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x32 1.27mm single row style2 pin1 right +0 +32 +32 +Connector_PinSocket_1.27mm +PinSocket_1x33_P1.27mm_Vertical +Through hole straight socket strip, 1x33, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x33 1.27mm single row +0 +33 +33 +Connector_PinSocket_1.27mm +PinSocket_1x33_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x33, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x33 1.27mm single row style1 pin1 left +0 +33 +33 +Connector_PinSocket_1.27mm +PinSocket_1x33_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x33, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x33 1.27mm single row style2 pin1 right +0 +33 +33 +Connector_PinSocket_1.27mm +PinSocket_1x34_P1.27mm_Vertical +Through hole straight socket strip, 1x34, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x34 1.27mm single row +0 +34 +34 +Connector_PinSocket_1.27mm +PinSocket_1x34_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x34, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x34 1.27mm single row style1 pin1 left +0 +34 +34 +Connector_PinSocket_1.27mm +PinSocket_1x34_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x34, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x34 1.27mm single row style2 pin1 right +0 +34 +34 +Connector_PinSocket_1.27mm +PinSocket_1x35_P1.27mm_Vertical +Through hole straight socket strip, 1x35, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x35 1.27mm single row +0 +35 +35 +Connector_PinSocket_1.27mm +PinSocket_1x35_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x35, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x35 1.27mm single row style1 pin1 left +0 +35 +35 +Connector_PinSocket_1.27mm +PinSocket_1x35_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x35, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x35 1.27mm single row style2 pin1 right +0 +35 +35 +Connector_PinSocket_1.27mm +PinSocket_1x36_P1.27mm_Vertical +Through hole straight socket strip, 1x36, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x36 1.27mm single row +0 +36 +36 +Connector_PinSocket_1.27mm +PinSocket_1x36_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x36, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x36 1.27mm single row style1 pin1 left +0 +36 +36 +Connector_PinSocket_1.27mm +PinSocket_1x36_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x36, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x36 1.27mm single row style2 pin1 right +0 +36 +36 +Connector_PinSocket_1.27mm +PinSocket_1x37_P1.27mm_Vertical +Through hole straight socket strip, 1x37, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x37 1.27mm single row +0 +37 +37 +Connector_PinSocket_1.27mm +PinSocket_1x37_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x37, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x37 1.27mm single row style1 pin1 left +0 +37 +37 +Connector_PinSocket_1.27mm +PinSocket_1x37_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x37, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x37 1.27mm single row style2 pin1 right +0 +37 +37 +Connector_PinSocket_1.27mm +PinSocket_1x38_P1.27mm_Vertical +Through hole straight socket strip, 1x38, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x38 1.27mm single row +0 +38 +38 +Connector_PinSocket_1.27mm +PinSocket_1x38_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x38, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x38 1.27mm single row style1 pin1 left +0 +38 +38 +Connector_PinSocket_1.27mm +PinSocket_1x38_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x38, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x38 1.27mm single row style2 pin1 right +0 +38 +38 +Connector_PinSocket_1.27mm +PinSocket_1x39_P1.27mm_Vertical +Through hole straight socket strip, 1x39, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x39 1.27mm single row +0 +39 +39 +Connector_PinSocket_1.27mm +PinSocket_1x39_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x39, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x39 1.27mm single row style1 pin1 left +0 +39 +39 +Connector_PinSocket_1.27mm +PinSocket_1x39_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x39, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x39 1.27mm single row style2 pin1 right +0 +39 +39 +Connector_PinSocket_1.27mm +PinSocket_1x40_P1.27mm_Vertical +Through hole straight socket strip, 1x40, 1.27mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x40 1.27mm single row +0 +40 +40 +Connector_PinSocket_1.27mm +PinSocket_1x40_P1.27mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x40, 1.27mm pitch, single row, style 1 (pin 1 left) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x40 1.27mm single row style1 pin1 left +0 +40 +40 +Connector_PinSocket_1.27mm +PinSocket_1x40_P1.27mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x40, 1.27mm pitch, single row, style 2 (pin 1 right) (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD075.pdf&t=1511594726925), script generated +Surface mounted socket strip SMD 1x40 1.27mm single row style2 pin1 right +0 +40 +40 +Connector_PinSocket_1.27mm +PinSocket_2x01_P1.27mm_Vertical +Through hole straight socket strip, 2x01, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x01 1.27mm double row +0 +2 +2 +Connector_PinSocket_1.27mm +PinSocket_2x01_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x01, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x01 1.27mm double row +0 +2 +2 +Connector_PinSocket_1.27mm +PinSocket_2x02_P1.27mm_Vertical +Through hole straight socket strip, 2x02, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x02 1.27mm double row +0 +4 +4 +Connector_PinSocket_1.27mm +PinSocket_2x02_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x02, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x02 1.27mm double row +0 +4 +4 +Connector_PinSocket_1.27mm +PinSocket_2x03_P1.27mm_Horizontal +Through hole angled socket strip, 2x03, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x03 1.27mm double row +0 +6 +6 +Connector_PinSocket_1.27mm +PinSocket_2x03_P1.27mm_Vertical +Through hole straight socket strip, 2x03, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x03 1.27mm double row +0 +6 +6 +Connector_PinSocket_1.27mm +PinSocket_2x03_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x03, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x03 1.27mm double row +0 +6 +6 +Connector_PinSocket_1.27mm +PinSocket_2x04_P1.27mm_Horizontal +Through hole angled socket strip, 2x04, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x04 1.27mm double row +0 +8 +8 +Connector_PinSocket_1.27mm +PinSocket_2x04_P1.27mm_Vertical +Through hole straight socket strip, 2x04, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x04 1.27mm double row +0 +8 +8 +Connector_PinSocket_1.27mm +PinSocket_2x04_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x04, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x04 1.27mm double row +0 +8 +8 +Connector_PinSocket_1.27mm +PinSocket_2x05_P1.27mm_Horizontal +Through hole angled socket strip, 2x05, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x05 1.27mm double row +0 +10 +10 +Connector_PinSocket_1.27mm +PinSocket_2x05_P1.27mm_Vertical +Through hole straight socket strip, 2x05, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x05 1.27mm double row +0 +10 +10 +Connector_PinSocket_1.27mm +PinSocket_2x05_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x05, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x05 1.27mm double row +0 +10 +10 +Connector_PinSocket_1.27mm +PinSocket_2x06_P1.27mm_Horizontal +Through hole angled socket strip, 2x06, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x06 1.27mm double row +0 +12 +12 +Connector_PinSocket_1.27mm +PinSocket_2x06_P1.27mm_Vertical +Through hole straight socket strip, 2x06, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x06 1.27mm double row +0 +12 +12 +Connector_PinSocket_1.27mm +PinSocket_2x06_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x06, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x06 1.27mm double row +0 +12 +12 +Connector_PinSocket_1.27mm +PinSocket_2x07_P1.27mm_Horizontal +Through hole angled socket strip, 2x07, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x07 1.27mm double row +0 +14 +14 +Connector_PinSocket_1.27mm +PinSocket_2x07_P1.27mm_Vertical +Through hole straight socket strip, 2x07, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x07 1.27mm double row +0 +14 +14 +Connector_PinSocket_1.27mm +PinSocket_2x07_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x07, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x07 1.27mm double row +0 +14 +14 +Connector_PinSocket_1.27mm +PinSocket_2x08_P1.27mm_Horizontal +Through hole angled socket strip, 2x08, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x08 1.27mm double row +0 +16 +16 +Connector_PinSocket_1.27mm +PinSocket_2x08_P1.27mm_Vertical +Through hole straight socket strip, 2x08, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x08 1.27mm double row +0 +16 +16 +Connector_PinSocket_1.27mm +PinSocket_2x08_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x08, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x08 1.27mm double row +0 +16 +16 +Connector_PinSocket_1.27mm +PinSocket_2x09_P1.27mm_Horizontal +Through hole angled socket strip, 2x09, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x09 1.27mm double row +0 +18 +18 +Connector_PinSocket_1.27mm +PinSocket_2x09_P1.27mm_Vertical +Through hole straight socket strip, 2x09, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x09 1.27mm double row +0 +18 +18 +Connector_PinSocket_1.27mm +PinSocket_2x09_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x09, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x09 1.27mm double row +0 +18 +18 +Connector_PinSocket_1.27mm +PinSocket_2x10_P1.27mm_Horizontal +Through hole angled socket strip, 2x10, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x10 1.27mm double row +0 +20 +20 +Connector_PinSocket_1.27mm +PinSocket_2x10_P1.27mm_Vertical +Through hole straight socket strip, 2x10, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x10 1.27mm double row +0 +20 +20 +Connector_PinSocket_1.27mm +PinSocket_2x10_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x10, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x10 1.27mm double row +0 +20 +20 +Connector_PinSocket_1.27mm +PinSocket_2x11_P1.27mm_Horizontal +Through hole angled socket strip, 2x11, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x11 1.27mm double row +0 +22 +22 +Connector_PinSocket_1.27mm +PinSocket_2x11_P1.27mm_Vertical +Through hole straight socket strip, 2x11, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x11 1.27mm double row +0 +22 +22 +Connector_PinSocket_1.27mm +PinSocket_2x11_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x11, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x11 1.27mm double row +0 +22 +22 +Connector_PinSocket_1.27mm +PinSocket_2x12_P1.27mm_Horizontal +Through hole angled socket strip, 2x12, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x12 1.27mm double row +0 +24 +24 +Connector_PinSocket_1.27mm +PinSocket_2x12_P1.27mm_Vertical +Through hole straight socket strip, 2x12, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x12 1.27mm double row +0 +24 +24 +Connector_PinSocket_1.27mm +PinSocket_2x12_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x12, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x12 1.27mm double row +0 +24 +24 +Connector_PinSocket_1.27mm +PinSocket_2x13_P1.27mm_Horizontal +Through hole angled socket strip, 2x13, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x13 1.27mm double row +0 +26 +26 +Connector_PinSocket_1.27mm +PinSocket_2x13_P1.27mm_Vertical +Through hole straight socket strip, 2x13, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x13 1.27mm double row +0 +26 +26 +Connector_PinSocket_1.27mm +PinSocket_2x13_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x13, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x13 1.27mm double row +0 +26 +26 +Connector_PinSocket_1.27mm +PinSocket_2x14_P1.27mm_Horizontal +Through hole angled socket strip, 2x14, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x14 1.27mm double row +0 +28 +28 +Connector_PinSocket_1.27mm +PinSocket_2x14_P1.27mm_Vertical +Through hole straight socket strip, 2x14, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x14 1.27mm double row +0 +28 +28 +Connector_PinSocket_1.27mm +PinSocket_2x14_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x14, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x14 1.27mm double row +0 +28 +28 +Connector_PinSocket_1.27mm +PinSocket_2x15_P1.27mm_Horizontal +Through hole angled socket strip, 2x15, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x15 1.27mm double row +0 +30 +30 +Connector_PinSocket_1.27mm +PinSocket_2x15_P1.27mm_Vertical +Through hole straight socket strip, 2x15, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x15 1.27mm double row +0 +30 +30 +Connector_PinSocket_1.27mm +PinSocket_2x15_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x15, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x15 1.27mm double row +0 +30 +30 +Connector_PinSocket_1.27mm +PinSocket_2x16_P1.27mm_Horizontal +Through hole angled socket strip, 2x16, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x16 1.27mm double row +0 +32 +32 +Connector_PinSocket_1.27mm +PinSocket_2x16_P1.27mm_Vertical +Through hole straight socket strip, 2x16, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x16 1.27mm double row +0 +32 +32 +Connector_PinSocket_1.27mm +PinSocket_2x16_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x16, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x16 1.27mm double row +0 +32 +32 +Connector_PinSocket_1.27mm +PinSocket_2x17_P1.27mm_Horizontal +Through hole angled socket strip, 2x17, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x17 1.27mm double row +0 +34 +34 +Connector_PinSocket_1.27mm +PinSocket_2x17_P1.27mm_Vertical +Through hole straight socket strip, 2x17, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x17 1.27mm double row +0 +34 +34 +Connector_PinSocket_1.27mm +PinSocket_2x17_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x17, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x17 1.27mm double row +0 +34 +34 +Connector_PinSocket_1.27mm +PinSocket_2x18_P1.27mm_Horizontal +Through hole angled socket strip, 2x18, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x18 1.27mm double row +0 +36 +36 +Connector_PinSocket_1.27mm +PinSocket_2x18_P1.27mm_Vertical +Through hole straight socket strip, 2x18, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x18 1.27mm double row +0 +36 +36 +Connector_PinSocket_1.27mm +PinSocket_2x18_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x18, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x18 1.27mm double row +0 +36 +36 +Connector_PinSocket_1.27mm +PinSocket_2x19_P1.27mm_Horizontal +Through hole angled socket strip, 2x19, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x19 1.27mm double row +0 +38 +38 +Connector_PinSocket_1.27mm +PinSocket_2x19_P1.27mm_Vertical +Through hole straight socket strip, 2x19, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x19 1.27mm double row +0 +38 +38 +Connector_PinSocket_1.27mm +PinSocket_2x19_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x19, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x19 1.27mm double row +0 +38 +38 +Connector_PinSocket_1.27mm +PinSocket_2x20_P1.27mm_Horizontal +Through hole angled socket strip, 2x20, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x20 1.27mm double row +0 +40 +40 +Connector_PinSocket_1.27mm +PinSocket_2x20_P1.27mm_Vertical +Through hole straight socket strip, 2x20, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x20 1.27mm double row +0 +40 +40 +Connector_PinSocket_1.27mm +PinSocket_2x20_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x20, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x20 1.27mm double row +0 +40 +40 +Connector_PinSocket_1.27mm +PinSocket_2x21_P1.27mm_Horizontal +Through hole angled socket strip, 2x21, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x21 1.27mm double row +0 +42 +42 +Connector_PinSocket_1.27mm +PinSocket_2x21_P1.27mm_Vertical +Through hole straight socket strip, 2x21, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x21 1.27mm double row +0 +42 +42 +Connector_PinSocket_1.27mm +PinSocket_2x21_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x21, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x21 1.27mm double row +0 +42 +42 +Connector_PinSocket_1.27mm +PinSocket_2x22_P1.27mm_Horizontal +Through hole angled socket strip, 2x22, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x22 1.27mm double row +0 +44 +44 +Connector_PinSocket_1.27mm +PinSocket_2x22_P1.27mm_Vertical +Through hole straight socket strip, 2x22, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x22 1.27mm double row +0 +44 +44 +Connector_PinSocket_1.27mm +PinSocket_2x22_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x22, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x22 1.27mm double row +0 +44 +44 +Connector_PinSocket_1.27mm +PinSocket_2x23_P1.27mm_Horizontal +Through hole angled socket strip, 2x23, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x23 1.27mm double row +0 +46 +46 +Connector_PinSocket_1.27mm +PinSocket_2x23_P1.27mm_Vertical +Through hole straight socket strip, 2x23, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x23 1.27mm double row +0 +46 +46 +Connector_PinSocket_1.27mm +PinSocket_2x23_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x23, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x23 1.27mm double row +0 +46 +46 +Connector_PinSocket_1.27mm +PinSocket_2x24_P1.27mm_Horizontal +Through hole angled socket strip, 2x24, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x24 1.27mm double row +0 +48 +48 +Connector_PinSocket_1.27mm +PinSocket_2x24_P1.27mm_Vertical +Through hole straight socket strip, 2x24, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x24 1.27mm double row +0 +48 +48 +Connector_PinSocket_1.27mm +PinSocket_2x24_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x24, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x24 1.27mm double row +0 +48 +48 +Connector_PinSocket_1.27mm +PinSocket_2x25_P1.27mm_Horizontal +Through hole angled socket strip, 2x25, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x25 1.27mm double row +0 +50 +50 +Connector_PinSocket_1.27mm +PinSocket_2x25_P1.27mm_Vertical +Through hole straight socket strip, 2x25, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x25 1.27mm double row +0 +50 +50 +Connector_PinSocket_1.27mm +PinSocket_2x25_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x25, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x25 1.27mm double row +0 +50 +50 +Connector_PinSocket_1.27mm +PinSocket_2x26_P1.27mm_Horizontal +Through hole angled socket strip, 2x26, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x26 1.27mm double row +0 +52 +52 +Connector_PinSocket_1.27mm +PinSocket_2x26_P1.27mm_Vertical +Through hole straight socket strip, 2x26, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x26 1.27mm double row +0 +52 +52 +Connector_PinSocket_1.27mm +PinSocket_2x26_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x26, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x26 1.27mm double row +0 +52 +52 +Connector_PinSocket_1.27mm +PinSocket_2x27_P1.27mm_Horizontal +Through hole angled socket strip, 2x27, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x27 1.27mm double row +0 +54 +54 +Connector_PinSocket_1.27mm +PinSocket_2x27_P1.27mm_Vertical +Through hole straight socket strip, 2x27, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x27 1.27mm double row +0 +54 +54 +Connector_PinSocket_1.27mm +PinSocket_2x27_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x27, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x27 1.27mm double row +0 +54 +54 +Connector_PinSocket_1.27mm +PinSocket_2x28_P1.27mm_Horizontal +Through hole angled socket strip, 2x28, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x28 1.27mm double row +0 +56 +56 +Connector_PinSocket_1.27mm +PinSocket_2x28_P1.27mm_Vertical +Through hole straight socket strip, 2x28, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x28 1.27mm double row +0 +56 +56 +Connector_PinSocket_1.27mm +PinSocket_2x28_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x28, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x28 1.27mm double row +0 +56 +56 +Connector_PinSocket_1.27mm +PinSocket_2x29_P1.27mm_Horizontal +Through hole angled socket strip, 2x29, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x29 1.27mm double row +0 +58 +58 +Connector_PinSocket_1.27mm +PinSocket_2x29_P1.27mm_Vertical +Through hole straight socket strip, 2x29, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x29 1.27mm double row +0 +58 +58 +Connector_PinSocket_1.27mm +PinSocket_2x29_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x29, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x29 1.27mm double row +0 +58 +58 +Connector_PinSocket_1.27mm +PinSocket_2x30_P1.27mm_Horizontal +Through hole angled socket strip, 2x30, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x30 1.27mm double row +0 +60 +60 +Connector_PinSocket_1.27mm +PinSocket_2x30_P1.27mm_Vertical +Through hole straight socket strip, 2x30, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x30 1.27mm double row +0 +60 +60 +Connector_PinSocket_1.27mm +PinSocket_2x30_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x30, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x30 1.27mm double row +0 +60 +60 +Connector_PinSocket_1.27mm +PinSocket_2x31_P1.27mm_Horizontal +Through hole angled socket strip, 2x31, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x31 1.27mm double row +0 +62 +62 +Connector_PinSocket_1.27mm +PinSocket_2x31_P1.27mm_Vertical +Through hole straight socket strip, 2x31, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x31 1.27mm double row +0 +62 +62 +Connector_PinSocket_1.27mm +PinSocket_2x31_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x31, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x31 1.27mm double row +0 +62 +62 +Connector_PinSocket_1.27mm +PinSocket_2x32_P1.27mm_Horizontal +Through hole angled socket strip, 2x32, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x32 1.27mm double row +0 +64 +64 +Connector_PinSocket_1.27mm +PinSocket_2x32_P1.27mm_Vertical +Through hole straight socket strip, 2x32, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x32 1.27mm double row +0 +64 +64 +Connector_PinSocket_1.27mm +PinSocket_2x32_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x32, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x32 1.27mm double row +0 +64 +64 +Connector_PinSocket_1.27mm +PinSocket_2x33_P1.27mm_Horizontal +Through hole angled socket strip, 2x33, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x33 1.27mm double row +0 +66 +66 +Connector_PinSocket_1.27mm +PinSocket_2x33_P1.27mm_Vertical +Through hole straight socket strip, 2x33, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x33 1.27mm double row +0 +66 +66 +Connector_PinSocket_1.27mm +PinSocket_2x33_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x33, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x33 1.27mm double row +0 +66 +66 +Connector_PinSocket_1.27mm +PinSocket_2x34_P1.27mm_Horizontal +Through hole angled socket strip, 2x34, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x34 1.27mm double row +0 +68 +68 +Connector_PinSocket_1.27mm +PinSocket_2x34_P1.27mm_Vertical +Through hole straight socket strip, 2x34, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x34 1.27mm double row +0 +68 +68 +Connector_PinSocket_1.27mm +PinSocket_2x34_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x34, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x34 1.27mm double row +0 +68 +68 +Connector_PinSocket_1.27mm +PinSocket_2x35_P1.27mm_Horizontal +Through hole angled socket strip, 2x35, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x35 1.27mm double row +0 +70 +70 +Connector_PinSocket_1.27mm +PinSocket_2x35_P1.27mm_Vertical +Through hole straight socket strip, 2x35, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x35 1.27mm double row +0 +70 +70 +Connector_PinSocket_1.27mm +PinSocket_2x35_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x35, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x35 1.27mm double row +0 +70 +70 +Connector_PinSocket_1.27mm +PinSocket_2x36_P1.27mm_Horizontal +Through hole angled socket strip, 2x36, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x36 1.27mm double row +0 +72 +72 +Connector_PinSocket_1.27mm +PinSocket_2x36_P1.27mm_Vertical +Through hole straight socket strip, 2x36, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x36 1.27mm double row +0 +72 +72 +Connector_PinSocket_1.27mm +PinSocket_2x36_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x36, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x36 1.27mm double row +0 +72 +72 +Connector_PinSocket_1.27mm +PinSocket_2x37_P1.27mm_Horizontal +Through hole angled socket strip, 2x37, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x37 1.27mm double row +0 +74 +74 +Connector_PinSocket_1.27mm +PinSocket_2x37_P1.27mm_Vertical +Through hole straight socket strip, 2x37, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x37 1.27mm double row +0 +74 +74 +Connector_PinSocket_1.27mm +PinSocket_2x37_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x37, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x37 1.27mm double row +0 +74 +74 +Connector_PinSocket_1.27mm +PinSocket_2x38_P1.27mm_Horizontal +Through hole angled socket strip, 2x38, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x38 1.27mm double row +0 +76 +76 +Connector_PinSocket_1.27mm +PinSocket_2x38_P1.27mm_Vertical +Through hole straight socket strip, 2x38, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x38 1.27mm double row +0 +76 +76 +Connector_PinSocket_1.27mm +PinSocket_2x38_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x38, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x38 1.27mm double row +0 +76 +76 +Connector_PinSocket_1.27mm +PinSocket_2x39_P1.27mm_Horizontal +Through hole angled socket strip, 2x39, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x39 1.27mm double row +0 +78 +78 +Connector_PinSocket_1.27mm +PinSocket_2x39_P1.27mm_Vertical +Through hole straight socket strip, 2x39, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x39 1.27mm double row +0 +78 +78 +Connector_PinSocket_1.27mm +PinSocket_2x39_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x39, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x39 1.27mm double row +0 +78 +78 +Connector_PinSocket_1.27mm +PinSocket_2x40_P1.27mm_Horizontal +Through hole angled socket strip, 2x40, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x40 1.27mm double row +0 +80 +80 +Connector_PinSocket_1.27mm +PinSocket_2x40_P1.27mm_Vertical +Through hole straight socket strip, 2x40, 1.27mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x40 1.27mm double row +0 +80 +80 +Connector_PinSocket_1.27mm +PinSocket_2x40_P1.27mm_Vertical_SMD +surface-mounted straight socket strip, 2x40, 1.27mm pitch, double cols (from Kicad 4.0.7!), script generated +Surface mounted socket strip SMD 2x40 1.27mm double row +0 +80 +80 +Connector_PinSocket_1.27mm +PinSocket_2x41_P1.27mm_Horizontal +Through hole angled socket strip, 2x41, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x41 1.27mm double row +0 +82 +82 +Connector_PinSocket_1.27mm +PinSocket_2x42_P1.27mm_Horizontal +Through hole angled socket strip, 2x42, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x42 1.27mm double row +0 +84 +84 +Connector_PinSocket_1.27mm +PinSocket_2x43_P1.27mm_Horizontal +Through hole angled socket strip, 2x43, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x43 1.27mm double row +0 +86 +86 +Connector_PinSocket_1.27mm +PinSocket_2x44_P1.27mm_Horizontal +Through hole angled socket strip, 2x44, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x44 1.27mm double row +0 +88 +88 +Connector_PinSocket_1.27mm +PinSocket_2x45_P1.27mm_Horizontal +Through hole angled socket strip, 2x45, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x45 1.27mm double row +0 +90 +90 +Connector_PinSocket_1.27mm +PinSocket_2x46_P1.27mm_Horizontal +Through hole angled socket strip, 2x46, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x46 1.27mm double row +0 +92 +92 +Connector_PinSocket_1.27mm +PinSocket_2x47_P1.27mm_Horizontal +Through hole angled socket strip, 2x47, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x47 1.27mm double row +0 +94 +94 +Connector_PinSocket_1.27mm +PinSocket_2x48_P1.27mm_Horizontal +Through hole angled socket strip, 2x48, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x48 1.27mm double row +0 +96 +96 +Connector_PinSocket_1.27mm +PinSocket_2x49_P1.27mm_Horizontal +Through hole angled socket strip, 2x49, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x49 1.27mm double row +0 +98 +98 +Connector_PinSocket_1.27mm +PinSocket_2x50_P1.27mm_Horizontal +Through hole angled socket strip, 2x50, 1.27mm pitch, 4.4mm socket length, double cols (https://gct.co/pdfjs/web/viewer.html?file=/Files/Drawings/BD091.pdf&t=1511594177220), script generated +Through hole angled socket strip THT 2x50 1.27mm double row +0 +100 +100 +Connector_PinSocket_2.00mm +PinSocket_1x01_P2.00mm_Horizontal +Through hole angled socket strip, 1x01, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x01 2.00mm single row +0 +1 +1 +Connector_PinSocket_2.00mm +PinSocket_1x01_P2.00mm_Vertical +Through hole straight socket strip, 1x01, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x01 2.00mm single row +0 +1 +1 +Connector_PinSocket_2.00mm +PinSocket_1x02_P2.00mm_Horizontal +Through hole angled socket strip, 1x02, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x02 2.00mm single row +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_1x02_P2.00mm_Vertical +Through hole straight socket strip, 1x02, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x02 2.00mm single row +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_1x02_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x02, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x02 2.00mm single row style1 pin1 left +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_1x02_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x02, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x02 2.00mm single row style2 pin1 right +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_1x03_P2.00mm_Horizontal +Through hole angled socket strip, 1x03, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x03 2.00mm single row +0 +3 +3 +Connector_PinSocket_2.00mm +PinSocket_1x03_P2.00mm_Vertical +Through hole straight socket strip, 1x03, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x03 2.00mm single row +0 +3 +3 +Connector_PinSocket_2.00mm +PinSocket_1x03_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x03, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x03 2.00mm single row style1 pin1 left +0 +3 +3 +Connector_PinSocket_2.00mm +PinSocket_1x03_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x03, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x03 2.00mm single row style2 pin1 right +0 +3 +3 +Connector_PinSocket_2.00mm +PinSocket_1x04_P2.00mm_Horizontal +Through hole angled socket strip, 1x04, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x04 2.00mm single row +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_1x04_P2.00mm_Vertical +Through hole straight socket strip, 1x04, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x04 2.00mm single row +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_1x04_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x04, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x04 2.00mm single row style1 pin1 left +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_1x04_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x04, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x04 2.00mm single row style2 pin1 right +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_1x05_P2.00mm_Horizontal +Through hole angled socket strip, 1x05, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x05 2.00mm single row +0 +5 +5 +Connector_PinSocket_2.00mm +PinSocket_1x05_P2.00mm_Vertical +Through hole straight socket strip, 1x05, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x05 2.00mm single row +0 +5 +5 +Connector_PinSocket_2.00mm +PinSocket_1x05_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x05, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x05 2.00mm single row style1 pin1 left +0 +5 +5 +Connector_PinSocket_2.00mm +PinSocket_1x05_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x05, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x05 2.00mm single row style2 pin1 right +0 +5 +5 +Connector_PinSocket_2.00mm +PinSocket_1x06_P2.00mm_Horizontal +Through hole angled socket strip, 1x06, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x06 2.00mm single row +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_1x06_P2.00mm_Vertical +Through hole straight socket strip, 1x06, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x06 2.00mm single row +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_1x06_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x06, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x06 2.00mm single row style1 pin1 left +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_1x06_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x06, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x06 2.00mm single row style2 pin1 right +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_1x07_P2.00mm_Horizontal +Through hole angled socket strip, 1x07, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x07 2.00mm single row +0 +7 +7 +Connector_PinSocket_2.00mm +PinSocket_1x07_P2.00mm_Vertical +Through hole straight socket strip, 1x07, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x07 2.00mm single row +0 +7 +7 +Connector_PinSocket_2.00mm +PinSocket_1x07_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x07, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x07 2.00mm single row style1 pin1 left +0 +7 +7 +Connector_PinSocket_2.00mm +PinSocket_1x07_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x07, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x07 2.00mm single row style2 pin1 right +0 +7 +7 +Connector_PinSocket_2.00mm +PinSocket_1x08_P2.00mm_Horizontal +Through hole angled socket strip, 1x08, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x08 2.00mm single row +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_1x08_P2.00mm_Vertical +Through hole straight socket strip, 1x08, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x08 2.00mm single row +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_1x08_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x08, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x08 2.00mm single row style1 pin1 left +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_1x08_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x08, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x08 2.00mm single row style2 pin1 right +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_1x09_P2.00mm_Horizontal +Through hole angled socket strip, 1x09, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x09 2.00mm single row +0 +9 +9 +Connector_PinSocket_2.00mm +PinSocket_1x09_P2.00mm_Vertical +Through hole straight socket strip, 1x09, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x09 2.00mm single row +0 +9 +9 +Connector_PinSocket_2.00mm +PinSocket_1x09_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x09, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x09 2.00mm single row style1 pin1 left +0 +9 +9 +Connector_PinSocket_2.00mm +PinSocket_1x09_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x09, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x09 2.00mm single row style2 pin1 right +0 +9 +9 +Connector_PinSocket_2.00mm +PinSocket_1x10_P2.00mm_Horizontal +Through hole angled socket strip, 1x10, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x10 2.00mm single row +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_1x10_P2.00mm_Vertical +Through hole straight socket strip, 1x10, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x10 2.00mm single row +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_1x10_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x10, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x10 2.00mm single row style1 pin1 left +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_1x10_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x10, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x10 2.00mm single row style2 pin1 right +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_1x11_P2.00mm_Horizontal +Through hole angled socket strip, 1x11, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x11 2.00mm single row +0 +11 +11 +Connector_PinSocket_2.00mm +PinSocket_1x11_P2.00mm_Vertical +Through hole straight socket strip, 1x11, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x11 2.00mm single row +0 +11 +11 +Connector_PinSocket_2.00mm +PinSocket_1x11_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x11, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x11 2.00mm single row style1 pin1 left +0 +11 +11 +Connector_PinSocket_2.00mm +PinSocket_1x11_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x11, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x11 2.00mm single row style2 pin1 right +0 +11 +11 +Connector_PinSocket_2.00mm +PinSocket_1x12_P2.00mm_Horizontal +Through hole angled socket strip, 1x12, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x12 2.00mm single row +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_1x12_P2.00mm_Vertical +Through hole straight socket strip, 1x12, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x12 2.00mm single row +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_1x12_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x12, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x12 2.00mm single row style1 pin1 left +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_1x12_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x12, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x12 2.00mm single row style2 pin1 right +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_1x13_P2.00mm_Horizontal +Through hole angled socket strip, 1x13, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x13 2.00mm single row +0 +13 +13 +Connector_PinSocket_2.00mm +PinSocket_1x13_P2.00mm_Vertical +Through hole straight socket strip, 1x13, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x13 2.00mm single row +0 +13 +13 +Connector_PinSocket_2.00mm +PinSocket_1x13_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x13, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x13 2.00mm single row style1 pin1 left +0 +13 +13 +Connector_PinSocket_2.00mm +PinSocket_1x13_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x13, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x13 2.00mm single row style2 pin1 right +0 +13 +13 +Connector_PinSocket_2.00mm +PinSocket_1x14_P2.00mm_Horizontal +Through hole angled socket strip, 1x14, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x14 2.00mm single row +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_1x14_P2.00mm_Vertical +Through hole straight socket strip, 1x14, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x14 2.00mm single row +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_1x14_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x14, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x14 2.00mm single row style1 pin1 left +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_1x14_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x14, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x14 2.00mm single row style2 pin1 right +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_1x15_P2.00mm_Horizontal +Through hole angled socket strip, 1x15, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x15 2.00mm single row +0 +15 +15 +Connector_PinSocket_2.00mm +PinSocket_1x15_P2.00mm_Vertical +Through hole straight socket strip, 1x15, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x15 2.00mm single row +0 +15 +15 +Connector_PinSocket_2.00mm +PinSocket_1x15_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x15, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x15 2.00mm single row style1 pin1 left +0 +15 +15 +Connector_PinSocket_2.00mm +PinSocket_1x15_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x15, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x15 2.00mm single row style2 pin1 right +0 +15 +15 +Connector_PinSocket_2.00mm +PinSocket_1x16_P2.00mm_Horizontal +Through hole angled socket strip, 1x16, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x16 2.00mm single row +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_1x16_P2.00mm_Vertical +Through hole straight socket strip, 1x16, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x16 2.00mm single row +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_1x16_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x16, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x16 2.00mm single row style1 pin1 left +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_1x16_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x16, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x16 2.00mm single row style2 pin1 right +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_1x17_P2.00mm_Horizontal +Through hole angled socket strip, 1x17, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x17 2.00mm single row +0 +17 +17 +Connector_PinSocket_2.00mm +PinSocket_1x17_P2.00mm_Vertical +Through hole straight socket strip, 1x17, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x17 2.00mm single row +0 +17 +17 +Connector_PinSocket_2.00mm +PinSocket_1x17_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x17, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x17 2.00mm single row style1 pin1 left +0 +17 +17 +Connector_PinSocket_2.00mm +PinSocket_1x17_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x17, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x17 2.00mm single row style2 pin1 right +0 +17 +17 +Connector_PinSocket_2.00mm +PinSocket_1x18_P2.00mm_Horizontal +Through hole angled socket strip, 1x18, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x18 2.00mm single row +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_1x18_P2.00mm_Vertical +Through hole straight socket strip, 1x18, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x18 2.00mm single row +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_1x18_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x18, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x18 2.00mm single row style1 pin1 left +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_1x18_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x18, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x18 2.00mm single row style2 pin1 right +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_1x19_P2.00mm_Horizontal +Through hole angled socket strip, 1x19, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x19 2.00mm single row +0 +19 +19 +Connector_PinSocket_2.00mm +PinSocket_1x19_P2.00mm_Vertical +Through hole straight socket strip, 1x19, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x19 2.00mm single row +0 +19 +19 +Connector_PinSocket_2.00mm +PinSocket_1x19_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x19, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x19 2.00mm single row style1 pin1 left +0 +19 +19 +Connector_PinSocket_2.00mm +PinSocket_1x19_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x19, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x19 2.00mm single row style2 pin1 right +0 +19 +19 +Connector_PinSocket_2.00mm +PinSocket_1x20_P2.00mm_Horizontal +Through hole angled socket strip, 1x20, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x20 2.00mm single row +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_1x20_P2.00mm_Vertical +Through hole straight socket strip, 1x20, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x20 2.00mm single row +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_1x20_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x20, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x20 2.00mm single row style1 pin1 left +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_1x20_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x20, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x20 2.00mm single row style2 pin1 right +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_1x21_P2.00mm_Horizontal +Through hole angled socket strip, 1x21, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x21 2.00mm single row +0 +21 +21 +Connector_PinSocket_2.00mm +PinSocket_1x21_P2.00mm_Vertical +Through hole straight socket strip, 1x21, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x21 2.00mm single row +0 +21 +21 +Connector_PinSocket_2.00mm +PinSocket_1x21_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x21, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x21 2.00mm single row style1 pin1 left +0 +21 +21 +Connector_PinSocket_2.00mm +PinSocket_1x21_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x21, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x21 2.00mm single row style2 pin1 right +0 +21 +21 +Connector_PinSocket_2.00mm +PinSocket_1x22_P2.00mm_Horizontal +Through hole angled socket strip, 1x22, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x22 2.00mm single row +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_1x22_P2.00mm_Vertical +Through hole straight socket strip, 1x22, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x22 2.00mm single row +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_1x22_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x22, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x22 2.00mm single row style1 pin1 left +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_1x22_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x22, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x22 2.00mm single row style2 pin1 right +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_1x23_P2.00mm_Horizontal +Through hole angled socket strip, 1x23, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x23 2.00mm single row +0 +23 +23 +Connector_PinSocket_2.00mm +PinSocket_1x23_P2.00mm_Vertical +Through hole straight socket strip, 1x23, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x23 2.00mm single row +0 +23 +23 +Connector_PinSocket_2.00mm +PinSocket_1x23_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x23, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x23 2.00mm single row style1 pin1 left +0 +23 +23 +Connector_PinSocket_2.00mm +PinSocket_1x23_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x23, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x23 2.00mm single row style2 pin1 right +0 +23 +23 +Connector_PinSocket_2.00mm +PinSocket_1x24_P2.00mm_Horizontal +Through hole angled socket strip, 1x24, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x24 2.00mm single row +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_1x24_P2.00mm_Vertical +Through hole straight socket strip, 1x24, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x24 2.00mm single row +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_1x24_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x24, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x24 2.00mm single row style1 pin1 left +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_1x24_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x24, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x24 2.00mm single row style2 pin1 right +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_1x25_P2.00mm_Horizontal +Through hole angled socket strip, 1x25, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x25 2.00mm single row +0 +25 +25 +Connector_PinSocket_2.00mm +PinSocket_1x25_P2.00mm_Vertical +Through hole straight socket strip, 1x25, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x25 2.00mm single row +0 +25 +25 +Connector_PinSocket_2.00mm +PinSocket_1x25_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x25, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x25 2.00mm single row style1 pin1 left +0 +25 +25 +Connector_PinSocket_2.00mm +PinSocket_1x25_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x25, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x25 2.00mm single row style2 pin1 right +0 +25 +25 +Connector_PinSocket_2.00mm +PinSocket_1x26_P2.00mm_Horizontal +Through hole angled socket strip, 1x26, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x26 2.00mm single row +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_1x26_P2.00mm_Vertical +Through hole straight socket strip, 1x26, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x26 2.00mm single row +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_1x26_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x26, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x26 2.00mm single row style1 pin1 left +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_1x26_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x26, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x26 2.00mm single row style2 pin1 right +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_1x27_P2.00mm_Horizontal +Through hole angled socket strip, 1x27, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x27 2.00mm single row +0 +27 +27 +Connector_PinSocket_2.00mm +PinSocket_1x27_P2.00mm_Vertical +Through hole straight socket strip, 1x27, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x27 2.00mm single row +0 +27 +27 +Connector_PinSocket_2.00mm +PinSocket_1x27_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x27, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x27 2.00mm single row style1 pin1 left +0 +27 +27 +Connector_PinSocket_2.00mm +PinSocket_1x27_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x27, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x27 2.00mm single row style2 pin1 right +0 +27 +27 +Connector_PinSocket_2.00mm +PinSocket_1x28_P2.00mm_Horizontal +Through hole angled socket strip, 1x28, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x28 2.00mm single row +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_1x28_P2.00mm_Vertical +Through hole straight socket strip, 1x28, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x28 2.00mm single row +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_1x28_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x28, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x28 2.00mm single row style1 pin1 left +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_1x28_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x28, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x28 2.00mm single row style2 pin1 right +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_1x29_P2.00mm_Horizontal +Through hole angled socket strip, 1x29, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x29 2.00mm single row +0 +29 +29 +Connector_PinSocket_2.00mm +PinSocket_1x29_P2.00mm_Vertical +Through hole straight socket strip, 1x29, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x29 2.00mm single row +0 +29 +29 +Connector_PinSocket_2.00mm +PinSocket_1x29_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x29, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x29 2.00mm single row style1 pin1 left +0 +29 +29 +Connector_PinSocket_2.00mm +PinSocket_1x29_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x29, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x29 2.00mm single row style2 pin1 right +0 +29 +29 +Connector_PinSocket_2.00mm +PinSocket_1x30_P2.00mm_Horizontal +Through hole angled socket strip, 1x30, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x30 2.00mm single row +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_1x30_P2.00mm_Vertical +Through hole straight socket strip, 1x30, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x30 2.00mm single row +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_1x30_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x30, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x30 2.00mm single row style1 pin1 left +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_1x30_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x30, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x30 2.00mm single row style2 pin1 right +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_1x31_P2.00mm_Horizontal +Through hole angled socket strip, 1x31, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x31 2.00mm single row +0 +31 +31 +Connector_PinSocket_2.00mm +PinSocket_1x31_P2.00mm_Vertical +Through hole straight socket strip, 1x31, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x31 2.00mm single row +0 +31 +31 +Connector_PinSocket_2.00mm +PinSocket_1x31_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x31, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x31 2.00mm single row style1 pin1 left +0 +31 +31 +Connector_PinSocket_2.00mm +PinSocket_1x31_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x31, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x31 2.00mm single row style2 pin1 right +0 +31 +31 +Connector_PinSocket_2.00mm +PinSocket_1x32_P2.00mm_Horizontal +Through hole angled socket strip, 1x32, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x32 2.00mm single row +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_1x32_P2.00mm_Vertical +Through hole straight socket strip, 1x32, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x32 2.00mm single row +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_1x32_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x32, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x32 2.00mm single row style1 pin1 left +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_1x32_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x32, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x32 2.00mm single row style2 pin1 right +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_1x33_P2.00mm_Horizontal +Through hole angled socket strip, 1x33, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x33 2.00mm single row +0 +33 +33 +Connector_PinSocket_2.00mm +PinSocket_1x33_P2.00mm_Vertical +Through hole straight socket strip, 1x33, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x33 2.00mm single row +0 +33 +33 +Connector_PinSocket_2.00mm +PinSocket_1x33_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x33, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x33 2.00mm single row style1 pin1 left +0 +33 +33 +Connector_PinSocket_2.00mm +PinSocket_1x33_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x33, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x33 2.00mm single row style2 pin1 right +0 +33 +33 +Connector_PinSocket_2.00mm +PinSocket_1x34_P2.00mm_Horizontal +Through hole angled socket strip, 1x34, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x34 2.00mm single row +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_1x34_P2.00mm_Vertical +Through hole straight socket strip, 1x34, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x34 2.00mm single row +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_1x34_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x34, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x34 2.00mm single row style1 pin1 left +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_1x34_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x34, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x34 2.00mm single row style2 pin1 right +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_1x35_P2.00mm_Horizontal +Through hole angled socket strip, 1x35, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x35 2.00mm single row +0 +35 +35 +Connector_PinSocket_2.00mm +PinSocket_1x35_P2.00mm_Vertical +Through hole straight socket strip, 1x35, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x35 2.00mm single row +0 +35 +35 +Connector_PinSocket_2.00mm +PinSocket_1x35_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x35, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x35 2.00mm single row style1 pin1 left +0 +35 +35 +Connector_PinSocket_2.00mm +PinSocket_1x35_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x35, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x35 2.00mm single row style2 pin1 right +0 +35 +35 +Connector_PinSocket_2.00mm +PinSocket_1x36_P2.00mm_Horizontal +Through hole angled socket strip, 1x36, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x36 2.00mm single row +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_1x36_P2.00mm_Vertical +Through hole straight socket strip, 1x36, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x36 2.00mm single row +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_1x36_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x36, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x36 2.00mm single row style1 pin1 left +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_1x36_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x36, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x36 2.00mm single row style2 pin1 right +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_1x37_P2.00mm_Horizontal +Through hole angled socket strip, 1x37, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x37 2.00mm single row +0 +37 +37 +Connector_PinSocket_2.00mm +PinSocket_1x37_P2.00mm_Vertical +Through hole straight socket strip, 1x37, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x37 2.00mm single row +0 +37 +37 +Connector_PinSocket_2.00mm +PinSocket_1x37_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x37, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x37 2.00mm single row style1 pin1 left +0 +37 +37 +Connector_PinSocket_2.00mm +PinSocket_1x37_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x37, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x37 2.00mm single row style2 pin1 right +0 +37 +37 +Connector_PinSocket_2.00mm +PinSocket_1x38_P2.00mm_Horizontal +Through hole angled socket strip, 1x38, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x38 2.00mm single row +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_1x38_P2.00mm_Vertical +Through hole straight socket strip, 1x38, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x38 2.00mm single row +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_1x38_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x38, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x38 2.00mm single row style1 pin1 left +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_1x38_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x38, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x38 2.00mm single row style2 pin1 right +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_1x39_P2.00mm_Horizontal +Through hole angled socket strip, 1x39, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x39 2.00mm single row +0 +39 +39 +Connector_PinSocket_2.00mm +PinSocket_1x39_P2.00mm_Vertical +Through hole straight socket strip, 1x39, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x39 2.00mm single row +0 +39 +39 +Connector_PinSocket_2.00mm +PinSocket_1x39_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x39, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x39 2.00mm single row style1 pin1 left +0 +39 +39 +Connector_PinSocket_2.00mm +PinSocket_1x39_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x39, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x39 2.00mm single row style2 pin1 right +0 +39 +39 +Connector_PinSocket_2.00mm +PinSocket_1x40_P2.00mm_Horizontal +Through hole angled socket strip, 1x40, 2.00mm pitch, 6.35mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x40 2.00mm single row +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_1x40_P2.00mm_Vertical +Through hole straight socket strip, 1x40, 2.00mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x40 2.00mm single row +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_1x40_P2.00mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x40, 2.00mm pitch, single row, style 1 (pin 1 left) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x40 2.00mm single row style1 pin1 left +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_1x40_P2.00mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x40, 2.00mm pitch, single row, style 2 (pin 1 right) (https://www.jayconsystems.com/fileuploader/download/download/?d=1&file=custom%2Fupload%2FFile-1375728122.pdf), script generated +Surface mounted socket strip SMD 1x40 2.00mm single row style2 pin1 right +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_2x01_P2.00mm_Horizontal +Through hole angled socket strip, 2x01, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x01 2.00mm double row +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_2x01_P2.00mm_Vertical +Through hole straight socket strip, 2x01, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x01 2.00mm double row +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_2x01_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x01, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x01 2.00mm double row +0 +2 +2 +Connector_PinSocket_2.00mm +PinSocket_2x02_P2.00mm_Horizontal +Through hole angled socket strip, 2x02, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x02 2.00mm double row +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_2x02_P2.00mm_Vertical +Through hole straight socket strip, 2x02, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x02 2.00mm double row +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_2x02_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x02, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x02 2.00mm double row +0 +4 +4 +Connector_PinSocket_2.00mm +PinSocket_2x03_P2.00mm_Horizontal +Through hole angled socket strip, 2x03, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x03 2.00mm double row +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_2x03_P2.00mm_Vertical +Through hole straight socket strip, 2x03, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x03 2.00mm double row +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_2x03_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x03, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x03 2.00mm double row +0 +6 +6 +Connector_PinSocket_2.00mm +PinSocket_2x04_P2.00mm_Horizontal +Through hole angled socket strip, 2x04, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x04 2.00mm double row +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_2x04_P2.00mm_Vertical +Through hole straight socket strip, 2x04, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x04 2.00mm double row +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_2x04_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x04, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x04 2.00mm double row +0 +8 +8 +Connector_PinSocket_2.00mm +PinSocket_2x05_P2.00mm_Horizontal +Through hole angled socket strip, 2x05, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x05 2.00mm double row +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_2x05_P2.00mm_Vertical +Through hole straight socket strip, 2x05, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x05 2.00mm double row +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_2x05_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x05, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x05 2.00mm double row +0 +10 +10 +Connector_PinSocket_2.00mm +PinSocket_2x06_P2.00mm_Horizontal +Through hole angled socket strip, 2x06, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x06 2.00mm double row +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_2x06_P2.00mm_Vertical +Through hole straight socket strip, 2x06, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x06 2.00mm double row +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_2x06_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x06, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x06 2.00mm double row +0 +12 +12 +Connector_PinSocket_2.00mm +PinSocket_2x07_P2.00mm_Horizontal +Through hole angled socket strip, 2x07, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x07 2.00mm double row +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_2x07_P2.00mm_Vertical +Through hole straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x07 2.00mm double row +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_2x07_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x07, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x07 2.00mm double row +0 +14 +14 +Connector_PinSocket_2.00mm +PinSocket_2x08_P2.00mm_Horizontal +Through hole angled socket strip, 2x08, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x08 2.00mm double row +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_2x08_P2.00mm_Vertical +Through hole straight socket strip, 2x08, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x08 2.00mm double row +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_2x08_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x08, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x08 2.00mm double row +0 +16 +16 +Connector_PinSocket_2.00mm +PinSocket_2x09_P2.00mm_Horizontal +Through hole angled socket strip, 2x09, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x09 2.00mm double row +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_2x09_P2.00mm_Vertical +Through hole straight socket strip, 2x09, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x09 2.00mm double row +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_2x09_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x09, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x09 2.00mm double row +0 +18 +18 +Connector_PinSocket_2.00mm +PinSocket_2x10_P2.00mm_Horizontal +Through hole angled socket strip, 2x10, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x10 2.00mm double row +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_2x10_P2.00mm_Vertical +Through hole straight socket strip, 2x10, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x10 2.00mm double row +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_2x10_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x10, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x10 2.00mm double row +0 +20 +20 +Connector_PinSocket_2.00mm +PinSocket_2x11_P2.00mm_Horizontal +Through hole angled socket strip, 2x11, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x11 2.00mm double row +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_2x11_P2.00mm_Vertical +Through hole straight socket strip, 2x11, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x11 2.00mm double row +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_2x11_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x11, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x11 2.00mm double row +0 +22 +22 +Connector_PinSocket_2.00mm +PinSocket_2x12_P2.00mm_Horizontal +Through hole angled socket strip, 2x12, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x12 2.00mm double row +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_2x12_P2.00mm_Vertical +Through hole straight socket strip, 2x12, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x12 2.00mm double row +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_2x12_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x12, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x12 2.00mm double row +0 +24 +24 +Connector_PinSocket_2.00mm +PinSocket_2x13_P2.00mm_Horizontal +Through hole angled socket strip, 2x13, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x13 2.00mm double row +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_2x13_P2.00mm_Vertical +Through hole straight socket strip, 2x13, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x13 2.00mm double row +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_2x13_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x13, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x13 2.00mm double row +0 +26 +26 +Connector_PinSocket_2.00mm +PinSocket_2x14_P2.00mm_Horizontal +Through hole angled socket strip, 2x14, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x14 2.00mm double row +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_2x14_P2.00mm_Vertical +Through hole straight socket strip, 2x14, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x14 2.00mm double row +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_2x14_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x14, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x14 2.00mm double row +0 +28 +28 +Connector_PinSocket_2.00mm +PinSocket_2x15_P2.00mm_Horizontal +Through hole angled socket strip, 2x15, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x15 2.00mm double row +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_2x15_P2.00mm_Vertical +Through hole straight socket strip, 2x15, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x15 2.00mm double row +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_2x15_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x15, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x15 2.00mm double row +0 +30 +30 +Connector_PinSocket_2.00mm +PinSocket_2x16_P2.00mm_Horizontal +Through hole angled socket strip, 2x16, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x16 2.00mm double row +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_2x16_P2.00mm_Vertical +Through hole straight socket strip, 2x16, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x16 2.00mm double row +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_2x16_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x16, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x16 2.00mm double row +0 +32 +32 +Connector_PinSocket_2.00mm +PinSocket_2x17_P2.00mm_Horizontal +Through hole angled socket strip, 2x17, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x17 2.00mm double row +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_2x17_P2.00mm_Vertical +Through hole straight socket strip, 2x17, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x17 2.00mm double row +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_2x17_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x17, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x17 2.00mm double row +0 +34 +34 +Connector_PinSocket_2.00mm +PinSocket_2x18_P2.00mm_Horizontal +Through hole angled socket strip, 2x18, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x18 2.00mm double row +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_2x18_P2.00mm_Vertical +Through hole straight socket strip, 2x18, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x18 2.00mm double row +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_2x18_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x18, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x18 2.00mm double row +0 +36 +36 +Connector_PinSocket_2.00mm +PinSocket_2x19_P2.00mm_Horizontal +Through hole angled socket strip, 2x19, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x19 2.00mm double row +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_2x19_P2.00mm_Vertical +Through hole straight socket strip, 2x19, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x19 2.00mm double row +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_2x19_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x19, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x19 2.00mm double row +0 +38 +38 +Connector_PinSocket_2.00mm +PinSocket_2x20_P2.00mm_Horizontal +Through hole angled socket strip, 2x20, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x20 2.00mm double row +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_2x20_P2.00mm_Vertical +Through hole straight socket strip, 2x20, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x20 2.00mm double row +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_2x20_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x20, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x20 2.00mm double row +0 +40 +40 +Connector_PinSocket_2.00mm +PinSocket_2x21_P2.00mm_Horizontal +Through hole angled socket strip, 2x21, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x21 2.00mm double row +0 +42 +42 +Connector_PinSocket_2.00mm +PinSocket_2x21_P2.00mm_Vertical +Through hole straight socket strip, 2x21, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x21 2.00mm double row +0 +42 +42 +Connector_PinSocket_2.00mm +PinSocket_2x21_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x21, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x21 2.00mm double row +0 +42 +42 +Connector_PinSocket_2.00mm +PinSocket_2x22_P2.00mm_Horizontal +Through hole angled socket strip, 2x22, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x22 2.00mm double row +0 +44 +44 +Connector_PinSocket_2.00mm +PinSocket_2x22_P2.00mm_Vertical +Through hole straight socket strip, 2x22, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x22 2.00mm double row +0 +44 +44 +Connector_PinSocket_2.00mm +PinSocket_2x22_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x22, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x22 2.00mm double row +0 +44 +44 +Connector_PinSocket_2.00mm +PinSocket_2x23_P2.00mm_Horizontal +Through hole angled socket strip, 2x23, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x23 2.00mm double row +0 +46 +46 +Connector_PinSocket_2.00mm +PinSocket_2x23_P2.00mm_Vertical +Through hole straight socket strip, 2x23, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x23 2.00mm double row +0 +46 +46 +Connector_PinSocket_2.00mm +PinSocket_2x23_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x23, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x23 2.00mm double row +0 +46 +46 +Connector_PinSocket_2.00mm +PinSocket_2x24_P2.00mm_Horizontal +Through hole angled socket strip, 2x24, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x24 2.00mm double row +0 +48 +48 +Connector_PinSocket_2.00mm +PinSocket_2x24_P2.00mm_Vertical +Through hole straight socket strip, 2x24, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x24 2.00mm double row +0 +48 +48 +Connector_PinSocket_2.00mm +PinSocket_2x24_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x24, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x24 2.00mm double row +0 +48 +48 +Connector_PinSocket_2.00mm +PinSocket_2x25_P2.00mm_Horizontal +Through hole angled socket strip, 2x25, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x25 2.00mm double row +0 +50 +50 +Connector_PinSocket_2.00mm +PinSocket_2x25_P2.00mm_Vertical +Through hole straight socket strip, 2x25, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x25 2.00mm double row +0 +50 +50 +Connector_PinSocket_2.00mm +PinSocket_2x25_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x25, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x25 2.00mm double row +0 +50 +50 +Connector_PinSocket_2.00mm +PinSocket_2x26_P2.00mm_Horizontal +Through hole angled socket strip, 2x26, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x26 2.00mm double row +0 +52 +52 +Connector_PinSocket_2.00mm +PinSocket_2x26_P2.00mm_Vertical +Through hole straight socket strip, 2x26, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x26 2.00mm double row +0 +52 +52 +Connector_PinSocket_2.00mm +PinSocket_2x26_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x26, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x26 2.00mm double row +0 +52 +52 +Connector_PinSocket_2.00mm +PinSocket_2x27_P2.00mm_Horizontal +Through hole angled socket strip, 2x27, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x27 2.00mm double row +0 +54 +54 +Connector_PinSocket_2.00mm +PinSocket_2x27_P2.00mm_Vertical +Through hole straight socket strip, 2x27, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x27 2.00mm double row +0 +54 +54 +Connector_PinSocket_2.00mm +PinSocket_2x27_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x27, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x27 2.00mm double row +0 +54 +54 +Connector_PinSocket_2.00mm +PinSocket_2x28_P2.00mm_Horizontal +Through hole angled socket strip, 2x28, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x28 2.00mm double row +0 +56 +56 +Connector_PinSocket_2.00mm +PinSocket_2x28_P2.00mm_Vertical +Through hole straight socket strip, 2x28, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x28 2.00mm double row +0 +56 +56 +Connector_PinSocket_2.00mm +PinSocket_2x28_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x28, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x28 2.00mm double row +0 +56 +56 +Connector_PinSocket_2.00mm +PinSocket_2x29_P2.00mm_Horizontal +Through hole angled socket strip, 2x29, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x29 2.00mm double row +0 +58 +58 +Connector_PinSocket_2.00mm +PinSocket_2x29_P2.00mm_Vertical +Through hole straight socket strip, 2x29, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x29 2.00mm double row +0 +58 +58 +Connector_PinSocket_2.00mm +PinSocket_2x29_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x29, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x29 2.00mm double row +0 +58 +58 +Connector_PinSocket_2.00mm +PinSocket_2x30_P2.00mm_Horizontal +Through hole angled socket strip, 2x30, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x30 2.00mm double row +0 +60 +60 +Connector_PinSocket_2.00mm +PinSocket_2x30_P2.00mm_Vertical +Through hole straight socket strip, 2x30, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x30 2.00mm double row +0 +60 +60 +Connector_PinSocket_2.00mm +PinSocket_2x30_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x30, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x30 2.00mm double row +0 +60 +60 +Connector_PinSocket_2.00mm +PinSocket_2x31_P2.00mm_Horizontal +Through hole angled socket strip, 2x31, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x31 2.00mm double row +0 +62 +62 +Connector_PinSocket_2.00mm +PinSocket_2x31_P2.00mm_Vertical +Through hole straight socket strip, 2x31, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x31 2.00mm double row +0 +62 +62 +Connector_PinSocket_2.00mm +PinSocket_2x31_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x31, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x31 2.00mm double row +0 +62 +62 +Connector_PinSocket_2.00mm +PinSocket_2x32_P2.00mm_Horizontal +Through hole angled socket strip, 2x32, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x32 2.00mm double row +0 +64 +64 +Connector_PinSocket_2.00mm +PinSocket_2x32_P2.00mm_Vertical +Through hole straight socket strip, 2x32, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x32 2.00mm double row +0 +64 +64 +Connector_PinSocket_2.00mm +PinSocket_2x32_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x32, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x32 2.00mm double row +0 +64 +64 +Connector_PinSocket_2.00mm +PinSocket_2x33_P2.00mm_Horizontal +Through hole angled socket strip, 2x33, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x33 2.00mm double row +0 +66 +66 +Connector_PinSocket_2.00mm +PinSocket_2x33_P2.00mm_Vertical +Through hole straight socket strip, 2x33, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x33 2.00mm double row +0 +66 +66 +Connector_PinSocket_2.00mm +PinSocket_2x33_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x33, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x33 2.00mm double row +0 +66 +66 +Connector_PinSocket_2.00mm +PinSocket_2x34_P2.00mm_Horizontal +Through hole angled socket strip, 2x34, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x34 2.00mm double row +0 +68 +68 +Connector_PinSocket_2.00mm +PinSocket_2x34_P2.00mm_Vertical +Through hole straight socket strip, 2x34, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x34 2.00mm double row +0 +68 +68 +Connector_PinSocket_2.00mm +PinSocket_2x34_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x34, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x34 2.00mm double row +0 +68 +68 +Connector_PinSocket_2.00mm +PinSocket_2x35_P2.00mm_Horizontal +Through hole angled socket strip, 2x35, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x35 2.00mm double row +0 +70 +70 +Connector_PinSocket_2.00mm +PinSocket_2x35_P2.00mm_Vertical +Through hole straight socket strip, 2x35, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x35 2.00mm double row +0 +70 +70 +Connector_PinSocket_2.00mm +PinSocket_2x35_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x35, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x35 2.00mm double row +0 +70 +70 +Connector_PinSocket_2.00mm +PinSocket_2x36_P2.00mm_Horizontal +Through hole angled socket strip, 2x36, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x36 2.00mm double row +0 +72 +72 +Connector_PinSocket_2.00mm +PinSocket_2x36_P2.00mm_Vertical +Through hole straight socket strip, 2x36, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x36 2.00mm double row +0 +72 +72 +Connector_PinSocket_2.00mm +PinSocket_2x36_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x36, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x36 2.00mm double row +0 +72 +72 +Connector_PinSocket_2.00mm +PinSocket_2x37_P2.00mm_Horizontal +Through hole angled socket strip, 2x37, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x37 2.00mm double row +0 +74 +74 +Connector_PinSocket_2.00mm +PinSocket_2x37_P2.00mm_Vertical +Through hole straight socket strip, 2x37, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x37 2.00mm double row +0 +74 +74 +Connector_PinSocket_2.00mm +PinSocket_2x37_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x37, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x37 2.00mm double row +0 +74 +74 +Connector_PinSocket_2.00mm +PinSocket_2x38_P2.00mm_Horizontal +Through hole angled socket strip, 2x38, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x38 2.00mm double row +0 +76 +76 +Connector_PinSocket_2.00mm +PinSocket_2x38_P2.00mm_Vertical +Through hole straight socket strip, 2x38, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x38 2.00mm double row +0 +76 +76 +Connector_PinSocket_2.00mm +PinSocket_2x38_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x38, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x38 2.00mm double row +0 +76 +76 +Connector_PinSocket_2.00mm +PinSocket_2x39_P2.00mm_Horizontal +Through hole angled socket strip, 2x39, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x39 2.00mm double row +0 +78 +78 +Connector_PinSocket_2.00mm +PinSocket_2x39_P2.00mm_Vertical +Through hole straight socket strip, 2x39, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x39 2.00mm double row +0 +78 +78 +Connector_PinSocket_2.00mm +PinSocket_2x39_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x39, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x39 2.00mm double row +0 +78 +78 +Connector_PinSocket_2.00mm +PinSocket_2x40_P2.00mm_Horizontal +Through hole angled socket strip, 2x40, 2.00mm pitch, 6.35mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x40 2.00mm double row +0 +80 +80 +Connector_PinSocket_2.00mm +PinSocket_2x40_P2.00mm_Vertical +Through hole straight socket strip, 2x40, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x40 2.00mm double row +0 +80 +80 +Connector_PinSocket_2.00mm +PinSocket_2x40_P2.00mm_Vertical_SMD +surface-mounted straight socket strip, 2x40, 2.00mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x40 2.00mm double row +0 +80 +80 +Connector_PinSocket_2.54mm +PinSocket_1x01_P2.54mm_Horizontal +Through hole angled socket strip, 1x01, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x01 2.54mm single row +0 +1 +1 +Connector_PinSocket_2.54mm +PinSocket_1x01_P2.54mm_Vertical +Through hole straight socket strip, 1x01, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x01 2.54mm single row +0 +1 +1 +Connector_PinSocket_2.54mm +PinSocket_1x02_P2.54mm_Horizontal +Through hole angled socket strip, 1x02, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x02 2.54mm single row +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_1x02_P2.54mm_Vertical +Through hole straight socket strip, 1x02, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x02 2.54mm single row +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x02 2.54mm single row style1 pin1 left +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_1x02_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x02, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x02 2.54mm single row style2 pin1 right +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_1x03_P2.54mm_Horizontal +Through hole angled socket strip, 1x03, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x03 2.54mm single row +0 +3 +3 +Connector_PinSocket_2.54mm +PinSocket_1x03_P2.54mm_Vertical +Through hole straight socket strip, 1x03, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x03 2.54mm single row +0 +3 +3 +Connector_PinSocket_2.54mm +PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x03 2.54mm single row style1 pin1 left +0 +3 +3 +Connector_PinSocket_2.54mm +PinSocket_1x03_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x03, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x03 2.54mm single row style2 pin1 right +0 +3 +3 +Connector_PinSocket_2.54mm +PinSocket_1x04_P2.54mm_Horizontal +Through hole angled socket strip, 1x04, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x04 2.54mm single row +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_1x04_P2.54mm_Vertical +Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x04 2.54mm single row +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x04 2.54mm single row style1 pin1 left +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_1x04_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x04, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x04 2.54mm single row style2 pin1 right +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_1x05_P2.54mm_Horizontal +Through hole angled socket strip, 1x05, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x05 2.54mm single row +0 +5 +5 +Connector_PinSocket_2.54mm +PinSocket_1x05_P2.54mm_Vertical +Through hole straight socket strip, 1x05, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x05 2.54mm single row +0 +5 +5 +Connector_PinSocket_2.54mm +PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x05 2.54mm single row style1 pin1 left +0 +5 +5 +Connector_PinSocket_2.54mm +PinSocket_1x05_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x05, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x05 2.54mm single row style2 pin1 right +0 +5 +5 +Connector_PinSocket_2.54mm +PinSocket_1x06_P2.54mm_Horizontal +Through hole angled socket strip, 1x06, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x06 2.54mm single row +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_1x06_P2.54mm_Vertical +Through hole straight socket strip, 1x06, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x06 2.54mm single row +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x06 2.54mm single row style1 pin1 left +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_1x06_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x06, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x06 2.54mm single row style2 pin1 right +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_1x07_P2.54mm_Horizontal +Through hole angled socket strip, 1x07, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x07 2.54mm single row +0 +7 +7 +Connector_PinSocket_2.54mm +PinSocket_1x07_P2.54mm_Vertical +Through hole straight socket strip, 1x07, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x07 2.54mm single row +0 +7 +7 +Connector_PinSocket_2.54mm +PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x07 2.54mm single row style1 pin1 left +0 +7 +7 +Connector_PinSocket_2.54mm +PinSocket_1x07_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x07, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x07 2.54mm single row style2 pin1 right +0 +7 +7 +Connector_PinSocket_2.54mm +PinSocket_1x08_P2.54mm_Horizontal +Through hole angled socket strip, 1x08, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x08 2.54mm single row +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_1x08_P2.54mm_Vertical +Through hole straight socket strip, 1x08, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x08 2.54mm single row +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x08 2.54mm single row style1 pin1 left +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_1x08_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x08, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x08 2.54mm single row style2 pin1 right +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_1x09_P2.54mm_Horizontal +Through hole angled socket strip, 1x09, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x09 2.54mm single row +0 +9 +9 +Connector_PinSocket_2.54mm +PinSocket_1x09_P2.54mm_Vertical +Through hole straight socket strip, 1x09, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x09 2.54mm single row +0 +9 +9 +Connector_PinSocket_2.54mm +PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x09 2.54mm single row style1 pin1 left +0 +9 +9 +Connector_PinSocket_2.54mm +PinSocket_1x09_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x09, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x09 2.54mm single row style2 pin1 right +0 +9 +9 +Connector_PinSocket_2.54mm +PinSocket_1x10_P2.54mm_Horizontal +Through hole angled socket strip, 1x10, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x10 2.54mm single row +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_1x10_P2.54mm_Vertical +Through hole straight socket strip, 1x10, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x10 2.54mm single row +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x10 2.54mm single row style1 pin1 left +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_1x10_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x10, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x10 2.54mm single row style2 pin1 right +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_1x11_P2.54mm_Horizontal +Through hole angled socket strip, 1x11, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x11 2.54mm single row +0 +11 +11 +Connector_PinSocket_2.54mm +PinSocket_1x11_P2.54mm_Vertical +Through hole straight socket strip, 1x11, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x11 2.54mm single row +0 +11 +11 +Connector_PinSocket_2.54mm +PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x11 2.54mm single row style1 pin1 left +0 +11 +11 +Connector_PinSocket_2.54mm +PinSocket_1x11_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x11, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x11 2.54mm single row style2 pin1 right +0 +11 +11 +Connector_PinSocket_2.54mm +PinSocket_1x12_P2.54mm_Horizontal +Through hole angled socket strip, 1x12, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x12 2.54mm single row +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_1x12_P2.54mm_Vertical +Through hole straight socket strip, 1x12, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x12 2.54mm single row +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x12 2.54mm single row style1 pin1 left +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_1x12_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x12, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x12 2.54mm single row style2 pin1 right +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_1x13_P2.54mm_Horizontal +Through hole angled socket strip, 1x13, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x13 2.54mm single row +0 +13 +13 +Connector_PinSocket_2.54mm +PinSocket_1x13_P2.54mm_Vertical +Through hole straight socket strip, 1x13, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x13 2.54mm single row +0 +13 +13 +Connector_PinSocket_2.54mm +PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x13 2.54mm single row style1 pin1 left +0 +13 +13 +Connector_PinSocket_2.54mm +PinSocket_1x13_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x13, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x13 2.54mm single row style2 pin1 right +0 +13 +13 +Connector_PinSocket_2.54mm +PinSocket_1x14_P2.54mm_Horizontal +Through hole angled socket strip, 1x14, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x14 2.54mm single row +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_1x14_P2.54mm_Vertical +Through hole straight socket strip, 1x14, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x14 2.54mm single row +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x14 2.54mm single row style1 pin1 left +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_1x14_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x14, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x14 2.54mm single row style2 pin1 right +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_1x15_P2.54mm_Horizontal +Through hole angled socket strip, 1x15, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x15 2.54mm single row +0 +15 +15 +Connector_PinSocket_2.54mm +PinSocket_1x15_P2.54mm_Vertical +Through hole straight socket strip, 1x15, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x15 2.54mm single row +0 +15 +15 +Connector_PinSocket_2.54mm +PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x15 2.54mm single row style1 pin1 left +0 +15 +15 +Connector_PinSocket_2.54mm +PinSocket_1x15_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x15, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x15 2.54mm single row style2 pin1 right +0 +15 +15 +Connector_PinSocket_2.54mm +PinSocket_1x16_P2.54mm_Horizontal +Through hole angled socket strip, 1x16, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x16 2.54mm single row +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_1x16_P2.54mm_Vertical +Through hole straight socket strip, 1x16, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x16 2.54mm single row +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x16 2.54mm single row style1 pin1 left +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_1x16_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x16, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x16 2.54mm single row style2 pin1 right +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_1x17_P2.54mm_Horizontal +Through hole angled socket strip, 1x17, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x17 2.54mm single row +0 +17 +17 +Connector_PinSocket_2.54mm +PinSocket_1x17_P2.54mm_Vertical +Through hole straight socket strip, 1x17, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x17 2.54mm single row +0 +17 +17 +Connector_PinSocket_2.54mm +PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x17 2.54mm single row style1 pin1 left +0 +17 +17 +Connector_PinSocket_2.54mm +PinSocket_1x17_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x17, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x17 2.54mm single row style2 pin1 right +0 +17 +17 +Connector_PinSocket_2.54mm +PinSocket_1x18_P2.54mm_Horizontal +Through hole angled socket strip, 1x18, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x18 2.54mm single row +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_1x18_P2.54mm_Vertical +Through hole straight socket strip, 1x18, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x18 2.54mm single row +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x18 2.54mm single row style1 pin1 left +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_1x18_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x18, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x18 2.54mm single row style2 pin1 right +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_1x19_P2.54mm_Horizontal +Through hole angled socket strip, 1x19, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x19 2.54mm single row +0 +19 +19 +Connector_PinSocket_2.54mm +PinSocket_1x19_P2.54mm_Vertical +Through hole straight socket strip, 1x19, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x19 2.54mm single row +0 +19 +19 +Connector_PinSocket_2.54mm +PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x19 2.54mm single row style1 pin1 left +0 +19 +19 +Connector_PinSocket_2.54mm +PinSocket_1x19_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x19, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x19 2.54mm single row style2 pin1 right +0 +19 +19 +Connector_PinSocket_2.54mm +PinSocket_1x20_P2.54mm_Horizontal +Through hole angled socket strip, 1x20, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x20 2.54mm single row +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_1x20_P2.54mm_Vertical +Through hole straight socket strip, 1x20, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x20 2.54mm single row +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x20 2.54mm single row style1 pin1 left +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_1x20_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x20, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x20 2.54mm single row style2 pin1 right +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_1x21_P2.54mm_Horizontal +Through hole angled socket strip, 1x21, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x21 2.54mm single row +0 +21 +21 +Connector_PinSocket_2.54mm +PinSocket_1x21_P2.54mm_Vertical +Through hole straight socket strip, 1x21, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x21 2.54mm single row +0 +21 +21 +Connector_PinSocket_2.54mm +PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x21 2.54mm single row style1 pin1 left +0 +21 +21 +Connector_PinSocket_2.54mm +PinSocket_1x21_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x21, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x21 2.54mm single row style2 pin1 right +0 +21 +21 +Connector_PinSocket_2.54mm +PinSocket_1x22_P2.54mm_Horizontal +Through hole angled socket strip, 1x22, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x22 2.54mm single row +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_1x22_P2.54mm_Vertical +Through hole straight socket strip, 1x22, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x22 2.54mm single row +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x22 2.54mm single row style1 pin1 left +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_1x22_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x22, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x22 2.54mm single row style2 pin1 right +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_1x23_P2.54mm_Horizontal +Through hole angled socket strip, 1x23, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x23 2.54mm single row +0 +23 +23 +Connector_PinSocket_2.54mm +PinSocket_1x23_P2.54mm_Vertical +Through hole straight socket strip, 1x23, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x23 2.54mm single row +0 +23 +23 +Connector_PinSocket_2.54mm +PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x23 2.54mm single row style1 pin1 left +0 +23 +23 +Connector_PinSocket_2.54mm +PinSocket_1x23_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x23, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x23 2.54mm single row style2 pin1 right +0 +23 +23 +Connector_PinSocket_2.54mm +PinSocket_1x24_P2.54mm_Horizontal +Through hole angled socket strip, 1x24, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x24 2.54mm single row +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_1x24_P2.54mm_Vertical +Through hole straight socket strip, 1x24, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x24 2.54mm single row +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x24 2.54mm single row style1 pin1 left +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_1x24_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x24, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x24 2.54mm single row style2 pin1 right +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_1x25_P2.54mm_Horizontal +Through hole angled socket strip, 1x25, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x25 2.54mm single row +0 +25 +25 +Connector_PinSocket_2.54mm +PinSocket_1x25_P2.54mm_Vertical +Through hole straight socket strip, 1x25, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x25 2.54mm single row +0 +25 +25 +Connector_PinSocket_2.54mm +PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x25 2.54mm single row style1 pin1 left +0 +25 +25 +Connector_PinSocket_2.54mm +PinSocket_1x25_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x25, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x25 2.54mm single row style2 pin1 right +0 +25 +25 +Connector_PinSocket_2.54mm +PinSocket_1x26_P2.54mm_Horizontal +Through hole angled socket strip, 1x26, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x26 2.54mm single row +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_1x26_P2.54mm_Vertical +Through hole straight socket strip, 1x26, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x26 2.54mm single row +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x26 2.54mm single row style1 pin1 left +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_1x26_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x26, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x26 2.54mm single row style2 pin1 right +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_1x27_P2.54mm_Horizontal +Through hole angled socket strip, 1x27, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x27 2.54mm single row +0 +27 +27 +Connector_PinSocket_2.54mm +PinSocket_1x27_P2.54mm_Vertical +Through hole straight socket strip, 1x27, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x27 2.54mm single row +0 +27 +27 +Connector_PinSocket_2.54mm +PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x27 2.54mm single row style1 pin1 left +0 +27 +27 +Connector_PinSocket_2.54mm +PinSocket_1x27_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x27, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x27 2.54mm single row style2 pin1 right +0 +27 +27 +Connector_PinSocket_2.54mm +PinSocket_1x28_P2.54mm_Horizontal +Through hole angled socket strip, 1x28, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x28 2.54mm single row +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_1x28_P2.54mm_Vertical +Through hole straight socket strip, 1x28, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x28 2.54mm single row +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x28 2.54mm single row style1 pin1 left +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_1x28_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x28, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x28 2.54mm single row style2 pin1 right +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_1x29_P2.54mm_Horizontal +Through hole angled socket strip, 1x29, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x29 2.54mm single row +0 +29 +29 +Connector_PinSocket_2.54mm +PinSocket_1x29_P2.54mm_Vertical +Through hole straight socket strip, 1x29, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x29 2.54mm single row +0 +29 +29 +Connector_PinSocket_2.54mm +PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x29 2.54mm single row style1 pin1 left +0 +29 +29 +Connector_PinSocket_2.54mm +PinSocket_1x29_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x29, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x29 2.54mm single row style2 pin1 right +0 +29 +29 +Connector_PinSocket_2.54mm +PinSocket_1x30_P2.54mm_Horizontal +Through hole angled socket strip, 1x30, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x30 2.54mm single row +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_1x30_P2.54mm_Vertical +Through hole straight socket strip, 1x30, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x30 2.54mm single row +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x30 2.54mm single row style1 pin1 left +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_1x30_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x30, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x30 2.54mm single row style2 pin1 right +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_1x31_P2.54mm_Horizontal +Through hole angled socket strip, 1x31, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x31 2.54mm single row +0 +31 +31 +Connector_PinSocket_2.54mm +PinSocket_1x31_P2.54mm_Vertical +Through hole straight socket strip, 1x31, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x31 2.54mm single row +0 +31 +31 +Connector_PinSocket_2.54mm +PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x31 2.54mm single row style1 pin1 left +0 +31 +31 +Connector_PinSocket_2.54mm +PinSocket_1x31_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x31, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x31 2.54mm single row style2 pin1 right +0 +31 +31 +Connector_PinSocket_2.54mm +PinSocket_1x32_P2.54mm_Horizontal +Through hole angled socket strip, 1x32, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x32 2.54mm single row +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_1x32_P2.54mm_Vertical +Through hole straight socket strip, 1x32, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x32 2.54mm single row +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x32 2.54mm single row style1 pin1 left +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_1x32_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x32, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x32 2.54mm single row style2 pin1 right +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_1x33_P2.54mm_Horizontal +Through hole angled socket strip, 1x33, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x33 2.54mm single row +0 +33 +33 +Connector_PinSocket_2.54mm +PinSocket_1x33_P2.54mm_Vertical +Through hole straight socket strip, 1x33, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x33 2.54mm single row +0 +33 +33 +Connector_PinSocket_2.54mm +PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x33 2.54mm single row style1 pin1 left +0 +33 +33 +Connector_PinSocket_2.54mm +PinSocket_1x33_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x33, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x33 2.54mm single row style2 pin1 right +0 +33 +33 +Connector_PinSocket_2.54mm +PinSocket_1x34_P2.54mm_Horizontal +Through hole angled socket strip, 1x34, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x34 2.54mm single row +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_1x34_P2.54mm_Vertical +Through hole straight socket strip, 1x34, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x34 2.54mm single row +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x34 2.54mm single row style1 pin1 left +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_1x34_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x34, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x34 2.54mm single row style2 pin1 right +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_1x35_P2.54mm_Horizontal +Through hole angled socket strip, 1x35, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x35 2.54mm single row +0 +35 +35 +Connector_PinSocket_2.54mm +PinSocket_1x35_P2.54mm_Vertical +Through hole straight socket strip, 1x35, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x35 2.54mm single row +0 +35 +35 +Connector_PinSocket_2.54mm +PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x35 2.54mm single row style1 pin1 left +0 +35 +35 +Connector_PinSocket_2.54mm +PinSocket_1x35_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x35, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x35 2.54mm single row style2 pin1 right +0 +35 +35 +Connector_PinSocket_2.54mm +PinSocket_1x36_P2.54mm_Horizontal +Through hole angled socket strip, 1x36, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x36 2.54mm single row +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_1x36_P2.54mm_Vertical +Through hole straight socket strip, 1x36, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x36 2.54mm single row +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x36 2.54mm single row style1 pin1 left +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_1x36_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x36, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x36 2.54mm single row style2 pin1 right +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_1x37_P2.54mm_Horizontal +Through hole angled socket strip, 1x37, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x37 2.54mm single row +0 +37 +37 +Connector_PinSocket_2.54mm +PinSocket_1x37_P2.54mm_Vertical +Through hole straight socket strip, 1x37, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x37 2.54mm single row +0 +37 +37 +Connector_PinSocket_2.54mm +PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x37 2.54mm single row style1 pin1 left +0 +37 +37 +Connector_PinSocket_2.54mm +PinSocket_1x37_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x37, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x37 2.54mm single row style2 pin1 right +0 +37 +37 +Connector_PinSocket_2.54mm +PinSocket_1x38_P2.54mm_Horizontal +Through hole angled socket strip, 1x38, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x38 2.54mm single row +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_1x38_P2.54mm_Vertical +Through hole straight socket strip, 1x38, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x38 2.54mm single row +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x38 2.54mm single row style1 pin1 left +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_1x38_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x38, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x38 2.54mm single row style2 pin1 right +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_1x39_P2.54mm_Horizontal +Through hole angled socket strip, 1x39, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x39 2.54mm single row +0 +39 +39 +Connector_PinSocket_2.54mm +PinSocket_1x39_P2.54mm_Vertical +Through hole straight socket strip, 1x39, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x39 2.54mm single row +0 +39 +39 +Connector_PinSocket_2.54mm +PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x39 2.54mm single row style1 pin1 left +0 +39 +39 +Connector_PinSocket_2.54mm +PinSocket_1x39_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x39, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x39 2.54mm single row style2 pin1 right +0 +39 +39 +Connector_PinSocket_2.54mm +PinSocket_1x40_P2.54mm_Horizontal +Through hole angled socket strip, 1x40, 2.54mm pitch, 8.51mm socket length, single row (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 1x40 2.54mm single row +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_1x40_P2.54mm_Vertical +Through hole straight socket strip, 1x40, 2.54mm pitch, single row (from Kicad 4.0.7), script generated +Through hole socket strip THT 1x40 2.54mm single row +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Left +surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 1 (pin 1 left) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x40 2.54mm single row style1 pin1 left +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_1x40_P2.54mm_Vertical_SMD_Pin1Right +surface-mounted straight socket strip, 1x40, 2.54mm pitch, single row, style 2 (pin 1 right) (https://cdn.harwin.com/pdfs/M20-786.pdf), script generated +Surface mounted socket strip SMD 1x40 2.54mm single row style2 pin1 right +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_2x01_P2.54mm_Horizontal +Through hole angled socket strip, 2x01, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x01 2.54mm double row +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_2x01_P2.54mm_Vertical +Through hole straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x01 2.54mm double row +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_2x01_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x01, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x01 2.54mm double row +0 +2 +2 +Connector_PinSocket_2.54mm +PinSocket_2x02_P2.54mm_Horizontal +Through hole angled socket strip, 2x02, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x02 2.54mm double row +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_2x02_P2.54mm_Vertical +Through hole straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x02 2.54mm double row +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_2x02_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x02, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x02 2.54mm double row +0 +4 +4 +Connector_PinSocket_2.54mm +PinSocket_2x03_P2.54mm_Horizontal +Through hole angled socket strip, 2x03, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x03 2.54mm double row +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_2x03_P2.54mm_Vertical +Through hole straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x03 2.54mm double row +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_2x03_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x03, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x03 2.54mm double row +0 +6 +6 +Connector_PinSocket_2.54mm +PinSocket_2x04_P2.54mm_Horizontal +Through hole angled socket strip, 2x04, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x04 2.54mm double row +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_2x04_P2.54mm_Vertical +Through hole straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x04 2.54mm double row +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_2x04_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x04, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x04 2.54mm double row +0 +8 +8 +Connector_PinSocket_2.54mm +PinSocket_2x05_P2.54mm_Horizontal +Through hole angled socket strip, 2x05, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x05 2.54mm double row +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_2x05_P2.54mm_Vertical +Through hole straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x05 2.54mm double row +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_2x05_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x05, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x05 2.54mm double row +0 +10 +10 +Connector_PinSocket_2.54mm +PinSocket_2x06_P2.54mm_Horizontal +Through hole angled socket strip, 2x06, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x06 2.54mm double row +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_2x06_P2.54mm_Vertical +Through hole straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x06 2.54mm double row +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_2x06_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x06, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x06 2.54mm double row +0 +12 +12 +Connector_PinSocket_2.54mm +PinSocket_2x07_P2.54mm_Horizontal +Through hole angled socket strip, 2x07, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x07 2.54mm double row +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_2x07_P2.54mm_Vertical +Through hole straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x07 2.54mm double row +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_2x07_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x07, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x07 2.54mm double row +0 +14 +14 +Connector_PinSocket_2.54mm +PinSocket_2x08_P2.54mm_Horizontal +Through hole angled socket strip, 2x08, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x08 2.54mm double row +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_2x08_P2.54mm_Vertical +Through hole straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x08 2.54mm double row +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_2x08_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x08, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x08 2.54mm double row +0 +16 +16 +Connector_PinSocket_2.54mm +PinSocket_2x09_P2.54mm_Horizontal +Through hole angled socket strip, 2x09, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x09 2.54mm double row +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_2x09_P2.54mm_Vertical +Through hole straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x09 2.54mm double row +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_2x09_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x09, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x09 2.54mm double row +0 +18 +18 +Connector_PinSocket_2.54mm +PinSocket_2x10_P2.54mm_Horizontal +Through hole angled socket strip, 2x10, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x10 2.54mm double row +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_2x10_P2.54mm_Vertical +Through hole straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x10 2.54mm double row +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_2x10_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x10, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x10 2.54mm double row +0 +20 +20 +Connector_PinSocket_2.54mm +PinSocket_2x11_P2.54mm_Horizontal +Through hole angled socket strip, 2x11, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x11 2.54mm double row +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_2x11_P2.54mm_Vertical +Through hole straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x11 2.54mm double row +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_2x11_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x11, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x11 2.54mm double row +0 +22 +22 +Connector_PinSocket_2.54mm +PinSocket_2x12_P2.54mm_Horizontal +Through hole angled socket strip, 2x12, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x12 2.54mm double row +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_2x12_P2.54mm_Vertical +Through hole straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x12 2.54mm double row +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_2x12_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x12, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x12 2.54mm double row +0 +24 +24 +Connector_PinSocket_2.54mm +PinSocket_2x13_P2.54mm_Horizontal +Through hole angled socket strip, 2x13, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x13 2.54mm double row +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_2x13_P2.54mm_Vertical +Through hole straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x13 2.54mm double row +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_2x13_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x13, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x13 2.54mm double row +0 +26 +26 +Connector_PinSocket_2.54mm +PinSocket_2x14_P2.54mm_Horizontal +Through hole angled socket strip, 2x14, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x14 2.54mm double row +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_2x14_P2.54mm_Vertical +Through hole straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x14 2.54mm double row +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_2x14_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x14, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x14 2.54mm double row +0 +28 +28 +Connector_PinSocket_2.54mm +PinSocket_2x15_P2.54mm_Horizontal +Through hole angled socket strip, 2x15, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x15 2.54mm double row +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_2x15_P2.54mm_Vertical +Through hole straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x15 2.54mm double row +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_2x15_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x15, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x15 2.54mm double row +0 +30 +30 +Connector_PinSocket_2.54mm +PinSocket_2x16_P2.54mm_Horizontal +Through hole angled socket strip, 2x16, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x16 2.54mm double row +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_2x16_P2.54mm_Vertical +Through hole straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x16 2.54mm double row +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_2x16_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x16, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x16 2.54mm double row +0 +32 +32 +Connector_PinSocket_2.54mm +PinSocket_2x17_P2.54mm_Horizontal +Through hole angled socket strip, 2x17, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x17 2.54mm double row +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_2x17_P2.54mm_Vertical +Through hole straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x17 2.54mm double row +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_2x17_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x17, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x17 2.54mm double row +0 +34 +34 +Connector_PinSocket_2.54mm +PinSocket_2x18_P2.54mm_Horizontal +Through hole angled socket strip, 2x18, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x18 2.54mm double row +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_2x18_P2.54mm_Vertical +Through hole straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x18 2.54mm double row +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_2x18_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x18, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x18 2.54mm double row +0 +36 +36 +Connector_PinSocket_2.54mm +PinSocket_2x19_P2.54mm_Horizontal +Through hole angled socket strip, 2x19, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x19 2.54mm double row +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_2x19_P2.54mm_Vertical +Through hole straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x19 2.54mm double row +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_2x19_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x19, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x19 2.54mm double row +0 +38 +38 +Connector_PinSocket_2.54mm +PinSocket_2x20_P2.54mm_Horizontal +Through hole angled socket strip, 2x20, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x20 2.54mm double row +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_2x20_P2.54mm_Vertical +Through hole straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x20 2.54mm double row +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_2x20_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x20, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x20 2.54mm double row +0 +40 +40 +Connector_PinSocket_2.54mm +PinSocket_2x21_P2.54mm_Horizontal +Through hole angled socket strip, 2x21, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x21 2.54mm double row +0 +42 +42 +Connector_PinSocket_2.54mm +PinSocket_2x21_P2.54mm_Vertical +Through hole straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x21 2.54mm double row +0 +42 +42 +Connector_PinSocket_2.54mm +PinSocket_2x21_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x21, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x21 2.54mm double row +0 +42 +42 +Connector_PinSocket_2.54mm +PinSocket_2x22_P2.54mm_Horizontal +Through hole angled socket strip, 2x22, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x22 2.54mm double row +0 +44 +44 +Connector_PinSocket_2.54mm +PinSocket_2x22_P2.54mm_Vertical +Through hole straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x22 2.54mm double row +0 +44 +44 +Connector_PinSocket_2.54mm +PinSocket_2x22_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x22, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x22 2.54mm double row +0 +44 +44 +Connector_PinSocket_2.54mm +PinSocket_2x23_P2.54mm_Horizontal +Through hole angled socket strip, 2x23, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x23 2.54mm double row +0 +46 +46 +Connector_PinSocket_2.54mm +PinSocket_2x23_P2.54mm_Vertical +Through hole straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x23 2.54mm double row +0 +46 +46 +Connector_PinSocket_2.54mm +PinSocket_2x23_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x23, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x23 2.54mm double row +0 +46 +46 +Connector_PinSocket_2.54mm +PinSocket_2x24_P2.54mm_Horizontal +Through hole angled socket strip, 2x24, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x24 2.54mm double row +0 +48 +48 +Connector_PinSocket_2.54mm +PinSocket_2x24_P2.54mm_Vertical +Through hole straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x24 2.54mm double row +0 +48 +48 +Connector_PinSocket_2.54mm +PinSocket_2x24_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x24, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x24 2.54mm double row +0 +48 +48 +Connector_PinSocket_2.54mm +PinSocket_2x25_P2.54mm_Horizontal +Through hole angled socket strip, 2x25, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x25 2.54mm double row +0 +50 +50 +Connector_PinSocket_2.54mm +PinSocket_2x25_P2.54mm_Vertical +Through hole straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x25 2.54mm double row +0 +50 +50 +Connector_PinSocket_2.54mm +PinSocket_2x25_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x25, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x25 2.54mm double row +0 +50 +50 +Connector_PinSocket_2.54mm +PinSocket_2x26_P2.54mm_Horizontal +Through hole angled socket strip, 2x26, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x26 2.54mm double row +0 +52 +52 +Connector_PinSocket_2.54mm +PinSocket_2x26_P2.54mm_Vertical +Through hole straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x26 2.54mm double row +0 +52 +52 +Connector_PinSocket_2.54mm +PinSocket_2x26_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x26, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x26 2.54mm double row +0 +52 +52 +Connector_PinSocket_2.54mm +PinSocket_2x27_P2.54mm_Horizontal +Through hole angled socket strip, 2x27, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x27 2.54mm double row +0 +54 +54 +Connector_PinSocket_2.54mm +PinSocket_2x27_P2.54mm_Vertical +Through hole straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x27 2.54mm double row +0 +54 +54 +Connector_PinSocket_2.54mm +PinSocket_2x27_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x27, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x27 2.54mm double row +0 +54 +54 +Connector_PinSocket_2.54mm +PinSocket_2x28_P2.54mm_Horizontal +Through hole angled socket strip, 2x28, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x28 2.54mm double row +0 +56 +56 +Connector_PinSocket_2.54mm +PinSocket_2x28_P2.54mm_Vertical +Through hole straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x28 2.54mm double row +0 +56 +56 +Connector_PinSocket_2.54mm +PinSocket_2x28_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x28, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x28 2.54mm double row +0 +56 +56 +Connector_PinSocket_2.54mm +PinSocket_2x29_P2.54mm_Horizontal +Through hole angled socket strip, 2x29, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x29 2.54mm double row +0 +58 +58 +Connector_PinSocket_2.54mm +PinSocket_2x29_P2.54mm_Vertical +Through hole straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x29 2.54mm double row +0 +58 +58 +Connector_PinSocket_2.54mm +PinSocket_2x29_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x29, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x29 2.54mm double row +0 +58 +58 +Connector_PinSocket_2.54mm +PinSocket_2x30_P2.54mm_Horizontal +Through hole angled socket strip, 2x30, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x30 2.54mm double row +0 +60 +60 +Connector_PinSocket_2.54mm +PinSocket_2x30_P2.54mm_Vertical +Through hole straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x30 2.54mm double row +0 +60 +60 +Connector_PinSocket_2.54mm +PinSocket_2x30_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x30, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x30 2.54mm double row +0 +60 +60 +Connector_PinSocket_2.54mm +PinSocket_2x31_P2.54mm_Horizontal +Through hole angled socket strip, 2x31, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x31 2.54mm double row +0 +62 +62 +Connector_PinSocket_2.54mm +PinSocket_2x31_P2.54mm_Vertical +Through hole straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x31 2.54mm double row +0 +62 +62 +Connector_PinSocket_2.54mm +PinSocket_2x31_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x31, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x31 2.54mm double row +0 +62 +62 +Connector_PinSocket_2.54mm +PinSocket_2x32_P2.54mm_Horizontal +Through hole angled socket strip, 2x32, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x32 2.54mm double row +0 +64 +64 +Connector_PinSocket_2.54mm +PinSocket_2x32_P2.54mm_Vertical +Through hole straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x32 2.54mm double row +0 +64 +64 +Connector_PinSocket_2.54mm +PinSocket_2x32_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x32, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x32 2.54mm double row +0 +64 +64 +Connector_PinSocket_2.54mm +PinSocket_2x33_P2.54mm_Horizontal +Through hole angled socket strip, 2x33, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x33 2.54mm double row +0 +66 +66 +Connector_PinSocket_2.54mm +PinSocket_2x33_P2.54mm_Vertical +Through hole straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x33 2.54mm double row +0 +66 +66 +Connector_PinSocket_2.54mm +PinSocket_2x33_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x33, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x33 2.54mm double row +0 +66 +66 +Connector_PinSocket_2.54mm +PinSocket_2x34_P2.54mm_Horizontal +Through hole angled socket strip, 2x34, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x34 2.54mm double row +0 +68 +68 +Connector_PinSocket_2.54mm +PinSocket_2x34_P2.54mm_Vertical +Through hole straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x34 2.54mm double row +0 +68 +68 +Connector_PinSocket_2.54mm +PinSocket_2x34_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x34, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x34 2.54mm double row +0 +68 +68 +Connector_PinSocket_2.54mm +PinSocket_2x35_P2.54mm_Horizontal +Through hole angled socket strip, 2x35, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x35 2.54mm double row +0 +70 +70 +Connector_PinSocket_2.54mm +PinSocket_2x35_P2.54mm_Vertical +Through hole straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x35 2.54mm double row +0 +70 +70 +Connector_PinSocket_2.54mm +PinSocket_2x35_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x35, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x35 2.54mm double row +0 +70 +70 +Connector_PinSocket_2.54mm +PinSocket_2x36_P2.54mm_Horizontal +Through hole angled socket strip, 2x36, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x36 2.54mm double row +0 +72 +72 +Connector_PinSocket_2.54mm +PinSocket_2x36_P2.54mm_Vertical +Through hole straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x36 2.54mm double row +0 +72 +72 +Connector_PinSocket_2.54mm +PinSocket_2x36_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x36, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x36 2.54mm double row +0 +72 +72 +Connector_PinSocket_2.54mm +PinSocket_2x37_P2.54mm_Horizontal +Through hole angled socket strip, 2x37, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x37 2.54mm double row +0 +74 +74 +Connector_PinSocket_2.54mm +PinSocket_2x37_P2.54mm_Vertical +Through hole straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x37 2.54mm double row +0 +74 +74 +Connector_PinSocket_2.54mm +PinSocket_2x37_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x37, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x37 2.54mm double row +0 +74 +74 +Connector_PinSocket_2.54mm +PinSocket_2x38_P2.54mm_Horizontal +Through hole angled socket strip, 2x38, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x38 2.54mm double row +0 +76 +76 +Connector_PinSocket_2.54mm +PinSocket_2x38_P2.54mm_Vertical +Through hole straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x38 2.54mm double row +0 +76 +76 +Connector_PinSocket_2.54mm +PinSocket_2x38_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x38, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x38 2.54mm double row +0 +76 +76 +Connector_PinSocket_2.54mm +PinSocket_2x39_P2.54mm_Horizontal +Through hole angled socket strip, 2x39, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x39 2.54mm double row +0 +78 +78 +Connector_PinSocket_2.54mm +PinSocket_2x39_P2.54mm_Vertical +Through hole straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x39 2.54mm double row +0 +78 +78 +Connector_PinSocket_2.54mm +PinSocket_2x39_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x39, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x39 2.54mm double row +0 +78 +78 +Connector_PinSocket_2.54mm +PinSocket_2x40_P2.54mm_Horizontal +Through hole angled socket strip, 2x40, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated +Through hole angled socket strip THT 2x40 2.54mm double row +0 +80 +80 +Connector_PinSocket_2.54mm +PinSocket_2x40_P2.54mm_Vertical +Through hole straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Through hole socket strip THT 2x40 2.54mm double row +0 +80 +80 +Connector_PinSocket_2.54mm +PinSocket_2x40_P2.54mm_Vertical_SMD +surface-mounted straight socket strip, 2x40, 2.54mm pitch, double cols (from Kicad 4.0.7), script generated +Surface mounted socket strip SMD 2x40 2.54mm double row +0 +80 +80 +Connector_RJ +RJ12_Amphenol_54601 +RJ12 connector https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0082.pdf +RJ12 connector +0 +6 +6 +Connector_RJ +RJ25_Wayconn_MJEA-660X1_Horizontal +RJ25 6P6C Socket 90 degrees, https://wayconn.com/wp-content/themes/way/datasheet/MJEA-660X1XXX_RJ25_6P6C_PCB_RA.pdf +RJ12 RJ18 RJ25 jack connector 6P6C +0 +6 +6 +Connector_RJ +RJ45_Abracon_ARJP11A-MA_Horizontal +Shielded RJ45 ethernet connector with transformer and POE (https://abracon.com/Magnetics/lan/ARJP11A.PDF) +ethernet 8p8c transformer poe rj45 +0 +15 +14 +Connector_RJ +RJ45_Amphenol_54602-x08_Horizontal +8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf) +RJ45 +0 +8 +8 +Connector_RJ +RJ45_Amphenol_RJHSE538X +Shielded, 2 LED, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf +RJ45 8p8c ethernet cat5 +0 +14 +13 +Connector_RJ +RJ45_Amphenol_RJHSE538X-02 +Shielded, 2 LED, 2 Ports, http://www.amphenolinfocom.eu/NavData/Drawings/RJHSE-538X-02-REVC.pdf +RJ45 8p8c dual ethernet cat5 +0 +26 +25 +Connector_RJ +RJ45_Amphenol_RJHSE5380 +Shielded, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X.pdf +RJ45 8p8c ethernet cat5 +0 +10 +9 +Connector_RJ +RJ45_Amphenol_RJHSE5380-08 +Shielded, https://www.amphenolcanada.com/ProductSearch/drawings/AC/RJHSE538X08.pdf +RJ45 8p8c ethernet cat5 +0 +68 +65 +Connector_RJ +RJ45_Amphenol_RJMG1BD3B8K1ANR +1 Port RJ45 Magjack Connector Through Hole 10/100 Base-T, AutoMDIX, https://www.amphenolcanada.com/ProductSearch/Drawings/AC/RJMG1BD3B8K1ANR.PDF +RJ45 Magjack +0 +14 +13 +Connector_RJ +RJ45_BEL_SS74301-00x_Vertical +https://belfuse.com/resources/drawings/stewartconnector/dr-stw-ss-74301-001-ss-74301-002-ss-74301-005.pdf +RJ45 Vertical Shield LED Green Yellow +0 +14 +13 +Connector_RJ +RJ45_Cetus_J1B1211CCD_Horizontal +1 Port RJ45 Magjack Connector Through Hole 10/100 Base-T, Cetus, used and distributed by WIZnet (https://wizwiki.net/wiki/lib/exe/fetch.php?media=products:wiz550web:wiz550webds_kr:j1b1211ccd.pdf) +RJ45 Magjack +0 +14 +13 +Connector_RJ +RJ45_Hanrun_HR911105A +http://www.kosmodrom.com.ua/pdf/HR911105A.pdf +RJ45 Magjack +0 +14 +13 +Connector_RJ +RJ45_OST_PJ012-8P8CX_Vertical +RJ45 vertical connector http://www.on-shore.com/wp-content/uploads/2015/09/PJ012-8P8CX.pdf +RJ45 PJ012 +0 +8 +8 +Connector_RJ +RJ45_Plug_Metz_AJP92A8813 +plug, ethernet, 8P8C, RJ45 Plug +AJP92A8813 8P8C RJ45 ethernet plug +0 +8 +8 +Connector_RJ +RJ45_Pulse_JK0654219NL_Horizontal +10/100/1000 Base-T RJ45 single port with LEDs https://media.digikey.com/pdf/Data%20Sheets/Pulse%20PDFs/JK%20Series.pdf#page=2 +RJ45 8p8c ethernet +0 +18 +17 +Connector_RJ +RJ45_Pulse_JXD6-0001NL_Horizontal +RJ45 ethernet transformer with magnetics (https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/JXD6-0001NL/doc_part/JXD6-0001NL.pdf) +ethernet 8p8c transformer magjack +0 +12 +11 +Connector_RJ +RJ45_Wuerth_7499010121A_Horizontal +10/100Base-TX RJ45 ethernet magnetic transformer connector horizontal https://katalog.we-online.de/pbs/datasheet/7499010121A.pdf +RJ45 ethernet magnetic +0 +14 +13 +Connector_RJ +RJ45_Wuerth_7499151120_Horizontal +Wuerth 7499151120, LAN-Transformer WE-RJ45LAN 10/100/1000 BaseT, Dual Ethernet Jack (http://katalog.we-online.de/pbs/datasheet/7499151120.pdf) +ethernet lan connector +0 +32 +29 +Connector_RJ +RJ45_Wuerth_74980111211_Horizontal +RJ45 LAN Transformer 10/100BaseT (https://katalog.we-online.de/pbs/datasheet/74980111211.pdf) +lan magnetics transformer +0 +14 +13 +Connector_SATA_SAS +SAS-mini_TEConnectivity_1888174_Vertical +36pin mini SAS connector, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=1888174&DocType=Customer+Drawing&DocLang=English +SAS mini connector +0 +44 +44 +Connector_SATA_SAS +SATA_Amphenol_10029364-001LF_Horizontal +https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10029364.pdf +SATA +0 +24 +23 +Connector_Samtec +Samtec_FMC_ASP-134486-01_10x40_P1.27mm_Vertical +http://suddendocs.samtec.com/prints/asp-134486-01-mkt.pdf +FMC HPC +0 +400 +400 +Connector_Samtec +Samtec_FMC_ASP-134602-01_10x40_P1.27mm_Vertical +https://www.marutsu.co.jp/contents/shop/marutsu/ds/asp-134602-01.pdf +FMC HPC +0 +400 +400 +Connector_Samtec +Samtec_FMC_ASP-134604-01_4x40_Vertical +http://www.samtec.com/standards/vita.aspx +FMC LPC VITA +0 +162 +160 +Connector_Samtec +Samtec_LSHM-105-xx.x-x-DV-N_2x05_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-105-xx.x-x-DV-N, 5 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +10 +10 +Connector_Samtec +Samtec_LSHM-105-xx.x-x-DV-S_2x05-1SH_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-105-xx.x-x-DV-S, 5 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +12 +11 +Connector_Samtec +Samtec_LSHM-110-xx.x-x-DV-N_2x10_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-110-xx.x-x-DV-N, 10 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +20 +20 +Connector_Samtec +Samtec_LSHM-110-xx.x-x-DV-S_2x10-1SH_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-110-xx.x-x-DV-S, 10 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +22 +21 +Connector_Samtec +Samtec_LSHM-120-xx.x-x-DV-N_2x20_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-120-xx.x-x-DV-N, 20 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +40 +40 +Connector_Samtec +Samtec_LSHM-120-xx.x-x-DV-S_2x20-1SH_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-120-xx.x-x-DV-S, 20 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +42 +41 +Connector_Samtec +Samtec_LSHM-130-xx.x-x-DV-N_2x30_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-130-xx.x-x-DV-N, 30 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +60 +60 +Connector_Samtec +Samtec_LSHM-130-xx.x-x-DV-S_2x30-1SH_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-130-xx.x-x-DV-S, 30 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +62 +61 +Connector_Samtec +Samtec_LSHM-140-xx.x-x-DV-N_2x40_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-140-xx.x-x-DV-N, 40 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +80 +80 +Connector_Samtec +Samtec_LSHM-140-xx.x-x-DV-S_2x40-1SH_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-140-xx.x-x-DV-S, 40 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +82 +81 +Connector_Samtec +Samtec_LSHM-150-xx.x-x-DV-N_2x50_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-150-xx.x-x-DV-N, 50 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +100 +100 +Connector_Samtec +Samtec_LSHM-150-xx.x-x-DV-S_2x50-1SH_P0.50mm_Vertical +Molex LSHM 0.50 mm Razor Beam High-Speed Hermaphroditic Terminal/Socket Strip, LSHM-150-xx.x-x-DV-S, 50 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator +connector Samtec side entry +0 +102 +101 +Connector_Samtec_HLE_SMD +Samtec_HLE-102-02-xxx-DV-BE-LC_2x02_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-BE-LC, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +4 +4 +Connector_Samtec_HLE_SMD +Samtec_HLE-102-02-xxx-DV-BE_2x02_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-BE, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +4 +4 +Connector_Samtec_HLE_SMD +Samtec_HLE-102-02-xxx-DV-LC_2x02_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV-LC, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +4 +4 +Connector_Samtec_HLE_SMD +Samtec_HLE-102-02-xxx-DV_2x02_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-102-02-xxx-DV, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +4 +4 +Connector_Samtec_HLE_SMD +Samtec_HLE-103-02-xxx-DV-BE-LC_2x03_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-BE-LC, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +6 +6 +Connector_Samtec_HLE_SMD +Samtec_HLE-103-02-xxx-DV-BE_2x03_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-BE, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +6 +6 +Connector_Samtec_HLE_SMD +Samtec_HLE-103-02-xxx-DV-LC_2x03_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV-LC, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +6 +6 +Connector_Samtec_HLE_SMD +Samtec_HLE-103-02-xxx-DV_2x03_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-103-02-xxx-DV, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +6 +6 +Connector_Samtec_HLE_SMD +Samtec_HLE-104-02-xxx-DV-A_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-A, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_SMD +Samtec_HLE-104-02-xxx-DV-BE-A_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE-A, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_SMD +Samtec_HLE-104-02-xxx-DV-BE-LC_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_SMD +Samtec_HLE-104-02-xxx-DV-BE_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-BE, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_SMD +Samtec_HLE-104-02-xxx-DV-LC_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_SMD +Samtec_HLE-104-02-xxx-DV_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xxx-DV, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_SMD +Samtec_HLE-105-02-xxx-DV-A_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-A, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_SMD +Samtec_HLE-105-02-xxx-DV-BE-A_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE-A, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_SMD +Samtec_HLE-105-02-xxx-DV-BE-LC_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_SMD +Samtec_HLE-105-02-xxx-DV-BE_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-BE, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_SMD +Samtec_HLE-105-02-xxx-DV-LC_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_SMD +Samtec_HLE-105-02-xxx-DV_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xxx-DV, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_SMD +Samtec_HLE-106-02-xxx-DV-A_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-A, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_SMD +Samtec_HLE-106-02-xxx-DV-BE-A_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE-A, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_SMD +Samtec_HLE-106-02-xxx-DV-BE-LC_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_SMD +Samtec_HLE-106-02-xxx-DV-BE_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-BE, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_SMD +Samtec_HLE-106-02-xxx-DV-LC_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_SMD +Samtec_HLE-106-02-xxx-DV_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xxx-DV, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_SMD +Samtec_HLE-107-02-xxx-DV-A_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-A, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_SMD +Samtec_HLE-107-02-xxx-DV-BE-A_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE-A, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_SMD +Samtec_HLE-107-02-xxx-DV-BE-LC_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_SMD +Samtec_HLE-107-02-xxx-DV-BE_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-BE, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_SMD +Samtec_HLE-107-02-xxx-DV-LC_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_SMD +Samtec_HLE-107-02-xxx-DV_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xxx-DV, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_SMD +Samtec_HLE-108-02-xxx-DV-A_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-A, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_SMD +Samtec_HLE-108-02-xxx-DV-BE-A_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE-A, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_SMD +Samtec_HLE-108-02-xxx-DV-BE-LC_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_SMD +Samtec_HLE-108-02-xxx-DV-BE_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-BE, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_SMD +Samtec_HLE-108-02-xxx-DV-LC_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_SMD +Samtec_HLE-108-02-xxx-DV_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xxx-DV, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_SMD +Samtec_HLE-109-02-xxx-DV-A_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-A, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_SMD +Samtec_HLE-109-02-xxx-DV-BE-A_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE-A, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_SMD +Samtec_HLE-109-02-xxx-DV-BE-LC_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_SMD +Samtec_HLE-109-02-xxx-DV-BE_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-BE, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_SMD +Samtec_HLE-109-02-xxx-DV-LC_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_SMD +Samtec_HLE-109-02-xxx-DV_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xxx-DV, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_SMD +Samtec_HLE-110-02-xxx-DV-A_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-A, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_SMD +Samtec_HLE-110-02-xxx-DV-BE-A_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE-A, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_SMD +Samtec_HLE-110-02-xxx-DV-BE-LC_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_SMD +Samtec_HLE-110-02-xxx-DV-BE_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-BE, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_SMD +Samtec_HLE-110-02-xxx-DV-LC_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_SMD +Samtec_HLE-110-02-xxx-DV_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xxx-DV, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_SMD +Samtec_HLE-111-02-xxx-DV-A_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-A, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_SMD +Samtec_HLE-111-02-xxx-DV-BE-A_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE-A, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_SMD +Samtec_HLE-111-02-xxx-DV-BE-LC_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_SMD +Samtec_HLE-111-02-xxx-DV-BE_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-BE, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_SMD +Samtec_HLE-111-02-xxx-DV-LC_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_SMD +Samtec_HLE-111-02-xxx-DV_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xxx-DV, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_SMD +Samtec_HLE-112-02-xxx-DV-A_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-A, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_SMD +Samtec_HLE-112-02-xxx-DV-BE-A_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE-A, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_SMD +Samtec_HLE-112-02-xxx-DV-BE-LC_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_SMD +Samtec_HLE-112-02-xxx-DV-BE_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-BE, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_SMD +Samtec_HLE-112-02-xxx-DV-LC_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_SMD +Samtec_HLE-112-02-xxx-DV_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xxx-DV, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_SMD +Samtec_HLE-113-02-xxx-DV-A_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-A, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_SMD +Samtec_HLE-113-02-xxx-DV-BE-A_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE-A, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_SMD +Samtec_HLE-113-02-xxx-DV-BE-LC_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_SMD +Samtec_HLE-113-02-xxx-DV-BE_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-BE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_SMD +Samtec_HLE-113-02-xxx-DV-LC_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_SMD +Samtec_HLE-113-02-xxx-DV_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xxx-DV, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_SMD +Samtec_HLE-114-02-xxx-DV-A_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_SMD +Samtec_HLE-114-02-xxx-DV-BE-A_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE-A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_SMD +Samtec_HLE-114-02-xxx-DV-BE-LC_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_SMD +Samtec_HLE-114-02-xxx-DV-BE_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-BE, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_SMD +Samtec_HLE-114-02-xxx-DV-LC_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_SMD +Samtec_HLE-114-02-xxx-DV_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xxx-DV, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_SMD +Samtec_HLE-115-02-xxx-DV-A_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-A, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_SMD +Samtec_HLE-115-02-xxx-DV-BE-A_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE-A, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_SMD +Samtec_HLE-115-02-xxx-DV-BE-LC_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_SMD +Samtec_HLE-115-02-xxx-DV-BE_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-BE, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_SMD +Samtec_HLE-115-02-xxx-DV-LC_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_SMD +Samtec_HLE-115-02-xxx-DV_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xxx-DV, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_SMD +Samtec_HLE-116-02-xxx-DV-A_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-A, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_SMD +Samtec_HLE-116-02-xxx-DV-BE-A_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE-A, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_SMD +Samtec_HLE-116-02-xxx-DV-BE-LC_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_SMD +Samtec_HLE-116-02-xxx-DV-BE_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-BE, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_SMD +Samtec_HLE-116-02-xxx-DV-LC_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_SMD +Samtec_HLE-116-02-xxx-DV_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xxx-DV, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_SMD +Samtec_HLE-117-02-xxx-DV-A_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-A, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_SMD +Samtec_HLE-117-02-xxx-DV-BE-A_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE-A, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_SMD +Samtec_HLE-117-02-xxx-DV-BE-LC_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_SMD +Samtec_HLE-117-02-xxx-DV-BE_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-BE, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_SMD +Samtec_HLE-117-02-xxx-DV-LC_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_SMD +Samtec_HLE-117-02-xxx-DV_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xxx-DV, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_SMD +Samtec_HLE-118-02-xxx-DV-A_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-A, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_SMD +Samtec_HLE-118-02-xxx-DV-BE-A_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE-A, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_SMD +Samtec_HLE-118-02-xxx-DV-BE-LC_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_SMD +Samtec_HLE-118-02-xxx-DV-BE_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-BE, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_SMD +Samtec_HLE-118-02-xxx-DV-LC_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_SMD +Samtec_HLE-118-02-xxx-DV_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xxx-DV, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_SMD +Samtec_HLE-119-02-xxx-DV-A_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-A, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_SMD +Samtec_HLE-119-02-xxx-DV-BE-A_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE-A, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_SMD +Samtec_HLE-119-02-xxx-DV-BE-LC_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_SMD +Samtec_HLE-119-02-xxx-DV-BE_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-BE, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_SMD +Samtec_HLE-119-02-xxx-DV-LC_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_SMD +Samtec_HLE-119-02-xxx-DV_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xxx-DV, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_SMD +Samtec_HLE-120-02-xxx-DV-A_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-A, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_SMD +Samtec_HLE-120-02-xxx-DV-BE-A_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE-A, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_SMD +Samtec_HLE-120-02-xxx-DV-BE-LC_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_SMD +Samtec_HLE-120-02-xxx-DV-BE_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-BE, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_SMD +Samtec_HLE-120-02-xxx-DV-LC_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_SMD +Samtec_HLE-120-02-xxx-DV_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xxx-DV, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_SMD +Samtec_HLE-121-02-xxx-DV-A_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-A, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_SMD +Samtec_HLE-121-02-xxx-DV-BE-A_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE-A, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_SMD +Samtec_HLE-121-02-xxx-DV-BE-LC_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_SMD +Samtec_HLE-121-02-xxx-DV-BE_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-BE, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_SMD +Samtec_HLE-121-02-xxx-DV-LC_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_SMD +Samtec_HLE-121-02-xxx-DV_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xxx-DV, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_SMD +Samtec_HLE-122-02-xxx-DV-A_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-A, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_SMD +Samtec_HLE-122-02-xxx-DV-BE-A_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE-A, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_SMD +Samtec_HLE-122-02-xxx-DV-BE-LC_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_SMD +Samtec_HLE-122-02-xxx-DV-BE_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-BE, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_SMD +Samtec_HLE-122-02-xxx-DV-LC_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_SMD +Samtec_HLE-122-02-xxx-DV_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xxx-DV, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_SMD +Samtec_HLE-123-02-xxx-DV-A_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-A, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_SMD +Samtec_HLE-123-02-xxx-DV-BE-A_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE-A, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_SMD +Samtec_HLE-123-02-xxx-DV-BE-LC_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_SMD +Samtec_HLE-123-02-xxx-DV-BE_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-BE, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_SMD +Samtec_HLE-123-02-xxx-DV-LC_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_SMD +Samtec_HLE-123-02-xxx-DV_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xxx-DV, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_SMD +Samtec_HLE-124-02-xxx-DV-A_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-A, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_SMD +Samtec_HLE-124-02-xxx-DV-BE-A_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE-A, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_SMD +Samtec_HLE-124-02-xxx-DV-BE-LC_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_SMD +Samtec_HLE-124-02-xxx-DV-BE_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-BE, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_SMD +Samtec_HLE-124-02-xxx-DV-LC_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_SMD +Samtec_HLE-124-02-xxx-DV_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xxx-DV, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_SMD +Samtec_HLE-125-02-xxx-DV-A_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-A, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_SMD +Samtec_HLE-125-02-xxx-DV-BE-A_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE-A, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_SMD +Samtec_HLE-125-02-xxx-DV-BE-LC_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_SMD +Samtec_HLE-125-02-xxx-DV-BE_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-BE, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_SMD +Samtec_HLE-125-02-xxx-DV-LC_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_SMD +Samtec_HLE-125-02-xxx-DV_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xxx-DV, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_SMD +Samtec_HLE-126-02-xxx-DV-A_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-A, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_SMD +Samtec_HLE-126-02-xxx-DV-BE-A_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-A, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_SMD +Samtec_HLE-126-02-xxx-DV-BE-LC_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_SMD +Samtec_HLE-126-02-xxx-DV-BE_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_SMD +Samtec_HLE-126-02-xxx-DV-LC_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_SMD +Samtec_HLE-126-02-xxx-DV_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_SMD +Samtec_HLE-127-02-xxx-DV-A_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-A, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_SMD +Samtec_HLE-127-02-xxx-DV-BE-A_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE-A, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_SMD +Samtec_HLE-127-02-xxx-DV-BE-LC_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_SMD +Samtec_HLE-127-02-xxx-DV-BE_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-BE, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_SMD +Samtec_HLE-127-02-xxx-DV-LC_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_SMD +Samtec_HLE-127-02-xxx-DV_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xxx-DV, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_SMD +Samtec_HLE-128-02-xxx-DV-A_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-A, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_SMD +Samtec_HLE-128-02-xxx-DV-BE-A_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE-A, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_SMD +Samtec_HLE-128-02-xxx-DV-BE-LC_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_SMD +Samtec_HLE-128-02-xxx-DV-BE_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-BE, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_SMD +Samtec_HLE-128-02-xxx-DV-LC_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_SMD +Samtec_HLE-128-02-xxx-DV_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xxx-DV, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_SMD +Samtec_HLE-129-02-xxx-DV-A_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-A, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_SMD +Samtec_HLE-129-02-xxx-DV-BE-A_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE-A, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_SMD +Samtec_HLE-129-02-xxx-DV-BE-LC_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_SMD +Samtec_HLE-129-02-xxx-DV-BE_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-BE, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_SMD +Samtec_HLE-129-02-xxx-DV-LC_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_SMD +Samtec_HLE-129-02-xxx-DV_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xxx-DV, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_SMD +Samtec_HLE-130-02-xxx-DV-A_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-A, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_SMD +Samtec_HLE-130-02-xxx-DV-BE-A_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE-A, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_SMD +Samtec_HLE-130-02-xxx-DV-BE-LC_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_SMD +Samtec_HLE-130-02-xxx-DV-BE_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-BE, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_SMD +Samtec_HLE-130-02-xxx-DV-LC_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_SMD +Samtec_HLE-130-02-xxx-DV_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xxx-DV, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_SMD +Samtec_HLE-131-02-xxx-DV-A_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_SMD +Samtec_HLE-131-02-xxx-DV-BE-A_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE-A, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_SMD +Samtec_HLE-131-02-xxx-DV-BE-LC_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_SMD +Samtec_HLE-131-02-xxx-DV-BE_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-BE, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_SMD +Samtec_HLE-131-02-xxx-DV-LC_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_SMD +Samtec_HLE-131-02-xxx-DV_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xxx-DV, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_SMD +Samtec_HLE-132-02-xxx-DV-A_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-A, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_SMD +Samtec_HLE-132-02-xxx-DV-BE-A_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE-A, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_SMD +Samtec_HLE-132-02-xxx-DV-BE-LC_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_SMD +Samtec_HLE-132-02-xxx-DV-BE_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-BE, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_SMD +Samtec_HLE-132-02-xxx-DV-LC_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_SMD +Samtec_HLE-132-02-xxx-DV_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xxx-DV, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_SMD +Samtec_HLE-133-02-xxx-DV-A_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-A, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_SMD +Samtec_HLE-133-02-xxx-DV-BE-A_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE-A, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_SMD +Samtec_HLE-133-02-xxx-DV-BE-LC_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_SMD +Samtec_HLE-133-02-xxx-DV-BE_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-BE, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_SMD +Samtec_HLE-133-02-xxx-DV-LC_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_SMD +Samtec_HLE-133-02-xxx-DV_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xxx-DV, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_SMD +Samtec_HLE-134-02-xxx-DV-A_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-A, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_SMD +Samtec_HLE-134-02-xxx-DV-BE-A_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE-A, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_SMD +Samtec_HLE-134-02-xxx-DV-BE-LC_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_SMD +Samtec_HLE-134-02-xxx-DV-BE_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-BE, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_SMD +Samtec_HLE-134-02-xxx-DV-LC_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_SMD +Samtec_HLE-134-02-xxx-DV_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xxx-DV, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_SMD +Samtec_HLE-135-02-xxx-DV-A_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-A, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_SMD +Samtec_HLE-135-02-xxx-DV-BE-A_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE-A, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_SMD +Samtec_HLE-135-02-xxx-DV-BE-LC_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_SMD +Samtec_HLE-135-02-xxx-DV-BE_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-BE, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_SMD +Samtec_HLE-135-02-xxx-DV-LC_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_SMD +Samtec_HLE-135-02-xxx-DV_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xxx-DV, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_SMD +Samtec_HLE-136-02-xxx-DV-A_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-A, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_SMD +Samtec_HLE-136-02-xxx-DV-BE-A_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE-A, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_SMD +Samtec_HLE-136-02-xxx-DV-BE-LC_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_SMD +Samtec_HLE-136-02-xxx-DV-BE_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-BE, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_SMD +Samtec_HLE-136-02-xxx-DV-LC_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_SMD +Samtec_HLE-136-02-xxx-DV_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xxx-DV, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_SMD +Samtec_HLE-137-02-xxx-DV-A_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-A, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_SMD +Samtec_HLE-137-02-xxx-DV-BE-A_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE-A, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_SMD +Samtec_HLE-137-02-xxx-DV-BE-LC_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_SMD +Samtec_HLE-137-02-xxx-DV-BE_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-BE, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_SMD +Samtec_HLE-137-02-xxx-DV-LC_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_SMD +Samtec_HLE-137-02-xxx-DV_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xxx-DV, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_SMD +Samtec_HLE-138-02-xxx-DV-A_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-A, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_SMD +Samtec_HLE-138-02-xxx-DV-BE-A_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE-A, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_SMD +Samtec_HLE-138-02-xxx-DV-BE-LC_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_SMD +Samtec_HLE-138-02-xxx-DV-BE_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-BE, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_SMD +Samtec_HLE-138-02-xxx-DV-LC_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_SMD +Samtec_HLE-138-02-xxx-DV_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xxx-DV, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_SMD +Samtec_HLE-139-02-xxx-DV-A_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-A, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_SMD +Samtec_HLE-139-02-xxx-DV-BE-A_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE-A, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_SMD +Samtec_HLE-139-02-xxx-DV-BE-LC_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_SMD +Samtec_HLE-139-02-xxx-DV-BE_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-BE, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_SMD +Samtec_HLE-139-02-xxx-DV-LC_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_SMD +Samtec_HLE-139-02-xxx-DV_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xxx-DV, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_SMD +Samtec_HLE-140-02-xxx-DV-A_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-A, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_SMD +Samtec_HLE-140-02-xxx-DV-BE-A_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE-A, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_SMD +Samtec_HLE-140-02-xxx-DV-BE-LC_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_SMD +Samtec_HLE-140-02-xxx-DV-BE_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_SMD +Samtec_HLE-140-02-xxx-DV-LC_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_SMD +Samtec_HLE-140-02-xxx-DV_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_SMD +Samtec_HLE-141-02-xxx-DV-A_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-A, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_SMD +Samtec_HLE-141-02-xxx-DV-BE-A_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE-A, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_SMD +Samtec_HLE-141-02-xxx-DV-BE-LC_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_SMD +Samtec_HLE-141-02-xxx-DV-BE_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-BE, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_SMD +Samtec_HLE-141-02-xxx-DV-LC_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_SMD +Samtec_HLE-141-02-xxx-DV_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xxx-DV, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_SMD +Samtec_HLE-142-02-xxx-DV-A_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-A, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_SMD +Samtec_HLE-142-02-xxx-DV-BE-A_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE-A, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_SMD +Samtec_HLE-142-02-xxx-DV-BE-LC_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_SMD +Samtec_HLE-142-02-xxx-DV-BE_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-BE, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_SMD +Samtec_HLE-142-02-xxx-DV-LC_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_SMD +Samtec_HLE-142-02-xxx-DV_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xxx-DV, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_SMD +Samtec_HLE-143-02-xxx-DV-A_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-A, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_SMD +Samtec_HLE-143-02-xxx-DV-BE-A_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE-A, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_SMD +Samtec_HLE-143-02-xxx-DV-BE-LC_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_SMD +Samtec_HLE-143-02-xxx-DV-BE_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-BE, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_SMD +Samtec_HLE-143-02-xxx-DV-LC_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_SMD +Samtec_HLE-143-02-xxx-DV_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xxx-DV, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_SMD +Samtec_HLE-144-02-xxx-DV-A_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-A, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_SMD +Samtec_HLE-144-02-xxx-DV-BE-A_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE-A, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_SMD +Samtec_HLE-144-02-xxx-DV-BE-LC_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_SMD +Samtec_HLE-144-02-xxx-DV-BE_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-BE, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_SMD +Samtec_HLE-144-02-xxx-DV-LC_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_SMD +Samtec_HLE-144-02-xxx-DV_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xxx-DV, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_SMD +Samtec_HLE-145-02-xxx-DV-A_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-A, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_SMD +Samtec_HLE-145-02-xxx-DV-BE-A_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE-A, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_SMD +Samtec_HLE-145-02-xxx-DV-BE-LC_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_SMD +Samtec_HLE-145-02-xxx-DV-BE_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-BE, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_SMD +Samtec_HLE-145-02-xxx-DV-LC_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_SMD +Samtec_HLE-145-02-xxx-DV_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xxx-DV, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_SMD +Samtec_HLE-146-02-xxx-DV-A_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-A, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_SMD +Samtec_HLE-146-02-xxx-DV-BE-A_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE-A, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_SMD +Samtec_HLE-146-02-xxx-DV-BE-LC_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_SMD +Samtec_HLE-146-02-xxx-DV-BE_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-BE, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_SMD +Samtec_HLE-146-02-xxx-DV-LC_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_SMD +Samtec_HLE-146-02-xxx-DV_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xxx-DV, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_SMD +Samtec_HLE-147-02-xxx-DV-A_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-A, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_SMD +Samtec_HLE-147-02-xxx-DV-BE-A_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE-A, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_SMD +Samtec_HLE-147-02-xxx-DV-BE-LC_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_SMD +Samtec_HLE-147-02-xxx-DV-BE_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-BE, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_SMD +Samtec_HLE-147-02-xxx-DV-LC_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_SMD +Samtec_HLE-147-02-xxx-DV_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xxx-DV, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_SMD +Samtec_HLE-148-02-xxx-DV-A_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-A, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_SMD +Samtec_HLE-148-02-xxx-DV-BE-A_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE-A, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_SMD +Samtec_HLE-148-02-xxx-DV-BE-LC_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_SMD +Samtec_HLE-148-02-xxx-DV-BE_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-BE, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_SMD +Samtec_HLE-148-02-xxx-DV-LC_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_SMD +Samtec_HLE-148-02-xxx-DV_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xxx-DV, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_SMD +Samtec_HLE-149-02-xxx-DV-A_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-A, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_SMD +Samtec_HLE-149-02-xxx-DV-BE-A_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE-A, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_SMD +Samtec_HLE-149-02-xxx-DV-BE-LC_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_SMD +Samtec_HLE-149-02-xxx-DV-BE_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-BE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_SMD +Samtec_HLE-149-02-xxx-DV-LC_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_SMD +Samtec_HLE-149-02-xxx-DV_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xxx-DV, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_SMD +Samtec_HLE-150-02-xxx-DV-A_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-A, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_SMD +Samtec_HLE-150-02-xxx-DV-BE-A_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE-A, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_SMD +Samtec_HLE-150-02-xxx-DV-BE-LC_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_SMD +Samtec_HLE-150-02-xxx-DV-BE_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-BE, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_SMD +Samtec_HLE-150-02-xxx-DV-LC_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_SMD +Samtec_HLE-150-02-xxx-DV_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xxx-DV, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_THT +Samtec_HLE-104-02-xx-DV-PE-LC_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-PE-LC, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_THT +Samtec_HLE-104-02-xx-DV-PE_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-PE (compatible alternatives: HLE-104-02-xx-DV-PE-BE), 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_THT +Samtec_HLE-104-02-xx-DV-TE_2x04_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-104-02-xx-DV-TE, 4 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +8 +8 +Connector_Samtec_HLE_THT +Samtec_HLE-105-02-xx-DV-PE-LC_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-PE-LC, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_THT +Samtec_HLE-105-02-xx-DV-PE_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-PE (compatible alternatives: HLE-105-02-xx-DV-PE-BE), 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_THT +Samtec_HLE-105-02-xx-DV-TE_2x05_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-105-02-xx-DV-TE, 5 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +10 +10 +Connector_Samtec_HLE_THT +Samtec_HLE-106-02-xx-DV-PE-LC_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-PE-LC, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_THT +Samtec_HLE-106-02-xx-DV-PE_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-PE (compatible alternatives: HLE-106-02-xx-DV-PE-BE), 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_THT +Samtec_HLE-106-02-xx-DV-TE_2x06_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-106-02-xx-DV-TE, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +12 +12 +Connector_Samtec_HLE_THT +Samtec_HLE-107-02-xx-DV-PE-LC_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-PE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_THT +Samtec_HLE-107-02-xx-DV-PE_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-PE (compatible alternatives: HLE-107-02-xx-DV-PE-BE), 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_THT +Samtec_HLE-107-02-xx-DV-TE_2x07_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-107-02-xx-DV-TE, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +14 +14 +Connector_Samtec_HLE_THT +Samtec_HLE-108-02-xx-DV-PE-LC_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE-LC, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_THT +Samtec_HLE-108-02-xx-DV-PE_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-PE (compatible alternatives: HLE-108-02-xx-DV-PE-BE), 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_THT +Samtec_HLE-108-02-xx-DV-TE_2x08_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-108-02-xx-DV-TE, 8 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +16 +16 +Connector_Samtec_HLE_THT +Samtec_HLE-109-02-xx-DV-PE-LC_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-PE-LC, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_THT +Samtec_HLE-109-02-xx-DV-PE_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-PE (compatible alternatives: HLE-109-02-xx-DV-PE-BE), 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_THT +Samtec_HLE-109-02-xx-DV-TE_2x09_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-109-02-xx-DV-TE, 9 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +18 +18 +Connector_Samtec_HLE_THT +Samtec_HLE-110-02-xx-DV-PE-LC_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-PE-LC, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_THT +Samtec_HLE-110-02-xx-DV-PE_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-PE (compatible alternatives: HLE-110-02-xx-DV-PE-BE), 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_THT +Samtec_HLE-110-02-xx-DV-TE_2x10_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-110-02-xx-DV-TE, 10 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +20 +20 +Connector_Samtec_HLE_THT +Samtec_HLE-111-02-xx-DV-PE-LC_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-PE-LC, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_THT +Samtec_HLE-111-02-xx-DV-PE_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-PE (compatible alternatives: HLE-111-02-xx-DV-PE-BE), 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_THT +Samtec_HLE-111-02-xx-DV-TE_2x11_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-111-02-xx-DV-TE, 11 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +22 +22 +Connector_Samtec_HLE_THT +Samtec_HLE-112-02-xx-DV-PE-LC_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-PE-LC, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_THT +Samtec_HLE-112-02-xx-DV-PE_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-PE (compatible alternatives: HLE-112-02-xx-DV-PE-BE), 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_THT +Samtec_HLE-112-02-xx-DV-TE_2x12_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-112-02-xx-DV-TE, 12 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +24 +24 +Connector_Samtec_HLE_THT +Samtec_HLE-113-02-xx-DV-PE-LC_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-PE-LC, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_THT +Samtec_HLE-113-02-xx-DV-PE_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-PE (compatible alternatives: HLE-113-02-xx-DV-PE-BE), 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_THT +Samtec_HLE-113-02-xx-DV-TE_2x13_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-113-02-xx-DV-TE, 13 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +26 +26 +Connector_Samtec_HLE_THT +Samtec_HLE-114-02-xx-DV-PE-LC_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-PE-LC, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_THT +Samtec_HLE-114-02-xx-DV-PE_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-PE (compatible alternatives: HLE-114-02-xx-DV-PE-BE), 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_THT +Samtec_HLE-114-02-xx-DV-TE_2x14_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-114-02-xx-DV-TE, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +28 +28 +Connector_Samtec_HLE_THT +Samtec_HLE-115-02-xx-DV-PE-LC_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-PE-LC, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_THT +Samtec_HLE-115-02-xx-DV-PE_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-PE (compatible alternatives: HLE-115-02-xx-DV-PE-BE), 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_THT +Samtec_HLE-115-02-xx-DV-TE_2x15_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-115-02-xx-DV-TE, 15 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +30 +30 +Connector_Samtec_HLE_THT +Samtec_HLE-116-02-xx-DV-PE-LC_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-PE-LC, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_THT +Samtec_HLE-116-02-xx-DV-PE_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-PE (compatible alternatives: HLE-116-02-xx-DV-PE-BE), 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_THT +Samtec_HLE-116-02-xx-DV-TE_2x16_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-116-02-xx-DV-TE, 16 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +32 +32 +Connector_Samtec_HLE_THT +Samtec_HLE-117-02-xx-DV-PE-LC_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-PE-LC, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_THT +Samtec_HLE-117-02-xx-DV-PE_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-PE (compatible alternatives: HLE-117-02-xx-DV-PE-BE), 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_THT +Samtec_HLE-117-02-xx-DV-TE_2x17_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-117-02-xx-DV-TE, 17 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +34 +34 +Connector_Samtec_HLE_THT +Samtec_HLE-118-02-xx-DV-PE-LC_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-PE-LC, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_THT +Samtec_HLE-118-02-xx-DV-PE_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-PE (compatible alternatives: HLE-118-02-xx-DV-PE-BE), 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_THT +Samtec_HLE-118-02-xx-DV-TE_2x18_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-118-02-xx-DV-TE, 18 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +36 +36 +Connector_Samtec_HLE_THT +Samtec_HLE-119-02-xx-DV-PE-LC_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-PE-LC, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_THT +Samtec_HLE-119-02-xx-DV-PE_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-PE (compatible alternatives: HLE-119-02-xx-DV-PE-BE), 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_THT +Samtec_HLE-119-02-xx-DV-TE_2x19_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-119-02-xx-DV-TE, 19 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +38 +38 +Connector_Samtec_HLE_THT +Samtec_HLE-120-02-xx-DV-PE-LC_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-PE-LC, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_THT +Samtec_HLE-120-02-xx-DV-PE_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-PE (compatible alternatives: HLE-120-02-xx-DV-PE-BE), 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_THT +Samtec_HLE-120-02-xx-DV-TE_2x20_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-120-02-xx-DV-TE, 20 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +40 +40 +Connector_Samtec_HLE_THT +Samtec_HLE-121-02-xx-DV-PE-LC_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-PE-LC, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_THT +Samtec_HLE-121-02-xx-DV-PE_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-PE (compatible alternatives: HLE-121-02-xx-DV-PE-BE), 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_THT +Samtec_HLE-121-02-xx-DV-TE_2x21_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-121-02-xx-DV-TE, 21 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +42 +42 +Connector_Samtec_HLE_THT +Samtec_HLE-122-02-xx-DV-PE-LC_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-PE-LC, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_THT +Samtec_HLE-122-02-xx-DV-PE_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-PE (compatible alternatives: HLE-122-02-xx-DV-PE-BE), 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_THT +Samtec_HLE-122-02-xx-DV-TE_2x22_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-122-02-xx-DV-TE, 22 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +44 +44 +Connector_Samtec_HLE_THT +Samtec_HLE-123-02-xx-DV-PE-LC_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-PE-LC, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_THT +Samtec_HLE-123-02-xx-DV-PE_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-PE (compatible alternatives: HLE-123-02-xx-DV-PE-BE), 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_THT +Samtec_HLE-123-02-xx-DV-TE_2x23_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-123-02-xx-DV-TE, 23 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +46 +46 +Connector_Samtec_HLE_THT +Samtec_HLE-124-02-xx-DV-PE-LC_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-PE-LC, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_THT +Samtec_HLE-124-02-xx-DV-PE_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-PE (compatible alternatives: HLE-124-02-xx-DV-PE-BE), 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_THT +Samtec_HLE-124-02-xx-DV-TE_2x24_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-124-02-xx-DV-TE, 24 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +48 +48 +Connector_Samtec_HLE_THT +Samtec_HLE-125-02-xx-DV-PE-LC_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-PE-LC, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_THT +Samtec_HLE-125-02-xx-DV-PE_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-PE (compatible alternatives: HLE-125-02-xx-DV-PE-BE), 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_THT +Samtec_HLE-125-02-xx-DV-TE_2x25_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-125-02-xx-DV-TE, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +50 +50 +Connector_Samtec_HLE_THT +Samtec_HLE-126-02-xx-DV-PE-LC_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-PE-LC, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_THT +Samtec_HLE-126-02-xx-DV-PE_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-PE (compatible alternatives: HLE-126-02-xx-DV-PE-BE), 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_THT +Samtec_HLE-126-02-xx-DV-TE_2x26_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xx-DV-TE, 26 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +52 +52 +Connector_Samtec_HLE_THT +Samtec_HLE-127-02-xx-DV-PE-LC_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-PE-LC, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_THT +Samtec_HLE-127-02-xx-DV-PE_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-PE (compatible alternatives: HLE-127-02-xx-DV-PE-BE), 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_THT +Samtec_HLE-127-02-xx-DV-TE_2x27_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-127-02-xx-DV-TE, 27 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +54 +54 +Connector_Samtec_HLE_THT +Samtec_HLE-128-02-xx-DV-PE-LC_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-PE-LC, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_THT +Samtec_HLE-128-02-xx-DV-PE_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-PE (compatible alternatives: HLE-128-02-xx-DV-PE-BE), 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_THT +Samtec_HLE-128-02-xx-DV-TE_2x28_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-128-02-xx-DV-TE, 28 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +56 +56 +Connector_Samtec_HLE_THT +Samtec_HLE-129-02-xx-DV-PE-LC_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-PE-LC, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_THT +Samtec_HLE-129-02-xx-DV-PE_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-PE (compatible alternatives: HLE-129-02-xx-DV-PE-BE), 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_THT +Samtec_HLE-129-02-xx-DV-TE_2x29_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-129-02-xx-DV-TE, 29 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +58 +58 +Connector_Samtec_HLE_THT +Samtec_HLE-130-02-xx-DV-PE-LC_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-PE-LC, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_THT +Samtec_HLE-130-02-xx-DV-PE_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-PE (compatible alternatives: HLE-130-02-xx-DV-PE-BE), 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_THT +Samtec_HLE-130-02-xx-DV-TE_2x30_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-130-02-xx-DV-TE, 30 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +60 +60 +Connector_Samtec_HLE_THT +Samtec_HLE-131-02-xx-DV-PE-LC_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-PE-LC, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_THT +Samtec_HLE-131-02-xx-DV-PE_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-PE (compatible alternatives: HLE-131-02-xx-DV-PE-BE), 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_THT +Samtec_HLE-131-02-xx-DV-TE_2x31_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-131-02-xx-DV-TE, 31 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +62 +62 +Connector_Samtec_HLE_THT +Samtec_HLE-132-02-xx-DV-PE-LC_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-PE-LC, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_THT +Samtec_HLE-132-02-xx-DV-PE_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-PE (compatible alternatives: HLE-132-02-xx-DV-PE-BE), 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_THT +Samtec_HLE-132-02-xx-DV-TE_2x32_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-132-02-xx-DV-TE, 32 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +64 +64 +Connector_Samtec_HLE_THT +Samtec_HLE-133-02-xx-DV-PE-LC_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-PE-LC, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_THT +Samtec_HLE-133-02-xx-DV-PE_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-PE (compatible alternatives: HLE-133-02-xx-DV-PE-BE), 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_THT +Samtec_HLE-133-02-xx-DV-TE_2x33_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-133-02-xx-DV-TE, 33 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +66 +66 +Connector_Samtec_HLE_THT +Samtec_HLE-134-02-xx-DV-PE-LC_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-PE-LC, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_THT +Samtec_HLE-134-02-xx-DV-PE_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-PE (compatible alternatives: HLE-134-02-xx-DV-PE-BE), 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_THT +Samtec_HLE-134-02-xx-DV-TE_2x34_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-134-02-xx-DV-TE, 34 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +68 +68 +Connector_Samtec_HLE_THT +Samtec_HLE-135-02-xx-DV-PE-LC_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-PE-LC, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_THT +Samtec_HLE-135-02-xx-DV-PE_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-PE (compatible alternatives: HLE-135-02-xx-DV-PE-BE), 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_THT +Samtec_HLE-135-02-xx-DV-TE_2x35_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-135-02-xx-DV-TE, 35 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +70 +70 +Connector_Samtec_HLE_THT +Samtec_HLE-136-02-xx-DV-PE-LC_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-PE-LC, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_THT +Samtec_HLE-136-02-xx-DV-PE_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-PE (compatible alternatives: HLE-136-02-xx-DV-PE-BE), 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_THT +Samtec_HLE-136-02-xx-DV-TE_2x36_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-136-02-xx-DV-TE, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +72 +72 +Connector_Samtec_HLE_THT +Samtec_HLE-137-02-xx-DV-PE-LC_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-PE-LC, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_THT +Samtec_HLE-137-02-xx-DV-PE_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-PE (compatible alternatives: HLE-137-02-xx-DV-PE-BE), 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_THT +Samtec_HLE-137-02-xx-DV-TE_2x37_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-137-02-xx-DV-TE, 37 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +74 +74 +Connector_Samtec_HLE_THT +Samtec_HLE-138-02-xx-DV-PE-LC_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-PE-LC, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_THT +Samtec_HLE-138-02-xx-DV-PE_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-PE (compatible alternatives: HLE-138-02-xx-DV-PE-BE), 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_THT +Samtec_HLE-138-02-xx-DV-TE_2x38_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-138-02-xx-DV-TE, 38 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +76 +76 +Connector_Samtec_HLE_THT +Samtec_HLE-139-02-xx-DV-PE-LC_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-PE-LC, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_THT +Samtec_HLE-139-02-xx-DV-PE_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-PE (compatible alternatives: HLE-139-02-xx-DV-PE-BE), 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_THT +Samtec_HLE-139-02-xx-DV-TE_2x39_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-139-02-xx-DV-TE, 39 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +78 +78 +Connector_Samtec_HLE_THT +Samtec_HLE-140-02-xx-DV-PE-LC_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-PE-LC, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_THT +Samtec_HLE-140-02-xx-DV-PE_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-PE (compatible alternatives: HLE-140-02-xx-DV-PE-BE), 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_THT +Samtec_HLE-140-02-xx-DV-TE_2x40_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xx-DV-TE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +80 +80 +Connector_Samtec_HLE_THT +Samtec_HLE-141-02-xx-DV-PE-LC_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-PE-LC, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_THT +Samtec_HLE-141-02-xx-DV-PE_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-PE (compatible alternatives: HLE-141-02-xx-DV-PE-BE), 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_THT +Samtec_HLE-141-02-xx-DV-TE_2x41_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-141-02-xx-DV-TE, 41 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +82 +82 +Connector_Samtec_HLE_THT +Samtec_HLE-142-02-xx-DV-PE-LC_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-PE-LC, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_THT +Samtec_HLE-142-02-xx-DV-PE_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-PE (compatible alternatives: HLE-142-02-xx-DV-PE-BE), 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_THT +Samtec_HLE-142-02-xx-DV-TE_2x42_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-142-02-xx-DV-TE, 42 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +84 +84 +Connector_Samtec_HLE_THT +Samtec_HLE-143-02-xx-DV-PE-LC_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-PE-LC, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_THT +Samtec_HLE-143-02-xx-DV-PE_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-PE (compatible alternatives: HLE-143-02-xx-DV-PE-BE), 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_THT +Samtec_HLE-143-02-xx-DV-TE_2x43_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-143-02-xx-DV-TE, 43 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +86 +86 +Connector_Samtec_HLE_THT +Samtec_HLE-144-02-xx-DV-PE-LC_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-PE-LC, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_THT +Samtec_HLE-144-02-xx-DV-PE_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-PE (compatible alternatives: HLE-144-02-xx-DV-PE-BE), 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_THT +Samtec_HLE-144-02-xx-DV-TE_2x44_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-144-02-xx-DV-TE, 44 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +88 +88 +Connector_Samtec_HLE_THT +Samtec_HLE-145-02-xx-DV-PE-LC_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-PE-LC, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_THT +Samtec_HLE-145-02-xx-DV-PE_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-PE (compatible alternatives: HLE-145-02-xx-DV-PE-BE), 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_THT +Samtec_HLE-145-02-xx-DV-TE_2x45_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-145-02-xx-DV-TE, 45 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +90 +90 +Connector_Samtec_HLE_THT +Samtec_HLE-146-02-xx-DV-PE-LC_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-PE-LC, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_THT +Samtec_HLE-146-02-xx-DV-PE_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-PE (compatible alternatives: HLE-146-02-xx-DV-PE-BE), 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_THT +Samtec_HLE-146-02-xx-DV-TE_2x46_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-146-02-xx-DV-TE, 46 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +92 +92 +Connector_Samtec_HLE_THT +Samtec_HLE-147-02-xx-DV-PE-LC_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-PE-LC, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_THT +Samtec_HLE-147-02-xx-DV-PE_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-PE (compatible alternatives: HLE-147-02-xx-DV-PE-BE), 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_THT +Samtec_HLE-147-02-xx-DV-TE_2x47_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-147-02-xx-DV-TE, 47 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +94 +94 +Connector_Samtec_HLE_THT +Samtec_HLE-148-02-xx-DV-PE-LC_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-PE-LC, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_THT +Samtec_HLE-148-02-xx-DV-PE_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-PE (compatible alternatives: HLE-148-02-xx-DV-PE-BE), 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_THT +Samtec_HLE-148-02-xx-DV-TE_2x48_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-148-02-xx-DV-TE, 48 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +96 +96 +Connector_Samtec_HLE_THT +Samtec_HLE-149-02-xx-DV-PE-LC_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-PE-LC, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_THT +Samtec_HLE-149-02-xx-DV-PE_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-PE (compatible alternatives: HLE-149-02-xx-DV-PE-BE), 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_THT +Samtec_HLE-149-02-xx-DV-TE_2x49_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-149-02-xx-DV-TE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +98 +98 +Connector_Samtec_HLE_THT +Samtec_HLE-150-02-xx-DV-PE-LC_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-PE-LC, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_THT +Samtec_HLE-150-02-xx-DV-PE_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-PE (compatible alternatives: HLE-150-02-xx-DV-PE-BE), 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Samtec_HLE_THT +Samtec_HLE-150-02-xx-DV-TE_2x50_P2.54mm_Horizontal +Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-150-02-xx-DV-TE, 50 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator +connector Samtec HLE top entry +0 +100 +100 +Connector_Stocko +Stocko_MKS_1651-6-0-202_1x2_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +2 +2 +Connector_Stocko +Stocko_MKS_1652-6-0-202_1x2_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +2 +2 +Connector_Stocko +Stocko_MKS_1653-6-0-303_1x3_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +3 +3 +Connector_Stocko +Stocko_MKS_1654-6-0-404_1x4_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +4 +4 +Connector_Stocko +Stocko_MKS_1655-6-0-505_1x5_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +5 +5 +Connector_Stocko +Stocko_MKS_1656-6-0-606_1x6_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +6 +6 +Connector_Stocko +Stocko_MKS_1657-6-0-707_1x7_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +7 +7 +Connector_Stocko +Stocko_MKS_1658-6-0-808_1x8_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +8 +8 +Connector_Stocko +Stocko_MKS_1659-6-0-909_1x9_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +9 +9 +Connector_Stocko +Stocko_MKS_1660-6-0-1010_1x10_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +10 +10 +Connector_Stocko +Stocko_MKS_1661-6-0-1111_1x11_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +11 +11 +Connector_Stocko +Stocko_MKS_1662-6-0-1212_1x12_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +12 +12 +Connector_Stocko +Stocko_MKS_1663-6-0-1313_1x13_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +13 +13 +Connector_Stocko +Stocko_MKS_1664-6-0-1414_1x14_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +14 +14 +Connector_Stocko +Stocko_MKS_1665-6-0-1515_1x15_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +15 +15 +Connector_Stocko +Stocko_MKS_1666-6-0-1616_1x16_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +16 +16 +Connector_Stocko +Stocko_MKS_1667-6-0-1717_1x17_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +17 +17 +Connector_Stocko +Stocko_MKS_1668-6-0-1818_1x18_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +18 +18 +Connector_Stocko +Stocko_MKS_1669-6-0-1919_1x19_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +19 +19 +Connector_Stocko +Stocko_MKS_1670-6-0-2020_1x20_P2.50mm_Vertical +Stocko MKS 16xx series connector, (https://www.stocko-contact.com/downloads/steckverbindersystem-raster-2,5-mm.pdf#page=15), generated with kicad-footprint-generator +Stocko RFK MKS 16xx +0 +20 +20 +Connector_TE-Connectivity +TE_1-826576-3_1x13_P3.96mm_Vertical +TE, 1-826576-3, 13 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +13 +13 +Connector_TE-Connectivity +TE_1-826576-5_1x15_P3.96mm_Vertical +TE, 1-826576-5, 15 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +15 +15 +Connector_TE-Connectivity +TE_1-826576-6_1x16_P3.96mm_Vertical +TE, 1-826576-6, 16 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +16 +16 +Connector_TE-Connectivity +TE_1-826576-7_1x17_P3.96mm_Vertical +TE, 1-826576-7, 17 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +17 +17 +Connector_TE-Connectivity +TE_1-826576-8_1x18_P3.96mm_Vertical +TE, 1-826576-8, 18 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +18 +18 +Connector_TE-Connectivity +TE_2-826576-0_1x20_P3.96mm_Vertical +TE, 2-826576-0, 20 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +20 +20 +Connector_TE-Connectivity +TE_3-826576-6_1x36_P3.96mm_Vertical +TE, 3-826576-6, 36 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +36 +36 +Connector_TE-Connectivity +TE_826576-2_1x02_P3.96mm_Vertical +TE, 826576-2, 2 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +2 +2 +Connector_TE-Connectivity +TE_826576-3_1x03_P3.96mm_Vertical +TE, 826576-3, 3 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +3 +3 +Connector_TE-Connectivity +TE_826576-5_1x05_P3.96mm_Vertical +TE, 826576-5, 5 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +5 +5 +Connector_TE-Connectivity +TE_826576-6_1x06_P3.96mm_Vertical +TE, 826576-6, 6 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +6 +6 +Connector_TE-Connectivity +TE_826576-7_1x07_P3.96mm_Vertical +TE, 826576-7, 7 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +7 +7 +Connector_TE-Connectivity +TE_826576-8_1x08_P3.96mm_Vertical +TE, 826576-8, 8 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +8 +8 +Connector_TE-Connectivity +TE_826576-9_1x09_P3.96mm_Vertical +TE, 826576-9, 9 Pins (https://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=826576&DocType=Customer+Drawing&DocLang=English), generated with kicad-footprint-generator +connector TE 826576 vertical +0 +9 +9 +Connector_TE-Connectivity +TE_AMPSEAL_1-776087-x_3Rows_23_P0.4mm_Horizontal +Connector +TE 776087 +0 +23 +23 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770182-x_3x03_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770182-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +9 +9 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770186-x_3x04_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770186-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +12 +12 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770190-x_3x05_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770190-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +15 +15 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770621-x_2x06_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770621-x, 6 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +12 +12 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770858-x_2x05_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770858-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +10 +10 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770866-x_1x02_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770866-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +2 +2 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770870-x_1x03_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770870-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +3 +3 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770874-x_2x02_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770874-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +4 +4 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770875-x_2x03_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770875-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +6 +6 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770966-x_1x02_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770966-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +2 +2 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770967-x_1x03_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770967-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +3 +3 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770968-x_2x02_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770968-x, 2 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +4 +4 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770969-x_2x03_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770969-x, 3 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +6 +6 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770970-x_2x04_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770970-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +8 +8 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770971-x_2x05_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770971-x, 5 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +10 +10 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770972-x_2x06_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770972-x, 6 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +12 +12 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770973-x_2x07_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770973-x, 7 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +14 +14 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-770974-x_2x08_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770974-x, 8 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +16 +16 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794067-x_2x07_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794067-x, 7 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +14 +14 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794068-x_2x08_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794068-x, 8 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +16 +16 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794069-x_2x09_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794069-x, 9 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +18 +18 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794070-x_2x10_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794070-x, 10 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +20 +20 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794071-x_2x11_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794071-x, 11 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +22 +22 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794072-x_2x12_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794072-x, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +24 +24 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794073-x_2x04_P4.14mm_Vertical +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794073-x, 4 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK side entry +0 +8 +8 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794105-x_2x09_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794105-x, 9 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +18 +18 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794106-x_2x10_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794106-x, 10 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +20 +20 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794107-x_2x11_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794107-x, 11 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +22 +22 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794108-x_2x12_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794108-x, 12 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +24 +24 +Connector_TE-Connectivity +TE_MATE-N-LOK_1-794374-x_1x01_P4.14mm_Horizontal +Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-794374-x, 1 Pins per row (http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=82181_SOFTSHELL_HIGH_DENSITY&DocType=CS&DocLang=EN), generated with kicad-footprint-generator +connector TE MATE-N-LOK top entry +0 +1 +1 +Connector_TE-Connectivity +TE_MATE-N-LOK_350211-1_1x04_P5.08mm_Vertical +https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F350211%7FU5%7Fpdf%7FEnglish%7FENG_CD_350211_U5.pdf%7F350211-1 +connector TE MATE-N-LOK top entry ATA PATA IDE 5.25 inch floppy drive power +0 +4 +4 +Connector_USB +USB3_A_Molex_48393-001 +USB 3.0, type A, right angle (http://www.molex.com/pdm_docs/sd/483930003_sd.pdf) +USB 3.0 type A right angle +0 +13 +10 +Connector_USB +USB3_A_Plug_Wuerth_692112030100_Horizontal +USB type A Plug, Horizontal, http://katalog.we-online.de/em/datasheet/692112030100.pdf +usb A plug horizontal +0 +11 +10 +Connector_USB +USB_A_CNCTech_1001-011-01101_Horizontal +http://cnctech.us/pdfs/1001-011-01101.pdf +USB-A +0 +6 +5 +Connector_USB +USB_A_Molex_105057_Vertical +https://www.molex.com/pdm_docs/sd/1050570001_sd.pdf +USB A Vertical +0 +7 +5 +Connector_USB +USB_A_Stewart_SS-52100-001_Horizontal +USB A connector https://belfuse.com/resources/drawings/stewartconnector/dr-stw-ss-52100-001.pdf +USB_A Female Connector receptacle +0 +6 +5 +Connector_USB +USB_A_Wuerth_61400826021_Horizontal_Stacked +Stacked USB A connector http://katalog.we-online.de/em/datasheet/61400826021.pdf +Wuerth stacked USB_A +0 +12 +9 +Connector_USB +USB_B_Amphenol_MUSB-D511_Vertical_Rugged +A,phenol MUSB_D511, USB B female connector, straight, rugged, https://www.amphenolcanada.com/ProductSearch/drawings/AC/MUSBD511XX.pdf +USB_B_MUSB_Straight female connector straight rugged MUSB D511 +0 +6 +5 +Connector_USB +USB_B_OST_USB-B1HSxx_Horizontal +USB B receptacle, Horizontal, through-hole, http://www.on-shore.com/wp-content/uploads/2015/09/usb-b1hsxx.pdf +USB-B receptacle horizontal through-hole +0 +6 +5 +Connector_USB +USB_B_TE_5787834_Vertical +http://www.mouser.com/ds/2/418/NG_CD_5787834_A4-669110.pdf +USB_B USB B vertical female connector +0 +6 +5 +Connector_USB +USB_C_Plug_JAE_DX07P024AJ1 +Universal Serial Bus (USB) Shielded I/O Plug, Type C, Right Angle, Surface Mount, https://www.jae.com/en/searchfilter/?topics_keyword=DX07P024AJ1&mainItemSelect=1 +USB Type-C Plug Edge Mount +0 +30 +25 +Connector_USB +USB_C_Plug_Molex_105444 +Universal Serial Bus (USB) Shielded I/O Plug, Type C, Right Angle, Surface Mount, http://www.molex.com/pdm_docs/sd/1054440001_sd.pdf +USB Type-C Plug Edge Mount +0 +24 +23 +Connector_USB +USB_C_Receptacle_Amphenol_12401548E4-2A +USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A +USB C Type-C Receptacle Hybrid +0 +28 +25 +Connector_USB +USB_C_Receptacle_Amphenol_12401548E4-2A_CircularHoles +USB TYPE C, RA RCPT PCB, Hybrid, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401548E4%7e2A +USB C Type-C Receptacle Hybrid +0 +28 +25 +Connector_USB +USB_C_Receptacle_Amphenol_12401610E4-2A +USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A +USB C Type-C Receptacle SMD +0 +28 +25 +Connector_USB +USB_C_Receptacle_Amphenol_12401610E4-2A_CircularHoles +USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A +USB C Type-C Receptacle SMD +0 +28 +25 +Connector_USB +USB_C_Receptacle_GCT_USB4085 +USB 2.0 Type C Receptacle, https://gct.co/Files/Drawings/USB4085.pdf +USB Type-C Receptacle Through-hole Right angle +0 +20 +17 +Connector_USB +USB_C_Receptacle_HRO_TYPE-C-31-M-12 +USB Type-C receptacle for USB 2.0 and PD, http://www.krhro.com/uploads/soft/180320/1-1P320120243.pdf +usb usb-c 2.0 pd +0 +20 +17 +Connector_USB +USB_C_Receptacle_JAE_DX07S024WJ1R350 +http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ117219.pdf +USB C Type-C Receptacle SMD +0 +30 +25 +Connector_USB +USB_C_Receptacle_JAE_DX07S024WJ3R400 +USB TYPE C, VERT RCPT PCB, SMT, http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ117928.pdf +USB C Type-C Receptacle SMD +0 +28 +25 +Connector_USB +USB_C_Receptacle_Palconn_UTC16-G +http://www.palpilot.com/wp-content/uploads/2017/05/UTC027-GKN-OR-Rev-A.pdf +USB C Type-C Receptacle USB2.0 +0 +20 +17 +Connector_USB +USB_Micro-AB_Molex_47590-0001 +Micro USB AB receptable, right-angle inverted (https://www.molex.com/pdm_docs/sd/475900001_sd.pdf) +Micro AB USB SMD +0 +14 +6 +Connector_USB +USB_Micro-B_Amphenol_10103594-0001LF_Horizontal +Micro USB Type B 10103594-0001LF, http://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10103594.pdf +USB USB_B USB_micro USB_OTG +0 +17 +6 +Connector_USB +USB_Micro-B_GCT_USB3076-30-A +GCT Micro USB https://gct.co/files/drawings/usb3076.pdf +Micro-USB SMD Typ-B GCT +0 +11 +6 +Connector_USB +USB_Micro-B_Molex-105017-0001 +http://www.molex.com/pdm_docs/sd/1050170001_sd.pdf +Micro-USB SMD Typ-B +0 +13 +6 +Connector_USB +USB_Micro-B_Molex-105133-0001 +Molex Vertical Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330001_sd.pdf) +Micro-USB SMD Typ-B Vertical +0 +8 +6 +Connector_USB +USB_Micro-B_Molex-105133-0031 +Molex Vertical Micro USB Typ-B (http://www.molex.com/pdm_docs/sd/1051330031_sd.pdf) +Micro-USB SMD Typ-B Vertical +0 +8 +6 +Connector_USB +USB_Micro-B_Molex_47346-0001 +Micro USB B receptable with flange, bottom-mount, SMD, right-angle (http://www.molex.com/pdm_docs/sd/473460001_sd.pdf) +Micro B USB SMD +0 +11 +6 +Connector_USB +USB_Micro-B_Wuerth_614105150721_Vertical +USB Micro-B receptacle, through-hole, vertical, http://katalog.we-online.de/em/datasheet/614105150721.pdf +usb micro receptacle vertical +0 +7 +6 +Connector_USB +USB_Micro-B_Wuerth_614105150721_Vertical_CircularHoles +USB Micro-B receptacle, through-hole, vertical, http://katalog.we-online.de/em/datasheet/614105150721.pdf +usb micro receptacle vertical +0 +7 +6 +Connector_USB +USB_Micro-B_Wuerth_629105150521 +USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf +usb micro receptacle +0 +9 +6 +Connector_USB +USB_Micro-B_Wuerth_629105150521_CircularHoles +USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf +usb micro receptacle +0 +9 +6 +Connector_USB +USB_Mini-B_AdamTech_MUSB-B5-S-VT-TSMT-1_SMD_Vertical +http://www.adam-tech.com/upload/MUSB-B5-S-VT-TSMT-1.pdf +USB Mini-B +0 +7 +6 +Connector_USB +USB_Mini-B_Lumberg_2486_01_Horizontal +USB Mini-B 5-pin SMD connector, http://downloads.lumberg.com/datenblaetter/en/2486_01.pdf +USB USB_B USB_Mini connector +0 +9 +6 +Connector_USB +USB_Mini-B_Tensility_54-00023_Vertical +http://www.tensility.com/pdffiles/54-00023.pdf +usb mini receptacle vertical +0 +7 +6 +Connector_USB +USB_Mini-B_Tensility_54-00023_Vertical_CircularHoles +http://www.tensility.com/pdffiles/54-00023.pdf +usb mini receptacle vertical +0 +7 +6 +Connector_USB +USB_Mini-B_Wuerth_65100516121_Horizontal +Mini USB 2.0 Type B SMT Horizontal 5 Contacts (https://katalog.we-online.de/em/datasheet/65100516121.pdf) +Mini USB 2.0 Type B +0 +9 +6 +Connector_Wago +Wago_734-132_1x02_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-132 , 2 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +2 +2 +Connector_Wago +Wago_734-133_1x03_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-133 , 3 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +3 +3 +Connector_Wago +Wago_734-134_1x04_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-134 , 4 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +4 +4 +Connector_Wago +Wago_734-135_1x05_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-135 , 5 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +5 +5 +Connector_Wago +Wago_734-136_1x06_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-136 , 6 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +6 +6 +Connector_Wago +Wago_734-137_1x07_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-137 , 7 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +7 +7 +Connector_Wago +Wago_734-138_1x08_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-138 , 8 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +8 +8 +Connector_Wago +Wago_734-139_1x09_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-139 , 9 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +9 +9 +Connector_Wago +Wago_734-140_1x10_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-140 , 10 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +10 +10 +Connector_Wago +Wago_734-141_1x11_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-141 , 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +11 +11 +Connector_Wago +Wago_734-142_1x12_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-142 , 12 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +12 +12 +Connector_Wago +Wago_734-143_1x13_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-143 , 13 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +13 +13 +Connector_Wago +Wago_734-144_1x14_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-144 , 14 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +14 +14 +Connector_Wago +Wago_734-146_1x16_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-146 , 16 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +16 +16 +Connector_Wago +Wago_734-148_1x18_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-148 , 18 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +18 +18 +Connector_Wago +Wago_734-150_1x20_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-150 , 20 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +20 +20 +Connector_Wago +Wago_734-154_1x24_P3.50mm_Vertical +Molex 734 Male header (for PCBs); Straight solder pin 1 x 1 mm, 734-154 , 24 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago side entry +0 +24 +24 +Connector_Wago +Wago_734-162_1x02_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-162 , 2 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +2 +2 +Connector_Wago +Wago_734-163_1x03_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-163 , 3 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +3 +3 +Connector_Wago +Wago_734-164_1x04_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-164 , 4 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +4 +4 +Connector_Wago +Wago_734-165_1x05_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-165 , 5 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +5 +5 +Connector_Wago +Wago_734-166_1x06_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-166 , 6 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +6 +6 +Connector_Wago +Wago_734-167_1x07_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-167 , 7 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +7 +7 +Connector_Wago +Wago_734-168_1x08_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-168 , 8 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +8 +8 +Connector_Wago +Wago_734-169_1x09_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-169 , 9 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +9 +9 +Connector_Wago +Wago_734-170_1x10_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-170 , 10 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +10 +10 +Connector_Wago +Wago_734-171_1x11_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-171 , 11 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +11 +11 +Connector_Wago +Wago_734-172_1x12_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-172 , 12 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +12 +12 +Connector_Wago +Wago_734-173_1x13_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-173 , 13 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +13 +13 +Connector_Wago +Wago_734-174_1x14_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-174 , 14 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +14 +14 +Connector_Wago +Wago_734-176_1x16_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-176 , 16 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +16 +16 +Connector_Wago +Wago_734-178_1x18_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-178 , 18 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +18 +18 +Connector_Wago +Wago_734-180_1x20_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-180 , 20 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +20 +20 +Connector_Wago +Wago_734-184_1x24_P3.50mm_Horizontal +Molex 734 Male header (for PCBs); Angled solder pin 1 x 1 mm, 734-184 , 24 Pins (http://www.farnell.com/datasheets/2157639.pdf), generated with kicad-footprint-generator +connector Wago top entry +0 +24 +24 +Connector_Wire +SolderWirePad_1x01_Drill0.8mm +Wire solder connection +connector +0 +1 +1 +Connector_Wire +SolderWirePad_1x01_Drill1.2mm +Wire solder connection +connector +0 +1 +1 +Connector_Wire +SolderWirePad_1x01_Drill1.5mm +Wire solder connection +connector +0 +1 +1 +Connector_Wire +SolderWirePad_1x01_Drill1mm +Wire solder connection +connector +0 +1 +1 +Connector_Wire +SolderWirePad_1x01_Drill2.5mm +Wire solder connection +connector +0 +1 +1 +Connector_Wire +SolderWirePad_1x01_Drill2mm +Wire solder connection +connector +0 +1 +1 +Connector_Wire +SolderWirePad_1x01_SMD_5x10mm +Wire Pad, Square, SMD Pad, 5mm x 10mm, +MesurementPoint Square SMDPad 5mmx10mm +0 +1 +1 +Connector_Wire +SolderWirePad_1x02_P3.81mm_Drill0.8mm +Wire solder connection +connector +0 +2 +2 +Connector_Wire +SolderWirePad_1x02_P3.81mm_Drill1.2mm +Wire solder connection +connector +0 +2 +2 +Connector_Wire +SolderWirePad_1x02_P3.81mm_Drill1mm +Wire solder connection +connector +0 +2 +2 +Connector_Wire +SolderWirePad_1x02_P5.08mm_Drill1.5mm +Wire solder connection +connector +0 +2 +2 +Connector_Wire +SolderWirePad_1x02_P7.62mm_Drill2.5mm +Wire solder connection +connector +0 +2 +2 +Connector_Wire +SolderWirePad_1x02_P7.62mm_Drill2mm +Wire solder connection +connector +0 +2 +2 +Connector_Wire +SolderWirePad_1x03_P3.81mm_Drill1.2mm +Wire solder connection +connector +0 +3 +3 +Connector_Wire +SolderWirePad_1x03_P3.175mm_Drill0.8mm +Wire solder connection +connector +0 +3 +3 +Connector_Wire +SolderWirePad_1x03_P3.175mm_Drill1mm +Wire solder connection +connector +0 +3 +3 +Connector_Wire +SolderWirePad_1x03_P4.445mm_Drill1.5mm +Wire solder connection +connector +0 +3 +3 +Connector_Wire +SolderWirePad_1x03_P5.715mm_Drill2mm +Wire solder connection +connector +0 +3 +3 +Connector_Wire +SolderWirePad_1x03_P7.62mm_Drill2.5mm +Wire solder connection +connector +0 +3 +3 +Connector_Wire +SolderWirePad_1x04_P3.81mm_Drill1.2mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_1x04_P3.81mm_Drill1mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_1x04_P3.175mm_Drill0.8mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_1x04_P5.08mm_Drill1.5mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_1x04_P6.35mm_Drill2mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_1x04_P7.62mm_Drill2.5mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_2x02_P2.54mm_Drill0.8mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_2x02_P3.81mm_Drill1.2mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_2x02_P3.81mm_Drill1mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_2x02_P5.08mm_Drill1.5mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_2x02_P6.35mm_Drill2mm +Wire solder connection +connector +0 +4 +4 +Connector_Wire +SolderWirePad_2x02_P7.62mm_Drill2.5mm +Wire solder connection +connector +0 +4 +4 +Connector_Wuerth +Wuerth_WR-WTB_64800211622_1x02_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800211622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +2 +2 +Connector_Wuerth +Wuerth_WR-WTB_64800311622_1x03_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800311622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +3 +3 +Connector_Wuerth +Wuerth_WR-WTB_64800411622_1x04_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800411622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +4 +4 +Connector_Wuerth +Wuerth_WR-WTB_64800511622_1x05_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800511622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +5 +5 +Connector_Wuerth +Wuerth_WR-WTB_64800611622_1x06_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800611622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +6 +6 +Connector_Wuerth +Wuerth_WR-WTB_64800711622_1x07_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800711622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +7 +7 +Connector_Wuerth +Wuerth_WR-WTB_64800811622_1x08_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800811622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +8 +8 +Connector_Wuerth +Wuerth_WR-WTB_64800911622_1x09_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64800911622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +9 +9 +Connector_Wuerth +Wuerth_WR-WTB_64801011622_1x10_P1.50mm_Vertical +Wuerth WR-WTB series connector, 64801011622 (https://katalog.we-online.com/em/datasheet/6480xx11622.pdf), generated with kicad-footprint-generator +connector Wuerth WR-WTB vertical +0 +10 +10 +Converter_ACDC +Converter_ACDC_CUI_PBO-3-Sxx_THT_Vertical +ACDC-Converter, 3W, CUI PBO-3, THT https://www.cui.com/product/resource/pbo-3.pdf +Converter AC-DC THT Vertical +0 +6 +6 +Converter_ACDC +Converter_ACDC_Hahn_HS-400xx_THT +ACDC-Converter, 3W, Hahn-HS-400xx, THT https://www.schukat.com/schukat/schukat_cms_de.nsf/index/FrameView?OpenDocument&art=HS40009&wg=M7942 +Hahn ACDC-Converter THT +0 +4 +4 +Converter_ACDC +Converter_ACDC_HiLink_HLK-PMxx +ACDC-Converter, 3W, HiLink, HLK-PMxx, THT, http://www.hlktech.net/product_detail.php?ProId=54 +ACDC-Converter 3W THT HiLink board mount module +0 +4 +4 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-02-xx_SMD +ACDC-Converter, 3W, Meanwell, IRM-02, SMD, https://www.meanwell.com/Upload/PDF/IRM-02/IRM-02-SPEC.PDF +ACDC-Converter 3W +0 +14 +14 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-02-xx_THT +ACDC-Converter, 2W, Meanwell, IRM-02, THT, https://www.meanwell.co.uk/media/productPDF/IRM-02-spec.pdf +ACDC-Converter 2W THT +0 +4 +4 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-03-xx_SMD +ACDC-Converter, 3W, Meanwell, IRM-03, SMD, http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-03 +ACDC-Converter 3W +0 +14 +14 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-03-xx_THT +ACDC-Converter, 3W, Meanwell, IRM-03, THT, https://www.meanwell.com/Upload/PDF/IRM-03/IRM-03-SPEC.PDF +ACDC-Converter 3W THT +0 +5 +5 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-05-xx_THT +http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-05 +ACDC-Converter 5W Meanwell IRM-05 +0 +4 +4 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-10-xx_THT +http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-10 +ACDC-Converter 10W Meanwell IRM-10 +0 +4 +4 +Converter_ACDC +Converter_ACDC_MeanWell_IRM-20-xx_THT +ACDC-Converter, 20W, Meanwell, IRM-20, THT http://www.meanwell.com/webapp/product/search.aspx?prod=IRM-20 +ACDC-Converter 20W Meanwell IRM-20 +0 +4 +4 +Converter_ACDC +Converter_ACDC_RECOM_RAC01-xxSGB_THT +https://www.recom-power.com/pdf/Powerline-AC-DC/RAC01-GB.pdf +recom power ac dc rac01xxgb rac01-05sgb rac01-12sgb +0 +4 +4 +Converter_ACDC +Converter_ACDC_RECOM_RAC04-xxSGx_THT +https://www.recom-power.com/pdf/Powerline-AC-DC/RAC04-GA.pdf +recom power ac dc +0 +5 +5 +Converter_ACDC +Converter_ACDC_RECOM_RAC05-xxSK_THT +https://www.recom-power.com/pdf/Powerline-AC-DC/RAC05-K.pdf +recom power ac dc +0 +5 +5 +Converter_ACDC +Converter_ACDC_TRACO_TMG-15_THT +ACDC-Converter, TRACO, TMG Series 15 https://www.tracopower.com/products/tmg.pdf +ACDC-Converter TRACO TMG Series 15 +0 +4 +4 +Converter_ACDC +Converter_ACDC_TRACO_TMLM-04_THT +ACDC-Converter, TRACO, TMLM Series 04 https://www.tracopower.com/products/tmlm.pdf +ACDC-Converter TRACO TMLM Series 04 +0 +7 +7 +Converter_ACDC +Converter_ACDC_TRACO_TMLM-05_THT +ACDC-Converter, TRACO TMLM 05,https://www.tracopower.com/products/tmlm.pdf +ACDC-Converter TRACO TMLM 05 +0 +4 +4 +Converter_ACDC +Converter_ACDC_TRACO_TMLM-10-20_THT +ACDC-Converter, TRACO TMLM 10, TRACO TMLM 20, https://www.tracopower.com/products/tmlm.pdf +ACDC-Converter TRACO TMLM 10 and TMLM 20 +0 +4 +4 +Converter_ACDC +Converter_ACDC_Vigortronix_VTX-214-010-xxx_THT +Vigortronix VTX-214-010-xxx serie of ACDC converter, http://www.vigortronix.com/10WattACDCPCBPowerModule.aspx +Vigortronix VTX-214-010-xxx serie of ACDC converter +0 +4 +4 +Converter_ACDC +Converter_ACDC_Vigortronix_VTX-214-015-1xx_THT +Vigortronix VTX-214-010-xxx serie of ACDC converter, http://www.vigortronix.com/10WattACDCPCBPowerModule.aspx +Vigortronix VTX-214-010-xxx serie of ACDC converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_Artesyn_ATA_SMD +DCDC-Converter, Artesyn, ATA Series, 3W Single and Dual Output, 1500VDC Isolation, 24.0x13.7x8.0mm https://www.artesyn.com/power/assets/ata_series_ds_01apr2015_79c25814fd.pdf https://www.artesyn.com/power/assets/trn_dc-dc_ata_3w_series_releas1430412818_techref.pdf +DCDC SMD +0 +7 +7 +Converter_DCDC +Converter_DCDC_Bothhand_CFUDxxxx_THT +DCDC-Converter, BOTHHAND, Type CFxxxx-Serie, (Very dodgy url but was the only at hand), +DCDC-Converter BOTHHAND Type CFxxxx-Serie +0 +10 +10 +Converter_DCDC +Converter_DCDC_Bothhand_CFUSxxxxEH_THT +DCDC-Converter, BOTHHAND, Type CFxxxx-Serie, (Very dodgy url but was the only at hand), +DCDC-Converter BOTHHAND Type CFxxxx-Serie +0 +9 +9 +Converter_DCDC +Converter_DCDC_Bothhand_CFUSxxxx_THT +DCDC-Converter, BOTHHAND, Type CFxxxx-Serie, (Very dodgy url but was the only at hand), +DCDC-Converter BOTHHAND Type CFxxxx-Serie +0 +8 +8 +Converter_DCDC +Converter_DCDC_Cincon_EC5BExx_Dual_THT +DCDC-Converter, CINCON, EC5BExx, 18-36VDC to Dual output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/B%20CASE/SPEC-EC5BE-V24.pdf +DCDC-Converter CINCON EC5BExx 18-36VDC to Dual output +0 +6 +6 +Converter_DCDC +Converter_DCDC_Cincon_EC5BExx_Single_THT +DCDC-Converter, CINCON, EC5BExx, 18-36VDC to dual output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/B%20CASE/SPEC-EC5BE-V24.pdf +DCDC-Converter CINCON EC5BExx 18-36VDC to dual output +0 +4 +4 +Converter_DCDC +Converter_DCDC_Cincon_EC6Cxx_Dual-Triple_THT +DCDC-Converter, CINCON, EC6Cxx, dual or tripple output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf +DCDC-Converter CINCON EC6Cxx dual or tripple output +0 +7 +7 +Converter_DCDC +Converter_DCDC_Cincon_EC6Cxx_Single_THT +DCDC-Converter, CINCON, EC6Cxx, single output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf +DCDC-Converter CINCON EC6Cxx single output +0 +6 +6 +Converter_DCDC +Converter_DCDC_MeanWell_NID30_THT +Meanwell DCDC non-isolated converter SIP module, http://www.meanwell.com/webapp/product/search.aspx?prod=nid30 +DCDC non-isolated converter +0 +11 +11 +Converter_DCDC +Converter_DCDC_MeanWell_NID60_THT +MeanWell NID60, http://www.meanwell.com/Upload/PDF/NID60/NID60-SPEC.PDF +MeanWell NID60 +0 +11 +11 +Converter_DCDC +Converter_DCDC_Murata_MGJ2DxxxxxxSC_THT +Murata MGJ2DxxxxxxSC, 19.5x9.8x12.5mm, 5.2kVDC Isolated, 2W, SIP package style, https://power.murata.com/data/power/ncl/kdc_mgj2.pdf +Murata MGJ2DxxxxxxSC +0 +5 +5 +Converter_DCDC +Converter_DCDC_Murata_MGJ3 +Murata MGJ3, 5.2kVDC Isolated 3W Gate Drive, 15V/5V/5V Configurable, 22.61x23.11x14.19mm, https://power.murata.com/datasheet?/data/power/ncl/kdc_mgj3.pdf +DCDC SMD +0 +7 +7 +Converter_DCDC +Converter_DCDC_Murata_NCS1SxxxxSC_THT +Murata NCS1SxxxxSC https://power.murata.com/data/power/ncl/kdc_ncs1.pdf (Script generated with StandardBox.py) (Murata NCS1SxxxxSC https://power.murata.com/data/power/ncl/kdc_ncs1.pdf) +Murata NCS1SxxxxSC +0 +5 +5 +Converter_DCDC +Converter_DCDC_RECOM_R-78B-2.0_THT +DCDC-Converter, RECOM, RECOM_R-78B-2.0, SIP-3, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78Bxx-2.0.pdf +dc-dc recom buck sip-3 pitch 2.54mm +0 +3 +3 +Converter_DCDC +Converter_DCDC_RECOM_R-78E-0.5_THT +DCDC-Converter, RECOM, RECOM_R-78E-0.5, SIP-3, pitch 2.54mm, package size 11.6x8.5x10.4mm^3, https://www.recom-power.com/pdf/Innoline/R-78Exx-0.5.pdf +dc-dc recom buck sip-3 pitch 2.54mm +0 +3 +3 +Converter_DCDC +Converter_DCDC_RECOM_R-78HB-0.5L_THT +DCDC-Converter, RECOM, RECOM_R-78HB-0.5L, SIP-3, Horizontally Mounted, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78HBxx-0.5_L.pdf +dc-dc recom buck sip-3 pitch 2.54mm +0 +3 +3 +Converter_DCDC +Converter_DCDC_RECOM_R-78HB-0.5_THT +DCDC-Converter, RECOM, RECOM_R-78HB-0.5, SIP-3, pitch 2.54mm, package size 11.5x8.5x17.5mm^3, https://www.recom-power.com/pdf/Innoline/R-78HBxx-0.5_L.pdf +dc-dc recom buck sip-3 pitch 2.54mm +0 +3 +3 +Converter_DCDC +Converter_DCDC_RECOM_R-78S-0.1_THT +DCDC-Converter, RECOM, RECOM_R-78S-0.1, SIP-4, pitch 2.54mm, package size 11.6x8.5x10.4mm^3, https://www.recom-power.com/pdf/Innoline/R-78Sxx-0.1.pdf +dc-dc recom buck sip-4 pitch 2.54mm +0 +4 +4 +Converter_DCDC +Converter_DCDC_RECOM_R5xxxDA_THT +DCDC-Converter, RECOM, RECOM_R5xxxDA, SIP-12, Horizontally Mounted, pitch 2.54mm, package size 32.2x9.1x15mm^3, https://www.recom-power.com/pdf/Innoline/R-5xxxPA_DA.pdf +dc-dc recom buck sip-12 pitch 2.54mm +0 +12 +12 +Converter_DCDC +Converter_DCDC_RECOM_R5xxxPA_THT +DCDC-Converter, RECOM, RECOM_R5xxxPA, SIP-12, pitch 2.54mm, package size 32.2x9.1x15mm^3, https://www.recom-power.com/pdf/Innoline/R-5xxxPA_DA.pdf +dc-dc recom buck sip-12 pitch 2.54mm +0 +12 +12 +Converter_DCDC +Converter_DCDC_RECOM_RPMx.x-x.0 +https://www.recom-power.com/pdf/Innoline/RPM-6.0.pdf +dc-dc recom buck lga-25 pitch 2.29mm +0 +25 +25 +Converter_DCDC +Converter_DCDC_TRACO_TEN10-xxxx_Dual_THT +DCDC-Converter, TRACO, TEN10-xxxx, single output, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf +DCDC-Converter TRACO TEN10-xxxx single output +0 +5 +5 +Converter_DCDC +Converter_DCDC_TRACO_TEN10-xxxx_Single_THT +DCDC-Converter, TRACO, TEN10-xxxx, single output, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf +DCDC-Converter TRACO TEN10-xxxx single output +0 +4 +4 +Converter_DCDC +Converter_DCDC_TRACO_TEN10-xxxx_THT +DCDC-Converter, TRACO, TEN10-xxxx, https://assets.tracopower.com/20171102100522/TEN10/documents/ten10-datasheet.pdf +DCDC-Converter TRACO TEN10-xxxx +0 +4 +4 +Converter_DCDC +Converter_DCDC_TRACO_TEN20-xxxx-N4_THT +DCDC-Converter TRACO TEN20 Generic, https://assets.tracopower.com/20171102100522/TEN20/documents/ten20-datasheet.pdf +DCDC-Converter TRACO TEN20 Generic +0 +5 +5 +Converter_DCDC +Converter_DCDC_TRACO_TEN20-xxxx_THT +DCDC-Converter TRACO TEN20 Generic, https://assets.tracopower.com/20171102100522/TEN20/documents/ten20-datasheet.pdf +DCDC-Converter TRACO TEN20 Generic +0 +6 +6 +Converter_DCDC +Converter_DCDC_TRACO_TMR-1-xxxx_Dual_THT +DCDC-Converter, TRACO, TMR 1-xxxx, Dual output, Rev. March 21.2016 +DCDC-Converter TRACO TMR1-xxxx Dual_output +0 +5 +5 +Converter_DCDC +Converter_DCDC_TRACO_TMR-1-xxxx_Single_THT +DCDC-Converter, TRACO, TMR 1-xxxx, Single output, Rev. March 21.2016 +DCDC-Converter TRACO TMR1-xxxx Single_output +0 +4 +4 +Converter_DCDC +Converter_DCDC_TRACO_TMR-1SM_SMD +http://assets.tracopower.com/TMR1SM/documents/tmr1sm-datasheet.pdf +DCDC SMD TRACO TMR-1SM +0 +7 +7 +Converter_DCDC +Converter_DCDC_TRACO_TMR-2xxxxWI_THT +https://www.tracopower.com/products/tmr2wi.pdf +DCDC-Converter TRACO TMRxxxxWI Single/Dual_output +0 +7 +7 +Converter_DCDC +Converter_DCDC_TRACO_TMR-xxxx_THT +DCDC-Converter, TRACO, TMR xxxx, Single/Dual output, http://www.datasheetlib.com/datasheet/135136/tmr-2-2410e_traco-power.html?page=3#datasheet +DCDC-Converter TRACO TMRxxxx Single/Dual_output +0 +7 +7 +Converter_DCDC +Converter_DCDC_TRACO_TSR-1_THT +DCDC-Converter, TRACO, TSR 1-xxxx +DCDC-Converter TRACO TSR-1 +0 +3 +3 +Converter_DCDC +Converter_DCDC_XP_POWER-IA48xxD_THT +XP_POWER IA48xxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator +XP_POWER IA48xxD DIP DCDC-Converter +0 +6 +6 +Converter_DCDC +Converter_DCDC_XP_POWER-IA48xxS_THT +XP_POWER IA48xxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator +XP_POWER IA48xxS SIP DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_XP_POWER-IAxxxxD_THT +XP_POWER IAxxxxD, DIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator +XP_POWER IAxxxxD DIP DCDC-Converter +0 +6 +6 +Converter_DCDC +Converter_DCDC_XP_POWER-IAxxxxS_THT +XP_POWER IAxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IA.pdf), generated with kicad-footprint-generator +XP_POWER IAxxxxS SIP DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_XP_POWER-IHxxxxDH_THT +XP_POWER IHxxxxDH, DIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator +XP_POWER IHxxxxDH DIP DCDC-Converter +0 +6 +6 +Converter_DCDC +Converter_DCDC_XP_POWER-IHxxxxD_THT +XP_POWER IHxxxxD, DIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator +XP_POWER IHxxxxD DIP DCDC-Converter +0 +6 +6 +Converter_DCDC +Converter_DCDC_XP_POWER-IHxxxxSH_THT +XP_POWER IHxxxxSH, SIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator +XP_POWER IHxxxxSH SIP DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_XP_POWER-IHxxxxS_THT +XP_POWER IHxxxxS, SIP, (https://www.xppower.com/pdfs/SF_IH.pdf), generated with kicad-footprint-generator +XP_POWER IHxxxxS SIP DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_XP_POWER-ISU02_SMD +DCDC-Converter, XP POWER, ISU02 Series, 2W Single and Dual Output, 1500VDC Isolation, 19.0x17.0x8.7mm https://www.xppower.com/Portals/0/pdfs/SF_ISU02.pdf +DCDC SMD XP POWER ISU02 +0 +7 +7 +Converter_DCDC +Converter_DCDC_XP_POWER-ITQxxxxS-H_THT +XP_POWER ITQxxxxS-H, SIP, (https://www.xppower.com/pdfs/SF_ITQ.pdf), generated with kicad-footprint-generator +XP_POWER ITQxxxxS-H SIP DCDC-Converter +0 +6 +6 +Converter_DCDC +Converter_DCDC_XP_POWER-ITXxxxxSA_THT +XP_POWER ITXxxxxSA, SIP, (https://www.xppower.com/pdfs/SF_ITX.pdf), generated with kicad-footprint-generator +XP_POWER ITXxxxxSA SIP DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_XP_POWER-ITxxxxxS_THT +XP_POWER ITxxxxxS, SIP, (https://www.xppower.com/pdfs/SF_ITX.pdf https://www.xppower.com/pdfs/SF_ITQ.pdf), generated with kicad-footprint-generator +XP_POWER ITxxxxxS SIP DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_XP_POWER_JTExxxxDxx_THT +DCDC-Converter, XP POWER, Type JTE06 Series, Dual Output +DCDC-Converter XP_POWER JTE06 Dual +0 +8 +8 +Converter_DCDC +Converter_DCDC_muRata_CRE1xxxxxx3C_THT +Isolated 1W single output DC/DC, http://power.murata.com/data/power/ncl/kdc_cre1.pdf +Isolated 1W single output DC/DC +0 +4 +4 +Converter_DCDC +Converter_DCDC_muRata_CRE1xxxxxxDC_THT +Isloated DC-DC, http://power.murata.com/data/power/ncl/kdc_cre1.pdf +Isloated DC-DC +0 +4 +4 +Converter_DCDC +Converter_DCDC_muRata_CRE1xxxxxxSC_THT +http://power.murata.com/data/power/ncl/kdc_cre1.pdf +murata dc-dc transformer +0 +4 +4 +Converter_DCDC +Converter_DCDC_muRata_NMAxxxxDC_THT +Isolated 1W DCDC-Converter, http://power.murata.com/data/power/ncl/kdc_nma.pdf +Isolated 1W DCDC-Converter +0 +6 +6 +Converter_DCDC +Converter_DCDC_muRata_NMAxxxxSC_THT +muRata NMAxxxxSC footprint based on SIP7, http://power.murata.com/data/power/ncl/kdc_nma.pdf +muRata NMAxxxxSC DCDC-Converter +0 +5 +5 +Converter_DCDC +Converter_DCDC_muRata_NXE2SxxxxMC_THT +Isolated 2W Single Output SM DC/DC Converters, http://power.murata.com/data/power/ncl/kdc_nxe2.pdf +Isolated 2W Single Output SM DC/DC Converters +0 +5 +5 +Converter_DCDC +Converter_DCDC_muRata_OKI-78SR_Horizontal +https://power.murata.com/data/power/oki-78sr.pdf +78sr3.3 78sr5 78sr9 78sr12 78srXX +0 +3 +3 +Converter_DCDC +Converter_DCDC_muRata_OKI-78SR_Vertical +https://power.murata.com/data/power/oki-78sr.pdf +78sr3.3 78sr5 78sr9 78sr12 78srXX +0 +3 +3 +Crystal +Crystal_AT310_D3.0mm_L10.0mm_Horizontal +Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf +['AT310'] +0 +2 +2 +Crystal +Crystal_AT310_D3.0mm_L10.0mm_Horizontal_1EP_style1 +Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf +['AT310'] +0 +3 +3 +Crystal +Crystal_AT310_D3.0mm_L10.0mm_Horizontal_1EP_style2 +Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf +['AT310'] +0 +5 +3 +Crystal +Crystal_AT310_D3.0mm_L10.0mm_Vertical +Crystal THT AT310 10.0mm-10.5mm length 3.0mm diameter http://www.cinetech.com.tw/upload/2011/04/20110401165201.pdf +['AT310'] +0 +2 +2 +Crystal +Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal +Crystal THT C26-LF 6.5mm length 2.06mm diameter +['C26-LF'] +0 +2 +2 +Crystal +Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal_1EP_style1 +Crystal THT C26-LF 6.5mm length 2.06mm diameter +['C26-LF'] +0 +3 +3 +Crystal +Crystal_C26-LF_D2.1mm_L6.5mm_Horizontal_1EP_style2 +Crystal THT C26-LF 6.5mm length 2.06mm diameter +['C26-LF'] +0 +5 +3 +Crystal +Crystal_C26-LF_D2.1mm_L6.5mm_Vertical +Crystal THT C26-LF 6.5mm length 2.06mm diameter +['C26-LF'] +0 +2 +2 +Crystal +Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal +Crystal THT C38-LF 8.0mm length 3.0mm diameter +['C38-LF'] +0 +2 +2 +Crystal +Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal_1EP_style1 +Crystal THT C38-LF 8.0mm length 3.0mm diameter +['C38-LF'] +0 +3 +3 +Crystal +Crystal_C38-LF_D3.0mm_L8.0mm_Horizontal_1EP_style2 +Crystal THT C38-LF 8.0mm length 3.0mm diameter +['C38-LF'] +0 +5 +3 +Crystal +Crystal_C38-LF_D3.0mm_L8.0mm_Vertical +Crystal THT C38-LF 8.0mm length 3.0mm diameter +['C38-LF'] +0 +2 +2 +Crystal +Crystal_DS10_D1.0mm_L4.3mm_Horizontal +Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS10'] +0 +2 +2 +Crystal +Crystal_DS10_D1.0mm_L4.3mm_Horizontal_1EP_style1 +Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS10'] +0 +3 +3 +Crystal +Crystal_DS10_D1.0mm_L4.3mm_Horizontal_1EP_style2 +Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS10'] +0 +5 +3 +Crystal +Crystal_DS10_D1.0mm_L4.3mm_Vertical +Crystal THT DS10 4.3mm length 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS10'] +0 +2 +2 +Crystal +Crystal_DS15_D1.5mm_L5.0mm_Horizontal +Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS15'] +0 +2 +2 +Crystal +Crystal_DS15_D1.5mm_L5.0mm_Horizontal_1EP_style1 +Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS15'] +0 +3 +3 +Crystal +Crystal_DS15_D1.5mm_L5.0mm_Horizontal_1EP_style2 +Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS15'] +0 +5 +3 +Crystal +Crystal_DS15_D1.5mm_L5.0mm_Vertical +Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS15'] +0 +2 +2 +Crystal +Crystal_DS26_D2.0mm_L6.0mm_Horizontal +Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS26'] +0 +2 +2 +Crystal +Crystal_DS26_D2.0mm_L6.0mm_Horizontal_1EP_style1 +Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS26'] +0 +3 +3 +Crystal +Crystal_DS26_D2.0mm_L6.0mm_Horizontal_1EP_style2 +Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS26'] +0 +5 +3 +Crystal +Crystal_DS26_D2.0mm_L6.0mm_Vertical +Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS26'] +0 +2 +2 +Crystal +Crystal_HC18-U_Horizontal +Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC18-U_Horizontal_1EP_style1 +Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC18-U_Horizontal_1EP_style2 +Crystal THT HC-18/U http://5hertz.com/pdfs/04404_D.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC18-U_Vertical +Crystal THT HC-18/U, http://5hertz.com/pdfs/04404_D.pdf +THT crystalHC-18/U +0 +2 +2 +Crystal +Crystal_HC33-U_Horizontal +Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC33-U_Horizontal_1EP_style1 +Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC33-U_Horizontal_1EP_style2 +Crystal THT HC-33/U http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC33-U_Vertical +Crystal THT HC-33/U, http://pdi.bentech-taiwan.com/PDI/GEN20SPEV20HC3320U.pdf +THT crystalHC-33/U +0 +2 +2 +Crystal +Crystal_HC35-U +Crystal, Quarz, HC35/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/TO71xx.pdf +Crystal Quarz HC35/U +0 +3 +3 +Crystal +Crystal_HC49-4H_Vertical +Crystal THT HC-49-4H http://5hertz.com/pdfs/04404_D.pdf +THT crystalHC-49-4H +0 +2 +2 +Crystal +Crystal_HC49-U-3Pin_Vertical +Crystal THT HC-49/U, 3pin-version, http://www.raltron.com/products/pdfspecs/crystal_hc_49_45_51.pdf +THT crystalHC-49/U +0 +3 +3 +Crystal +Crystal_HC49-U_Horizontal +Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC49-U_Horizontal_1EP_style1 +Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC49-U_Horizontal_1EP_style2 +Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC49-U_Vertical +Crystal THT HC-49/U http://5hertz.com/pdfs/04404_D.pdf +THT crystalHC-49/U +0 +2 +2 +Crystal +Crystal_HC50_Horizontal +Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC50_Horizontal_1EP_style1 +Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC50_Horizontal_1EP_style2 +Crystal THT HC-50 http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC50_Vertical +Crystal THT HC-50, http://www.crovencrystals.com/croven_pdf/HC-50_Crystal_Holder_Rev_00.pdf +THT crystalHC-50 +0 +2 +2 +Crystal +Crystal_HC51-U_Vertical +Crystal THT HC-51/U, http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf +THT crystalHC-51/U +0 +2 +2 +Crystal +Crystal_HC51_Horizontal +Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC51_Horizontal_1EP_style1 +Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC51_Horizontal_1EP_style2 +Crystal THT HC-51 http://www.crovencrystals.com/croven_pdf/HC-51_Crystal_Holder_Rev_00.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC52-6mm_Horizontal +Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC52-6mm_Horizontal_1EP_style1 +Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC52-6mm_Horizontal_1EP_style2 +Crystal THT HC-51/6mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC52-6mm_Vertical +Crystal THT HC-52/6mm, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystalHC-49/U +0 +2 +2 +Crystal +Crystal_HC52-8mm_Horizontal +Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC52-8mm_Horizontal_1EP_style1 +Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC52-8mm_Horizontal_1EP_style2 +Crystal THT HC-51/8mm http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC52-8mm_Vertical +Crystal THT HC-52/8mm, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystalHC-49/U +0 +2 +2 +Crystal +Crystal_HC52-U-3Pin_Vertical +Crystal THT HC-52/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystalHC-52/U +0 +3 +3 +Crystal +Crystal_HC52-U_Horizontal +Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +2 +2 +Crystal +Crystal_HC52-U_Horizontal_1EP_style1 +Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +3 +3 +Crystal +Crystal_HC52-U_Horizontal_1EP_style2 +Crystal THT HC-51/U http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal +0 +5 +3 +Crystal +Crystal_HC52-U_Vertical +Crystal THT HC-52/U, http://www.kvg-gmbh.de/assets/uploads/files/product_pdfs/XS71xx.pdf +THT crystal HC-52/U +0 +2 +2 +Crystal +Crystal_Round_D1.0mm_Vertical +Crystal THT DS10 1.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS10'] +0 +2 +2 +Crystal +Crystal_Round_D1.5mm_Vertical +Crystal THT DS15 5.0mm length 1.5mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS15'] +0 +2 +2 +Crystal +Crystal_Round_D2.0mm_Vertical +Crystal THT DS26 6.0mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/DS-Series.pdf +['DS26'] +0 +2 +2 +Crystal +Crystal_Round_D3.0mm_Vertical +Crystal THT C38-LF 8.0mm length 3.0mm diameter +['C38-LF'] +0 +2 +2 +Crystal +Crystal_SMD_0603-2Pin_6.0x3.5mm +SMD Crystal SERIES SMD0603/2 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-2.pdf, 6.0x3.5mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_0603-2Pin_6.0x3.5mm_HandSoldering +SMD Crystal SERIES SMD0603/2 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-2.pdf, hand-soldering, 6.0x3.5mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_0603-4Pin_6.0x3.5mm +SMD Crystal SERIES SMD0603/4 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-4.pdf, 6.0x3.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_0603-4Pin_6.0x3.5mm_HandSoldering +SMD Crystal SERIES SMD0603/4 http://www.petermann-technik.de/fileadmin/petermann/pdf/SMD0603-4.pdf, hand-soldering, 6.0x3.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_2012-2Pin_2.0x1.2mm +SMD Crystal 2012/2 http://txccrystal.com/images/pdf/9ht11.pdf, 2.0x1.2mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_2012-2Pin_2.0x1.2mm_HandSoldering +SMD Crystal 2012/2 http://txccrystal.com/images/pdf/9ht11.pdf, hand-soldering, 2.0x1.2mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_2016-4Pin_2.0x1.6mm +SMD Crystal SERIES SMD2016/4 http://www.q-crystal.com/upload/5/2015552223166229.pdf, 2.0x1.6mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_2520-4Pin_2.5x2.0mm +SMD Crystal SERIES SMD2520/4 http://www.newxtal.com/UploadFiles/Images/2012-11-12-09-29-09-776.pdf, 2.5x2.0mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_3215-2Pin_3.2x1.5mm +SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf +SMD SMT Crystal +0 +2 +2 +Crystal +Crystal_SMD_3225-4Pin_3.2x2.5mm +SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_3225-4Pin_3.2x2.5mm_HandSoldering +SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_5032-2Pin_5.0x3.2mm +SMD Crystal SERIES SMD2520/2 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, 5.0x3.2mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_5032-2Pin_5.0x3.2mm_HandSoldering +SMD Crystal SERIES SMD2520/2 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_5032-4Pin_5.0x3.2mm +SMD Crystal SERIES SMD2520/4 http://www.icbase.com/File/PDF/HKC/HKC00061008.pdf, 5.0x3.2mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_7050-2Pin_7.0x5.0mm +SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_7050-2Pin_7.0x5.0mm_HandSoldering +SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_7050-4Pin_7.0x5.0mm +SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_Abracon_ABM3-2Pin_5.0x3.2mm +Abracon Miniature Ceramic Smd Crystal ABM3 http://www.abracon.com/Resonators/abm3.pdf, 5.0x3.2mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_Abracon_ABM3-2Pin_5.0x3.2mm_HandSoldering +Abracon Miniature Ceramic Smd Crystal ABM3 http://www.abracon.com/Resonators/abm3.pdf, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_Abracon_ABM3B-4Pin_5.0x3.2mm +Abracon Miniature Ceramic Smd Crystal ABM3B http://www.abracon.com/Resonators/abm3b.pdf, 5.0x3.2mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_Abracon_ABM3C-4Pin_5.0x3.2mm +Abracon Miniature Ceramic Smd Crystal ABM3C http://www.abracon.com/Resonators/abm3c.pdf, 5.0x3.2mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_Abracon_ABM7-2Pin_6.0x3.5mm +SMD Crystal Abracon ABM7, https://abracon.com/Resonators/abm7.pdf +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_Abracon_ABM8G-4Pin_3.2x2.5mm +Abracon Miniature Ceramic Smd Crystal ABM8G http://www.abracon.com/Resonators/ABM8G.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_Abracon_ABM10-4Pin_2.5x2.0mm +Abracon Miniature Ceramic Smd Crystal ABM10 http://www.abracon.com/Resonators/ABM10.pdf +SMD SMT crystal Abracon ABM10 +0 +4 +4 +Crystal +Crystal_SMD_Abracon_ABS25-4Pin_8.0x3.8mm +Abracon Miniature Ceramic SMD Crystal ABS25 https://abracon.com/Resonators/abs25.pdf, 8.0x3.8mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_ECS_CSM3X-2Pin_7.6x4.1mm +http://www.ecsxtal.com/store/pdf/CSM-3X.pdf +Crystal CSM-3X +0 +2 +2 +Crystal +Crystal_SMD_EuroQuartz_EQ161-2Pin_3.2x1.5mm +SMD Crystal EuroQuartz EQ161 series http://cdn-reichelt.de/documents/datenblatt/B400/PG32768C.pdf, 3.2x1.5mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_EuroQuartz_EQ161-2Pin_3.2x1.5mm_HandSoldering +SMD Crystal EuroQuartz EQ161 series http://cdn-reichelt.de/documents/datenblatt/B400/PG32768C.pdf, hand-soldering, 3.2x1.5mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_EuroQuartz_MJ-4Pin_5.0x3.2mm +SMD Crystal EuroQuartz MJ series http://cdn-reichelt.de/documents/datenblatt/B400/MJ.pdf, 5.0x3.2mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_MJ-4Pin_5.0x3.2mm_HandSoldering +SMD Crystal EuroQuartz MJ series http://cdn-reichelt.de/documents/datenblatt/B400/MJ.pdf, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_MQ-4Pin_7.0x5.0mm +SMD Crystal EuroQuartz MQ series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, 7.0x5.0mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_MQ-4Pin_7.0x5.0mm_HandSoldering +SMD Crystal EuroQuartz MQ series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_MQ2-2Pin_7.0x5.0mm +SMD Crystal EuroQuartz MQ2 series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, 7.0x5.0mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_EuroQuartz_MQ2-2Pin_7.0x5.0mm_HandSoldering +SMD Crystal EuroQuartz MQ2 series http://cdn-reichelt.de/documents/datenblatt/B400/MQ.pdf, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_EuroQuartz_MT-4Pin_3.2x2.5mm +SMD Crystal EuroQuartz MT series http://cdn-reichelt.de/documents/datenblatt/B400/MT.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_MT-4Pin_3.2x2.5mm_HandSoldering +SMD Crystal EuroQuartz MT series http://cdn-reichelt.de/documents/datenblatt/B400/MT.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_X22-4Pin_2.5x2.0mm +SMD Crystal EuroQuartz X22 series http://cdn-reichelt.de/documents/datenblatt/B400/DS_X22.pdf, 2.5x2.0mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_EuroQuartz_X22-4Pin_2.5x2.0mm_HandSoldering +SMD Crystal EuroQuartz X22 series http://cdn-reichelt.de/documents/datenblatt/B400/DS_X22.pdf, hand-soldering, 2.5x2.0mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_FOX_FE-2Pin_7.5x5.0mm +crystal Ceramic Resin Sealed SMD http://www.foxonline.com/pdfs/fe.pdf, 7.5x5.0mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_FOX_FE-2Pin_7.5x5.0mm_HandSoldering +crystal Ceramic Resin Sealed SMD http://www.foxonline.com/pdfs/fe.pdf, hand-soldering, 7.5x5.0mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_FOX_FQ7050-2Pin_7.0x5.0mm +FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_FOX_FQ7050-2Pin_7.0x5.0mm_HandSoldering +FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_FOX_FQ7050-4Pin_7.0x5.0mm +FOX SMD Crystal SERIES SMD7050/4 https://www.foxonline.com/pdfs/FQ7050.pdf, 7.0x5.0mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_FrontierElectronics_FM206 +SMD Watch Crystal FrontierElectronics FM206 6.0mm length 1.9mm diameter http://www.chinafronter.com/wp-content/uploads/2013/12/FM206.pdf +['FM206'] +0 +3 +3 +Crystal +Crystal_SMD_G8-2Pin_3.2x1.5mm +SMD Crystal G8, 3.2x1.5mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_G8-2Pin_3.2x1.5mm_HandSoldering +SMD Crystal G8, hand-soldering, 3.2x1.5mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_HC49-SD +SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, 11.4x4.7mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_HC49-SD_HandSoldering +SMD Crystal HC-49-SD http://cdn-reichelt.de/documents/datenblatt/B400/xxx-HC49-SMD.pdf, hand-soldering, 11.4x4.7mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC1V-T1A-2Pin_8.0x3.7mm +SMD Crystal MicroCrystal CC1V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC1V-T1A.pdf, 8.0x3.7mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC1V-T1A-2Pin_8.0x3.7mm_HandSoldering +SMD Crystal MicroCrystal CC1V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC1V-T1A.pdf, hand-soldering, 8.0x3.7mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm +SMD Crystal MicroCrystal CC4V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC4V-T1A.pdf, 5.0x1.9mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC4V-T1A-2Pin_5.0x1.9mm_HandSoldering +SMD Crystal MicroCrystal CC4V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC4V-T1A.pdf, hand-soldering, 5.0x1.9mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC5V-T1A-2Pin_4.1x1.5mm +SMD Crystal MicroCrystal CC5V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC5V-T1A.pdf, 4.1x1.5mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC5V-T1A-2Pin_4.1x1.5mm_HandSoldering +SMD Crystal MicroCrystal CC5V-T1A series http://cdn-reichelt.de/documents/datenblatt/B400/CC5V-T1A.pdf, hand-soldering, 4.1x1.5mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC7V-T1A-2Pin_3.2x1.5mm +SMD Crystal MicroCrystal CC7V-T1A/CM7V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC7V-T1A.pdf, 3.2x1.5mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC7V-T1A-2Pin_3.2x1.5mm_HandSoldering +SMD Crystal MicroCrystal CC7V-T1A/CM7V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CC1V-T1A.pdf, hand-soldering, 3.2x1.5mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC8V-T1A-2Pin_2.0x1.2mm +SMD Crystal MicroCrystal CC8V-T1A/CM8V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CC8V-T1A.pdf, 2.0x1.2mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CC8V-T1A-2Pin_2.0x1.2mm_HandSoldering +SMD Crystal MicroCrystal CC8V-T1A/CM8V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CC8V-T1A.pdf, hand-soldering, 2.0x1.2mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CM9V-T1A-2Pin_1.6x1.0mm +SMD Crystal MicroCrystal CM9V-T1A series https://www.microcrystal.com/fileadmin/Media/Products/32kHz/Datasheet/CM9V-T1A.pdf, 1.6x1.0mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_CM9V-T1A-2Pin_1.6x1.0mm_HandSoldering +SMD Crystal MicroCrystal CM9V-T1A series http://www.microcrystal.com/images/_Product-Documentation/01_TF_ceramic_Packages/01_Datasheet/CM9V-T1A.pdf, hand-soldering, 1.6x1.0mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_MicroCrystal_MS1V-T1K +SMD Watch Crystal MicroCrystal MS1V-T1K 6.1mm length 2.0mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/MS1V-T1K.pdf +['MS1V-T1K'] +0 +3 +3 +Crystal +Crystal_SMD_MicroCrystal_MS3V-T1R +SMD Watch Crystal MicroCrystal MS3V-T1R 5.2mm length 1.4mm diameter http://www.microcrystal.com/images/_Product-Documentation/03_TF_metal_Packages/01_Datasheet/MS3V-T1R.pdf +['MS3V-T1R'] +0 +3 +3 +Crystal +Crystal_SMD_Qantek_QC5CB-2Pin_5x3.2mm +SMD Crystal Qantek QC5CB, https://www.qantek.com/tl_files/products/crystals/QC5CB.pdf +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_SeikoEpson_FA238-4Pin_3.2x2.5mm +crystal Epson Toyocom FA-238 https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_FA238-4Pin_3.2x2.5mm_HandSoldering +crystal Epson Toyocom FA-238 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_FA238V-4Pin_3.2x2.5mm +crystal Epson Toyocom FA-238 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_FA238V-4Pin_3.2x2.5mm_HandSoldering +crystal Epson Toyocom FA-238 series http://www.mouser.com/ds/2/137/1721499-465440.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MA406-4Pin_11.7x4.0mm +SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 11.7x4.0mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MA406-4Pin_11.7x4.0mm_HandSoldering +SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 11.7x4.0mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MA505-2Pin_12.7x5.1mm +SMD Crystal Seiko Epson MC-505 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 12.7x5.1mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_SeikoEpson_MA505-2Pin_12.7x5.1mm_HandSoldering +SMD Crystal Seiko Epson MC-505 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 12.7x5.1mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_SeikoEpson_MA506-4Pin_12.7x5.1mm +SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, 12.7x5.1mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MA506-4Pin_12.7x5.1mm_HandSoldering +SMD Crystal Seiko Epson MC-506 http://media.digikey.com/pdf/Data%20Sheets/Epson%20PDFs/MA-505,506.pdf, hand-soldering, 12.7x5.1mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC146-4Pin_6.7x1.5mm +SMD Crystal Seiko Epson MC-146 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, 6.7x1.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC146-4Pin_6.7x1.5mm_HandSoldering +SMD Crystal Seiko Epson MC-146 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, hand-soldering, 6.7x1.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC156-4Pin_7.1x2.5mm +SMD Crystal Seiko Epson MC-156 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, 7.1x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC156-4Pin_7.1x2.5mm_HandSoldering +SMD Crystal Seiko Epson MC-156 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-156_en.pdf, hand-soldering, 7.1x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC306-4Pin_8.0x3.2mm +SMD Crystal Seiko Epson MC-306 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 8.0x3.2mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC306-4Pin_8.0x3.2mm_HandSoldering +SMD Crystal Seiko Epson MC-306 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 8.0x3.2mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC405-2Pin_9.6x4.1mm +SMD Crystal Seiko Epson MC-405 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 9.6x4.1mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_SeikoEpson_MC405-2Pin_9.6x4.1mm_HandSoldering +SMD Crystal Seiko Epson MC-405 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 9.6x4.1mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_SeikoEpson_MC406-4Pin_9.6x4.1mm +SMD Crystal Seiko Epson MC-406 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, 9.6x4.1mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_MC406-4Pin_9.6x4.1mm_HandSoldering +SMD Crystal Seiko Epson MC-406 https://support.epson.biz/td/api/doc_check.php?dl=brief_MC-306_en.pdf, hand-soldering, 9.6x4.1mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm +crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering +crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_TXC_7A-2Pin_5x3.2mm +SMD Crystal TXC 7A http://txccrystal.com/images/pdf/7a.pdf +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_TXC_7M-4Pin_3.2x2.5mm +SMD Crystal TXC 7M http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package +SMD SMT crystal +0 +4 +4 +Crystal +Crystal_SMD_TXC_7M-4Pin_3.2x2.5mm_HandSoldering +SMD Crystal TXC 7M http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal hand-soldering +0 +4 +4 +Crystal +Crystal_SMD_TXC_9HT11-2Pin_2.0x1.2mm +SMD Crystal TXC 9HT11 http://txccrystal.com/images/pdf/9ht11.pdf, 2.0x1.2mm^2 package +SMD SMT crystal +0 +2 +2 +Crystal +Crystal_SMD_TXC_9HT11-2Pin_2.0x1.2mm_HandSoldering +SMD Crystal TXC 9HT11 http://txccrystal.com/images/pdf/9ht11.pdf, hand-soldering, 2.0x1.2mm^2 package +SMD SMT crystal hand-soldering +0 +2 +2 +Crystal +Crystal_SMD_TXC_AX_8045-2Pin_8.0x4.5mm +http://www.txccrystal.com/images/pdf/ax-automotive.pdf +SMD SMT crystal +0 +2 +2 +Crystal +Resonator-2Pin_W6.0mm_H3.0mm +Ceramic Resomator/Filter 6.0x3.0mm^2, length*width=6.0x3.0mm^2 package, package length=6.0mm, package width=3.0mm, 2 pins +THT ceramic resonator filter +0 +2 +2 +Crystal +Resonator-2Pin_W7.0mm_H2.5mm +Ceramic Resomator/Filter 7.0x2.5mm^2, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 2 pins +THT ceramic resonator filter +0 +2 +2 +Crystal +Resonator-2Pin_W8.0mm_H3.5mm +Ceramic Resomator/Filter 8.0x3.5mm^2, length*width=8.0x3.5mm^2 package, package length=8.0mm, package width=3.5mm, 2 pins +THT ceramic resonator filter +0 +2 +2 +Crystal +Resonator-2Pin_W10.0mm_H5.0mm +Ceramic Resomator/Filter 10.0x5.0 RedFrequency MG/MT/MX series, http://www.red-frequency.com/download/datenblatt/redfrequency-datenblatt-ir-zta.pdf, length*width=10.0x5.0mm^2 package, package length=10.0mm, package width=5.0mm, 2 pins +THT ceramic resonator filter +0 +2 +2 +Crystal +Resonator-3Pin_W6.0mm_H3.0mm +Ceramic Resomator/Filter 6.0x3.0mm^2, length*width=6.0x3.0mm^2 package, package length=6.0mm, package width=3.0mm, 3 pins +THT ceramic resonator filter +0 +3 +3 +Crystal +Resonator-3Pin_W7.0mm_H2.5mm +Ceramic Resomator/Filter 7.0x2.5mm^2, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins +THT ceramic resonator filter +0 +3 +3 +Crystal +Resonator-3Pin_W8.0mm_H3.5mm +Ceramic Resomator/Filter 8.0x3.5mm^2, length*width=8.0x3.5mm^2 package, package length=8.0mm, package width=3.5mm, 3 pins +THT ceramic resonator filter +0 +3 +3 +Crystal +Resonator-3Pin_W10.0mm_H5.0mm +Ceramic Resomator/Filter 10.0x5.0mm^2 RedFrequency MG/MT/MX series, http://www.red-frequency.com/download/datenblatt/redfrequency-datenblatt-ir-zta.pdf, length*width=10.0x5.0mm^2 package, package length=10.0mm, package width=5.0mm, 3 pins +THT ceramic resonator filter +0 +3 +3 +Crystal +Resonator_SMD-3Pin_7.2x3.0mm +SMD Resomator/Filter 7.2x3.0mm, Murata CSTCC8M00G53-R0; 8MHz resonator, SMD, Farnell (Element 14) #1170435, http://www.farnell.com/datasheets/19296.pdf?_ga=1.247244932.122297557.1475167906, 7.2x3.0mm^2 package +SMD SMT ceramic resonator filter filter +0 +3 +3 +Crystal +Resonator_SMD-3Pin_7.2x3.0mm_HandSoldering +SMD Resomator/Filter 7.2x3.0mm, Murata CSTCC8M00G53-R0; 8MHz resonator, SMD, Farnell (Element 14) #1170435, http://www.farnell.com/datasheets/19296.pdf?_ga=1.247244932.122297557.1475167906, hand-soldering, 7.2x3.0mm^2 package +SMD SMT ceramic resonator filter filter hand-soldering +0 +3 +3 +Crystal +Resonator_SMD_muRata_CDSCB-2Pin_4.5x2.0mm +SMD Resomator/Filter Murata CDSCB, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 4.5x2.0mm^2 package +SMD SMT ceramic resonator filter filter +0 +2 +2 +Crystal +Resonator_SMD_muRata_CDSCB-2Pin_4.5x2.0mm_HandSoldering +SMD Resomator/Filter Murata CDSCB, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 4.5x2.0mm^2 package +SMD SMT ceramic resonator filter filter hand-soldering +0 +2 +2 +Crystal +Resonator_SMD_muRata_CSTxExxV-3Pin_3.0x1.1mm +SMD Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf +SMD SMT ceramic resonator filter +0 +3 +3 +Crystal +Resonator_SMD_muRata_CSTxExxV-3Pin_3.0x1.1mm_HandSoldering +SMD Resomator/Filter Murata CSTCE, https://www.murata.com/en-eu/products/productdata/8801162264606/SPEC-CSTNE16M0VH3C000R0.pdf +SMD SMT ceramic resonator filter +0 +3 +3 +Crystal +Resonator_SMD_muRata_SFECV-3Pin_6.9x2.9mm +SMD Resomator/Filter Murata SFECV, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 6.9x2.9mm^2 package +SMD SMT ceramic resonator filter filter +0 +3 +3 +Crystal +Resonator_SMD_muRata_SFECV-3Pin_6.9x2.9mm_HandSoldering +SMD Resomator/Filter Murata SFECV, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 6.9x2.9mm^2 package +SMD SMT ceramic resonator filter filter hand-soldering +0 +3 +3 +Crystal +Resonator_SMD_muRata_SFSKA-3Pin_7.9x3.8mm +SMD Resomator/Filter Murata SFSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 7.9x3.8mm^2 package +SMD SMT ceramic resonator filter filter +0 +3 +3 +Crystal +Resonator_SMD_muRata_SFSKA-3Pin_7.9x3.8mm_HandSoldering +SMD Resomator/Filter Murata SFSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 7.9x3.8mm^2 package +SMD SMT ceramic resonator filter filter hand-soldering +0 +3 +3 +Crystal +Resonator_SMD_muRata_TPSKA-3Pin_7.9x3.8mm +SMD Resomator/Filter Murata TPSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, 7.9x3.8mm^2 package +SMD SMT ceramic resonator filter filter +0 +3 +3 +Crystal +Resonator_SMD_muRata_TPSKA-3Pin_7.9x3.8mm_HandSoldering +SMD Resomator/Filter Murata TPSKA, http://cdn-reichelt.de/documents/datenblatt/B400/SFECV-107.pdf, hand-soldering, 7.9x3.8mm^2 package +SMD SMT ceramic resonator filter filter hand-soldering +0 +3 +3 +Crystal +Resonator_muRata_CSTLSxxxG-3Pin_W8.0mm_H3.0mm +Ceramic Resomator/Filter Murata CSTLSxxxG, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/timingdevice/ceralock/p17e.ashx, length*width=8.0x3.0mm^2 package, package length=8.0mm, package width=3.0mm, 3 pins +THT ceramic resonator filter CSTLSxxxG +0 +3 +3 +Crystal +Resonator_muRata_CSTLSxxxX-3Pin_W5.5mm_H3.0mm +Ceramic Resomator/Filter Murata CSTLSxxxX, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/timingdevice/ceralock/p17e.ashx, length*width=5.5x3.0mm^2 package, package length=5.5mm, package width=3.0mm, 3 pins +THT ceramic resonator filter CSTLSxxxX +0 +3 +3 +Crystal +Resonator_muRata_DSN6-3Pin_W7.0mm_H2.5mm +Ceramic Resomator/Filter Murata DSN6, http://cdn-reichelt.de/documents/datenblatt/B400/DSN6NC51H.pdf, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins +THT ceramic resonator filter DSN6 +0 +3 +3 +Crystal +Resonator_muRata_DSS6-3Pin_W7.0mm_H2.5mm +Ceramic Resomator/Filter Murata DSS6, http://cdn-reichelt.de/documents/datenblatt/B400/DSN6NC51H.pdf, length*width=7.0x2.5mm^2 package, package length=7.0mm, package width=2.5mm, 3 pins +THT ceramic resonator filter DSS6 +0 +3 +3 +Diode_SMD +D_0201_0603Metric +Diode SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +diode +0 +4 +2 +Diode_SMD +D_0402_1005Metric +Diode SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_0603_1608Metric +Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_0603_1608Metric_Castellated +Diode SMD 0603 (1608 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_0603_1608Metric_Pad1.05x0.95mm_HandSolder +Diode SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_0805_2012Metric +Diode SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_0805_2012Metric_Castellated +Diode SMD 0805 (2012 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_0805_2012Metric_Pad1.15x1.40mm_HandSolder +Diode SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_01005_0402Metric +Diode SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +diode +0 +4 +2 +Diode_SMD +D_1206_3216Metric +Diode SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_1206_3216Metric_Castellated +Diode SMD 1206 (3216 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_1206_3216Metric_Pad1.42x1.75mm_HandSolder +Diode SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_1210_3225Metric +Diode SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_1210_3225Metric_Castellated +Diode SMD 1210 (3225 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_1210_3225Metric_Pad1.42x2.65mm_HandSolder +Diode SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_1806_4516Metric +Diode SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_1806_4516Metric_Castellated +Diode SMD 1806 (4516 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_1806_4516Metric_Pad1.57x1.80mm_HandSolder +Diode SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_1812_4532Metric +Diode SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_1812_4532Metric_Castellated +Diode SMD 1812 (4532 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_1812_4532Metric_Pad1.30x3.40mm_HandSolder +Diode SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_2010_5025Metric +Diode SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_2010_5025Metric_Castellated +Diode SMD 2010 (5025 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_2010_5025Metric_Pad1.52x2.65mm_HandSolder +Diode SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_2114_3652Metric +Diode SMD 2114 (3652 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_2114_3652Metric_Castellated +Diode SMD 2114 (3652 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_2114_3652Metric_Pad1.85x3.75mm_HandSolder +Diode SMD 2114 (3652 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_2512_6332Metric +Diode SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_2512_6332Metric_Castellated +Diode SMD 2512 (6332 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_2512_6332Metric_Pad1.52x3.35mm_HandSolder +Diode SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_2816_7142Metric +Diode SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_2816_7142Metric_Castellated +Diode SMD 2816 (7142 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_2816_7142Metric_Pad3.20x4.45mm_HandSolder +Diode SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_3220_8050Metric +Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +Diode_SMD +D_3220_8050Metric_Castellated +Diode SMD 3220 (8050 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator +diode castellated +0 +2 +2 +Diode_SMD +D_3220_8050Metric_Pad2.65x5.15mm_HandSolder +Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator +diode handsolder +0 +2 +2 +Diode_SMD +D_MELF +Diode, MELF,, +Diode MELF +0 +2 +2 +Diode_SMD +D_MELF-RM10_Universal_Handsoldering +Diode, Universal, MELF, RM10, Handsoldering, SMD, Thruhole, +Diode Universal MELF RM10 Handsoldering SMD Thruhole +0 +2 +2 +Diode_SMD +D_MELF_Handsoldering +Diode MELF Handsoldering +Diode MELF Handsoldering +0 +2 +2 +Diode_SMD +D_MicroMELF +Diode, MicroMELF, Reflow Soldering, http://www.vishay.com/docs/85597/bzm55.pdf +MicroMELF Diode +0 +2 +2 +Diode_SMD +D_MicroMELF_Handsoldering +Diode, MicroMELF, Hand Soldering, http://www.vishay.com/docs/85597/bzm55.pdf +MicroMELF Diode +0 +2 +2 +Diode_SMD +D_MiniMELF +Diode Mini-MELF +Diode Mini-MELF +0 +2 +2 +Diode_SMD +D_MiniMELF_Handsoldering +Diode Mini-MELF Handsoldering +Diode Mini-MELF Handsoldering +0 +2 +2 +Diode_SMD +D_PowerDI-5 +PowerDI,Diode,Vishay,https://www.diodes.com/assets/Package-Files/PowerDI5.pdf +PowerDI diode vishay +0 +3 +2 +Diode_SMD +D_PowerDI-123 +http://www.diodes.com/_files/datasheets/ds30497.pdf +PowerDI diode vishay +0 +2 +2 +Diode_SMD +D_Powermite2_AK +Microsemi Powermite 2 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5341) +PowerMite2 +0 +2 +2 +Diode_SMD +D_Powermite2_KA +Microsemi Powermite 2 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5341) +PowerMite2 +0 +2 +2 +Diode_SMD +D_Powermite3 +Microsemi Powermite 3 SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5340) +PowerMite3 +0 +3 +3 +Diode_SMD +D_Powermite_AK +Microsemi Powermite SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5339, https://www.onsemi.com/pub/Collateral/457-04.PDF) +Powermite +0 +2 +2 +Diode_SMD +D_Powermite_KA +Microsemi Powermite SMD power package (https://www.microsemi.com/packaging-information/partpackage/details?pid=5339, https://www.onsemi.com/pub/Collateral/457-04.PDF) +Powermite +0 +2 +2 +Diode_SMD +D_QFN_3.3x3.3mm_P0.65mm +QFN, diode, 3.3x3.3x1mm (https://www.wolfspeed.com/media/downloads/846/C3D1P7060Q.pdf) +diode qfn 3.3 +0 +3 +2 +Diode_SMD +D_SC-80 +JEITA SC-80 +SC-80 +0 +2 +2 +Diode_SMD +D_SC-80_HandSoldering +JEITA SC-80 +SC-80 +0 +2 +2 +Diode_SMD +D_SMA +Diode SMA (DO-214AC) +Diode SMA (DO-214AC) +0 +2 +2 +Diode_SMD +D_SMA-SMB_Universal_Handsoldering +Diode, Universal, SMA (DO-214AC) or SMB (DO-214AA), Handsoldering, +Diode Universal SMA (DO-214AC) SMB (DO-214AA) Handsoldering +0 +2 +2 +Diode_SMD +D_SMA_Handsoldering +Diode SMA (DO-214AC) Handsoldering +Diode SMA (DO-214AC) Handsoldering +0 +2 +2 +Diode_SMD +D_SMB +Diode SMB (DO-214AA) +Diode SMB (DO-214AA) +0 +2 +2 +Diode_SMD +D_SMB-SMC_Universal_Handsoldering +Diode, Universal, SMB(DO-214AA) or SMC (DO-214AB), Handsoldering, +Diode Universal SMB(DO-214AA) SMC (DO-214AB) Handsoldering +0 +2 +2 +Diode_SMD +D_SMB_Handsoldering +Diode SMB (DO-214AA) Handsoldering +Diode SMB (DO-214AA) Handsoldering +0 +2 +2 +Diode_SMD +D_SMB_Modified +Diode SMB (DO-214AA) Modified (http://www.littelfuse.com/~/media/electronics/datasheets/sidactors/littelfuse_sidactor_battrax_positive_negative_modified_do_214_datasheet.pdf.pdf) +Diode SMB (DO-214AA) +0 +3 +3 +Diode_SMD +D_SMC +Diode SMC (DO-214AB) +Diode SMC (DO-214AB) +0 +2 +2 +Diode_SMD +D_SMC-RM10_Universal_Handsoldering +Diode, Universal, SMC (DO-214AB), RM10, Handsoldering, SMD, Thruhole +Diode Universal SMC (DO-214AB) RM10 Handsoldering SMD Thruhole +0 +2 +2 +Diode_SMD +D_SMC_Handsoldering +Diode SMC (DO-214AB) Handsoldering +Diode SMC (DO-214AB) Handsoldering +0 +2 +2 +Diode_SMD +D_SMF +Diode SMF (DO-219AB), http://www.vishay.com/docs/95572/smf_do-219ab.pdf +Diode SMF (DO-214AB) +0 +2 +2 +Diode_SMD +D_SOD-110 +SOD-110 +SOD-110 +0 +2 +2 +Diode_SMD +D_SOD-123 +SOD-123 +SOD-123 +0 +2 +2 +Diode_SMD +D_SOD-123F +D_SOD-123F +D_SOD-123F +0 +2 +2 +Diode_SMD +D_SOD-128 +D_SOD-128 (CFP5 SlimSMAW), https://assets.nexperia.com/documents/outline-drawing/SOD128.pdf +D_SOD-128 +0 +2 +2 +Diode_SMD +D_SOD-323 +SOD-323 +SOD-323 +0 +2 +2 +Diode_SMD +D_SOD-323F +SOD-323F http://www.nxp.com/documents/outline_drawing/SOD323F.pdf +SOD-323F +0 +2 +2 +Diode_SMD +D_SOD-323_HandSoldering +SOD-323 +SOD-323 +0 +2 +2 +Diode_SMD +D_SOD-523 +http://www.diodes.com/datasheets/ap02001.pdf p.144 +Diode SOD523 +0 +2 +2 +Diode_SMD +D_SOT-23_ANK +SOT-23, Single Diode +SOT-23 +0 +3 +2 +Diode_SMD +D_SOT-23_NKA +SOT-23, Single Diode +SOT-23 +0 +3 +2 +Diode_SMD +D_TUMD2 +ROHM - TUMD2 +TUMD2 +0 +2 +2 +Diode_SMD +Diode_Bridge_Bourns_CD-DF4xxS +8.1x10.5mm, 4A, single phase bridge rectifier, https://www.bourns.com/docs/Product-Datasheets/CD-DF4xxSL.pdf +Surface Mount Bridge Rectifier Diode +0 +4 +4 +Diode_SMD +Diode_Bridge_Diotec_ABS +SMD diode bridge ABS (Diotec), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/abs2.pdf +ABS MBLS +0 +4 +4 +Diode_SMD +Diode_Bridge_Diotec_MicroDil_3.0x3.0x1.8mm +SMD package Diotec Diotec MicroDil, body 3.0x3.0x1.8mm (e.g. diode bridge), see https://diotec.com/tl_files/diotec/files/pdf/datasheets/mys40.pdf +Diotec MicroDil diode bridge +0 +4 +4 +Diode_SMD +Diode_Bridge_Diotec_SO-DIL-Slim +SMD diode bridge Diotec SO-DIL Slim, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40fs.pdf +DFS SO-DIL Slim +0 +4 +4 +Diode_SMD +Diode_Bridge_Vishay_DFS +SMD diode bridge DFS, see http://www.vishay.com/docs/88854/padlayouts.pdf +DFS +0 +4 +4 +Diode_SMD +Diode_Bridge_Vishay_DFSFlat +SMD diode bridge Low Profile DFS "Flat", see http://www.vishay.com/docs/88874/dfl15005.pdf +DFS +0 +4 +4 +Diode_SMD +Diode_Bridge_Vishay_MBLS +SMD diode bridge MBLS, see http://www.vishay.com/docs/89959/mbl104s.pdf http://www.vishay.com/docs/88854/padlayouts.pdf +DFS +0 +4 +4 +Diode_SMD +Littelfuse_PolyZen-LS +http://m.littelfuse.com/~/media/electronics/datasheets/polyzen_devices/littelfuse_polyzen_standard_polyzen_catalog_datasheet.pdf.pdf +Diode Polymer Protected Zener Diode Littelfuse LS +0 +3 +3 +Diode_THT +D_5KPW_P7.62mm_Vertical_AnodeUp +Diode, 5KPW series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KPW series Axial Vertical pin pitch 7.62mm length 9mm diameter 8mm +0 +2 +2 +Diode_THT +D_5KPW_P7.62mm_Vertical_KathodeUp +Diode, 5KPW series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KPW series Axial Vertical pin pitch 7.62mm length 9mm diameter 8mm +0 +2 +2 +Diode_THT +D_5KPW_P12.70mm_Horizontal +Diode, 5KPW series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9*8mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KPW series Axial Horizontal pin pitch 12.7mm length 9mm diameter 8mm +0 +2 +2 +Diode_THT +D_5KP_P7.62mm_Vertical_AnodeUp +Diode, 5KP series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KP series Axial Vertical pin pitch 7.62mm length 7.62mm diameter 9.53mm +0 +2 +2 +Diode_THT +D_5KP_P7.62mm_Vertical_KathodeUp +Diode, 5KP series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KP series Axial Vertical pin pitch 7.62mm length 7.62mm diameter 9.53mm +0 +2 +2 +Diode_THT +D_5KP_P10.16mm_Horizontal +Diode, 5KP series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KP series Axial Horizontal pin pitch 10.16mm length 7.62mm diameter 9.53mm +0 +2 +2 +Diode_THT +D_5KP_P12.70mm_Horizontal +Diode, 5KP series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7.62*9.53mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5KP series Axial Horizontal pin pitch 12.7mm length 7.62mm diameter 9.53mm +0 +2 +2 +Diode_THT +D_5W_P5.08mm_Vertical_AnodeUp +Diode, 5W series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5W series Axial Vertical pin pitch 5.08mm length 8.9mm diameter 3.7mm +0 +2 +2 +Diode_THT +D_5W_P5.08mm_Vertical_KathodeUp +Diode, 5W series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5W series Axial Vertical pin pitch 5.08mm length 8.9mm diameter 3.7mm +0 +2 +2 +Diode_THT +D_5W_P10.16mm_Horizontal +Diode, 5W series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5W series Axial Horizontal pin pitch 10.16mm length 8.9mm diameter 3.7mm +0 +2 +2 +Diode_THT +D_5W_P12.70mm_Horizontal +Diode, 5W series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=8.9*3.7mm^2, , http://www.diodes.com/_files/packages/8686949.gif +Diode 5W series Axial Horizontal pin pitch 12.7mm length 8.9mm diameter 3.7mm +0 +2 +2 +Diode_THT +D_A-405_P2.54mm_Vertical_AnodeUp +Diode, A-405 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_A-405_P2.54mm_Vertical_KathodeUp +Diode, A-405 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_A-405_P5.08mm_Vertical_AnodeUp +Diode, A-405 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_A-405_P5.08mm_Vertical_KathodeUp +Diode, A-405 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_A-405_P7.62mm_Horizontal +Diode, A-405 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_A-405_P10.16mm_Horizontal +Diode, A-405 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Horizontal pin pitch 10.16mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_A-405_P12.70mm_Horizontal +Diode, A-405 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/A-405.pdf +Diode A-405 series Axial Horizontal pin pitch 12.7mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-15_P2.54mm_Vertical_AnodeUp +Diode, DO-15 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Vertical pin pitch 2.54mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P2.54mm_Vertical_KathodeUp +Diode, DO-15 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Vertical pin pitch 2.54mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P3.81mm_Vertical_AnodeUp +Diode, DO-15 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Vertical pin pitch 3.81mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P3.81mm_Vertical_KathodeUp +Diode, DO-15 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Vertical pin pitch 3.81mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P5.08mm_Vertical_AnodeUp +Diode, DO-15 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Vertical pin pitch 5.08mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P5.08mm_Vertical_KathodeUp +Diode, DO-15 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Vertical pin pitch 5.08mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P10.16mm_Horizontal +Diode, DO-15 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Horizontal pin pitch 10.16mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P12.70mm_Horizontal +Diode, DO-15 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Horizontal pin pitch 12.7mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-15_P15.24mm_Horizontal +Diode, DO-15 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=7.6*3.6mm^2, , http://www.diodes.com/_files/packages/DO-15.pdf +Diode DO-15 series Axial Horizontal pin pitch 15.24mm length 7.6mm diameter 3.6mm +0 +2 +2 +Diode_THT +D_DO-27_P5.08mm_Vertical_AnodeUp +Diode, DO-27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg +Diode DO-27 series Axial Vertical pin pitch 5.08mm length 9.52mm diameter 5.33mm +0 +2 +2 +Diode_THT +D_DO-27_P5.08mm_Vertical_KathodeUp +Diode, DO-27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg +Diode DO-27 series Axial Vertical pin pitch 5.08mm length 9.52mm diameter 5.33mm +0 +2 +2 +Diode_THT +D_DO-27_P12.70mm_Horizontal +Diode, DO-27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg +Diode DO-27 series Axial Horizontal pin pitch 12.7mm length 9.52mm diameter 5.33mm +0 +2 +2 +Diode_THT +D_DO-27_P15.24mm_Horizontal +Diode, DO-27 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.52*5.33mm^2, , http://www.slottechforum.com/slotinfo/Techstuff/CD2%20Diodes%20and%20Transistors/Cases/Diode%20DO-27.jpg +Diode DO-27 series Axial Horizontal pin pitch 15.24mm length 9.52mm diameter 5.33mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P2.54mm_Vertical_AnodeUp +Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Vertical pin pitch 2.54mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P2.54mm_Vertical_KathodeUp +Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Vertical pin pitch 2.54mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P5.08mm_Vertical_AnodeUp +Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Vertical pin pitch 5.08mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P5.08mm_Vertical_KathodeUp +Diode, DO-34_SOD68 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Vertical pin pitch 5.08mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P7.62mm_Horizontal +Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Horizontal pin pitch 7.62mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P10.16mm_Horizontal +Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Horizontal pin pitch 10.16mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-34_SOD68_P12.70mm_Horizontal +Diode, DO-34_SOD68 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=3.04*1.6mm^2, , https://www.nxp.com/docs/en/data-sheet/KTY83_SER.pdf +Diode DO-34_SOD68 series Axial Horizontal pin pitch 12.7mm length 3.04mm diameter 1.6mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P2.54mm_Vertical_AnodeUp +Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Vertical pin pitch 2.54mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P2.54mm_Vertical_KathodeUp +Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Vertical pin pitch 2.54mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P3.81mm_Vertical_AnodeUp +Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Vertical pin pitch 3.81mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P3.81mm_Vertical_KathodeUp +Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Vertical pin pitch 3.81mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P5.08mm_Vertical_AnodeUp +Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Vertical pin pitch 5.08mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P5.08mm_Vertical_KathodeUp +Diode, DO-35_SOD27 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Vertical pin pitch 5.08mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P7.62mm_Horizontal +Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Horizontal pin pitch 7.62mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P10.16mm_Horizontal +Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Horizontal pin pitch 10.16mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-35_SOD27_P12.70mm_Horizontal +Diode, DO-35_SOD27 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=4*2mm^2, , http://www.diodes.com/_files/packages/DO-35.pdf +Diode DO-35_SOD27 series Axial Horizontal pin pitch 12.7mm length 4mm diameter 2mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P2.54mm_Vertical_AnodeUp +Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P2.54mm_Vertical_KathodeUp +Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Vertical pin pitch 2.54mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P3.81mm_Vertical_AnodeUp +Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=5.2*2.7mm^2, , https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf +Diode DO-41_SOD81 series Axial Vertical pin pitch 3.81mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P3.81mm_Vertical_KathodeUp +Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=5.2*2.7mm^2, , https://www.diodes.com/assets/Package-Files/DO-41-Plastic.pdf +Diode DO-41_SOD81 series Axial Vertical pin pitch 3.81mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P5.08mm_Vertical_AnodeUp +Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P5.08mm_Vertical_KathodeUp +Diode, DO-41_SOD81 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Vertical pin pitch 5.08mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P7.62mm_Horizontal +Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Horizontal pin pitch 7.62mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P10.16mm_Horizontal +Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Horizontal pin pitch 10.16mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-41_SOD81_P12.70mm_Horizontal +Diode, DO-41_SOD81 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=5.2*2.7mm^2, , http://www.diodes.com/_files/packages/DO-41%20(Plastic).pdf +Diode DO-41_SOD81 series Axial Horizontal pin pitch 12.7mm length 5.2mm diameter 2.7mm +0 +2 +2 +Diode_THT +D_DO-201AD_P3.81mm_Vertical_AnodeUp +Diode, DO-201AD series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf +Diode DO-201AD series Axial Vertical pin pitch 3.81mm length 9.5mm diameter 5.2mm +0 +2 +2 +Diode_THT +D_DO-201AD_P3.81mm_Vertical_KathodeUp +Diode, DO-201AD series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf +Diode DO-201AD series Axial Vertical pin pitch 3.81mm length 9.5mm diameter 5.2mm +0 +2 +2 +Diode_THT +D_DO-201AD_P5.08mm_Vertical_AnodeUp +Diode, DO-201AD series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf +Diode DO-201AD series Axial Vertical pin pitch 5.08mm length 9.5mm diameter 5.2mm +0 +2 +2 +Diode_THT +D_DO-201AD_P5.08mm_Vertical_KathodeUp +Diode, DO-201AD series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf +Diode DO-201AD series Axial Vertical pin pitch 5.08mm length 9.5mm diameter 5.2mm +0 +2 +2 +Diode_THT +D_DO-201AD_P12.70mm_Horizontal +Diode, DO-201AD series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf +Diode DO-201AD series Axial Horizontal pin pitch 12.7mm length 9.5mm diameter 5.2mm +0 +2 +2 +Diode_THT +D_DO-201AD_P15.24mm_Horizontal +Diode, DO-201AD series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.5*5.2mm^2, , http://www.diodes.com/_files/packages/DO-201AD.pdf +Diode DO-201AD series Axial Horizontal pin pitch 15.24mm length 9.5mm diameter 5.2mm +0 +2 +2 +Diode_THT +D_DO-201AE_P3.81mm_Vertical_AnodeUp +Diode, DO-201AE series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf +Diode DO-201AE series Axial Vertical pin pitch 3.81mm length 9mm diameter 5.3mm +0 +2 +2 +Diode_THT +D_DO-201AE_P3.81mm_Vertical_KathodeUp +Diode, DO-201AE series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf +Diode DO-201AE series Axial Vertical pin pitch 3.81mm length 9mm diameter 5.3mm +0 +2 +2 +Diode_THT +D_DO-201AE_P5.08mm_Vertical_AnodeUp +Diode, DO-201AE series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf +Diode DO-201AE series Axial Vertical pin pitch 5.08mm length 9mm diameter 5.3mm +0 +2 +2 +Diode_THT +D_DO-201AE_P5.08mm_Vertical_KathodeUp +Diode, DO-201AE series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf +Diode DO-201AE series Axial Vertical pin pitch 5.08mm length 9mm diameter 5.3mm +0 +2 +2 +Diode_THT +D_DO-201AE_P12.70mm_Horizontal +Diode, DO-201AE series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf +Diode DO-201AE series Axial Horizontal pin pitch 12.7mm length 9mm diameter 5.3mm +0 +2 +2 +Diode_THT +D_DO-201AE_P15.24mm_Horizontal +Diode, DO-201AE series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9*5.3mm^2, , http://www.farnell.com/datasheets/529758.pdf +Diode DO-201AE series Axial Horizontal pin pitch 15.24mm length 9mm diameter 5.3mm +0 +2 +2 +Diode_THT +D_DO-201_P3.81mm_Vertical_AnodeUp +Diode, DO-201 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf +Diode DO-201 series Axial Vertical pin pitch 3.81mm length 9.53mm diameter 5.21mm +0 +2 +2 +Diode_THT +D_DO-201_P3.81mm_Vertical_KathodeUp +Diode, DO-201 series, Axial, Vertical, pin pitch=3.81mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf +Diode DO-201 series Axial Vertical pin pitch 3.81mm length 9.53mm diameter 5.21mm +0 +2 +2 +Diode_THT +D_DO-201_P5.08mm_Vertical_AnodeUp +Diode, DO-201 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf +Diode DO-201 series Axial Vertical pin pitch 5.08mm length 9.53mm diameter 5.21mm +0 +2 +2 +Diode_THT +D_DO-201_P5.08mm_Vertical_KathodeUp +Diode, DO-201 series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf +Diode DO-201 series Axial Vertical pin pitch 5.08mm length 9.53mm diameter 5.21mm +0 +2 +2 +Diode_THT +D_DO-201_P12.70mm_Horizontal +Diode, DO-201 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf +Diode DO-201 series Axial Horizontal pin pitch 12.7mm length 9.53mm diameter 5.21mm +0 +2 +2 +Diode_THT +D_DO-201_P15.24mm_Horizontal +Diode, DO-201 series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.53*5.21mm^2, , http://www.diodes.com/_files/packages/DO-201.pdf +Diode DO-201 series Axial Horizontal pin pitch 15.24mm length 9.53mm diameter 5.21mm +0 +2 +2 +Diode_THT +D_P600_R-6_P7.62mm_Vertical_AnodeUp +Diode, P600_R-6 series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf +Diode P600_R-6 series Axial Vertical pin pitch 7.62mm length 9.1mm diameter 9.1mm +0 +2 +2 +Diode_THT +D_P600_R-6_P7.62mm_Vertical_KathodeUp +Diode, P600_R-6 series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf +Diode P600_R-6 series Axial Vertical pin pitch 7.62mm length 9.1mm diameter 9.1mm +0 +2 +2 +Diode_THT +D_P600_R-6_P12.70mm_Horizontal +Diode, P600_R-6 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf +Diode P600_R-6 series Axial Horizontal pin pitch 12.7mm length 9.1mm diameter 9.1mm +0 +2 +2 +Diode_THT +D_P600_R-6_P20.00mm_Horizontal +Diode, P600_R-6 series, Axial, Horizontal, pin pitch=20mm, , length*diameter=9.1*9.1mm^2, , http://www.vishay.com/docs/88692/p600a.pdf, http://www.diodes.com/_files/packages/R-6.pdf +Diode P600_R-6 series Axial Horizontal pin pitch 20mm length 9.1mm diameter 9.1mm +0 +2 +2 +Diode_THT +D_T-1_P2.54mm_Vertical_AnodeUp +Diode, T-1 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf +Diode T-1 series Axial Vertical pin pitch 2.54mm length 3.2mm diameter 2.6mm +0 +2 +2 +Diode_THT +D_T-1_P2.54mm_Vertical_KathodeUp +Diode, T-1 series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf +Diode T-1 series Axial Vertical pin pitch 2.54mm length 3.2mm diameter 2.6mm +0 +2 +2 +Diode_THT +D_T-1_P5.08mm_Horizontal +Diode, T-1 series, Axial, Horizontal, pin pitch=5.08mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf +Diode T-1 series Axial Horizontal pin pitch 5.08mm length 3.2mm diameter 2.6mm +0 +2 +2 +Diode_THT +D_T-1_P10.16mm_Horizontal +Diode, T-1 series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf +Diode T-1 series Axial Horizontal pin pitch 10.16mm length 3.2mm diameter 2.6mm +0 +2 +2 +Diode_THT +D_T-1_P12.70mm_Horizontal +Diode, T-1 series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf +Diode T-1 series Axial Horizontal pin pitch 12.7mm length 3.2mm diameter 2.6mm +0 +2 +2 +Diode_THT +Diode_Bridge_15.1x15.1x6.3mm_P10.9mm +Single phase bridge rectifier case 15.1x15.1mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf +Diode Bridge PB10xxS +0 +4 +4 +Diode_THT +Diode_Bridge_15.2x15.2x6.3mm_P10.9mm +Single phase bridge rectifier case 15.2x15.2mm, pitch 10.9mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc600.pdf +Diode Bridge KBPC6xx +0 +4 +4 +Diode_THT +Diode_Bridge_15.7x15.7x6.3mm_P10.8mm +Single phase bridge rectifier case 15.7x15.7 +Diode Bridge +0 +4 +4 +Diode_THT +Diode_Bridge_16.7x16.7x6.3mm_P10.8mm +Single phase bridge rectifier case 16.7x16.7 +Diode Bridge +0 +4 +4 +Diode_THT +Diode_Bridge_19.0x3.5x10.0mm_P5.0mm +Vishay GBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88606/g3sba20.pdf +Vishay GBU rectifier diode bridge +0 +4 +4 +Diode_THT +Diode_Bridge_19.0x19.0x6.8mm_P12.7mm +Single phase bridge rectifier case 19x19mm, pitch 12.7mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/pb1000.pdf +Diode Bridge PB10xx +0 +4 +4 +Diode_THT +Diode_Bridge_28.6x28.6x7.3mm_P18.0mm_P11.6mm +Single phase bridge rectifier case 28.6x28.6mm, pitch 18.0mm & 11.6mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/kbpc1500fw.pdf +Diode Bridge KBPCxxxxWP +0 +4 +4 +Diode_THT +Diode_Bridge_32.0x5.6x17.0mm_P10.0mm_P7.5mm +Diotec 32x5.6x17mm rectifier package, 7.5mm/10mm pitch, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40c3700.pdf +Diotec rectifier diode bridge +0 +4 +4 +Diode_THT +Diode_Bridge_DIP-4_W5.08mm_P2.54mm +4-lead dip package for diode bridges, row spacing 5.08mm, pin-spacing 2.54mm, see http://www.vishay.com/docs/88898/b2m.pdf +DIL DIP PDIP 5.08mm 2.54 +0 +4 +4 +Diode_THT +Diode_Bridge_DIP-4_W7.62mm_P5.08mm +4-lead dip package for diode bridges, row spacing 7.62 mm (300 mils), see http://cdn-reichelt.de/documents/datenblatt/A400/HDBL101G_20SERIES-TSC.pdf +DIL DIP PDIP 5.08mm 7.62mm 300mil +0 +4 +4 +Diode_THT +Diode_Bridge_Round_D8.9mm +4-lead round diode bridge package, diameter 8.9mm, pin pitch 5.08mm, see http://cdn-reichelt.de/documents/datenblatt/A400/W005M-W10M_SEP.PDF +diode bridge 8.9mm 8.85mm WOB pitch 5.08mm +0 +4 +4 +Diode_THT +Diode_Bridge_Round_D9.0mm +4-lead round diode bridge package, diameter 9.0mm, pin pitch 5.0mm, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40r.pdf +diode bridge 9.0mm 8.85mm WOB pitch 5.0mm +0 +4 +4 +Diode_THT +Diode_Bridge_Round_D9.8mm +4-lead round diode bridge package, diameter 9.8mm, pin pitch 5.08mm, see http://www.vishay.com/docs/88769/woo5g.pdf +diode bridge 9.8mm WOG pitch 5.08mm +0 +4 +4 +Diode_THT +Diode_Bridge_Vishay_GBL +Vishay GBL rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88609/gbl005.pdf +Vishay GBL rectifier diode bridge +0 +4 +4 +Diode_THT +Diode_Bridge_Vishay_GBU +Vishay GBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88606/g3sba20.pdf +Vishay GBU rectifier diode bridge +0 +4 +4 +Diode_THT +Diode_Bridge_Vishay_KBL +Vishay KBL rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88655/kbl005.pdf +Vishay KBL rectifier diode bridge +0 +4 +4 +Diode_THT +Diode_Bridge_Vishay_KBPC1 +Single phase bridge rectifier case KBPC1, see http://www.vishay.com/docs/93585/vs-kbpc1series.pdf +Diode Bridge +0 +4 +4 +Diode_THT +Diode_Bridge_Vishay_KBPC6 +Single phase bridge rectifier case KBPC6, see http://www.vishay.com/docs/93585/vs-kbpc1series.pdf +Diode Bridge +0 +4 +4 +Diode_THT +Diode_Bridge_Vishay_KBU +Vishay KBU rectifier package, 5.08mm pitch, see http://www.vishay.com/docs/88656/kbu4.pdf +Vishay KBU rectifier diode bridge +0 +4 +4 +Display +AG12864E +STN/FSTN LCD 128x64 dot https://www.digchip.com/datasheets/parts/datasheet/1121/AG-12864E-pdf.php +AG12864E Graphics Display 128x64 Ampire +0 +24 +20 +Display +Adafruit_SSD1306 +Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI https://learn.adafruit.com/monochrome-oled-breakouts/downloads +Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI +0 +8 +8 +Display +Adafruit_SSD1306_No_Mounting_Holes +Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI https://learn.adafruit.com/monochrome-oled-breakouts/downloads +Adafruit SSD1306 OLED 1.3 inch 128x64 I2C & SPI +0 +8 +8 +Display +CR2013-MI2120 +CR2013-MI2120 ILI9341 LCD Breakout http://pan.baidu.com/s/11Y990 +CR2013-MI2120 ILI9341 LCD Breakout +0 +18 +14 +Display +EA-eDIP128B-XXX +LCD-graphical display with LED backlight 128x64 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip128-6e.pdf +LCD-graphical display with LED backlight 128x64 RS-232 I2C or SPI +0 +32 +32 +Display +EA_DOGS104X-A +LCD 4x10 character 3.3V VDD I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/doma/dogs104e.pdf +LCD 4x10 character 3.3V VDD I2C or SPI +0 +14 +14 +Display +EA_DOGXL160-7 +Grapchical,Display,LCD,160x104 http://www.lcd-module.com/eng/pdf/grafik/dogxl160-7e.pdf +EA_DOGXL160-7 +0 +22 +22 +Display +EA_DOGXL160-7_Backlight +Grapchical,Display,LCD,160x104 http://www.lcd-module.com/eng/pdf/grafik/dogxl160-7e.pdf +EA_DOGXL160-7_Backlight +0 +22 +22 +Display +EA_T123X-I2C +http://www.lcd-module.de/pdf/doma/t123-i2c.pdf +3 Line 12 character wide alpha numeric LCD +0 +6 +6 +Display +EA_eDIP160-XXX +LCD-graphical display with LED backlight 160x104 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip160-7e.pdf +LCD-graphical display with LED backlight 160x104 RS-232 I2C or SPI +0 +40 +40 +Display +EA_eDIP240-XXX +LCD graphical display LED backlight 240x128 http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip240-7e.pdf +LCD graphical display LED backlight 240x128 +0 +40 +40 +Display +EA_eDIP320X-XXX +LCD display 320x340 RS-232 I2C or SPI http://www.lcd-module.com/fileadmin/eng/pdf/grafik/edip320-8e.pdf +LCD display 320x340 RS-232 I2C or SPI +0 +48 +48 +Display +EA_eDIPTFT32-XXX +TFT-graphic display 320x240 16 bit colour with led backlight http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft32-ae.pdf +TFT-graphic display 320x240 16 bit colour with led backlight +0 +40 +40 +Display +EA_eDIPTFT43-ATC +http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft43-ae.pdf +TFT graphical display 480x272 16-bit colour with LED backlight +0 +40 +40 +Display +EA_eDIPTFT43-XXX +TFT graphical display 480x272 16-bit colour with LED backlight http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft43-ae.pdf +TFT graphical display 480x272 16-bit colour with LED backlight +0 +40 +40 +Display +EA_eDIPTFT57-XXX +http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft57-ae.pdf +TFT-graphic display 640x480 16 bit colour +0 +48 +48 +Display +EA_eDIPTFT70-ATC +TFT-graphical display 800x480 16-bit colours with capacitive touch panel http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft70-ae.pdf +TFT-graphical display 800x480 16-bit colours with capacitive touch panel +0 +48 +48 +Display +EA_eDIPTFT70-XXX +TFT-graphical display 800x480 16-bit colours http://www.lcd-module.com/fileadmin/eng/pdf/grafik/ediptft70-ae.pdf +TFT-graphical display 800x480 16-bit colours and touch display +0 +48 +48 +Display +HDSM-441B_HDSM-443B +2 Digit 7 segemnt blue LED, right hand decimal, https://docs.broadcom.com/docs/AV02-1589EN +2 Digit 7 segment blue LED +0 +10 +10 +Display +HDSM-541B_HDSM-543B +2 digit 7 segement blue LED with right hand decimal, https://docs.broadcom.com/docs/AV02-1588EN +2 digit 7 segement blue LED with right hand decimal +0 +10 +10 +Display +HDSP-48xx +10-Element Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Bar Graph Array +0 +20 +20 +Display +HDSP-4830 +10-Element Red Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Red Bar Graph Array +0 +20 +20 +Display +HDSP-4832 +10-Element Red Yellow Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Red Yellow Green Bar Graph Array +0 +20 +20 +Display +HDSP-4836 +10-Element Red Yellow Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Red Yellow Green Bar Graph Array +0 +20 +20 +Display +HDSP-4840 +10-Element Yellow Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Yellow Bar Graph Array +0 +20 +20 +Display +HDSP-4850 +10-Element Green Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Green Bar Graph Array +0 +20 +20 +Display +HLCP-J100 +10-Element Red Bar Graph Array https://docs.broadcom.com/docs/AV02-1798EN +10-Element Red Bar Graph Array +0 +20 +20 +Display +HY1602E +http://www.icbank.com/data/ICBShop/board/HY1602E.pdf +LCD 16x2 Alphanumeric 16pin +0 +20 +16 +Display +LCD-016N002L +16 x 2 Character LCD, http://www.vishay.com/product?docid=37299 +LCD-016N002L 16 x 2 Character LCD +0 +24 +20 +Display +LM16255 +LCD LM16255 16x2 character http://www.datasheetlib.com/datasheet/259542/lm16255_sharp-electronics.html +LCD 12x2 +0 +14 +14 +Display +NHD-0420H1Z +NHD-0420H1Z LCD http://www.newhavendisplay.com/specs/NHD-0420H1Z-FSW-GBW-33V3.pdf +NHD-0420H1Z LCD +0 +16 +16 +Display +RC1602A +http://www.raystar-optronics.com/down.php?ProID=18 +LCD 16x2 Alphanumeric 16pin +0 +22 +18 +Display +WC1602A +LCD 16x2 http://www.wincomlcd.com/pdf/WC1602A-SFYLYHTC06.pdf +LCD 16x2 Alphanumeric 16pin +0 +20 +16 +Display_7Segment +7SEGMENT-LED__HDSM531_HDSM533_SMD +7-Segment Display, HDSM53x, https://docs.broadcom.com/docs/AV02-0713EN +7segment LED HDSM531 HDSM533 +0 +10 +10 +Display_7Segment +7SegmentLED_LTS6760_LTS6780 +7-Segment Display, LTS67x0, http://optoelectronics.liteon.com/upload/download/DS30-2001-355/S6760jd.pdf +7Segment LED LTS6760 LTS6780 +0 +10 +10 +Display_7Segment +AD-121F2 +Single Digit 7-segment RGB LED Display, 1-inch digit height, common anode, http://usasyck.com/products/AD-121F2_cat_e.pdf +RGB LED digit +0 +22 +22 +Display_7Segment +AFF_2x7SEG-DIGIT_10mm +Afficheur 7 segments 10mm DIGIT +AFFICHEUR +0 +16 +16 +Display_7Segment +CA56-12CGKWA +4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12CGKWA(Ver.9A).pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CA56-12EWA +4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-12EWA.pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CA56-12SEKWA +4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SEKWA(Ver.7A).pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CA56-12SRWA +4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-12SRWA.pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CA56-12SURKWA +4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SURKWA(Ver.8A).pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CA56-12SYKWA +4 digit 7 segment green LED, http://www.kingbright.com/attachments/file/psearch/000/00/00/CA56-12SYKWA(Ver.6A).pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CC56-12GWA +4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CA56-11GWA.pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +CC56-12YWA +4 digit 7 segment green LED, http://www.kingbrightusa.com/images/catalog/SPEC/CC56-12YWA.pdf +4 digit 7 segment green LED +0 +12 +12 +Display_7Segment +DA04-11CGKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11CGKWA(Ver.6A).pdf +Dubble digit green 7 segment LED display +0 +16 +16 +Display_7Segment +DA04-11SEKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SEKWA(Ver.9A).pdf +Dubble digit super bright orange 7 segment LED display +0 +16 +16 +Display_7Segment +DA04-11SURKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SURKWA(Ver.10A).pdf +Dubble digit hyper red 7 segment LED display +0 +16 +16 +Display_7Segment +DA04-11SYKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA04-11SYKWA(Ver.6A).pdf +Dubble digit super bright yellow 7 segment LED display +0 +16 +16 +Display_7Segment +DA56-11CGKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11CGKWA(Ver.16A).pdf +Double digit seven segment green LED display +0 +18 +18 +Display_7Segment +DA56-11SEKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SEKWA(Ver.9A).pdf +Double digit seven segment super bright orange LED display +0 +18 +18 +Display_7Segment +DA56-11SURKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SURKWA(Ver.11A).pdf +Double digit seven segment hyper red LED display +0 +18 +18 +Display_7Segment +DA56-11SYKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/DA56-11SYKWA(Ver.11A).pdf +Double digit seven segment super bright yellow LED display +0 +18 +18 +Display_7Segment +DE113-XX-XX +http://www.display-elektronik.de/filter/DE113-RS-20_635.pdf +3 1/5 digit LOW BAT + 7-Segment LCD +0 +40 +40 +Display_7Segment +DE114-RS-20 +http://www.display-elektronik.de/filter/DE113-RS-20_635.pdf +3 1/5 digit reflective LCD LOW-BAT + 7-Segment +0 +40 +40 +Display_7Segment +DE122-XX-XX +http://www.display-elektronik.de/filter/DE122-RS-20_635.pdf +6 digit 7 segment LCD +0 +50 +50 +Display_7Segment +DE170-XX-XX +http://www.display-elektronik.de/filter/DE170-RS-20_75.pdf +3 1/5 digit reflective arrow bat + 7 segment LCD +0 +40 +40 +Display_7Segment +ELD_426XXXX +http://www.everlight.com/file/ProductFile/D426SYGWA-S530-E2.pdf +Double digit 7 segment brilliant yellow green LED +0 +10 +10 +Display_7Segment +HDSP-7401 +One digit 7 segment yellow, https://docs.broadcom.com/docs/AV02-2553EN +One digit 7 segment yellow +0 +10 +10 +Display_7Segment +HDSP-7507 ++-1 overflow 7 segment high efficiency red, https://docs.broadcom.com/docs/AV02-2553EN ++-1 overflow 7 segment high efficiency red +0 +10 +10 +Display_7Segment +HDSP-7801 +One digit 7 segment green, https://docs.broadcom.com/docs/AV02-2553EN +One digit 7 segment green +0 +10 +10 +Display_7Segment +HDSP-7807 ++-1 overflow 7 segment green, https://docs.broadcom.com/docs/AV02-2553EN ++-1 overflow 7 segment green +0 +10 +10 +Display_7Segment +HDSP-A151 +One digit 7 segment red, https://docs.broadcom.com/docs/AV02-2553EN +One digit 7 segment high efficiency red +0 +10 +10 +Display_7Segment +HDSP-A401 +One digit 7 segment orange, common anode, https://docs.broadcom.com/docs/AV02-2553EN +One digit 7 segment orange common anode +0 +10 +10 +Display_7Segment +KCSC02-105 +http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-105(Ver.9A).pdf +Single digit 7 segement hyper red LED +0 +10 +10 +Display_7Segment +KCSC02-106 +http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-106(Ver.10A).pdf +Single digit 7 segement super bright orange LED +0 +10 +10 +Display_7Segment +KCSC02-107 +http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-107(Ver.9A).pdf +Single digit 7 segement super bright yellow LED +0 +10 +10 +Display_7Segment +KCSC02-123 +http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-123(Ver.10A).pdf +Single digit 7 segement super bright yellow LED +0 +10 +10 +Display_7Segment +KCSC02-136 +http://www.kingbright.com/attachments/file/psearch/000/00/00/KCSC02-136(Ver.6B).pdf +Single digit 7 segement super bright yellow LED +0 +10 +10 +Display_7Segment +MAN71A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment red LED with right dot +0 +14 +14 +Display_7Segment +MAN72A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment red LED with left dot +0 +14 +14 +Display_7Segment +MAN73A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +Overflow +- 1 red LED +0 +14 +14 +Display_7Segment +MAN3410A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment green LED with dot +0 +14 +14 +Display_7Segment +MAN3420A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment green LED with left dot +0 +14 +14 +Display_7Segment +MAN3610A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment orange LED with right dot +0 +14 +14 +Display_7Segment +MAN3620A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment orange LED with left dot +0 +14 +14 +Display_7Segment +MAN3630A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +Overflow +- 1 orange LED +0 +14 +14 +Display_7Segment +MAN3810A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment yellow LED with right dot +0 +14 +14 +Display_7Segment +MAN3820A +https://www.digchip.com/datasheets/parts/datasheet/161/MAN3640A-pdf.php +One digit 7 segment yellow LED with left dot +0 +14 +14 +Display_7Segment +SA15-11xxx +http://www.kingbrightusa.com/images/catalog/SPEC/SA15-11SRWA.pdf +SA15-11xxx single digit 7 segment display 38.1mm 1.5inch +0 +10 +10 +Display_7Segment +SBC18-11SURKCGKWA +http://www.kingbright.com/attachments/file/psearch/000/00/00/SBC18-11SURKCGKWA(Ver.6A).pdf +single digit 7 segemnt red/green LED +0 +10 +10 +Display_7Segment +Sx39-1xxxxx +Single digit 7 segment LED display in red, yellow or green colour http://www.kingbrightusa.com/images/catalog/SPEC/sa39-11ewa.pdf +One digit LED 7 segment SA39-11 SC39-11 SA39-12 SC39-12 +0 +10 +10 +Ferrite_THT +LairdTech_28C0236-0JW-10 +Ferrite, vertical, LairdTech 28C0236-0JW-10, https://assets.lairdtech.com/home/brandworld/files/28C0236-0JW-10.pdf, JW Miller core https://www.bourns.com/products/magnetic-products/j.w.-miller-through-hole-ferrite-beads-emi-filters +Ferrite vertical LairdTech 28C0236-0JW-10 +0 +2 +2 +Fiducial +Fiducial_0.5mm_Mask1.5mm +Circular Fiducial, 0.5mm bare copper, 1.5mm soldermask opening +fiducial +0 +1 +0 +Fiducial +Fiducial_0.5mm_Mask1mm +Circular Fiducial, 0.5mm bare copper, 1mm soldermask opening (Level C) +fiducial +0 +1 +0 +Fiducial +Fiducial_0.75mm_Mask1.5mm +Circular Fiducial, 0.75mm bare copper, 1.5mm soldermask opening (Level B) +fiducial +0 +1 +0 +Fiducial +Fiducial_0.75mm_Mask2.25mm +Circular Fiducial, 0.75mm bare copper, 2.25mm soldermask opening +fiducial +0 +1 +0 +Fiducial +Fiducial_1.5mm_Mask3mm +Circular Fiducial, 1.5mm bare copper, 3mm soldermask opening +fiducial +0 +1 +0 +Fiducial +Fiducial_1.5mm_Mask4.5mm +Circular Fiducial, 1.5mm bare copper, 4.5mm soldermask opening +fiducial +0 +1 +0 +Fiducial +Fiducial_1mm_Mask2mm +Circular Fiducial, 1mm bare copper, 2mm soldermask opening (Level A) +fiducial +0 +1 +0 +Fiducial +Fiducial_1mm_Mask3mm +Circular Fiducial, 1mm bare copper, 3mm soldermask opening (recommended) +fiducial +0 +1 +0 +Filter +Filter_1109-5_1.1x0.9mm +5-pin SAW filter package - 1.1x0.9 mm Body; (see https://www.murata.com/~/media/webrenewal/support/library/catalog/products/filter/rf/p73e.ashx?la=en-gb) +Filter 5 +0 +5 +5 +Filter +Filter_1411-5_1.4x1.1mm +5-pin filter package - 1.4x1.1 mm Body; (see https://global.kyocera.com/prdct/electro/product/pdf/sf14_tdlte.pdf) +Filter 5 +0 +5 +5 +Filter +Filter_Bourns_SRF0905_6.0x9.2mm +https://www.bourns.com/docs/Product-Datasheets/SRF0905.pdf +Line Filter +0 +4 +4 +Filter +Filter_Mini-Circuits_FV1206 +Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206.pdf +Mini-Circuits Filter SMD 1206 +0 +6 +4 +Filter +Filter_Mini-Circuits_FV1206-1 +Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-1.pdf +Mini-Circuits Filter SMD 1206 +0 +6 +6 +Filter +Filter_Mini-Circuits_FV1206-4 +Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-4.pdf +Mini-Circuits Filter SMD 1206 +0 +8 +4 +Filter +Filter_Mini-Circuits_FV1206-5 +Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-5.pdf +Mini-Circuits Filter SMD 1206 +0 +8 +4 +Filter +Filter_Mini-Circuits_FV1206-6 +Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-6.pdf +Mini-Circuits Filter SMD 1206 +0 +14 +8 +Filter +Filter_Mini-Circuits_FV1206-7 +Mini-Circuits Filter SMD 1206 https://ww2.minicircuits.com/case_style/FV1206-7.pdf +Mini-Circuits Filter SMD 1206 +0 +5 +3 +Filter +Filter_Murata_BNX025 +https://www.murata.com/en-us/products/productdata/8796778004510/QNFH9101.pdf?1496719830000 +EMI Filter +0 +6 +4 +Filter +Filter_Murata_BNX025_ThermalVias +https://www.murata.com/en-us/products/productdata/8796778004510/QNFH9101.pdf?1496719830000 +EMI Filter +0 +19 +4 +Filter +Filter_Schaffner_FN405 +Compact PCB mounting EMI filter (https://www.schaffner.com/de/produkte/download/product/datasheet/fn-405-pcb-mounting-filter/) +EMI filter +0 +5 +5 +Filter +Filter_Schaffner_FN406 +Ultra Compact EMC Filter (https://www.schaffner.com/products/download/product/datasheet/fn-406-ultra-compact-emc-filter/) +emi filter +0 +5 +5 +Fuse +Fuse_0201_0603Metric +Fuse SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +resistor +0 +4 +2 +Fuse +Fuse_0402_1005Metric +Fuse SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_0603_1608Metric +Fuse SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_0603_1608Metric_Pad1.05x0.95mm_HandSolder +Fuse SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_0805_2012Metric +Fuse SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_0805_2012Metric_Pad1.15x1.40mm_HandSolder +Fuse SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_01005_0402Metric +Fuse SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +resistor +0 +4 +2 +Fuse +Fuse_1206_3216Metric +Fuse SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_1206_3216Metric_Pad1.42x1.75mm_HandSolder +Fuse SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_1210_3225Metric +Fuse SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_1210_3225Metric_Pad1.42x2.65mm_HandSolder +Fuse SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_1806_4516Metric +Fuse SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_1806_4516Metric_Pad1.57x1.80mm_HandSolder +Fuse SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_1812_4532Metric +Fuse SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_1812_4532Metric_Pad1.30x3.40mm_HandSolder +Fuse SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_2010_5025Metric +Fuse SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_2010_5025Metric_Pad1.52x2.65mm_HandSolder +Fuse SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_2512_6332Metric +Fuse SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_2512_6332Metric_Pad1.52x3.35mm_HandSolder +Fuse SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_2816_7142Metric +Fuse SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_2816_7142Metric_Pad3.20x4.45mm_HandSolder +Fuse SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_2920_7451Metric +Fuse SMD 2920 (7451 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://www.megastar.com/products/fusetronic/polyswitch/PDF/smd2920.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Fuse +Fuse_2920_7451Metric_Pad2.10x5.45mm_HandSolder +Fuse SMD 2920 (7451 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://www.megastar.com/products/fusetronic/polyswitch/PDF/smd2920.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0005FF_L8.3mm_W3.8mm +Fuse 0ZRE0005FF, BelFuse, Radial Leaded PTC, https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0008FF_L8.3mm_W3.8mm +Fuse 0ZRE0008FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0012FF_L8.3mm_W3.8mm +Fuse 0ZRE0012FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0016FF_L9.9mm_W3.8mm +Fuse 0ZRE0016FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0025FF_L9.6mm_W3.8mm +Fuse 0ZRE0025FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0033FF_L11.4mm_W3.8mm +Fuse 0ZRE0033FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0040FF_L11.5mm_W3.8mm +Fuse 0ZRE0040FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0055FF_L14.0mm_W4.1mm +Fuse 0ZRE0055FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0075FF_L11.5mm_W4.8mm +Fuse 0ZRE0075FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0100FF_L18.7mm_W5.1mm +Fuse 0ZRE0100FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0125FF_L21.2mm_W5.3mm +Fuse 0ZRE0125FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0150FF_L23.4mm_W5.3mm +Fuse 0ZRE0150FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_BelFuse_0ZRE0200FF_L24.9mm_W6.1mm +Fuse 0ZRE0200FF, BelFuse, Radial Leaded PTC,https://www.belfuse.com/resources/datasheets/circuitprotection/ds-cp-0zre-series.pdf +0ZRE BelFuse radial PTC +0 +2 +2 +Fuse +Fuse_Blade_ATO_directSolder +car blade fuse direct solder +car blade fuse +0 +2 +2 +Fuse +Fuse_Blade_Mini_directSolder +car blade fuse mini, direct solder +car blade fuse mini +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG300 +PTC Resettable Fuse, Ihold = 3.0A, Itrip=5.1A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG400 +PTC Resettable Fuse, Ihold = 4.0A, Itrip=6.8A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG500 +PTC Resettable Fuse, Ihold = 5.0A, Itrip=8.5A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG600 +PTC Resettable Fuse, Ihold = 6.0A, Itrip=10.2A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG650 +PTC Resettable Fuse, Ihold = 6.5A, Itrip=11.1A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG700 +PTC Resettable Fuse, Ihold = 7.0A, Itrip=11.9A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG800 +PTC Resettable Fuse, Ihold = 8.0A, Itrip=13.6A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG900 +PTC Resettable Fuse, Ihold = 9.0A, Itrip=15.3A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG1000 +PTC Resettable Fuse, Ihold = 10.0A, Itrip=17.0A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RG1100 +PTC Resettable Fuse, Ihold = 11.0A, Itrip=18.7A, http://www.bourns.com/docs/Product-Datasheets/mfrg.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT050 +PTC Resettable Fuse, Ihold = 0.5A, Itrip=0.92A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT070 +PTC Resettable Fuse, Ihold = 0.7A, Itrip=1.4A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT100 +PTC Resettable Fuse, Ihold = 1.0A, Itrip=1.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT200 +PTC Resettable Fuse, Ihold = 2.0A, Itrip=3.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT300 +PTC Resettable Fuse, Ihold = 3.0A, Itrip=6.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT400 +PTC Resettable Fuse, Ihold = 4.0A, Itrip=7.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT500 +PTC Resettable Fuse, Ihold = 5.0A, Itrip=9.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT550 +PTC Resettable Fuse, Ihold = 5.5A, Itrip=10.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT600 +PTC Resettable Fuse, Ihold = 6.0A, Itrip=10.8A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT650 +PTC Resettable Fuse, Ihold = 6.5A, Itrip=12.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT700 +PTC Resettable Fuse, Ihold = 7.0A, Itrip=13.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT750 +PTC Resettable Fuse, Ihold = 7.5A, Itrip=13.1A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT800 +PTC Resettable Fuse, Ihold = 8.0A, Itrip=15.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT900 +PTC Resettable Fuse, Ihold = 9.0A, Itrip=16.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT1000 +PTC Resettable Fuse, Ihold = 10.0A, Itrip=18.5A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT1100 +PTC Resettable Fuse, Ihold = 11.0A, Itrip=20.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-RHT1300 +PTC Resettable Fuse, Ihold = 13.0A, Itrip=24.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf +ptc resettable fuse polyfuse THT +0 +2 +2 +Fuse +Fuse_Bourns_MF-SM_7.98x5.44mm +https://www.bourns.com/docs/Product-Datasheets/mfsm.pdf +bourns ptc resettable fuse polyfuse MF-SM MF-SMHT +0 +2 +2 +Fuse +Fuse_Bourns_MF-SM_9.5x6.71mm +https://www.bourns.com/docs/Product-Datasheets/mfsm.pdf +bourns ptc resettable fuse polyfuse MF-SM MF-SMHT +0 +2 +2 +Fuse +Fuse_Littelfuse-LVR100 +Littelfuse, resettable fuse, PTC, polyswitch LVR100, Ih 1A http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf +LVR100 PTC resettable polyswitch +0 +2 +2 +Fuse +Fuse_Littelfuse-LVR125 +Littelfuse, resettable fuse, PTC, polyswitch LVR125, Ih 1.25A, http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf +LVR125 PTC resettable polyswitch +0 +2 +2 +Fuse +Fuse_Littelfuse-LVR200 +Littelfuse, resettable fuse, PTC, polyswitch LVR200, Ih 2A, http://www.littelfuse.com/~/media/electronics/datasheets/resettable_ptcs/littelfuse_ptc_lvr_catalog_datasheet.pdf.pdf +LVR200 PTC resettable polyswitch +0 +2 +2 +Fuse +Fuse_Littelfuse-NANO2-451_453 +Littelfuse NANO2 https://www.littelfuse.com/~/media/electronics/datasheets/fuses/littelfuse_fuse_451_453_datasheet.pdf.pdf +Fuse Nano2 +0 +2 +2 +Fuse +Fuse_Littelfuse_372_D8.50mm +Fuse, Littelfuse, 372, 8.5x8mm, https://www.littelfuse.com/~/media/electronics/datasheets/fuses/littelfuse_fuse_372_datasheet.pdf.pdf +fuse tht radial +0 +2 +2 +Fuse +Fuse_Littelfuse_395Series +Fuse, TE5, Littelfuse/Wickmann, No. 460, No560, +Fuse TE5 Littelfuse/Wickmann No. 460 No560 +0 +2 +2 +Fuse +Fuse_Schurter_UMT250 +Surface Mount Fuse, 3 x 10.1 mm, Time-Lag T, 250 VAC, 125 VDC (https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_UMT_250.pdf) +Schurter fuse smd +0 +2 +2 +Fuse +Fuse_SunFuse-6HP +SunFuse Ceramic Slow Blow Fuse 6H_6HP.PDF +UL/CSA 6x32mm Ceramic Slow Blow Fuse +0 +2 +2 +Fuse +Fuseholder_Blade_ATO_Littelfuse_Pudenz_2_Pin +Fuseholder ATO Blade littelfuse Pudenz 2 Pin +Fuseholder ATO Blade littelfuse Pudenz 2 Pin +0 +2 +2 +Fuse +Fuseholder_Blade_Mini_Keystone_3568 +fuse holder, car blade fuse mini, http://www.keyelco.com/product-pdf.cfm?p=306 +car blade fuse mini +0 +4 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Bulgin_FX0456_Vertical_Closed +Fuseholder, 5x20, closed, vertical, Bulgin, FX0456, https://www.bulgin.com/products/pub/media/bulgin/data/Fuseholders.pdf +Fuseholder 5x20 closed vertical Bulgin FX0456 Sicherungshalter +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Bulgin_FX0457_Horizontal_Closed +Fuseholder, 5x20, closed, horizontal, Bulgin, FX0457, Sicherungshalter, +Fuseholder 5x20 closed horizontal Bulgin FX0457 Sicherungshalter +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_EATON_H15-V-1_Vertical_Closed +PCB fuse holders for 5 mm x 20 mm fuses; 250V; 10A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/bus-elx-ds-4426-h15.pdf) +fuse holder vertical 5x20mm +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_EATON_HBV_Vertical_Closed +5 mm x 20 mm fuse holders; Vertical w/ Stability Pins; 250V; 6.3-16A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/Bus_Elx_DS_2118_HB_PCB_Series.pdf) +fuse holder vertical 5x20mm +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_EATON_HBW_Vertical_Closed +5 mm x 20 mm fuse holders; Vertical w/o Stability Pins; 250V; 6.3-16A (http://www.cooperindustries.com/content/dam/public/bussmann/Electronics/Resources/product-datasheets/Bus_Elx_DS_2118_HB_PCB_Series.pdf) +fuse holder vertical 5x20mm +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Schurter_0031_8201_Horizontal_Open +Fuseholder horizontal open, 5x20mm, 500V, 16A, Schurter 0031.8201, https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_OGN.pdf +Fuseholder horizontal open 5x20 Schurter 0031.8201 +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Schurter_FAB_0031-355x_Horizontal_Closed +Fuseholder 5x20mm horizontal Shurter model FAB, Suitable for order numbers 0031.3551 and 0031.3558 (https://www.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FAB.pdf) +Fuseholder 5x20mm closed horizontal +0 +2 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Schurter_FPG4_Vertical_Closed +Shock-Safe Fuseholder, 5 x 20 mm, Slotted Cap/Fingergrip, vertical, IEC 60335-1; 250VAC/10A VDE; 500V/16A UL/CSA (https://us.schurter.com/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FPG4.pdf) +fuse holder vertical 5x20mm +0 +4 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Schurter_FUP_0031.2510_Horizontal_Closed +Shock-Safe closed Fuseholder, Schurter FUP Series, 5.0 x 20mm, Slotted Cap, horizontal, 500 VAC 4W/16A (VDE), 600V 30A (UL/CSA), order numbers: 0031.2510 (0031.2500 + 0031.2323), http://www.schurter.ch/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FUP.pdf +Fuseholder 5x20mm horizontal closed +0 +3 +2 +Fuse +Fuseholder_Cylinder-5x20mm_Stelvio-Kontek_PTF78_Horizontal_Open +https://www.tme.eu/en/Document/3b48dbe2b9714a62652c97b08fcd464b/PTF78.pdf +Fuseholder horizontal open 5x20 Stelvio-Kontek PTF/78 +0 +2 +2 +Fuse +Fuseholder_Cylinder-6.3x32mm_Schurter_0031-8002_Horizontal_Open +Fuseholder, horizontal, open, 6.3x32, Schurter, 0031.8002, https://www.schurter.com/en/datasheet/typ_OG__Holder__6.3x32.pdf +Fuseholder horizontal open 6.3x32 Schurter 0031.8002 +0 +2 +2 +Fuse +Fuseholder_Cylinder-6.3x32mm_Schurter_FUP_0031.2520_Horizontal_Closed +Shock-Safe closed Fuseholder, Schurter FUP Series, 6.3 x 32 mm, Slotted Cap, horizontal, 500 VAC 4W/16A (VDE), 600V 30A (UL/CSA), order numbers: 0031.2520 (0031.2500 + 0031.2321), http://www.schurter.ch/bundles/snceschurter/epim/_ProdPool_/newDS/en/typ_FUP.pdf +Fuseholder 6.3x32mm horizontal closed +0 +3 +2 +Fuse +Fuseholder_TR5_Littelfuse_No560_No460 +Fuse, Fuseholder, TR5, Littelfuse/Wickmann, No. 460, No560, https://www.littelfuse.com/~/media/electronics/datasheets/fuse_holders/littelfuse_fuse_holder_559_560_datasheet.pdf.pdf +Fuse Fuseholder TR5 Littelfuse/Wickmann No. 460 No560 +0 +2 +2 +Heatsink +Heatsink_35x26mm_1xFixation3mm_Fischer-SK486-35 +Heatsink, 35mm x 26mm, 1x Fixation 3mm, Fischer SK486-35 +heatsink +0 +1 +1 +Heatsink +Heatsink_38x38mm_SpringFixation +Heatsink, 38x38mm, Spring Fixation, diagonal, +heatsink +0 +4 +1 +Heatsink +Heatsink_62x40mm_2xFixation3mm +Heatsink, 62 x 40mm, 2x 3mm Drills, +heatsink +0 +2 +1 +Heatsink +Heatsink_125x35x50mm_3xFixationM3 +Heatsink, 125x35x50mm, 3 fixation holes 3.2mm +heatsink +0 +0 +0 +Heatsink +Heatsink_AAVID_573300D00010G_TO-263 +Heatsink, 12.70mm x 26.16mm x 10.16, SMD, 18K/W, TO-263, D2 Pak, https://www.shopaavid.com/Product/573300D00000G +Heatsink AAVID TO-263 D2 Pak +0 +2 +1 +Heatsink +Heatsink_Aavid-TV5G_TO220_Horizontal +Heatsink TV5G TO-220 Horizontal, https://www.shopaavid.com/Product/TV-5G +Heatsink TV5G TO-220 Horizontal +0 +0 +0 +Heatsink +Heatsink_Fischer_FK24413D2PAK_26x13mm +26x13 mm SMD heatsink for TO-252 TO-263 TO-268, https://www.fischerelektronik.de/pim/upload/fischerData/cadpdf/base/fk_244_13_d2_pak.pdf +heatsink TO-252 TO-263 TO-268 +0 +2 +1 +Heatsink +Heatsink_Fischer_SK104-STC-STIC_35x13mm_2xDrill2.5mm +Heatsink, 35mm x 13mm, 2x Fixation 2,5mm Drill, Soldering, Fischer SK104-STC-STIC, +Heatsink fischer TO-220 +0 +2 +1 +Heatsink +Heatsink_Fischer_SK104-STCB_35x13mm__2xDrill3.5mm_ScrewM3 +Heatsink, 35mm x 13mm, 2x Fixation 2,5mm Drill, Soldering, Fischer SK104-STC-STIC, +Heatsink fischer TO-220 +0 +2 +1 +Heatsink +Heatsink_Fischer_SK129-STS_42x25mm_2xDrill2.5mm +Heatsink, Fischer SK129 +heatsink fischer +0 +2 +1 +Heatsink +Heatsink_SheetType_50x7mm_2Fixations +Heatsink, Sheet type, 50x7mm, 2 fixations (solder), +Heatsink sheet +0 +2 +1 +Heatsink +Heatsink_Stonecold_HS-132_32x14mm_2xFixation1.5mm +Heatsink, StoneCold HS +heatsink +0 +2 +1 +Inductor_SMD +L_6.3x6.3_H3 +Choke, SMD, 6.3x6.3mm 3mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_7.3x7.3_H3.5 +Choke, SMD, 7.3x7.3mm 3.5mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_7.3x7.3_H4.5 +Choke, SMD, 7.3x7.3mm 4.5mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_10.4x10.4_H4.8 +Choke, SMD, 10.4x10.4mm 4.8mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_12x12mm_H4.5mm +Choke, SMD, 12x12mm 4.5mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_12x12mm_H6mm +Choke, SMD, 12x12mm 6mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_12x12mm_H8mm +Choke, SMD, 12x12mm 8mm height +Choke SMD +0 +2 +2 +Inductor_SMD +L_0201_0603Metric +Inductor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +inductor +0 +4 +2 +Inductor_SMD +L_0402_1005Metric +Inductor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_0603_1608Metric +Inductor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_0603_1608Metric_Pad1.05x0.95mm_HandSolder +Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_0805_2012Metric +Inductor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_0805_2012Metric_Pad1.15x1.40mm_HandSolder +Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_01005_0402Metric +Inductor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +inductor +0 +4 +2 +Inductor_SMD +L_1008_2520Metric +Inductor SMD 1008 (2520 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://ecsxtal.com/store/pdf/ECS-MPI2520-SMD-POWER-INDUCTOR.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_1206_3216Metric +Inductor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_1206_3216Metric_Pad1.42x1.75mm_HandSolder +Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_1210_3225Metric +Inductor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_1210_3225Metric_Pad1.42x2.65mm_HandSolder +Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_1806_4516Metric +Inductor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_1806_4516Metric_Pad1.57x1.80mm_HandSolder +Capacitor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_1812_4532Metric +Inductor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_1812_4532Metric_Pad1.30x3.40mm_HandSolder +Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_2010_5025Metric +Inductor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_2010_5025Metric_Pad1.52x2.65mm_HandSolder +Capacitor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_2512_6332Metric +Inductor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_2512_6332Metric_Pad1.52x3.35mm_HandSolder +Capacitor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_2816_7142Metric +Inductor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +inductor +0 +2 +2 +Inductor_SMD +L_2816_7142Metric_Pad3.20x4.45mm_HandSolder +Capacitor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +inductor handsolder +0 +2 +2 +Inductor_SMD +L_Abracon_ASPI-0630LR +smd shielded power inductor https://abracon.com/Magnetics/power/ASPI-0630LR.pdf +inductor abracon smd shielded +0 +2 +2 +Inductor_SMD +L_Abracon_ASPI-3012S +smd shielded power inductor http://www.abracon.com/Magnetics/power/ASPI-3012S.pdf +inductor abracon smd shielded +0 +2 +2 +Inductor_SMD +L_Bourns-SRN1060 +Bourns SRN1060 series SMD inductor https://www.bourns.com/docs/Product-Datasheets/SRN1060.pdf +Bourns SRN1060 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns-SRN4018 +Bourns SRN4018 series SMD inductor, https://www.bourns.com/docs/Product-Datasheets/SRN4018.pdf +Bourns SRN4018 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns-SRN6028 +Bourns SRN6028 series SMD inductor +Bourns SRN6028 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns-SRN8040_8x8.15mm +Bourns SRN8040 series SMD inductor 8x8.15mm, https://www.bourns.com/docs/Product-Datasheets/SRN8040.pdf +Bourns SRN8040 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns-SRR1005 +Bourns SRR1005 series SMD inductor +Bourns SRR1005 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns-SRU1028_10.0x10.0mm +Bourns SRU1028 series SMD inductor, https://www.bourns.com/docs/Product-Datasheets/SRU1028.pdf +Bourns SRU1028 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns-SRU8043 +Bourns SRU8043 series SMD inductor +Bourns SRU8043 SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns_SDR1806 +https://www.bourns.com/docs/Product-Datasheets/SDR1806.pdf +Bourns SDR1806 +0 +2 +2 +Inductor_SMD +L_Bourns_SRN6045TA +http://www.bourns.com/docs/product-datasheets/srn6045ta.pdf +Semi-shielded Power Inductor +0 +2 +2 +Inductor_SMD +L_Bourns_SRN8040TA +https://www.bourns.com/docs/product-datasheets/srn8040ta.pdf +Inductor +0 +2 +2 +Inductor_SMD +L_Bourns_SRP1245A +Bourns SRP1245A series SMD inductor http://www.bourns.com/docs/Product-Datasheets/SRP1245A.pdf +Bourns SRP1245A SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns_SRP2313AA +Bourns SRR1260 series SMD inductor http://www.bourns.com/docs/product-datasheets/srp2313aa.pdf +Bourns SRR1260 SMD inductor +0 +4 +2 +Inductor_SMD +L_Bourns_SRP7028A_7.3x6.6mm +Shielded Power Inductors (https://www.bourns.com/docs/product-datasheets/srp7028a.pdf) +Shielded Inductors Bourns SMD SRP7028A +0 +2 +2 +Inductor_SMD +L_Bourns_SRR1210A +Bourns SRR1210A series SMD inductor https://www.bourns.com/docs/Product-Datasheets/SRR1210A.pdf +Bourns SRR1210A SMD inductor +0 +2 +2 +Inductor_SMD +L_Bourns_SRR1260 +Bourns SRR1260 series SMD inductor http://www.bourns.com/docs/Product-Datasheets/SRR1260.pdf +Bourns SRR1260 SMD inductor +0 +2 +2 +Inductor_SMD +L_Coilcraft_LPS4018 +SMD Inductor Coilcraft LPS4018 https://www.coilcraft.com/pdfs/lps4018.pdf +L Coilcraft LPS4018 +0 +2 +2 +Inductor_SMD +L_Coilcraft_LPS5030 +Shielded Power Inductor SMD, Coilcraft LPS5030, https://www.coilcraft.com/pdfs/lps5030.pdf, StepUp generated footprint +inductor +0 +2 +2 +Inductor_SMD +L_Coilcraft_XAL60xx_6.36x6.56mm +Coilcraft XAL60xx series, https://www.coilcraft.com/pdfs/xal60xx.pdf +L Coilcraft XAL60xx +0 +2 +2 +Inductor_SMD +L_Coilcraft_XAL5030 +L_Coilcraft_XAL5030 +L Coilcraft XAL5030 +0 +2 +2 +Inductor_SMD +L_Coilcraft_XxL4020 +L_Coilcraft_XxL4020 https://www.coilcraft.com/pdfs/xfl4020.pdf +L Coilcraft XxL4020 +0 +2 +2 +Inductor_SMD +L_Coilcraft_XxL4030 +L_Coilcraft_XxL4030 https://www.coilcraft.com/pdfs/xfl4030.pdf +L Coilcraft XxL4030 +0 +2 +2 +Inductor_SMD +L_Coilcraft_XxL4040 +L_Coilcraft_XxL4040 https://www.coilcraft.com/pdfs/xal4000.pdf +L Coilcraft XxL4040 +0 +2 +2 +Inductor_SMD +L_CommonMode_Delevan_4222 +API Delevan, Surface Mount Common Mode Bead, 4222 4222R, http://www.delevan.com/seriesPDFs/4222.pdf +surface mount common mode bead +0 +4 +4 +Inductor_SMD +L_CommonMode_Wuerth_WE-SL2 +http://katalog.we-online.de/en/pbs/WE-SL2?sid=5fbec16187#vs_t1:c1_ct:1 +Wuerth WE-SL2 +0 +4 +4 +Inductor_SMD +L_Fastron_PISN +Choke, Drossel, PISN, SMD, Fastron, +Choke Drossel PISN SMD Fastron +0 +2 +2 +Inductor_SMD +L_Fastron_PISN_Handsoldering +Choke, Drossel, PISN, SMD, Fastron, +Choke Drossel PISN SMD Fastron +0 +2 +2 +Inductor_SMD +L_Fastron_PISR +Choke, Drossel, PISR, Fastron, SMD, +Choke Drossel PISR Fastron SMD +0 +2 +2 +Inductor_SMD +L_Fastron_PISR_Handsoldering +Choke, Drossel, PISR, Fastron, SMD, +Choke Drossel PISR Fastron SMD +0 +2 +2 +Inductor_SMD +L_Murata_DEM35xxC +https://www.murata.com/~/media/webrenewal/products/inductor/chip/tokoproducts/wirewoundferritetypeforpl/m_dem3518c.ashx +Inductor SMD DEM35xxC +0 +2 +2 +Inductor_SMD +L_Murata_LQH2MCNxxxx02_2.0x1.6mm +Inductor, Murata, LQH2MCN_02 series, 1.6x2.0x0.9mm (https://search.murata.co.jp/Ceramy/image/img/P02/JELF243A-0053.pdf) +chip coil inductor Murata LQH2MC +0 +2 +2 +Inductor_SMD +L_Murata_LQH55DN_5.7x5.0mm +Inductor, SMD, 5.7x5.0x4.7mm, https://search.murata.co.jp/Ceramy/image/img/P02/JELF243A-0045.pdf +inductor smd +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_1turn_HDM0131A +Neosid, Air-Coil, SML, 1turn, HDM0131A, +Neosid Air-Coil SML 1turn HDM0131A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_2turn_HAM0231A +Neosid, Air-Coil, SML, 2turn, HAM0231A, +Neosid Air-Coil SML 2turn HAM0231A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_2turn_HDM0231A +Neosid, Air-Coil, SML, 2turn, HDM0231A, +Neosid Air-Coil SML 2turn HDM0231A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_3turn_HAM0331A +Neosid, Air-Coil, SML, 2turn, HAM0331A, +Neosid Air-Coil SML 3turn HAM0331A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_3turn_HDM0331A +Neosid, Air-Coil, SML, 3turn, HDM0331A, +Neosid Air-Coil SML 3turn HDM0331A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_4turn_HAM0431A +Neosid, Air-Coil, SML, 4turn, HAM0431A, +Neosid Air-Coil SML 4turn HAM0431A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_4turn_HDM0431A +Neosid, Air-Coil, SML, 4turn, HDM0431A, +Neosid Air-Coil SML 4turn HDM0431A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_5turn_HAM0531A +Neosid, Air-Coil, SML, 5turn, HAM0531A, +Neosid Air-Coil SML 5turn HAM0531A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_5turn_HDM0531A +Neosid, Air-Coil, SML, 5turn, HDM0531A, +Neosid Air-Coil SML 5turn HDM0531A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_6-10turn_HAM0631A-HAM1031A +Neosid, Air-Coil, SML, 6-10turn, HAM0631A-HAM1031A, +Neosid Air-Coil SML 6-10turn HAM0631A-HAM1031A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_6-10turn_HDM0431A-HDM1031A +Neosid, Air-Coil, SML, 6-10turn, HDM0431A-HDM1031A, +Neosid Air-Coil SML 6-10turn HDM0431A-HDM1031A +0 +2 +2 +Inductor_SMD +L_Neosid_Air-Coil_SML_6turn_HAM0631A +Neosid, Air-Coil, SML, 6turn, HAM0631A, +Neosid Air-Coil SML 6turn HAM0631A +0 +2 +2 +Inductor_SMD +L_Neosid_MicroCoil_Ms36-L +Neosid, Micro Coil, Inductor, Ms36-L, SMD, Fixed inductor, anti clockwise, https://neosid.de/en/products/inductors/rod-core-chokes/smd-rod-core-chokes/52026/ms-36/7-h?c=94 +Neosid Micro Coil Inductor Ms36-L SMD Fixed inductor anti clockwise +0 +2 +2 +Inductor_SMD +L_Neosid_Ms42 +Neosid, Inductor, SMs42, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_Ms42.pdf +Neosid Inductor SMs42 Fixed inductor SMD magneticaly shielded +0 +2 +2 +Inductor_SMD +L_Neosid_Ms50 +Neosid, Power Inductor, Ms50, SMD, Fixed inductor, https://neosid.de/import-data/product-pdf/neoFestind_Ms50.pdf +Neosid Power Inductor Ms50 SMD Fixed inductor +0 +2 +2 +Inductor_SMD +L_Neosid_Ms50T +Neosid, Power Inductor, Ms50T, SMD, Fixed inductor, high temperature, https://neosid.de/import-data/product-pdf/neoFestind_Ms50T.pdf +Neosid Power Inductor Ms50T SMD Fixed inductor high temperature +0 +2 +2 +Inductor_SMD +L_Neosid_Ms85 +Neosid, Ms85, Ms85T, SMD Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms85.pdf +Neosid Ms85 Ms85T SMD Inductor Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_Ms85T +Neosid, Ms85, Ms85T, SMD Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms85T.pdf +Neosid Ms85 Ms85T SMD Inductor Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_Ms95 +Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95.pdf +NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_Ms95T +Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95T.pdf +NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_Ms95a +Neosid,Inductor,Ms95, Ms95a, Ms95T, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_Ms95a.pdf +NeosidInductorMs95 Ms95a Ms95T Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-NE95H +Neosid, Inductor,SM-NE95H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE95H.pdf +Neosid Inductor SM-NE95H Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-NE127 +Neosid, Inductor, SM-NE127, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE127.pdf +Neosid Inductor SM-NE127 Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-NE127_HandSoldering +Neosid, Inductor, SM-NE127, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE127.pdf +Neosid Inductor SM-NE127 Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-NE150 +Neosid, Inductor, SM-NE150, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMNE150.pdf +Neosid Inductor SM-NE150 Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-PIC0512H +Neosid, Inductor, PIC0512H, Power Inductor, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0512H.pdf +Neosid Inductor PIC0512H Power Inductor Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-PIC0602H +Neosid, Power Inductor, SM-PIC0602H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0602H.pdf +Neosid Power Inductor SM-PIC0602H Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-PIC0612H +Neosid, Power Inductor, SM-PIC0612H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC0612H.pdf +Neosid Power Inductor SM-PIC0612H Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SM-PIC1004H +Neosid, Inductor, SM-PIC1004H, Fixed inductor, SMD, https://neosid.de/import-data/product-pdf/neoFestind_SMPIC1004H.pdf +Neosid Inductor SM-PIC1004H Fixed inductor SMD +0 +2 +2 +Inductor_SMD +L_Neosid_SMS-ME3010 +Neosid, Inductor, SMS-ME3010, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMSME3010.pdf +Neosid Inductor SMS-ME3010 Fixed inductor SMD magnetically shielded +0 +2 +2 +Inductor_SMD +L_Neosid_SMS-ME3015 +Neosid, Power Inductor, SMS-ME3015, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMSME3015.pdf +Neosid Power Inductor SMS-ME3015 Fixed inductor SMD magnetically shielded +0 +2 +2 +Inductor_SMD +L_Neosid_SMs42 +Neosid, Inductor, SMs42, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs42.pdf +Neosid Inductor SMs42 Fixed inductor SMD magneticaly shielded +0 +2 +2 +Inductor_SMD +L_Neosid_SMs50 +Neosid, Inductor, SMs50, Fixed inductor, SMD, magneticaly shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs50.pdf +Neosid Inductor SMs50 Fixed inductor SMD magneticaly shielded +0 +2 +2 +Inductor_SMD +L_Neosid_SMs85 +Neosid, Inductor, SMs85, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_ma_SMs85.pdf +Neosid Inductor SMs85 Fixed inductor SMD magnetically shielded +0 +2 +2 +Inductor_SMD +L_Neosid_SMs95_SMs95p +Neosid, Inductor, SMs95, Fixed inductor, SMD, magnetically shielded, https://neosid.de/import-data/product-pdf/neoFestind_SMs95SMs95p.pdf +Neosid Inductor SMs95 Fixed inductor SMD magnetically shielded +0 +2 +2 +Inductor_SMD +L_Pulse_PA4320 +Inductor SMD Pulse PA4320 http://productfinder.pulseeng.com/products/datasheets/P787.pdf +Inductor SMD Pulse PA4320 +0 +2 +2 +Inductor_SMD +L_Sagami_CER1242B +Inductor, Sagami, h=4.5mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf +inductor sagami cer12xxb smd +0 +2 +2 +Inductor_SMD +L_Sagami_CER1257B +Inductor, Sagami, h=6.0mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf +inductor sagami cer12xxb smd +0 +2 +2 +Inductor_SMD +L_Sagami_CER1277B +Inductor, Sagami, h=8.0mm, http://www.sagami-elec.co.jp/file/CER1242B-CER1257B-CER1277B.pdf +inductor sagami cer12xxb smd +0 +2 +2 +Inductor_SMD +L_Sagami_CWR1242C +Sagami power inductor, CWR1242C, H=4.5mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf) +inductor sagami cwr12xx smd +0 +4 +2 +Inductor_SMD +L_Sagami_CWR1257C +Sagami power inductor, CWR1242C, H=6.0mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf) +inductor sagami cwr12xx smd +0 +4 +2 +Inductor_SMD +L_Sagami_CWR1277C +Sagami power inductor, CWR1242C, H=7.7mm (http://www.sagami-elec.co.jp/file/16Car_SMDCwr.pdf) +inductor sagami cwr12xx smd +0 +4 +2 +Inductor_SMD +L_SigTra_SC3316F +http://www.signaltransformer.com/sites/all/pdf/smd/P080_SC3316F.pdf +Choke +0 +2 +2 +Inductor_SMD +L_Sumida_CDMC6D28_7.25x6.5mm +SMD Power Inductor (http://products.sumida.com/products/pdf/CDMC6D28.pdf) +Inductor Sumida SMD CDMC6D28 +0 +2 +2 +Inductor_SMD +L_Sunlord_MWSA0518_5.4x5.2mm +Inductor, Sunlord, MWSA0518, 5.4mmx5.2mm +inductor Sunlord smd +0 +2 +2 +Inductor_SMD +L_TDK_NLV25_2.5x2.0mm +TDK NLV25, 2.5x2.0x1.8mm, https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_standard_nlv25-ef_en.pdf +tdk nlv25 nlcv25 nlfv25 +0 +2 +2 +Inductor_SMD +L_TDK_NLV32_3.2x2.5mm +TDK NLV32, 3.2x2.5x2.2mm, https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_standard_nlv32-ef_en.pdf +tdk nlv32 nlcv32 nlfv32 +0 +2 +2 +Inductor_SMD +L_TDK_SLF6025 +Inductor, TDK, SLF6025, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6025_en.pdf) +Inductor TDK_SLF6025 +0 +2 +2 +Inductor_SMD +L_TDK_SLF6028 +Inductor, TDK, SLF6028, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6028_en.pdf) +Inductor TDK_SLF6028 +0 +2 +2 +Inductor_SMD +L_TDK_SLF6045 +Inductor, TDK, SLF6045, 6.0mmx6.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf6045_en.pdf) +Inductor TDK_SLF6045 +0 +2 +2 +Inductor_SMD +L_TDK_SLF7032 +Inductor, TDK, SLF7032, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7032_en.pdf) +Inductor TDK_SLF7032 +0 +2 +2 +Inductor_SMD +L_TDK_SLF7045 +Inductor, TDK, SLF7045, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7045_en.pdf) +Inductor TDK_SLF7045 +0 +2 +2 +Inductor_SMD +L_TDK_SLF7055 +Inductor, TDK, SLF7055, 7.0mmx7.0mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/document/catalog/smd/inductor_commercial_power_slf7055_en.pdf) +Inductor TDK_SLF7055 +0 +2 +2 +Inductor_SMD +L_TDK_SLF10145 +Inductor, TDK, SLF10145, 10.1mmx10.1mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf10145-h_en.pdf) +Inductor TDK_SLF10145 +0 +2 +2 +Inductor_SMD +L_TDK_SLF10165 +Inductor, TDK, SLF10165, 10.1mmx10.1mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_power_slf10165_en.pdf) +Inductor TDK_SLF10165 +0 +2 +2 +Inductor_SMD +L_TDK_SLF12555 +Inductor, TDK, SLF12555, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_commercial_power_slf12555_en.pdf) +Inductor SLF12555 +0 +2 +2 +Inductor_SMD +L_TDK_SLF12565 +Inductor, TDK, SLF12565, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf12565-h_en.pdf) +Inductor SLF12565 +0 +2 +2 +Inductor_SMD +L_TDK_SLF12575 +Inductor, TDK, SLF12575, 12.5mmx12.5mm (Script generated with StandardBox.py) (https://product.tdk.com/info/en/catalog/datasheets/inductor_automotive_power_slf12575-h_en.pdf) +Inductor SLF12575 +0 +2 +2 +Inductor_SMD +L_TDK_VLF10040 +Inductor,TDK, TDK-VLP-8040, 8.6mmx8.6mm +inductor TDK VLP smd VLF10040 +0 +2 +2 +Inductor_SMD +L_TDK_VLP8040 +Inductor,TDK, TDK-VLP-8040, 8.6mmx8.6mm +inductor TDK VLP smd VLP8040 +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_MD-1616 +Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-1616, 1.6mmx1.6mm +inductor taiyo-yuden md smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_MD-2020 +Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-2020, 2.0mmx2.0mm +inductor taiyo-yuden md smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_MD-3030 +Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-3030, 3.0mmx3.0mm +inductor taiyo-yuden md smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_MD-4040 +Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-4040, 4.0mmx4.0mm +inductor taiyo-yuden md smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_MD-5050 +Inductor, Taiyo Yuden, MD series, Taiyo-Yuden_MD-5050, 5.0mmx5.0mm +inductor taiyo-yuden md smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-20xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-20xx, 2.0mmx2.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-20xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-20xx, 2.0mmx2.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-24xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-24xx, 2.4mmx2.4mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-24xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-24xx, 2.4mmx2.4mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-30xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-30xx, 3.0mmx3.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-30xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-30xx, 3.0mmx3.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-40xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-40xx, 4.0mmx4.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-40xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-40xx, 4.0mmx4.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-50xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-50xx, 4.9mmx4.9mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-50xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-50xx, 4.9mmx4.9mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-60xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-60xx, 6.0mmx6.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-60xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-60xx, 6.0mmx6.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-80xx +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-80xx, 8.0mmx8.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-80xx_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-80xx, 8.0mmx8.0mm +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-10050_9.8x10.0mm +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-10050, 9.8mmx10.0mm, https://ds.yuden.co.jp/TYCOMPAS/or/specSheet?pn=NR10050T1R3N +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_Taiyo-Yuden_NR-10050_9.8x10.0mm_HandSoldering +Inductor, Taiyo Yuden, NR series, Taiyo-Yuden_NR-10050, 9.8mmx10.0mm, https://ds.yuden.co.jp/TYCOMPAS/or/specSheet?pn=NR10050T1R3N +inductor taiyo-yuden nr smd +0 +2 +2 +Inductor_SMD +L_TracoPower_TCK-141 +Choke, SMD, 4.0x4.0mm 2.1mm height, https://www.tracopower.com/products/tck141.pdf +Choke SMD +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-1212 +Inductor, Vishay, IHLP series, 3.0mmx3.0mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-1616 +Inductor, Vishay, IHLP series, 4.1mmx4.1mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-2020 +Inductor, Vishay, IHLP series, 5.1mmx5.1mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-2525 +Inductor, Vishay, IHLP series, 6.3mmx6.3mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-4040 +Inductor, Vishay, IHLP series, 10.2mmx10.2mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-5050 +Inductor, Vishay, IHLP series, 12.7mmx12.7mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHLP-6767 +Inductor, Vishay, IHLP series, 17.0mmx17.0mm +inductor vishay ihlp smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHSM-3825 +Inductor, Vishay, Vishay_IHSM-3825, http://www.vishay.com/docs/34018/ihsm3825.pdf, 11.2mmx6.3mm +inductor vishay icsm smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHSM-4825 +Inductor, Vishay, Vishay_IHSM-4825, http://www.vishay.com/docs/34019/ihsm4825.pdf, 13.7mmx6.3mm +inductor vishay icsm smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHSM-5832 +Inductor, Vishay, Vishay_IHSM-5832, http://www.vishay.com/docs/34020/ihsm5832.pdf, 16.3mmx8.1mm +inductor vishay icsm smd +0 +2 +2 +Inductor_SMD +L_Vishay_IHSM-7832 +Inductor, Vishay, Vishay_IHSM-7832, http://www.vishay.com/docs/34021/ihsm7832.pdf, 19.8mmx8.1mm +inductor vishay icsm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1030 +Inductor, Wuerth Elektronik, Wuerth_HCI-1030, 10.6mmx10.6mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1040 +Inductor, Wuerth Elektronik, Wuerth_HCI-1040, 10.2mmx10.2mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1050 +Inductor, Wuerth Elektronik, Wuerth_HCI-1050, 10.2mmx10.2mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1335 +Inductor, Wuerth Elektronik, Wuerth_HCI-1335, 12.8mmx12.8mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1350 +Inductor, Wuerth Elektronik, Wuerth_HCI-1350, 12.8mmx12.8mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1365 +Inductor, Wuerth Elektronik, Wuerth_HCI-1365, 12.8mmx12.8mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-1890 +Inductor, Wuerth Elektronik, Wuerth_HCI-1890, 18.2mmx18.2mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-2212 +Inductor, Wuerth Elektronik, Wuerth_HCI-2212, 22.5mmx22.0mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-5040 +Inductor, Wuerth Elektronik, Wuerth_HCI-5040, 5.5mmx5.2mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-7030 +Inductor, Wuerth Elektronik, Wuerth_HCI-7030, 6.9mmx6.9mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-7040 +Inductor, Wuerth Elektronik, Wuerth_HCI-7040, 6.9mmx6.9mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCI-7050 +Inductor, Wuerth Elektronik, Wuerth_HCI-7050, 6.9mmx6.9mm +inductor Wuerth hci smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1050 +Inductor, Wuerth Elektronik, Wuerth_HCM-1050, 10.2mmx7.0mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1052 +Inductor, Wuerth Elektronik, Wuerth_HCM-1052, 10.5mmx10.3mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1070 +Inductor, Wuerth Elektronik, Wuerth_HCM-1070, 10.1mmx7.0mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1078 +Inductor, Wuerth Elektronik, Wuerth_HCM-1078, 9.4mmx6.2mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1190 +Inductor, Wuerth Elektronik, Wuerth_HCM-1190, 10.5mmx11.0mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1240 +Inductor, Wuerth Elektronik, Wuerth_HCM-1240, 10.0mmx11.8mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1350 +Inductor, Wuerth Elektronik, Wuerth_HCM-1350, 13.5mmx13.3mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-1390 +Inductor, Wuerth Elektronik, Wuerth_HCM-1390, 12.5mmx13.0mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-7050 +Inductor, Wuerth Elektronik, Wuerth_HCM-7050, 7.2mmx7.0mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_HCM-7070 +Inductor, Wuerth Elektronik, Wuerth_HCM-7070, 7.4mmx7.2mm +inductor Wuerth hcm smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-1610 +Inductor, Wuerth Elektronik, Wuerth_MAPI-1610, 1.6mmx1.6mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-2010 +Inductor, Wuerth Elektronik, Wuerth_MAPI-2010, 2.0mmx1.6mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-2506 +Inductor, Wuerth Elektronik, Wuerth_MAPI-2506, 2.5mmx2.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-2508 +Inductor, Wuerth Elektronik, Wuerth_MAPI-2508, 2.5mmx2.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-2510 +Inductor, Wuerth Elektronik, Wuerth_MAPI-2510, 2.5mmx2.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-2512 +Inductor, Wuerth Elektronik, Wuerth_MAPI-2512, 2.5mmx2.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-3010 +Inductor, Wuerth Elektronik, Wuerth_MAPI-3010, 3.0mmx3.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-3012 +Inductor, Wuerth Elektronik, Wuerth_MAPI-3012, 3.0mmx3.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-3015 +Inductor, Wuerth Elektronik, Wuerth_MAPI-3015, 3.0mmx3.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-3020 +Inductor, Wuerth Elektronik, Wuerth_MAPI-3020, 3.0mmx3.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-4020 +Inductor, Wuerth Elektronik, Wuerth_MAPI-4020, 4.0mmx4.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_MAPI-4030 +Inductor, Wuerth Elektronik, Wuerth_MAPI-4030, 4.0mmx4.0mm +inductor Wuerth smd +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-DD-Typ-L-Typ-XL-Typ-XXL +Shielded Coupled Inductor, Wuerth Elektronik, WE-DD, SMD, Typ L, Typ XL, Typ XXL, https://katalog.we-online.com/pbs/datasheet/744874001.pdf +Choke Coupled Double Inductor SMD Wuerth WE-DD TypL TypXL TypXXL +0 +4 +4 +Inductor_SMD +L_Wuerth_WE-DD-Typ-M-Typ-S +Shielded Coupled Inductor, Wuerth Elektronik, WE-DD, SMD, Typ M, Typ S, https://katalog.we-online.com/pbs/datasheet/744878001.pdf, https://katalog.we-online.de/pbs/datasheet/744877001.pdf +Choke Coupled Double Inductor SMD Wuerth WE-DD TypM TypS +0 +4 +4 +Inductor_SMD +L_Wuerth_WE-PD-Typ-7345 +Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, 7345, https://katalog.we-online.com/pbs/datasheet/744777001.pdf +Choke Shielded Power Inductor WE-PD 7345 Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD-Typ-LS +Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, Typ LS, https://katalog.we-online.com/pbs/datasheet/7447715906.pdf +Choke Shielded Power Inductor WE-PD TypLS Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD-Typ-LS_Handsoldering +Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMD, Typ LS, Handsoldering, https://katalog.we-online.com/pbs/datasheet/7447715906.pdf +Choke Shielded Power Inductor WE-PD TypLS Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD-Typ-M-Typ-S +Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMT, Typ M, Typ S, https://katalog.we-online.com/pbs/datasheet/744778005.pdf +Choke Shielded Power Inductor WE-PD TypM TypS Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD-Typ-M-Typ-S_Handsoldering +Shielded Power Inductor, Wuerth Elektronik, WE-PD, SMT, Typ M, Typ S, Handsoldering, https://katalog.we-online.com/pbs/datasheet/744778005.pdf +Choke Shielded Power Inductor WE-PD TypM TypS Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD2-Typ-L +Power Inductor, Wuerth Elektronik, WE-PD2, SMD, Typ L, , https://katalog.we-online.com/pbs/datasheet/74477510.pdf +Choke Power Inductor WE-PD2 TypL Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD2-Typ-MS +Power Inductor, Wuerth Elektronik, WE-PD2, SMD, Typ MS, https://katalog.we-online.com/pbs/datasheet/744774022.pdf +Choke Power Inductor WE-PD2 TypMS Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD2-Typ-XL +Power Inductor, Wuerth Elektronik, WE-PD2, SMT, Typ XL, https://katalog.we-online.com/pbs/datasheet/744776012.pdf +Choke Power Inductor WE-PD2 TypXL Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PD4-Typ-X +Power Inductor, Wuerth Elektronik, WE-PD4, SMT, Typ X, https://katalog.we-online.de/pbs/datasheet/74458001.pdf +Choke Power Inductor WE-PD4 TypX Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PDF +Shielded Power Inductor, Wuerth Elektronik, WE-PDF, SMD, https://katalog.we-online.de/pbs/datasheet/7447797022.pdf +Choke Shielded Power Inductor WE-PDF Wuerth +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-PDF_Handsoldering +Shielded Power Inductor, Wuerth Elektronik, WE-PDF, SMD, Handsoldering, https://katalog.we-online.de/pbs/datasheet/7447797022.pdf +Choke Shielded Power Inductor WE-PDF Wuerth Handsoldering +0 +2 +2 +Inductor_SMD +L_Wuerth_WE-TPC-3816 +L_Wuerth_WE-TPC-3816 StepUp generated footprint, http://katalog.we-online.de/pbs/datasheet/7440310047.pdf +wurth wuerth smd inductor +0 +2 +2 +Inductor_THT +Choke_EPCOS_B82722A +Current-Compensated Ring Core Double Chokes, EPCOS, B82722A, 22.3mmx22.7mm, https://en.tdk.eu/inf/30/db/ind_2008/b82722a_j.pdf +chokes epcos tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN102-04-14.0x14.0mm +Current-compensated Chokes, Scaffner, RN102-04, 14.0mmx14.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN112-04-17.7x17.1mm +Current-compensated Chokes, Scaffner, RN112-04, 17.7mmx17.1mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN114-04-22.5x21.5mm +Current-compensated Chokes, Scaffner, RN114-04, 22.5mmx21.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN116-04-22.5x21.5mm +Current-compensated Chokes, Scaffner, RN116-04, 22.5mmx21.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN122-04-28.0x27.0mm +Current-compensated Chokes, Scaffner, RN122-04, 28.0mmx27.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN142-04-33.1x32.5mm +Current-compensated Chokes, Scaffner, RN142-04, 33.1mmx32.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN143-04-33.1x32.5mm +Current-compensated Chokes, Scaffner, RN143-04, 33.1mmx32.5mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN152-04-43.0x41.8mm +Current-compensated Chokes, Scaffner, RN152-04, 43.0mmx41.8mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN202-04-8.8x18.2mm +Current-compensated Chokes, Scaffner, RN202-04, 8.8mmx18.2mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN204-04-9.0x14.0mm +Current-compensated Chokes, Scaffner, RN204-04, 9.0mmx14.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN212-04-12.5x18.0mm +Current-compensated Chokes, Scaffner, RN212-04, 12.5mmx18.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN214-04-15.5x23.0mm +Current-compensated Chokes, Scaffner, RN214-04, 15.5mmx23.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN216-04-15.5x23.0mm +Current-compensated Chokes, Scaffner, RN216-04, 15.5mmx23.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN222-04-18.0x31.0mm +Current-compensated Chokes, Scaffner, RN222-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN232-04-18.0x31.0mm +Current-compensated Chokes, Scaffner, RN232-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +Choke_Schaffner_RN242-04-18.0x31.0mm +Current-compensated Chokes, Scaffner, RN242-04, 18.0mmx31.0mm https://www.schaffner.com/products/download/product/datasheet/rn-series-common-mode-chokes-new/ +chokes schaffner tht +0 +4 +4 +Inductor_THT +L_Axial_L5.0mm_D3.6mm_P10.00mm_Horizontal_Murata_BL01RN1A2A2 +Inductor, Murata BL01RN1A2A2, Axial, Horizontal, pin pitch=10.00mm, length*diameter=5*3.6mm, https://www.murata.com/en-global/products/productdetail?partno=BL01RN1A2A2%23 +inductor axial horizontal +0 +2 +2 +Inductor_THT +L_Axial_L5.3mm_D2.2mm_P2.54mm_Vertical_Vishay_IM-1 +Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf +Inductor Axial series Axial Vertical pin pitch 2.54mm length 5.3mm diameter 2.2mm Vishay IM-1 +0 +2 +2 +Inductor_THT +L_Axial_L5.3mm_D2.2mm_P7.62mm_Horizontal_Vishay_IM-1 +Inductor, Axial series, Axial, Horizontal, pin pitch=7.62mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf +Inductor Axial series Axial Horizontal pin pitch 7.62mm length 5.3mm diameter 2.2mm Vishay IM-1 +0 +2 +2 +Inductor_THT +L_Axial_L5.3mm_D2.2mm_P10.16mm_Horizontal_Vishay_IM-1 +Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=5.3*2.2mm^2, Vishay, IM-1, http://www.vishay.com/docs/34030/im.pdf +Inductor Axial series Axial Horizontal pin pitch 10.16mm length 5.3mm diameter 2.2mm Vishay IM-1 +0 +2 +2 +Inductor_THT +L_Axial_L6.6mm_D2.7mm_P2.54mm_Vertical_Vishay_IM-2 +Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=6.6*2.7mm^2, Vishay, IM-2, http://www.vishay.com/docs/34030/im.pdf +Inductor Axial series Axial Vertical pin pitch 2.54mm length 6.6mm diameter 2.7mm Vishay IM-2 +0 +2 +2 +Inductor_THT +L_Axial_L6.6mm_D2.7mm_P10.16mm_Horizontal_Vishay_IM-2 +Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=6.6*2.7mm^2, Vishay, IM-2, http://www.vishay.com/docs/34030/im.pdf +Inductor Axial series Axial Horizontal pin pitch 10.16mm length 6.6mm diameter 2.7mm Vishay IM-2 +0 +2 +2 +Inductor_THT +L_Axial_L7.0mm_D3.3mm_P2.54mm_Vertical_Fastron_MICC +Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 2.54mm length 7mm diameter 3.3mm Fastron MICC +0 +2 +2 +Inductor_THT +L_Axial_L7.0mm_D3.3mm_P5.08mm_Vertical_Fastron_MICC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 7mm diameter 3.3mm Fastron MICC +0 +2 +2 +Inductor_THT +L_Axial_L7.0mm_D3.3mm_P10.16mm_Horizontal_Fastron_MICC +Inductor, Axial series, Axial, Horizontal, pin pitch=10.16mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 10.16mm length 7mm diameter 3.3mm Fastron MICC +0 +2 +2 +Inductor_THT +L_Axial_L7.0mm_D3.3mm_P12.70mm_Horizontal_Fastron_MICC +Inductor, Axial series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=7*3.3mm^2, Fastron, MICC, http://www.fastrongroup.com/image-show/70/MICC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 12.7mm length 7mm diameter 3.3mm Fastron MICC +0 +2 +2 +Inductor_THT +L_Axial_L9.5mm_D4.0mm_P2.54mm_Vertical_Fastron_SMCC +Inductor, Axial series, Axial, Vertical, pin pitch=2.54mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf +Inductor Axial series Axial Vertical pin pitch 2.54mm length 9.5mm diameter 4mm Fastron SMCC +0 +2 +2 +Inductor_THT +L_Axial_L9.5mm_D4.0mm_P5.08mm_Vertical_Fastron_SMCC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 9.5mm diameter 4mm Fastron SMCC +0 +2 +2 +Inductor_THT +L_Axial_L9.5mm_D4.0mm_P12.70mm_Horizontal_Fastron_SMCC +Inductor, Axial series, Axial, Horizontal, pin pitch=12.7mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf +Inductor Axial series Axial Horizontal pin pitch 12.7mm length 9.5mm diameter 4mm Fastron SMCC +0 +2 +2 +Inductor_THT +L_Axial_L9.5mm_D4.0mm_P15.24mm_Horizontal_Fastron_SMCC +Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=9.5*4mm^2, Fastron, SMCC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_SMCC_NEU.pdf, http://cdn-reichelt.de/documents/datenblatt/B400/LEADEDINDUCTORS.pdf +Inductor Axial series Axial Horizontal pin pitch 15.24mm length 9.5mm diameter 4mm Fastron SMCC +0 +2 +2 +Inductor_THT +L_Axial_L11.0mm_D4.5mm_P5.08mm_Vertical_Fastron_MECC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 11mm diameter 4.5mm Fastron MECC +0 +2 +2 +Inductor_THT +L_Axial_L11.0mm_D4.5mm_P7.62mm_Vertical_Fastron_MECC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 11mm diameter 4.5mm Fastron MECC +0 +2 +2 +Inductor_THT +L_Axial_L11.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_MECC +Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=11*4.5mm^2, Fastron, MECC, http://www.fastrongroup.com/image-show/21/MECC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 15.24mm length 11mm diameter 4.5mm Fastron MECC +0 +2 +2 +Inductor_THT +L_Axial_L12.0mm_D5.0mm_P5.08mm_Vertical_Fastron_MISC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 12mm diameter 5mm Fastron MISC +0 +2 +2 +Inductor_THT +L_Axial_L12.0mm_D5.0mm_P7.62mm_Vertical_Fastron_MISC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 12mm diameter 5mm Fastron MISC +0 +2 +2 +Inductor_THT +L_Axial_L12.0mm_D5.0mm_P15.24mm_Horizontal_Fastron_MISC +Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=12*5mm^2, Fastron, MISC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MISC.pdf +Inductor Axial series Axial Horizontal pin pitch 15.24mm length 12mm diameter 5mm Fastron MISC +0 +2 +2 +Inductor_THT +L_Axial_L12.8mm_D5.8mm_P5.08mm_Vertical_Fastron_HBCC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 12.8mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L12.8mm_D5.8mm_P7.62mm_Vertical_Fastron_HBCC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 12.8mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L12.8mm_D5.8mm_P20.32mm_Horizontal_Fastron_HBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 20.32mm length 12.8mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L12.8mm_D5.8mm_P25.40mm_Horizontal_Fastron_HBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=12.8*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 25.4mm length 12.8mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L13.0mm_D4.5mm_P5.08mm_Vertical_Fastron_HCCC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 13mm diameter 4.5mm Fastron HCCC +0 +2 +2 +Inductor_THT +L_Axial_L13.0mm_D4.5mm_P7.62mm_Vertical_Fastron_HCCC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 13mm diameter 4.5mm Fastron HCCC +0 +2 +2 +Inductor_THT +L_Axial_L13.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_HCCC +Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=13*4.5mm^2, Fastron, HCCC, http://www.fastrongroup.com/image-show/19/HCCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 15.24mm length 13mm diameter 4.5mm Fastron HCCC +0 +2 +2 +Inductor_THT +L_Axial_L14.0mm_D4.5mm_P5.08mm_Vertical_Fastron_LACC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 14mm diameter 4.5mm Fastron LACC +0 +2 +2 +Inductor_THT +L_Axial_L14.0mm_D4.5mm_P7.62mm_Vertical_Fastron_LACC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 14mm diameter 4.5mm Fastron LACC +0 +2 +2 +Inductor_THT +L_Axial_L14.0mm_D4.5mm_P15.24mm_Horizontal_Fastron_LACC +Inductor, Axial series, Axial, Horizontal, pin pitch=15.24mm, , length*diameter=14*4.5mm^2, Fastron, LACC, http://www.fastrongroup.com/image-show/20/LACC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 15.24mm length 14mm diameter 4.5mm Fastron LACC +0 +2 +2 +Inductor_THT +L_Axial_L14.5mm_D5.8mm_P5.08mm_Vertical_Fastron_HBCC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 14.5mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L14.5mm_D5.8mm_P7.62mm_Vertical_Fastron_HBCC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 14.5mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L14.5mm_D5.8mm_P20.32mm_Horizontal_Fastron_HBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 20.32mm length 14.5mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L14.5mm_D5.8mm_P25.40mm_Horizontal_Fastron_HBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=14.5*5.8mm^2, Fastron, HBCC, http://www.fastrongroup.com/image-show/18/HBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 25.4mm length 14.5mm diameter 5.8mm Fastron HBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D6.3mm_P5.08mm_Vertical_Fastron_VHBCC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 16mm diameter 6.3mm Fastron VHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D6.3mm_P7.62mm_Vertical_Fastron_VHBCC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 16mm diameter 6.3mm Fastron VHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D6.3mm_P20.32mm_Horizontal_Fastron_VHBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 20.32mm length 16mm diameter 6.3mm Fastron VHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D6.3mm_P25.40mm_Horizontal_Fastron_VHBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=16*6.3mm^2, Fastron, VHBCC, http://www.fastrongroup.com/image-show/25/VHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 25.4mm length 16mm diameter 6.3mm Fastron VHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D7.5mm_P5.08mm_Vertical_Fastron_XHBCC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 5.08mm length 16mm diameter 7.5mm Fastron XHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D7.5mm_P7.62mm_Vertical_Fastron_XHBCC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Vertical pin pitch 7.62mm length 16mm diameter 7.5mm Fastron XHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D7.5mm_P20.32mm_Horizontal_Fastron_XHBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 20.32mm length 16mm diameter 7.5mm Fastron XHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D7.5mm_P25.40mm_Horizontal_Fastron_XHBCC +Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=16*7.5mm^2, Fastron, XHBCC, http://www.fastrongroup.com/image-show/26/XHBCC.pdf?type=Complete-DataSheet&productType=series +Inductor Axial series Axial Horizontal pin pitch 25.4mm length 16mm diameter 7.5mm Fastron XHBCC +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D9.5mm_P5.08mm_Vertical_Vishay_IM-10-37 +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=16*9.5mm^2, Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 16mm diameter 9.5mm Vishay IM-10-37 +0 +2 +2 +Inductor_THT +L_Axial_L16.0mm_D9.5mm_P20.32mm_Horizontal_Vishay_IM-10-37 +Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=16*9.5mm^2, Vishay, IM-10-37, http://www.vishay.com/docs/34030/im10.pdf +Inductor Axial series Axial Horizontal pin pitch 20.32mm length 16mm diameter 9.5mm Vishay IM-10-37 +0 +2 +2 +Inductor_THT +L_Axial_L17.5mm_D12.0mm_P7.62mm_Vertical_Vishay_IM-10-46 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=17.5*12mm^2, Vishay, IM-10-46, http://www.vishay.com/docs/34030/im10.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 17.5mm diameter 12mm Vishay IM-10-46 +0 +2 +2 +Inductor_THT +L_Axial_L17.5mm_D12.0mm_P20.32mm_Horizontal_Vishay_IM-10-46 +Inductor, Axial series, Axial, Horizontal, pin pitch=20.32mm, , length*diameter=17.5*12mm^2, Vishay, IM-10-46, http://www.vishay.com/docs/34030/im10.pdf +Inductor Axial series Axial Horizontal pin pitch 20.32mm length 17.5mm diameter 12mm Vishay IM-10-46 +0 +2 +2 +Inductor_THT +L_Axial_L20.0mm_D8.0mm_P5.08mm_Vertical +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=20*8mm^2 +Inductor Axial series Axial Vertical pin pitch 5.08mm length 20mm diameter 8mm +0 +2 +2 +Inductor_THT +L_Axial_L20.0mm_D8.0mm_P7.62mm_Vertical +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20*8mm^2 +Inductor Axial series Axial Vertical pin pitch 7.62mm length 20mm diameter 8mm +0 +2 +2 +Inductor_THT +L_Axial_L20.0mm_D8.0mm_P25.40mm_Horizontal +Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=20*8mm^2 +Inductor Axial series Axial Horizontal pin pitch 25.4mm length 20mm diameter 8mm +0 +2 +2 +Inductor_THT +L_Axial_L20.3mm_D12.1mm_P7.62mm_Vertical_Vishay_IHA-101 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20.32*12.07mm^2, Vishay, IHA-101, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 20.32mm diameter 12.07mm Vishay IHA-101 +0 +2 +2 +Inductor_THT +L_Axial_L20.3mm_D12.1mm_P28.50mm_Horizontal_Vishay_IHA-101 +Inductor, Axial series, Axial, Horizontal, pin pitch=28.5mm, , length*diameter=20.32*12.07mm^2, Vishay, IHA-101, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Horizontal pin pitch 28.5mm length 20.32mm diameter 12.07mm Vishay IHA-101 +0 +2 +2 +Inductor_THT +L_Axial_L20.3mm_D12.7mm_P7.62mm_Vertical_Vishay_IHA-201 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=20.32*12.7mm^2, Vishay, IHA-201, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 20.32mm diameter 12.7mm Vishay IHA-201 +0 +2 +2 +Inductor_THT +L_Axial_L20.3mm_D12.7mm_P25.40mm_Horizontal_Vishay_IHA-201 +Inductor, Axial series, Axial, Horizontal, pin pitch=25.4mm, , length*diameter=20.32*12.7mm^2, Vishay, IHA-201, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Horizontal pin pitch 25.4mm length 20.32mm diameter 12.7mm Vishay IHA-201 +0 +2 +2 +Inductor_THT +L_Axial_L23.4mm_D12.7mm_P7.62mm_Vertical_Vishay_IHA-203 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=23.37*12.7mm^2, Vishay, IHA-203, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 23.37mm diameter 12.7mm Vishay IHA-203 +0 +2 +2 +Inductor_THT +L_Axial_L23.4mm_D12.7mm_P32.00mm_Horizontal_Vishay_IHA-203 +Inductor, Axial series, Axial, Horizontal, pin pitch=32mm, , length*diameter=23.37*12.7mm^2, Vishay, IHA-203, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Horizontal pin pitch 32mm length 23.37mm diameter 12.7mm Vishay IHA-203 +0 +2 +2 +Inductor_THT +L_Axial_L24.0mm_D7.1mm_P5.08mm_Vertical_Vishay_IM-10-28 +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=24*7.1mm^2, Vishay, IM-10-28, http://www.vishay.com/docs/34035/im10.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 24mm diameter 7.1mm Vishay IM-10-28 +0 +2 +2 +Inductor_THT +L_Axial_L24.0mm_D7.1mm_P30.48mm_Horizontal_Vishay_IM-10-28 +Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=24*7.1mm^2, Vishay, IM-10-28, http://www.vishay.com/docs/34035/im10.pdf +Inductor Axial series Axial Horizontal pin pitch 30.48mm length 24mm diameter 7.1mm Vishay IM-10-28 +0 +2 +2 +Inductor_THT +L_Axial_L24.0mm_D7.5mm_P5.08mm_Vertical_Fastron_MESC +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 24mm diameter 7.5mm Fastron MESC +0 +2 +2 +Inductor_THT +L_Axial_L24.0mm_D7.5mm_P7.62mm_Vertical_Fastron_MESC +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 24mm diameter 7.5mm Fastron MESC +0 +2 +2 +Inductor_THT +L_Axial_L24.0mm_D7.5mm_P27.94mm_Horizontal_Fastron_MESC +Inductor, Axial series, Axial, Horizontal, pin pitch=27.94mm, , length*diameter=24*7.5mm^2, Fastron, MESC, http://cdn-reichelt.de/documents/datenblatt/B400/DS_MESC.pdf +Inductor Axial series Axial Horizontal pin pitch 27.94mm length 24mm diameter 7.5mm Fastron MESC +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D9.0mm_P5.08mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 26mm diameter 9mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D9.0mm_P7.62mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 26mm diameter 9mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D9.0mm_P30.48mm_Horizontal_Fastron_77A +Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*9mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Horizontal pin pitch 30.48mm length 26mm diameter 9mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D10.0mm_P5.08mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 26mm diameter 10mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D10.0mm_P7.62mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 26mm diameter 10mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D10.0mm_P30.48mm_Horizontal_Fastron_77A +Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*10mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Horizontal pin pitch 30.48mm length 26mm diameter 10mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D11.0mm_P5.08mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 26mm diameter 11mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D11.0mm_P7.62mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 26mm diameter 11mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.0mm_D11.0mm_P30.48mm_Horizontal_Fastron_77A +Inductor, Axial series, Axial, Horizontal, pin pitch=30.48mm, , length*diameter=26*11mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Horizontal pin pitch 30.48mm length 26mm diameter 11mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L26.7mm_D12.1mm_P7.62mm_Vertical_Vishay_IHA-103 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26.67*12.07mm^2, Vishay, IHA-103, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 26.67mm diameter 12.07mm Vishay IHA-103 +0 +2 +2 +Inductor_THT +L_Axial_L26.7mm_D12.1mm_P35.00mm_Horizontal_Vishay_IHA-103 +Inductor, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=26.67*12.07mm^2, Vishay, IHA-103, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Horizontal pin pitch 35mm length 26.67mm diameter 12.07mm Vishay IHA-103 +0 +2 +2 +Inductor_THT +L_Axial_L26.7mm_D14.0mm_P7.62mm_Vertical_Vishay_IHA-104 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=26.67*13.97mm^2, Vishay, IHA-104, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 26.67mm diameter 13.97mm Vishay IHA-104 +0 +2 +2 +Inductor_THT +L_Axial_L26.7mm_D14.0mm_P35.00mm_Horizontal_Vishay_IHA-104 +Inductor, Axial series, Axial, Horizontal, pin pitch=35mm, , length*diameter=26.67*13.97mm^2, Vishay, IHA-104, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Horizontal pin pitch 35mm length 26.67mm diameter 13.97mm Vishay IHA-104 +0 +2 +2 +Inductor_THT +L_Axial_L29.9mm_D14.0mm_P7.62mm_Vertical_Vishay_IHA-105 +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=29.85*13.97mm^2, Vishay, IHA-105, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 29.85mm diameter 13.97mm Vishay IHA-105 +0 +2 +2 +Inductor_THT +L_Axial_L29.9mm_D14.0mm_P38.00mm_Horizontal_Vishay_IHA-105 +Inductor, Axial series, Axial, Horizontal, pin pitch=38mm, , length*diameter=29.85*13.97mm^2, Vishay, IHA-105, http://www.vishay.com/docs/34014/iha.pdf +Inductor Axial series Axial Horizontal pin pitch 38mm length 29.85mm diameter 13.97mm Vishay IHA-105 +0 +2 +2 +Inductor_THT +L_Axial_L30.0mm_D8.0mm_P5.08mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=5.08mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 5.08mm length 30mm diameter 8mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L30.0mm_D8.0mm_P7.62mm_Vertical_Fastron_77A +Inductor, Axial series, Axial, Vertical, pin pitch=7.62mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Vertical pin pitch 7.62mm length 30mm diameter 8mm Fastron 77A +0 +2 +2 +Inductor_THT +L_Axial_L30.0mm_D8.0mm_P35.56mm_Horizontal_Fastron_77A +Inductor, Axial series, Axial, Horizontal, pin pitch=35.56mm, , length*diameter=30*8mm^2, Fastron, 77A, http://cdn-reichelt.de/documents/datenblatt/B400/DS_77A.pdf +Inductor Axial series Axial Horizontal pin pitch 35.56mm length 30mm diameter 8mm Fastron 77A +0 +2 +2 +Inductor_THT +L_CommonMode_Toroid_Vertical_L19.3mm_W10.8mm_Px6.35mm_Py15.24mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=6.35*15.24mm^2, , length*width=19.304*10.795mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 6.35*15.24mm^2 length 19.304mm width 10.795mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L21.0mm_W10.0mm_Px5.08mm_Py12.70mm_muRATA_5100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=5.08*12.70mm^2, , length*width=21*10mm^2, muRATA, 5100, http://www.murata-ps.com/data/magnetics/kmp_5100.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 5.08*12.70mm^2 length 21mm width 10mm muRATA 5100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L24.0mm_W16.3mm_Px10.16mm_Py20.32mm_muRATA_5200 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=10.16*20.32mm^2, , length*width=24*16.3mm^2, muRATA, 5200, http://www.murata-ps.com/data/magnetics/kmp_5200.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 10.16*20.32mm^2 length 24mm width 16.3mm muRATA 5200 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L30.5mm_W15.2mm_Px10.16mm_Py20.32mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=10.16*20.32mm^2, , length*width=30.479999999999997*15.239999999999998mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 10.16*20.32mm^2 length 30.479999999999997mm width 15.239999999999998mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L34.3mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=34.29*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 34.29mm width 20.32mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L36.8mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=36.83*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 36.83mm width 20.32mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L38.1mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=38.099999999999994*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 38.099999999999994mm width 20.32mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L39.4mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=39.37*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 39.37mm width 20.32mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L41.9mm_W20.3mm_Px15.24mm_Py22.86mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=15.24*22.86mm^2, , length*width=41.91*20.32mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 15.24*22.86mm^2 length 41.91mm width 20.32mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Toroid_Vertical_L43.2mm_W22.9mm_Px17.78mm_Py30.48mm_Bourns_8100 +L_CommonMode_Toroid, Vertical series, Radial, pin pitch=17.78*30.48mm^2, , length*width=43.18*22.86mm^2, Bourns, 8100, http://datasheet.octopart.com/8120-RC-Bourns-datasheet-10228452.pdf +L_CommonMode_Toroid Vertical series Radial pin pitch 17.78*30.48mm^2 length 43.18mm width 22.86mm Bourns 8100 +0 +4 +4 +Inductor_THT +L_CommonMode_Wuerth_WE-CMB-L +Wuerth, WE-CMB, Bauform L, +CommonModeChoke Gleichtaktdrossel +0 +4 +4 +Inductor_THT +L_CommonMode_Wuerth_WE-CMB-M +Wuerth, WE-CMB, Bauform M, +CommonModeChoke Gleichtaktdrossel +0 +4 +4 +Inductor_THT +L_CommonMode_Wuerth_WE-CMB-S +Wuerth, WE-CMB, Bauform S, +CommonModeChoke Gleichtaktdrossel +0 +4 +4 +Inductor_THT +L_CommonMode_Wuerth_WE-CMB-XL +Wuerth, WE-CMB, Bauform XL, +CommonModeChoke Gleichtaktdrossel +0 +4 +4 +Inductor_THT +L_CommonMode_Wuerth_WE-CMB-XS +Wuerth, WE-CMB, Bauform XS, +CommonModeChoke Gleichtaktdrossel +0 +4 +4 +Inductor_THT +L_CommonMode_Wuerth_WE-CMB-XXL +Wuerth, WE-CMB, Bauform XXL, +CommonModeChoke Gleichtaktdrossel +0 +4 +4 +Inductor_THT +L_Mount_Lodestone_VTM120 +Lodestone Pacific, 30.48mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf +vertical inductor toroid mount +0 +4 +4 +Inductor_THT +L_Mount_Lodestone_VTM160 +Lodestone Pacific, 40.64mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf +vertical inductor toroid mount +0 +4 +4 +Inductor_THT +L_Mount_Lodestone_VTM254 +Lodestone Pacific, 64.51mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf +vertical inductor toroid mount +0 +4 +4 +Inductor_THT +L_Mount_Lodestone_VTM280 +Lodestone Pacific, 71.12mm diameter vertical toroid mount, 16AWG/1.27mm holes, http://www.lodestonepacific.com/CatKpdf/VTM_Series.pdf +vertical inductor toroid mount +0 +4 +4 +Inductor_THT +L_Mount_Lodestone_VTM950-6 +Lodestone Pacific, vertical toroid mount, 11x19mm, 6 pins, http://www.lodestonepacific.com/CatKpdf/VTM950-6.pdf +vertical inductor toroid mount +0 +6 +6 +Inductor_THT +L_Radial_D6.0mm_P4.00mm +Inductor, Radial series, Radial, pin pitch=4.00mm, , diameter=6.0mm, http://www.abracon.com/Magnetics/radial/AIUR-07.pdf +Inductor Radial series Radial pin pitch 4.00mm diameter 6.0mm +0 +2 +2 +Inductor_THT +L_Radial_D7.0mm_P3.00mm +Inductor, Radial series, Radial, pin pitch=3.00mm, , diameter=7mm, http://www.abracon.com/Magnetics/radial/AIUR-16.pdf +Inductor Radial series Radial pin pitch 3.00mm diameter 7mm +0 +2 +2 +Inductor_THT +L_Radial_D7.2mm_P3.00mm_MuRATA_1700 +Inductor, Radial series, Radial, pin pitch=3.00mm, , diameter=7.2mm, MuRATA, 1700, http://www.murata-ps.com/data/magnetics/kmp_1700.pdf +Inductor Radial series Radial pin pitch 3.00mm diameter 7.2mm MuRATA 1700 +0 +2 +2 +Inductor_THT +L_Radial_D7.5mm_P3.50mm_Fastron_07P +Inductor, Radial series, Radial, pin pitch=3.50mm, , diameter=7.5mm, Fastron, 07P, http://www.fastrongroup.com/image-show/39/07P.pdf?type=Complete-DataSheet&productType=series +Inductor Radial series Radial pin pitch 3.50mm diameter 7.5mm Fastron 07P +0 +2 +2 +Inductor_THT +L_Radial_D7.5mm_P5.00mm_Fastron_07P +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=7.5mm, Fastron, 07P, http://www.fastrongroup.com/image-show/39/07P.pdf?type=Complete-DataSheet&productType=series +Inductor Radial series Radial pin pitch 5.00mm diameter 7.5mm Fastron 07P +0 +2 +2 +Inductor_THT +L_Radial_D7.8mm_P5.00mm_Fastron_07HCP +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=7.8mm, Fastron, 07HCP, http://www.abracon.com/Magnetics/radial/AISR875.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 7.8mm Fastron 07HCP +0 +2 +2 +Inductor_THT +L_Radial_D8.7mm_P5.00mm_Fastron_07HCP +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=8.7mm, Fastron, 07HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_07HCP.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 8.7mm Fastron 07HCP +0 +2 +2 +Inductor_THT +L_Radial_D9.5mm_P5.00mm_Fastron_07HVP +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=9.5mm, Fastron, 07HVP, http://www.fastrongroup.com/image-show/107/07HVP%2007HVP_T.pdf?type=Complete-DataSheet&productType=series +Inductor Radial series Radial pin pitch 5.00mm diameter 9.5mm Fastron 07HVP +0 +2 +2 +Inductor_THT +L_Radial_D10.0mm_P5.00mm_Fastron_07M +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Fastron, 07M, http://www.fastrongroup.com/image-show/37/07M.pdf?type=Complete-DataSheet&productType=series +Inductor Radial series Radial pin pitch 5.00mm diameter 10mm Fastron 07M +0 +2 +2 +Inductor_THT +L_Radial_D10.0mm_P5.00mm_Fastron_07P +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Fastron, 07P, http://www.fastrongroup.com/image-show/37/07M.pdf?type=Complete-DataSheet&productType=series +Inductor Radial series Radial pin pitch 5.00mm diameter 10mm Fastron 07P +0 +2 +2 +Inductor_THT +L_Radial_D10.0mm_P5.00mm_Neosid_SD12_style3 +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.0mm, Neosid, SD12, style3, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 10.0mm Neosid SD12 style3 +0 +2 +2 +Inductor_THT +L_Radial_D10.0mm_P5.00mm_Neosid_SD12k_style3 +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.0mm, Neosid, SD12k, style3, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 10.0mm Neosid SD12k style3 +0 +2 +2 +Inductor_THT +L_Radial_D10.5mm_P4.00x5.00mm_Murata_1200RS +Inductor, Radial, Pitch=4.00x5.00mm, Diameter=10.5mm, Murata 1200RS, http://www.murata-ps.com/data/magnetics/kmp_1200rs.pdf +Inductor Radial Murata 1200RS +0 +4 +2 +Inductor_THT +L_Radial_D10.5mm_P5.00mm_Abacron_AISR-01 +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=10.5mm, Abacron, AISR-01, http://www.abracon.com/Magnetics/radial/AISR-01.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 10.5mm Abacron AISR-01 +0 +2 +2 +Inductor_THT +L_Radial_D12.0mm_P5.00mm_Fastron_11P +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Fastron, 11P, http://cdn-reichelt.de/documents/datenblatt/B400/DS_11P.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 12.0mm Fastron 11P +0 +2 +2 +Inductor_THT +L_Radial_D12.0mm_P5.00mm_Neosid_SD12_style2 +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Neosid, SD12, style2, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 12.0mm Neosid SD12 style2 +0 +2 +2 +Inductor_THT +L_Radial_D12.0mm_P5.00mm_Neosid_SD12k_style2 +Inductor, Radial series, Radial, pin pitch=5.00mm, , diameter=12.0mm, Neosid, SD12k, style2, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf +Inductor Radial series Radial pin pitch 5.00mm diameter 12.0mm Neosid SD12k style2 +0 +2 +2 +Inductor_THT +L_Radial_D12.0mm_P6.00mm_MuRATA_1900R +Inductor, Radial series, Radial, pin pitch=6.00mm, , diameter=12.0mm, MuRATA, 1900R, http://www.murata-ps.com/data/magnetics/kmp_1900r.pdf +Inductor Radial series Radial pin pitch 6.00mm diameter 12.0mm MuRATA 1900R +0 +2 +2 +Inductor_THT +L_Radial_D12.0mm_P10.00mm_Neosid_SD12_style1 +Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=12.0mm, Neosid, SD12, style1, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12.pdf +Inductor Radial series Radial pin pitch 10.00mm diameter 12.0mm Neosid SD12 style1 +0 +2 +2 +Inductor_THT +L_Radial_D12.0mm_P10.00mm_Neosid_SD12k_style1 +Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=12.0mm, Neosid, SD12k, style1, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd12k.pdf +Inductor Radial series Radial pin pitch 10.00mm diameter 12.0mm Neosid SD12k style1 +0 +2 +2 +Inductor_THT +L_Radial_D12.5mm_P7.00mm_Fastron_09HCP +Inductor, Radial series, Radial, pin pitch=7.00mm, , diameter=12.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf +Inductor Radial series Radial pin pitch 7.00mm diameter 12.5mm Fastron 09HCP +0 +2 +2 +Inductor_THT +L_Radial_D12.5mm_P9.00mm_Fastron_09HCP +Inductor, Radial series, Radial, pin pitch=9.00mm, , diameter=12.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf +Inductor Radial series Radial pin pitch 9.00mm diameter 12.5mm Fastron 09HCP +0 +2 +2 +Inductor_THT +L_Radial_D13.5mm_P7.00mm_Fastron_09HCP +Inductor, Radial series, Radial, pin pitch=7.00mm, , diameter=13.5mm, Fastron, 09HCP, http://cdn-reichelt.de/documents/datenblatt/B400/DS_09HCP.pdf +Inductor Radial series Radial pin pitch 7.00mm diameter 13.5mm Fastron 09HCP +0 +2 +2 +Inductor_THT +L_Radial_D14.2mm_P10.00mm_Neosid_SD14 +Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=14.2mm, Neosid, SD14, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd14.pdf +Inductor Radial series Radial pin pitch 10.00mm diameter 14.2mm Neosid SD14 +0 +2 +2 +Inductor_THT +L_Radial_D16.8mm_P11.43mm_Vishay_IHB-1 +Inductor, Radial series, Radial, pin pitch=11.43mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 11.43mm diameter 16.8mm Vishay IHB-1 +0 +2 +2 +Inductor_THT +L_Radial_D16.8mm_P12.07mm_Vishay_IHB-1 +Inductor, Radial series, Radial, pin pitch=12.07mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 12.07mm diameter 16.8mm Vishay IHB-1 +0 +2 +2 +Inductor_THT +L_Radial_D16.8mm_P12.70mm_Vishay_IHB-1 +Inductor, Radial series, Radial, pin pitch=12.70mm, , diameter=16.8mm, Vishay, IHB-1, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 12.70mm diameter 16.8mm Vishay IHB-1 +0 +2 +2 +Inductor_THT +L_Radial_D18.0mm_P10.00mm +Inductor, Radial series, Radial, pin pitch=10.00mm, , diameter=18mm, http://www.abracon.com/Magnetics/radial/AIUR-15.pdf +Inductor Radial series Radial pin pitch 10.00mm diameter 18mm +0 +2 +2 +Inductor_THT +L_Radial_D21.0mm_P14.61mm_Vishay_IHB-2 +Inductor, Radial series, Radial, pin pitch=14.61mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 14.61mm diameter 21mm Vishay IHB-2 +0 +2 +2 +Inductor_THT +L_Radial_D21.0mm_P15.00mm_Vishay_IHB-2 +Inductor, Radial series, Radial, pin pitch=15.00mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 15.00mm diameter 21mm Vishay IHB-2 +0 +2 +2 +Inductor_THT +L_Radial_D21.0mm_P15.24mm_Vishay_IHB-2 +Inductor, Radial series, Radial, pin pitch=15.24mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 15.24mm diameter 21mm Vishay IHB-2 +0 +2 +2 +Inductor_THT +L_Radial_D21.0mm_P15.75mm_Vishay_IHB-2 +Inductor, Radial series, Radial, pin pitch=15.75mm, , diameter=21mm, Vishay, IHB-2, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 15.75mm diameter 21mm Vishay IHB-2 +0 +2 +2 +Inductor_THT +L_Radial_D21.0mm_P19.00mm +Inductor, Radial series, Radial, pin pitch=19.00mm, , diameter=21mm, http://www.abracon.com/Magnetics/radial/AIRD02.pdf +Inductor Radial series Radial pin pitch 19.00mm diameter 21mm +0 +2 +2 +Inductor_THT +L_Radial_D24.0mm_P24.00mm +Inductor, Radial series, Radial, pin pitch=24.00mm, , diameter=24mm +Inductor Radial series Radial pin pitch 24.00mm diameter 24mm +0 +2 +2 +Inductor_THT +L_Radial_D24.4mm_P22.90mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=22.90mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 22.90mm diameter 24.4mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D24.4mm_P23.10mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=23.10mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 23.10mm diameter 24.4mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D24.4mm_P23.40mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=23.40mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 23.40mm diameter 24.4mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D24.4mm_P23.70mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=23.70mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 23.70mm diameter 24.4mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D24.4mm_P23.90mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=23.90mm, , diameter=24.4mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 23.90mm diameter 24.4mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D27.9mm_P18.29mm_Vishay_IHB-3 +Inductor, Radial series, Radial, pin pitch=18.29mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 18.29mm diameter 27.9mm Vishay IHB-3 +0 +2 +2 +Inductor_THT +L_Radial_D27.9mm_P19.05mm_Vishay_IHB-3 +Inductor, Radial series, Radial, pin pitch=19.05mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 19.05mm diameter 27.9mm Vishay IHB-3 +0 +2 +2 +Inductor_THT +L_Radial_D27.9mm_P20.07mm_Vishay_IHB-3 +Inductor, Radial series, Radial, pin pitch=20.07mm, , diameter=27.9mm, Vishay, IHB-3, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 20.07mm diameter 27.9mm Vishay IHB-3 +0 +2 +2 +Inductor_THT +L_Radial_D28.0mm_P29.20mm +Inductor, Radial series, Radial, pin pitch=29.20mm, , diameter=28mm +Inductor Radial series Radial pin pitch 29.20mm diameter 28mm +0 +2 +2 +Inductor_THT +L_Radial_D29.8mm_P28.30mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=28.30mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 28.30mm diameter 29.8mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D29.8mm_P28.50mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=28.50mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 28.50mm diameter 29.8mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D29.8mm_P28.80mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=28.80mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 28.80mm diameter 29.8mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D29.8mm_P29.00mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=29.00mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 29.00mm diameter 29.8mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D29.8mm_P29.30mm_muRATA_1400series +Inductor, Radial series, Radial, pin pitch=29.30mm, , diameter=29.8mm, muRATA, 1400series, http://www.murata-ps.com/data/magnetics/kmp_1400.pdf +Inductor Radial series Radial pin pitch 29.30mm diameter 29.8mm muRATA 1400series +0 +2 +2 +Inductor_THT +L_Radial_D40.6mm_P26.16mm_Vishay_IHB-5 +Inductor, Radial series, Radial, pin pitch=26.16mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 26.16mm diameter 40.64mm Vishay IHB-5 +0 +2 +2 +Inductor_THT +L_Radial_D40.6mm_P27.18mm_Vishay_IHB-4 +Inductor, Radial series, Radial, pin pitch=27.18mm, , diameter=40.64mm, Vishay, IHB-4, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 27.18mm diameter 40.64mm Vishay IHB-4 +0 +2 +2 +Inductor_THT +L_Radial_D40.6mm_P27.94mm_Vishay_IHB-4 +Inductor, Radial series, Radial, pin pitch=27.94mm, , diameter=40.64mm, Vishay, IHB-4, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 27.94mm diameter 40.64mm Vishay IHB-4 +0 +2 +2 +Inductor_THT +L_Radial_D40.6mm_P27.94mm_Vishay_IHB-5 +Inductor, Radial series, Radial, pin pitch=27.94mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 27.94mm diameter 40.64mm Vishay IHB-5 +0 +2 +2 +Inductor_THT +L_Radial_D40.6mm_P28.70mm_Vishay_IHB-5 +Inductor, Radial series, Radial, pin pitch=28.70mm, , diameter=40.64mm, Vishay, IHB-5, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 28.70mm diameter 40.64mm Vishay IHB-5 +0 +2 +2 +Inductor_THT +L_Radial_D50.8mm_P33.27mm_Vishay_IHB-6 +Inductor, Radial series, Radial, pin pitch=33.27mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 33.27mm diameter 50.8mm Vishay IHB-6 +0 +2 +2 +Inductor_THT +L_Radial_D50.8mm_P34.29mm_Vishay_IHB-6 +Inductor, Radial series, Radial, pin pitch=34.29mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 34.29mm diameter 50.8mm Vishay IHB-6 +0 +2 +2 +Inductor_THT +L_Radial_D50.8mm_P35.81mm_Vishay_IHB-6 +Inductor, Radial series, Radial, pin pitch=35.81mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 35.81mm diameter 50.8mm Vishay IHB-6 +0 +2 +2 +Inductor_THT +L_Radial_D50.8mm_P36.32mm_Vishay_IHB-6 +Inductor, Radial series, Radial, pin pitch=36.32mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 36.32mm diameter 50.8mm Vishay IHB-6 +0 +2 +2 +Inductor_THT +L_Radial_D50.8mm_P38.86mm_Vishay_IHB-6 +Inductor, Radial series, Radial, pin pitch=38.86mm, , diameter=50.8mm, Vishay, IHB-6, http://www.vishay.com/docs/34015/ihb.pdf +Inductor Radial series Radial pin pitch 38.86mm diameter 50.8mm Vishay IHB-6 +0 +2 +2 +Inductor_THT +L_Radial_L7.5mm_W4.6mm_P5.00mm_Neosid_SD75 +Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=7.5*4.6mm^2, Neosid, SD75, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd75.pdf +Inductor Radial series Radial pin pitch 5.00mm length 7.5mm width 4.6mm Neosid SD75 +0 +2 +2 +Inductor_THT +L_Radial_L8.0mm_W8.0mm_P5.00mm_Neosid_NE-CPB-07E +Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=8*8mm^2, Neosid, NE-CPB-07E, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB07E.pdf +Inductor Radial series Radial pin pitch 5.00mm length 8mm width 8mm Neosid NE-CPB-07E +0 +2 +2 +Inductor_THT +L_Radial_L8.0mm_W8.0mm_P5.00mm_Neosid_SD8 +Inductor, Radial series, Radial, pin pitch=5.00mm, , length*width=8*8mm^2, Neosid, SD8, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_Sd8.pdf +Inductor Radial series Radial pin pitch 5.00mm length 8mm width 8mm Neosid SD8 +0 +2 +2 +Inductor_THT +L_Radial_L9.1mm_W9.1mm_Px6.35mm_Py6.35mm_Pulse_LP-25 +Inductor, Radial series, Radial, pin pitch=6.35*6.35mm^2, , length*width=9.14*9.14mm^2, Pulse, LP-25, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf +Inductor Radial series Radial pin pitch 6.35*6.35mm^2 length 9.14mm width 9.14mm Pulse LP-25 +0 +2 +2 +Inductor_THT +L_Radial_L10.2mm_W10.2mm_Px7.62mm_Py7.62mm_Pulse_LP-30 +Inductor, Radial series, Radial, pin pitch=7.62*7.62mm^2, , length*width=10.16*10.16mm^2, Pulse, LP-30, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf +Inductor Radial series Radial pin pitch 7.62*7.62mm^2 length 10.16mm width 10.16mm Pulse LP-30 +0 +2 +2 +Inductor_THT +L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.3mm +Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.3mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf +Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.3mm +0 +2 +2 +Inductor_THT +L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.5mm +Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.5mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf +Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.5mm +0 +2 +2 +Inductor_THT +L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.7mm +Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.7mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf +Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.7mm +0 +2 +2 +Inductor_THT +L_Radial_L11.5mm_W11.5mm_Px6.00mm_Py6.00mm_Neosid_NE-CPB-11EN_Drill1.8mm +Inductor, Radial series, Radial, pin pitch=6.00*6.00mm^2, , length*width=11.5*11.5mm^2, Neosid, NE-CPB-11EN, Drill1.8mm, http://www.neosid.de/produktblaetter/neosid_Festinduktivitaet_NE_CPB11EN.pdf +Inductor Radial series Radial pin pitch 6.00*6.00mm^2 length 11.5mm width 11.5mm Neosid NE-CPB-11EN Drill1.8mm +0 +2 +2 +Inductor_THT +L_Radial_L12.6mm_W12.6mm_Px9.52mm_Py9.52mm_Pulse_LP-37 +Inductor, Radial series, Radial, pin pitch=9.52*9.52mm^2, , length*width=12.57*12.57mm^2, Pulse, LP-37, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf +Inductor Radial series Radial pin pitch 9.52*9.52mm^2 length 12.57mm width 12.57mm Pulse LP-37 +0 +2 +2 +Inductor_THT +L_Radial_L16.1mm_W16.1mm_Px7.62mm_Py12.70mm_Pulse_LP-44 +Inductor, Radial series, Radial, pin pitch=7.62*12.70mm^2, , length*width=16.13*16.13mm^2, Pulse, LP-44, http://datasheet.octopart.com/PE-54044NL-Pulse-datasheet-5313493.pdf +Inductor Radial series Radial pin pitch 7.62*12.70mm^2 length 16.13mm width 16.13mm Pulse LP-44 +0 +2 +2 +Inductor_THT +L_SELF1408 +Self Ferrite 14 - 08 +SELF +0 +7 +3 +Inductor_THT +L_SELF1418 +Self Ferrite 14 - 18 +SELF +0 +10 +4 +Inductor_THT +L_Toroid_Horizontal_D3.2mm_P6.40mm_Diameter3-5mm_Amidon-T12 +L_Toroid, Horizontal series, Radial, pin pitch=6.40mm, , diameter=3.175mm, Diameter3-5mm, Amidon-T12 +L_Toroid Horizontal series Radial pin pitch 6.40mm diameter 3.175mm Diameter3-5mm Amidon-T12 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D4.1mm_P8.00mm_Diameter4-5mm_Amidon-T16 +L_Toroid, Horizontal series, Radial, pin pitch=8.00mm, , diameter=4.064mm, Diameter4-5mm, Amidon-T16 +L_Toroid Horizontal series Radial pin pitch 8.00mm diameter 4.064mm Diameter4-5mm Amidon-T16 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D5.1mm_P9.00mm_Diameter6-5mm_Amidon-T20 +L_Toroid, Horizontal series, Radial, pin pitch=9.00mm, , diameter=5.08mm, Diameter6-5mm, Amidon-T20 +L_Toroid Horizontal series Radial pin pitch 9.00mm diameter 5.08mm Diameter6-5mm Amidon-T20 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D6.5mm_P10.00mm_Diameter7-5mm_Amidon-T25 +L_Toroid, Horizontal series, Radial, pin pitch=10.00mm, , diameter=6.476999999999999mm, Diameter7-5mm, Amidon-T25 +L_Toroid Horizontal series Radial pin pitch 10.00mm diameter 6.476999999999999mm Diameter7-5mm Amidon-T25 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D7.8mm_P13.00mm_Diameter9-5mm_Amidon-T30 +L_Toroid, Horizontal series, Radial, pin pitch=13.00mm, , diameter=7.7978mm, Diameter9-5mm, Amidon-T30 +L_Toroid Horizontal series Radial pin pitch 13.00mm diameter 7.7978mm Diameter9-5mm Amidon-T30 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D9.5mm_P15.00mm_Diameter10-5mm_Amidon-T37 +L_Toroid, Horizontal series, Radial, pin pitch=15.00mm, , diameter=9.524999999999999mm, Diameter10-5mm, Amidon-T37 +L_Toroid Horizontal series Radial pin pitch 15.00mm diameter 9.524999999999999mm Diameter10-5mm Amidon-T37 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D11.2mm_P17.00mm_Diameter12-5mm_Amidon-T44 +L_Toroid, Horizontal series, Radial, pin pitch=17.00mm, , diameter=11.176mm, Diameter12-5mm, Amidon-T44 +L_Toroid Horizontal series Radial pin pitch 17.00mm diameter 11.176mm Diameter12-5mm Amidon-T44 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D12.7mm_P20.00mm_Diameter14-5mm_Amidon-T50 +L_Toroid, Horizontal series, Radial, pin pitch=20.00mm, , diameter=12.7mm, Diameter14-5mm, Amidon-T50 +L_Toroid Horizontal series Radial pin pitch 20.00mm diameter 12.7mm Diameter14-5mm Amidon-T50 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D16.8mm_P14.70mm_Vishay_TJ3 +L_Toroid, Horizontal series, Radial, pin pitch=14.70mm, , diameter=16.8mm, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 14.70mm diameter 16.8mm Vishay TJ3 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D16.8mm_P14.70mm_Vishay_TJ3_BigPads +L_Toroid, Horizontal series, Radial, pin pitch=14.70mm, , diameter=16.8mm, Vishay, TJ3, BigPads, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 14.70mm diameter 16.8mm Vishay TJ3 BigPads +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D17.3mm_P15.24mm_Bourns_2000 +L_Toroid, Horizontal series, Radial, pin pitch=15.24mm, , diameter=17.3mm, Bourns, 2000, http://www.bourns.com/docs/Product-Datasheets/2000_series.pdf?sfvrsn=5 +L_Toroid Horizontal series Radial pin pitch 15.24mm diameter 17.3mm Bourns 2000 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D21.8mm_P19.10mm_Bourns_2100 +L_Toroid, Horizontal series, Radial, pin pitch=19.10mm, , diameter=21.8mm, Bourns, 2100, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 19.10mm diameter 21.8mm Bourns 2100 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D21.8mm_P19.60mm_Bourns_2100 +L_Toroid, Horizontal series, Radial, pin pitch=19.60mm, , diameter=21.8mm, Bourns, 2100, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 19.60mm diameter 21.8mm Bourns 2100 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D22.4mm_P19.80mm_Vishay_TJ4 +L_Toroid, Horizontal series, Radial, pin pitch=19.80mm, , diameter=22.4mm, Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 19.80mm diameter 22.4mm Vishay TJ4 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D24.1mm_P21.80mm_Bourns_2200 +L_Toroid, Horizontal series, Radial, pin pitch=21.80mm, , diameter=24.1mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 21.80mm diameter 24.1mm Bourns 2200 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D24.1mm_P23.10mm_Bourns_2200 +L_Toroid, Horizontal series, Radial, pin pitch=23.10mm, , diameter=24.1mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 23.10mm diameter 24.1mm Bourns 2200 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D25.4mm_P22.90mm_Vishay_TJ5 +L_Toroid, Horizontal series, Radial, pin pitch=22.90mm, , diameter=25.4mm, Vishay, TJ5, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 22.90mm diameter 25.4mm Vishay TJ5 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D25.4mm_P22.90mm_Vishay_TJ5_BigPads +L_Toroid, Horizontal series, Radial, pin pitch=22.90mm, , diameter=25.4mm, Vishay, TJ5, BigPads, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 22.90mm diameter 25.4mm Vishay TJ5 BigPads +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D26.0mm_P5.08mm +inductor 26mm diameter toroid +SELF INDUCTOR +0 +3 +2 +Inductor_THT +L_Toroid_Horizontal_D28.0mm_P25.10mm_Bourns_2200 +L_Toroid, Horizontal series, Radial, pin pitch=25.10mm, , diameter=28mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 25.10mm diameter 28mm Bourns 2200 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D28.0mm_P26.67mm_Bourns_2200 +L_Toroid, Horizontal series, Radial, pin pitch=26.67mm, , diameter=28mm, Bourns, 2200, http://www.bourns.com/docs/Product-Datasheets/2100_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 26.67mm diameter 28mm Bourns 2200 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D32.5mm_P28.90mm_Bourns_2300 +L_Toroid, Horizontal series, Radial, pin pitch=28.90mm, , diameter=32.5mm, Bourns, 2300, http://www.bourns.com/docs/Product-Datasheets/2300_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 28.90mm diameter 32.5mm Bourns 2300 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D32.5mm_P30.00mm_Bourns_2300 +L_Toroid, Horizontal series, Radial, pin pitch=30.00mm, , diameter=32.5mm, Bourns, 2300, http://www.bourns.com/docs/Product-Datasheets/2300_series.pdf?sfvrsn=3 +L_Toroid Horizontal series Radial pin pitch 30.00mm diameter 32.5mm Bourns 2300 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D35.1mm_P31.00mm_Vishay_TJ6 +L_Toroid, Horizontal series, Radial, pin pitch=31.00mm, , diameter=35.1mm, Vishay, TJ6, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 31.00mm diameter 35.1mm Vishay TJ6 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D40.0mm_P48.26mm +L_Toroid, Horizontal series, Radial, pin pitch=48.26mm, , diameter=40mm +L_Toroid Horizontal series Radial pin pitch 48.26mm diameter 40mm +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D41.9mm_P37.60mm_Vishay_TJ7 +L_Toroid, Horizontal series, Radial, pin pitch=37.60mm, , diameter=41.9mm, Vishay, TJ7, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 37.60mm diameter 41.9mm Vishay TJ7 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D49.3mm_P44.60mm_Vishay_TJ8 +L_Toroid, Horizontal series, Radial, pin pitch=44.60mm, , diameter=49.3mm, Vishay, TJ8, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 44.60mm diameter 49.3mm Vishay TJ8 +0 +2 +2 +Inductor_THT +L_Toroid_Horizontal_D69.1mm_P63.20mm_Vishay_TJ9 +L_Toroid, Horizontal series, Radial, pin pitch=63.20mm, , diameter=69.1mm, Vishay, TJ9, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Horizontal series Radial pin pitch 63.20mm diameter 69.1mm Vishay TJ9 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L10.0mm_W5.0mm_P5.08mm +L_Toroid, Vertical series, Radial, pin pitch=5.08mm, , length*width=10*5mm^2 +L_Toroid Vertical series Radial pin pitch 5.08mm length 10mm width 5mm +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L13.0mm_W6.5mm_P5.60mm +L_Toroid, Vertical series, Radial, pin pitch=5.60mm, , length*width=13*6.5mm^2 +L_Toroid Vertical series Radial pin pitch 5.60mm length 13mm width 6.5mm +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L14.0mm_W5.6mm_P5.30mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=5.30mm, , length*width=14*5.6mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 5.30mm length 14mm width 5.6mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L14.0mm_W6.3mm_P4.57mm_Pulse_A +L_Toroid, Vertical series, Radial, pin pitch=4.57mm, , length*width=13.97*6.35mm^2, Pulse, A, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 4.57mm length 13.97mm width 6.35mm Pulse A +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L14.7mm_W8.6mm_P5.58mm_Pulse_KM-1 +L_Toroid, Vertical series, Radial, pin pitch=5.58mm, , length*width=14.73*8.64mm^2, Pulse, KM-1, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 5.58mm length 14.73mm width 8.64mm Pulse KM-1 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L16.0mm_W8.0mm_P7.62mm +L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=16*8mm^2 +L_Toroid Vertical series Radial pin pitch 7.62mm length 16mm width 8mm +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L16.3mm_W7.1mm_P7.11mm_Pulse_H +L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=16.26*7.11mm^2, Pulse, H, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 7.11mm length 16.26mm width 7.11mm Pulse H +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L16.4mm_W7.6mm_P6.60mm_Vishay_TJ3 +L_Toroid, Vertical series, Radial, pin pitch=6.60mm, , length*width=16.4*7.6mm^2, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 6.60mm length 16.4mm width 7.6mm Vishay TJ3 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L16.5mm_W11.4mm_P7.62mm_Pulse_KM-2 +L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=16.51*11.43mm^2, Pulse, KM-2, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 7.62mm length 16.51mm width 11.43mm Pulse KM-2 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L16.8mm_W9.2mm_P7.10mm_Vishay_TJ3 +L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=16.8*9.2mm^2, Vishay, TJ3, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 7.10mm length 16.8mm width 9.2mm Vishay TJ3 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L16.8mm_W9.2mm_P7.10mm_Vishay_TJ3_BigPads +L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=16.8*9.2mm^2, Vishay, TJ3, BigPads, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 7.10mm length 16.8mm width 9.2mm Vishay TJ3 BigPads +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L17.8mm_W8.1mm_P7.62mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=17.8*8.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 7.62mm length 17.8mm width 8.1mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L17.8mm_W9.7mm_P7.11mm_Pulse_B +L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=17.78*9.65mm^2, Pulse, B, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 7.11mm length 17.78mm width 9.65mm Pulse B +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L19.1mm_W8.1mm_P7.10mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=7.10mm, , length*width=19.1*8.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 7.10mm length 19.1mm width 8.1mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L21.6mm_W8.4mm_P8.38mm_Pulse_G +L_Toroid, Vertical series, Radial, pin pitch=8.38mm, , length*width=21.59*8.38mm^2, Pulse, G, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 8.38mm length 21.59mm width 8.38mm Pulse G +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L21.6mm_W9.1mm_P8.40mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=8.40mm, , length*width=21.6*9.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 8.40mm length 21.6mm width 9.1mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L21.6mm_W9.5mm_P7.11mm_Pulse_C +L_Toroid, Vertical series, Radial, pin pitch=7.11mm, , length*width=21.59*9.53mm^2, Pulse, C, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 7.11mm length 21.59mm width 9.53mm Pulse C +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L21.6mm_W11.4mm_P7.62mm_Pulse_KM-3 +L_Toroid, Vertical series, Radial, pin pitch=7.62mm, , length*width=21.59*11.43mm^2, Pulse, KM-3, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 7.62mm length 21.59mm width 11.43mm Pulse KM-3 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L22.4mm_W10.2mm_P7.90mm_Vishay_TJ4 +L_Toroid, Vertical series, Radial, pin pitch=7.90mm, , length*width=22.4*10.2mm^2, Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 7.90mm length 22.4mm width 10.2mm Vishay TJ4 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L24.6mm_W15.5mm_P11.44mm_Pulse_KM-4 +L_Toroid, Vertical series, Radial, pin pitch=11.44mm, , length*width=24.64*15.5mm^2, Pulse, KM-4, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 11.44mm length 24.64mm width 15.5mm Pulse KM-4 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L25.4mm_W14.7mm_P12.20mm_Vishay_TJ5 +L_Toroid, Vertical series, Radial, pin pitch=12.20mm, , length*width=25.4*14.7mm^2, Vishay, TJ5, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 12.20mm length 25.4mm width 14.7mm Vishay TJ5 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L25.4mm_W14.7mm_P12.20mm_Vishay_TJ5_BigPads +L_Toroid, Vertical series, Radial, pin pitch=12.20mm, , length*width=25.4*14.7mm^2, Vishay, TJ5, BigPads, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 12.20mm length 25.4mm width 14.7mm Vishay TJ5 BigPads +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L26.7mm_W14.0mm_P10.16mm_Pulse_D +L_Toroid, Vertical series, Radial, pin pitch=10.16mm, , length*width=26.67*13.97mm^2, Pulse, D, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 10.16mm length 26.67mm width 13.97mm Pulse D +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L28.6mm_W14.3mm_P11.43mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=11.43mm, , length*width=28.6*14.3mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 11.43mm length 28.6mm width 14.3mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L31.8mm_W15.9mm_P13.50mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=13.50mm, , length*width=31.8*15.9mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 13.50mm length 31.8mm width 15.9mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L33.0mm_W17.8mm_P12.70mm_Pulse_KM-5 +L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=33.02*17.78mm^2, Pulse, KM-5, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 12.70mm length 33.02mm width 17.78mm Pulse KM-5 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L35.1mm_W21.1mm_P18.50mm_Vishay_TJ6 +L_Toroid, Vertical series, Radial, pin pitch=18.50mm, , length*width=35.1*21.1mm^2, Vishay, TJ6, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 18.50mm length 35.1mm width 21.1mm Vishay TJ6 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L35.6mm_W17.8mm_P12.70mm_Pulse_E +L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=35.56*17.78mm^2, Pulse, E, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 12.70mm length 35.56mm width 17.78mm Pulse E +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L41.9mm_W17.8mm_P12.70mm_Pulse_F +L_Toroid, Vertical series, Radial, pin pitch=12.70mm, , length*width=41.91*17.78mm^2, Pulse, F, http://datasheet.octopart.com/PE-92112KNL-Pulse-datasheet-17853305.pdf +L_Toroid Vertical series Radial pin pitch 12.70mm length 41.91mm width 17.78mm Pulse F +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L41.9mm_W19.1mm_P15.80mm_Vishay_TJ7 +L_Toroid, Vertical series, Radial, pin pitch=15.80mm, , length*width=41.9*19.1mm^2, Vishay, TJ7, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 15.80mm length 41.9mm width 19.1mm Vishay TJ7 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L46.0mm_W19.1mm_P21.80mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=21.80mm, , length*width=46*19.1mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 21.80mm length 46mm width 19.1mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L48.8mm_W25.4mm_P20.80mm_Vishay_TJ8 +L_Toroid, Vertical series, Radial, pin pitch=20.80mm, , length*width=48.8*25.4mm^2, Vishay, TJ8, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 20.80mm length 48.8mm width 25.4mm Vishay TJ8 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L54.0mm_W23.8mm_P20.10mm_Bourns_5700 +L_Toroid, Vertical series, Radial, pin pitch=20.10mm, , length*width=54*23.8mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf +L_Toroid Vertical series Radial pin pitch 20.10mm length 54mm width 23.8mm Bourns 5700 +0 +2 +2 +Inductor_THT +L_Toroid_Vertical_L67.6mm_W36.1mm_P31.80mm_Vishay_TJ9 +L_Toroid, Vertical series, Radial, pin pitch=31.80mm, , length*width=67.6*36.1mm^2, Vishay, TJ9, http://www.vishay.com/docs/34079/tj.pdf +L_Toroid Vertical series Radial pin pitch 31.80mm length 67.6mm width 36.1mm Vishay TJ9 +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Bridged2Bar_Pad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, bridged with 2 copper strips +solder jumper open +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Bridged2Bar_RoundedPad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, bridged with 2 copper strips +solder jumper open +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Bridged_Pad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, bridged with 1 copper strip +solder jumper open +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, bridged with 1 copper strip +solder jumper open +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Open_Pad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, open +solder jumper open +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm, rounded Pads, 0.3mm gap, open +solder jumper open +0 +2 +2 +Jumper +SolderJumper-2_P1.3mm_Open_TrianglePad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open +solder jumper open +0 +2 +2 +Jumper +SolderJumper-3_P1.3mm_Bridged2Bar12_Pad1.0x1.5mm +SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged2Bar12_Pad1.0x1.5mm_NumberLabels +SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip, labeled with numbers +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged2Bar12_RoundedPad1.0x1.5mm +SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged2Bar12_RoundedPad1.0x1.5mm_NumberLabels +SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 Bridged2Bar with 2 copper strip, labeled with numbers +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged12_Pad1.0x1.5mm +SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged12_Pad1.0x1.5mm_NumberLabels +SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip, labeled with numbers +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm +SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Bridged12_RoundedPad1.0x1.5mm_NumberLabels +SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, pads 1-2 bridged with 1 copper strip, labeled with numbers +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm +SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, open +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm_NumberLabels +SMD Solder Jumper, 1x1.5mm Pads, 0.3mm gap, open, labeled with numbers +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm +SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P1.3mm_Open_RoundedPad1.0x1.5mm_NumberLabels +SMD Solder 3-pad Jumper, 1x1.5mm rounded Pads, 0.3mm gap, open, labeled with numbers +solder jumper open +0 +3 +3 +Jumper +SolderJumper-3_P2.0mm_Open_TrianglePad1.0x1.5mm +SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open +solder jumper open +0 +5 +3 +Jumper +SolderJumper-3_P2.0mm_Open_TrianglePad1.0x1.5mm_NumberLabels +SMD Solder Jumper, 1x1.5mm Triangular Pads, 0.3mm gap, open, labeled with numbers +solder jumper open +0 +5 +3 +LED_SMD +LED-APA102-2020 +http://www.led-color.com/upload/201604/APA102-2020%20SMD%20LED.pdf +LED RGB SPI +0 +8 +6 +LED_SMD +LED-L1T2_LUMILEDS +http://www.lumileds.com/uploads/438/DS133-pdf +LUMILEDS LUXEON TX L1T2 LED +0 +3 +3 +LED_SMD +LED_1W_3W_R8 +https://www.gme.cz/data/attachments/dsh.518-234.1.pdf +LED 1W 3W 5W +0 +3 +3 +LED_SMD +LED_0201_0603Metric +LED SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +LED +0 +4 +2 +LED_SMD +LED_0402_1005Metric +LED SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED +0 +2 +2 +LED_SMD +LED_0603_1608Metric +LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_0603_1608Metric_Castellated +LED SMD 0603 (1608 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder +LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_0805_2012Metric +LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_0805_2012Metric_Castellated +LED SMD 0805 (2012 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_0805_2012Metric_Pad1.15x1.40mm_HandSolder +LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_01005_0402Metric +LED SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +LED +0 +4 +2 +LED_SMD +LED_1206_3216Metric +LED SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_1206_3216Metric_Castellated +LED SMD 1206 (3216 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_1206_3216Metric_Pad1.42x1.75mm_HandSolder +LED SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_1206_3216Metric_ReverseMount_Hole1.8x2.4mm +LED SMD 1206 (3216 Metric), reverse mount, square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode reverse +0 +2 +2 +LED_SMD +LED_1210_3225Metric +LED SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_1210_3225Metric_Castellated +LED SMD 1210 (3225 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_1210_3225Metric_Pad1.42x2.65mm_HandSolder +LED SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_1806_4516Metric +LED SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_1806_4516Metric_Castellated +LED SMD 1806 (4516 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_1806_4516Metric_Pad1.57x1.80mm_HandSolder +LED SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_1812_4532Metric +LED SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_1812_4532Metric_Castellated +LED SMD 1812 (4532 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_1812_4532Metric_Pad1.30x3.40mm_HandSolder +LED SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_2010_5025Metric +LED SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_2010_5025Metric_Castellated +LED SMD 2010 (5025 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_2010_5025Metric_Pad1.52x2.65mm_HandSolder +LED SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_2512_6332Metric +LED SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_2512_6332Metric_Castellated +LED SMD 2512 (6332 Metric), castellated end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_2512_6332Metric_Pad1.52x3.35mm_HandSolder +LED SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_2816_7142Metric +LED SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +diode +0 +2 +2 +LED_SMD +LED_2816_7142Metric_Castellated +LED SMD 2816 (7142 Metric), castellated end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +LED castellated +0 +2 +2 +LED_SMD +LED_2816_7142Metric_Pad3.20x4.45mm_HandSolder +LED SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +LED handsolder +0 +2 +2 +LED_SMD +LED_Avago_PLCC4_3.2x2.8mm_CW +https://docs.broadcom.com/docs/AV02-4186EN +LED Avago PLCC-4 ASMB-MTB0-0A3A2 +0 +4 +4 +LED_SMD +LED_Avago_PLCC6_3x2.8mm +https://docs.broadcom.com/docs/AV02-3793EN +LED Avago PLCC-6 ASMT-YTB7-0AA02 +0 +6 +6 +LED_SMD +LED_Cree-PLCC4_2x2mm_CW +2.0mm x 2.0mm PLCC4 LED, http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/HB/Data-Sheets/CLMVBFKA.pdf +LED Cree PLCC-4 +0 +4 +4 +LED_SMD +LED_Cree-PLCC4_3.2x2.8mm_CCW +3.2mm x 2.8mm PLCC4 LED, http://www.cree.com/led-components/media/documents/CLV1AFKB(874).pdf +LED Cree PLCC-4 +0 +4 +4 +LED_SMD +LED_Cree-PLCC4_5x5mm_CW +5.0mm x 5.0mm PLCC4 LED +LED Cree PLCC-4 +0 +4 +4 +LED_SMD +LED_Cree-PLCC6_4.7x1.5mm +4.7mm x 1.5mm PLCC6 LED, http://www.cree.com/led-components/media/documents/1381-QLS6AFKW.pdf +LED Cree PLCC-6 +0 +6 +6 +LED_SMD +LED_Cree-XB +http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/XLampXBD.pdf +LED Cree XB +0 +5 +3 +LED_SMD +LED_Cree-XH +http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XHB.pdf +LED Cree XH +0 +8 +2 +LED_SMD +LED_Cree-XHP35 +http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds--XHP35.pdf +LED Cree XHP35 +0 +6 +3 +LED_SMD +LED_Cree-XHP50_6V +Cree XHP50, 6V footprint, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP50.pdf +LED Cree XHP50 +0 +17 +3 +LED_SMD +LED_Cree-XHP50_12V +Cree XHP50, 12V footprint, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP50.pdf +LED XHP50 Cree +0 +15 +3 +LED_SMD +LED_Cree-XHP70_6V +Cree XHP70 LED, 6V version, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP70.pdf +LED Cree XHP70 +0 +17 +3 +LED_SMD +LED_Cree-XHP70_12V +Cree XHP70 LED, 12V version, http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/ds%20XHP70.pdf +LED Cree XHP70 +0 +15 +3 +LED_SMD +LED_Cree-XP +LED Cree-XP http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/XLampXPE2.pdf +LED Cree XP +0 +6 +3 +LED_SMD +LED_Cree-XP-G +LED Cree-XP-G http://www.cree.com/~/media/Files/Cree/LED%20Components%20and%20Modules/XLamp/Data%20and%20Binning/XLampXPG.pdf +LED Cree XP-G +0 +6 +3 +LED_SMD +LED_Cree-XQ +LED Cree-XQ http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XQB.pdf +LED Cree XQ +0 +2 +2 +LED_SMD +LED_Cree-XQ_HandSoldering +LED Cree-XQ handsoldering pads http://www.cree.com/~/media/Files/Cree/LED-Components-and-Modules/XLamp/Data-and-Binning/ds-XQB.pdf +LED Cree XQ +0 +2 +2 +LED_SMD +LED_Dialight_591 +LED SMD 3mm Right Angle series (http://www.dialightsignalsandcomponents.com/Assets/Drawings/2D_Drawings_DrawingDetailedSpec/C17354.pdf) +LED Dialight 591 +0 +2 +2 +LED_SMD +LED_Inolux_IN-PI554FCH_PLCC4_5.0x5.0mm_P3.2mm +http://www.inolux-corp.com/datasheet/SMDLED/Addressable%20LED/IN-PI554FCH.pdf +RGB LED NeoPixel addressable +0 +4 +4 +LED_SMD +LED_Kingbright_AAA3528ESGCT +Kingbright, dual LED, 3.5 x 2.8 mm Surface Mount LED Lamp (http://www.kingbrightusa.com/images/catalog/SPEC/AAA3528ESGCT.pdf) +dual led smd +0 +4 +4 +LED_SMD +LED_Kingbright_APFA3010_3x1.5mm_Horizontal +LED RGB, APFA3010, http://www.kingbrightusa.com/images/catalog/SPEC/APFA3010LSEEZGKQBKC.pdf +LED RGB APFA3010 KINGBRIGHT 3x1.5mm +0 +4 +4 +LED_SMD +LED_LiteOn_LTST-C19HE1WT +LiteOn RGB LED; https://optoelectronics.liteon.com/upload/download/DS22-2008-0044/LTST-C19HE1WT.pdf +LED RGB Chip SMD +0 +4 +4 +LED_SMD +LED_LiteOn_LTST-S326 +http://optoelectronics.liteon.com/upload/download/DS22-2000-287/LTST-S326KGJRKT.PDF +LED SMD right angle CCA +0 +3 +3 +LED_SMD +LED_Osram_Lx_P47F_D2mm_ReverseMount +OSRAM, reverse-mount LED, SMD, 2mm diameter, http://www.farnell.com/datasheets/2711587.pdf +LED ReverseMount Reverse +0 +4 +2 +LED_SMD +LED_PLCC-2 +LED PLCC-2 SMD package +LED PLCC-2 SMD +0 +2 +2 +LED_SMD +LED_PLCC_2835 +https://www.luckylight.cn/media/component/data-sheet/R2835BC-B2M-M10.pdf +LED +0 +2 +2 +LED_SMD +LED_PLCC_2835_Handsoldering +https://www.luckylight.cn/media/component/data-sheet/R2835BC-B2M-M10.pdf +LED +0 +2 +2 +LED_SMD +LED_RGB_1210 +RGB LED 3.2x2.7mm http://www.avagotech.com/docs/AV02-0610EN +LED 3227 +0 +4 +4 +LED_SMD +LED_RGB_5050-6 +http://cdn.sparkfun.com/datasheets/Components/LED/5060BRG4.pdf +RGB LED 5050-6 +0 +6 +6 +LED_SMD +LED_RGB_Cree-PLCC-6_6x5mm_P2.1mm +http://www.farnell.com/datasheets/2003905.pdf +LED RGB PLCC-6 CLP6C-FBK +0 +6 +6 +LED_SMD +LED_RGB_Getian_GT-P6PRGB4303 +https://www.gme.sk/img/cache/doc/518/177/vykonova-led-getian-gt-p6prgb4303-datasheet-1.pdf +LED RGB +0 +7 +7 +LED_SMD +LED_RGB_PLCC-6 +RGB LED PLCC-6 +RGB LED PLCC-6 +0 +6 +6 +LED_SMD +LED_ROHM_SMLVN6 +https://www.rohm.com/datasheet/SMLVN6RGB1U +LED ROHM SMLVN6 +0 +6 +6 +LED_SMD +LED_SK6805_PLCC4_2.4x2.7mm_P1.3mm +https://cdn-shop.adafruit.com/product-files/3484/3484_Datasheet.pdf +LED RGB NeoPixel Nano +0 +4 +4 +LED_SMD +LED_SK6812MINI_PLCC4_3.5x3.5mm_P1.75mm +https://cdn-shop.adafruit.com/product-files/2686/SK6812MINI_REV.01-1-2.pdf +LED RGB NeoPixel Mini +0 +4 +4 +LED_SMD +LED_SK6812_EC15_1.5x1.5mm +http://www.newstar-ledstrip.com/product/20181119172602110.pdf +LED RGB NeoPixel +0 +4 +4 +LED_SMD +LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm +https://cdn-shop.adafruit.com/product-files/1138/SK6812+LED+datasheet+.pdf +LED RGB NeoPixel +0 +4 +4 +LED_SMD +LED_WS2812B_PLCC4_5.0x5.0mm_P3.2mm +https://cdn-shop.adafruit.com/datasheets/WS2812B.pdf +LED RGB NeoPixel +0 +4 +4 +LED_SMD +LED_WS2812_PLCC6_5.0x5.0mm_P1.6mm +https://cdn-shop.adafruit.com/datasheets/WS2812.pdf +LED RGB NeoPixel +0 +6 +6 +LED_SMD +LED_Yuji_5730 +LED,Yuji,5730,https://cdn.shopify.com/s/files/1/0344/6401/files/YJWJ014-1.1_YJ-BC-5730L-G02.pdf +LED Yuji 5730 +0 +3 +2 +LED_SMD +LED_miniPLCC_2315 +https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DAV02-2205EN_DS_ASMT-TxBM_2014-05-09.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430858274704&ssbinary=true +LED +0 +2 +2 +LED_SMD +LED_miniPLCC_2315_Handsoldering +https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DAV02-2205EN_DS_ASMT-TxBM_2014-05-09.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430858274704&ssbinary=true +LED +0 +2 +2 +LED_THT +LED_BL-FL7680RGB +'Piranha' RGB LED, through hole, common anode, 7.62x7.62mm, BGRA pin order, https://cdn-shop.adafruit.com/datasheets/BL-FL7680RGB.pdf +RGB LED Piranha Super-Flux BetLux +0 +4 +4 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z1.6mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z4.9mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O1.27mm_Z8.2mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z1.6mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z4.9mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O3.81mm_Z8.2mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z1.6mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z4.9mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W1.8mm_H2.4mm_Horizontal_O6.35mm_Z8.2mm +LED, , diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins, diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm, 2 pins +LED diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 1.6mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 4.9mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins diameter 1.8mm size 1.8x2.4mm^2 z-position of LED center 8.2mm 2 pins +0 +2 +2 +LED_THT +LED_D1.8mm_W3.3mm_H2.4mm +LED, Round, Rectangular size 3.3x2.4mm^2 diameter 1.8mm, 2 pins +LED Round Rectangular size 3.3x2.4mm^2 diameter 1.8mm 2 pins +0 +2 +2 +LED_THT +LED_D2.0mm_W4.0mm_H2.8mm_FlatTop +LED, Round, FlatTop, Rectangular size 4.0x2.8mm^2 diameter 2.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-1034IDT(Ver.9A).pdf +LED Round FlatTop Rectangular size 4.0x2.8mm^2 diameter 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D2.0mm_W4.8mm_H2.5mm_FlatTop +LED, Round, FlatTop, Rectangular size 4.8x2.5mm^2 diameter 2.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-13GD(Ver.11B).pdf +LED Round FlatTop Rectangular size 4.8x2.5mm^2 diameter 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm +LED, diameter 3.0mm, 2 pins +LED diameter 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm-3 +LED, diameter 3.0mm, 2 pins, diameter 3.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-3VSURKCGKC(Ver.8A).pdf +LED diameter 3.0mm 2 pins diameter 3.0mm 3 pins +0 +3 +3 +LED_THT +LED_D3.0mm_Clear +IR-LED, diameter 3.0mm, 2 pins, color: clear +IR infrared LED diameter 3.0mm 2 pins clear +0 +2 +2 +LED_THT +LED_D3.0mm_FlatTop +LED, Round, FlatTop, diameter 3.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-47XEC(Ver.9A).pdf +LED Round FlatTop diameter 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_Clear +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_IRBlack +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm_IRGrey +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O1.27mm_Z6.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O1.27mm_Z10.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O3.81mm_Z2.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O3.81mm_Z6.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O3.81mm_Z10.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O6.35mm_Z2.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O6.35mm_Z6.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_Horizontal_O6.35mm_Z10.0mm +LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 2.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 6.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins, diameter 3.0mm z-position of LED center 10.0mm, 2 pins +LED diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 2.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 6.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins diameter 3.0mm z-position of LED center 10.0mm 2 pins +0 +2 +2 +LED_THT +LED_D3.0mm_IRBlack +IR-ED, diameter 3.0mm, 2 pins, color: black +IR infrared LED diameter 3.0mm 2 pins black +0 +2 +2 +LED_THT +LED_D3.0mm_IRGrey +IR-LED, diameter 3.0mm, 2 pins, color: grey +IR infrared LED diameter 3.0mm 2 pins grey +0 +2 +2 +LED_THT +LED_D4.0mm +LED, diameter 4.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-43GD(Ver.12B).pdf +LED diameter 4.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm +LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf +LED diameter 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm-3 +LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-59EGC(Ver.17A).pdf +LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins +0 +3 +3 +LED_THT +LED_D5.0mm-3_Horizontal_O3.81mm_Z3.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 3 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 3 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +3 +3 +LED_THT +LED_D5.0mm-4_RGB +LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf +LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED +0 +4 +4 +LED_THT +LED_D5.0mm-4_RGB_Staggered_Pins +LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf +LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED +0 +4 +4 +LED_THT +LED_D5.0mm-4_RGB_Wide_Pins +LED, diameter 5.0mm, 2 pins, diameter 5.0mm, 3 pins, diameter 5.0mm, 4 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-154A4SUREQBFZGEW(Ver.9A).pdf +LED diameter 5.0mm 2 pins diameter 5.0mm 3 pins diameter 5.0mm 4 pins RGB RGBLED +0 +4 +4 +LED_THT +LED_D5.0mm_Clear +LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf +LED diameter 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_FlatTop +LED, Round, FlatTop, diameter 5.0mm, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-483GDT(Ver.15B).pdf +LED Round FlatTop diameter 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_Clear +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_IRBlack +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O1.27mm_Z3.0mm_IRGrey +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O1.27mm_Z9.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O1.27mm_Z15.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O3.81mm_Z3.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O3.81mm_Z9.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O3.81mm_Z15.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O6.35mm_Z3.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O6.35mm_Z9.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_Horizontal_O6.35mm_Z15.0mm +LED, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 3.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 9.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins, diameter 5.0mm z-position of LED center 15.0mm, 2 pins +LED diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 3.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 9.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins diameter 5.0mm z-position of LED center 15.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_IRBlack +LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf +LED diameter 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_D5.0mm_IRGrey +LED, diameter 5.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LL-504BC2E-009.pdf +LED diameter 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_D8.0mm +LED, diameter 8.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED8MMGE_LED8MMGN_LED8MMRT%23KIN.pdf +LED diameter 8.0mm 2 pins +0 +2 +2 +LED_THT +LED_D8.0mm-3 +LED, diameter 8.0mm, 2 pins, diameter 8.0mm, 3 pins +LED diameter 8.0mm 2 pins diameter 8.0mm 3 pins +0 +3 +3 +LED_THT +LED_D10.0mm +LED, diameter 10.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED10-4500RT%23KIN.pdf +LED diameter 10.0mm 2 pins +0 +2 +2 +LED_THT +LED_D10.0mm-3 +LED, diameter 10.0mm, 2 pins, diameter 10.0mm, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-819EGW(Ver.14A).pdf +LED diameter 10.0mm 2 pins diameter 10.0mm 3 pins +0 +3 +3 +LED_THT +LED_D20.0mm +LED, diameter 20.0mm, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/DLC2-6GD%28V6%29.pdf +LED diameter 20.0mm 2 pins +0 +2 +2 +LED_THT +LED_Oval_W5.2mm_H3.8mm +LED_Oval, Oval, Oval size 5.2x3.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-5603QBC-D(Ver.12B).pdf +LED_Oval Oval Oval size 5.2x3.8mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W3.0mm_H2.0mm +LED_Rectangular, Rectangular, Rectangular size 3.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf +LED_Rectangular Rectangular Rectangular size 3.0x2.0mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W3.9mm_H1.8mm +LED_Rectangular, Rectangular, Rectangular size 3.9x1.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-2774GD(Ver.7B).pdf +LED_Rectangular Rectangular Rectangular size 3.9x1.8mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W3.9mm_H1.8mm_FlatTop +LED_Rectangular, Rectangular, Rectangular size 3.9x1.8mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-2774GD(Ver.7B).pdf +LED_Rectangular Rectangular Rectangular size 3.9x1.8mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W3.9mm_H1.9mm +LED_Rectangular, Rectangular, Rectangular size 3.9x1.9mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-144GDT(Ver.14B).pdf +LED_Rectangular Rectangular Rectangular size 3.9x1.9mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm-3Pins +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2, 3 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 3 pins +0 +3 +3 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z1.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z3.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O1.27mm_Z5.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z1.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z3.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O3.81mm_Z5.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z1.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z3.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H2.0mm_Horizontal_O6.35mm_Z5.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins, Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm, 2 pins +LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 1.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 3.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins Rectangular size 5.0x2.0mm^2 z-position of LED center 5.0mm 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W5.0mm_H5.0mm +LED_Rectangular, Rectangular, Rectangular size 5.0x5.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf +LED_Rectangular Rectangular Rectangular size 5.0x5.0mm^2 2 pins +0 +2 +2 +LED_THT +LED_Rectangular_W7.62mm_H4.55mm_P5.08mm_R3 +Datasheet can be found at https://www.gme.cz/data/attachments/dsh.511-795.1.pdf +LED automotive super flux 7.62mm +0 +4 +2 +LED_THT +LED_SideEmitter_Rectangular_W4.5mm_H1.6mm +LED_SideEmitter_Rectangular, Rectangular, SideEmitter, Rectangular size 4.5x1.6mm^2, 2 pins, http://cdn-reichelt.de/documents/datenblatt/A500/LED15MMGE_LED15MMGN%23KIN.pdf +LED_SideEmitter_Rectangular Rectangular SideEmitter Rectangular size 4.5x1.6mm^2 2 pins +0 +2 +2 +LED_THT +LED_VCCLite_5381H1_6.35x6.35mm +Red 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf +Red 5381 Series LED +0 +2 +2 +LED_THT +LED_VCCLite_5381H3_6.35x6.35mm +Amber 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf +Amber 5381 Series LED +0 +2 +2 +LED_THT +LED_VCCLite_5381H5_6.35x6.35mm +Green 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf +Green 5381 Series LED +0 +2 +2 +LED_THT +LED_VCCLite_5381H7_6.35x6.35mm +Yellow 5381 Series LED VCCLite https://vcclite.com/wp-content/uploads/wpallimport/files/files/5381Series.pdf http://static.vcclite.com/pdf/Mounting%20Hole%20Pattern%202.pdf +Yellow 5381 Series LED +0 +2 +2 +Module +A20_OLINUXINO_LIME2 +A20 Olinuxino LIME2, 1.2GHz, 512-1024MB RAM, Micro-SD, NAND or eMMC, 1000Mbit Ethernet +A20 Olimex Olinuxino LIME2 development board +0 +180 +180 +Module +Adafruit_HUZZAH_ESP8266_breakout +32-bit microcontroller module with WiFi, https://www.adafruit.com/product/2471 +ESP8266 WiFi microcontroller +0 +20 +20 +Module +Adafruit_HUZZAH_ESP8266_breakout_WithMountingHoles +32-bit microcontroller module with WiFi, https://www.adafruit.com/product/2471 +ESP8266 WiFi microcontroller +0 +20 +20 +Module +Arduino_Nano +Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf +Arduino Nano +0 +30 +30 +Module +Arduino_Nano_WithMountingHoles +Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf +Arduino Nano +0 +30 +30 +Module +Arduino_UNO_R2 +Arduino UNO R2, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf +Arduino UNO R2 +0 +30 +30 +Module +Arduino_UNO_R2_WithMountingHoles +Arduino UNO R2, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf +Arduino UNO R2 +0 +30 +30 +Module +Arduino_UNO_R3 +Arduino UNO R3, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf +Arduino UNO R3 +0 +32 +32 +Module +Arduino_UNO_R3_WithMountingHoles +Arduino UNO R3, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf +Arduino UNO R3 +0 +32 +32 +Module +BeagleBoard_PocketBeagle +PocketBeagle, https://github.com/beagleboard/pocketbeagle/wiki/System-Reference-Manual#71_Expansion_Header_Connectors +PocketBeagle +0 +72 +72 +Module +Maple_Mini +Maple Mini, http://docs.leaflabs.com/static.leaflabs.com/pub/leaflabs/maple-docs/0.0.12/hardware/maple-mini.html +Maple Mini +0 +40 +40 +Module +Onion_Omega2+ +https://onion.io/omega2/ +Omega Onion module +0 +32 +32 +Module +Onion_Omega2S +https://github.com/OnionIoT/Omega2/raw/master/Documents/Omega2S%20Datasheet.pdf +onion omega module +0 +89 +64 +Module +Pololu_Breakout-16_15.2x20.3mm +Pololu Breakout 16-pin 15.2x20.3mm 0.6x0.8\ +Pololu Breakout +0 +16 +16 +Module +Raspberry_Pi_Zero_Socketed_THT_FaceDown_MountingHoles +Raspberry Pi Zero using through hole straight pin socket, 2x20, 2.54mm pitch, https://www.raspberrypi.org/documentation/hardware/raspberrypi/mechanical/rpi_MECH_Zero_1p2.pdf +raspberry pi zero through hole +0 +40 +40 +Module +ST_Morpho_Connector_144_STLink +ST Morpho Connector 144 With STLink +ST Morpho Connector 144 STLink +0 +148 +148 +Module +ST_Morpho_Connector_144_STLink_MountingHoles +ST Morpho Connector 144 With STLink +ST Morpho Connector 144 STLink +0 +148 +148 +Module +WEMOS_D1_mini_light +16-pin module, column spacing 22.86 mm (900 mils), https://wiki.wemos.cc/products:d1:d1_mini, https://c1.staticflickr.com/1/734/31400410271_f278b087db_z.jpg +ESP8266 WiFi microcontroller +0 +16 +16 +MountingEquipment +DINRailAdapter_3xM3_PhoenixContact_1201578 +https://www.phoenixcontact.com/online/portal/us?uri=pxc-oc-itemdetail:pid=1201578&library=usen&tab=1 +DIN rail adapter universal three M3 clearance holes +0 +0 +0 +MountingHole +MountingHole_2.1mm +Mounting Hole 2.1mm, no annular +mounting hole 2.1mm no annular +0 +0 +0 +MountingHole +MountingHole_2.2mm_M2 +Mounting Hole 2.2mm, no annular, M2 +mounting hole 2.2mm no annular m2 +0 +0 +0 +MountingHole +MountingHole_2.2mm_M2_DIN965 +Mounting Hole 2.2mm, no annular, M2, DIN965 +mounting hole 2.2mm no annular m2 din965 +0 +0 +0 +MountingHole +MountingHole_2.2mm_M2_DIN965_Pad +Mounting Hole 2.2mm, M2, DIN965 +mounting hole 2.2mm m2 din965 +0 +1 +1 +MountingHole +MountingHole_2.2mm_M2_ISO7380 +Mounting Hole 2.2mm, no annular, M2, ISO7380 +mounting hole 2.2mm no annular m2 iso7380 +0 +0 +0 +MountingHole +MountingHole_2.2mm_M2_ISO7380_Pad +Mounting Hole 2.2mm, M2, ISO7380 +mounting hole 2.2mm m2 iso7380 +0 +1 +1 +MountingHole +MountingHole_2.2mm_M2_ISO14580 +Mounting Hole 2.2mm, no annular, M2, ISO14580 +mounting hole 2.2mm no annular m2 iso14580 +0 +0 +0 +MountingHole +MountingHole_2.2mm_M2_ISO14580_Pad +Mounting Hole 2.2mm, M2, ISO14580 +mounting hole 2.2mm m2 iso14580 +0 +1 +1 +MountingHole +MountingHole_2.2mm_M2_Pad +Mounting Hole 2.2mm, M2 +mounting hole 2.2mm m2 +0 +1 +1 +MountingHole +MountingHole_2.2mm_M2_Pad_Via +Mounting Hole 2.2mm, M2 +mounting hole 2.2mm m2 +0 +9 +1 +MountingHole +MountingHole_2.5mm +Mounting Hole 2.5mm, no annular +mounting hole 2.5mm no annular +0 +0 +0 +MountingHole +MountingHole_2.5mm_Pad +Mounting Hole 2.5mm +mounting hole 2.5mm +0 +1 +1 +MountingHole +MountingHole_2.5mm_Pad_Via +Mounting Hole 2.5mm +mounting hole 2.5mm +0 +9 +1 +MountingHole +MountingHole_2.7mm +Mounting Hole 2.7mm, no annular +mounting hole 2.7mm no annular +0 +0 +0 +MountingHole +MountingHole_2.7mm_M2.5 +Mounting Hole 2.7mm, no annular, M2.5 +mounting hole 2.7mm no annular m2.5 +0 +0 +0 +MountingHole +MountingHole_2.7mm_M2.5_DIN965 +Mounting Hole 2.7mm, no annular, M2.5, DIN965 +mounting hole 2.7mm no annular m2.5 din965 +0 +0 +0 +MountingHole +MountingHole_2.7mm_M2.5_DIN965_Pad +Mounting Hole 2.7mm, M2.5, DIN965 +mounting hole 2.7mm m2.5 din965 +0 +1 +1 +MountingHole +MountingHole_2.7mm_M2.5_ISO7380 +Mounting Hole 2.7mm, no annular, M2.5, ISO7380 +mounting hole 2.7mm no annular m2.5 iso7380 +0 +0 +0 +MountingHole +MountingHole_2.7mm_M2.5_ISO7380_Pad +Mounting Hole 2.7mm, M2.5, ISO7380 +mounting hole 2.7mm m2.5 iso7380 +0 +1 +1 +MountingHole +MountingHole_2.7mm_M2.5_ISO14580 +Mounting Hole 2.7mm, no annular, M2.5, ISO14580 +mounting hole 2.7mm no annular m2.5 iso14580 +0 +0 +0 +MountingHole +MountingHole_2.7mm_M2.5_ISO14580_Pad +Mounting Hole 2.7mm, M2.5, ISO14580 +mounting hole 2.7mm m2.5 iso14580 +0 +1 +1 +MountingHole +MountingHole_2.7mm_M2.5_Pad +Mounting Hole 2.7mm, M2.5 +mounting hole 2.7mm m2.5 +0 +1 +1 +MountingHole +MountingHole_2.7mm_M2.5_Pad_Via +Mounting Hole 2.7mm +mounting hole 2.7mm +0 +9 +1 +MountingHole +MountingHole_2.7mm_Pad +Mounting Hole 2.7mm +mounting hole 2.7mm +0 +1 +1 +MountingHole +MountingHole_2.7mm_Pad_Via +Mounting Hole 2.7mm +mounting hole 2.7mm +0 +9 +1 +MountingHole +MountingHole_2mm +Mounting Hole 2mm, no annular +mounting hole 2mm no annular +0 +0 +0 +MountingHole +MountingHole_3.2mm_M3 +Mounting Hole 3.2mm, no annular, M3 +mounting hole 3.2mm no annular m3 +0 +0 +0 +MountingHole +MountingHole_3.2mm_M3_DIN965 +Mounting Hole 3.2mm, no annular, M3, DIN965 +mounting hole 3.2mm no annular m3 din965 +0 +0 +0 +MountingHole +MountingHole_3.2mm_M3_DIN965_Pad +Mounting Hole 3.2mm, M3, DIN965 +mounting hole 3.2mm m3 din965 +0 +1 +1 +MountingHole +MountingHole_3.2mm_M3_ISO7380 +Mounting Hole 3.2mm, no annular, M3, ISO7380 +mounting hole 3.2mm no annular m3 iso7380 +0 +0 +0 +MountingHole +MountingHole_3.2mm_M3_ISO7380_Pad +Mounting Hole 3.2mm, M3, ISO7380 +mounting hole 3.2mm m3 iso7380 +0 +1 +1 +MountingHole +MountingHole_3.2mm_M3_ISO14580 +Mounting Hole 3.2mm, no annular, M3, ISO14580 +mounting hole 3.2mm no annular m3 iso14580 +0 +0 +0 +MountingHole +MountingHole_3.2mm_M3_ISO14580_Pad +Mounting Hole 3.2mm, M3, ISO14580 +mounting hole 3.2mm m3 iso14580 +0 +1 +1 +MountingHole +MountingHole_3.2mm_M3_Pad +Mounting Hole 3.2mm, M3 +mounting hole 3.2mm m3 +0 +1 +1 +MountingHole +MountingHole_3.2mm_M3_Pad_Via +Mounting Hole 3.2mm, M3 +mounting hole 3.2mm m3 +0 +9 +1 +MountingHole +MountingHole_3.5mm +Mounting Hole 3.5mm, no annular +mounting hole 3.5mm no annular +0 +0 +0 +MountingHole +MountingHole_3.5mm_Pad +Mounting Hole 3.5mm +mounting hole 3.5mm +0 +1 +1 +MountingHole +MountingHole_3.5mm_Pad_Via +Mounting Hole 3.5mm +mounting hole 3.5mm +0 +9 +1 +MountingHole +MountingHole_3.7mm +Mounting Hole 3.7mm, no annular +mounting hole 3.7mm no annular +0 +0 +0 +MountingHole +MountingHole_3.7mm_Pad +Mounting Hole 3.7mm +mounting hole 3.7mm +0 +1 +1 +MountingHole +MountingHole_3.7mm_Pad_Via +Mounting Hole 3.7mm +mounting hole 3.7mm +0 +9 +1 +MountingHole +MountingHole_3mm +Mounting Hole 3mm, no annular +mounting hole 3mm no annular +0 +0 +0 +MountingHole +MountingHole_3mm_Pad +Mounting Hole 3mm +mounting hole 3mm +0 +1 +1 +MountingHole +MountingHole_3mm_Pad_Via +Mounting Hole 3mm +mounting hole 3mm +0 +9 +1 +MountingHole +MountingHole_4.3mm_M4 +Mounting Hole 4.3mm, no annular, M4 +mounting hole 4.3mm no annular m4 +0 +0 +0 +MountingHole +MountingHole_4.3mm_M4_DIN965 +Mounting Hole 4.3mm, no annular, M4, DIN965 +mounting hole 4.3mm no annular m4 din965 +0 +0 +0 +MountingHole +MountingHole_4.3mm_M4_DIN965_Pad +Mounting Hole 4.3mm, M4, DIN965 +mounting hole 4.3mm m4 din965 +0 +1 +1 +MountingHole +MountingHole_4.3mm_M4_ISO7380 +Mounting Hole 4.3mm, no annular, M4, ISO7380 +mounting hole 4.3mm no annular m4 iso7380 +0 +0 +0 +MountingHole +MountingHole_4.3mm_M4_ISO7380_Pad +Mounting Hole 4.3mm, M4, ISO7380 +mounting hole 4.3mm m4 iso7380 +0 +1 +1 +MountingHole +MountingHole_4.3mm_M4_ISO14580 +Mounting Hole 4.3mm, no annular, M4, ISO14580 +mounting hole 4.3mm no annular m4 iso14580 +0 +0 +0 +MountingHole +MountingHole_4.3mm_M4_ISO14580_Pad +Mounting Hole 4.3mm, M4, ISO14580 +mounting hole 4.3mm m4 iso14580 +0 +1 +1 +MountingHole +MountingHole_4.3mm_M4_Pad +Mounting Hole 4.3mm, M4 +mounting hole 4.3mm m4 +0 +1 +1 +MountingHole +MountingHole_4.3mm_M4_Pad_Via +Mounting Hole 4.3mm, M4 +mounting hole 4.3mm m4 +0 +9 +1 +MountingHole +MountingHole_4.3x6.2mm_M4_Pad +Mounting Hole 4.3x6.2mm, M4 +mounting hole 4.3x6.2mm m4 +0 +1 +1 +MountingHole +MountingHole_4.3x6.2mm_M4_Pad_Via +Mounting Hole 4.3x6.2mm, M4 +mounting hole 4.3x6.2mm m4 +0 +17 +1 +MountingHole +MountingHole_4.5mm +Mounting Hole 4.5mm, no annular +mounting hole 4.5mm no annular +0 +0 +0 +MountingHole +MountingHole_4.5mm_Pad +Mounting Hole 4.5mm +mounting hole 4.5mm +0 +1 +1 +MountingHole +MountingHole_4.5mm_Pad_Via +Mounting Hole 4.5mm +mounting hole 4.5mm +0 +9 +1 +MountingHole +MountingHole_4mm +Mounting Hole 4mm, no annular +mounting hole 4mm no annular +0 +0 +0 +MountingHole +MountingHole_4mm_Pad +Mounting Hole 4mm +mounting hole 4mm +0 +1 +1 +MountingHole +MountingHole_4mm_Pad_Via +Mounting Hole 4mm +mounting hole 4mm +0 +9 +1 +MountingHole +MountingHole_5.3mm_M5 +Mounting Hole 5.3mm, no annular, M5 +mounting hole 5.3mm no annular m5 +0 +0 +0 +MountingHole +MountingHole_5.3mm_M5_DIN965 +Mounting Hole 5.3mm, no annular, M5, DIN965 +mounting hole 5.3mm no annular m5 din965 +0 +0 +0 +MountingHole +MountingHole_5.3mm_M5_DIN965_Pad +Mounting Hole 5.3mm, M5, DIN965 +mounting hole 5.3mm m5 din965 +0 +1 +1 +MountingHole +MountingHole_5.3mm_M5_ISO7380 +Mounting Hole 5.3mm, no annular, M5, ISO7380 +mounting hole 5.3mm no annular m5 iso7380 +0 +0 +0 +MountingHole +MountingHole_5.3mm_M5_ISO7380_Pad +Mounting Hole 5.3mm, M5, ISO7380 +mounting hole 5.3mm m5 iso7380 +0 +1 +1 +MountingHole +MountingHole_5.3mm_M5_ISO14580 +Mounting Hole 5.3mm, no annular, M5, ISO14580 +mounting hole 5.3mm no annular m5 iso14580 +0 +0 +0 +MountingHole +MountingHole_5.3mm_M5_ISO14580_Pad +Mounting Hole 5.3mm, M5, ISO14580 +mounting hole 5.3mm m5 iso14580 +0 +1 +1 +MountingHole +MountingHole_5.3mm_M5_Pad +Mounting Hole 5.3mm, M5 +mounting hole 5.3mm m5 +0 +1 +1 +MountingHole +MountingHole_5.3mm_M5_Pad_Via +Mounting Hole 5.3mm, M5 +mounting hole 5.3mm m5 +0 +9 +1 +MountingHole +MountingHole_5.5mm +Mounting Hole 5.5mm, no annular +mounting hole 5.5mm no annular +0 +0 +0 +MountingHole +MountingHole_5.5mm_Pad +Mounting Hole 5.5mm +mounting hole 5.5mm +0 +1 +1 +MountingHole +MountingHole_5.5mm_Pad_Via +Mounting Hole 5.5mm +mounting hole 5.5mm +0 +9 +1 +MountingHole +MountingHole_5mm +Mounting Hole 5mm, no annular +mounting hole 5mm no annular +0 +0 +0 +MountingHole +MountingHole_5mm_Pad +Mounting Hole 5mm +mounting hole 5mm +0 +1 +1 +MountingHole +MountingHole_5mm_Pad_Via +Mounting Hole 5mm +mounting hole 5mm +0 +9 +1 +MountingHole +MountingHole_6.4mm_M6 +Mounting Hole 6.4mm, no annular, M6 +mounting hole 6.4mm no annular m6 +0 +0 +0 +MountingHole +MountingHole_6.4mm_M6_DIN965 +Mounting Hole 6.4mm, no annular, M6, DIN965 +mounting hole 6.4mm no annular m6 din965 +0 +0 +0 +MountingHole +MountingHole_6.4mm_M6_DIN965_Pad +Mounting Hole 6.4mm, M6, DIN965 +mounting hole 6.4mm m6 din965 +0 +1 +1 +MountingHole +MountingHole_6.4mm_M6_ISO7380 +Mounting Hole 6.4mm, no annular, M6, ISO7380 +mounting hole 6.4mm no annular m6 iso7380 +0 +0 +0 +MountingHole +MountingHole_6.4mm_M6_ISO7380_Pad +Mounting Hole 6.4mm, M6, ISO7380 +mounting hole 6.4mm m6 iso7380 +0 +1 +1 +MountingHole +MountingHole_6.4mm_M6_ISO14580 +Mounting Hole 6.4mm, no annular, M6, ISO14580 +mounting hole 6.4mm no annular m6 iso14580 +0 +0 +0 +MountingHole +MountingHole_6.4mm_M6_ISO14580_Pad +Mounting Hole 6.4mm, M6, ISO14580 +mounting hole 6.4mm m6 iso14580 +0 +1 +1 +MountingHole +MountingHole_6.4mm_M6_Pad +Mounting Hole 6.4mm, M6 +mounting hole 6.4mm m6 +0 +1 +1 +MountingHole +MountingHole_6.4mm_M6_Pad_Via +Mounting Hole 6.4mm, M6 +mounting hole 6.4mm m6 +0 +9 +1 +MountingHole +MountingHole_6.5mm +Mounting Hole 6.5mm, no annular +mounting hole 6.5mm no annular +0 +0 +0 +MountingHole +MountingHole_6.5mm_Pad +Mounting Hole 6.5mm +mounting hole 6.5mm +0 +1 +1 +MountingHole +MountingHole_6.5mm_Pad_Via +Mounting Hole 6.5mm +mounting hole 6.5mm +0 +9 +1 +MountingHole +MountingHole_6mm +Mounting Hole 6mm, no annular +mounting hole 6mm no annular +0 +0 +0 +MountingHole +MountingHole_6mm_Pad +Mounting Hole 6mm +mounting hole 6mm +0 +1 +1 +MountingHole +MountingHole_6mm_Pad_Via +Mounting Hole 6mm +mounting hole 6mm +0 +9 +1 +MountingHole +MountingHole_8.4mm_M8 +Mounting Hole 8.4mm, no annular, M8 +mounting hole 8.4mm no annular m8 +0 +0 +0 +MountingHole +MountingHole_8.4mm_M8_Pad +Mounting Hole 8.4mm, M8 +mounting hole 8.4mm m8 +0 +1 +1 +MountingHole +MountingHole_8.4mm_M8_Pad_Via +Mounting Hole 8.4mm, M8 +mounting hole 8.4mm m8 +0 +9 +1 +NetTie +NetTie-2_SMD_Pad0.5mm +Net tie, 2 pin, 0.5mm square SMD pads +net tie +0 +2 +2 +NetTie +NetTie-2_SMD_Pad2.0mm +Net tie, 2 pin, 2.0mm square SMD pads +net tie +0 +2 +2 +NetTie +NetTie-2_THT_Pad0.3mm +Net tie, 2 pin, 0.3mm round THT pads +net tie +0 +2 +2 +NetTie +NetTie-2_THT_Pad1.0mm +Net tie, 2 pin, 1.0mm round THT pads +net tie +0 +2 +2 +NetTie +NetTie-3_SMD_Pad0.5mm +Net tie, 3 pin, 0.5mm square SMD pads +net tie +0 +3 +3 +NetTie +NetTie-3_SMD_Pad2.0mm +Net tie, 3 pin, 2.0mm square SMD pads +net tie +0 +3 +3 +NetTie +NetTie-3_THT_Pad0.3mm +Net tie, 3 pin, 0.3mm round THT pads +net tie +0 +3 +3 +NetTie +NetTie-3_THT_Pad1.0mm +Net tie, 3 pin, 1.0mm round THT pads +net tie +0 +3 +3 +NetTie +NetTie-4_SMD_Pad0.5mm +Net tie, 4 pin, 0.5mm square SMD pads +net tie +0 +4 +4 +NetTie +NetTie-4_SMD_Pad2.0mm +Net tie, 4 pin, 2.0mm square SMD pads +net tie +0 +4 +4 +NetTie +NetTie-4_THT_Pad0.3mm +Net tie, 4 pin, 0.3mm round THT pads +net tie +0 +4 +4 +NetTie +NetTie-4_THT_Pad1.0mm +Net tie, 4 pin, 1.0mm round THT pads +net tie +0 +4 +4 +OptoDevice +ADNS-9800 +Laser Gaming Sensor ADNS-9800 +MOUSE MOUSE_SENSOR LASER_GAMING_SENSOR +0 +16 +16 +OptoDevice +AGILENT_HFBR-152x +Fiberoptic Transmitter TX, HFBR series (https://docs.broadcom.com/docs/AV02-3283EN) +Fiberoptic Transmitter +0 +6 +6 +OptoDevice +AGILENT_HFBR-252x +Fiberoptic Receiver RX, HFBR series (https://docs.broadcom.com/docs/AV02-3283EN) +Fiberoptic Transmitter +0 +6 +6 +OptoDevice +AMS_TSL2550_SMD +http://ams.com/eng/content/download/250130/975613/142977 +TSL2550 ambient light sensor +0 +4 +4 +OptoDevice +Broadcom_AFBR-16xxZ_Horizontal +Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN +Fiber Optic Transmitter and Receiver +0 +6 +6 +OptoDevice +Broadcom_AFBR-16xxZ_Tilted +Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN +Fiber Optic Transmitter and Receiver +0 +6 +6 +OptoDevice +Broadcom_AFBR-16xxZ_Vertical +Fiber Optic Transmitter and Receiver, https://docs.broadcom.com/docs/AV02-4369EN +Fiber Optic Transmitter and Receiver +0 +6 +6 +OptoDevice +Broadcom_APDS-9301 +ambient light sensor, i2c interface, 6-pin chipled package, https://docs.broadcom.com/docs/AV02-2315EN +ambient light sensor chipled +0 +6 +6 +OptoDevice +Broadcom_DFN-6_2x2mm_P0.65mm +Broadcom DFN, 6 Pin (https://docs.broadcom.com/docs/AV02-4755EN), generated with kicad-footprint-generator ipc_noLead_generator.py +Broadcom DFN NoLead +0 +6 +6 +OptoDevice +Broadcom_LGA-8_2x2mm_P0.53mm +Broadcom LGA, 8 Pin (https://docs.broadcom.com/docs/AV02-4755EN), generated with kicad-footprint-generator ipc_noLead_generator.py +Broadcom LGA NoLead +0 +8 +8 +OptoDevice +Everlight_ITR8307 +package for Everlight ITR8307 with PCB cutout, light-direction upwards, see http://www.everlight.com/file/ProductFile/ITR8307.pdf +refective opto couple photo coupler +0 +4 +4 +OptoDevice +Everlight_ITR8307F43 +package for Everlight ITR8307/F43, see https://everlighteurope.com/index.php?controller=attachment&id_attachment=5385 +refective opto couple photo coupler +0 +4 +4 +OptoDevice +Everlight_ITR8307_Reverse +package for Everlight ITR8307 with PCB cutout, light-direction downwards, see http://www.everlight.com/file/ProductFile/ITR8307.pdf +refective opto couple photo coupler +0 +4 +4 +OptoDevice +Finder_34.81 +Relay SPST, Finder Type 34.81 (opto relays/coupler), vertical/standing form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf +Relay SPST Finder +0 +4 +4 +OptoDevice +Hamamatsu_C12880 +Hamamatsu spectrometer, see http://www.hamamatsu.com/resources/pdf/ssd/c12880ma_kacc1226e.pdf +opto spectrometer Hamamatsu +0 +10 +10 +OptoDevice +Hamamatsu_S13360-30CS +SiPM, 2pin +Hamamatsu SiPM +0 +2 +2 +OptoDevice +Kingbright_KPS-5130 +http://www.kingbright.com/attachments/file/psearch/000/00/00/KPS-5130PD7C(Ver.14).pdf +KPS-5130 photodiode RGB sensor +0 +4 +4 +OptoDevice +Kingbright_KRC011_Horizontal +Subminiature Reflective Optical Sensor, http://www.kingbright.com/attachments/file/psearch/000/00/00/KRC011(Ver.15).pdf +Subminiature Reflective Optical Sensor +0 +4 +4 +OptoDevice +Kingbright_KRC011_Vertical +Subminiature Reflective Optical Sensor, http://www.kingbright.com/attachments/file/psearch/000/00/00/KRC011(Ver.15).pdf +Subminiature Reflective Optical Sensor +0 +4 +4 +OptoDevice +Kodenshi_LG206D +http://kodenshi.co.jp/products/pdf/sensor/photointerrupter_ic/LG206D.pdf +Photointerrupter infrared LED with photo IC +0 +5 +5 +OptoDevice +Kodenshi_LG206L +http://kodenshi.co.jp/products/pdf/sensor/photointerrupter_ic/LG205L.pdf +Photointerrupter infrared LED with photo IC +0 +5 +5 +OptoDevice +Kodenshi_SG105 +package for Kodenshi SG-105 with PCB cutout, light-direction upwards, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105.pdf +refective opto couple photo coupler +0 +4 +4 +OptoDevice +Kodenshi_SG105F +package for Kodenshi SG-105F, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105F.pdf +refective opto couple photo coupler +0 +4 +4 +OptoDevice +Kodenshi_SG105_Reverse +package for Kodenshi SG-105 with PCB cutout, light-direction downwards, see http://www.kodenshi.co.jp/products/pdf/sensor/photointerrupter_ref/SG-105.pdf +refective opto couple photo coupler +0 +4 +4 +OptoDevice +LaserDiode_TO3.3-D3.3-3 +Laser Diode, TO-3.3mm, 3pin +Laser Diode TO3.3 +0 +3 +3 +OptoDevice +LaserDiode_TO5-D9-3 +Laser Diode, TO5-like (D=9mm), 3pin +Laser Diode TO5-like +0 +3 +3 +OptoDevice +LaserDiode_TO18-D5.6-3 +Laser Diode, TO18-like (D=5.6mm), 3pin +Laser Diode TO18-like +0 +3 +3 +OptoDevice +LaserDiode_TO38ICut-3 +Laser Diode, TO-38-ICut, 3pin +Laser Diode TO38-ICut +0 +3 +3 +OptoDevice +LaserDiode_TO56-3 +Laser Diode, TO-56, 3pin +Laser Diode TO56 +0 +3 +3 +OptoDevice +Lightpipe_LPF-C012303S +https://www.lumex.com/spec/LPF-C012303S.pdf +lightpipe dual tower right angle 3mm +0 +0 +0 +OptoDevice +Lightpipe_Mentor_1276.1004 +https://www.mentor-bauelemente.de/katalog/ll/MENTOR-LL.pdf +spherical light pipe 4 way 3mm PLCC-2 PLCC-4 +0 +0 +0 +OptoDevice +Lightpipe_Mentor_1276.2004 +https://www.mentor-bauelemente.de/katalog/ll/MENTOR-LL.pdf +planar light pipe 4 way 3mm PLCC-2 PLCC-4 +0 +0 +0 +OptoDevice +Lite-On_LTR-303ALS-01 +ambient light sensor, i2c interface, 6-pin chipled package, http://optoelectronics.liteon.com/upload/download/DS86-2013-0004/LTR-303ALS-01_DS_V1.pdf +ambient light sensor chipled +0 +6 +6 +OptoDevice +Luna_NSL-32 +Optoisolator with LED and photoresistor +optoisolator +0 +4 +4 +OptoDevice +Maxim_OLGA-14_3.3x5.6mm_P0.8mm +https://pdfserv.maximintegrated.com/land_patterns/90-0602.PDF +OLGA-14 OESIP-14 +0 +14 +14 +OptoDevice +ONSemi_QSE15x +3 Lead Plastic Package +ONSemi QSE158 QSE159 +0 +3 +3 +OptoDevice +OnSemi_CASE100CY +OnSemi CASE 100CY, light-direction upwards, see http://www.onsemi.com/pub/Collateral/QRE1113-D.PDF +refective opto couple photo coupler +0 +4 +4 +OptoDevice +Osram_BPW82 +PhotoDiode, BPW82, RM2.54 +PhotoDiode BPW82 RM2.54 +0 +2 +2 +OptoDevice +Osram_DIL2_4.3x4.65mm_P5.08mm +PhotoDiode, plastic DIL, 4.3x4.65mm², RM5.08 +PhotoDiode plastic DIL RM5.08 +0 +2 +2 +OptoDevice +Osram_LPT80A +PhotoTransistor, sidelooker package, RM2.54 +PhotoTransistor sidelooker package RM2.54 +0 +2 +2 +OptoDevice +Osram_SFH9x0x +package for Osram SFH9x0x series of reflective photo interrupters/couplers, see http://www.osram-os.com/Graphics/XPic6/00200860_0.pdf +reflective photo interrupter SMD +0 +6 +6 +OptoDevice +Osram_SFH205 +PhotoDiode, SFH205, RM2.54 +PhotoDiode SFH205 RM2.54 +0 +2 +2 +OptoDevice +Osram_SFH225 +PhotoDiode, SFH225, RM2.54 +PhotoDiode SFH225 RM2.54 +0 +2 +2 +OptoDevice +Osram_SMD-DIL2_4.5x4.0mm +PhotoDiode, plastic SMD DIL, 4.5x4mm² +PhotoDiode plastic SMD DIL +0 +2 +2 +OptoDevice +Osram_SMD-SmartDIL +PhotoDiode, plastic SMD SmatDIL +PhotoDiode plastic SMD SmatDIL +0 +3 +3 +OptoDevice +Panasonic_APV-AQY_SSOP-4_4.45x2.65mm_P1.27mm +https://www.panasonic-electric-works.com/cps/rde/xbcr/pew_eu_en/technical_information_photomos_en.pdf +SSOP4 APV21 AQY22 +0 +4 +4 +OptoDevice +PerkinElmer_VTL5C +Axial Vactrol (http://www.qsl.net/wa1ion/vactrol/vactrol.pdf) +vactrol +0 +4 +4 +OptoDevice +PerkinElmer_VTL5Cx2 +Axial Vactrol (http://www.qsl.net/wa1ion/vactrol/vactrol.pdf) +vactrol +0 +5 +5 +OptoDevice +R_LDR_4.9x4.2mm_P2.54mm_Vertical +Resistor, LDR 4.9x4.2mm +Resistor LDR4.9x4.2 +0 +2 +2 +OptoDevice +R_LDR_5.0x4.1mm_P3mm_Vertical +Resistor, LDR 5x4.1mm, see http://cdn-reichelt.de/documents/datenblatt/A500/A90xxxx%23PE.pdf +Resistor LDR5x4.1mm +0 +2 +2 +OptoDevice +R_LDR_5.1x4.3mm_P3.4mm_Vertical +Resistor, LDR 5.1x3.4mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf +Resistor LDR5.1x3.4mm +0 +2 +2 +OptoDevice +R_LDR_5.2x5.2mm_P3.5mm_Horizontal +Resistor, LDR 5.2x5.2, upright, see http://cdn-reichelt.de/documents/datenblatt/A500/M996011A.pdf +Resistor LDR5.2x5.2 +0 +2 +2 +OptoDevice +R_LDR_7x6mm_P5.1mm_Vertical +Resistor, LDR 7x6mm +Resistor LDR7x6mm +0 +2 +2 +OptoDevice +R_LDR_10x8.5mm_P7.6mm_Vertical +Resistor, LDR 10x8.5mm +Resistor LDR10.8.5mm +0 +2 +2 +OptoDevice +R_LDR_11x9.4mm_P8.2mm_Vertical +Resistor, LDR 11x9.4mm +Resistor LDR11x9.4mm +0 +2 +2 +OptoDevice +R_LDR_12x10.8mm_P9.0mm_Vertical +Resistor, LDR 12x10.8mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf +Resistor LDR12x10.8mm +0 +2 +2 +OptoDevice +R_LDR_D6.4mm_P3.4mm_Vertical +Resistor, LDR D=6.4mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf +Resistor LDRD=6.4mm +0 +2 +2 +OptoDevice +R_LDR_D13.8mm_P9.0mm_Vertical +Resistor, diameter 13.8mm pitch 9mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf +Resistor LDR +0 +2 +2 +OptoDevice +R_LDR_D20mm_P17.5mm_Vertical +Resistor, LDR 20mm diameter, pin pitch 17.5mm, see http://yourduino.com/docs/Photoresistor-5516-datasheet.pdf +Resistor LDR +0 +2 +2 +OptoDevice +ST_VL53L0X +https://www.st.com/resource/en/datasheet/vl53l1x.pdf +laser-ranging sensor +0 +12 +12 +OptoDevice +ST_VL53L1X +https://www.st.com/resource/en/datasheet/vl53l1x.pdf +laser-ranging sensor +0 +12 +12 +OptoDevice +Sharp_GP2Y0A41SK0F +http://www.sharp-world.com/products/device/lineup/data/pdf/datasheet/gp2y0a41sk_e.pdf +Distance Sensor Sharp +0 +2 +2 +OptoDevice +Sharp_IS471F +Sharp OPIC IS471F, see http://pdf.datasheetcatalog.com/datasheet/Sharp/mXvrzty.pdf +Sharp OPIC IS471F +0 +4 +4 +OptoDevice +Sharp_IS485 +Sharp OPIC, IS485, IS486, see http://microrato.ua.pt/main/Actividades/Estagios/Docs/IS485_6.pdf +Sharp OPIC IS485 IS486 +0 +3 +3 +OptoDevice +Siemens_SFH900 +package for Siemens SFH900 reflex photo interrupter/coupler/object detector, see https://www.batronix.com/pdf/sfh900.pdf +Siemens SFH900 reflex photo interrupter coupler object detector +0 +3 +3 +OptoDevice +Toshiba_TORX170_TORX173_TORX193_TORX194 +Fiberoptic Reciver, RX, Toshiba, Toslink, TORX170, TORX173, TORX193, TORX194 +Fiberoptic Reciver RX Toshiba Toslink TORX170 TORX173 TORX193 TORX194 +0 +6 +6 +OptoDevice +Toshiba_TOTX170_TOTX173_TOTX193_TOTX194 +Fiberoptic Reciver, RX, Toshiba, Toslink, TORX170, TORX173, TORX193, TORX194 +Fiberoptic Reciver RX Toshiba Toslink TORX170 TORX173 TORX193 TORX194 +0 +6 +6 +OptoDevice +Vishay_CAST-3Pin +IR Receiver Vishay TSOP-xxxx, CAST package, see https://www.vishay.com/docs/82493/tsop311.pdf +IRReceiverVishayTSOP-xxxx CAST +0 +3 +3 +OptoDevice +Vishay_CNY70 +package for Vishay CNY70 refective photo coupler/interrupter +Vishay CNY70 refective photo coupler +0 +4 +4 +OptoDevice +Vishay_MINICAST-3Pin +IR Receiver Vishay TSOP-xxxx, MINICAST package, see https://www.vishay.com/docs/82669/tsop32s40f.pdf +IR Receiver Vishay TSOP-xxxx MINICAST +0 +3 +3 +OptoDevice +Vishay_MINIMOLD-3Pin +IR Receiver Vishay TSOP-xxxx, MINIMOLD package, see https://www.vishay.com/docs/82742/tsop331.pdf +IR Receiver Vishay TSOP-xxxx MINIMOLD +0 +3 +3 +OptoDevice +Vishay_MOLD-3Pin +IR Receiver Vishay TSOP-xxxx, MOLD package, see https://www.vishay.com/docs/82669/tsop32s40f.pdf +IR Receiver Vishay TSOP-xxxx MOLD +0 +3 +3 +Oscillator +Oscillator_DIP-8 +Oscillator, DIP8,http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf +oscillator +0 +4 +4 +Oscillator +Oscillator_DIP-8_LargePads +Oscillator, DIP8, Large Pads, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf +oscillator +0 +4 +4 +Oscillator +Oscillator_DIP-14 +Oscillator, DIP14, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf +oscillator +0 +4 +4 +Oscillator +Oscillator_DIP-14_LargePads +Oscillator, DIP14, Large Pads, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf +oscillator +0 +4 +4 +Oscillator +Oscillator_OCXO_Morion_MV267 +http://www.morion.com.ru/catalog_pdf/MV267.pdf +OCXO +0 +5 +5 +Oscillator +Oscillator_OCXO_Morion_MV317 +https://www.morion-us.com/catalog_pdf/mv317.pdf +OCXO +0 +5 +5 +Oscillator +Oscillator_SMD_Abracon_ABLNO +https://abracon.com/Precisiontiming/ABLNO.pdf +VCXO XO +0 +4 +4 +Oscillator +Oscillator_SMD_Abracon_ASCO-4Pin_1.6x1.2mm +Miniature Crystal Clock Oscillator Abracon ASCO series, https://abracon.com/Oscillators/ASCO.pdf, 1.6x1.2mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Abracon_ASDMB-4Pin_2.5x2.0mm +Miniature Crystal Clock Oscillator Abracon ASDMB series, 2.5x2.0mm package, http://www.abracon.com/Oscillators/ASDMB.pdf +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm +Miniature Crystal Clock Oscillator Abracon ASE series, http://www.abracon.com/Oscillators/ASEseries.pdf, 3.2x2.5mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm_HandSoldering +Miniature Crystal Clock Oscillator Abracon ASE series, http://www.abracon.com/Oscillators/ASEseries.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Abracon_ASV-4Pin_7.0x5.1mm +Miniature Crystal Clock Oscillator Abracon ASV series, http://www.abracon.com/Oscillators/ASV.pdf, 7.0x5.1mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Abracon_ASV-4Pin_7.0x5.1mm_HandSoldering +Miniature Crystal Clock Oscillator Abracon ASV series, http://www.abracon.com/Oscillators/ASV.pdf, hand-soldering, 7.0x5.1mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Diodes_FN-4Pin_7.0x5.0mm +FN Series Crystal Clock Oscillator (XO) (https://www.diodes.com/assets/Datasheets/FN_3-3V.pdf) +Oscillator Crystal SMD SMT +0 +4 +4 +Oscillator +Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm +Miniature Crystal Clock Oscillator ECS 2520MV series, https://www.ecsxtal.com/store/pdf/ECS-2520MV.pdf +Miniature Crystal Clock Oscillator ECS 2520MV series SMD SMT HCMOS +0 +4 +4 +Oscillator +Oscillator_SMD_EuroQuartz_XO32-4Pin_3.2x2.5mm +Miniature Crystal Clock Oscillator EuroQuartz XO32 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO32.pdf, 3.2x2.5mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_EuroQuartz_XO32-4Pin_3.2x2.5mm_HandSoldering +Miniature Crystal Clock Oscillator EuroQuartz XO32 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO32.pdf, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_EuroQuartz_XO53-4Pin_5.0x3.2mm +Miniature Crystal Clock Oscillator EuroQuartz XO53 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO53.pdf, 5.0x3.2mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_EuroQuartz_XO53-4Pin_5.0x3.2mm_HandSoldering +Miniature Crystal Clock Oscillator EuroQuartz XO53 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO53.pdf, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_EuroQuartz_XO91-4Pin_7.0x5.0mm +Miniature Crystal Clock Oscillator EuroQuartz XO91 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO91.pdf, 7.0x5.0mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_EuroQuartz_XO91-4Pin_7.0x5.0mm_HandSoldering +Miniature Crystal Clock Oscillator EuroQuartz XO91 series, http://cdn-reichelt.de/documents/datenblatt/B400/XO91.pdf, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS1-6Pin_14.8x9.1mm +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S1-KHZ/LHZ, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 14.8x9.1mm^2 package +SMD SMT crystal oscillator +0 +6 +6 +Oscillator +Oscillator_SMD_Fordahl_DFAS2-4Pin_7.3x5.1mm +Mminiature Crystal Clock Oscillator TXCO Fordahl DFA S2-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.3x5.1mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS2-4Pin_7.3x5.1mm_HandSoldering +Mminiature Crystal Clock Oscillator TXCO Fordahl DFA S2-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.3x5.1mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS3-4Pin_9.1x7.2mm +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S3-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 9.1x7.2mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS3-4Pin_9.1x7.2mm_HandSoldering +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S3-KS/LS/US, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 9.1x7.2mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS7-4Pin_19.9x12.9mm +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S7-K/L, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 19.9x12.9mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS7-4Pin_19.9x12.9mm_HandSoldering +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S7-K/L, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 19.9x12.9mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS11-4Pin_7.0x5.0mm +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.0x5.0mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS11-4Pin_7.0x5.0mm_HandSoldering +Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS15-4Pin_5.0x3.2mm +Ultraminiature Crystal Clock Oscillator TXCO Fordahl DFA S15-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 5.0x3.2mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_Fordahl_DFAS15-4Pin_5.0x3.2mm_HandSoldering +Ultraminiature Crystal Clock Oscillator TXCO Fordahl DFA S15-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_IDT_JS6-6_5.0x3.2mm_P1.27mm +SMD Crystal Oscillator IDT https://www.idt.com/document/dst/xu-family-datasheet#page=15, 5.0x3.2mm +SMD SMT crystal oscillator +0 +6 +6 +Oscillator +Oscillator_SMD_IDT_JU6-6_7.0x5.0mm_P2.54mm +SMD Crystal Oscillator IDT https://www.idt.com/document/dst/xu-family-datasheet#page=17, 7.0x5.0mm +SMD SMT crystal oscillator +0 +6 +6 +Oscillator +Oscillator_SMD_IQD_IQXO70-4Pin_7.5x5.0mm +IQD Crystal Clock Oscillator IQXO-70, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, 7.5x5.0mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_IQD_IQXO70-4Pin_7.5x5.0mm_HandSoldering +IQD Crystal Clock Oscillator IQXO-70, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 7.5x5.0mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Kyocera_2520-6Pin_2.5x2.0mm +https://global.kyocera.com/prdct/electro/product/pdf/kt2520_e.pdf +2.5mm 2mm SMD +0 +6 +6 +Oscillator +Oscillator_SMD_OCXO_ConnorWinfield_OH300 +http://www.conwin.com/datasheets/cx/cx282.pdf +OCXO +0 +7 +7 +Oscillator +Oscillator_SMD_SI570_SI571_HandSoldering +SI570, SI571, Programmable oscillator, Standard +SI570 SI571 Programmable oscillator Standard +0 +8 +8 +Oscillator +Oscillator_SMD_SI570_SI571_Standard +SI570, SI571, Programmable oscillator, Standard +SI570 SI571 Programmable oscillator Standard +0 +8 +8 +Oscillator +Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm +SMD Crystal Oscillator Seiko Epson SG-210 https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-210SED, 2.5x2.0mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm_HandSoldering +SMD Crystal Oscillator Seiko Epson SG-210 https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-210SED, hand-soldering, 2.5x2.0mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG3030CM +SMD Crystal Oscillator Seiko Epson SG-3030CM package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002CA-4Pin_7.0x5.0mm +SMD Crystal Oscillator Seiko Epson SG-8002CA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 7.0x5.0mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002CA-4Pin_7.0x5.0mm_HandSoldering +SMD Crystal Oscillator Seiko Epson SG-8002CA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 7.0x5.0mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm +SMD Crystal Oscillator Seiko Epson SG-8002CE https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 3.2x2.5mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002CE-4Pin_3.2x2.5mm_HandSoldering +SMD Crystal Oscillator Seiko Epson SG-8002CE https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 3.2x2.5mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002JA-4Pin_14.0x8.7mm +SMD Crystal Oscillator Seiko Epson SG-8002JA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 14.0x8.7mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002JA-4Pin_14.0x8.7mm_HandSoldering +SMD Crystal Oscillator Seiko Epson SG-8002JA https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 14.0x8.7mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002JC-4Pin_10.5x5.0mm +SMD Crystal Oscillator Seiko Epson SG-8002JC https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 10.5x5.0mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002JC-4Pin_10.5x5.0mm_HandSoldering +SMD Crystal Oscillator Seiko Epson SG-8002JC https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 10.5x5.0mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002LB-4Pin_5.0x3.2mm +SMD Crystal Oscillator Seiko Epson SG-8002LB https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, 5.0x3.2mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_SeikoEpson_SG8002LB-4Pin_5.0x3.2mm_HandSoldering +SMD Crystal Oscillator Seiko Epson SG-8002LB https://support.epson.biz/td/api/doc_check.php?mode=dl&lang=en&Parts=SG-8002DC, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SMD_Silicon_Labs_LGA-6_2.5x3.2mm_P1.25mm +Silicon_Labs LGA, 6 Pin (https://www.silabs.com/documents/public/data-sheets/si512-13.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +Silicon_Labs LGA NoLead +0 +6 +6 +Oscillator +Oscillator_SMD_TCXO_G158 +TCXO +TCXO +0 +4 +4 +Oscillator +Oscillator_SMD_TXC_7C-4Pin_5.0x3.2mm +Miniature Crystal Clock Oscillator TXC 7C series, http://www.txccorp.com/download/products/osc/7C_o.pdf, 5.0x3.2mm^2 package +SMD SMT crystal oscillator +0 +4 +4 +Oscillator +Oscillator_SMD_TXC_7C-4Pin_5.0x3.2mm_HandSoldering +Miniature Crystal Clock Oscillator TXC 7C series, http://www.txccorp.com/download/products/osc/7C_o.pdf, hand-soldering, 5.0x3.2mm^2 package +SMD SMT crystal oscillator hand-soldering +0 +4 +4 +Oscillator +Oscillator_SeikoEpson_SG-8002DB +14-lead dip package, row spacing 7.62 mm (300 mils) +DIL DIP PDIP 2.54mm 7.62mm 300mil +0 +4 +4 +Oscillator +Oscillator_SeikoEpson_SG-8002DC +8-lead dip package, row spacing 7.62 mm (300 mils) +DIL DIP PDIP 2.54mm 7.62mm 300mil +0 +4 +4 +Package_BGA +Analog_BGA-28_4.0x6.25mm_Layout4x7_P0.8mm_Ball0.45mm_Pad0.4 +Analog BGA-28 4.0mm x 6.25mm package, pitch 0.4mm pad, based on https://www.analog.com/media/en/technical-documentation/data-sheets/8063fa.pdf +BGA 28 0.8 +0 +28 +28 +Package_BGA +BGA-9_1.6x1.6mm_Layout3x3_P0.5mm +BGA-9, http://www.ti.com/lit/ds/symlink/bq27421-g1.pdf +BGA-9 +0 +9 +9 +Package_BGA +BGA-16_1.92x1.92mm_Layout4x4_P0.5mm +BGA-16, http://www.st.com/content/ccc/resource/technical/document/datasheet/group2/bc/cd/62/9e/8f/30/47/69/CD00151267/files/CD00151267.pdf/jcr:content/translations/en.CD00151267.pdf +BGA-16 +0 +16 +16 +Package_BGA +BGA-25_6.35x6.35mm_Layout5x5_P1.27mm +BGA-25, http://cds.linear.com/docs/en/datasheet/4624fc.pdf +BGA-25 uModule +0 +25 +25 +Package_BGA +BGA-36_3.396x3.466mm_Layout6x6_P0.4mm_Ball0.25mm_Pad0.2mm_NSMD +Altera V36, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00486-00.pdf +Altera BGA-36 V36 VBGA +0 +36 +36 +Package_BGA +BGA-48_8.0x9.0mm_Layout6x8_P0.8mm +BGA-48 - pitch 0.8 mm +BGA-48 +0 +48 +48 +Package_BGA +BGA-64_9.0x9.0mm_Layout10x10_P0.8mm +BGA-64, 10x10 raster, 9x9mm package, pitch 0.8mm +BGA-64 +0 +64 +64 +Package_BGA +BGA-68_5.0x5.0mm_Layout9x9_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD +Altera MBGA-68, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00344-01.pdf +Altera BGA-68 M68 MBGA +0 +68 +68 +Package_BGA +BGA-81_4.496x4.377mm_Layout9x9_P0.4mm_Ball0.25mm_Pad0.2mm_NSMD +Altera V81, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00478-01.pdf +Altera VBGA V81 BGA-81 +0 +81 +81 +Package_BGA +BGA-90_8.0x13.0mm_Layout2x3x15_P0.8mm +BGA-90, http://www.issi.com/WW/pdf/42-45S32800J.pdf +BGA-90 +0 +90 +90 +Package_BGA +BGA-96_9.0x13.0mm_Layout2x3x16_P0.8mm +BGA-96, http://www.mouser.com/ds/2/198/43-46TR16640B-81280BL-706483.pdf +BGA-96 +0 +96 +96 +Package_BGA +BGA-100_6.0x6.0mm_Layout11x11_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD +Altera MBGA-100, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00345-01.pdf +Altera BGA-100 M100 MBGA +0 +100 +100 +Package_BGA +BGA-100_11.0x11.0mm_Layout10x10_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD +BGA-100, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00223-02.pdf +BGA-100 +0 +100 +100 +Package_BGA +BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD +121-ball, 0.8mm BGA (based on http://www.latticesemi.com/view_document?document_id=213) +BGA 0.8mm 9mm 121 +0 +121 +121 +Package_BGA +BGA-121_12.0x12.0mm_Layout11x11_P1.0mm +BGA-121, http://cds.linear.com/docs/en/packaging/05081891_A_bga121.pdf +BGA-121 +0 +121 +121 +Package_BGA +BGA-132_12x18mm_Layout11x17_P0.5mm +BGA-132 11x17 12x18mm 0.5pitch +BGA-132 +0 +132 +132 +Package_BGA +BGA-144_7.0x7.0mm_Layout13x13_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD +Altera MBGA-144, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00346-00.pdf +Altera BGA-144 M144 MBGA +0 +144 +144 +Package_BGA +BGA-144_13.0x13.0mm_Layout12x12_P1.0mm +BGA-144, http://www.topline.tv/drawings/pdf/BGA%201,0mm%20pitch/LBGA144T1.0-DC128.pdf +BGA-144 +0 +144 +144 +Package_BGA +BGA-152_14x18mm_Layout13x17_P0.5mm +BGA-152_14x18mm_Layout13x17_P0.5mm +VBGA-152 +0 +152 +152 +Package_BGA +BGA-153_8.0x8.0mm_Layout15x15_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD +Altera MBGA-153, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00471-00.pdf +Altera BGA-153 M153 MBGA +0 +153 +153 +Package_BGA +BGA-169_11.0x11.0mm_Layout13x13_P0.8mm_Ball0.5mm_Pad0.4mm_NSMD +Altera U169, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00470-01.pdf +Altera UBGA U169 BGA-169 +0 +169 +169 +Package_BGA +BGA-256_11.0x11.0mm_Layout20x20_P0.5mm_Ball0.3mm_Pad0.25mm_NSMD +Altera MBGA-256, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00348-01.pdf +Altera BGA-256 M256 MBGA +0 +256 +256 +Package_BGA +BGA-256_14.0x14.0mm_Layout16x16_P0.8mm_Ball0.45mm_Pad0.32mm_NSMD +BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf +BGA-256 +0 +256 +256 +Package_BGA +BGA-256_17.0x17.0mm_Layout16x16_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD +BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf +BGA-256 +0 +256 +256 +Package_BGA +BGA-324_15.0x15.0mm_Layout18x18_P0.8mm_Ball0.5mm_Pad0.4mm_NSMD +Altera U324, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00474-02.pdf +Altera UBGA U324 BGA-324 +0 +324 +324 +Package_BGA +BGA-324_19.0x19.0mm_Layout18x18_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD +BGA-324, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00233-03.pdf +BGA-324 +0 +324 +324 +Package_BGA +BGA-352_35.0x35.0mm_Layout26x26_P1.27mm +BGA-352, https://www.fujitsu.com/downloads/MICRO/fma/pdfmcu/b352p05.pdf +BGA-352 +0 +352 +352 +Package_BGA +BGA-400_21.0x21.0mm_Layout20x20_P1.0mm +BGA-400, https://www.xilinx.com/support/documentation/package_specs/fg400.pdf +BGA-400 +0 +400 +400 +Package_BGA +BGA-484_23.0x23.0mm_Layout22x22_P1.0mm +BGA-484, https://www.xilinx.com/support/documentation/package_specs/fg484.pdf +BGA-484 +0 +484 +484 +Package_BGA +BGA-624_21.0x21.0mm_Layout25x25_P0.8mm +BGA-624, 25x25 grid, 21x21mm package, pitch 0.8mm; https://www.nxp.com/docs/en/package-information/SOT1529-1.pdf +BGA 624 0.8 +0 +624 +624 +Package_BGA +BGA-625_21.0x21.0mm_Layout25x25_P0.8mm +BGA-625 +BGA-625 +0 +625 +625 +Package_BGA +BGA-672_27.0x27.0mm_Layout26x26_P1.0mm_Ball0.6mm_Pad0.5mm_NSMD +Altera BGA-672, https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/packaging/04r00472-00.pdf +Altera BGA-672 F672 FBGA +0 +672 +672 +Package_BGA +BGA-676_27.0x27.0mm_Layout26x26_P1.0mm_Ball0.6mm_Pad0.5mm_NSMD +XILINX BGA-676, https://www.xilinx.com/support/documentation/package_specs/fg676.pdf +XILINX BGA-676 FG676/FGG676 +0 +676 +676 +Package_BGA +BGA-1023_33.0x33.0mm_Layout32x32_P1.0mm +BGA-1023 +BGA-1023 +0 +1023 +1023 +Package_BGA +BGA-1156_35.0x35.0mm_Layout34x34_P1.0mm +BGA-1156 +BGA-1156 +0 +1156 +1156 +Package_BGA +BGA-1295_37.5x37.5mm_Layout36x36_P1.0mm +BGA-1295 +BGA-1295 +0 +1295 +1295 +Package_BGA +FB-BGA-484_23.0x23.0mm_Layout22x22_P1.0mm +Xilinx FB-484, https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf +FB-BGA-484 +0 +484 +484 +Package_BGA +FBGA-78_7.5x11mm_Layout2x3x13_P0.8mm +FBGA-78, https://www.skhynix.com/product/filedata/fileDownload.do?seq=7687 +FBGA-78 +0 +78 +78 +Package_BGA +Fujitsu_WLP-15_2.28x3.092mm_Layout3x5_P0.4mm +WLP-15, 3x5 raster, 2.28x3.092mm package, pitch 0.4mm; http://www.fujitsu.com/global/documents/products/devices/semiconductor/fram/lineup/MB85RS1MT-DS501-00022-7v0-E.pdf +BGA 8 0.4 +0 +8 +8 +Package_BGA +LFBGA-100_10x10mm_Layout10x10_P0.8mm +LFBGA-100, 10x10 raster, 10x10mm package, pitch 0.8mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf +BGA 100 0.8 +0 +100 +100 +Package_BGA +LFBGA-144_10x10mm_Layout12x12_P0.8mm +LFBGA-144, 12x12 raster, 10x10mm package, pitch 0.8mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf +BGA 144 0.8 +0 +144 +144 +Package_BGA +LFBGA-169_16x12mm_Layout28x14_P0.5mm_Ball0.3_Pad0.3mm_NSMD +https://4donline.ihs.com/images/VipMasterIC/IC/SGST/SGSTS20279/SGSTS20279-1.pdf?hkey=EF798316E3902B6ED9A73243A3159BB0 +eMMC Flash LFBGA169 +0 +169 +169 +Package_BGA +Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD +Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213 +BGA 381 0.8 +0 +381 +381 +Package_BGA +Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.6mm_SMD +Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213 +BGA 381 0.8 +0 +381 +381 +Package_BGA +Linear_BGA-133_15.0x15.0_Layout12x12_P1.27mm +Analog Devices (Linear Tech), 133-pin BGA uModule, 15.0x15.0x4.92mm, https://www.analog.com/media/en/technical-documentation/data-sheets/4637fc.pdf +133 pin bga +0 +134 +134 +Package_BGA +Maxim_WLP-12 +Maxim_WLP-12 W121B2+1 http://pdfserv.maximintegrated.com/package_dwgs/21-0009.PDF +Maxim_WLP-12 +0 +12 +12 +Package_BGA +TFBGA-64_5x5mm_Layout8x8_P0.5mm +TFBGA-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f100v8.pdf +BGA 64 0.5 +0 +64 +64 +Package_BGA +TFBGA-100_8x8mm_Layout10x10_P0.8mm +TFBGA-100, 10x10 raster, 8x8mm package, pitch 0.8mm; see section 6.2 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf +BGA 100 0.8 +0 +100 +100 +Package_BGA +TFBGA-100_9.0x9.0mm_Layout10x10_P0.8mm +TFBGA-100, 10x10, 9x9mm package, pitch 0.8mm +TFBGA-100 +0 +100 +100 +Package_BGA +TFBGA-121_10x10mm_Layout11x11_P0.8mm +TFBGA-121, 11x11 raster, 10x10mm package, pitch 0.8mm; http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#p495 +BGA 121 0.8 +0 +121 +121 +Package_BGA +TFBGA-216_13x13mm_Layout15x15_P0.8mm +TFBGA-216, 15x15 raster, 13x13mm package, pitch 0.8mm; see section 6.8 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf +BGA 216 0.8 +0 +216 +216 +Package_BGA +TFBGA-265_14x14mm_Layout17x17_P0.8mm +TFBGA-265, 17x17 raster, 14x14mm package, pitch 0.8mm; see section 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf +BGA 265 0.8 +0 +265 +265 +Package_BGA +Texas_DSBGA-5_0.822x1.116mm_Layout2x1x2_P0.4mm +Texas Instruments, DSBGA, 0.822x1.116mm, 5 bump 2x1x2 array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/opa330.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +Texas Instruments DSBGA BGA YFF S-XBGA-N5 +0 +10 +5 +Package_BGA +Texas_DSBGA-6_0.9x1.4mm_Layout2x3_P0.5mm +Texas Instruments, DSBGA, 0.9x1.4mm, 6 bump 2x3 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/ts5a3159a.pdf) +Texas Instruments DSBGA BGA YZP R-XBGA-N6 +0 +12 +6 +Package_BGA +Texas_DSBGA-8_0.9x1.9mm_Layout2x4_P0.5mm +Texas Instruments, DSBGA, 0.9x1.9mm, 8 bump 2x4 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0102.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +Texas Instruments DSBGA BGA YZP R-XBGA-N8 +0 +16 +8 +Package_BGA +Texas_DSBGA-8_1.43x1.41mm_Layout3x3_P0.5mm +Texas Instruments, DSBGA, 1.43x1.41mm, 8 bump 3x3 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lmc555.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +Texas Instruments DSBGA BGA YZP R-XBGA-N8 +0 +16 +8 +Package_BGA +Texas_DSBGA-8_1.5195x1.5195mm_Layout3x3_P0.5mm +Texas Instruments, DSBGA, 1.5195x1.5195x0.600mm, 8 ball 3x3 area grid, YZR pad definition (http://www.ti.com/lit/ml/mxbg270/mxbg270.pdf) +BGA 8 0.5 +0 +8 +8 +Package_BGA +Texas_DSBGA-9_1.4715x1.4715mm_Layout3x3_P0.5mm +Texas Instruments, DSBGA, 1.4715x1.4715mm, 9 bump 3x3 array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lm4990.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +Texas Instruments DSBGA BGA YZR0009 +0 +18 +9 +Package_BGA +Texas_DSBGA-10_1.36x1.86mm_Layout3x4_P0.5mm +Texas Instruments, DSBGA, 1.36x1.86mm, 10 bump 3x4 (perimeter) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +Texas Instruments DSBGA BGA +0 +20 +10 +Package_BGA +Texas_DSBGA-12_1.36x1.86mm_Layout3x4_P0.5mm +Texas Instruments, DSBGA, 1.36x1.86mm, 12 bump 3x4 (area) array, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txs0104e.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +Texas Instruments DSBGA BGA +0 +24 +12 +Package_BGA +Texas_DSBGA-28_1.9x3.0mm_Layout4x7_P0.4mm +Texas Instruments, DSBGA, 3.0x1.9x0.625mm, 28 ball 7x4 area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/bq51050b.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +BGA 28 0.4 +0 +28 +28 +Package_BGA +Texas_DSBGA-49_3.33x3.488mm_Layout7x7_P0.4mm +Texas Instruments, DSBGA, 3.33x3.488x0.625mm, 49 ball 7x7 area grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/msp430f2234.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +texas dsbga 49 +0 +49 +49 +Package_BGA +Texas_DSBGA-64_3.415x3.535mm_Layout8x8_P0.4mm +Texas Instruments, DSBGA, 3.415x3.535x0.625mm, 64 ball 8x8 area grid, NSMD pad definition (http://www.ti.com/lit/ds/slas718g/slas718g.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf) +texas dsbga 64 +0 +64 +64 +Package_BGA +Texas_MicroStar_Junior_BGA-12_2.0x2.5mm_Layout4x3_P0.5mm +Texas Instruments, BGA Microstar Junior, 2x2.5mm, 12 bump 4x3 grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf) +Texas_Junior_BGA-12 +0 +12 +12 +Package_BGA +Texas_MicroStar_Junior_BGA-80_5.0x5.0mm_Layout9x9_P0.5mm +Texas Instruments, BGA Microstar Junior, 5x5mm, 80 ball 9x9 grid, NSMD pad definition (http://www.ti.com/lit/ds/symlink/tlv320aic23b.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf) +Texas_Junior_BGA-80 +0 +80 +80 +Package_BGA +Texas_MicroStar_Junior_BGA-113_7.0x7.0mm_Layout12x12_P0.5mm +Texas Instruments, BGA Microstar Junior, 7x7mm, 113 ball 12x12 grid, NSMD pad definition (http://www.ti.com/lit/ml/mpbg674/mpbg674.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf) +Texas_Junior_BGA-113 +0 +113 +113 +Package_BGA +UCBGA-36_2.5x2.5mm_Layout6x6_P0.4mm +UCBGA-36, 6x6 raster, 2.5x2.5mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 +BGA 36 0.4 +0 +36 +36 +Package_BGA +UCBGA-49_3x3mm_Layout7x7_P0.4mm +UCBGA-49, 7x7 raster, 3x3mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 +BGA 49 0.4 +0 +49 +49 +Package_BGA +UCBGA-81_4x4mm_Layout9x9_P0.4mm +UCBGA-81, 9x9 raster, 4x4mm package, pitch 0.4mm; https://www.latticesemi.com/view_document?document_id=213 +BGA 81 0.4 +0 +81 +81 +Package_BGA +UFBGA-15_3.0x3.0mm_Layout4x4_P0.65mm +UFBGA-15, 4x4, 3x3mm package, pitch 0.65mm +UFBGA-15 +0 +15 +15 +Package_BGA +UFBGA-32_4.0x4.0mm_Layout6x6_P0.5mm +UFBGA-32, 6x6, 4x4mm package, pitch 0.5mm +UFBGA-32 +0 +32 +32 +Package_BGA +UFBGA-64_5x5mm_Layout8x8_P0.5mm +UFBGA-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf +BGA 64 0.5 +0 +64 +64 +Package_BGA +UFBGA-100_7x7mm_Layout12x12_P0.5mm +UFBGA-100, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf +BGA 100 0.5 +0 +100 +100 +Package_BGA +UFBGA-132_7x7mm_Layout12x12_P0.5mm +UFBGA-132, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf +BGA 132 0.5 +0 +132 +132 +Package_BGA +UFBGA-132_7x7mm_P0.5mm +UFBGA 132 Pins, 0.5mm Pitch, 0.3mm Ball, http://www.st.com/resource/en/datasheet/stm32l486qg.pdf +ufbga bga small-pitch +0 +132 +132 +Package_BGA +UFBGA-144_7x7mm_Layout12x12_P0.5mm +UFBGA-144, 12x12 raster, 7x7mm package, pitch 0.5mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf +BGA 144 0.5 +0 +144 +144 +Package_BGA +UFBGA-144_10x10mm_Layout12x12_P0.8mm +UFBGA-144, 12x12 raster, 10x10mm package, pitch 0.8mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf +BGA 144 0.8 +0 +144 +144 +Package_BGA +UFBGA-169_7x7mm_Layout13x13_P0.5mm +UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf +BGA 169 0.5 +0 +169 +169 +Package_BGA +UFBGA-201_10x10mm_Layout15x15_P0.65mm +UFBGA-201, 15x15 raster, 10x10mm package, pitch 0.65mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf +BGA 201 0.65 +0 +201 +201 +Package_BGA +VFBGA-49_5.0x5.0mm_Layout7x7_P0.65mm +VFBGA-49, 7x7, 5x5mm package, pitch 0.65mm +VFBGA-49 +0 +49 +49 +Package_BGA +VFBGA-100_7.0x7.0mm_Layout10x10_P0.65mm +VFBGA-100, 10x10, 7x7mm package, pitch 0.65mm +VFBGA-100 +0 +100 +100 +Package_BGA +WLP-4_0.73x0.73mm_Layout2x2_P0.35mm_Ball0.22mm_Pad0.2mm_NSMD +WLP-4, 2x2 raster, 0.73x0.73mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf +BGA 4 0.35 +0 +4 +4 +Package_BGA +WLP-4_0.83x0.83mm_P0.4mm +WLP-4_0.83x0.83mm_P0.4mm https://pdfserv.maximintegrated.com/package_dwgs/21-100107.PDF, https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891 +WLP-4 +0 +4 +4 +Package_BGA +WLP-4_0.86x0.86mm_P0.4mm +WLP-4_0.86x0.86mm_P0.4mm https://pdfserv.maximintegrated.com/package_dwgs/21-0612.PDF, https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891 +WLP-4 +0 +4 +4 +Package_BGA +XBGA-121_10x10mm_Layout11x11_P0.8mm +XBGA-121, 11x11 raster, 10x10mm package, pitch 0.6mm; http://ww1.microchip.com/downloads/en/DeviceDoc/39969b.pdf +BGA 121 0.8 +0 +121 +121 +Package_BGA +XFBGA-36_3.5x3.5mm_Layout6x6_P0.5mm +XFBGA-36, https://www.nxp.com/docs/en/package-information/SOT1555-1.pdf +XFBGA-36 +0 +36 +36 +Package_BGA +XFBGA-64_5.0x5.0mm_Layout8x8_P0.5mm +XFBGA-64, https://www.nxp.com/docs/en/package-information/SOT1555-1.pdf +XFBGA-64 +0 +64 +64 +Package_BGA +XFBGA-121_8x8mm_Layout11x11_P0.65mm +XFBGA-121, https://www.nxp.com/docs/en/package-information/SOT1533-1.pdf +XFBGA-121 +0 +121 +121 +Package_BGA +Xilinx_CLG225 +Zynq-7000 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=77, NSMD pad definition Appendix A +BGA 225 0.8 CLG225 +0 +225 +225 +Package_BGA +Xilinx_CLG400 +Zynq-7000 BGA, 20x20 grid, 17x17mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=78, NSMD pad definition Appendix A +BGA 400 0.8 CLG400 CL400 +0 +400 +400 +Package_BGA +Xilinx_CLG484_CLG485 +Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=79, NSMD pad definition Appendix A +BGA 484 0.8 CLG484 CL484 CLG485 CL485 +0 +484 +484 +Package_BGA +Xilinx_CPG236 +Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=266, NSMD pad definition Appendix A +BGA 238 0.5 CP236 CPG236 +0 +238 +238 +Package_BGA +Xilinx_CPG238 +Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=267, NSMD pad definition Appendix A +BGA 238 0.5 CPG238 +0 +238 +238 +Package_BGA +Xilinx_CPGA196 +Spartan-7 BGA, 14x14 grid, 8x8mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=260, NSMD pad definition Appendix A +BGA 196 0.5 CPGA196 +0 +196 +196 +Package_BGA +Xilinx_CSG324 +Artix-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A +BGA 324 0.8 CS324 CSG324 +0 +324 +324 +Package_BGA +Xilinx_CSG325 +Artix-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A +BGA 324 0.8 CS325 CSG235 +0 +324 +324 +Package_BGA +Xilinx_CSGA225 +Spartan-7 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=262, NSMD pad definition Appendix A +BGA 225 0.8 CSGA225 +0 +225 +225 +Package_BGA +Xilinx_CSGA324 +Spartan-7 BGA, 18x18 grid, 15x15mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=263, NSMD pad definition Appendix A +BGA 324 0.8 CSGA324 +0 +324 +324 +Package_BGA +Xilinx_FBG484 +Artix-7, Kintex-7 and Zynq-7000 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=271, ttps://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=281, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=82, NSMD pad definition Appendix A +BGA 484 1 FB484 FBG484 FBV484 +0 +484 +484 +Package_BGA +Xilinx_FBG676 +Artix-7, Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=273, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=284, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=84, NSMD pad definition Appendix A +BGA 676 1 FB676 FBG676 FBV676 +0 +676 +676 +Package_BGA +Xilinx_FBG900 +Kintex-7 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=289, NSMD pad definition Appendix A +BGA 900 1 FB900 FBG900 FBV900 +0 +900 +900 +Package_BGA +Xilinx_FFG676 +Kintex-7 and Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=292, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=88, NSMD pad definition Appendix A +BGA 676 1 FF676 FFG676 FFV676 +0 +676 +676 +Package_BGA +Xilinx_FFG900_FFG901 +Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=294, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=90, NSMD pad definition Appendix A +BGA 900 1 FF900 FFG900 FFV900 FF901 FFG901 FFV901 +0 +900 +900 +Package_BGA +Xilinx_FFG1156 +Artix-7, Kintex-7 and Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=277, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=296, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=91, NSMD pad definition Appendix A +BGA 1156 1 FF1156 FFG1156 FFV1156 +0 +1156 +1156 +Package_BGA +Xilinx_FFG1157_FFG1158 +Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=299, NSMD pad definition Appendix A +BGA 1156 1 FF1157 FFG1157 FFV1157 FF1158 FFG1158 FFV1158 +0 +1156 +1156 +Package_BGA +Xilinx_FFG1761 +Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=300, NSMD pad definition Appendix A +BGA 1760 1 FF1761 FFG1761 +0 +1760 +1760 +Package_BGA +Xilinx_FFG1926_FFG1927_FFG1928_FFG1930 +Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=303, NSMD pad definition Appendix A +BGA 1924 1 FF1926 FFG1926 FF1927 FFG1927 FFV1927 FF1928 FFG1928 FF1930 FFG1930 +0 +1924 +1924 +Package_BGA +Xilinx_FFV1761 +Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=301, NSMD pad definition Appendix A +BGA 1760 1 FFV1761 +0 +1760 +1760 +Package_BGA +Xilinx_FGG484 +Artix-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=275, NSMD pad definition Appendix A +BGA 484 1 FG484 FGG484 +0 +484 +484 +Package_BGA +Xilinx_FGG676 +Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=276, NSMD pad definition Appendix A +BGA 676 1 FG676 FGG676 +0 +676 +676 +Package_BGA +Xilinx_FGGA484 +Spartan-7 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=264, NSMD pad definition Appendix A +BGA 484 1 FGGA484 +0 +484 +484 +Package_BGA +Xilinx_FGGA676 +Spartan-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=265, NSMD pad definition Appendix A +BGA 676 1 FGGA676 +0 +676 +676 +Package_BGA +Xilinx_FHG1761 +Virtex-7 BGA, 42x42 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=302, NSMD pad definition Appendix A +BGA 1760 1 FH1761 FHG1761 +0 +1760 +1760 +Package_BGA +Xilinx_FLG1925_FLG1926_FLG1928_FLG1930 +Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=304, NSMD pad definition Appendix A +BGA 1924 1 FL1925 FLG1925 FL1926 FLG1926 FL1928 FLG1928 FL1930 FLG1930 +0 +1924 +1924 +Package_BGA +Xilinx_FTG256 +Artix-7 BGA, 16x16 grid, 17x17mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=269, NSMD pad definition Appendix A +BGA 256 1 FT256 FTG256 +0 +256 +256 +Package_BGA +Xilinx_FTGB196 +Spartan-7 BGA, 14x14 grid, 15x15mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=261, NSMD pad definition Appendix A +BGA 196 1 FTGB196 +0 +196 +196 +Package_BGA +Xilinx_RB484 +Artix-7 and Zynq-7000 BGA, 22x22 grid, 23x23mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition Appendix A +BGA 484 1 RB484 +0 +484 +484 +Package_BGA +Xilinx_RB676 +Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=280, NSMD pad definition Appendix A +BGA 676 1 RB676 +0 +676 +676 +Package_BGA +Xilinx_RF676 +Kintex-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=297, NSMD pad definition Appendix A +BGA 676 1 RF676 +0 +676 +676 +Package_BGA +Xilinx_RF900 +Kintex-7 and Zynq-7000 BGA, 30x30 grid, 31x31mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=298, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=94, NSMD pad definition Appendix A +BGA 900 1 RF900 +0 +900 +900 +Package_BGA +Xilinx_RF1156 +Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=95, NSMD pad definition Appendix A +BGA 1156 1 RF1156 +0 +1156 +1156 +Package_BGA +Xilinx_RF1157_RF1158 +Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=305, NSMD pad definition Appendix A +BGA 1156 1 RF1157 RF1158 +0 +1156 +1156 +Package_BGA +Xilinx_RF1761 +Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=306, NSMD pad definition Appendix A +BGA 1760 1 RF1761 +0 +1760 +1760 +Package_BGA +Xilinx_RF1930 +Virtex-7 BGA, 44x44 grid, 45x45mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=307, NSMD pad definition Appendix A +BGA 1924 1 RF1930 +0 +1924 +1924 +Package_BGA +Xilinx_RFG676 +Zynq-7000 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=93, NSMD pad definition Appendix A +BGA 676 1 RF676 RFG676 +0 +676 +676 +Package_BGA +Xilinx_RS484 +Artix-7 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=279, NSMD pad definition Appendix A +BGA 484 0.8 RS484 +0 +484 +484 +Package_BGA +Xilinx_SBG484 +Artix-7 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=270, NSMD pad definition Appendix A +BGA 484 0.8 SB484 SBG484 SBV484 +0 +484 +484 +Package_BGA +Xilinx_SBG485 +Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=80, NSMD pad definition Appendix A +BGA 484 0.8 SBG485 SBV485 +0 +484 +484 +Package_CSP +Analog_LFCSP-8-1EP_3x3mm_P0.5mm_EP1.53x1.85mm +LFCSP, exposed pad, Analog Devices (http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5542.pdf) +LFCSP 8 0.5 +0 +12 +5 +Package_CSP +LFCSP-8-1EP_3x2mm_P0.5mm_EP1.6x1.65mm +LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/57080735642908cp_8_4.pdf +LFCSP 8pin thermal pad 3x2mm Pitch 0.5mm +0 +9 +9 +Package_CSP +LFCSP-8-1EP_3x3mm_P0.5mm_EP1.45x1.74mm +LFCSP, 8 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-8/CP_8_13.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +LFCSP DFN_QFN +0 +13 +9 +Package_CSP +LFCSP-8_2x2mm_P0.5mm +LFCSP 8pin Pitch 0.5mm, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_8_6.pdf +LFCSP 8pin 2x2mm Pitch 0.5mm +0 +8 +8 +Package_CSP +LFCSP-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm +LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/CP_16_22.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +21 +17 +Package_CSP +LFCSP-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias +LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/CP_16_22.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +26 +17 +Package_CSP +LFCSP-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm +LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7992.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +21 +17 +Package_CSP +LFCSP-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm_ThermalVias +LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7992.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +26 +17 +Package_CSP +LFCSP-16-1EP_3x3mm_P0.5mm_EP1.854x1.854mm +16-Lead Lead Frame Chip Scale Package, 3x3mm, 0.5mm pitch, 1.854mm thermal pad (CP-16-22, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_16_22.pdf) +LFCSP 16 0.5 +0 +21 +17 +Package_CSP +LFCSP-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm +LFCSP, 16 pin, 4x4mm, 2.1mm sq pad (http://www.analog.com/media/en/technical-documentation/data-sheets/ADG633.pdf) +LFCSP 16 0.65 +0 +21 +17 +Package_CSP +LFCSP-16-1EP_4x4mm_P0.65mm_EP2.4x2.4mm +LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/cp-16-40.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +21 +17 +Package_CSP +LFCSP-16-1EP_4x4mm_P0.65mm_EP2.4x2.4mm_ThermalVias +LFCSP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-16/cp-16-40.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +31 +17 +Package_CSP +LFCSP-20-1EP_4x4mm_P0.5mm_EP2.1x2.1mm +20-Lead Frame Chip Scale Package - 4x4x0.9 mm Body [LFCSP], (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_20_6.pdf) +LFCSP 0.5 +0 +25 +21 +Package_CSP +LFCSP-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm +LFCSP, 20 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +LFCSP DFN_QFN +0 +25 +21 +Package_CSP +LFCSP-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias +LFCSP, 20 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +LFCSP DFN_QFN +0 +35 +21 +Package_CSP +LFCSP-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm +LFCSP, 20 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-20/CP_20_8.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +25 +21 +Package_CSP +LFCSP-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias +LFCSP, 20 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-20/CP_20_8.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +35 +21 +Package_CSP +LFCSP-24-1EP_4x4mm_P0.5mm_EP2.3x2.3mm +LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +29 +25 +Package_CSP +LFCSP-24-1EP_4x4mm_P0.5mm_EP2.3x2.3mm_ThermalVias +LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_14.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +39 +25 +Package_CSP +LFCSP-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm +LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +29 +25 +Package_CSP +LFCSP-24-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias +LFCSP, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_24_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +39 +25 +Package_CSP +LFCSP-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm +LFCSP, 32 Pin (https://www.analog.com/media/en/package-pcb-resources/package/414143737956480539664569cp_32_2.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +42 +33 +Package_CSP +LFCSP-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias +LFCSP, 32 Pin (https://www.analog.com/media/en/package-pcb-resources/package/414143737956480539664569cp_32_2.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +59 +33 +Package_CSP +LFCSP-32-1EP_5x5mm_P0.5mm_EP3.25x3.25mm +32-Lead Frame Chip Scale Package LFCSP (5mm x 5mm); (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-32/CP_32_27.pdf +LFCSP 0.5 +0 +37 +33 +Package_CSP +LFCSP-48-1EP_7x7mm_P0.5mm_EP4.1x4.1mm +LFCSP, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +58 +49 +Package_CSP +LFCSP-48-1EP_7x7mm_P0.5mm_EP4.1x4.1mm_ThermalVias +LFCSP, 48 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_48_5.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +75 +49 +Package_CSP +LFCSP-64-1EP_9x9mm_P0.5mm_EP5.21x5.21mm +LFCSP, 64 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_64_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +69 +65 +Package_CSP +LFCSP-64-1EP_9x9mm_P0.5mm_EP5.21x5.21mm_ThermalVias +LFCSP, 64 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp_64_7.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +86 +65 +Package_CSP +LFCSP-72-1EP_10x10mm_P0.5mm_EP5.3x5.3mm +LFCSP, 72 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +82 +73 +Package_CSP +LFCSP-72-1EP_10x10mm_P0.5mm_EP5.3x5.3mm_ThermalVias +LFCSP, 72 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1452_1451_1450.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP NoLead +0 +99 +73 +Package_CSP +LFCSP-72-1EP_10x10mm_P0.5mm_EP6.15x6.15mm +72-Lead Frame Chip Scale Package - 10x10x0.9 mm Body [LFCSP]; (see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf) +LFCSP 0.5 +0 +77 +73 +Package_CSP +LFCSP-VQ-24-1EP_4x4mm_P0.5mm_EP2.642x2.642mm +LFCSP VQ, 24 pin, exposed pad, 4x4mm body, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf) +LFCSP 0.5 +0 +29 +25 +Package_CSP +LFCSP-VQ-48-1EP_7x7mm_P0.5mm +LFCSP VQ, 48 pin, exposed pad, 7x7mm body (http://www.analog.com/media/en/technical-documentation/data-sheets/AD7951.pdf, http://www.analog.com/en/design-center/packaging-quality-symbols-footprints/symbols-and-footprints/AD7951.html) +LFCSP 48 +0 +49 +49 +Package_CSP +LFCSP-WD-10-1EP_3x3mm_P0.5mm_EP1.64x2.38mm +LFCSP-WD, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-10/CP_10_9.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP-WD NoLead +0 +17 +11 +Package_CSP +LFCSP-WD-10-1EP_3x3mm_P0.5mm_EP1.64x2.38mm_ThermalVias +LFCSP-WD, 10 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-10/CP_10_9.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LFCSP-WD NoLead +0 +24 +11 +Package_CSP +ST_WLCSP-25_Die425 +WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf +BGA 25 0.4 +0 +25 +25 +Package_CSP +ST_WLCSP-25_Die444 +WLCSP-25, 5x5 raster, 2.423x2.325mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f031k6.pdf +BGA 25 0.4 +0 +25 +25 +Package_CSP +ST_WLCSP-25_Die457 +WLCSP-25, 5x5 raster, 2.133x2.070mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32l011k3.pdf +BGA 25 0.4 +0 +25 +25 +Package_CSP +ST_WLCSP-36_Die417 +WLCSP-36, 6x6 raster, 2.61x2.88mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l052t8.pdf +BGA 36 0.4 +0 +36 +36 +Package_CSP +ST_WLCSP-36_Die440 +WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf +BGA 36 0.4 +0 +36 +36 +Package_CSP +ST_WLCSP-36_Die445 +WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.3 of http://www.st.com/resource/en/datasheet/stm32f042k6.pdf +BGA 36 0.4 +0 +36 +36 +Package_CSP +ST_WLCSP-36_Die458 +WLCSP-36, 6x6 raster, 2.553x2.579mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f410t8.pdf +BGA 36 0.4 +0 +36 +36 +Package_CSP +ST_WLCSP-49_Die423 +WLCSP-49, 7x7 raster, 2.965x2.965mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f401vc.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die431 +WLCSP-49, 7x7 raster, 2.999x3.185mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f411vc.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die433 +WLCSP-49, 7x7 raster, 3.029x3.029mm package, pitch 0.4mm; see section 7.1.1 of http://www.st.com/resource/en/datasheet/stm32f401ce.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die435 +WLCSP-49, 7x7 raster, 3.141x3.127mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/DM00257211.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die438 +WLCSP-49, 7x7 raster, 3.89x3.74mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303r8.pdf +BGA 49 0.5 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die439 +WLCSP-49, 7x7 raster, 3.417x3.151mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f301r8.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die447 +WLCSP-49, 7x7 raster, 3.294x3.258mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-49_Die448 +WLCSP-49, 7x7 raster, 3.277x3.109mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f071v8.pdf +BGA 49 0.4 +0 +49 +49 +Package_CSP +ST_WLCSP-63_Die427 +WLCSP-63, 7x9 raster, 3.228x4.164mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l151cc.pdf +BGA 63 0.4 +0 +63 +63 +Package_CSP +ST_WLCSP-64_Die414 +WLCSP-64, 8x8 raster, 4.466x4.395mm package, pitch 0.5mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf +BGA 64 0.5 +0 +64 +64 +Package_CSP +ST_WLCSP-64_Die427 +WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf +BGA 64 0.4 +0 +64 +64 +Package_CSP +ST_WLCSP-64_Die435 +WLCSP-64, 8x8 raster, 3.141x3.127mm package, pitch 0.35mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00257211.pdf +BGA 64 0.35 +0 +64 +64 +Package_CSP +ST_WLCSP-64_Die436 +WLCSP-64, 8x8 raster, 4.539x4.911mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zd.pdf +BGA 64 0.4 +0 +64 +64 +Package_CSP +ST_WLCSP-64_Die441 +WLCSP-64, 8x8 raster, 3.623x3.651mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00213872.pdf +BGA 64 0.4 +0 +64 +64 +Package_CSP +ST_WLCSP-64_Die442 +WLCSP-64, 8x8 raster, 3.347x3.585mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f091vb.pdf +BGA 64 0.4 +0 +64 +64 +Package_CSP +ST_WLCSP-64_Die462 +WLCSP-64, 8x8 raster, 3.357x3.657mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00340475.pdf +BGA 64 0.4 +0 +64 +64 +Package_CSP +ST_WLCSP-66_Die411 +WLCSP-66, 9x9 raster, 3.639x3.971mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf +BGA 66 0.4 +0 +66 +66 +Package_CSP +ST_WLCSP-66_Die432 +WLCSP-66, 8x9 raster, 3.767x4.229mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f378vc.pdf +BGA 66 0.4 +0 +66 +66 +Package_CSP +ST_WLCSP-72_Die415 +WLCSP-72, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf +BGA 72 0.4 +0 +72 +72 +Package_CSP +ST_WLCSP-81_Die415 +WLCSP-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf +BGA 81 0.4 +0 +81 +81 +Package_CSP +ST_WLCSP-81_Die421 +WLCSP-81, 9x9 raster, 3.693x3.815mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf +BGA 81 0.4 +0 +81 +81 +Package_CSP +ST_WLCSP-81_Die463 +WLCSP-81, 9x9 raster, 4.039x3.951mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf +BGA 81 0.4 +0 +81 +81 +Package_CSP +ST_WLCSP-90_Die413 +WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f405og.pdf +BGA 90 0.4 +0 +90 +90 +Package_CSP +ST_WLCSP-100_Die422 +WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f302vc.pdf +BGA 100 0.4 +0 +100 +100 +Package_CSP +ST_WLCSP-100_Die446 +WLCSP-100, 10x10 raster, 4.775x5.041mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303zd.pdf +BGA 100 0.4 +0 +100 +100 +Package_CSP +ST_WLCSP-100_Die452 +WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.7 of http://www.st.com/resource/en/datasheet/DM00330506.pdf +BGA 100 0.4 +0 +100 +100 +Package_CSP +ST_WLCSP-100_Die461 +WLCSP-100, 10x10 raster, 4.618x4.142mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00284211.pdf +BGA 100 0.4 +0 +100 +100 +Package_CSP +ST_WLCSP-104_Die437 +WLCSP-104, 9x12 raster, 4.095x5.094mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152ze.pdf +BGA 104 0.4 +0 +104 +104 +Package_CSP +ST_WLCSP-143_Die419 +WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf +BGA 143 0.4 +0 +143 +143 +Package_CSP +ST_WLCSP-143_Die449 +WLCSP-143, 11x13 raster, 4.539x5.849mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf +BGA 143 0.4 +0 +143 +143 +Package_CSP +ST_WLCSP-144_Die470 +WLCSP-144, 12x12 raster, 5.24x5.24mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/DM00366448.pdf +BGA 144 0.4 +0 +144 +144 +Package_CSP +ST_WLCSP-168_Die434 +WLCSP-168, 12x14 raster, 4.891x5.692mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f469ni.pdf +BGA 168 0.4 +0 +168 +168 +Package_CSP +ST_WLCSP-180_Die451 +WLCSP-180, 13x14 raster, 5.537x6.095mm package, pitch 0.4mm; see section 6.6 of http://www.st.com/resource/en/datasheet/DM00273119.pdf +BGA 180 0.4 +0 +180 +180 +Package_CSP +WLCSP-6_1.4x1.0mm_P0.4mm +6pin Pitch 0.4mm +6pin Pitch 0.4mm WLCSP +0 +6 +6 +Package_CSP +WLCSP-8_1.58x1.63x0.35mm_Layout3x5_P0.35x0.4mm_Ball0.25mm_Pad0.25mm_NSMD +WLCSP/XFBGA 8-pin package, staggered pins, http://www.adestotech.com/wp-content/uploads/DS-AT25DF041B_040.pdf +WLCSP WLCSP-8 XFBGA XFBGA-8 CSP BGA Chip-Scale Glass-Top +0 +8 +8 +Package_CSP +WLCSP-12_1.56x1.56mm_P0.4mm +WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf +BMM150 WLCSP +0 +12 +12 +Package_CSP +WLCSP-12_1.403x1.555mm_P0.4mm_Stagger +WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; http://ww1.microchip.com/downloads/en/devicedoc/atmel-8235-8-bit-avr-microcontroller-attiny20_datasheet.pdf#page=208 +CSP 12 0.2x0.346333 +0 +12 +12 +Package_CSP +WLCSP-16_4x4_B2.17x2.32mm_P0.5mm +WLCSP-16, http://www.nxp.com/documents/data_sheet/LPC1102_1104.pdf, http://www.nxp.com/assets/documents/data/en/application-notes/AN3846.pdf +WLCSP-16 NXP +0 +16 +16 +Package_CSP +WLCSP-20_1.934x2.434mm_Layout4x5_P0.4mm +WLCSP-20, 4x5 raster, 1.934x2.434mm package, pitch 0.4mm; see section 36.2.3 of http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42363-SAM-D11_Datasheet.pdf +BGA 20 0.4 +0 +20 +20 +Package_CSP +WLCSP-20_1.994x1.94mm_Layout4x5_P0.4mm +WLCSP-20, https://www.nxp.com/docs/en/package-information/98ASA00539D.pdf +WLCSP-20 +0 +20 +20 +Package_CSP +WLCSP-20_1.994x1.609mm_Layout5x4_P0.4mm +WLCSP-20, https://www.nxp.com/docs/en/package-information/98ASA00676D.pdf +WLCSP-20 +0 +20 +20 +Package_CSP +WLCSP-36_2.82x2.67mm_Layout6x6_P0.4mm +WLCSP-36, https://www.nxp.com/docs/en/package-information/98ASA00949D.pdf +WLCSP-36 +0 +36 +36 +Package_CSP +WLCSP-36_2.374x2.459mm_Layout6x6_P0.35mm +WLCSP-36, https://www.nxp.com/docs/en/package-information/98ASA00604D.pdf +WLCSP-36 +0 +36 +36 +Package_CSP +WLCSP-56_3.170x3.444mm_Layout7x8_P0.4mm +WLCSP-56, 7x8 raster, 3.170x3.444mm package, pitch 0.4mm; see section 48.2.4 of http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001479B.pdf +BGA 56 0.4 +0 +56 +56 +Package_CSP +WLCSP-81_4.41x3.76mm_P0.4mm +WLCSP-81, 9x9, 0.4mm Pitch, http://www.st.com/content/ccc/resource/technical/document/technical_note/92/30/3c/a1/4c/bb/43/6f/DM00103228.pdf/files/DM00103228.pdf/jcr:content/translations/en.DM00103228.pdf +WLCSP ST +0 +81 +81 +Package_CSP +pSemi_CSP-16_1.64x2.04mm_P0.4mm +pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf) +psemi csp 16 +0 +16 +16 +Package_CSP +pSemi_CSP-16_1.64x2.04mm_P0.4mm_Pad0.18mm +pSemi CSP-16 1.64x2.04x0.285mm (http://www.psemi.com/pdf/datasheets/pe29101ds.pdf, http://www.psemi.com/pdf/app_notes/an77.pdf) +psemi csp 16 +0 +16 +16 +Package_DFN_QFN +AMS_QFN-4-1EP_2x2mm_P0.95mm_EP0.7x1.6mm +UFD Package, 4-Lead Plastic QFN (2mm x 2mm), http://ams.com/eng/content/download/950231/2267959/483138 +QFN 0.95 +0 +6 +5 +Package_DFN_QFN +Cypress_QFN-56-1EP_8x8mm_P0.5mm_EP6.22x6.22mm_ThermalVias +56-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8x0.9 mm Body [QFN] (see datasheet at http://www.cypress.com/file/138911/download and app note at http://www.cypress.com/file/140006/download) +QFN 0.5 +0 +87 +57 +Package_DFN_QFN +DFN-6-1EP_1.2x1.2mm_P0.4mm_EP0.3x0.94mm_PullBack +DFN, 6 Pin (http://www.onsemi.com/pub/Collateral/NCP133-D.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +9 +7 +Package_DFN_QFN +DFN-6-1EP_2x1.8mm_P0.5mm_EP1.2x1.6mm +DFN, 6 Pin (https://www.diodes.com/assets/Package-Files/U-DFN2018-6.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +11 +7 +Package_DFN_QFN +DFN-6-1EP_2x2mm_P0.5mm_EP0.61x1.42mm +DC6 Package; 6-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_6_05-08-1703.pdf) +DFN 0.5 +0 +9 +7 +Package_DFN_QFN +DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm +6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.65 +0 +9 +7 +Package_DFN_QFN +DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm +DFN, 6 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/(DCB6)%20DFN%2005-08-1715%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +11 +7 +Package_DFN_QFN +DFN-6-1EP_3x3mm_P0.95mm_EP1.7x2.6mm +DFN6 3*3 MM, 0.95 PITCH; CASE 506AH-01 (see ON Semiconductor 506AH.PDF) +DFN 0.95 +0 +13 +7 +Package_DFN_QFN +DFN-6-1EP_3x3mm_P1mm_EP1.5x2.4mm +DFN, 6 Pin (https://www.silabs.com/documents/public/data-sheets/Si7020-A20.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +11 +7 +Package_DFN_QFN +DFN-6_1.3x1.2mm_P0.4mm +6-Lead Plastic DFN (1.3mm x 1.2mm) +DFN 0.4 +0 +6 +6 +Package_DFN_QFN +DFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.3mm +DFN, 8 Pin (https://www.onsemi.com/pub/Collateral/NB3N551-D.PDF#page=7), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.5mm +DFN, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8127-AVR-8-bit-Microcontroller-ATtiny4-ATtiny5-ATtiny9-ATtiny10_Datasheet.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_2x2mm_P0.5mm_EP1.05x1.75mm +DFN8 2x2, 0.5P; CASE 506CN (see ON Semiconductor 506CN.PDF) +DFN 0.5 +0 +11 +9 +Package_DFN_QFN +DFN-8-1EP_2x2mm_P0.45mm_EP0.64x1.38mm +DC8 Package 8-Lead Plastic DFN (2mm x 2mm) (see Linear Technology DFN_8_05-08-1719.pdf) +DFN 0.45 +0 +11 +9 +Package_DFN_QFN +DFN-8-1EP_2x3mm_P0.5mm_EP0.61x2.2mm +DDB Package; 8-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_8_05-08-1702.pdf) +DFN 0.5 +0 +12 +9 +Package_DFN_QFN +DFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.5mm +8-Lead Plastic Dual Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body [UDFN] (see Atmel-8815-SEEPROM-AT24CS01-02-Datasheet.pdf) +DFN 0.5 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_3x2mm_P0.5mm_EP1.36x1.46mm +8-Lead Plastic Dual Flat, No Lead Package (8MA2) - 2x3x0.6 mm Body (http://ww1.microchip.com/downloads/en/DeviceDoc/20005010F.pdf) +DFN 0.5 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_3x2mm_P0.5mm_EP1.75x1.45mm +8-Lead Plastic Dual Flat, No Lead Package (MC) - 2x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.5 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_3x2mm_P0.45mm_EP1.66x1.36mm +DCB Package 8-Lead Plastic DFN (2mm x 3mm) (see Linear Technology DFN_8_05-08-1718.pdf) +DFN 0.45 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_3x3mm_P0.5mm_EP1.66x2.38mm +DD Package; 8-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_8_05-08-1698.pdf) +DFN 0.5 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_3x3mm_P0.65mm_EP1.7x2.05mm +DFN, 8 Pin (http://www.ixysic.com/home/pdfs.nsf/www/IX4426-27-28.pdf/$file/IX4426-27-28.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_3x3mm_P0.65mm_EP1.55x2.4mm +8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.65 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_4x4mm_P0.8mm_EP2.3x3.24mm +DFN, 8 Pin (https://www.st.com/resource/en/datasheet/ld1086.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm +8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.8 +0 +15 +9 +Package_DFN_QFN +DFN-8-1EP_4x4mm_P0.8mm_EP2.39x2.21mm +8-Lead Plastic Dual Flat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN] (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF) +DFN 0.8 +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_6x5mm_P1.27mm_EP2x2mm +DD Package; 8-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download) +dfn +0 +13 +9 +Package_DFN_QFN +DFN-8-1EP_6x5mm_P1.27mm_EP4x4mm +DD Package; 8-Lead Plastic DFN (6mm x 5mm) (see http://www.everspin.com/file/236/download) +dfn +0 +25 +9 +Package_DFN_QFN +DFN-8_2x2mm_P0.5mm +DFN8 2x2, 0.5P; No exposed pad - Ref http://pdfserv.maximintegrated.com/land_patterns/90-0349.PDF +DFN 0.5 +0 +8 +8 +Package_DFN_QFN +DFN-10-1EP_2x3mm_P0.5mm_EP0.64x2.4mm +DDB Package; 10-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_10_05-08-1722.pdf) +DFN 0.5 +0 +13 +11 +Package_DFN_QFN +DFN-10-1EP_3x3mm_P0.5mm_EP1.7x2.5mm +DFN, 10 Pin (https://www.monolithicpower.com/pub/media/document/MPQ2483_r1.05.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +15 +11 +Package_DFN_QFN +DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm +10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.5 +0 +15 +11 +Package_DFN_QFN +DFN-10-1EP_3x3mm_P0.5mm_EP1.65x2.38mm +DFN, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +15 +11 +Package_DFN_QFN +DFN-10-1EP_3x3mm_P0.5mm_EP1.65x2.38mm_ThermalVias +DFN, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3471fb.pdf#page=15), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +22 +11 +Package_DFN_QFN +DFN-10-1EP_3x3mm_P0.5mm_EP1.75x2.7mm +10-Lead Plastic Dual Flat No-Lead Package, 3x3mm Body (see Atmel Appnote 8826) +DFN 0.5 +0 +15 +11 +Package_DFN_QFN +DFN-10_2x2mm_P0.4mm +10-Lead Plastic DFN (2mm x 2mm) 0.40mm pitch +DFN 10 0.4mm +0 +10 +10 +Package_DFN_QFN +DFN-12-1EP_2x3mm_P0.45mm_EP0.64x2.4mm +DDB Package; 12-Lead Plastic DFN (3mm x 2mm) (see Linear Technology DFN_12_05-08-1723.pdf) +DFN 0.45 +0 +15 +13 +Package_DFN_QFN +DFN-12-1EP_3x3mm_P0.5mm_EP2.05x2.86mm +10-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.5 +0 +17 +13 +Package_DFN_QFN +DFN-12-1EP_3x3mm_P0.45mm_EP1.66x2.38mm +DD Package; 12-Lead Plastic DFN (3mm x 3mm) (see Linear Technology DFN_12_05-08-1725.pdf) +DFN 0.45 +0 +17 +13 +Package_DFN_QFN +DFN-12-1EP_3x4mm_P0.5mm_EP1.7x3.3mm +DE/UE Package; 12-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_12_05-08-1695.pdf) +DFN 0.5 +0 +21 +13 +Package_DFN_QFN +DFN-12-1EP_4x4mm_P0.5mm_EP2.66x3.38mm +DF Package; 12-Lead Plastic DFN (4mm x 4mm) (see Linear Technology 05081733_A_DF12.pdf) +DFN 0.5 +0 +21 +13 +Package_DFN_QFN +DFN-12-1EP_4x4mm_P0.65mm_EP2.64x3.54mm +DFN12, 4x4, 0.65P; CASE 506CE (see ON Semiconductor 506CE.PDF) +DFN 0.65 +0 +21 +13 +Package_DFN_QFN +DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm +DD Package; 14-Lead Plastic DFN (3mm x 3mm) (http://pdfserv.maximintegrated.com/land_patterns/90-0063.PDF) +DFN 0.40 +0 +19 +15 +Package_DFN_QFN +DFN-14-1EP_3x4.5mm_P0.65mm_EP1.65x4.25mm +14-lead very thin plastic quad flat, 3.0x4.5mm size, 0.65mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/14L_VDFN_4_5x3_0mm_JHA_C041198A.pdf) +VDFN DFN 0.65mm +0 +23 +15 +Package_DFN_QFN +DFN-14-1EP_3x4.5mm_P0.65mm_EP1.65x4.25mm_ThermalVias +14-lead very thin plastic quad flat, 3.0x4.5mm size, 0.65mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/14L_VDFN_4_5x3_0mm_JHA_C041198A.pdf) +VDFN DFN 0.65mm +0 +33 +15 +Package_DFN_QFN +DFN-14-1EP_3x4mm_P0.5mm_EP1.7x3.3mm +DE Package; 14-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_14_05-08-1708.pdf) +DFN 0.5 +0 +23 +15 +Package_DFN_QFN +DFN-14-1EP_4x4mm_P0.5mm_EP2.86x3.6mm +DFN14, 4x4, 0.5P; CASE 506CM (see ON Semiconductor 506CM.PDF) +DFN 0.5 +0 +23 +15 +Package_DFN_QFN +DFN-16-1EP_3x4mm_P0.45mm_EP1.7x3.3mm +DE Package; 16-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_16_05-08-1732.pdf) +DFN 0.45 +0 +25 +17 +Package_DFN_QFN +DFN-16-1EP_3x5mm_P0.5mm_EP1.66x4.4mm +DHC Package; 16-Lead Plastic DFN (5mm x 3mm) (see Linear Technology DFN_16_05-08-1706.pdf) +DFN 0.5 +0 +27 +17 +Package_DFN_QFN +DFN-16-1EP_4x5mm_P0.5mm_EP2.44x4.34mm +DHD Package; 16-Lead Plastic DFN (5mm x 4mm) (see Linear Technology 05081707_A_DHD16.pdf) +DFN 0.5 +0 +25 +17 +Package_DFN_QFN +DFN-16-1EP_5x5mm_P0.5mm_EP3.46x4mm +DH Package; 16-Lead Plastic DFN (5mm x 5mm) (see Linear Technology DFN_16_05-08-1709.pdf) +DFN 0.5 +0 +26 +17 +Package_DFN_QFN +DFN-18-1EP_3x5mm_P0.5mm_EP1.66x4.4mm +DHC Package; 18-Lead Plastic DFN (5mm x 3mm) (see Linear Technology 05081955_0_DHC18.pdf) +DFN 0.5 +0 +29 +19 +Package_DFN_QFN +DFN-18-1EP_4x5mm_P0.5mm_EP2.44x4.34mm +DHD Package; 18-Lead Plastic DFN (5mm x 4mm) (see Linear Technology DFN_18_05-08-1778.pdf) +DFN 0.5 +0 +27 +19 +Package_DFN_QFN +DFN-20-1EP_5x6mm_P0.5mm_EP3.24x4.24mm +DFN20, 6x5, 0.5P; CASE 505AB (see ON Semiconductor 505AB.PDF) +DFN 0.5 +0 +33 +21 +Package_DFN_QFN +DFN-22-1EP_5x6mm_P0.5mm_EP3.14x4.3mm +DFN22 6*5*0.9 MM, 0.5 P; CASE 506AF\xe2\x88\x9201 (see ON Semiconductor 506AF.PDF) +DFN 0.5 +0 +35 +23 +Package_DFN_QFN +DFN-24-1EP_4x7mm_P0.5mm_EP2.64x6.44mm +DKD Package; 24-Lead Plastic DFN (7mm x 4mm) (see Linear Technology DFN_24_05-08-1864.pdf) +DFN 0.5 +0 +35 +25 +Package_DFN_QFN +DFN-32-1EP_4x7mm_P0.4mm_EP2.64x6.44mm +DKD Package; 32-Lead Plastic DFN (7mm x 4mm) (see Linear Technology DFN_32_05-08-1734.pdf) +DFN 0.4 +0 +43 +33 +Package_DFN_QFN +DFN-44-1EP_5x8.9mm_P0.4mm_EP3.7x8.4mm +DFN44 8.9x5, 0.4P; CASE 506BU-01 (see ON Semiconductor 506BU.PDF) +DFN 0.4 +0 +63 +45 +Package_DFN_QFN +DFN-S-8-1EP_6x5mm_P1.27mm +8-Lead Plastic Dual Flat, No Lead Package (MF) - 6x5 mm Body [DFN-S] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 1.27 +0 +16 +9 +Package_DFN_QFN +Diodes_DFN1006-3 +DFN package size 1006 3 pins +DFN package size 1006 3 pins +0 +3 +3 +Package_DFN_QFN +Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm +MLPQ 32 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) +mlpq 32 7x7mm +0 +19 +15 +Package_DFN_QFN +Infineon_MLPQ-40-32-1EP_7x7mm_P0.5mm +MLPQ 32 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) +mlpq 32 7x7mm +0 +76 +33 +Package_DFN_QFN +Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_EP5.55x5.55mm +MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2093mpbf.pdf?fileId=5546d462533600a401535675fb892793) +mlpq 32 7x7mm +0 +113 +49 +Package_DFN_QFN +Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_Pad5.15x5.15mm +MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2052mpbf.pdf?fileId=5546d462533600a401535675d3b32788) +mlpq 32 7x7mm +0 +117 +49 +Package_DFN_QFN +Infineon_MLPQ-48-1EP_7x7mm_P0.5mm_Pad5.55x5.55mm +MLPQ 48 leads, 7x7mm (https://www.infineon.com/dgdl/irs2093mpbf.pdf?fileId=5546d462533600a401535675fb892793) +mlpq 32 7x7mm +0 +117 +49 +Package_DFN_QFN +Infineon_PQFN-22-15-4EP_6x5mm_P0.65mm +PQFN 22 leads, 5x6mm, 0.127mm stencil (https://www.infineon.com/dgdl/ir4301.pdf?fileId=5546d462533600a4015355d5fc691819, https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) +pqfn 22 5x6mm +0 +56 +15 +Package_DFN_QFN +Infineon_PQFN-44-31-5EP_7x7mm_P0.5mm +PQFN 44 leads, 7x7mm, 0.127mm stencil (https://www.infineon.com/dgdl/ir4302.pdf?fileId=5546d462533600a4015355d602a9181d, https://www.infineon.com/dgdl/Infineon-AN1170-AN-v05_00-EN.pdf?fileId=5546d462533600a40153559ac3e51134) +pqfn 44 7x7mm +0 +125 +27 +Package_DFN_QFN +Linear_DE14MA +14-Lead Plastic DFN, 4mm x 3mm (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-dfn/05081731_C_DE14MA.pdf) +DFN 0.5 +0 +14 +14 +Package_DFN_QFN +Linear_UGK52_QFN-46-52 +Linear UKG52(46) package, QFN-52-1EP variant (see http://cds.linear.com/docs/en/datasheet/3886fe.pdf) +QFN 0.5 +0 +62 +47 +Package_DFN_QFN +MLF-6-1EP_1.6x1.6mm_P0.5mm_EP0.5x1.26mm +MLF, 6 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5353.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +MLF NoLead +0 +9 +7 +Package_DFN_QFN +MLF-8-1EP_3x3mm_P0.65mm_EP1.55x2.3mm +8-Pin ePad 3mm x 3mm MLF - 3x3x0.85 mm Body (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf) +DFN MLF 0.65 +0 +12 +9 +Package_DFN_QFN +MLF-8-1EP_3x3mm_P0.65mm_EP1.55x2.3mm_ThermalVias +8-Pin ePad 3mm x 3mm MLF - 3x3x0.85 mm Body (see Microchip datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf) +DFN MLF 0.65 +0 +15 +9 +Package_DFN_QFN +MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm +MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=263), generated with kicad-footprint-generator ipc_noLead_generator.py +MLF NoLead +0 +25 +21 +Package_DFN_QFN +MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias +MLF, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=263), generated with kicad-footprint-generator ipc_noLead_generator.py +MLF NoLead +0 +30 +21 +Package_DFN_QFN +MLPQ-16-1EP_4x4mm_P0.65mm_EP2.8x2.8mm +Micro Leadframe Package, 16 pin with exposed pad +MLPQ- 0.65 +0 +21 +17 +Package_DFN_QFN +Micrel_MLF-8-1EP_2x2mm_P0.5mm_EP0.8x1.3mm_ThermalVias +http://ww1.microchip.com/downloads/en/DeviceDoc/mic2290.pdf +mlf 8 2x2 mm +0 +14 +9 +Package_DFN_QFN +Microchip_8E-16 +16-Lead Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf) +QFN Microchip 8E 16 +0 +20 +17 +Package_DFN_QFN +Microchip_DRQFN-44-1EP_5x5mm_P0.7mm_EP2.65x2.65mm +QFN, 44 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/44L_VQFN_5x5mm_Dual_Row_%5BS3B%5D_C04-21399a.pdf) +QFN dual row +0 +49 +45 +Package_DFN_QFN +Microchip_DRQFN-44-1EP_5x5mm_P0.7mm_EP2.65x2.65mm_ThermalVias +QFN, 44 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/44L_VQFN_5x5mm_Dual_Row_%5BS3B%5D_C04-21399a.pdf) +QFN dual row +0 +59 +45 +Package_DFN_QFN +Microchip_DRQFN-64-1EP_7x7mm_P0.65mm_EP4.1x4.1mm +QFN, 64 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_7x7_Dual_Row_%5BSVB%5D_C04-21420a.pdf) +QFN dual row +0 +74 +65 +Package_DFN_QFN +Microchip_DRQFN-64-1EP_7x7mm_P0.65mm_EP4.1x4.1mm_ThermalVias +QFN, 64 Pin, dual row (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_7x7_Dual_Row_%5BSVB%5D_C04-21420a.pdf) +QFN dual row +0 +91 +65 +Package_DFN_QFN +Microsemi_QFN-40-32-2EP_6x8mm_P0.5mm +40-Lead (32-Lead Populated) Plastic Quad Flat, No Lead Package - 6x8x0.9mm Body (https://www.microsemi.com/document-portal/doc_download/131677-pd70224-data-sheet) +QFN 0.5 +0 +92 +34 +Package_DFN_QFN +Mini-Circuits_DL805 +https://ww2.minicircuits.com/case_style/DL805.pdf +RF Switch +0 +11 +9 +Package_DFN_QFN +Mini-Circuits_FG873-4_3x3mm +Mini Circuits Case style FG (https://ww2.minicircuits.com/case_style/FG873.pdf) +FG873 +0 +4 +4 +Package_DFN_QFN +Nordic_AQFN-73-1EP_7x7mm_P0.5mm +http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.nrf52%2Fdita%2Fnrf52%2Fchips%2Fnrf52840.html +AQFN 7mm +0 +78 +74 +Package_DFN_QFN +OnSemi_DFN-8_2x2mm_P0.5mm +DFN8 2x2, 0.5P (https://www.onsemi.com/pub/Collateral/511AT.PDF) +DFN 0.5 +0 +8 +8 +Package_DFN_QFN +OnSemi_UDFN-8_1.2x1.8mm_P0.4mm +8-Lead Plastic Dual Flat, No Lead Package, 1.2x1.8x1.55 mm Body [UDFN] (See http://www.onsemi.com/pub/Collateral/NLSV2T244-D.PDF) +dfn udfn dual flat +0 +8 +8 +Package_DFN_QFN +OnSemi_VCT-28_3.5x3.5mm_P0.4mm +OnSemi VCT, 28 Pin (http://www.onsemi.com/pub/Collateral/601AE.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +OnSemi VCT DFN_QFN +0 +28 +28 +Package_DFN_QFN +Panasonic_HQFN-16-1EP_4x4mm_P0.65mm_EP2.9x2.9mm +Panasonic HQFN-16, 4x4x0.85mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HQFN016-A-0404XZL_EN.pdf) +panasonic hqfn +0 +37 +17 +Package_DFN_QFN +Panasonic_HSON-8_8x8mm_P2.00mm +Panasonic HSON-8, 8x8x1.25mm (https://industrial.panasonic.com/content/data/SC/ds/ds7/c0/PKG_HSON008-A-0808XXI_EN.pdf) +panasonic hson +0 +27 +9 +Package_DFN_QFN +QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm +QFN, 12 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_12_%2005-08-1855.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +17 +13 +Package_DFN_QFN +QFN-12-1EP_3x3mm_P0.5mm_EP1.65x1.65mm_ThermalVias +QFN, 12 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_12_%2005-08-1855.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +22 +13 +Package_DFN_QFN +QFN-12-1EP_3x3mm_P0.51mm_EP1.45x1.45mm +QFN, 12 Pin (https://ww2.minicircuits.com/case_style/DQ1225.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +17 +13 +Package_DFN_QFN +QFN-14-1EP_1.6x1.6mm_P0.4mm_EP0.74x0.74mm +QFN, 14 Pin (http://www.skyworksinc.com/uploads/documents/SKY13575_639LF_203270D.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +19 +15 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm +QFN, 16 Pin (https://www.st.com/content/ccc/resource/technical/document/datasheet/4a/50/94/16/69/af/4b/58/DM00047334.pdf/files/DM00047334.pdf/jcr:content/translations/en.DM00047334.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm_ThermalVias +QFN, 16 Pin (http://www.cypress.com/file/46236/download), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.9x1.9mm +QFN, 16 Pin (https://www.nxp.com/docs/en/package-information/98ASA00525D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.9x1.9mm_ThermalVias +QFN, 16 Pin (https://www.nxp.com/docs/en/package-information/98ASA00525D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +26 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm +QFN, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm_ThermalVias +QFN, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +26 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm +QFN, 16 Pin (https://www.onsemi.com/pub/Collateral/NCN4555-D.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm_ThermalVias +QFN, 16 Pin (https://www.onsemi.com/pub/Collateral/NCN4555-D.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +26 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.5mm_EP2.45x2.45mm +QFN, 16 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/isl8117.pdf#page=22), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias +QFN, 16 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/isl8117.pdf#page=22), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm +QFN, 16 Pin (http://www.thatcorp.com/datashts/THAT_1580_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.1x2.1mm_ThermalVias +QFN, 16 Pin (http://www.thatcorp.com/datashts/THAT_1580_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.5x2.5mm +QFN, 16 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=266), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.5x2.5mm_ThermalVias +QFN, 16 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=266), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm +QFN, 16 Pin (https://www.allegromicro.com/~/media/Files/Datasheets/A4403-Datasheet.ashx), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_PullBack +QFN, 16 Pin (https://ams.com/documents/20143/36005/AS5055A_DS000304_2-00.pdf#page=24), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_PullBack_ThermalVias +QFN, 16 Pin (https://ams.com/documents/20143/36005/AS5055A_DS000304_2-00.pdf#page=24), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm_ThermalVias +QFN, 16 Pin (https://www.allegromicro.com/~/media/Files/Datasheets/A4403-Datasheet.ashx), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.15x2.15mm +QFN, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4001f.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_4x4mm_P0.65mm_EP2.15x2.15mm_ThermalVias +QFN, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4001f.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-16-1EP_5x5mm_P0.8mm_EP2.7x2.7mm +QFN, 16 Pin (http://www.intersil.com/content/dam/Intersil/documents/l16_/l16.5x5.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +QFN-16-1EP_5x5mm_P0.8mm_EP2.7x2.7mm_ThermalVias +QFN, 16 Pin (http://www.intersil.com/content/dam/Intersil/documents/l16_/l16.5x5.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm +QFN, 20 Pin (http://www.ti.com/lit/ml/mpqf239/mpqf239.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +25 +21 +Package_DFN_QFN +QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm_ThermalVias +QFN, 20 Pin (http://www.ti.com/lit/ml/mpqf239/mpqf239.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +30 +21 +Package_DFN_QFN +QFN-20-1EP_3x3mm_P0.4mm_EP1.65x1.65mm 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DFN_QFN +0 +30 +21 +Package_DFN_QFN +QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm +QFN, 20 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1742.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +25 +21 +Package_DFN_QFN +QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm_ThermalVias +QFN, 20 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1742.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +32 +21 +Package_DFN_QFN +QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm +QFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=274), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +25 +21 +Package_DFN_QFN +QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm_ThermalVias +QFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=274), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +30 +21 +Package_DFN_QFN +QFN-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm +QFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc2535.pdf#page=164), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +25 +21 +Package_DFN_QFN +QFN-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias +QFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc2535.pdf#page=164), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +30 +21 +Package_DFN_QFN +QFN-20-1EP_4x4mm_P0.5mm_EP2.7x2.7mm +QFN, 20 Pin (https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +25 +21 +Package_DFN_QFN +QFN-20-1EP_4x4mm_P0.5mm_EP2.7x2.7mm_ThermalVias +QFN, 20 Pin (https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +30 +21 +Package_DFN_QFN +QFN-20-1EP_4x5mm_P0.5mm_EP2.65x3.65mm +QFN, 20 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1711.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +27 +21 +Package_DFN_QFN +QFN-20-1EP_4x5mm_P0.5mm_EP2.65x3.65mm_ThermalVias +QFN, 20 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1711.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +40 +21 +Package_DFN_QFN +QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm +QFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=276), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +25 +21 +Package_DFN_QFN +QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm_ThermalVias +QFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=276), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +35 +21 +Package_DFN_QFN +QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm +QFN, 24 Pin (https://www.invensense.com/wp-content/uploads/2015/02/PS-MPU-9250A-01-v1.1.pdf#page=39), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm_ThermalVias +QFN, 24 Pin (https://www.invensense.com/wp-content/uploads/2015/02/PS-MPU-9250A-01-v1.1.pdf#page=39), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +34 +25 +Package_DFN_QFN +QFN-24-1EP_3x4mm_P0.4mm_EP1.65x2.65mm +QFN, 24 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1742.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +25 +Package_DFN_QFN +QFN-24-1EP_3x4mm_P0.4mm_EP1.65x2.65mm_ThermalVias +QFN, 24 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_20_05-08-1742.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +38 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm +QFN, 24 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=278), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias +QFN, 24 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=278), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.6mm +QFN, 24 Pin (https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.6mm_ThermalVias +QFN, 24 Pin (https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm +QFN, 24 Pin (http://www.alfarzpp.lv/eng/sc/AS3330.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm_ThermalVias +QFN, 24 Pin (http://www.alfarzpp.lv/eng/sc/AS3330.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm +QFN, 24 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/hmc431.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_ThermalVias +QFN, 24 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/hmc431.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +39 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.65x2.65mm +QFN, 24 Pin (http://www.cypress.com/file/46236/download), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_4x4mm_P0.5mm_EP2.65x2.65mm_ThermalVias +QFN, 24 Pin (http://www.cypress.com/file/46236/download), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm +QFN, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_24_05-08-1696.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +31 +25 +Package_DFN_QFN +QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm_ThermalVias +QFN, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_24_05-08-1696.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +44 +25 +Package_DFN_QFN +QFN-24-1EP_5x5mm_P0.65mm_EP3.2x3.2mm +QFN, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UH24)%20QFN%2005-08-1747%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_5x5mm_P0.65mm_EP3.2x3.2mm_ThermalVias +QFN, 24 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UH24)%20QFN%2005-08-1747%20Rev%20A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +51 +25 +Package_DFN_QFN +QFN-24-1EP_5x5mm_P0.65mm_EP3.4x3.4mm +QFN, 24 Pin (http://www.thatcorp.com/datashts/THAT_5173_Datasheet.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +QFN-24-1EP_5x5mm_P0.65mm_EP3.4x3.4mm_ThermalVias +QFN, 24 Pin (http://www.thatcorp.com/datashts/THAT_5173_Datasheet.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +QFN-24-1EP_5x5mm_P0.65mm_EP3.6x3.6mm +QFN, 24 Pin (https://www.nxp.com/docs/en/package-information/98ASA00734D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +34 +25 +Package_DFN_QFN +QFN-24-1EP_5x5mm_P0.65mm_EP3.6x3.6mm_ThermalVias +QFN, 24 Pin (https://www.nxp.com/docs/en/package-information/98ASA00734D.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +67 +25 +Package_DFN_QFN +QFN-28-1EP_3x6mm_P0.5mm_EP1.7x4.75mm +QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081926_0_UDE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +37 +29 +Package_DFN_QFN +QFN-28-1EP_3x6mm_P0.5mm_EP1.7x4.75mm_ThermalVias +QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081926_0_UDE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +53 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.4mm_EP2.3x2.3mm +QFN, 28 Pin (http://www.issi.com/WW/pdf/31FL3731.pdf#page=21), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +33 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.4mm_EP2.3x2.3mm_ThermalVias +QFN, 28 Pin (http://www.issi.com/WW/pdf/31FL3731.pdf#page=21), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +43 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.4mm_EP2.4x2.4mm +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=280), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +33 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.4mm_EP2.4x2.4mm_ThermalVias +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=280), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +43 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.4mm_EP2.6x2.6mm +QFN, 28 Pin (package code T2844-1; https://pdfserv.maximintegrated.com/package_dwgs/21-0139.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +33 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.4mm_EP2.6x2.6mm_ThermalVias +QFN, 28 Pin (package code T2844-1; https://pdfserv.maximintegrated.com/package_dwgs/21-0139.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +43 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf#page=16), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +33 +29 +Package_DFN_QFN +QFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm_ThermalVias +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf#page=16), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +43 +29 +Package_DFN_QFN +QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm +QFN, 28 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/3555fe.pdf#page=32), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +35 +29 +Package_DFN_QFN +QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm_ThermalVias +QFN, 28 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/3555fe.pdf#page=32), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +48 +29 +Package_DFN_QFN +QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=283), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +38 +29 +Package_DFN_QFN +QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm_ThermalVias +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=283), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +55 +29 +Package_DFN_QFN +QFN-28-1EP_5x6mm_P0.5mm_EP3.65x4.65mm +QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081932_0_UHE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +41 +29 +Package_DFN_QFN +QFN-28-1EP_5x6mm_P0.5mm_EP3.65x4.65mm_ThermalVias +QFN, 28 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081932_0_UHE28.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +62 +29 +Package_DFN_QFN +QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm +QFN, 28 Pin (https://www.semtech.com/uploads/documents/sx1272.pdf#page=125), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +38 +29 +Package_DFN_QFN +QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm_ThermalVias +QFN, 28 Pin (https://www.semtech.com/uploads/documents/sx1272.pdf#page=125), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +71 +29 +Package_DFN_QFN +QFN-28-1EP_6x6mm_P0.65mm_EP4.25x4.25mm +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=289), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +38 +29 +Package_DFN_QFN +QFN-28-1EP_6x6mm_P0.65mm_EP4.25x4.25mm_ThermalVias +QFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=289), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +71 +29 +Package_DFN_QFN +QFN-28_4x4mm_P0.5mm +QFN, 28 Pin (http://www.st.com/resource/en/datasheet/stm32f031k6.pdf#page=90), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +28 +28 +Package_DFN_QFN +QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm +QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8153-8-and-16-bit-avr-microcontroller-xmega-e-atxmega8e5-atxmega16e5-atxmega32e5_datasheet.pdf (Page 70)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +37 +33 +Package_DFN_QFN +QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm_ThermalVias +QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8153-8-and-16-bit-avr-microcontroller-xmega-e-atxmega8e5-atxmega16e5-atxmega32e5_datasheet.pdf (Page 70)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +47 +33 +Package_DFN_QFN +QFN-32-1EP_4x4mm_P0.4mm_EP2.65x2.65mm +QFN, 32 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/l32.4x4a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +37 +33 +Package_DFN_QFN +QFN-32-1EP_4x4mm_P0.4mm_EP2.65x2.65mm_ThermalVias +QFN, 32 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/l32.4x4a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +59 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm +QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf (Page 20)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +42 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias +QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8008S.pdf (Page 20)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +59 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.6x3.6mm +QFN, 32 Pin (http://infocenter.nordicsemi.com/pdf/nRF52810_PS_v1.1.pdf (Page 468)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +42 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.6x3.6mm_ThermalVias +QFN, 32 Pin (http://infocenter.nordicsemi.com/pdf/nRF52810_PS_v1.1.pdf (Page 468)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +59 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm +QFN, 32 Pin (https://www.espressif.com/sites/default/files/documentation/0a-esp8285_datasheet_en.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +37 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm_ThermalVias +QFN, 32 Pin (https://www.espressif.com/sites/default/files/documentation/0a-esp8285_datasheet_en.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +59 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm +QFN, 32 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_32_05-08-1693.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +42 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.45x3.45mm_ThermalVias +QFN, 32 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_32_05-08-1693.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +59 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.65x3.65mm +QFN, 32 Pin (https://www.exar.com/ds/mxl7704.pdf (Page 35)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +42 +33 +Package_DFN_QFN +QFN-32-1EP_5x5mm_P0.5mm_EP3.65x3.65mm_ThermalVias +QFN, 32 Pin (https://www.exar.com/ds/mxl7704.pdf (Page 35)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +59 +33 +Package_DFN_QFN +QFN-32-1EP_7x7mm_P0.65mm_EP4.7x4.7mm +QFN, 32 Pin (https://www.nxp.com/docs/en/data-sheet/LPC111X.pdf (Page 108)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +49 +33 +Package_DFN_QFN +QFN-32-1EP_7x7mm_P0.65mm_EP4.7x4.7mm_ThermalVias +QFN, 32 Pin (https://www.nxp.com/docs/en/data-sheet/LPC111X.pdf (Page 108)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +75 +33 +Package_DFN_QFN +QFN-32-1EP_7x7mm_P0.65mm_EP4.65x4.65mm +QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8209-8-bit%20AVR%20ATmega16M1-32M1-64M1_Datasheet.pdf (Page 426)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +49 +33 +Package_DFN_QFN +QFN-32-1EP_7x7mm_P0.65mm_EP4.65x4.65mm_ThermalVias +QFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8209-8-bit%20AVR%20ATmega16M1-32M1-64M1_Datasheet.pdf (Page 426)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +75 +33 +Package_DFN_QFN +QFN-32-1EP_7x7mm_P0.65mm_EP5.4x5.4mm +QFN, 32 Pin (http://www.thatcorp.com/datashts/THAT_5171_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +49 +33 +Package_DFN_QFN +QFN-32-1EP_7x7mm_P0.65mm_EP5.4x5.4mm_ThermalVias +QFN, 32 Pin (http://www.thatcorp.com/datashts/THAT_5171_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +75 +33 +Package_DFN_QFN +QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.1mm +QFN, 36 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 43)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +46 +37 +Package_DFN_QFN +QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.1mm_ThermalVias +QFN, 36 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 43)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +56 +37 +Package_DFN_QFN +QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.6mm +QFN, 36 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UHE36)%20QFN%2005-08-1876%20Rev%20%C3%98.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +49 +37 +Package_DFN_QFN +QFN-36-1EP_5x6mm_P0.5mm_EP3.6x4.6mm_ThermalVias +QFN, 36 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/(UHE36)%20QFN%2005-08-1876%20Rev%20%C3%98.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +56 +37 +Package_DFN_QFN +QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm +QFN, 36 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/36L_QFN_6x6_with_3_7x3_7_EP_Punch_Dimpled_4E_C04-0241A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +46 +37 +Package_DFN_QFN +QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm_ThermalVias +QFN, 36 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/36L_QFN_6x6_with_3_7x3_7_EP_Punch_Dimpled_4E_C04-0241A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +63 +37 +Package_DFN_QFN +QFN-36-1EP_6x6mm_P0.5mm_EP4.1x4.1mm +QFN, 36 Pin (www.st.com/resource/en/datasheet/stm32f101t6.pdf (page 72)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +46 +37 +Package_DFN_QFN +QFN-36-1EP_6x6mm_P0.5mm_EP4.1x4.1mm_ThermalVias +QFN, 36 Pin (www.st.com/resource/en/datasheet/stm32f101t6.pdf (page 72)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +63 +37 +Package_DFN_QFN +QFN-38-1EP_4x6mm_P0.4mm_EP2.65x4.65mm +QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1750.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +47 +39 +Package_DFN_QFN +QFN-38-1EP_4x6mm_P0.4mm_EP2.65x4.65mm_ThermalVias +QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1750.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +56 +39 +Package_DFN_QFN +QFN-38-1EP_5x7mm_P0.5mm_EP3.15x5.15mm +QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1701.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +54 +39 +Package_DFN_QFN +QFN-38-1EP_5x7mm_P0.5mm_EP3.15x5.15mm_ThermalVias +QFN, 38 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_38_05-08-1701.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +63 +39 +Package_DFN_QFN +QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm +QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=297), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +50 +41 +Package_DFN_QFN +QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm_ThermalVias +QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=297), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +67 +41 +Package_DFN_QFN +QFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm +QFN, 40 Pin (http://www.issi.com/WW/pdf/31FL3736.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +50 +41 +Package_DFN_QFN +QFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm_ThermalVias +QFN, 40 Pin (http://www.issi.com/WW/pdf/31FL3736.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +67 +41 +Package_DFN_QFN +QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm +QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=295), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +57 +41 +Package_DFN_QFN +QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm_ThermalVias +QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=295), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +83 +41 +Package_DFN_QFN +QFN-42-1EP_5x6mm_P0.4mm_EP3.7x4.7mm +QFN, 42 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081875_0_UHE42.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +55 +43 +Package_DFN_QFN +QFN-42-1EP_5x6mm_P0.4mm_EP3.7x4.7mm_ThermalVias +QFN, 42 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/05081875_0_UHE42.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +76 +43 +Package_DFN_QFN +QFN-44-1EP_7x7mm_P0.5mm_EP5.2x5.2mm +QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/2512S.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +61 +45 +Package_DFN_QFN +QFN-44-1EP_7x7mm_P0.5mm_EP5.2x5.2mm_ThermalVias +QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/2512S.pdf#page=17), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +87 +45 +Package_DFN_QFN +QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm +QFN, 44 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_44_05-08-1763.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +61 +45 +Package_DFN_QFN +QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias +QFN, 44 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_44_05-08-1763.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +87 +45 +Package_DFN_QFN +QFN-44-1EP_8x8mm_P0.65mm_EP6.45x6.45mm +QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf#page=152), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +70 +45 +Package_DFN_QFN +QFN-44-1EP_8x8mm_P0.65mm_EP6.45x6.45mm_ThermalVias +QFN, 44 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf#page=152), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +107 +45 +Package_DFN_QFN +QFN-44-1EP_9x9mm_P0.65mm_EP7.5x7.5mm +44-Lead Plastic Quad Flat, No Lead Package - 9x9 mm Body [QFN]; see section 10.3 of https://www.parallax.com/sites/default/files/downloads/P8X32A-Propeller-Datasheet-v1.4.0_0.pdf +QFN 0.65 +0 +49 +45 +Package_DFN_QFN +QFN-44-1EP_9x9mm_P0.65mm_EP7.5x7.5mm_ThermalVias +44-Lead Plastic Quad Flat, No Lead Package - 9x9 mm Body [QFN] with thermal vias; see section 10.3 of https://www.parallax.com/sites/default/files/downloads/P8X32A-Propeller-Datasheet-v1.4.0_0.pdf +QFN 0.65 +0 +55 +45 +Package_DFN_QFN +QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm +QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +58 +49 +Package_DFN_QFN +QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm_ThermalVias +QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +75 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm +QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +58 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm_ThermalVias +QFN, 48 Pin (https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1p5.pdf#page=20), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.3x4.3mm +QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +58 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.3x4.3mm_ThermalVias +QFN, 48 Pin (https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf#page=38), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +75 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm +QFN, 48 Pin (http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.3.pdf#page=67), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +58 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.6x4.6mm_ThermalVias +QFN, 48 Pin (http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.3.pdf#page=67), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.66x4.66mm +QFN, 48 Pin (https://www.onsemi.com/pub/Collateral/485BA.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +58 +49 +Package_DFN_QFN +QFN-48-1EP_6x6mm_P0.4mm_EP4.66x4.66mm_ThermalVias +QFN, 48 Pin (https://www.onsemi.com/pub/Collateral/485BA.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm +QFN, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2041_datasheet.pdf#page=62), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +65 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm_ThermalVias +QFN, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2041_datasheet.pdf#page=62), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm +QFN, 48 Pin (http://www.st.com/resource/en/datasheet/stm32f042k6.pdf#page=94), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +65 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm_ThermalVias +QFN, 48 Pin (http://www.st.com/resource/en/datasheet/stm32f042k6.pdf#page=94), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm +QFN, 48 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_48_05-08-1704.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +65 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias +QFN, 48 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_48_05-08-1704.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.45x5.45mm +QFN, 48 Pin (http://www.thatcorp.com/datashts/THAT_626x_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +65 +49 +Package_DFN_QFN +QFN-48-1EP_7x7mm_P0.5mm_EP5.45x5.45mm_ThermalVias +QFN, 48 Pin (http://www.thatcorp.com/datashts/THAT_626x_Datasheet.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +49 +Package_DFN_QFN +QFN-48-1EP_8x8mm_P0.5mm_EP6.2x6.2mm +QFN, 48 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf#page=49), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +74 +49 +Package_DFN_QFN +QFN-48-1EP_8x8mm_P0.5mm_EP6.2x6.2mm_ThermalVias +QFN, 48 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf#page=49), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +111 +49 +Package_DFN_QFN +QFN-52-1EP_7x8mm_P0.5mm_EP5.41x6.45mm +QFN, 52 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_52_05-08-1729.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +73 +53 +Package_DFN_QFN +QFN-52-1EP_7x8mm_P0.5mm_EP5.41x6.45mm_ThermalVias +QFN, 52 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-qfn/QFN_52_05-08-1729.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +104 +53 +Package_DFN_QFN +QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm +QFN, 56 Pin (http://www.cypress.com/file/416486/download#page=40), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +73 +57 +Package_DFN_QFN +QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm_ThermalVias +QFN, 56 Pin (http://www.cypress.com/file/416486/download#page=40), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +99 +57 +Package_DFN_QFN +QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm +QFN, 56 Pin (http://www.ti.com/lit/an/scea032/scea032.pdf#page=4), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +73 +57 +Package_DFN_QFN +QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm_ThermalVias +QFN, 56 Pin (http://www.ti.com/lit/an/scea032/scea032.pdf#page=4), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +99 +57 +Package_DFN_QFN +QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm_ThermalVias_TopTented +QFN, 56 Pin top tented version (manually modified). For information see: http://www.cypress.com/file/138911/download +QFN DFN_QFN +0 +115 +57 +Package_DFN_QFN +QFN-56-1EP_8x8mm_P0.5mm_EP5.6x5.6mm +QFN, 56 Pin (http://www.ti.com/lit/ds/symlink/tlc5957.pdf#page=23), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +73 +57 +Package_DFN_QFN +QFN-56-1EP_8x8mm_P0.5mm_EP5.6x5.6mm_ThermalVias +QFN, 56 Pin (http://www.ti.com/lit/ds/symlink/tlc5957.pdf#page=23), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +99 +57 +Package_DFN_QFN +QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_8x8_with%206_5x6_5%20EP_JXX_C04-0437A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +90 +65 +Package_DFN_QFN +QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm_ThermalVias +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/64L_VQFN_8x8_with%206_5x6_5%20EP_JXX_C04-0437A.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +127 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP3.8x3.8mm +QFN, 64 Pin (https://datasheet.lcsc.com/szlcsc/Realtek-Semicon-RTL8211EG-VB-CG_C69264.pdf#page=77), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +74 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP3.8x3.8mm_ThermalVias +QFN, 64 Pin (https://datasheet.lcsc.com/szlcsc/Realtek-Semicon-RTL8211EG-VB-CG_C69264.pdf#page=77), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +79 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP4.7x4.7mm +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/60001477A.pdf (page 1083)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +74 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP4.7x4.7mm_ThermalVias +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/60001477A.pdf (page 1083)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +91 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP4.35x4.35mm +QFN, 64 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf#page=57), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +74 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP4.35x4.35mm_ThermalVias +QFN, 64 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf#page=57), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +91 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP5.4x5.4mm +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/70593d.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +81 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP5.4x5.4mm_ThermalVias +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/70593d.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +107 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP5.45x5.45mm +QFN, 64 Pin (https://www.infineon.com/dgdl/Infineon-MA12040-DS-v01_00-EN.pdf?fileId=5546d46264a8de7e0164b7467a3d617c#page=81), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +81 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP5.45x5.45mm_ThermalVias +QFN, 64 Pin (https://www.infineon.com/dgdl/Infineon-MA12040-DS-v01_00-EN.pdf?fileId=5546d46264a8de7e0164b7467a3d617c#page=81), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +107 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm +QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/tusb8041.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +81 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm_ThermalVias +QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/tusb8041.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +107 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.3x7.3mm +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00002304A.pdf (page 43)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +90 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.3x7.3mm_ThermalVias +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00002304A.pdf (page 43)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +127 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.5x7.5mm +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc7593.pdf (page 432)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +101 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.5x7.5mm_ThermalVias +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc7593.pdf (page 432)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +151 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.15x7.15mm +QFN, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/229321fa.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +90 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.15x7.15mm_ThermalVias +QFN, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/229321fa.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +127 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.25x7.25mm +64-Lead Plastic Quad Flat No-Lead Package, 9x9mm Body (see Atmel Appnote 8826) +QFN 0.5 +0 +90 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.35x7.35mm +64-Lead Plastic Quad Flat, No Lead Package (MR) - 9x9x0.9 mm Body [QFN]; (see Microchip Packaging Specification 00000049BS.pdf) +QFN 0.5 +0 +90 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.65x7.65mm +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2549-8-bit-AVR-Microcontroller-ATmega640-1280-1281-2560-2561_datasheet.pdf (page 415)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +101 +65 +Package_DFN_QFN +QFN-64-1EP_9x9mm_P0.5mm_EP7.65x7.65mm_ThermalVias +QFN, 64 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2549-8-bit-AVR-Microcontroller-ATmega640-1280-1281-2560-2561_datasheet.pdf (page 415)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +151 +65 +Package_DFN_QFN +QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm +QFN, 68 Pin (https://cdn.microsemi.com/documents/1bf6886f-5919-4508-a50b-b1dbf3fdf0f4/download/#page=98), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +85 +69 +Package_DFN_QFN +QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm_ThermalVias +QFN, 68 Pin (https://cdn.microsemi.com/documents/1bf6886f-5919-4508-a50b-b1dbf3fdf0f4/download/#page=98), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +111 +69 +Package_DFN_QFN +QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm +QFN, 72 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001682C.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +82 +73 +Package_DFN_QFN +QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm_ThermalVias +QFN, 72 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001682C.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +135 +73 +Package_DFN_QFN +QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm +QFN, 76 Pin (https://www.marvell.com/documents/bqcwxsoiqfjkcjdjhkvc/#page=19), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +86 +77 +Package_DFN_QFN +QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm_ThermalVias +QFN, 76 Pin (https://www.marvell.com/documents/bqcwxsoiqfjkcjdjhkvc/#page=19), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +QFN DFN_QFN +0 +103 +77 +Package_DFN_QFN +Qorvo_DFN-8-1EP_2x2mm_P0.5mm +DFN 8 2x2mm, 0.5mm http://www.qorvo.com/products/d/da000896 +DFN 0.5 Qorvo 2x2mm +0 +9 +9 +Package_DFN_QFN +ROHM_DFN0604-3 +DFN package size 0604 3 pins +DFN package size 0604 3 pins +0 +3 +3 +Package_DFN_QFN +ST_UFQFPN-20_3x3mm_P0.5mm +UFQFPN 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package (http://www.st.com/resource/en/datasheet/stm8s003f3.pdf) +UFQFPN 0.5 +0 +20 +20 +Package_DFN_QFN +ST_UQFN-6L_1.5x1.7mm_Pitch0.5mm +ST UQFN 6 pin 0.5mm Pitch http://www.st.com/resource/en/datasheet/ecmf02-2amx6.pdf +UQFN DFN 0.5 ST +0 +6 +6 +Package_DFN_QFN +SiliconLabs_QFN-20-1EP_3x3mm_P0.5mm +20-Lead Plastic Quad Flat, No Lead Package - 3x3 mm Body [QFN] with corner pads; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf +QFN 0.5 +0 +25 +21 +Package_DFN_QFN +SiliconLabs_QFN-20-1EP_3x3mm_P0.5mm_ThermalVias +20-Lead Plastic Quad Flat, No Lead Package - 3x3 mm Body [QFN] with corner pads and thermal vias; see figure 8.2 of https://www.silabs.com/documents/public/data-sheets/efm8bb1-datasheet.pdf +QFN 0.5 +0 +31 +21 +Package_DFN_QFN +TDFN-6-1EP_2.5x2.5mm_P0.65mm_EP1.3x2mm +TDFN, 6 Pin (http://www.nve.com/Downloads/ab3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +TDFN NoLead +0 +11 +7 +Package_DFN_QFN +TDFN-6-1EP_2.5x2.5mm_P0.65mm_EP1.3x2mm_ThermalVias +TDFN, 6 Pin (http://www.nve.com/Downloads/ab3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +TDFN NoLead +0 +18 +7 +Package_DFN_QFN +TDFN-8-1EP_3x2mm_P0.5mm_EP1.80x1.65mm +8-lead plastic dual flat, 2x3x0.75mm size, 0.5mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MN_C04-0129E-MN.pdf) +TDFN DFN 0.5mm +0 +12 +9 +Package_DFN_QFN +TDFN-8-1EP_3x2mm_P0.5mm_EP1.80x1.65mm_ThermalVias +8-lead plastic dual flat, 2x3x0.75mm size, 0.5mm pitch (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MN_C04-0129E-MN.pdf) +TDFN DFN 0.5mm +0 +17 +9 +Package_DFN_QFN +TDFN-12_2x3mm_P0.5mm +TDFN, 12 Pads, No exposed, http://www.st.com/resource/en/datasheet/stm6600.pdf +DFN +0 +12 +12 +Package_DFN_QFN +TQFN-16-1EP_3x3mm_P0.5mm_EP1.23x1.23mm +TQFN, 16 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0136.PDF (T1633-5), https://pdfserv.maximintegrated.com/land_patterns/90-0032.PDF), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +TQFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +TQFN-16-1EP_5x5mm_P0.8mm_EP3.1x3.1mm +TQFN, 16 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +TQFN NoLead +0 +21 +17 +Package_DFN_QFN +TQFN-20-1EP_5x5mm_P0.65mm_EP3.1x3.1mm +TQFN, 20 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +TQFN NoLead +0 +25 +21 +Package_DFN_QFN +TQFN-20-1EP_5x5mm_P0.65mm_EP3.1x3.1mm_ThermalVias +TQFN, 20 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0140.PDF), generated with kicad-footprint-generator ipc_noLead_generator.py +TQFN NoLead +0 +35 +21 +Package_DFN_QFN +TQFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_PullBack +TQFN, 24 Pin (https://ams.com/documents/20143/36005/AS1115_DS000206_1-00.pdf/3d3e6d35-b184-1329-adf9-2d769eb2404f), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +TQFN DFN_QFN +0 +29 +25 +Package_DFN_QFN +TQFN-24-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_PullBack_ThermalVias +TQFN, 24 Pin (https://ams.com/documents/20143/36005/AS1115_DS000206_1-00.pdf/3d3e6d35-b184-1329-adf9-2d769eb2404f), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +TQFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +Texas_DRB0008A +DFN-8, 3x3x1mm, http://www.ti.com/lit/ds/symlink/ucc24610.pdf +DRB0008A +0 +23 +9 +Package_DFN_QFN +Texas_MOF0009A +Texas Instruments, QFM MOF0009A, 6x8x2mm (http://www.ti.com/lit/ml/mpsi063a/mpsi063a.pdf) +ti qfm mof0009a +0 +24 +9 +Package_DFN_QFN +Texas_R-PUQFN-N10 +http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=MPQF186&fileType=pdf +Texas_R-PUQFN-N10 +0 +10 +10 +Package_DFN_QFN +Texas_R-PWQFN-N28_EP2.1x3.1mm +QFN, 28 Pin (http://www.ti.com/lit/ds/symlink/tps51363.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +33 +29 +Package_DFN_QFN +Texas_R-PWQFN-N28_EP2.1x3.1mm_ThermalVias +QFN, 28 Pin (http://www.ti.com/lit/ds/symlink/tps51363.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +43 +29 +Package_DFN_QFN +Texas_RGE0024C_EP2.1x2.1mm +Texas QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/pca9548a.pdf#page=34), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas QFN NoLead +0 +29 +25 +Package_DFN_QFN +Texas_RGE0024C_EP2.1x2.1mm_ThermalVias +Texas QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/pca9548a.pdf#page=34), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas QFN NoLead +0 +39 +25 +Package_DFN_QFN +Texas_RGE0024H_EP2.7x2.7mm +Texas QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas QFN NoLead +0 +29 +25 +Package_DFN_QFN +Texas_RGE0024H_EP2.7x2.7mm_ThermalVias +Texas QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas QFN NoLead +0 +39 +25 +Package_DFN_QFN +Texas_RGV_S-PVQFN-N16_EP2.1x2.1mm +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ina3221.pdf#page=44), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +21 +17 +Package_DFN_QFN +Texas_RGV_S-PVQFN-N16_EP2.1x2.1mm_ThermalVias +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ina3221.pdf#page=44), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +31 +17 +Package_DFN_QFN +Texas_RGY_R-PVQFN-N24_EP2.05x3.1mm +QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40) +QFN NoLead +0 +29 +25 +Package_DFN_QFN +Texas_RGY_R-PVQFN-N24_EP2.05x3.1mm_ThermalVias +QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq24133.pdf#page=40) +QFN NoLead +0 +36 +25 +Package_DFN_QFN +Texas_RNN0018A +Texas Instruments, VQFN-HR RNN0018A (http://www.ti.com/lit/ds/symlink/tps568215.pdf) +ti vqfn-hr rnn0018a +0 +26 +18 +Package_DFN_QFN +Texas_RUM0016A_EP2.6x2.6mm +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +21 +17 +Package_DFN_QFN +Texas_RUM0016A_EP2.6x2.6mm_ThermalVias +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/lmh0074.pdf#page=13), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +31 +17 +Package_DFN_QFN +Texas_RWH0032A +Texas Instruments, RWH0032A, 8x8x0.9mm (http://www.ti.com/lit/ds/snosd10c/snosd10c.pdf) +ti rwh0032a +0 +71 +33 +Package_DFN_QFN +Texas_RWH0032A_ThermalVias +Texas Instruments, RWH0032A, 8x8x0.9mm (http://www.ti.com/lit/ds/snosd10c/snosd10c.pdf) +ti rwh0032a +0 +94 +33 +Package_DFN_QFN +Texas_R_PUQFN-N12 +Texas_R_PUQFN-N12 http://www.ti.com/lit/ds/symlink/txb0104.pdf +Texas_R_PUQFN-N12 +0 +13 +12 +Package_DFN_QFN +Texas_S-PDSO-N10_EP1.2x2mm +DFN, 10 Pin (http://www.ti.com/lit/ds/symlink/tps7a91.pdf#page=30), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +15 +11 +Package_DFN_QFN +Texas_S-PDSO-N10_EP1.2x2mm_ThermalVias +DFN, 10 Pin (http://www.ti.com/lit/ds/symlink/tps7a91.pdf#page=30), generated with kicad-footprint-generator ipc_noLead_generator.py +DFN NoLead +0 +22 +11 +Package_DFN_QFN +Texas_S-PVQFN-N14 +Texas_S-PVQFN-N14 http://www.ti.com/lit/ds/symlink/txb0104.pdf +Texas_S-PVQFN-N14_4.3x4.3_Pitch0.5mm_ThermalPad +0 +19 +15 +Package_DFN_QFN +Texas_S-PVQFN-N14_ThermalVias +Texas_S-PVQFN-N14_ThermalVias http://www.ti.com/lit/ds/symlink/txb0104.pdf +Texas_S-PVQFN-N14_ThermalVias +0 +24 +15 +Package_DFN_QFN +Texas_S-PVQFN-N16_EP2.7x2.7mm +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/msp430g2001.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +26 +17 +Package_DFN_QFN +Texas_S-PVQFN-N16_EP2.7x2.7mm_ThermalVias +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/msp430g2001.pdf#page=43), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +31 +17 +Package_DFN_QFN +Texas_S-PVQFN-N20_EP2.4x2.4mm +QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/cc1101.pdf#page=101), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +25 +21 +Package_DFN_QFN +Texas_S-PVQFN-N20_EP2.4x2.4mm_ThermalVias +QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/cc1101.pdf#page=101), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +35 +21 +Package_DFN_QFN +Texas_S-PVQFN-N20_EP2.7x2.7mm +QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/drv8662.pdf#page=23), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +25 +21 +Package_DFN_QFN +Texas_S-PVQFN-N20_EP2.7x2.7mm_ThermalVias +QFN, 20 Pin (http://www.ti.com/lit/ds/symlink/drv8662.pdf#page=23), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +35 +21 +Package_DFN_QFN +Texas_S-PVQFN-N20_EP3.15x3.15mm +QFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +25 +21 +Package_DFN_QFN +Texas_S-PVQFN-N20_EP3.15x3.15mm_ThermalVias +QFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +47 +21 +Package_DFN_QFN +Texas_S-PVQFN-N24_EP2.1x2.1mm +QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5720.pdf#page=111), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +29 +25 +Package_DFN_QFN +Texas_S-PVQFN-N24_EP2.1x2.1mm_ThermalVias +QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5720.pdf#page=111), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +39 +25 +Package_DFN_QFN +Texas_S-PVQFN-N32_EP3.45x3.45mm +QFN, 32 Pin (http://www.ti.com/lit/ds/symlink/msp430f1122.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +42 +33 +Package_DFN_QFN +Texas_S-PVQFN-N32_EP3.45x3.45mm_ThermalVias +QFN, 32 Pin (http://www.ti.com/lit/ds/symlink/msp430f1122.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +59 +33 +Package_DFN_QFN +Texas_S-PVQFN-N36_EP4.4x4.4mm +QFN, 36 Pin (http://www.ti.com/lit/ds/slvsba5d/slvsba5d.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +46 +37 +Package_DFN_QFN +Texas_S-PVQFN-N36_EP4.4x4.4mm_ThermalVias +QFN, 36 Pin (http://www.ti.com/lit/ds/slvsba5d/slvsba5d.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +79 +37 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP2.9x2.9mm +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5731.pdf#page=114), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +45 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP2.9x2.9mm_ThermalVias +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430fr5731.pdf#page=114), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +55 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP3.52x2.62mm +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/drv8308.pdf#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +47 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP3.52x2.62mm_ThermalVias +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/drv8308.pdf#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +60 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP4.6x4.6mm +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/dac7750.pdf#page=55), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +50 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP4.6x4.6mm_ThermalVias +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/dac7750.pdf#page=55), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +83 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP4.15x4.15mm +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +50 +41 +Package_DFN_QFN +Texas_S-PVQFN-N40_EP4.15x4.15mm_ThermalVias +QFN, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +83 +41 +Package_DFN_QFN +Texas_S-PVQFN-N48_EP5.15x5.15mm +QFN, 48 Pin (http://www.ti.com/lit/ds/symlink/msp430f5232.pdf#page=112), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +65 +49 +Package_DFN_QFN +Texas_S-PVQFN-N48_EP5.15x5.15mm_ThermalVias +QFN, 48 Pin (http://www.ti.com/lit/ds/symlink/msp430f5232.pdf#page=112), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +111 +49 +Package_DFN_QFN +Texas_S-PVQFN-N64_EP4.25x4.25mm +QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/msp430f5217.pdf#page=117), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +69 +65 +Package_DFN_QFN +Texas_S-PVQFN-N64_EP4.25x4.25mm_ThermalVias +QFN, 64 Pin (http://www.ti.com/lit/ds/symlink/msp430f5217.pdf#page=117), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +127 +65 +Package_DFN_QFN +Texas_S-PWQFN-N16_EP2.1x2.1mm +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +21 +17 +Package_DFN_QFN +Texas_S-PWQFN-N16_EP2.1x2.1mm_ThermalVias +QFN, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +31 +17 +Package_DFN_QFN +Texas_S-PWQFN-N20 +20-Pin Plastic Quad Flatpack No-Lead Package, Body 3.0x3.0x0.8mm, Texas Instruments (http://www.ti.com/lit/ds/symlink/tps22993.pdf) +QFN 0.4 +0 +24 +20 +Package_DFN_QFN +Texas_S-PWQFN-N24_EP2.7x2.7mm +QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +29 +25 +Package_DFN_QFN +Texas_S-PWQFN-N24_EP2.7x2.7mm_ThermalVias +QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +39 +25 +Package_DFN_QFN +Texas_S-PWQFN-N32_EP2.8x2.8mm +QFN, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=91), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +37 +33 +Package_DFN_QFN +Texas_S-PWQFN-N32_EP2.8x2.8mm_ThermalVias +QFN, 32 Pin (https://www.ti.com/lit/ds/symlink/bq25703a.pdf#page=91), generated with kicad-footprint-generator ipc_noLead_generator.py +QFN NoLead +0 +47 +33 +Package_DFN_QFN +Texas_S-PWQFN-N100_EP5.5x5.5mm +http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/lit/ds/sllse76m/sllse76m.pdf +MultiRow QFN +0 +114 +105 +Package_DFN_QFN +Texas_S-PWQFN-N100_EP5.5x5.5mm_ThermalVias +http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/lit/ds/sllse76m/sllse76m.pdf +MultiRow QFN +0 +131 +105 +Package_DFN_QFN +Texas_S-PX2QFN-14 +Texas QFN, 14 Pin (http://www.ti.com/lit/ds/symlink/tlv9004.pdf#page=64), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas QFN NoLead +0 +14 +14 +Package_DFN_QFN +Texas_VQFN-RHL-20 +http://www.ti.com/lit/ds/symlink/bq51050b.pdf +RHL0020A +0 +33 +21 +Package_DFN_QFN +Texas_VQFN-RHL-20_ThermalVias +http://www.ti.com/lit/ds/symlink/bq51050b.pdf +RHL0020A +0 +41 +21 +Package_DFN_QFN +Texas_VSON-HR-8_1.5x2mm_P0.5mm +Texas VSON-HR, 8 Pin (http://www.ti.com/lit/ds/symlink/tps62823.pdf#page=29), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas VSON-HR NoLead +0 +8 +8 +Package_DFN_QFN +Texas_WQFN-MR-100_3x3-DapStencil +http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=mpqf258&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=LPPD235&fileType=pdf +MultiRow QFN +0 +113 +105 +Package_DFN_QFN +Texas_WQFN-MR-100_ThermalVias_3x3-DapStencil +http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=szza059&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=mpqf258&fileType=pdf,http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=LPPD235&fileType=pdf +MultiRow QFN +0 +126 +105 +Package_DFN_QFN +Texas_X2QFN-12_1.6x1.6mm_P0.4mm +Texas X2QFN, 12 Pin (http://www.ti.com/lit/ml/mpqf391c/mpqf391c.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +Texas X2QFN DFN_QFN +0 +12 +12 +Package_DFN_QFN +UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm +UDFN-4_1x1mm_P0.65mm, http://ww1.microchip.com/downloads/en/DeviceDoc/MIC550x-300mA-Single-Output-LDO-in-Small-Packages-DS20006006A.pdf +UDFN-4_1x1mm_P0.65mm +0 +5 +5 +Package_DFN_QFN +UDFN-9_1.0x3.8mm_P0.5mm +9-pin UDFN package, 1.0x3.8mm, (Ref: https://katalog.we-online.de/pbs/datasheet/824014881.pdf) +UDFN SMD +0 +9 +9 +Package_DFN_QFN +UDFN-10_1.35x2.6mm_P0.5mm +http://www.st.com/content/ccc/resource/technical/document/datasheet/f2/11/8a/ed/40/31/40/56/DM00088292.pdf/files/DM00088292.pdf/jcr:content/translations/en.DM00088292.pdf +UDFN 0.5 uQFN +0 +10 +10 +Package_DFN_QFN +UQFN-10_1.3x1.8mm_P0.4mm +UQFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 9)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +UQFN DFN_QFN +0 +10 +10 +Package_DFN_QFN +UQFN-10_1.4x1.8mm_P0.4mm +UQFN 10pin, https://www.onsemi.com/pub/Collateral/488AT.PDF +UQFN-10_1.4x1.8mm_P0.4mm +0 +10 +10 +Package_DFN_QFN +UQFN-10_1.6x2.1mm_P0.5mm +UQFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 12)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +UQFN DFN_QFN +0 +10 +10 +Package_DFN_QFN +UQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm +16-Lead Ultra Thin Quad Flat, No Lead Package (UC) - 3x3x0.5 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf) +QFN 0.5 +0 +21 +17 +Package_DFN_QFN +UQFN-16-1EP_4x4mm_P0.65mm_EP2.6x2.6mm +UQFN, 16 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/16L_UQFN_4x4x0_5mm_JQ_C04257A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +UQFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +UQFN-16-1EP_4x4mm_P0.65mm_EP2.6x2.6mm_ThermalVias +UQFN, 16 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/16L_UQFN_4x4x0_5mm_JQ_C04257A.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +UQFN DFN_QFN +0 +31 +17 +Package_DFN_QFN +UQFN-16-1EP_4x4mm_P0.65mm_EP2.7x2.7mm +16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf) +QFN 0.65 +0 +21 +17 +Package_DFN_QFN +UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm +UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=332), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +25 +21 +Package_DFN_QFN +UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm_ThermalVias +UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=332), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +30 +21 +Package_DFN_QFN +UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm +UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +25 +21 +Package_DFN_QFN +UQFN-20-1EP_4x4mm_P0.5mm_EP2.8x2.8mm_ThermalVias +UQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001839B.pdf#page=464), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +35 +21 +Package_DFN_QFN +UQFN-28-1EP_4x4mm_P0.4mm_EP2.35x2.35mm +UQFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=338), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +33 +29 +Package_DFN_QFN +UQFN-28-1EP_4x4mm_P0.4mm_EP2.35x2.35mm_ThermalVias +UQFN, 28 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=338), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +43 +29 +Package_DFN_QFN +UQFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm +UQFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=345), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +50 +41 +Package_DFN_QFN +UQFN-40-1EP_5x5mm_P0.4mm_EP3.8x3.8mm_ThermalVias +UQFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=345), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +67 +41 +Package_DFN_QFN +UQFN-48-1EP_6x6mm_P0.4mm_EP4.45x4.45mm +UQFN, 48 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=347), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +58 +49 +Package_DFN_QFN +UQFN-48-1EP_6x6mm_P0.4mm_EP4.45x4.45mm_ThermalVias +UQFN, 48 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=347), generated with kicad-footprint-generator ipc_noLead_generator.py +UQFN NoLead +0 +75 +49 +Package_DFN_QFN +UQFN-48-1EP_6x6mm_P0.4mm_EP4.62x4.62mm +UQFN, 48 Pin (https://github.com/KiCad/kicad-symbols/pull/1189#issuecomment-449506354), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +UQFN DFN_QFN +0 +53 +49 +Package_DFN_QFN +UQFN-48-1EP_6x6mm_P0.4mm_EP4.62x4.62mm_ThermalVias +UQFN, 48 Pin (https://github.com/KiCad/kicad-symbols/pull/1189#issuecomment-449506354), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +UQFN DFN_QFN +0 +75 +49 +Package_DFN_QFN +VDFN-8-1EP_2x2mm_P0.5mm_EP0.9x1.7mm +8-Lead Very Thin Dual Flatpack No-Lead (LZ) - 2x3x0.9 mm Body [VDFN] (see Microchip Packaging Specification 00000049BS.pdf) +DFN 0.5 +0 +11 +9 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm +VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/cdclvp1102.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +21 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias +VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/cdclvp1102.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +26 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm +VQFN, 16 Pin (https://www.st.com/resource/en/datasheet/stspin220.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.8x1.8mm_ThermalVias +VQFN, 16 Pin (https://www.st.com/resource/en/datasheet/stspin220.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +26 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm +VQFN, 16 Pin (http://www.ti.com/lit/ds/sbos354a/sbos354a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.45x1.45mm_ThermalVias +VQFN, 16 Pin (http://www.ti.com/lit/ds/sbos354a/sbos354a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +26 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.68x1.68mm +VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/tlv62095.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +21 +17 +Package_DFN_QFN +VQFN-16-1EP_3x3mm_P0.5mm_EP1.68x1.68mm_ThermalVias +VQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/tlv62095.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +26 +17 +Package_DFN_QFN +VQFN-20-1EP_3x3mm_P0.4mm_EP1.7x1.7mm +VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +25 +21 +Package_DFN_QFN +VQFN-20-1EP_3x3mm_P0.4mm_EP1.7x1.7mm_ThermalVias +VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20%20Lead%20VQFN%203x3x0_9mm_1_7EP%20U2B%20C04-21496a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +30 +21 +Package_DFN_QFN +VQFN-20-1EP_3x3mm_P0.45mm_EP1.55x1.55mm +VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=264), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +25 +21 +Package_DFN_QFN +VQFN-20-1EP_3x3mm_P0.45mm_EP1.55x1.55mm_ThermalVias +VQFN, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf#page=264), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +30 +21 +Package_DFN_QFN +VQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm +VQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430f1101a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +34 +25 +Package_DFN_QFN +VQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias +VQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/msp430f1101a.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +39 +25 +Package_DFN_QFN +VQFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm +VQFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-9505-AT42-QTouch-BSW-AT42QT1060_Datasheet.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +33 +29 +Package_DFN_QFN +VQFN-28-1EP_4x4mm_P0.45mm_EP2.4x2.4mm_ThermalVias +VQFN, 28 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-9505-AT42-QTouch-BSW-AT42QT1060_Datasheet.pdf#page=28), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +43 +29 +Package_DFN_QFN +VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm +VQFN, 28 Pin (http://www.ti.com/lit/ds/symlink/lm5175.pdf#page=37), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +35 +29 +Package_DFN_QFN +VQFN-28-1EP_4x5mm_P0.5mm_EP2.55x3.55mm_ThermalVias +VQFN, 28 Pin (http://www.ti.com/lit/ds/symlink/lm5175.pdf#page=37), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py +VQFN DFN_QFN +0 +48 +29 +Package_DFN_QFN +VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm +VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/devicedoc/atmel-9520-at42-qtouch-bsw-at42qt1110_datasheet.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +37 +33 +Package_DFN_QFN +VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm_ThermalVias +VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/devicedoc/atmel-9520-at42-qtouch-bsw-at42qt1110_datasheet.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +47 +33 +Package_DFN_QFN +VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm +VQFN, 32 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf#page=40), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +37 +33 +Package_DFN_QFN +VQFN-32-1EP_5x5mm_P0.5mm_EP3.5x3.5mm_ThermalVias +VQFN, 32 Pin (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4222H.pdf#page=40), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +47 +33 +Package_DFN_QFN +VQFN-46-1EP_5x6mm_P0.4mm_EP2.8x3.8mm +VQFN, 46 Pin (http://www.ti.com/lit/ds/symlink/lp5036.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +53 +47 +Package_DFN_QFN +VQFN-46-1EP_5x6mm_P0.4mm_EP2.8x3.8mm_ThermalVias +VQFN, 46 Pin (http://www.ti.com/lit/ds/symlink/lp5036.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +66 +47 +Package_DFN_QFN +VQFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm +VQFN, 48 Pin (http://www.ti.com/lit/ds/symlink/cc1312r.pdf#page=48), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +53 +49 +Package_DFN_QFN +VQFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm_ThermalVias +VQFN, 48 Pin (http://www.ti.com/lit/ds/symlink/cc1312r.pdf#page=48), generated with kicad-footprint-generator ipc_noLead_generator.py +VQFN NoLead +0 +79 +49 +Package_DFN_QFN +WDFN-8-1EP_2x2.2mm_P0.5mm_EP0.80x0.54 +https://www.onsemi.com/pub/Collateral/511BN.PDF +WDFN-8 1EP 2.2X2.0 0.5P +0 +9 +9 +Package_DFN_QFN +WDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm +WDFN, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/8L_TDFN_2x3_MNY_C04-0129E-MNY.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +WDFN NoLead +0 +13 +9 +Package_DFN_QFN +WDFN-8_2x2mm_P0.5mm +DFN8 2x2, 0.5P; No exposed pad (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF) +DFN 0.5 +0 +8 +8 +Package_DFN_QFN +WDFN-12-1EP_3x3mm_P0.45mm_EP1.7x2.5mm +WDFN, 12 Pin (https://www.diodes.com/assets/Datasheets/PAM2306.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +WDFN NoLead +0 +17 +13 +Package_DFN_QFN +WQFN-14-1EP_2.5x2.5mm_P0.5mm_EP1.45x1.45mm +WQFN, 14 Pin (https://www.onsemi.com/pub/Collateral/FUSB302B-D.PDF#page=32), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +19 +15 +Package_DFN_QFN +WQFN-14-1EP_2.5x2.5mm_P0.5mm_EP1.45x1.45mm_ThermalVias +WQFN, 14 Pin (https://www.onsemi.com/pub/Collateral/FUSB302B-D.PDF#page=32), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +24 +15 +Package_DFN_QFN +WQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm +WQFN, 16 Pin (https://www.onsemi.com/pub/Collateral/FUSB307B-D.PDF#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +21 +17 +Package_DFN_QFN +WQFN-16-1EP_3x3mm_P0.5mm_EP1.75x1.75mm_ThermalVias +WQFN, 16 Pin (https://www.onsemi.com/pub/Collateral/FUSB307B-D.PDF#page=56), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +26 +17 +Package_DFN_QFN +WQFN-16-1EP_4x4mm_P0.5mm_EP2.6x2.6mm +WQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +21 +17 +Package_DFN_QFN +WQFN-16-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias +WQFN, 16 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=59), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +31 +17 +Package_DFN_QFN +WQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x2.9mm +http://www.onsemi.com/pub/Collateral/510CD.PDF +WQFN-20 4.5mm 2.5mm 0.5mm +0 +24 +21 +Package_DFN_QFN +WQFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm +WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/lm26480.pdf#page=39), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +29 +25 +Package_DFN_QFN +WQFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm_ThermalVias +WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/lm26480.pdf#page=39), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +39 +25 +Package_DFN_QFN +WQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm +WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/ts3a27518e.pdf#page=33), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +29 +25 +Package_DFN_QFN +WQFN-24-1EP_4x4mm_P0.5mm_EP2.45x2.45mm_ThermalVias +WQFN, 24 Pin (http://www.ti.com/lit/ds/symlink/ts3a27518e.pdf#page=33), generated with kicad-footprint-generator ipc_noLead_generator.py +WQFN NoLead +0 +39 +25 +Package_DFN_QFN +WQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm +QFN, 32-Leads, Body 5x5x0.8mm, Pitch 0.5mm, Thermal Pad 3.1x3.1mm; (see Texas Instruments LM25119 http://www.ti.com/lit/ds/symlink/lm25119.pdf) +WQFN 0.5 +0 +37 +33 +Package_DIP +DIP-4_W7.62mm +4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +4 +4 +Package_DIP +DIP-4_W7.62mm_LongPads +4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +4 +4 +Package_DIP +DIP-4_W7.62mm_SMDSocket_SmallPads +4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +4 +4 +Package_DIP +DIP-4_W7.62mm_Socket +4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +4 +4 +Package_DIP +DIP-4_W7.62mm_Socket_LongPads +4-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +4 +4 +Package_DIP +DIP-4_W8.89mm_SMDSocket_LongPads +4-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +4 +4 +Package_DIP +DIP-4_W10.16mm +4-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +4 +4 +Package_DIP +DIP-4_W10.16mm_LongPads +4-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +4 +4 +Package_DIP +DIP-5-6_W7.62mm +5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +5 +5 +Package_DIP +DIP-5-6_W7.62mm_LongPads +5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +5 +5 +Package_DIP +DIP-5-6_W7.62mm_SMDSocket_SmallPads +5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +5 +5 +Package_DIP +DIP-5-6_W7.62mm_Socket +5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +5 +5 +Package_DIP +DIP-5-6_W7.62mm_Socket_LongPads +5-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +5 +5 +Package_DIP +DIP-5-6_W8.89mm_SMDSocket_LongPads +5-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +5 +5 +Package_DIP +DIP-5-6_W10.16mm +5-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +5 +5 +Package_DIP +DIP-5-6_W10.16mm_LongPads +5-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +5 +5 +Package_DIP +DIP-6_W7.62mm +6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +6 +6 +Package_DIP +DIP-6_W7.62mm_LongPads +6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +6 +6 +Package_DIP +DIP-6_W7.62mm_SMDSocket_SmallPads +6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +6 +6 +Package_DIP +DIP-6_W7.62mm_Socket +6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +6 +6 +Package_DIP +DIP-6_W7.62mm_Socket_LongPads +6-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +6 +6 +Package_DIP +DIP-6_W8.89mm_SMDSocket_LongPads +6-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +6 +6 +Package_DIP +DIP-6_W10.16mm +6-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +6 +6 +Package_DIP +DIP-6_W10.16mm_LongPads +6-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +6 +6 +Package_DIP +DIP-8-16_W7.62mm +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +8 +8 +Package_DIP +DIP-8-16_W7.62mm_Socket +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +8 +8 +Package_DIP +DIP-8-16_W7.62mm_Socket_LongPads +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +8 +8 +Package_DIP +DIP-8-N6_W7.62mm +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 6 +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +7 +7 +Package_DIP +DIP-8-N7_W7.62mm +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), missing pin 7 +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +7 +7 +Package_DIP +DIP-8_W7.62mm +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +8 +8 +Package_DIP +DIP-8_W7.62mm_LongPads +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +8 +8 +Package_DIP +DIP-8_W7.62mm_SMDSocket_SmallPads +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +8 +8 +Package_DIP +DIP-8_W7.62mm_Socket +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +8 +8 +Package_DIP +DIP-8_W7.62mm_Socket_LongPads +8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +8 +8 +Package_DIP +DIP-8_W8.89mm_SMDSocket_LongPads +8-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +8 +8 +Package_DIP +DIP-8_W10.16mm +8-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +8 +8 +Package_DIP +DIP-8_W10.16mm_LongPads +8-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +8 +8 +Package_DIP +DIP-10_W7.62mm +10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +10 +10 +Package_DIP +DIP-10_W7.62mm_LongPads +10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +10 +10 +Package_DIP +DIP-10_W7.62mm_SMDSocket_SmallPads +10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +10 +10 +Package_DIP +DIP-10_W7.62mm_Socket +10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +10 +10 +Package_DIP +DIP-10_W7.62mm_Socket_LongPads +10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +10 +10 +Package_DIP +DIP-10_W8.89mm_SMDSocket_LongPads +10-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +10 +10 +Package_DIP +DIP-10_W10.16mm +10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +10 +10 +Package_DIP +DIP-10_W10.16mm_LongPads +10-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +10 +10 +Package_DIP +DIP-12_W7.62mm +12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +12 +12 +Package_DIP +DIP-12_W7.62mm_LongPads +12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +12 +12 +Package_DIP +DIP-12_W7.62mm_SMDSocket_SmallPads +12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +12 +12 +Package_DIP +DIP-12_W7.62mm_Socket +12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +12 +12 +Package_DIP +DIP-12_W7.62mm_Socket_LongPads +12-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +12 +12 +Package_DIP +DIP-12_W8.89mm_SMDSocket_LongPads +12-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +12 +12 +Package_DIP +DIP-12_W10.16mm +12-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +12 +12 +Package_DIP +DIP-12_W10.16mm_LongPads +12-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +12 +12 +Package_DIP +DIP-14_W7.62mm +14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +14 +14 +Package_DIP +DIP-14_W7.62mm_LongPads +14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +14 +14 +Package_DIP +DIP-14_W7.62mm_SMDSocket_SmallPads +14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +14 +14 +Package_DIP +DIP-14_W7.62mm_Socket +14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +14 +14 +Package_DIP +DIP-14_W7.62mm_Socket_LongPads +14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +14 +14 +Package_DIP +DIP-14_W8.89mm_SMDSocket_LongPads +14-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +14 +14 +Package_DIP +DIP-14_W10.16mm +14-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +14 +14 +Package_DIP +DIP-14_W10.16mm_LongPads +14-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +14 +14 +Package_DIP +DIP-16_W7.62mm +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +16 +16 +Package_DIP +DIP-16_W7.62mm_LongPads +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +16 +16 +Package_DIP +DIP-16_W7.62mm_SMDSocket_SmallPads +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +16 +16 +Package_DIP +DIP-16_W7.62mm_Socket +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +16 +16 +Package_DIP +DIP-16_W7.62mm_Socket_LongPads +16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +16 +16 +Package_DIP +DIP-16_W8.89mm_SMDSocket_LongPads +16-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +16 +16 +Package_DIP +DIP-16_W10.16mm +16-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +16 +16 +Package_DIP +DIP-16_W10.16mm_LongPads +16-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +16 +16 +Package_DIP +DIP-18_W7.62mm +18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +18 +18 +Package_DIP +DIP-18_W7.62mm_LongPads +18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +18 +18 +Package_DIP +DIP-18_W7.62mm_SMDSocket_SmallPads +18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +18 +18 +Package_DIP +DIP-18_W7.62mm_Socket +18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +18 +18 +Package_DIP +DIP-18_W7.62mm_Socket_LongPads +18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +18 +18 +Package_DIP +DIP-18_W8.89mm_SMDSocket_LongPads +18-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +18 +18 +Package_DIP +DIP-20_W7.62mm +20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +20 +20 +Package_DIP +DIP-20_W7.62mm_LongPads +20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +20 +20 +Package_DIP +DIP-20_W7.62mm_SMDSocket_SmallPads +20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +20 +20 +Package_DIP +DIP-20_W7.62mm_Socket +20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +20 +20 +Package_DIP +DIP-20_W7.62mm_Socket_LongPads +20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +20 +20 +Package_DIP +DIP-20_W8.89mm_SMDSocket_LongPads +20-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +20 +20 +Package_DIP +DIP-22_W7.62mm +22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +22 +22 +Package_DIP +DIP-22_W7.62mm_LongPads +22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +22 +22 +Package_DIP +DIP-22_W7.62mm_SMDSocket_SmallPads +22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +22 +22 +Package_DIP +DIP-22_W7.62mm_Socket +22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +22 +22 +Package_DIP +DIP-22_W7.62mm_Socket_LongPads +22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +22 +22 +Package_DIP +DIP-22_W8.89mm_SMDSocket_LongPads +22-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +22 +22 +Package_DIP +DIP-22_W10.16mm +22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +22 +22 +Package_DIP +DIP-22_W10.16mm_LongPads +22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +22 +22 +Package_DIP +DIP-22_W10.16mm_SMDSocket_SmallPads +22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil SMDSocket SmallPads +0 +22 +22 +Package_DIP +DIP-22_W10.16mm_Socket +22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket +THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket +0 +22 +22 +Package_DIP +DIP-22_W10.16mm_Socket_LongPads +22-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket LongPads +0 +22 +22 +Package_DIP +DIP-22_W11.43mm_SMDSocket_LongPads +22-lead though-hole mounted DIP package, row spacing 11.43 mm (450 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 11.43mm 450mil SMDSocket LongPads +0 +22 +22 +Package_DIP +DIP-24_W7.62mm +24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +24 +24 +Package_DIP +DIP-24_W7.62mm_LongPads +24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +24 +24 +Package_DIP +DIP-24_W7.62mm_SMDSocket_SmallPads +24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +24 +24 +Package_DIP +DIP-24_W7.62mm_Socket +24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +24 +24 +Package_DIP +DIP-24_W7.62mm_Socket_LongPads +24-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +24 +24 +Package_DIP +DIP-24_W8.89mm_SMDSocket_LongPads +24-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +24 +24 +Package_DIP +DIP-24_W10.16mm +24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils) +THT DIP DIL PDIP 2.54mm 10.16mm 400mil +0 +24 +24 +Package_DIP +DIP-24_W10.16mm_LongPads +24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil LongPads +0 +24 +24 +Package_DIP +DIP-24_W10.16mm_SMDSocket_SmallPads +24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil SMDSocket SmallPads +0 +24 +24 +Package_DIP +DIP-24_W10.16mm_Socket +24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket +THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket +0 +24 +24 +Package_DIP +DIP-24_W10.16mm_Socket_LongPads +24-lead though-hole mounted DIP package, row spacing 10.16 mm (400 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 10.16mm 400mil Socket LongPads +0 +24 +24 +Package_DIP +DIP-24_W11.43mm_SMDSocket_LongPads +24-lead though-hole mounted DIP package, row spacing 11.43 mm (450 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 11.43mm 450mil SMDSocket LongPads +0 +24 +24 +Package_DIP +DIP-24_W15.24mm +24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +24 +24 +Package_DIP +DIP-24_W15.24mm_LongPads +24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +24 +24 +Package_DIP +DIP-24_W15.24mm_SMDSocket_SmallPads +24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +24 +24 +Package_DIP +DIP-24_W15.24mm_Socket +24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +24 +24 +Package_DIP +DIP-24_W15.24mm_Socket_LongPads +24-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +24 +24 +Package_DIP +DIP-24_W16.51mm_SMDSocket_LongPads +24-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +24 +24 +Package_DIP +DIP-28_W7.62mm +28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils) +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +28 +28 +Package_DIP +DIP-28_W7.62mm_LongPads +28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +28 +28 +Package_DIP +DIP-28_W7.62mm_SMDSocket_SmallPads +28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil SMDSocket SmallPads +0 +28 +28 +Package_DIP +DIP-28_W7.62mm_Socket +28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket +0 +28 +28 +Package_DIP +DIP-28_W7.62mm_Socket_LongPads +28-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads +0 +28 +28 +Package_DIP +DIP-28_W8.89mm_SMDSocket_LongPads +28-lead though-hole mounted DIP package, row spacing 8.89 mm (350 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 8.89mm 350mil SMDSocket LongPads +0 +28 +28 +Package_DIP +DIP-28_W15.24mm +28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +28 +28 +Package_DIP +DIP-28_W15.24mm_LongPads +28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +28 +28 +Package_DIP +DIP-28_W15.24mm_SMDSocket_SmallPads +28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +28 +28 +Package_DIP +DIP-28_W15.24mm_Socket +28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +28 +28 +Package_DIP +DIP-28_W15.24mm_Socket_LongPads +28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +28 +28 +Package_DIP +DIP-28_W16.51mm_SMDSocket_LongPads +28-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +28 +28 +Package_DIP +DIP-32_W7.62mm +32-lead dip package, row spacing 7.62 mm (300 mils) +DIL DIP PDIP 2.54mm 7.62mm 300mil +0 +32 +32 +Package_DIP +DIP-32_W15.24mm +32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +32 +32 +Package_DIP +DIP-32_W15.24mm_LongPads +32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +32 +32 +Package_DIP +DIP-32_W15.24mm_SMDSocket_SmallPads +32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +32 +32 +Package_DIP +DIP-32_W15.24mm_Socket +32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +32 +32 +Package_DIP +DIP-32_W15.24mm_Socket_LongPads +32-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +32 +32 +Package_DIP +DIP-32_W16.51mm_SMDSocket_LongPads +32-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +32 +32 +Package_DIP +DIP-40_W15.24mm +40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +40 +40 +Package_DIP +DIP-40_W15.24mm_LongPads +40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +40 +40 +Package_DIP +DIP-40_W15.24mm_SMDSocket_SmallPads +40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +40 +40 +Package_DIP +DIP-40_W15.24mm_Socket +40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +40 +40 +Package_DIP +DIP-40_W15.24mm_Socket_LongPads +40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +40 +40 +Package_DIP +DIP-40_W16.51mm_SMDSocket_LongPads +40-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +40 +40 +Package_DIP +DIP-40_W25.4mm +40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils) +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil +0 +40 +40 +Package_DIP +DIP-40_W25.4mm_LongPads +40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), LongPads +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil LongPads +0 +40 +40 +Package_DIP +DIP-40_W25.4mm_SMDSocket_SmallPads +40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil SMDSocket SmallPads +0 +40 +40 +Package_DIP +DIP-40_W25.4mm_Socket +40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket +0 +40 +40 +Package_DIP +DIP-40_W25.4mm_Socket_LongPads +40-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket LongPads +0 +40 +40 +Package_DIP +DIP-40_W26.67mm_SMDSocket_LongPads +40-lead though-hole mounted DIP package, row spacing 26.67 mm (1050 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 26.669999999999998mm 1050mil SMDSocket LongPads +0 +40 +40 +Package_DIP +DIP-42_W15.24mm +42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +42 +42 +Package_DIP +DIP-42_W15.24mm_LongPads +42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +42 +42 +Package_DIP +DIP-42_W15.24mm_SMDSocket_SmallPads +42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +42 +42 +Package_DIP +DIP-42_W15.24mm_Socket +42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +42 +42 +Package_DIP +DIP-42_W15.24mm_Socket_LongPads +42-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +42 +42 +Package_DIP +DIP-42_W16.51mm_SMDSocket_LongPads +42-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +42 +42 +Package_DIP +DIP-48_W15.24mm +48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +48 +48 +Package_DIP +DIP-48_W15.24mm_LongPads +48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +48 +48 +Package_DIP +DIP-48_W15.24mm_SMDSocket_SmallPads +48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +48 +48 +Package_DIP +DIP-48_W15.24mm_Socket +48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +48 +48 +Package_DIP +DIP-48_W15.24mm_Socket_LongPads +48-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +48 +48 +Package_DIP +DIP-48_W16.51mm_SMDSocket_LongPads +48-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +48 +48 +Package_DIP +DIP-64_W15.24mm +64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils) +THT DIP DIL PDIP 2.54mm 15.24mm 600mil +0 +64 +64 +Package_DIP +DIP-64_W15.24mm_LongPads +64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil LongPads +0 +64 +64 +Package_DIP +DIP-64_W15.24mm_SMDSocket_SmallPads +64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil SMDSocket SmallPads +0 +64 +64 +Package_DIP +DIP-64_W15.24mm_Socket +64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket +0 +64 +64 +Package_DIP +DIP-64_W15.24mm_Socket_LongPads +64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket LongPads +0 +64 +64 +Package_DIP +DIP-64_W16.51mm_SMDSocket_LongPads +64-lead though-hole mounted DIP package, row spacing 16.51 mm (650 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 16.51mm 650mil SMDSocket LongPads +0 +64 +64 +Package_DIP +DIP-64_W22.86mm +64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils) +THT DIP DIL PDIP 2.54mm 22.86mm 900mil +0 +64 +64 +Package_DIP +DIP-64_W22.86mm_LongPads +64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), LongPads +THT DIP DIL PDIP 2.54mm 22.86mm 900mil LongPads +0 +64 +64 +Package_DIP +DIP-64_W22.86mm_SMDSocket_SmallPads +64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 22.86mm 900mil SMDSocket SmallPads +0 +64 +64 +Package_DIP +DIP-64_W22.86mm_Socket +64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), Socket +THT DIP DIL PDIP 2.54mm 22.86mm 900mil Socket +0 +64 +64 +Package_DIP +DIP-64_W22.86mm_Socket_LongPads +64-lead though-hole mounted DIP package, row spacing 22.86 mm (900 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 22.86mm 900mil Socket LongPads +0 +64 +64 +Package_DIP +DIP-64_W24.13mm_SMDSocket_LongPads +64-lead though-hole mounted DIP package, row spacing 24.13 mm (950 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 24.13mm 950mil SMDSocket LongPads +0 +64 +64 +Package_DIP +DIP-64_W25.4mm +64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils) +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil +0 +64 +64 +Package_DIP +DIP-64_W25.4mm_LongPads +64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), LongPads +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil LongPads +0 +64 +64 +Package_DIP +DIP-64_W25.4mm_SMDSocket_SmallPads +64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), SMDSocket, SmallPads +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil SMDSocket SmallPads +0 +64 +64 +Package_DIP +DIP-64_W25.4mm_Socket +64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket +0 +64 +64 +Package_DIP +DIP-64_W25.4mm_Socket_LongPads +64-lead though-hole mounted DIP package, row spacing 25.4 mm (1000 mils), Socket, LongPads +THT DIP DIL PDIP 2.54mm 25.4mm 1000mil Socket LongPads +0 +64 +64 +Package_DIP +DIP-64_W26.67mm_SMDSocket_LongPads +64-lead though-hole mounted DIP package, row spacing 26.67 mm (1050 mils), SMDSocket, LongPads +THT DIP DIL PDIP 2.54mm 26.669999999999998mm 1050mil SMDSocket LongPads +0 +64 +64 +Package_DIP +Fairchild_LSOP-8 +8-Lead, 300\" Wide, Surface Mount Package (https://www.fairchildsemi.com/package-drawings/ML/MLSOP08A.pdf) +LSOP 2.54mm 300mil +0 +8 +8 +Package_DIP +PowerIntegrations_PDIP-8B +Power Integrations variant of 8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://www.power.com/sites/default/files/product-docs/lnk520.pdf +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +7 +7 +Package_DIP +PowerIntegrations_PDIP-8C +Power Integrations variant of 8-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-iii_family_datasheet.pdf +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +7 +7 +Package_DIP +PowerIntegrations_SDIP-10C +PowerIntegrations variant of 10-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads, see https://www.power.com/sites/default/files/product-docs/tophx_family_datasheet.pdf +THT DIP DIL PDIP 2.54mm 7.62mm 300mil LongPads +0 +9 +9 +Package_DIP +PowerIntegrations_SMD-8 +PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://www.power.com/sites/default/files/product-docs/lnk520.pdf +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +8 +8 +Package_DIP +PowerIntegrations_SMD-8B +PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://www.power.com/sites/default/files/product-docs/lnk520.pdf +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +7 +7 +Package_DIP +PowerIntegrations_SMD-8C +PowerIntegrations variant of 8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), see https://ac-dc.power.com/sites/default/files/product-docs/tinyswitch-iii_family_datasheet.pdf +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +7 +7 +Package_DIP +PowerIntegrations_eDIP-12B +Power Integrations eDIP-12B, see https://www.power.com/sites/default/files/product-docs/linkswitch-pl_family_datasheet.pdf +THT DIP DIL PDIP 2.54mm 7.62mm 300mil +0 +11 +11 +Package_DIP +SMDIP-4_W7.62mm +4-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +4 +4 +Package_DIP +SMDIP-4_W9.53mm +4-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +4 +4 +Package_DIP +SMDIP-4_W9.53mm_Clearance8mm +4-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +4 +4 +Package_DIP +SMDIP-4_W11.48mm +4-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +4 +4 +Package_DIP +SMDIP-6_W7.62mm +6-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +6 +6 +Package_DIP +SMDIP-6_W9.53mm +6-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +6 +6 +Package_DIP +SMDIP-6_W9.53mm_Clearance8mm +6-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +6 +6 +Package_DIP +SMDIP-6_W11.48mm +6-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +6 +6 +Package_DIP +SMDIP-8_W7.62mm +8-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +8 +8 +Package_DIP +SMDIP-8_W9.53mm +8-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +8 +8 +Package_DIP +SMDIP-8_W9.53mm_Clearance8mm +8-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +8 +8 +Package_DIP +SMDIP-8_W11.48mm +8-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +8 +8 +Package_DIP +SMDIP-10_W7.62mm +10-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +10 +10 +Package_DIP +SMDIP-10_W9.53mm +10-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +10 +10 +Package_DIP +SMDIP-10_W9.53mm_Clearance8mm +10-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +10 +10 +Package_DIP +SMDIP-10_W11.48mm +10-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +10 +10 +Package_DIP +SMDIP-12_W7.62mm +12-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +12 +12 +Package_DIP +SMDIP-12_W9.53mm +12-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +12 +12 +Package_DIP +SMDIP-12_W9.53mm_Clearance8mm +12-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +12 +12 +Package_DIP +SMDIP-12_W11.48mm +12-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +12 +12 +Package_DIP +SMDIP-14_W7.62mm +14-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +14 +14 +Package_DIP +SMDIP-14_W9.53mm +14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +14 +14 +Package_DIP +SMDIP-14_W9.53mm_Clearance8mm +14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +14 +14 +Package_DIP +SMDIP-14_W11.48mm +14-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +14 +14 +Package_DIP +SMDIP-16_W7.62mm +16-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +16 +16 +Package_DIP +SMDIP-16_W9.53mm +16-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +16 +16 +Package_DIP +SMDIP-16_W9.53mm_Clearance8mm +16-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +16 +16 +Package_DIP +SMDIP-16_W11.48mm +16-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +16 +16 +Package_DIP +SMDIP-18_W7.62mm +18-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +18 +18 +Package_DIP +SMDIP-18_W9.53mm +18-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +18 +18 +Package_DIP +SMDIP-18_W9.53mm_Clearance8mm +18-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +18 +18 +Package_DIP +SMDIP-18_W11.48mm +18-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +18 +18 +Package_DIP +SMDIP-20_W7.62mm +20-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +20 +20 +Package_DIP +SMDIP-20_W9.53mm +20-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +20 +20 +Package_DIP +SMDIP-20_W9.53mm_Clearance8mm +20-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +20 +20 +Package_DIP +SMDIP-20_W11.48mm +20-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +20 +20 +Package_DIP +SMDIP-22_W7.62mm +22-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +22 +22 +Package_DIP +SMDIP-22_W9.53mm +22-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +22 +22 +Package_DIP +SMDIP-22_W9.53mm_Clearance8mm +22-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil Clearance8mm +0 +22 +22 +Package_DIP +SMDIP-22_W11.48mm +22-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +22 +22 +Package_DIP +SMDIP-24_W7.62mm +24-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +24 +24 +Package_DIP +SMDIP-24_W9.53mm +24-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +24 +24 +Package_DIP +SMDIP-24_W11.48mm +24-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +24 +24 +Package_DIP +SMDIP-24_W15.24mm +24-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +24 +24 +Package_DIP +SMDIP-28_W15.24mm +28-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +28 +28 +Package_DIP +SMDIP-32_W7.62mm +32-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 7.62mm 300mil +0 +32 +32 +Package_DIP +SMDIP-32_W9.53mm +32-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 9.53mm 375mil +0 +32 +32 +Package_DIP +SMDIP-32_W11.48mm +32-lead surface-mounted (SMD) DIP package, row spacing 11.48 mm (451 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 11.48mm 451mil +0 +32 +32 +Package_DIP +SMDIP-32_W15.24mm +32-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +32 +32 +Package_DIP +SMDIP-40_W15.24mm +40-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +40 +40 +Package_DIP +SMDIP-40_W25.24mm +40-lead surface-mounted (SMD) DIP package, row spacing 25.24 mm (993 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 25.24mm 993mil +0 +40 +40 +Package_DIP +SMDIP-42_W15.24mm +42-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +42 +42 +Package_DIP +SMDIP-48_W15.24mm +48-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +48 +48 +Package_DIP +SMDIP-64_W15.24mm +64-lead surface-mounted (SMD) DIP package, row spacing 15.24 mm (600 mils) +SMD DIP DIL PDIP SMDIP 2.54mm 15.24mm 600mil +0 +64 +64 +Package_DIP +Toshiba_11-7A9 +Toshiba 11-7A9 package, like 6-lead dip package with missing pin 5, row spacing 7.62 mm (300 mils), https://toshiba.semicon-storage.com/info/docget.jsp?did=1421&prodName=TLP3021(S) +Toshiba 11-7A9 DIL DIP PDIP 2.54mm 7.62mm 300mil +0 +5 +5 +Package_DIP +Vishay_HVM-DIP-3_W7.62mm +3-lead though-hole mounted high-volatge DIP package (based on standard DIP-4), row spacing 7.62 mm (300 mils), see https://www.vishay.com/docs/91361/hexdip.pdf +THT DIP DIL PDIP 2.54mm 7.62mm 300mil Vishay HVMDIP HEXDIP +0 +4 +3 +Package_DirectFET +DirectFET_L4 +DirectFET L4 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=41 +DirectFET L4 MOSFET Infineon +0 +11 +3 +Package_DirectFET +DirectFET_L6 +DirectFET L6 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=42 +DirectFET L6 MOSFET Infineon +0 +13 +3 +Package_DirectFET +DirectFET_L8 +DirectFET L8 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=43 +DirectFET L8 MOSFET Infineon +0 +15 +3 +Package_DirectFET +DirectFET_LA +DirectFET LA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=44 +DirectFET LA MOSFET Infineon +0 +15 +3 +Package_DirectFET +DirectFET_M2 +DirectFET M2 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=33 +DirectFET M2 MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_M4 +DirectFET M4 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=34 +DirectFET M4 MOSFET Infineon +0 +9 +3 +Package_DirectFET +DirectFET_MA +DirectFET MA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=35 +DirectFET MA MOSFET Infineon +0 +8 +3 +Package_DirectFET +DirectFET_MB +DirectFET MB https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=36 +DirectFET MB MOSFET Infineon +0 +8 +3 +Package_DirectFET +DirectFET_MC +DirectFET MC https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=37 +DirectFET MC MOSFET Infineon +0 +10 +3 +Package_DirectFET +DirectFET_MD +DirectFET MD https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=38 +DirectFET MD MOSFET Infineon +0 +8 +3 +Package_DirectFET +DirectFET_ME +DirectFET ME https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=39 +DirectFET ME MOSFET Infineon +0 +10 +3 +Package_DirectFET +DirectFET_MF +DirectFET MF https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=40 +DirectFET MF MOSFET Infineon +0 +8 +3 +Package_DirectFET +DirectFET_MN +DirectFET MN https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=30 +DirectFET MN MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_MP +DirectFET MP https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=28 +DirectFET MP MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_MQ +DirectFET MQ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=29 +DirectFET MQ MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_MT +DirectFET MT https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=26 +DirectFET MT MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_MU +DirectFET MU https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=32 +DirectFET MU MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_MX +DirectFET MX https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=27 +DirectFET MX MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_MZ +DirectFET MZ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=31 +DirectFET MZ MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_S1 +DirectFET S1 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=20 +DirectFET S1 MOSFET Infineon +0 +6 +3 +Package_DirectFET +DirectFET_S2 +DirectFET S2 https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=21 +DirectFET S2 MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_S3C +DirectFET S3C https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=25 +DirectFET S3C MOSFET Infineon +0 +8 +3 +Package_DirectFET +DirectFET_SA +DirectFET SA https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=22 +DirectFET SA MOSFET Infineon +0 +8 +3 +Package_DirectFET +DirectFET_SB +DirectFET SB https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=23 +DirectFET SB MOSFET Infineon +0 +6 +3 +Package_DirectFET +DirectFET_SC +DirectFET SC https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=24 +DirectFET SC MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_SH +DirectFET SH https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=19 +DirectFET SH MOSFET Infineon +0 +6 +3 +Package_DirectFET +DirectFET_SJ +DirectFET SJ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=18 +DirectFET SJ MOSFET Infineon +0 +7 +3 +Package_DirectFET +DirectFET_SQ +DirectFET SQ https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=17 +DirectFET SQ MOSFET Infineon +0 +6 +3 +Package_DirectFET +DirectFET_ST +DirectFET ST https://www.infineon.com/dgdl/Infineon-AN-1035-ApplicationNotes-v29_01-EN.pdf?fileId=5546d462533600a40153559159020f76#page=16 +DirectFET ST MOSFET Infineon +0 +7 +3 +Package_LCC +PLCC-20 +PLCC, 20 pins, surface mount +plcc smt +0 +20 +20 +Package_LCC +PLCC-20_SMD-Socket +PLCC, 20 pins, surface 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kicad-footprint-generator ipc_plcc_jLead_generator.py +PLCC LCC +0 +84 +84 +Package_LCC +PLCC-84_SMD-Socket +PLCC, 84 pins, surface mount +plcc smt +0 +84 +84 +Package_LCC +PLCC-84_THT-Socket +PLCC, 84 pins, through hole +plcc leaded +0 +84 +84 +Package_LGA +AMS_LGA-10-1EP_2.7x4mm_P0.6mm +LGA-10, http://ams.com/eng/content/download/951091/2269479/471718 +lga land grid array +0 +13 +11 +Package_LGA +AMS_LGA-20_4.7x4.5mm_P0.65mm +http://ams.com/eng/content/download/1008631/2361759/498838 +AMS LGA +0 +20 +20 +Package_LGA +Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering +LGA-8 +lga land grid array +0 +8 +8 +Package_LGA +Bosch_LGA-8_2x2.5mm_P0.65mm_ClockwisePinNumbering +LGA-8, https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMP280-DS001-18.pdf +lga land grid array +0 +8 +8 +Package_LGA +Bosch_LGA-8_3x3mm_P0.8mm_ClockwisePinNumbering +Bosch LGA, 8 Pin (https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BME680-DS001-00.pdf#page=44), generated with kicad-footprint-generator ipc_noLead_generator.py +Bosch LGA NoLead +0 +8 +8 +Package_LGA +Bosch_LGA-14_3x2.5mm_P0.5mm +LGA-14 Bosch https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMI160-DS000-07.pdf +lga land grid array +0 +14 +14 +Package_LGA +LGA-8_3x5mm_P1.25mm +LGA-8 +lga land grid array +0 +8 +8 +Package_LGA +LGA-12_2x2mm_P0.5mm +LGA12 +lga land grid array +0 +12 +12 +Package_LGA +LGA-14_2x2mm_P0.35mm_LayoutBorder3x4y +LGA, 14 Pin (http://www.st.com/resource/en/datasheet/lis2dh.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LGA NoLead +0 +14 +14 +Package_LGA +LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y +LGA, 14 Pin (http://www.st.com/resource/en/datasheet/lsm6ds3.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +LGA NoLead +0 +14 +14 +Package_LGA +LGA-14_3x5mm_P0.8mm_LayoutBorder1x6y +LGA, 14 Pin (http://www.st.com/resource/en/datasheet/lsm303dlhc.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py 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https://www.analog.com/media/en/technical-documentation/data-sheets/4637fc.pdf +133 pin lga +0 +133 +133 +Package_LGA +NXP_LGA-8_3x5mm_P1.25mm_H1.1mm +NXP LGA, 8 Pin (https://www.nxp.com/docs/en/data-sheet/MPL3115A2.pdf#page=42), generated with kicad-footprint-generator ipc_noLead_generator.py +NXP LGA NoLead +0 +8 +8 +Package_LGA +NXP_LGA-8_3x5mm_P1.25mm_H1.2mm +NXP LGA, 8 Pin (https://www.nxp.com/docs/en/data-sheet/MPL115A1.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +NXP LGA NoLead +0 +8 +8 +Package_LGA +ST_HLGA-10_2.5x2.5mm_P0.6mm_LayoutBorder3x2y +ST HLGA, 10 Pin (https://www.st.com/resource/en/datasheet/lps25hb.pdf#page=46), generated with kicad-footprint-generator ipc_noLead_generator.py +ST HLGA NoLead +0 +10 +10 +Package_LGA +Texas_SIL0008D_MicroSiP-8-1EP_2.8x3mm_P0.65mm_EP1.1x1.9mm +Texas SIL0008D MicroSiP, 8 Pin (http://www.ti.com/lit/ds/symlink/tps82130.pdf#page=19), generated with kicad-footprint-generator ipc_noLead_generator.py +Texas MicroSiP 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generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +171 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP5x5mm +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00476-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +161 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP5x5mm_ThermalVias +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00476-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +187 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP6.61x5.615mm +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00485-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +165 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP6.61x5.615mm_ThermalVias +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00485-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +196 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP7.2x6.35mm +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00487-01.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +175 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP7.2x6.35mm_ThermalVias +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00487-01.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +218 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP8.93x8.7mm +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00479-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +194 +145 +Package_QFP +EQFP-144-1EP_20x20mm_P0.5mm_EP8.93x8.7mm_ThermalVias +EQFP, 144 Pin (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00479-02.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +EQFP QFP +0 +259 +145 +Package_QFP +HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm +64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [HTQFP] thermal pad +HTQFP-64 Pitch 0.5 +0 +69 +65 +Package_QFP +HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm_Mask4.4x4.4mm_ThermalVias +64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [HTQFP] thermal pad +HTQFP-64 Pitch 0.5 +0 +135 +65 +Package_QFP +LQFP-32_5x5mm_P0.5mm +LQFP, 32 Pin (https://www.nxp.com/docs/en/package-information/SOT401-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +32 +32 +Package_QFP +LQFP-32_7x7mm_P0.8mm +LQFP, 32 Pin (https://www.nxp.com/docs/en/package-information/SOT358-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +32 +32 +Package_QFP +LQFP-36_7x7mm_P0.65mm +LQFP, 36 Pin (https://www.onsemi.com/pub/Collateral/561AV.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +36 +36 +Package_QFP +LQFP-44_10x10mm_P0.8mm +LQFP, 44 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ASS23225W.pdf?&fsrch=1), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +44 +44 +Package_QFP +LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm +LQFP, 48 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/LTC7810.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +58 +49 +Package_QFP +LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm_ThermalVias +LQFP, 48 Pin (http://www.analog.com/media/en/technical-documentation/data-sheets/LTC7810.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +75 +49 +Package_QFP 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ipc_gullwing_generator.py +LQFP QFP +0 +52 +52 +Package_QFP +LQFP-64-1EP_10x10mm_P0.5mm_EP5x5mm +LQFP, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/adv7611.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +90 +65 +Package_QFP +LQFP-64-1EP_10x10mm_P0.5mm_EP5x5mm_ThermalVias +LQFP, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/adv7611.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +107 +65 +Package_QFP +LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm +LQFP, 64 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ARH98426A.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +90 +65 +Package_QFP +LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm_ThermalVias +LQFP, 64 Pin (https://www.nxp.com/files-static/shared/doc/package_info/98ARH98426A.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +127 +65 +Package_QFP +LQFP-64_7x7mm_P0.4mm +LQFP, 64 Pin (https://www.nxp.com/docs/en/package-information/SOT414-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +64 +64 +Package_QFP +LQFP-64_10x10mm_P0.5mm +LQFP, 64 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +64 +64 +Package_QFP +LQFP-64_14x14mm_P0.8mm +LQFP, 64 Pin (https://www.nxp.com/docs/en/package-information/SOT791-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +64 +64 +Package_QFP +LQFP-80_10x10mm_P0.4mm +LQFP, 80 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/q80.10x10.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +80 +80 +Package_QFP +LQFP-80_12x12mm_P0.5mm +LQFP, 80 Pin (https://www.nxp.com/docs/en/package-information/SOT315-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +80 +80 +Package_QFP +LQFP-80_14x14mm_P0.65mm +LQFP, 80 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/AD9852.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +80 +80 +Package_QFP +LQFP-100_14x14mm_P0.5mm +LQFP, 100 Pin (https://www.nxp.com/docs/en/package-information/SOT407-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +100 +100 +Package_QFP +LQFP-128_14x14mm_P0.4mm +LQFP, 128 Pin (https://www.renesas.com/eu/en/package-image/pdf/outdrawing/q128.14x14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +128 +128 +Package_QFP +LQFP-128_14x20mm_P0.5mm +LQFP, 128 Pin (https://www.nxp.com/docs/en/package-information/SOT425-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +128 +128 +Package_QFP +LQFP-144_20x20mm_P0.5mm +LQFP, 144 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=425), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +144 +144 +Package_QFP +LQFP-160_24x24mm_P0.5mm +LQFP, 160 Pin (https://www.nxp.com/docs/en/package-information/SOT435-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +160 +160 +Package_QFP +LQFP-176_20x20mm_P0.4mm +LQFP, 176 Pin (https://www.onsemi.com/pub/Collateral/566DB.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +176 +176 +Package_QFP +LQFP-176_24x24mm_P0.5mm +LQFP, 176 Pin (https://www.st.com/resource/en/datasheet/stm32f207vg.pdf#page=163), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +176 +176 +Package_QFP +LQFP-208_28x28mm_P0.5mm +LQFP, 208 Pin (https://www.nxp.com/docs/en/package-information/SOT459-1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +208 +208 +Package_QFP +LQFP-216_24x24mm_P0.4mm +LQFP, 216 Pin (https://www.onsemi.com/pub/Collateral/561BE.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py +LQFP QFP +0 +216 +216 +Package_QFP +MQFP-44_10x10mm_P0.8mm +MQFP, 44 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ad7722.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +MQFP QFP +0 +44 +44 +Package_QFP +PQFP-44_10x10mm_P0.8mm +44-Lead Plastic Quad Flatpack - 10x10x2.5mm Body (http://www.onsemi.com/pub/Collateral/122BK.PDF) +PQFP 0.8 +0 +44 +44 +Package_QFP +PQFP-80_14x20mm_P0.8mm +PQFP80 14x20 / QIP80E CASE 122BS (see ON Semiconductor 122BS.PDF) +QFP 0.8 +0 +80 +80 +Package_QFP +PQFP-100_14x20mm_P0.65mm +PQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +PQFP QFP +0 +100 +100 +Package_QFP +PQFP-112_20x20mm_P0.65mm +PQFP, 112 pins, 20mm sq body, 0.65mm pitch (http://cache.freescale.com/files/shared/doc/package_info/98ASS23330W.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf) +PQFP 112 +0 +112 +112 +Package_QFP +PQFP-132_24x24mm_P0.635mm +PQFP, 132 pins, 24mm sq body, 0.635mm pitch (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf) +PQFP 132 +0 +132 +132 +Package_QFP +PQFP-132_24x24mm_P0.635mm_i386 +PQFP, 132 pins, 24mm sq body, 0.635mm pitch, Intel 386EX (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf) +PQFP 132 Intel 386EX +0 +132 +132 +Package_QFP +PQFP-144_28x28mm_P0.65mm +PQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +PQFP QFP +0 +144 +144 +Package_QFP +PQFP-160_28x28mm_P0.65mm +PQFP, 160 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +PQFP QFP +0 +160 +160 +Package_QFP +PQFP-208_28x28mm_P0.5mm +PQFP, 208 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +PQFP QFP +0 +208 +208 +Package_QFP +PQFP-240_32.1x32.1mm_P0.5mm +PQFP, 240 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +PQFP QFP +0 +240 +240 +Package_QFP +PQFP-256_28x28mm_P0.4mm +PQFP256 28x28 / QFP256J CASE 122BX (see ON Semiconductor 122BX.PDF) +QFP 0.4 +0 +256 +256 +Package_QFP +TQFP-32_7x7mm_P0.8mm +32-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.8 +0 +32 +32 +Package_QFP +TQFP-44-1EP_10x10mm_P0.8mm_EP4.5x4.5mm +44-Lead Plastic Thin Quad Flatpack (MW) - 10x10x1.0 mm Body [TQFP] With 4.5x4.5 mm Exposed Pad (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.8 +0 +54 +45 +Package_QFP +TQFP-44_10x10mm_P0.8mm +44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.8 +0 +44 +44 +Package_QFP +TQFP-48-1EP_7x7mm_P0.5mm_EP3.5x3.5mm +48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.5 +0 +53 +49 +Package_QFP +TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm +TQFP, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 45)), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +65 +49 +Package_QFP +TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm_ThermalVias +TQFP, 48 Pin (https://www.trinamic.com/fileadmin/assets/Products/ICs_Documents/TMC2100_datasheet_Rev1.08.pdf (page 45)), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +91 +49 +Package_QFP +TQFP-48_7x7mm_P0.5mm +48 LEAD TQFP 7x7mm (see MICREL TQFP7x7-48LD-PL-1.pdf) +QFP 0.5 +0 +48 +48 +Package_QFP +TQFP-52-1EP_10x10mm_P0.65mm_EP6.5x6.5mm +TQFP, 52 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_52_1.pdf), generated with kicad-footprint-generator ipc_qfp_generator.py +TQFP QFP +0 +78 +53 +Package_QFP +TQFP-52-1EP_10x10mm_P0.65mm_EP6.5x6.5mm_ThermalVias +TQFP, 52 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_52_1.pdf), generated with kicad-footprint-generator ipc_qfp_generator.py +TQFP QFP +0 +79 +53 +Package_QFP +TQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm +64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP] thermal pad +QFP 0.5 +0 +90 +65 +Package_QFP +TQFP-64_7x7mm_P0.4mm +TQFP64 7x7, 0.4P CASE 932BH (see ON Semiconductor 932BH.PDF) +QFP 0.4 +0 +64 +64 +Package_QFP +TQFP-64_10x10mm_P0.5mm +TQFP, 64 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +64 +64 +Package_QFP +TQFP-64_14x14mm_P0.8mm +64-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.8 +0 +64 +64 +Package_QFP +TQFP-80-1EP_14x14mm_P0.65mm_EP9.5x9.5mm +80-Lead Plastic Thin Quad Flatpack (PF) - 14x14mm body, 9.5mm sq thermal pad (http://www.analog.com/media/en/technical-documentation/data-sheets/AD9852.pdf) +QFP 0.65 +0 +85 +81 +Package_QFP +TQFP-80_12x12mm_P0.5mm +80-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.5 +0 +80 +80 +Package_QFP +TQFP-80_14x14mm_P0.65mm +80-Lead Plastic Thin Quad Flatpack (PF) - 14x14x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.65 +0 +80 +80 +Package_QFP +TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm +TQFP, 100 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_100_4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +117 +101 +Package_QFP +TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm_ThermalVias +TQFP, 100 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/tqfp_edsv/sv_100_4.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +143 +101 +Package_QFP +TQFP-100_12x12mm_P0.4mm +100-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.4 +0 +100 +100 +Package_QFP +TQFP-100_14x14mm_P0.5mm +TQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +100 +100 +Package_QFP +TQFP-120_14x14mm_P0.4mm +TQFP120 14x14 / TQFP120 CASE 932AZ (see ON Semiconductor 932AZ.PDF) +QFP 0.4 +0 +120 +120 +Package_QFP +TQFP-128_14x14mm_P0.4mm +TQFP128 14x14 / TQFP128 CASE 932BB (see ON Semiconductor 932BB.PDF) +QFP 0.4 +0 +128 +128 +Package_QFP +TQFP-144_16x16mm_P0.4mm +144-Lead Plastic Thin Quad Flatpack (PH) - 16x16x1 mm Body, 2.00 mm Footprint [TQFP] (see Microchip Packaging Specification 00000049BS.pdf) +QFP 0.4 +0 +144 +144 +Package_QFP +TQFP-144_20x20mm_P0.5mm +TQFP, 144 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +144 +144 +Package_QFP +TQFP-176_24x24mm_P0.5mm +TQFP, 176 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +TQFP QFP +0 +176 +176 +Package_QFP +VQFP-80_14x14mm_P0.65mm +VQFP, 80 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +VQFP QFP +0 +80 +80 +Package_QFP +VQFP-100_14x14mm_P0.5mm +VQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +VQFP QFP +0 +100 +100 +Package_QFP +VQFP-128_14x14mm_P0.4mm +VQFP, 128 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +VQFP QFP +0 +128 +128 +Package_QFP +VQFP-176_20x20mm_P0.4mm +VQFP, 176 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py +VQFP QFP +0 +176 +176 +Package_SIP +PowerIntegrations_eSIP-7C +eSIP-7C Vertical Flat Package with Heatsink Tab, https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf +Power Integrations E Package +0 +6 +6 +Package_SIP +PowerIntegrations_eSIP-7F +eSIP-7F Flat Package with Heatsink Tab https://ac-dc.power.com/sites/default/files/product-docs/linkswitch-ph_family_datasheet.pdf +Power Integrations L Package +0 +6 +6 +Package_SIP +SIP-8_19x3mm_P2.54mm +SIP 8-pin (http://www.njr.com/semicon/PDF/package/SIP8_E.pdf) +SIP8 +0 +8 +8 +Package_SIP +SIP-9_21.54x3mm_P2.54mm +SIP 9-pin () +SIP8 +0 +9 +9 +Package_SIP +SIP3_11.6x8.5mm +RECOM,R78EXX,https://www.recom-power.com/pdf/Innoline/R-78Exx-0.5.pdf +SIP3 Regulator Module +0 +3 +3 +Package_SIP +SIP4_Sharp-SSR_P7.62mm_Angled +SIP4 Footprint for SSR made by Sharp +Solid State relais SSR Sharp +0 +4 +4 +Package_SIP +SIP4_Sharp-SSR_P7.62mm_Angled_NoHole +SIP4 Footprint for SSR made by Sharp +Solid State relais SSR Sharp +0 +4 +4 +Package_SIP +SIP4_Sharp-SSR_P7.62mm_Straight +SIP4 Footprint for SSR made by Sharp +Solid State relais SSR Sharp +0 +4 +4 +Package_SIP +SIP9_Housing +SIP9 +SIP9 +0 +9 +9 +Package_SIP +SIP9_Housing_BigPads +SIP9, large pads +SIP9 +0 +9 +9 +Package_SIP +SLA704XM +SIP SLA704XM (http://www.sumzi.com/upload/files/2007/07/2007073114282034189.PDF) +SIP +0 +18 +18 +Package_SIP +STK672-040-E +SIP-22 (http://www.onsemi.com/pub_link/Collateral/EN5227-D.PDF) +SIP-22 +0 +22 +22 +Package_SIP +STK672-080-E +SIP-15 (http://www.onsemi.com/pub_link/Collateral/EN6507-D.PDF) +SIP-15 +0 +15 +15 +Package_SIP +Sanyo_STK4xx-15_59.2x8.0mm_P2.54mm +Sanyo SIP-15, 59.2mm x 8.0mm bosy size, STK-433E STK-435E STK-436E (http://datasheet.octopart.com/STK430-Sanyo-datasheet-107060.pdf) +Sanyo SIP-15 +0 +15 +15 +Package_SIP +Sanyo_STK4xx-15_78.0x8.0mm_P2.54mm +Sanyo SIP-15, 78.0mm x 8.0mm bosy size, STK-437E STK-439E STK-441E STK-443E (http://datasheet.octopart.com/STK430-Sanyo-datasheet-107060.pdf) +Sanyo SIP-15 +0 +15 +15 +Package_SO +Diodes_PSOP-8 +8-Lead Plastic PSOP, Exposed Die Pad (see https://www.diodes.com/assets/Datasheets/AP2204.pdf) +SSOP 0.50 exposed pad +0 +12 +9 +Package_SO +Diodes_SO-8EP +8-Lead Plastic SO, Exposed Die Pad (see https://www.diodes.com/assets/Package-Files/SO-8EP.pdf) +SO exposed pad +0 +9 +9 +Package_SO +ETSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3x4.2mm +20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body with Exposed Pad [eTSSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +27 +21 +Package_SO +HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm +HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HSOP SO +0 +13 +9 +Package_SO +HSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.1mm_ThermalVias +HSOP, 8 Pin (https://www.st.com/resource/en/datasheet/l5973d.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HSOP SO +0 +20 +9 +Package_SO +HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugDown +HSOP 11.0x15.9mm Pitch 1.27mm Slug Down (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf) +HSOP 11.0 x 15.9mm Pitch 1.27mm +0 +23 +21 +Package_SO +HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugDown_ThermalVias +HSOP 11.0x15.9mm Pitch 1.27mm Slug Down Thermal Vias (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf) +HSOP 11.0 x 15.9mm Pitch 1.27mm +0 +45 +21 +Package_SO +HSOP-20-1EP_11.0x15.9mm_P1.27mm_SlugUp +HSOP 11.0x15.9mm Pitch 1.27mm Slug Up (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf) +HSOP 11.0 x 15.9mm Pitch 1.27mm +0 +20 +20 +Package_SO +HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugDown +HSOP 11.0x15.9mm Pitch 0.65mm Slug Down (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf) +HSOP 11.0 x 15.9mm Pitch 0.65mm +0 +39 +37 +Package_SO +HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugDown_ThermalVias +HSOP 11.0x15.9mm Pitch 0.65mm Slug Down Thermal Vias (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf) +HSOP 11.0 x 15.9mm Pitch 0.65mm +0 +61 +37 +Package_SO +HSOP-36-1EP_11.0x15.9mm_P0.65mm_SlugUp +HSOP 11.0x15.9mm Pitch 0.65mm Slug Up (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf, http://www.st.com/resource/en/application_note/cd00003801.pdf) +HSOP 11.0 x 15.9mm Pitch 0.65mm +0 +36 +36 +Package_SO +HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm +HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSOP SO +0 +13 +9 +Package_SO +HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.4x3.2mm_ThermalVias +HTSOP, 8 Pin (https://media.digikey.com/pdf/Data%20Sheets/Rohm%20PDFs/BD9G341EFJ.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSOP SO +0 +20 +9 +Package_SO +HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm +16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad; (http://www.ti.com/lit/ds/symlink/drv8833.pdf) +SSOP 0.65 +0 +29 +17 +Package_SO +HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask2.46x2.31mm_ThermalVias +16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8833.pdf) +SSOP 0.65 +0 +27 +17 +Package_SO +HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3.4x5mm_Mask3x3mm_ThermalVias +16-Lead Plastic HTSSOP (4.4x5x1.2mm); Thermal pad with vias; (http://www.ti.com/lit/ds/symlink/drv8800.pdf) +SSOP 0.65 +0 +46 +17 +Package_SO +HTSSOP-16-1EP_4.4x5mm_P0.65mm_EP3x3mm +HTSSOP, 16 Pin (https://www.st.com/resource/en/datasheet/stp08cp05.pdf#page=20), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +21 +17 +Package_SO +HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm +20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [HTSSOP], with thermal pad with vias +HTSSOP 0.65 +0 +29 +21 +Package_SO +HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.4x3.7mm +HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/bq24006.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +24 +21 +Package_SO +HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm +HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +26 +21 +Package_SO +HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias +HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +42 +21 +Package_SO +HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_Mask2.75x3.43mm_ThermalVias_HandSolder +HTSSOP, 20 Pin (http://www.ti.com/lit/ds/symlink/tlc5971.pdf#page=37&zoom=160,-90,3), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +42 +21 +Package_SO +HTSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP3.4x6.5mm_ThermalVias +20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [HTSSOP], with thermal pad with vias +HTSSOP 0.65 +0 +45 +21 +Package_SO +HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.2x5mm +HTSSOP, 24 Pin (https://www.st.com/resource/en/datasheet/stp16cp05.pdf#page=25), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +31 +25 +Package_SO +HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm +HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +28 +25 +Package_SO +HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm_ThermalVias +HTSSOP, 24 Pin (http://www.ti.com/lit/ds/symlink/tps703.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +47 +25 +Package_SO +HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm +HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +30 +29 +Package_SO +HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm_ThermalVias +HTSSOP, 28 Pin (https://pdfserv.maximintegrated.com/package_dwgs/21-0108.PDF), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +41 +29 +Package_SO +HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm +HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad +TSSOP HTSSOP 0.65 thermal pad +0 +39 +29 +Package_SO +HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm +HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad +TSSOP HTSSOP 0.65 thermal pad +0 +40 +29 +Package_SO +HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_Mask2.4x6.17mm_ThermalVias +HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad +TSSOP HTSSOP 0.65 thermal pad +0 +55 +29 +Package_SO +HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm_ThermalVias +HTSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; thermal pad +TSSOP HTSSOP 0.65 thermal pad +0 +58 +29 +Package_SO +HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm +HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf) +SSOP 0.65 PowerPAD +0 +43 +33 +Package_SO +HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm_ThermalVias +HTSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf) +SSOP 0.65 PowerPAD +0 +83 +33 +Package_SO +HTSSOP-38-1EP_6.1x12.5mm_P0.65mm_EP5.2x12.5mm_Mask3.39x6.35mm +HTSSOP, 38 Pin (http://www.ti.com/lit/ds/symlink/tlc5951.pdf#page=47&zoom=140,-67,15), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +46 +39 +Package_SO +HTSSOP-38-1EP_6.1x12.5mm_P0.65mm_EP5.2x12.5mm_Mask3.39x6.35mm_ThermalVias +HTSSOP, 38 Pin (http://www.ti.com/lit/ds/symlink/tlc5951.pdf#page=47&zoom=140,-67,15), generated with kicad-footprint-generator ipc_gullwing_generator.py +HTSSOP SO +0 +87 +39 +Package_SO +HTSSOP-56-1EP_6.1x14mm_P0.5mm_EP3.61x6.35mm +HTSSOP56: plastic thin shrink small outline package http://www.ti.com/lit/ds/symlink/drv8301.pdf +HTSSOP 0.5 +0 +72 +57 +Package_SO +Infineon_PG-DSO-8-27_3.9x4.9mm_EP2.65x3mm +Infineon PG-DSO, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator ipc_gullwing_generator.py +Infineon PG-DSO SO +0 +13 +9 +Package_SO +Infineon_PG-DSO-8-27_3.9x4.9mm_EP2.65x3mm_ThermalVias +Infineon PG-DSO, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator ipc_gullwing_generator.py +Infineon PG-DSO SO +0 +23 +9 +Package_SO +Infineon_PG-DSO-8-43 +Infineon_PG-DSO-8-43 +DSO DSO-8 SOIC SOIC-8 +0 +12 +9 +Package_SO +Infineon_PG-DSO-12-9 +Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/) +PG-DSO +0 +23 +13 +Package_SO +Infineon_PG-DSO-12-9_ThermalVias +Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/) +PG-DSO +0 +42 +13 +Package_SO +Infineon_PG-DSO-12-11 +Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/) +PG-DSO +0 +23 +13 +Package_SO +Infineon_PG-DSO-12-11_ThermalVias +Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/) +PG-DSO +0 +42 +13 +Package_SO +Infineon_PG-DSO-20-30 +Infineon SO package 20pin, exposed pad 4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/) +DSO-20 +0 +31 +21 +Package_SO +Infineon_PG-DSO-20-30_ThermalVias +Infineon SO package 20pin, exposed pad 4.5x7mm (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-71/) +DSO-20 +0 +45 +21 +Package_SO +Infineon_PG-DSO-20-32 +Infineon SO package 20pin without exposed pad (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-20-32/) +DSO-20 +0 +20 +20 +Package_SO +Infineon_PG-TSDSO-14-22 +Infineon_PG-TSDSO-14-22 +Infineon TSDSO 14-22 +0 +17 +15 +Package_SO +Linear_MSOP-12-16-1EP_3x4mm_P0.5mm +12-Lead Plastic Micro Small Outline Package (MS) [MSOP], variant of MSOP-16 (see http://cds.linear.com/docs/en/datasheet/3630fd.pdf) +SSOP 0.5 +0 +15 +13 +Package_SO +Linear_MSOP-12-16_3x4mm_P0.5mm +12-Lead Plastic Micro Small Outline Package (MS) [MSOP], variant of MSOP-16 (see https://www.analog.com/media/en/technical-documentation/data-sheets/3748fb.pdf) +SSOP 0.5 +0 +12 +12 +Package_SO +MFSOP6-4_4.4x3.6mm_P1.27mm +https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.4pin%20MFSOP6.html +MFSOP 4 pin SMD +0 +4 +4 +Package_SO +MFSOP6-5_4.4x3.6mm_P1.27mm +https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.5pin%20MFSOP6.html +MFSOP 4 pin SMD +0 +5 +5 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm +MS8E Package; 8-Lead Plastic MSOP, Exposed Die Pad (see Linear Technology 05081662_K_MS8E.pdf) +SSOP 0.65 +0 +13 +9 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP1.73x1.85mm +MSOP, 8 Pin (http://www.ti.com/lit/ds/symlink/lm25085.pdf#page=32), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +13 +9 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP1.73x1.85mm_ThermalVias +MSOP, 8 Pin (http://www.ti.com/lit/ds/symlink/lm25085.pdf#page=32), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +18 +9 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm +MSOP, 8 Pin (http://www.st.com/resource/en/datasheet/pm8834.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +13 +9 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm_ThermalVias +MSOP, 8 Pin (http://www.st.com/resource/en/datasheet/pm8834.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +18 +9 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP2.5x3mm_Mask1.73x2.36mm +MSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf#page=15), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +14 +9 +Package_SO +MSOP-8-1EP_3x3mm_P0.65mm_EP2.5x3mm_Mask1.73x2.36mm_ThermalVias +MSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5355_6.pdf#page=15), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +19 +9 +Package_SO +MSOP-8_3x3mm_P0.65mm +MSOP, 8 Pin (https://www.jedec.org/system/files/docs/mo-187F.pdf variant AA), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +8 +8 +Package_SO +MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm +MSOP, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3805fg.pdf#page=18), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +15 +11 +Package_SO +MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm_ThermalVias +MSOP, 10 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3805fg.pdf#page=18), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +20 +11 +Package_SO +MSOP-10-1EP_3x3mm_P0.5mm_EP1.73x1.98mm +MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +15 +11 +Package_SO +MSOP-10-1EP_3x3mm_P0.5mm_EP1.73x1.98mm_ThermalVias +MSOP, 10 Pin (www.allegromicro.com/~/media/Files/Datasheets/A4952-3-Datasheet.ashx?la=en#page=10), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +20 +11 +Package_SO +MSOP-10_3x3mm_P0.5mm +10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.5 +0 +10 +10 +Package_SO +MSOP-12-1EP_3x4mm_P0.65mm_EP1.65x2.85mm +MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3652fe.pdf#page=24), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +17 +13 +Package_SO +MSOP-12-1EP_3x4mm_P0.65mm_EP1.65x2.85mm_ThermalVias +MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/3652fe.pdf#page=24), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +24 +13 +Package_SO +MSOP-12-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm +10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.5 +0 +19 +13 +Package_SO +MSOP-12-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm_ThermalVias +10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.5 +0 +25 +13 +Package_SO +MSOP-12-16_3x4mm_P0.5mm +10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.5 +0 +12 +12 +Package_SO +MSOP-12_3x4mm_P0.65mm +MSOP, 12 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/6957fb.pdf#page=36), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +12 +12 +Package_SO +MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm +MSOP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081667_F_MSE16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +21 +17 +Package_SO +MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm_ThermalVias +MSOP, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081667_F_MSE16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +28 +17 +Package_SO +MSOP-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm +MSOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +21 +17 +Package_SO +MSOP-16-1EP_3x4mm_P0.5mm_EP1.65x2.85mm_ThermalVias +MSOP, 16 Pin (http://cds.linear.com/docs/en/datasheet/37551fd.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +28 +17 +Package_SO +MSOP-16_3x4.039mm_P0.5mm +MSOP, 16 Pin (http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-msop/05081669_A_MS16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +16 +16 +Package_SO +MSOP-16_3x4mm_P0.5mm +MSOP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/436412f.pdf#page=22), generated with kicad-footprint-generator ipc_gullwing_generator.py +MSOP SO +0 +16 +16 +Package_SO +OnSemi_Micro8 +ON Semiconductor Micro8 (Case846A-02): https://www.onsemi.com/pub/Collateral/846A-02.PDF +micro8 +0 +8 +8 +Package_SO +PSOP-44_16.9x27.17mm_P1.27mm +PSOP44: plastic thin shrink small outline package; 44 leads; body width 16.90 mm +PSOP 1.27 +0 +44 +44 +Package_SO +PowerIntegrations_SO-8 +Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://ac-dc.power.com/sites/default/files/product-docs/senzero_family_datasheet.pdf +SOIC 1.27 +0 +8 +8 +Package_SO +PowerIntegrations_SO-8B +Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf +SOIC 1.27 +0 +7 +7 +Package_SO +PowerIntegrations_SO-8C +Power-Integrations variant of 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], see https://www.mouser.com/ds/2/328/linkswitch-pl_family_datasheet-12517.pdf +SOIC 1.27 +0 +7 +7 +Package_SO +PowerIntegrations_eSOP-12B +eSOP-12B SMT Flat Package with Heatsink Tab, see https://ac-dc.power.com/sites/default/files/product-docs/topswitch-jx_family_datasheet.pdf +Power Integrations K Package +0 +12 +12 +Package_SO +PowerPAK_SO-8_Dual +PowerPAK SO-8 Dual (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72600/72600.pdf) +PowerPAK SO-8 Dual +0 +10 +6 +Package_SO +PowerPAK_SO-8_Single +PowerPAK SO-8 Single (https://www.vishay.com/docs/71655/powerpak.pdf, https://www.vishay.com/docs/72599/72599.pdf) +PowerPAK SO-8 Single +0 +9 +5 +Package_SO +QSOP-16_3.9x4.9mm_P0.635mm +16-Lead Plastic Shrink Small Outline Narrow Body (QR)-.150" Body [QSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.635 +0 +16 +16 +Package_SO +QSOP-20_3.9x8.7mm_P0.635mm +20-Lead Plastic Shrink Small Outline Narrow Body (http://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7640_7641_7642_7643.pdf) +QSOP 0.635 +0 +20 +20 +Package_SO +QSOP-24_3.9x8.7mm_P0.635mm +24-Lead Plastic Shrink Small Outline Narrow Body (QR)-.150" Body [QSOP] (see Microchip Packaging Specification 00000049CH.pdf) +QSOP 0.635 +0 +24 +24 +Package_SO +SC-74-6_1.5x2.9mm_P0.95mm +SC-74, 6 Pin (https://www.nxp.com/docs/en/package-information/SOT457.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SC-74 SO +0 +6 +6 +Package_SO +SO-4_4.4x2.3mm_P1.27mm +4-Lead Plastic Small Outline (SO), see http://datasheet.octopart.com/OPIA403BTRE-Optek-datasheet-5328560.pdf +SO SOIC 1.27 +0 +4 +4 +Package_SO +SO-4_4.4x3.6mm_P2.54mm +4-Lead Plastic Small Outline (SO), see https://www.elpro.org/de/index.php?controller=attachment&id_attachment=339 +SO SOIC 2.54 +0 +4 +4 +Package_SO +SO-4_4.4x3.9mm_P2.54mm +SO, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=10047&prodName=TLP3123), generated with kicad-footprint-generator ipc_gullwing_generator.py +SO SO +0 +4 +4 +Package_SO +SO-4_4.4x4.3mm_P2.54mm +4-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/docs/AV02-0173EN +SO SOIC 2.54 +0 +4 +4 +Package_SO +SO-4_7.6x3.6mm_P2.54mm +4-Lead Plastic Small Outline (SO) (http://www.everlight.com/file/ProductFile/201407061745083848.pdf) +SO SOIC 2.54 +0 +4 +4 +Package_SO +SO-5_4.4x3.6mm_P1.27mm +5-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SO SOIC 1.27 +0 +5 +5 +Package_SO +SO-6L_10x3.84mm_P1.27mm +6-pin plasic small outline 7,5mm long https://toshiba.semicon-storage.com/info/docget.jsp?did=53548&prodName=TLP2770 +SO-6L +0 +6 +6 +Package_SO +SO-6_4.4x3.6mm_P1.27mm +6-Lead Plastic Small Outline (SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SO SOIC 1.27 +0 +6 +6 +Package_SO +SO-8_3.9x4.9mm_P1.27mm +SO, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SO SO +0 +8 +8 +Package_SO +SO-8_5.3x6.2mm_P1.27mm +8-Lead Plastic Small Outline, 5.3x6.2mm Body (http://www.ti.com.cn/cn/lit/ds/symlink/tl7705a.pdf) +SOIC 1.27 +0 +8 +8 +Package_SO +SO-20_12.8x7.5mm_P1.27mm +SO-20, 12.8x7.5mm, https://www.nxp.com/docs/en/data-sheet/SA605.pdf +S0-20 +0 +20 +20 +Package_SO +SOIC-4_4.55x2.6mm_P1.27mm +SOIC, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12884&prodName=TLP291), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +4 +4 +Package_SO +SOIC-4_4.55x3.7mm_P2.54mm +SOIC, 6 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=11791&prodName=TLP185), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +4 +4 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm +SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +13 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias +SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +20 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm +SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +13 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm_ThermalVias +SOIC, 8 Pin (http://www.allegromicro.com/~/media/Files/Datasheets/A4950-Datasheet.ashx#page=8), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +20 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm +SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +13 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.81mm_ThermalVias +SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +20 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm +SOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lm5017.pdf#page=31), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +14 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm_ThermalVias +SOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lm5017.pdf#page=31), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +23 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm +SOIC, 8 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/hip2100.pdf#page=13), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +13 +9 +Package_SO +SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm_ThermalVias +SOIC, 8 Pin (https://www.renesas.com/eu/en/www/doc/datasheet/hip2100.pdf#page=13), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +20 +9 +Package_SO +SOIC-8-N7_3.9x4.9mm_P1.27mm +8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC], pin 7 removed (Microchip Packaging Specification 00000049BS.pdf, http://www.onsemi.com/pub/Collateral/NCP1207B.PDF) +SOIC 1.27 +0 +7 +7 +Package_SO +SOIC-8_3.9x4.9mm_P1.27mm +SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +8 +8 +Package_SO +SOIC-8_5.23x5.23mm_P1.27mm +SOIC, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf#page=68), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +8 +8 +Package_SO +SOIC-8_5.275x5.275mm_P1.27mm +SOIC, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/20005045C.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +8 +8 +Package_SO +SOIC-8_7.5x5.85mm_P1.27mm +SOIC, 8 Pin (http://www.ti.com/lit/ml/mpds382b/mpds382b.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +8 +8 +Package_SO +SOIC-14W_7.5x9mm_P1.27mm +SOIC, 14 Pin (JEDEC MS-013AF, https://www.analog.com/media/en/package-pcb-resources/package/54614177245586rw_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +14 +14 +Package_SO +SOIC-14_3.9x8.7mm_P1.27mm +SOIC, 14 Pin (JEDEC MS-012AB, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_14.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +14 +14 +Package_SO +SOIC-16W-12_7.5x10.3mm_P1.27mm +SOIC-16 With 12 Pin Placed - Wide, 7.50 mm Body [SOIC] (https://docs.broadcom.com/docs/AV02-0169EN) +SOIC 1.27 16 12 Wide +0 +12 +12 +Package_SO +SOIC-16W_5.3x10.2mm_P1.27mm +16-Lead Plastic Small Outline (SO) - Wide, 5.3 mm Body (http://www.ti.com/lit/ml/msop002a/msop002a.pdf) +SOIC 1.27 +0 +16 +16 +Package_SO +SOIC-16W_7.5x10.3mm_P1.27mm +SOIC, 16 Pin (JEDEC MS-013AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/rw_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +16 +16 +Package_SO +SOIC-16W_7.5x12.8mm_P1.27mm +SOIC, 16 Pin (https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ri_soic_ic/ri_16_1.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +16 +16 +Package_SO +SOIC-16_3.9x9.9mm_P1.27mm +SOIC, 16 Pin (JEDEC MS-012AC, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +16 +16 +Package_SO +SOIC-16_4.55x10.3mm_P1.27mm +SOIC, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12858&prodName=TLP291-4), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +16 +16 +Package_SO +SOIC-18W_7.5x11.6mm_P1.27mm +SOIC, 18 Pin (JEDEC MS-013AB, https://www.analog.com/media/en/package-pcb-resources/package/33254132129439rw_18.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +18 +18 +Package_SO +SOIC-20W_7.5x12.8mm_P1.27mm +SOIC, 20 Pin (JEDEC MS-013AC, https://www.analog.com/media/en/package-pcb-resources/package/233848rw_20.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +20 +20 +Package_SO +SOIC-24W_7.5x15.4mm_P1.27mm +SOIC, 24 Pin (JEDEC MS-013AD, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_wide-rw/RW_24.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +24 +24 +Package_SO +SOIC-28W_7.5x17.9mm_P1.27mm +SOIC, 28 Pin (JEDEC MS-013AE, https://www.analog.com/media/en/package-pcb-resources/package/35833120341221rw_28.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +28 +28 +Package_SO +SOIC-28W_7.5x18.7mm_P1.27mm +SOIC, 28 Pin (https://www.akm.com/akm/en/file/datasheet/AK5394AVS.pdf#page=23), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOIC SO +0 +28 +28 +Package_SO +SOIJ-8_5.3x5.3mm_P1.27mm +8-Lead Plastic Small Outline (SM) - Medium, 5.28 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf) +SOIC 1.27 +0 +8 +8 +Package_SO +SOJ-36_10.16x23.49mm_P1.27mm +SOJ, 36 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOJ SO +0 +36 +36 +Package_SO +SOP-4_3.8x4.1mm_P2.54mm +SOP, 4 Pin (http://www.ixysic.com/home/pdfs.nsf/www/CPC1017N.pdf/$file/CPC1017N.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +4 +4 +Package_SO +SOP-4_4.4x2.6mm_P1.27mm +SOP, 4 Pin (http://www.vishay.com/docs/83510/tcmt1100.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +4 +4 +Package_SO +SOP-8-1EP_4.57x4.57mm_P1.27mm_EP4.57x4.45mm +SOP, 8 Pin (Mini-Circuits XX112 housing; https://ww2.minicircuits.com/case_style/XX112.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +13 +9 +Package_SO +SOP-8-1EP_4.57x4.57mm_P1.27mm_EP4.57x4.45mm_ThermalVias +SOP, 8 Pin (Mini-Circuits XX112 housing; https://ww2.minicircuits.com/case_style/XX112.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +20 +9 +Package_SO +SOP-8_3.9x4.9mm_P1.27mm +SOP, 8 Pin (http://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf#page=79), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +8 +8 +Package_SO +SOP-8_3.76x4.96mm_P1.27mm +SOP, 8 Pin (https://ww2.minicircuits.com/case_style/XX211.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +8 +8 +Package_SO +SOP-8_5.28x5.23mm_P1.27mm +SOP, 8 Pin (http://www.macronix.com/Lists/Datasheet/Attachments/7534/MX25R3235F,%20Wide%20Range,%2032Mb,%20v1.6.pdf#page=80), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +8 +8 +Package_SO +SOP-8_6.62x9.15mm_P2.54mm +SOP, 8 Pin (http://www.ti.com/lit/ds/symlink/iso1050.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +8 +8 +Package_SO +SOP-16_4.4x10.4mm_P1.27mm +16-Lead Plastic Small Outline http://www.vishay.com/docs/49633/sg2098.pdf +SOP 1.27 +0 +16 +16 +Package_SO +SOP-16_4.55x10.3mm_P1.27mm +SOP, 16 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=12855&prodName=TLP290-4), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +16 +16 +Package_SO +SOP-18_7x12.5mm_P1.27mm +SOP, 18 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=30523), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +18 +18 +Package_SO +SOP-24_7.5x15.4mm_P1.27mm +SOP, 24 Pin (http://www.issi.com/WW/pdf/31FL3218.pdf#page=14), generated with kicad-footprint-generator ipc_gullwing_generator.py +SOP SO +0 +24 +24 +Package_SO +SSO-4_6.7x5.1mm_P2.54mm_Clearance8mm +4-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/84299/vor1142b4.pdf +SSO Stretched SO SOIC 2.54 +0 +4 +4 +Package_SO +SSO-6_6.8x4.6mm_P1.27mm_Clearance7mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SSO Stretched SO SOIC 1.27 +0 +6 +6 +Package_SO +SSO-6_6.8x4.6mm_P1.27mm_Clearance8mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SSO Stretched SO SOIC 1.27 +0 +6 +6 +Package_SO +SSO-8_6.7x9.8mm_P2.54mm_Clearance8mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://www.vishay.com/docs/83831/lh1533ab.pdf +SSO Stretched SO SOIC Pitch 2.54 +0 +8 +8 +Package_SO +SSO-8_6.8x5.9mm_P1.27mm_Clearance7mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SSO Stretched SO SOIC Pitch 1.27 +0 +8 +8 +Package_SO +SSO-8_6.8x5.9mm_P1.27mm_Clearance8mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SSO Stretched SO SOIC Pitch 1.27 +0 +8 +8 +Package_SO +SSO-8_9.6x6.3mm_P1.27mm_Clearance10.5mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SSO Stretched SO SOIC Pitch 1.27 +0 +8 +8 +Package_SO +SSO-8_13.6x6.3mm_P1.27mm_Clearance14.2mm +8-Lead Plastic Stretched Small Outline (SSO/Stretched SO), see https://docs.broadcom.com/cs/Satellite?blobcol=urldata&blobheader=application%2Fpdf&blobheadername1=Content-Disposition&blobheadername2=Content-Type&blobheadername3=MDT-Type&blobheadervalue1=attachment%3Bfilename%3DIPD-Selection-Guide_AV00-0254EN_030617.pdf&blobheadervalue2=application%2Fx-download&blobheadervalue3=abinary%253B%2Bcharset%253DUTF-8&blobkey=id&blobnocache=true&blobtable=MungoBlobs&blobwhere=1430884105675&ssbinary=true +SSO Stretched SO SOIC Pitch 1.27 +0 +8 +8 +Package_SO +SSOP-8_2.95x2.8mm_P0.65mm +SSOP-8 2.9 x2.8mm Pitch 0.65mm +SSOP-8 2.95x2.8mm Pitch 0.65mm +0 +8 +8 +Package_SO +SSOP-8_3.9x5.05mm_P1.27mm +SSOP, 8 Pin (http://www.fujitsu.com/downloads/MICRO/fsa/pdf/products/memory/fram/MB85RS16-DS501-00014-6v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SSOP SO +0 +8 +8 +Package_SO +SSOP-8_3.95x5.21x3.27mm_P1.27mm +SSOP-8 3.95x5.21x3.27mm Pitch 1.27mm +SSOP-8 3.95x5.21x3.27mm 1.27mm +0 +8 +8 +Package_SO +SSOP-8_5.25x5.24mm_P1.27mm +SSOP, 8 Pin (http://www.fujitsu.com/ca/en/Images/MB85RS2MT-DS501-00023-1v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SSOP SO +0 +8 +8 +Package_SO +SSOP-10_3.9x4.9mm_P1.00mm +10-Lead SSOP, 3.9 x 4.9mm body, 1.00mm pitch (http://www.st.com/resource/en/datasheet/viper01.pdf) +SSOP 3.9 4.9 1.00 +0 +10 +10 +Package_SO +SSOP-14_5.3x6.2mm_P0.65mm +SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot337-1_po.pdf) +SSOP 0.65 +0 +14 +14 +Package_SO +SSOP-16_3.9x4.9mm_P0.635mm +SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot519-1_po.pdf) +SSOP 0.635 +0 +16 +16 +Package_SO +SSOP-16_4.4x5.2mm_P0.65mm +SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot369-1_po.pdf) +SSOP 0.65 +0 +16 +16 +Package_SO +SSOP-16_5.3x6.2mm_P0.65mm +SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot338-1_po.pdf) +SSOP 0.65 +0 +16 +16 +Package_SO +SSOP-18_4.4x6.5mm_P0.65mm +SSOP18: plastic shrink small outline package; 18 leads; body width 4.4 mm (http://toshiba.semicon-storage.com/info/docget.jsp?did=30523&prodName=TBD62783APG) +SSOP 0.65 +0 +18 +18 +Package_SO +SSOP-20_3.9x8.7mm_P0.635mm +SSOP20: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT231X.pdf) +SSOP 0.635 +0 +20 +20 +Package_SO +SSOP-20_4.4x6.5mm_P0.65mm +SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot266-1_po.pdf) +SSOP 0.65 +0 +20 +20 +Package_SO +SSOP-20_5.3x7.2mm_P0.65mm +SSOP, 20 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/40001800C.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SSOP SO +0 +20 +20 +Package_SO +SSOP-24_3.9x8.7mm_P0.635mm +SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot556-1_po.pdf) +SSOP 0.635 +0 +24 +24 +Package_SO +SSOP-24_5.3x8.2mm_P0.65mm +24-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +24 +24 +Package_SO +SSOP-28_3.9x9.9mm_P0.635mm +SSOP28: plastic shrink small outline package; 28 leads; body width 3.9 mm; lead pitch 0.635; (see http://cds.linear.com/docs/en/datasheet/38901fb.pdf) +SSOP 0.635 +0 +28 +28 +Package_SO +SSOP-28_5.3x10.2mm_P0.65mm +28-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +28 +28 +Package_SO +SSOP-32_11.305x20.495mm_P1.27mm +SSOP, 32 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +SSOP SO +0 +32 +32 +Package_SO +SSOP-44_5.3x12.8mm_P0.5mm +44-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (http://cds.linear.com/docs/en/datasheet/680313fa.pdf) +SSOP 0.5 +0 +44 +44 +Package_SO +SSOP-48_7.5x15.9mm_P0.635mm +SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot370-1_po.pdf) +SSOP 0.635 +0 +48 +48 +Package_SO +SSOP-56_7.5x18.5mm_P0.635mm +SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot371-1_po.pdf) +SSOP 0.635 +0 +56 +56 +Package_SO +STC_SOP-16_3.9x9.9mm_P1.27mm +STC SOP, 16 Pin (https://www.stcmicro.com/datasheet/STC15F2K60S2-en.pdf#page=156), generated with kicad-footprint-generator ipc_gullwing_generator.py +STC SOP SO +0 +16 +16 +Package_SO +ST_MultiPowerSO-30 +MultiPowerSO-30 3EP 16.0x17.2mm Pitch 1mm (http://www.st.com/resource/en/datasheet/vnh2sp30-e.pdf) +MultiPowerSO-30 3EP 16.0x17.2mm Pitch 1mm +0 +33 +33 +Package_SO +ST_PowerSSO-24_SlugDown +ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) +ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm +0 +25 +25 +Package_SO +ST_PowerSSO-24_SlugDown_ThermalVias +ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) +ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm +0 +38 +25 +Package_SO +ST_PowerSSO-24_SlugUp +ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7266p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) +ST PowerSSO-24 1EP 7.5x10.3mm Pitch 0.8mm +0 +24 +24 +Package_SO +ST_PowerSSO-36_SlugDown +ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) +ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm +0 +37 +37 +Package_SO +ST_PowerSSO-36_SlugDown_ThermalVias +ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) +ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm +0 +50 +37 +Package_SO +ST_PowerSSO-36_SlugUp +ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm [JEDEC MO-271] (http://www.st.com/resource/en/datasheet/tda7492p.pdf, http://freedatasheets.com/downloads/Technical%20Note%20Powersso24%20TN0054.pdf) +ST PowerSSO-36 1EP 7.5x10.3mm Pitch 0.8mm +0 +36 +36 +Package_SO +TI_SO-PowerPAD-8 +8-Lead Plastic PSOP, Exposed Die Pad (TI DDA0008B, see http://www.ti.com/lit/ds/symlink/lm3404.pdf) +SSOP 0.50 exposed pad +0 +12 +9 +Package_SO +TI_SO-PowerPAD-8_ThermalVias +8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf +HTSOP 1.27 +0 +19 +9 +Package_SO +TSOP-5_1.65x3.05mm_P0.95mm +TSOP-5 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf +Jedec MO-193C TSOP-5L +0 +5 +5 +Package_SO +TSOP-6_1.65x3.05mm_P0.95mm +TSOP-6 package (comparable to TSOT-23), https://www.vishay.com/docs/71200/71200.pdf +Jedec MO-193C TSOP-6L +0 +6 +6 +Package_SO +TSOP-I-28_11.8x8mm_P0.55mm +TSOP I, 28 pins, 18.8x8mm body, 0.55mm pitch, IPC-calculated pads (http://ww1.microchip.com/downloads/en/devicedoc/doc0807.pdf) +TSOP I 28 pins +0 +28 +28 +Package_SO +TSOP-I-32_11.8x8mm_P0.5mm +TSOP-I, 32 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +TSOP-I SO +0 +32 +32 +Package_SO +TSOP-I-32_18.4x8mm_P0.5mm +TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf, http://www.fujitsu.com/downloads/MICRO/fma/pdfmcu/f32pm25.pdf) +TSOP I 32 +0 +32 +32 +Package_SO +TSOP-I-32_18.4x8mm_P0.5mm_Reverse +TSOP I, 32 pins, 18.4x8mm body (http://www.futurlec.com/Datasheet/Memory/628128.pdf), reverse mount +TSOP I 32 reverse +0 +32 +32 +Package_SO +TSOP-I-48_18.4x12mm_P0.5mm +TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf) +TSOP I 32 +0 +48 +48 +Package_SO +TSOP-I-56_18.4x14mm_P0.5mm +TSOP I, 32 pins, 18.4x8mm body (https://www.micron.com/~/media/documents/products/technical-note/nor-flash/tn1225_land_pad_design.pdf) +TSOP I 32 +0 +56 +56 +Package_SO +TSOP-II-32_21.0x10.2mm_P1.27mm +32-lead plastic TSOP; Type II +TSOP-II 32 +0 +32 +32 +Package_SO +TSOP-II-44_10.16x18.41mm_P0.8mm +TSOP-II, 44 Pin (http://www.issi.com/WW/pdf/61-64C5128AL.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +TSOP-II SO +0 +44 +44 +Package_SO +TSOP-II-54_22.2x10.16mm_P0.8mm +54-lead TSOP typ II package +TSOPII TSOP2 +0 +54 +54 +Package_SO +TSSOP-8_3x3mm_P0.65mm +TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot505-1_po.pdf) +SSOP 0.65 +0 +8 +8 +Package_SO +TSSOP-8_4.4x3mm_P0.65mm +8-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +8 +8 +Package_SO +TSSOP-10_3x3mm_P0.5mm +TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot552-1_po.pdf) +SSOP 0.5 +0 +10 +10 +Package_SO +TSSOP-14-1EP_4.4x5mm_P0.65mm +14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] with exposed pad (http://cds.linear.com/docs/en/datasheet/34301fa.pdf) +SSOP 0.65 exposed pad +0 +18 +15 +Package_SO +TSSOP-14_4.4x5mm_P0.65mm +14-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +14 +14 +Package_SO +TSSOP-16-1EP_4.4x5mm_P0.65mm +FE Package; 16-Lead Plastic TSSOP (4.4mm); Exposed Pad Variation BB; (see Linear Technology 1956f.pdf) +SSOP 0.65 +0 +24 +17 +Package_SO +TSSOP-16_4.4x5mm_P0.65mm +16-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +16 +16 +Package_SO +TSSOP-20_4.4x6.5mm_P0.65mm +20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf) +SSOP 0.65 +0 +20 +20 +Package_SO +TSSOP-24_4.4x7.8mm_P0.65mm +TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot355-1_po.pdf) +SSOP 0.65 +0 +24 +24 +Package_SO +TSSOP-28-1EP_4.4x9.7mm_P0.65mm +TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; Exposed Pad Variation; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot361-1_po.pdf) +SSOP 0.65 +0 +36 +29 +Package_SO +TSSOP-28_4.4x9.7mm_P0.65mm +TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot361-1_po.pdf) +SSOP 0.65 +0 +28 +28 +Package_SO +TSSOP-30_4.4x7.8mm_P0.5mm +TSSOP30: plastic thin shrink small outline package; 30 leads; body width 4.4 mm (http://www.ti.com/lit/ds/symlink/bq78350.pdf) +SSOP 0.5 +0 +30 +30 +Package_SO +TSSOP-32_6.1x11mm_P0.65mm +TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot487-1_po.pdf) +SSOP 0.65 +0 +32 +32 +Package_SO +TSSOP-38_4.4x9.7mm_P0.5mm +TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot510-1_po.pdf) +SSOP 0.5 +0 +38 +38 +Package_SO +TSSOP-38_6.1x12.5mm_P0.65mm +TSSOP38: plastic thin shrink small outline package; 38 leads; body width 6.1 mm (http://www.ti.com/lit/ds/symlink/msp430g2744.pdf) +SSOP 0.65 +0 +38 +38 +Package_SO +TSSOP-44_4.4x11.2mm_P0.5mm +TSSOP44: plastic thin shrink small outline package; 44 leads; body width 4.4 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot510-1_po.pdf) +SSOP 0.5 +0 +44 +44 +Package_SO +TSSOP-48_6.1x12.5mm_P0.5mm +TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot362-1_po.pdf) +SSOP 0.5 +0 +48 +48 +Package_SO +TSSOP-56_6.1x14mm_P0.5mm +TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot364-1_po.pdf) +SSOP 0.5 +0 +56 +56 +Package_SO +Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm +Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf) +HSOP 1.27 +0 +11 +9 +Package_SO +Texas_HSOP-8-1EP_3.9x4.9mm_P1.27mm_ThermalVias +Texas Instruments HSOP 9, 1.27mm pitch, 3.9x4.9mm body, exposed pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf) +HSOP 1.27 +0 +20 +9 +Package_SO +Texas_HTSOP-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias +8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf +HTSOP 1.27 +0 +18 +9 +Package_SO +Texas_PWP0020A +20-Pin Thermally Enhanced Thin Shrink Small-Outline Package, Body 4.4x6.5x1.1mm, Pad 3.0x4.2mm, Texas Instruments (see http://www.ti.com/lit/ds/symlink/lm5118.pdf) +PWP HTSSOP 0.65mm +0 +25 +21 +Package_SO +Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm +HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HSOIC SO +0 +16 +9 +Package_SO +Texas_R-PDSO-G8_EP2.95x4.9mm_Mask2.4x3.1mm_ThermalVias +HSOIC, 8 Pin (http://www.ti.com/lit/ds/symlink/lmr14030.pdf#page=28, http://www.ti.com/lit/ml/msoi002j/msoi002j.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +HSOIC SO +0 +23 +9 +Package_SO +Texas_R-PDSO-N5 +Plastic Small outline http://www.ti.com/lit/ml/mpds158c/mpds158c.pdf +SOT23 R-PDSO-N5 +0 +5 +5 +Package_SO +VSO-40_7.6x15.4mm_P0.762mm +VSO40: plastic very small outline package; 40 leads (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot158-1_po.pdf) +SSOP 0.762 +0 +40 +40 +Package_SO +VSO-56_11.1x21.5mm_P0.75mm +VSO56: plastic very small outline package; 56 leads (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot190-1_po.pdf) +SSOP 0.75 +0 +56 +56 +Package_SO +VSSOP-8_2.3x2mm_P0.5mm +VSSOP-8 2.3x2mm Pitch 0.5mm +VSSOP-8 2.3x2mm Pitch 0.5mm +0 +8 +8 +Package_SO +VSSOP-8_2.4x2.1mm_P0.5mm +http://www.ti.com/lit/ml/mpds050d/mpds050d.pdf +VSSOP DCU R-PDSO-G8 Pitch0.5mm +0 +8 +8 +Package_SO +VSSOP-8_3.0x3.0mm_P0.65mm +VSSOP-8 3.0 x 3.0, http://www.ti.com/lit/ds/symlink/lm75b.pdf +VSSOP-8 3.0 x 3.0 +0 +8 +8 +Package_SO +VSSOP-10_3x3mm_P0.5mm +VSSOP, 10 Pin (http://www.ti.com/lit/ds/symlink/ads1115.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py +VSSOP SO +0 +10 +10 +Package_SO +Vishay_PowerPAK_1212-8_Dual +PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf) +Vishay_PowerPAK_1212-8_Dual +0 +6 +6 +Package_SO +Vishay_PowerPAK_1212-8_Single +PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf) +Vishay PowerPAK 1212-8 Single +0 +5 +5 +Package_SO +Zetex_SM8 +Zetex, SMD, 8 pin package (http://datasheet.octopart.com/ZDT6758TA-Zetex-datasheet-68057.pdf) +Zetex SM8 +0 +8 +8 +Package_SON +Diodes_PowerDI3333-8 +Diodes Incorporated PowerDI3333-8, Plastic Dual Flat No Lead Package, 3.3x3.3x0.8mm Body, https://www.diodes.com/assets/Package-Files/PowerDI3333-8.pdf +PowerDI 0.65 +0 +13 +5 +Package_SON +Fairchild_DualPower33-6_3x3mm +Fairchild Power33 MOSFET package, 3x3mm (see https://www.fairchildsemi.com/datasheets/FD/FDMC8032L.pdf) +mosfet +0 +18 +6 +Package_SON +Fairchild_MicroPak-6_1.0x1.45mm_P0.5mm +Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm https://www.nxp.com/docs/en/application-note/AN10343.pdff +Fairchild-specific MicroPak-6 1.0x1.45mm Pitch 0.5mm +0 +6 +6 +Package_SON +Fairchild_MicroPak2-6_1.0x1.0mm_P0.35mm +Fairchild-specific MicroPak2-6 1.0x1.0mm Pitch 0.35mm https://www.nxp.com/docs/en/application-note/AN10343.pdff +Fairchild-specific MicroPak2-6 1.0x1.0mm Pitch 0.35mm +0 +6 +6 +Package_SON +HUSON-3-1EP_2x2mm_P1.3mm_EP1.1x1.6mm +HUSON, 3 Pin, SOT1061 (Ref: https://assets.nexperia.com/documents/data-sheet/PMEG2020CPA.pdf) +huson nolead SOT1061 +0 +4 +3 +Package_SON +HVSON-8-1EP_4x4mm_P0.8mm_EP2.2x3.1mm +HVSON, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf (page 57)), generated with kicad-footprint-generator ipc_noLead_generator.py +HVSON NoLead +0 +13 +9 +Package_SON +Infineon_PG-TISON-8-2 +Infineon, PG-TISON-8-2, 5x6x1.15mm, 1.27mm Pitch, Exposed Paddle, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-2/ +tison +0 +23 +7 +Package_SON +Infineon_PG-TISON-8-3 +Infineon, PG-TISON-8-2, 5x6x1.15mm, 1.27mm Pitch, Exposed Paddle, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-2/ +tison +0 +23 +7 +Package_SON +Infineon_PG-TISON-8-4 +Infineon, PG-TISON-8-4, 5x6x1.15mm, 1.27mm Pitch, Exposed Paddle, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-4/ +tison +0 +26 +8 +Package_SON +Infineon_PG-TISON-8-5 +Infineon, PG-TISON-8-5, 8x8x1.1mm, 1mm Pitch, https://www.infineon.com/cms/en/product/packages/PG-TISON/PG-TISON-8-5/ +tison +0 +34 +8 +Package_SON +NXP_XSON-16 +http://www.nxp.com/documents/outline_drawing/SOT1341-1.pdf +NXP XSON SOT-1341 +0 +16 +16 +Package_SON +ROHM_VML0806 +VML0806, Rohm (http://rohmfs.rohm.com/en/techdata_basic/transistor/soldering_condition/VML0806_Soldering_Condition.pdf, http://rohmfs.rohm.com/en/products/databook/package/spec/discrete/vml0806_tr-e.pdf) +ROHM VML0806 +0 +3 +3 +Package_SON +RTC_SMD_MicroCrystal_C3_2.5x3.7mm +MicroCrystal C3 2.5x3.7mm, https://www.microcrystal.com/fileadmin/Media/Products/RTC/Datasheet/RV-1805-C3.pdf +RTC C3 +0 +10 +10 +Package_SON +SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm +SON, 8 Pin (http://www.fujitsu.com/downloads/MICRO/fsa/pdf/products/memory/fram/MB85RS16-DS501-00014-6v0-E.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +SON NoLead +0 +13 +9 +Package_SON +Texas_DQK +Texas WSON-6 DQK, http://www.ti.com/lit/ds/symlink/csd16301q2.pdf +Texas WSON6 2x2mm +0 +10 +8 +Package_SON +Texas_DRC0010J +Texas DRC0010J, VSON10 3x3mm Body, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/tps63000.pdf +Texas VSON10 3x3mm +0 +17 +11 +Package_SON +Texas_DRC0010J_ThermalVias +Texas DRC0010J, VSON10 3x3mm Body, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/tps63000.pdf +Texas VSON10 3x3mm +0 +21 +11 +Package_SON +Texas_DSC0010J +3x3mm Body, 0.5mm Pitch, DSC0010J, WSON, http://www.ti.com/lit/ds/symlink/tps61201.pdf +0.5 DSC0010J WSON +0 +33 +11 +Package_SON +Texas_DSC0010J_ThermalVias +3x3mm Body, 0.5mm Pitch, DSC0010J, WSON, http://www.ti.com/lit/ds/symlink/tps61201.pdf +0.5 DSC0010J WSON +0 +39 +11 +Package_SON +Texas_PWSON-N6 +Plastic Small Outline No-Lead http://www.ti.com/lit/ml/mpds176e/mpds176e.pdf +Plastic Small Outline No-Lead +0 +7 +7 +Package_SON +Texas_R-PWSON-N12_EP0.4x2mm +http://www.ti.com/lit/ds/symlink/tpd6f003.pdf +WSON SMD +0 +16 +13 +Package_SON +Texas_S-PDSO-N12 +http://www.ti.com/lit/ds/symlink/bq27441-g1.pdf +SON thermal pads +0 +44 +13 +Package_SON +Texas_S-PVSON-N8 +8-Lead Plastic VSON, 3x3mm Body, 0.65mm Pitch, S-PVSON-N8, http://www.ti.com/lit/ds/symlink/opa2333.pdf +DFN 0.65 S-PVSON-N8 +0 +21 +9 +Package_SON +Texas_S-PVSON-N8_ThermalVias +8-Lead Plastic VSON, 3x3mm Body, 0.65mm Pitch, S-PVSON-N8, http://www.ti.com/lit/ds/symlink/opa2333.pdf +DFN 0.65 S-PVSON-N8 +0 +27 +9 +Package_SON +Texas_S-PVSON-N10 +3x3mm Body, 0.5mm Pitch, S-PVSON-N10, DRC, http://www.ti.com/lit/ds/symlink/tps61201.pdf +0.5 S-PVSON-N10 DRC +0 +33 +11 +Package_SON +Texas_S-PVSON-N10_ThermalVias +3x3mm Body, 0.5mm Pitch, S-PVSON-N10, DRC, http://www.ti.com/lit/ds/symlink/tps61201.pdf +0.5 S-PVSON-N10 DRC +0 +39 +11 +Package_SON +Texas_S-PWSON-N8_EP1.2x2mm +WSON, 8 Pin (http://www.ti.com/lit/ds/symlink/lp2951.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +11 +9 +Package_SON +Texas_S-PWSON-N8_EP1.2x2mm_ThermalVias +WSON, 8 Pin (http://www.ti.com/lit/ds/symlink/lp2951.pdf#page=27), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +18 +9 +Package_SON +Texas_S-PWSON-N10 +3x3mm Body, 0.5mm Pitch, S-PWSON-N10, DSC, http://www.ti.com/lit/ds/symlink/tps63060.pdf +0.5 S-PWSON-N10 DSC +0 +41 +11 +Package_SON +Texas_S-PWSON-N10_ThermalVias +3x3mm Body, 0.5mm Pitch, S-PWSON-N10, DSC, http://www.ti.com/lit/ds/symlink/tps63060.pdf +0.5 S-PWSON-N10 DSC +0 +47 +11 +Package_SON +Texas_X2SON-4_1x1mm_P0.65mm +X2SON 5 pin 1x1mm package (Reference Datasheet: http://www.ti.com/lit/ds/sbvs193d/sbvs193d.pdf Reference part: TPS383x) [StepUp generated footprint] +X2SON +0 +13 +5 +Package_SON +USON-10_2.5x1.0mm_P0.5mm +USON-10 2.5x1.0mm_ Pitch 0.5mm http://www.ti.com/lit/ds/symlink/tpd4e02b04.pdf +USON-10 2.5x1.0mm Pitch 0.5mm +0 +10 +10 +Package_SON +USON-20_2x4mm_P0.4mm +USON-20 2x4mm Pitch 0.4mm http://www.ti.com/lit/ds/symlink/txb0108.pdf +USON-20 2x4mm Pitch 0.4mm +0 +20 +20 +Package_SON +VSON-8_3.3x3.3mm_P0.65mm_NexFET +8-Lead Plastic Dual Flat, No Lead Package (MF) - 3.3x3.3x1 mm Body [VSON] http://www.ti.com/lit/ds/symlink/csd87334q3d.pdf +VSON 0.65 +0 +12 +5 +Package_SON +VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm +VSON, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_noLead_generator.py +VSON NoLead +0 +15 +11 +Package_SON +VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm_ThermalVias +VSON, 10 Pin (http://rohmfs.rohm.com/en/products/databook/datasheet/ic/power/switching_regulator/bd8314nuv-e.pdf (Page 20)), generated with kicad-footprint-generator ipc_noLead_generator.py +VSON NoLead +0 +18 +11 +Package_SON +VSON-10-1EP_3x3mm_P0.5mm_EP1.65x2.4mm +VSON 10 Thermal on 11 3x3mm Pitch 0.5mm http://chip.tomsk.ru/chip/chipdoc.nsf/Package/D8A64DD165C2AAD9472579400024FC41!OpenDocument +VSON 10 Thermal on 11 3x3mm Pitch 0.5mm +0 +21 +11 +Package_SON +VSON-10-1EP_3x3mm_P0.5mm_EP1.65x2.4mm_ThermalVias +VSON 10 Thermal on 11 3x3mm Pitch 0.5mm http://chip.tomsk.ru/chip/chipdoc.nsf/Package/D8A64DD165C2AAD9472579400024FC41!OpenDocument +VSON 10 Thermal on 11 3x3mm Pitch 0.5mm +0 +27 +11 +Package_SON +VSONP-8-1EP_5x6_P1.27mm +SON, 8-Leads, Body 5x6x1mm, Pitch 1.27mm; (see Texas Instruments CSD18531Q5A http://www.ti.com/lit/ds/symlink/csd18531q5a.pdf) +VSONP 1.27 +0 +13 +3 +Package_SON +WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm +WSON, 6 Pin (http://www.ti.com/lit/ds/symlink/tps61040.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +9 +7 +Package_SON +WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm_ThermalVias +WSON, 6 Pin (http://www.ti.com/lit/ds/symlink/tps61040.pdf#page=35), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +12 +7 +Package_SON +WSON-6-1EP_3x3mm_P0.95mm +WSON6 3*3 MM, 0.95 PITCH; http://www.ti.com/lit/ds/symlink/lmr62421.pdf +WSON6 0.95 +0 +10 +7 +Package_SON +WSON-6_1.5x1.5mm_P0.5mm +WSON6, http://www.ti.com/lit/ds/symlink/tlv702.pdf +WSON6_1.5x1.5mm_P0.5mm +0 +6 +6 +Package_SON +WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm +8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf +WSON 8 1EP +0 +11 +9 +Package_SON +WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm_ThermalVias +8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf +WSON 8 1EP ThermalVias +0 +14 +9 +Package_SON +WSON-8-1EP_3x2.5mm_P0.5mm_EP1.2x1.5mm_PullBack +WSON, 8 Pin (http://www.ti.com/lit/ml/mpds400/mpds400.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +13 +9 +Package_SON +WSON-8-1EP_3x2.5mm_P0.5mm_EP1.2x1.5mm_PullBack_ThermalVias +WSON, 8 Pin (http://www.ti.com/lit/ml/mpds400/mpds400.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +18 +9 +Package_SON +WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm +8-Lead Plastic WSON, 2x2mm Body, 0.5mm Pitch, WSON-8, http://www.ti.com/lit/ds/symlink/lm27761.pdf +WSON 8 1EP +0 +13 +9 +Package_SON +WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm +WSON, 8 Pin (http://www.winbond.com/resource-files/w25q32jv%20revg%2003272018%20plus.pdf (page 68)), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +13 +9 +Package_SON +WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4mm +WSON, 8 Pin (http://ww1.microchip.com/downloads/en/AppNotes/S72030.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +13 +9 +Package_SON +WSON-8_4x4mm_P0.8mm +http://www.ti.com/lit/ml/mpds406/mpds406.pdf +WSON8_4x4mm_P0.8mm +0 +9 +9 +Package_SON +WSON-10-1EP_2x3mm_P0.5mm_EP0.84x2.4mm +WSON-10 package 2x3mm body, pitch 0.5mm, see http://www.ti.com/lit/ds/symlink/tps62177.pdf +WSON 0.5 +0 +14 +11 +Package_SON +WSON-10-1EP_2x3mm_P0.5mm_EP0.84x2.4mm_ThermalVias +WSON-10 package 2x3mm body, pitch 0.5mm, thermal vias and counter-pad, see http://www.ti.com/lit/ds/symlink/tps62177.pdf +WSON 0.5 thermal vias +0 +17 +11 +Package_SON +WSON-10-1EP_4x3mm_P0.5mm_EP2.2x2mm +10-Lead Plastic WSON, 4x3mm Body, 0.5mm Pitch (http://www.ti.com/lit/ds/symlink/lm4990.pdf) +WSON 0.5 +0 +15 +11 +Package_SON +WSON-12-1EP_3x2mm_P0.5mm_EP1x2.65 +WSON-12 http://www.ti.com/lit/ds/symlink/lm27762.pdf +WSON-12 +0 +15 +13 +Package_SON +WSON-12-1EP_3x2mm_P0.5mm_EP1x2.65_ThermalVias +WSON-12 http://www.ti.com/lit/ds/symlink/lm27762.pdf +WSON-12 +0 +19 +13 +Package_SON +WSON-12-1EP_4x4mm_P0.5mm_EP2.6x3mm +WSON, 12 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=62), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +17 +13 +Package_SON +WSON-12-1EP_4x4mm_P0.5mm_EP2.6x3mm_ThermalVias +WSON, 12 Pin (http://www.ti.com/lit/ds/symlink/ldc1312.pdf#page=62), generated with kicad-footprint-generator ipc_noLead_generator.py +WSON NoLead +0 +27 +13 +Package_SON +WSON-14-1EP_4.0x4.0mm_P0.5mm_EP2.6x2.6mm +14-Lead Plastic Dual Flat, No Lead Package - 4.0x4.0x0.8 mm Body [WSON], http://www.ti.com/lit/ml/mpds421/mpds421.pdf +NHL014B +0 +19 +15 +Package_SON +WSON-16_3.3x1.35_P0.4mm +WSON-16 3.3 x 1.35mm Pitch 0.4mm http://www.chip.tomsk.ru/chip/chipdoc.nsf/Package/C67E729A4D6C883A4725793E004C8739!OpenDocument +WSON-16 3.3 x 1.35mm Pitch 0.4mm +0 +20 +17 +Package_SON +X2SON-8_1.4x1mm_P0.35mm +X2SON-8 1.4x1mm Pitch0.35mm http://www.ti.com/lit/ds/symlink/pca9306.pdf +X2SON-8 1.4x1mm Pitch0.35mm +0 +8 +8 +Package_SO_J-Lead +TSOC-6_3.76x3.94mm_P1.27mm +Maxim Integrated TSOC-6 D6+1,https://datasheets.maximintegrated.com/en/ds/DS2401.pdf, https://pdfserv.maximintegrated.com/land_patterns/90-0321.PDF +TSOC-6 +0 +6 +6 +Package_TO_SOT_SMD +ATPAK-2 +ATPAK SMD package, http://www.onsemi.com/pub/Collateral/ENA2192-D.PDF +ATPAK +0 +7 +3 +Package_TO_SOT_SMD +Analog_KS-4 +Analog Devices KS-4, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sc70ks/ks_4.pdf +Analog Devices KS-4 (like EIAJ SC-82) +0 +4 +4 +Package_TO_SOT_SMD +Diodes_SOT-553 +Diodes SOT-553, https://www.diodes.com/assets/Package-Files/SOT553.pdf +SOT-553 +0 +5 +5 +Package_TO_SOT_SMD +HVSOF5 +HVSOF5, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hvsof5_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/sensor/hall/bu52001gul-e.pdf +HVSOF5 +0 +5 +5 +Package_TO_SOT_SMD +HVSOF6 +HVSOF6, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hvsof6_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/audio_video/video_amplifier/bh76106hfv-e.pdf +HVSOF6 +0 +7 +7 +Package_TO_SOT_SMD +Infineon_PG-HDSOP-10-1 +Infineon PG-HDSOP-10-1 (DDPAK), 20.96x6.5x2.3mm, slug up (https://www.infineon.com/cms/en/product/packages/PG-HDSOP/PG-HDSOP-10-1/) +hdsop 10 ddpak +0 +10 +10 +Package_TO_SOT_SMD +Infineon_PG-HSOF-8-1 +Infineon HSOF-8-1 power mosfet http://www.infineon.com/cms/en/product/packages/PG-HSOF/PG-HSOF-8-1/ +mosfet hsof +0 +54 +3 +Package_TO_SOT_SMD +Infineon_PG-HSOF-8-1_ThermalVias +HSOF-8-1 power mosfet http://www.infineon.com/cms/en/product/packages/PG-HSOF/PG-HSOF-8-1/ +mosfet hsof thermal vias +0 +57 +3 +Package_TO_SOT_SMD +Infineon_PG-TO-220-7Lead_TabPin8 +Infineon PG-TO-220-7, Tab as Pin 8, see e.g. https://www.infineon.com/dgdl/Infineon-BTS50055-1TMC-DS-v01_00-EN.pdf?fileId=5546d4625a888733015aa9b0007235e9 +Infineon PG-TO-220-7 +0 +12 +8 +Package_TO_SOT_SMD +LFPAK33 +LFPAK33 SOT-1210 https://assets.nexperia.com/documents/outline-drawing/SOT1210.pdf +LFPAK33 SOT-1210 +0 +17 +5 +Package_TO_SOT_SMD +LFPAK56 +LFPAK56 https://assets.nexperia.com/documents/outline-drawing/SOT669.pdf +LFPAK56 SOT-669 Power-SO8 +0 +18 +5 +Package_TO_SOT_SMD +OnSemi_ECH8 +On Semiconductor ECH8, https://www.onsemi.com/pub/Collateral/318BF.PDF +ECH8 SOT28-FL SOT-28-FL +0 +8 +8 +Package_TO_SOT_SMD +PQFN_8x8 +Low Profile 8x8mm PQFN, Dual Cool 88, https://www.onsemi.com/pub/Collateral/FDMT80080DC-D.pdf +pqfn vdfn mosfet +0 +9 +3 +Package_TO_SOT_SMD +PowerMacro_M234_NoHole +TO-50-4 Power Macro Package Style M234 +TO-50-4 Power Macro Package Style M234 +0 +4 +4 +Package_TO_SOT_SMD +PowerMacro_M234_WithHole +TO-50-4 Power Macro Package Style M234 +TO-50-4 Power Macro Package Style M234 +0 +4 +4 +Package_TO_SOT_SMD +Rohm_HRP7 +Rohm HRP7 SMD package, http://rohmfs.rohm.com/en/techdata_basic/ic/package/hrp7_1-e.pdf, http://rohmfs.rohm.com/en/products/databook/datasheet/ic/motor/dc/bd621x-e.pdf +Rohm HRP7 SMD +0 +69 +7 +Package_TO_SOT_SMD +SC-59 +SC-59, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg +SC-59 +0 +3 +3 +Package_TO_SOT_SMD +SC-59_Handsoldering +SC-59, hand-soldering varaint, https://lib.chipdip.ru/images/import_diod/original/SOT-23_SC-59.jpg +SC-59 hand-soldering +0 +3 +3 +Package_TO_SOT_SMD +SC-70-8 +SC70-8 +SC70-8 +0 +8 +8 +Package_TO_SOT_SMD +SC-70-8_Handsoldering +SC70-8, Handsoldering +SC70-8 Handsoldering +0 +8 +8 +Package_TO_SOT_SMD +SC-82AA +SC-82AA +SC-82AA +0 +4 +4 +Package_TO_SOT_SMD +SC-82AA_Handsoldering +SC-82AA +SC-82AA +0 +4 +4 +Package_TO_SOT_SMD +SC-82AB +SC-82AB +SC-82AB +0 +4 +4 +Package_TO_SOT_SMD +SC-82AB_Handsoldering +SC-82AB +SC-82AB +0 +4 +4 +Package_TO_SOT_SMD +SOT-23 +SOT-23, Standard +SOT-23 +0 +3 +3 +Package_TO_SOT_SMD +SOT-23-5 +5-pin SOT23 package +SOT-23-5 +0 +5 +5 +Package_TO_SOT_SMD +SOT-23-5_HandSoldering +5-pin SOT23 package +SOT-23-5 hand-soldering +0 +5 +5 +Package_TO_SOT_SMD +SOT-23-6 +6-pin SOT-23 package +SOT-23-6 +0 +6 +6 +Package_TO_SOT_SMD +SOT-23-6_Handsoldering +6-pin SOT-23 package, Handsoldering +SOT-23-6 Handsoldering +0 +6 +6 +Package_TO_SOT_SMD +SOT-23-8 +8-pin SOT-23 package, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sot-23rj/rj_8.pdf +SOT-23-8 +0 +8 +8 +Package_TO_SOT_SMD +SOT-23-8_Handsoldering +8-pin SOT-23 package, Handsoldering, http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/sot-23rj/rj_8.pdf +SOT-23-8 Handsoldering +0 +8 +8 +Package_TO_SOT_SMD +SOT-23W +SOT-23W http://www.allegromicro.com/~/media/Files/Datasheets/A112x-Datasheet.ashx?la=en&hash=7BC461E058CC246E0BAB62433B2F1ECA104CA9D3 +SOT-23W +0 +3 +3 +Package_TO_SOT_SMD +SOT-23W_Handsoldering +SOT-23W http://www.allegromicro.com/~/media/Files/Datasheets/A112x-Datasheet.ashx?la=en&hash=7BC461E058CC246E0BAB62433B2F1ECA104CA9D3 +SOT-23W for handsoldering +0 +3 +3 +Package_TO_SOT_SMD +SOT-23_Handsoldering +SOT-23, Handsoldering +SOT-23 +0 +3 +3 +Package_TO_SOT_SMD +SOT-89-3 +SOT-89-3 +SOT-89-3 +0 +6 +3 +Package_TO_SOT_SMD +SOT-89-3_Handsoldering +SOT-89-3 Handsoldering +SOT-89-3 Handsoldering +0 +5 +3 +Package_TO_SOT_SMD +SOT-89-5 +SOT-89-5, Housing,http://www.e-devices.ricoh.co.jp/en/products/product_power/pkg/sot-89-5.pdf +SOT-89-5 Housing +0 +9 +5 +Package_TO_SOT_SMD +SOT-89-5_Handsoldering +SOT89-5, Housing,http://www.e-devices.ricoh.co.jp/en/products/product_power/pkg/sot-89-5.pdf +SOT89-5 Housing +0 +9 +5 +Package_TO_SOT_SMD +SOT-143 +SOT-143 +SOT-143 +0 +4 +4 +Package_TO_SOT_SMD +SOT-143R_Reverse +SOT-143R Reverse +SOT-143R Reverse +0 +4 +4 +Package_TO_SOT_SMD +SOT-143R_Reverse_Handsoldering +SOT-143R Reverse Handsoldering +SOT-143 Reverse Handsoldering +0 +4 +4 +Package_TO_SOT_SMD +SOT-143_Handsoldering +SOT-143 Handsoldering +SOT-143 Handsoldering +0 +4 +4 +Package_TO_SOT_SMD +SOT-223 +module CMS SOT223 4 pins +CMS SOT +0 +4 +4 +Package_TO_SOT_SMD +SOT-223-3_TabPin2 +module CMS SOT223 4 pins +CMS SOT +0 +4 +3 +Package_TO_SOT_SMD +SOT-223-5 +module CMS SOT223 5 pins, http://ww1.microchip.com/downloads/en/DeviceDoc/51751a.pdf +CMS SOT +0 +5 +5 +Package_TO_SOT_SMD +SOT-223-6 +module CMS SOT223 6 pins, http://www.ti.com/lit/ds/symlink/tps737.pdf +CMS SOT +0 +6 +6 +Package_TO_SOT_SMD +SOT-223-6_TabPin3 +module CMS SOT223 6 pins, http://www.ti.com/lit/ds/symlink/tps737.pdf +CMS SOT +0 +6 +5 +Package_TO_SOT_SMD +SOT-223-8 +module CMS SOT223 8 pins, https://www.diodes.com/assets/Datasheets/ZXSBMR16PT8.pdf +CMS SOT +0 +8 +8 +Package_TO_SOT_SMD +SOT-323_SC-70 +SOT-323, SC-70 +SOT-323 SC-70 +0 +3 +3 +Package_TO_SOT_SMD +SOT-323_SC-70_Handsoldering +SOT-323, SC-70 Handsoldering +SOT-323 SC-70 Handsoldering +0 +3 +3 +Package_TO_SOT_SMD +SOT-343_SC-70-4 +SOT-343, SC-70-4 +SOT-343 SC-70-4 +0 +4 +4 +Package_TO_SOT_SMD +SOT-343_SC-70-4_Handsoldering +SOT-343, SC-70-4, Handsoldering +SOT-343 SC-70-4 Handsoldering +0 +4 +4 +Package_TO_SOT_SMD +SOT-353_SC-70-5 +SOT-353, SC-70-5 +SOT-353 SC-70-5 +0 +5 +5 +Package_TO_SOT_SMD +SOT-353_SC-70-5_Handsoldering +SOT-353, SC-70-5, Handsoldering +SOT-353 SC-70-5 Handsoldering +0 +5 +5 +Package_TO_SOT_SMD +SOT-363_SC-70-6 +SOT-363, SC-70-6 +SOT-363 SC-70-6 +0 +6 +6 +Package_TO_SOT_SMD +SOT-363_SC-70-6_Handsoldering +SOT-363, SC-70-6, Handsoldering +SOT-363 SC-70-6 Handsoldering +0 +6 +6 +Package_TO_SOT_SMD +SOT-383F +8-pin SOT-383F, http://www.mouser.com/ds/2/80/CPDVR085V0C-HF-RevB-10783.pdf +SOT-383F +0 +9 +9 +Package_TO_SOT_SMD +SOT-383FL +8-pin SOT-383FL package, http://www.onsemi.com/pub_link/Collateral/ENA2267-D.PDF +SOT-383FL +0 +8 +8 +Package_TO_SOT_SMD +SOT-416 +SOT-416, https://www.nxp.com/docs/en/package-information/SOT416.pdf +SOT-416 +0 +3 +3 +Package_TO_SOT_SMD +SOT-543 +SOT-543 4 lead surface package +SOT-543 SC-107A EMD4 +0 +4 +4 +Package_TO_SOT_SMD +SOT-553 +SOT553 +SOT-553 +0 +5 +5 +Package_TO_SOT_SMD +SOT-563 +SOT563 +SOT-563 +0 +6 +6 +Package_TO_SOT_SMD +SOT-665 +SOT665 +SOT-665 +0 +5 +5 +Package_TO_SOT_SMD +SOT-666 +SOT666 +SOT-666 +0 +6 +6 +Package_TO_SOT_SMD +SOT-723 +http://toshiba.semicon-storage.com/info/docget.jsp?did=5879&prodName=RN1104MFV +sot 723 +0 +3 +3 +Package_TO_SOT_SMD +SOT-883 +SOT-883, https://assets.nexperia.com/documents/outline-drawing/SOT883.pdf +SOT-883 +0 +3 +3 +Package_TO_SOT_SMD +SOT-886 +SOT-886 +SOT-886 +0 +6 +6 +Package_TO_SOT_SMD +SOT-963 +SOT 963 6 pins package 1x0.8mm pitch 0.35mm +SOT 963 6 pins package 1x0.8mm pitch 0.35mm +0 +6 +6 +Package_TO_SOT_SMD +SOT-1123 +SOT-1123 small outline transistor (see http://www.onsemi.com/pub/Collateral/NST3906F3-D.PDF) +SOT-1123 transistor +0 +3 +3 +Package_TO_SOT_SMD +SOT-1333-1 +SOT-1333-1 +SOT-1333-1 +0 +9 +9 +Package_TO_SOT_SMD +SOT-1334-1 +SOT-1334-1 +SOT-1334-1 +0 +14 +14 +Package_TO_SOT_SMD +SuperSOT-3 +3-pin SuperSOT package https://www.fairchildsemi.com/package-drawings/MA/MA03B.pdf +SuperSOT-3 SSOT-3 +0 +3 +3 +Package_TO_SOT_SMD +SuperSOT-6 +6-pin SuperSOT package http://www.mouser.com/ds/2/149/FMB5551-889214.pdf +SuperSOT-6 SSOT-6 +0 +6 +6 +Package_TO_SOT_SMD +SuperSOT-8 +8-pin SuperSOT package, http://www.icbank.com/icbank_data/semi_package/ssot8_dim.pdf +SuperSOT-8 SSOT-8 +0 +8 +8 +Package_TO_SOT_SMD +TDSON-8-1 +Power MOSFET package, TDSON-8-1, 5.15x5.9mm (https://www.infineon.com/cms/en/product/packages/PG-TDSON/PG-TDSON-8-1/) +tdson +0 +14 +5 +Package_TO_SOT_SMD +TO-50-3_LongPad-NoHole_Housing +TO-50-3 Macro T Package Style M236 +TO-50-3 Macro T Package Style M236 +0 +3 +3 +Package_TO_SOT_SMD +TO-50-3_LongPad-WithHole_Housing +TO-50-3 Macro T Package Style M236 +TO-50-3 Macro T Package Style M236 +0 +3 +3 +Package_TO_SOT_SMD +TO-50-3_ShortPad-NoHole_Housing +TO-50-3 Macro T Package Style M236 +TO-50-3 Macro T Package Style M236 +0 +3 +3 +Package_TO_SOT_SMD +TO-50-3_ShortPad-WithHole_Housing +TO-50-3 Macro T Package Style M236 +TO-50-3 Macro T Package Style M236 +0 +3 +3 +Package_TO_SOT_SMD +TO-50-4_LongPad-NoHole_Housing +TO-50-4 Macro X Package Style M238 +TO-50-4 Macro X Package Style M238 +0 +4 +4 +Package_TO_SOT_SMD +TO-50-4_LongPad-WithHole_Housing +TO-50-4 Macro X Package Style M238 +TO-50-4 Macro X Package Style M238 +0 +4 +4 +Package_TO_SOT_SMD +TO-50-4_ShortPad-NoHole_Housing +TO-50-4 Macro X Package Style M238 +TO-50-4 Macro X Package Style M238 +0 +4 +4 +Package_TO_SOT_SMD +TO-50-4_ShortPad-WithHole_Housing +TO-50-4 Macro X Package Style M238 +TO-50-4 Macro X Package Style M238 +0 +4 +4 +Package_TO_SOT_SMD +TO-252-2 +TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/ +DPAK TO-252 DPAK-3 TO-252-3 SOT-428 +0 +7 +3 +Package_TO_SOT_SMD +TO-252-2_TabPin1 +TO-252-2, tab to pin 1 https://www.wolfspeed.com/media/downloads/87/CSD01060.pdf +TO-252-2 diode +0 +7 +2 +Package_TO_SOT_SMD +TO-252-3_TabPin2 +TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/ +DPAK TO-252 DPAK-3 TO-252-3 SOT-428 +0 +8 +3 +Package_TO_SOT_SMD +TO-252-3_TabPin4 +TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-3-1/ +DPAK TO-252 DPAK-3 TO-252-3 SOT-428 +0 +8 +4 +Package_TO_SOT_SMD +TO-252-4 +TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/ +DPAK TO-252 DPAK-5 TO-252-5 +0 +9 +5 +Package_TO_SOT_SMD +TO-252-5_TabPin3 +TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/ +DPAK TO-252 DPAK-5 TO-252-5 +0 +10 +5 +Package_TO_SOT_SMD +TO-252-5_TabPin6 +TO-252 / DPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO252/PG-TO252-5-11/ +DPAK TO-252 DPAK-5 TO-252-5 +0 +10 +6 +Package_TO_SOT_SMD +TO-263-2 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/ +D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 +0 +7 +3 +Package_TO_SOT_SMD +TO-263-2_TabPin1 +TO-263 / D2PAK / DDPAK SMD package, tab to pin 1, https://www.wolfspeed.com/media/downloads/137/C3D06060G.pdf +D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 diode +0 +7 +2 +Package_TO_SOT_SMD +TO-263-3_TabPin2 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/ +D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 +0 +8 +3 +Package_TO_SOT_SMD +TO-263-3_TabPin4 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-3-1/ +D2PAK DDPAK TO-263 D2PAK-3 TO-263-3 SOT-404 +0 +8 +4 +Package_TO_SOT_SMD +TO-263-4 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ +D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426 +0 +9 +5 +Package_TO_SOT_SMD +TO-263-5_TabPin3 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ +D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426 +0 +10 +5 +Package_TO_SOT_SMD +TO-263-5_TabPin6 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-5-1/ +D2PAK DDPAK TO-263 D2PAK-5 TO-263-5 SOT-426 +0 +10 +6 +Package_TO_SOT_SMD +TO-263-6 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/ +D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 +0 +11 +7 +Package_TO_SOT_SMD +TO-263-7_TabPin4 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/ +D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 +0 +12 +7 +Package_TO_SOT_SMD +TO-263-7_TabPin8 +TO-263 / D2PAK / DDPAK SMD package, http://www.infineon.com/cms/en/product/packages/PG-TO263/PG-TO263-7-1/ +D2PAK DDPAK TO-263 D2PAK-7 TO-263-7 SOT-427 +0 +12 +8 +Package_TO_SOT_SMD +TO-263-9_TabPin5 +TO-263 / D2PAK / DDPAK SMD package, http://www.ti.com/lit/ds/symlink/lm4755.pdf +D2PAK DDPAK TO-263 D2PAK-9 TO-263-9 +0 +14 +9 +Package_TO_SOT_SMD +TO-263-9_TabPin10 +TO-263 / D2PAK / DDPAK SMD package, http://www.ti.com/lit/ds/symlink/lm4755.pdf +D2PAK DDPAK TO-263 D2PAK-9 TO-263-9 +0 +14 +10 +Package_TO_SOT_SMD +TO-268-2 +TO-268/D3PAK SMD package, http://www.icbank.com/icbank_data/semi_package/to268aa_dim.pdf +D3PAK TO-268 D3PAK-3 TO-268-3 +0 +7 +3 +Package_TO_SOT_SMD +TO-269AA +SMD package TO-269AA (e.g. diode bridge), see http://www.vishay.com/docs/88854/padlayouts.pdf +TO-269AA MBS diode bridge +0 +4 +4 +Package_TO_SOT_SMD +TO-277A +Thermal enhanced ultra thin SMD package; 3 leads; body: 4.3x6.1x0.43mm, https://www.vishay.com/docs/95570/to-277asmpc.pdf +TO-277A SMPC +0 +12 +3 +Package_TO_SOT_SMD +TO-277B +TO-227B https://media.digikey.com/pdf/Data%20Sheets/Littelfuse%20PDFs/DST2050S.pdf +TO-277B +0 +9 +3 +Package_TO_SOT_SMD +TSOT-23 +3-pin TSOT23 package, http://www.analog.com.tw/pdf/All_In_One.pdf +TSOT-23 +0 +3 +3 +Package_TO_SOT_SMD +TSOT-23-5 +5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf +TSOT-23-5 +0 +5 +5 +Package_TO_SOT_SMD +TSOT-23-5_HandSoldering +5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf +TSOT-23-5 Hand-soldering +0 +5 +5 +Package_TO_SOT_SMD +TSOT-23-6 +6-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_6_05-08-1636.pdf +TSOT-23-6 MK06A TSOT-6 +0 +6 +6 +Package_TO_SOT_SMD +TSOT-23-6_HandSoldering +6-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_6_05-08-1636.pdf +TSOT-23-6 MK06A TSOT-6 Hand-soldering +0 +6 +6 +Package_TO_SOT_SMD +TSOT-23-8 +8-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf +TSOT-23-8 +0 +8 +8 +Package_TO_SOT_SMD +TSOT-23-8_HandSoldering +8-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf +TSOT-23-8 Hand-soldering +0 +8 +8 +Package_TO_SOT_SMD +TSOT-23_HandSoldering +5-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_5_05-08-1635.pdf +TSOT-23 Hand-soldering +0 +3 +3 +Package_TO_SOT_SMD +Texas_DRT-3 +Texas Instrument DRT-3 1x0.8mm Pitch 0.7mm http://www.ti.com/lit/ds/symlink/tpd2eusb30.pdf +DRT-3 1x0.8mm Pitch 0.7mm +0 +3 +3 +Package_TO_SOT_SMD +Texas_NDY0011A +TO-PMOD-11 11-pin switching regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf +Texas TO-PMOD NDY00011A +0 +12 +12 +Package_TO_SOT_SMD +Texas_R-PDSO-G6 +R-PDSO-G6, http://www.ti.com/lit/ds/slis144b/slis144b.pdf +R-PDSO-G6 SC-70-6 +0 +6 +6 +Package_TO_SOT_SMD +VSOF5 +VSOF5 +VSOF5 +0 +5 +5 +Package_TO_SOT_SMD +Vishay_PowerPAK_SC70-6L_Dual +Vishay PowerPAK SC70 dual transistor package http://www.vishay.com/docs/70487/70487.pdf +powerpak sc70 sc-70 dual +0 +8 +6 +Package_TO_SOT_SMD +Vishay_PowerPAK_SC70-6L_Single +Vishay PowerPAK SC70 single transistor package http://www.vishay.com/docs/70486/70486.pdf +powerpak sc70 sc-70 +0 +6 +3 +Package_TO_SOT_THT +Fairchild_TO-220F-6L +Fairchild TO-220F-6L, http://www.mouser.com/ds/2/149/FSL136MRT-113334.pdf +Fairchild TO-220F-6L +0 +6 +6 +Package_TO_SOT_THT +Heraeus_TO-92-2 +TO-92 2-pin variant by Heraeus, drill 0.75mm (http://www.produktinfo.conrad.com/datenblaetter/175000-199999/181293-da-01-de-TO92_Temperatursensor_PT1000_32209225.pdf) +to-92 +0 +2 +2 +Package_TO_SOT_THT +NEC_Molded_7x4x9mm +Molded Japan Transistor Package 7x4x9mm^3, http://rtellason.com/transdata/2sb734.pdf +Japan transistor +0 +3 +3 +Package_TO_SOT_THT +PowerIntegrations_TO-220-7C +Non Isolated Modified TO-220 7pin Package, see http://www.farnell.com/datasheets/5793.pdf +Power Integration Y Package +0 +6 +6 +Package_TO_SOT_THT +SIPAK-1EP_Horizontal_TabDown +SIPAK, Horizontal, RM 2.286mm +SIPAK Horizontal RM 2.286mm +0 +4 +4 +Package_TO_SOT_THT +SIPAK_Vertical +SIPAK, Vertical, RM 2.286mm +SIPAK Vertical RM 2.286mm +0 +3 +3 +Package_TO_SOT_THT +SOD-70_P2.54mm +Plastic near cylindrical package Sod-70 see: https://www.nxp.com/docs/en/data-sheet/KTY81_SER.pdf [StepUp generated footprint] +Sod-70 +0 +2 +2 +Package_TO_SOT_THT +SOD-70_P5.08mm +Plastic near cylindrical package Sod-70 see: https://www.nxp.com/docs/en/data-sheet/KTY81_SER.pdf [StepUp generated footprint] +Sod-70 +0 +2 +2 +Package_TO_SOT_THT +SOT-227 +SOT-227 / SOT-227B / ISOTOP, M4 mounting screws (https://www.vishay.com/docs/95423/sot227g2.pdf, https://www.vishay.com/docs/95793/vs-fc420sa10.pdf) +sot 227 isotop +0 +8 +4 +Package_TO_SOT_THT +TO-3 +Transistor TO-3 +TR TO-3 TO3 TO-204 +0 +4 +3 +Package_TO_SOT_THT +TO-3P-3_Horizontal_TabDown +TO-3P-3, Horizontal, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html +TO-3P-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-3P-3_Horizontal_TabUp +TO-3P-3, Horizontal, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html +TO-3P-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-3P-3_Vertical +TO-3P-3, Vertical, RM 5.45mm, , see https://toshiba.semicon-storage.com/ap-en/design-support/package/detail.TO-3P(N).html +TO-3P-3 Vertical RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-3PB-3_Horizontal_TabDown +TO-3PB-3, Horizontal, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF +TO-3PB-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-3PB-3_Horizontal_TabUp +TO-3PB-3, Horizontal, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF +TO-3PB-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-3PB-3_Vertical +TO-3PB-3, Vertical, RM 5.45mm, , see http://www.onsemi.com/pub/Collateral/340AC.PDF +TO-3PB-3 Vertical RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-5-2 +TO-5-2 +TO-5-2 +0 +2 +2 +Package_TO_SOT_THT +TO-5-2_Window +TO-5-2_Window, Window +TO-5-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-5-3 +TO-5-3 +TO-5-3 +0 +3 +3 +Package_TO_SOT_THT +TO-5-3_Window +TO-5-3_Window, Window +TO-5-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-5-4 +TO-5-4 +TO-5-4 +0 +4 +4 +Package_TO_SOT_THT +TO-5-4_Window +TO-5-4_Window, Window +TO-5-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-5-6 +TO-5-6 +TO-5-6 +0 +6 +6 +Package_TO_SOT_THT +TO-5-6_Window +TO-5-6_Window, Window +TO-5-6_Window Window +0 +6 +6 +Package_TO_SOT_THT +TO-5-8 +TO-5-8 +TO-5-8 +0 +8 +8 +Package_TO_SOT_THT +TO-5-8_PD5.08 +TO-5-8_PD5.08 +TO-5-8_PD5.08 +0 +8 +8 +Package_TO_SOT_THT +TO-5-8_PD5.08_Window +TO-5-8_PD5.08_Window, Window +TO-5-8_PD5.08_Window Window +0 +8 +8 +Package_TO_SOT_THT +TO-5-8_Window +TO-5-8_Window, Window +TO-5-8_Window Window +0 +8 +8 +Package_TO_SOT_THT +TO-5-10 +TO-5-10 +TO-5-10 +0 +10 +10 +Package_TO_SOT_THT +TO-5-10_Window +TO-5-10_Window, Window +TO-5-10_Window Window +0 +10 +10 +Package_TO_SOT_THT +TO-8-2 +TO-8-2 +TO-8-2 +0 +2 +2 +Package_TO_SOT_THT +TO-8-2_Window +TO-8-2_Window, Window +TO-8-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-8-3 +TO-8-3 +TO-8-3 +0 +3 +3 +Package_TO_SOT_THT +TO-8-3_Window +TO-8-3_Window, Window +TO-8-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-11-2 +TO-11-2 +TO-11-2 +0 +2 +2 +Package_TO_SOT_THT +TO-11-2_Window +TO-11-2_Window, Window +TO-11-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-11-3 +TO-11-3 +TO-11-3 +0 +3 +3 +Package_TO_SOT_THT +TO-11-3_Window +TO-11-3_Window, Window +TO-11-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-12-4 +TO-12-4 +TO-12-4 +0 +4 +4 +Package_TO_SOT_THT +TO-12-4_Window +TO-12-4_Window, Window +TO-12-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-17-4 +TO-17-4 +TO-17-4 +0 +4 +4 +Package_TO_SOT_THT +TO-17-4_Window +TO-17-4_Window, Window +TO-17-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-18-2 +TO-18-2 +TO-18-2 +0 +2 +2 +Package_TO_SOT_THT +TO-18-2_Lens +TO-18-2_Lens, Lens +TO-18-2_Lens Lens +0 +2 +2 +Package_TO_SOT_THT +TO-18-2_Window +TO-18-2_Window, Window +TO-18-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-18-3 +TO-18-3 +TO-18-3 +0 +3 +3 +Package_TO_SOT_THT +TO-18-3_Lens +TO-18-3_Lens, Lens +TO-18-3_Lens Lens +0 +3 +3 +Package_TO_SOT_THT +TO-18-3_Window +TO-18-3_Window, Window +TO-18-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-18-4 +TO-18-4 +TO-18-4 +0 +4 +4 +Package_TO_SOT_THT +TO-18-4_Lens +TO-18-4_Lens, Lens +TO-18-4_Lens Lens +0 +4 +4 +Package_TO_SOT_THT +TO-18-4_Window +TO-18-4_Window, Window +TO-18-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-33-4 +TO-33-4 +TO-33-4 +0 +4 +4 +Package_TO_SOT_THT +TO-33-4_Window +TO-33-4_Window, Window +TO-33-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-38-2 +TO-38-2 +TO-38-2 +0 +2 +2 +Package_TO_SOT_THT +TO-38-2_Window +TO-38-2_Window, Window +TO-38-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-38-3 +TO-38-3 +TO-38-3 +0 +3 +3 +Package_TO_SOT_THT +TO-38-3_Window +TO-38-3_Window, Window +TO-38-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-39-2 +TO-39-2 +TO-39-2 +0 +2 +2 +Package_TO_SOT_THT +TO-39-2_Window +TO-39-2_Window, Window +TO-39-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-39-3 +TO-39-3 +TO-39-3 +0 +3 +3 +Package_TO_SOT_THT +TO-39-3_Window +TO-39-3_Window, Window +TO-39-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-39-4 +TO-39-4 +TO-39-4 +0 +4 +4 +Package_TO_SOT_THT +TO-39-4_Window +TO-39-4_Window, Window +TO-39-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-39-6 +TO-39-6 +TO-39-6 +0 +6 +6 +Package_TO_SOT_THT +TO-39-6_Window +TO-39-6_Window, Window +TO-39-6_Window Window +0 +6 +6 +Package_TO_SOT_THT +TO-39-8 +TO-39-8 +TO-39-8 +0 +8 +8 +Package_TO_SOT_THT +TO-39-8_Window +TO-39-8_Window, Window +TO-39-8_Window Window +0 +8 +8 +Package_TO_SOT_THT +TO-39-10 +TO-39-10 +TO-39-10 +0 +10 +10 +Package_TO_SOT_THT +TO-39-10_Window +TO-39-10_Window, Window +TO-39-10_Window Window +0 +10 +10 +Package_TO_SOT_THT +TO-46-2 +TO-46-2 +TO-46-2 +0 +2 +2 +Package_TO_SOT_THT +TO-46-2_Pin2Center +TO-46-2, Pin2 at center of package, Thorlabs photodiodes +TO-46-2 Thorlabs +0 +2 +2 +Package_TO_SOT_THT +TO-46-2_Pin2Center_Window +TO-46-2, Pin2 at center of package, Thorlabs photodiodes +TO-46-2 Thorlabs +0 +2 +2 +Package_TO_SOT_THT +TO-46-2_Window +TO-46-2_Window, Window +TO-46-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-46-3 +TO-46-3 +TO-46-3 +0 +3 +3 +Package_TO_SOT_THT +TO-46-3_Pin2Center +TO-46-3, Pin2 at center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf +TO-46-3 Thorlabs +0 +3 +3 +Package_TO_SOT_THT +TO-46-3_Pin2Center_Window +TO-46-3, Pin2 at center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf +TO-46-3 Thorlabs +0 +3 +3 +Package_TO_SOT_THT +TO-46-3_Window +TO-46-3_Window, Window +TO-46-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-46-4 +TO-46-4 +TO-46-4 +0 +4 +4 +Package_TO_SOT_THT +TO-46-4_Window +TO-46-4_Window, Window +TO-46-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-52-2 +TO-52-2 +TO-52-2 +0 +2 +2 +Package_TO_SOT_THT +TO-52-2_Window +TO-52-2_Window, Window +TO-52-2_Window Window +0 +2 +2 +Package_TO_SOT_THT +TO-52-3 +TO-52-3 +TO-52-3 +0 +3 +3 +Package_TO_SOT_THT +TO-52-3_Window +TO-52-3_Window, Window +TO-52-3_Window Window +0 +3 +3 +Package_TO_SOT_THT +TO-72-4 +TO-72-4 +TO-72-4 +0 +4 +4 +Package_TO_SOT_THT +TO-72-4_Window +TO-72-4_Window, Window +TO-72-4_Window Window +0 +4 +4 +Package_TO_SOT_THT +TO-75-6 +TO-75-6 +TO-75-6 +0 +6 +6 +Package_TO_SOT_THT +TO-75-6_Window +TO-75-6_Window, Window +TO-75-6_Window Window +0 +6 +6 +Package_TO_SOT_THT +TO-78-6 +TO-78-6 +TO-78-6 +0 +6 +6 +Package_TO_SOT_THT +TO-78-6_Window +TO-78-6_Window, Window +TO-78-6_Window Window +0 +6 +6 +Package_TO_SOT_THT +TO-78-8 +TO-78-8 +TO-78-8 +0 +8 +8 +Package_TO_SOT_THT +TO-78-8_Window +TO-78-8_Window, Window +TO-78-8_Window Window +0 +8 +8 +Package_TO_SOT_THT +TO-78-10 +TO-78-10 +TO-78-10 +0 +10 +10 +Package_TO_SOT_THT +TO-78-10_Window +TO-78-10_Window, Window +TO-78-10_Window Window +0 +10 +10 +Package_TO_SOT_THT +TO-92 +TO-92 leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92-2 +TO-92 2-pin leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 diode SOD70 +0 +2 +2 +Package_TO_SOT_THT +TO-92-2_Horizontal1 +2-pin TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 temperature sensor diode +0 +2 +2 +Package_TO_SOT_THT +TO-92-2_Horizontal2 +2-pin TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 temperature sensor diode +0 +2 +2 +Package_TO_SOT_THT +TO-92-2_W4.0mm_Horizontal_FlatSideDown +TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +2 +2 +Package_TO_SOT_THT +TO-92-2_W4.0mm_Horizontal_FlatSideUp +TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +2 +2 +Package_TO_SOT_THT +TO-92-2_Wide +TO-92 2-pin leads in-line, wide, drill 0.75mm +to-92 sc-43 sc-43a sot54 PA33 diode SOD70 +0 +2 +2 +Package_TO_SOT_THT +TO-92Flat +TO-92Flat package, often used for hall sensors, drill 0.75mm (see e.g. http://www.ti.com/lit/ds/symlink/drv5023.pdf) +to-92Flat hall sensor +0 +3 +3 +Package_TO_SOT_THT +TO-92L +TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) +TO-92L Molded Narrow transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92L_HandSolder +TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm, hand-soldering variant with enlarged pads (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92L_Inline +TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) +TO-92L Inline Wide transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92L_Inline_Wide +TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) +TO-92L Inline Wide transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92L_Wide +TO-92L leads in-line (large body variant of TO-92), also known as TO-226, wide, drill 0.75mm (see https://www.diodes.com/assets/Package-Files/TO92L.pdf and http://www.ti.com/lit/an/snoa059/snoa059.pdf) +TO-92L Molded Wide transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92Mini-2 +TO-92Mini package, drill 0.6mm (https://media.digikey.com/pdf/Data%20Sheets/Infineon%20PDFs/KT,KTY.pdf) +to-92Mini transistor +0 +2 +2 +Package_TO_SOT_THT +TO-92S +TO-92S package, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf) +to-92S transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92S-2 +TO-92S package, 2-pin, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf) +to-92S transistor +0 +2 +2 +Package_TO_SOT_THT +TO-92S_Wide +TO-92S_Wide package, drill 0.75mm (https://www.diodes.com/assets/Package-Files/TO92S%20(Type%20B).pdf) +TO-92S_Wide transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_HandSolder +TO-92 leads molded, narrow, drill 0.75mm, handsoldering variant with enlarged pads (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Horizontal1 +TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Horizontal2 +TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Inline +TO-92 leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Inline_Horizontal1 +TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Inline_Horizontal2 +TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Inline_W4.0mm_Horizontal_FlatSideDown +TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Inline_W4.0mm_Horizontal_FlatSideUp +TO-92 horizontal, leads in-line, narrow, oval pads, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Inline_Wide +TO-92 leads in-line, wide, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_W4.0mm_StaggerEven_Horizontal_FlatSideDown +TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_W4.0mm_StaggerEven_Horizontal_FlatSideUp +TO-92 horizontal, leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-92_Wide +TO-92 leads molded, wide, drill 0.75mm (see NXP sot054_po.pdf) +to-92 sc-43 sc-43a sot54 PA33 transistor +0 +3 +3 +Package_TO_SOT_THT +TO-99-6 +TO-99-6 +TO-99-6 +0 +6 +6 +Package_TO_SOT_THT +TO-99-6_Window +TO-99-6_Window, Window +TO-99-6_Window Window +0 +6 +6 +Package_TO_SOT_THT +TO-99-8 +TO-99-8 +TO-99-8 +0 +8 +8 +Package_TO_SOT_THT +TO-99-8_Window +TO-99-8_Window, Window +TO-99-8_Window Window +0 +8 +8 +Package_TO_SOT_THT +TO-100-10 +TO-100-10 +TO-100-10 +0 +10 +10 +Package_TO_SOT_THT +TO-100-10_Window +TO-100-10_Window, Window +TO-100-10_Window Window +0 +10 +10 +Package_TO_SOT_THT +TO-126-2_Horizontal_TabDown +TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf +TO-126-2 Horizontal RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-126-2_Horizontal_TabUp +TO-126-2, Horizontal, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf +TO-126-2 Horizontal RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-126-2_Vertical +TO-126-2, Vertical, RM 5.08mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf +TO-126-2 Vertical RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-126-3_Horizontal_TabDown +TO-126-3, Horizontal, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf +TO-126-3 Horizontal RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-126-3_Horizontal_TabUp +TO-126-3, Horizontal, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf +TO-126-3 Horizontal RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-126-3_Vertical +TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf +TO-126-3 Vertical RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-218-2_Horizontal_TabDown +TO-218-2, Horizontal, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf +TO-218-2 Horizontal RM 10.95mm SOT-93 +0 +2 +2 +Package_TO_SOT_THT +TO-218-2_Horizontal_TabUp +TO-218-2, Horizontal, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf +TO-218-2 Horizontal RM 10.95mm SOT-93 +0 +2 +2 +Package_TO_SOT_THT +TO-218-2_Vertical +TO-218-2, Vertical, RM 10.95mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf +TO-218-2 Vertical RM 10.95mm SOT-93 +0 +2 +2 +Package_TO_SOT_THT +TO-218-3_Horizontal_TabDown +TO-218-3, Horizontal, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf +TO-218-3 Horizontal RM 5.475mm SOT-93 +0 +3 +3 +Package_TO_SOT_THT +TO-218-3_Horizontal_TabUp +TO-218-3, Horizontal, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf +TO-218-3 Horizontal RM 5.475mm SOT-93 +0 +3 +3 +Package_TO_SOT_THT +TO-218-3_Vertical +TO-218-3, Vertical, RM 5.475mm, SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf +TO-218-3 Vertical RM 5.475mm SOT-93 +0 +3 +3 +Package_TO_SOT_THT +TO-220-2_Horizontal_TabDown +TO-220-2, Horizontal, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF +TO-220-2 Horizontal RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-220-2_Horizontal_TabUp +TO-220-2, Horizontal, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF +TO-220-2 Horizontal RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-220-2_Vertical +TO-220-2, Vertical, RM 5.08mm, see https://www.centralsemi.com/PDFS/CASE/TO-220-2PD.PDF +TO-220-2 Vertical RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-220-3_Horizontal_TabDown +TO-220-3, Horizontal, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf +TO-220-3 Horizontal RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-220-3_Horizontal_TabUp +TO-220-3, Horizontal, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf +TO-220-3 Horizontal RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-220-3_Vertical +TO-220-3, Vertical, RM 2.54mm, see https://www.vishay.com/docs/66542/to-220-1.pdf +TO-220-3 Vertical RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-220-4_Horizontal_TabDown +TO-220-4, Horizontal, RM 2.54mm +TO-220-4 Horizontal RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-220-4_Horizontal_TabUp +TO-220-4, Horizontal, RM 2.54mm +TO-220-4 Horizontal RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-220-4_P5.08x2.54mm_StaggerEven_Lead3.8mm_Vertical +TO-220-4, Vertical, RM 2.54mm, staggered type-2 +TO-220-4 Vertical RM 2.54mm staggered type-2 +0 +4 +4 +Package_TO_SOT_THT +TO-220-4_P5.08x2.54mm_StaggerEven_Lead5.84mm_TabDown +TO-220-4, Horizontal, RM 2.54mm, staggered type-2 +TO-220-4 Horizontal RM 2.54mm staggered type-2 +0 +4 +4 +Package_TO_SOT_THT +TO-220-4_P5.08x2.54mm_StaggerOdd_Lead3.8mm_Vertical +TO-220-4, Vertical, RM 2.54mm, staggered type-1 +TO-220-4 Vertical RM 2.54mm staggered type-1 +0 +4 +4 +Package_TO_SOT_THT +TO-220-4_P5.08x2.54mm_StaggerOdd_Lead5.84mm_TabDown +TO-220-4, Horizontal, RM 2.54mm, staggered type-1 +TO-220-4 Horizontal RM 2.54mm staggered type-1 +0 +4 +4 +Package_TO_SOT_THT +TO-220-4_Vertical +TO-220-4, Vertical, RM 2.54mm +TO-220-4 Vertical RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-220-5_Horizontal_TabDown +TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf +TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 +0 +5 +5 +Package_TO_SOT_THT +TO-220-5_Horizontal_TabUp +TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf +TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 +0 +5 +5 +Package_TO_SOT_THT +TO-220-5_P3.4x3.7mm_StaggerEven_Lead3.8mm_Vertical +TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-2, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf +TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 staggered type-2 +0 +5 +5 +Package_TO_SOT_THT +TO-220-5_P3.4x3.7mm_StaggerOdd_Lead3.8mm_Vertical +TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-1, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf +TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 staggered type-1 +0 +5 +5 +Package_TO_SOT_THT +TO-220-5_P3.4x3.8mm_StaggerEven_Lead7.13mm_TabDown +TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-2, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf +TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered type-2 +0 +5 +5 +Package_TO_SOT_THT +TO-220-5_P3.4x3.8mm_StaggerOdd_Lead7.13mm_TabDown +TO-220-5, Horizontal, RM 1.7mm, Pentawatt, Multiwatt-5, staggered type-1, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421.pdf?domain=www.linear.com, https://www.diodes.com/assets/Package-Files/TO220-5.pdf +TO-220-5 Horizontal RM 1.7mm Pentawatt Multiwatt-5 staggered type-1 +0 +5 +5 +Package_TO_SOT_THT +TO-220-5_Vertical +TO-220-5, Vertical, RM 1.7mm, Pentawatt, Multiwatt-5, see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-to-220/to-220_5_05-08-1421_straight_lead.pdf +TO-220-5 Vertical RM 1.7mm Pentawatt Multiwatt-5 +0 +5 +5 +Package_TO_SOT_THT +TO-220-7_P2.54x3.7mm_StaggerEven_Lead3.8mm_Vertical +TO-220-7, Vertical, RM 1.27mm, Multiwatt-7, staggered type-2 +TO-220-7 Vertical RM 1.27mm Multiwatt-7 staggered type-2 +0 +7 +7 +Package_TO_SOT_THT +TO-220-7_P2.54x3.7mm_StaggerOdd_Lead3.8mm_Vertical +TO-220-7, Vertical, RM 1.27mm, Multiwatt-7, staggered type-1 +TO-220-7 Vertical RM 1.27mm Multiwatt-7 staggered type-1 +0 +7 +7 +Package_TO_SOT_THT +TO-220-7_P2.54x3.8mm_StaggerEven_Lead5.85mm_TabDown +TO-220-7, Horizontal, RM 1.27mm, Multiwatt-7, staggered type-2 +TO-220-7 Horizontal RM 1.27mm Multiwatt-7 staggered type-2 +0 +7 +7 +Package_TO_SOT_THT +TO-220-7_P2.54x3.8mm_StaggerOdd_Lead5.85mm_TabDown +TO-220-7, Horizontal, RM 1.27mm, Multiwatt-7, staggered type-1 +TO-220-7 Horizontal RM 1.27mm Multiwatt-7 staggered type-1 +0 +7 +7 +Package_TO_SOT_THT +TO-220-8_Vertical +TO-220-8 (Multiwatt8), Vertical, 2.54mm Pitch (http://www.st.com/resource/en/datasheet/tda7264.pdf) +TO-220-9 Vertical 2.54mm Pitch Multiwatt 8 +0 +8 +8 +Package_TO_SOT_THT +TO-220-9_P1.94x3.7mm_StaggerEven_Lead3.8mm_Vertical +TO-220-9, Vertical, RM 0.97mm, Multiwatt-9, staggered type-2 +TO-220-9 Vertical RM 0.97mm Multiwatt-9 staggered type-2 +0 +9 +9 +Package_TO_SOT_THT +TO-220-9_P1.94x3.7mm_StaggerOdd_Lead3.8mm_Vertical +TO-220-9, Vertical, RM 0.97mm, Multiwatt-9, staggered type-1 +TO-220-9 Vertical RM 0.97mm Multiwatt-9 staggered type-1 +0 +9 +9 +Package_TO_SOT_THT +TO-220-9_P1.94x3.8mm_StaggerEven_Lead5.85mm_TabDown +TO-220-9, Horizontal, RM 0.97mm, Multiwatt-9, staggered type-2 +TO-220-9 Horizontal RM 0.97mm Multiwatt-9 staggered type-2 +0 +9 +9 +Package_TO_SOT_THT +TO-220-9_P1.94x3.8mm_StaggerOdd_Lead5.85mm_TabDown +TO-220-9, Horizontal, RM 0.97mm, Multiwatt-9, staggered type-1 +TO-220-9 Horizontal RM 0.97mm Multiwatt-9 staggered type-1 +0 +9 +9 +Package_TO_SOT_THT +TO-220-11_P3.4x2.54mm_StaggerEven_Lead5.84mm_TabDown +TO-220-11, Horizontal, RM 1.7mm, staggered type-2, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf +TO-220-11 Horizontal RM 1.7mm staggered type-2 +0 +11 +11 +Package_TO_SOT_THT +TO-220-11_P3.4x2.54mm_StaggerOdd_Lead5.84mm_TabDown +TO-220-11, Horizontal, RM 1.7mm, staggered type-1, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf +TO-220-11 Horizontal RM 1.7mm staggered type-1 +0 +11 +11 +Package_TO_SOT_THT +TO-220-11_P3.4x5.08mm_StaggerEven_Lead4.58mm_Vertical +TO-220-11, Vertical, RM 1.7mm, staggered type-2, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf +TO-220-11 Vertical RM 1.7mm staggered type-2 +0 +11 +11 +Package_TO_SOT_THT +TO-220-11_P3.4x5.08mm_StaggerOdd_Lead4.85mm_Vertical +TO-220-11, Vertical, RM 1.7mm, staggered type-1, see http://www.st.com/resource/en/datasheet/tda7391lv.pdf +TO-220-11 Vertical RM 1.7mm staggered type-1 +0 +11 +11 +Package_TO_SOT_THT +TO-220-11_P3.4x5.08mm_StaggerOdd_Lead8.45mm_TabDown +TO-220-11, Horizontal, RM 1.7mm, staggered type-1, see http://www.ti.com/lit/ds/symlink/lmd18200.pdf +TO-220-11 Horizontal RM 1.7mm staggered type-1 +0 +11 +11 +Package_TO_SOT_THT +TO-220-15_P2.54x2.54mm_StaggerEven_Lead4.58mm_Vertical +TO-220-15, Vertical, RM 1.27mm, staggered type-2, see http://www.st.com/resource/en/datasheet/l298.pdf +TO-220-15 Vertical RM 1.27mm staggered type-2 +0 +15 +15 +Package_TO_SOT_THT +TO-220-15_P2.54x2.54mm_StaggerEven_Lead5.84mm_TabDown +TO-220-15, Horizontal, RM 1.27mm, staggered type-2, see http://www.st.com/resource/en/datasheet/l298.pdf +TO-220-15 Horizontal RM 1.27mm staggered type-2 +0 +15 +15 +Package_TO_SOT_THT +TO-220-15_P2.54x2.54mm_StaggerOdd_Lead4.58mm_Vertical +TO-220-15, Vertical, RM 1.27mm, staggered type-1, see http://www.st.com/resource/en/datasheet/l298.pdf +TO-220-15 Vertical RM 1.27mm staggered type-1 +0 +15 +15 +Package_TO_SOT_THT +TO-220-15_P2.54x2.54mm_StaggerOdd_Lead5.84mm_TabDown +TO-220-15, Horizontal, RM 1.27mm, staggered type-1, see http://www.st.com/resource/en/datasheet/l298.pdf +TO-220-15 Horizontal RM 1.27mm staggered type-1 +0 +15 +15 +Package_TO_SOT_THT +TO-220F-2_Horizontal_TabDown +TO-220F-2, Horizontal, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf +TO-220F-2 Horizontal RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-220F-2_Horizontal_TabUp +TO-220F-2, Horizontal, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf +TO-220F-2 Horizontal RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-220F-2_Vertical +TO-220F-2, Vertical, RM 5.08mm, see http://www.onsemi.com/pub/Collateral/FFPF10F150S-D.pdf +TO-220F-2 Vertical RM 5.08mm +0 +2 +2 +Package_TO_SOT_THT +TO-220F-3_Horizontal_TabDown +TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf +TO-220F-3 Horizontal RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-220F-3_Horizontal_TabUp +TO-220F-3, Horizontal, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf +TO-220F-3 Horizontal RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-220F-3_Vertical +TO-220F-3, Vertical, RM 2.54mm, see http://www.st.com/resource/en/datasheet/stp20nm60.pdf +TO-220F-3 Vertical RM 2.54mm +0 +3 +3 +Package_TO_SOT_THT +TO-220F-4_Horizontal_TabDown +TO-220F-4, Horizontal, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Horizontal RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-220F-4_Horizontal_TabUp +TO-220F-4, Horizontal, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Horizontal RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-220F-4_P5.08x2.05mm_StaggerEven_Lead1.85mm_Vertical +TO-220F-4, Vertical, RM 2.54mm, staggered type-2, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Vertical RM 2.54mm staggered type-2 +0 +4 +4 +Package_TO_SOT_THT +TO-220F-4_P5.08x2.05mm_StaggerOdd_Lead1.85mm_Vertical +TO-220F-4, Vertical, RM 2.54mm, staggered type-1, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Vertical RM 2.54mm staggered type-1 +0 +4 +4 +Package_TO_SOT_THT +TO-220F-4_P5.08x3.7mm_StaggerEven_Lead3.5mm_Vertical +TO-220F-4, Vertical, RM 2.54mm, staggered type-2, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Vertical RM 2.54mm staggered type-2 +0 +4 +4 +Package_TO_SOT_THT +TO-220F-4_P5.08x3.7mm_StaggerOdd_Lead3.5mm_Vertical +TO-220F-4, Vertical, RM 2.54mm, staggered type-1, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Vertical RM 2.54mm staggered type-1 +0 +4 +4 +Package_TO_SOT_THT +TO-220F-4_Vertical +TO-220F-4, Vertical, RM 2.54mm, see https://www.njr.com/semicon/PDF/package/TO-220F-4_E.pdf +TO-220F-4 Vertical RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-220F-5_Horizontal_TabDown +TO-220F-5, Horizontal, RM 1.7mm, PentawattF-, MultiwattF-5 +TO-220F-5 Horizontal RM 1.7mm PentawattF- MultiwattF-5 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-5_Horizontal_TabUp +TO-220F-5, Horizontal, RM 1.7mm, PentawattF-, MultiwattF-5 +TO-220F-5 Horizontal RM 1.7mm PentawattF- MultiwattF-5 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-5_P3.4x2.06mm_StaggerEven_Lead1.86mm_Vertical +TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-2 +TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-2 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-5_P3.4x2.06mm_StaggerOdd_Lead1.86mm_Vertical +TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-1 +TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-1 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-5_P3.4x3.7mm_StaggerEven_Lead3.5mm_Vertical +TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-2 +TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-2 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-5_P3.4x3.7mm_StaggerOdd_Lead3.5mm_Vertical +TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5, staggered type-1 +TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 staggered type-1 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-5_Vertical +TO-220F-5, Vertical, RM 1.7mm, PentawattF-, MultiwattF-5 +TO-220F-5 Vertical RM 1.7mm PentawattF- MultiwattF-5 +0 +5 +5 +Package_TO_SOT_THT +TO-220F-7_P2.54x3.7mm_StaggerEven_Lead3.5mm_Vertical +TO-220F-7, Vertical, RM 1.27mm, staggered type-2 +TO-220F-7 Vertical RM 1.27mm staggered type-2 +0 +7 +7 +Package_TO_SOT_THT +TO-220F-7_P2.54x3.7mm_StaggerOdd_Lead3.5mm_Vertical +TO-220F-7, Vertical, RM 1.27mm, staggered type-1 +TO-220F-7 Vertical RM 1.27mm staggered type-1 +0 +7 +7 +Package_TO_SOT_THT +TO-220F-9_P1.8x3.7mm_StaggerEven_Lead3.5mm_Vertical +TO-220F-9, Vertical, RM 0.9mm, staggered type-2 +TO-220F-9 Vertical RM 0.9mm staggered type-2 +0 +9 +9 +Package_TO_SOT_THT +TO-220F-9_P1.8x3.7mm_StaggerOdd_Lead3.5mm_Vertical +TO-220F-9, Vertical, RM 0.9mm, staggered type-1 +TO-220F-9 Vertical RM 0.9mm staggered type-1 +0 +9 +9 +Package_TO_SOT_THT +TO-220F-11_P3.4x5.08mm_StaggerEven_Lead5.08mm_Vertical +TO-220F-11, Vertical, RM 1.7mm, MultiwattF-11, staggered type-2, see http://www.ti.com/lit/ds/symlink/lm3886.pdf +TO-220F-11 Vertical RM 1.7mm MultiwattF-11 staggered type-2 +0 +11 +11 +Package_TO_SOT_THT +TO-220F-11_P3.4x5.08mm_StaggerOdd_Lead5.08mm_Vertical +TO-220F-11, Vertical, RM 1.7mm, MultiwattF-11, staggered type-1, see http://www.ti.com/lit/ds/symlink/lm3886.pdf +TO-220F-11 Vertical RM 1.7mm MultiwattF-11 staggered type-1 +0 +11 +11 +Package_TO_SOT_THT +TO-220F-15_P2.54x5.08mm_StaggerEven_Lead5.08mm_Vertical +TO-220F-15, Vertical, RM 1.27mm, MultiwattF-15, staggered type-2 +TO-220F-15 Vertical RM 1.27mm MultiwattF-15 staggered type-2 +0 +15 +15 +Package_TO_SOT_THT +TO-220F-15_P2.54x5.08mm_StaggerOdd_Lead5.08mm_Vertical +TO-220F-15, Vertical, RM 1.27mm, MultiwattF-15, staggered type-1 +TO-220F-15 Vertical RM 1.27mm MultiwattF-15 staggered type-1 +0 +15 +15 +Package_TO_SOT_THT +TO-247-2_Horizontal_TabDown +TO-247-2, Horizontal, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-2 Horizontal RM 10.9mm +0 +2 +2 +Package_TO_SOT_THT +TO-247-2_Horizontal_TabUp +TO-247-2, Horizontal, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-2 Horizontal RM 10.9mm +0 +2 +2 +Package_TO_SOT_THT +TO-247-2_Vertical +TO-247-2, Vertical, RM 10.9mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-2 Vertical RM 10.9mm +0 +2 +2 +Package_TO_SOT_THT +TO-247-3_Horizontal_TabDown +TO-247-3, Horizontal, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-247-3_Horizontal_TabUp +TO-247-3, Horizontal, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-247-3_Vertical +TO-247-3, Vertical, RM 5.45mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-3 Vertical RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-247-4_Horizontal_TabDown +TO-247-4, Horizontal, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-4 Horizontal RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-247-4_Horizontal_TabUp +TO-247-4, Horizontal, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-4 Horizontal RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-247-4_Vertical +TO-247-4, Vertical, RM 2.54mm, see https://toshiba.semicon-storage.com/us/product/mosfet/to-247-4l.html +TO-247-4 Vertical RM 2.54mm +0 +4 +4 +Package_TO_SOT_THT +TO-247-5_Horizontal_TabDown +TO-247-5, Horizontal, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf +TO-247-5 Horizontal RM 2.54mm +0 +5 +5 +Package_TO_SOT_THT +TO-247-5_Horizontal_TabUp +TO-247-5, Horizontal, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf +TO-247-5 Horizontal RM 2.54mm +0 +5 +5 +Package_TO_SOT_THT +TO-247-5_Vertical +TO-247-5, Vertical, RM 2.54mm, see http://ww1.microchip.com/downloads/en/DeviceDoc/20005685A.pdf +TO-247-5 Vertical RM 2.54mm +0 +5 +5 +Package_TO_SOT_THT +TO-251-2-1EP_Horizontal_TabDown +TO-251-2, Horizontal, RM 4.58mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf +TO-251-2 Horizontal RM 4.58mm IPAK +0 +3 +3 +Package_TO_SOT_THT +TO-251-2_Vertical +TO-251-2, Vertical, RM 4.58mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf +TO-251-2 Vertical RM 4.58mm IPAK +0 +2 +2 +Package_TO_SOT_THT +TO-251-3-1EP_Horizontal_TabDown +TO-251-3, Horizontal, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf +TO-251-3 Horizontal RM 2.29mm IPAK +0 +4 +4 +Package_TO_SOT_THT +TO-251-3_Vertical +TO-251-3, Vertical, RM 2.29mm, IPAK, see https://www.diodes.com/assets/Package-Files/TO251.pdf +TO-251-3 Vertical RM 2.29mm IPAK +0 +3 +3 +Package_TO_SOT_THT +TO-262-3-1EP_Horizontal_TabDown +TO-262-3, Horizontal, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF +TO-262-3 Horizontal RM 2.54mm IIPAK I2PAK +0 +4 +4 +Package_TO_SOT_THT +TO-262-3_Vertical +TO-262-3, Vertical, RM 2.54mm, IIPAK, I2PAK, see http://www.onsemi.com/pub/Collateral/EN8586-D.PDF +TO-262-3 Vertical RM 2.54mm IIPAK I2PAK +0 +3 +3 +Package_TO_SOT_THT +TO-262-5-1EP_Horizontal_TabDown +TO-262-5, Horizontal, RM 1.7mm, IIPAK, I2PAK, see http://pdf.datasheetcatalog.com/datasheet/irf/iris4011.pdf +TO-262-5 Horizontal RM 1.7mm IIPAK I2PAK +0 +6 +6 +Package_TO_SOT_THT +TO-262-5_Vertical +TO-262-5, Vertical, RM 1.7mm, IIPAK, I2PAK, see http://pdf.datasheetcatalog.com/datasheet/irf/iris4011.pdf +TO-262-5 Vertical RM 1.7mm IIPAK I2PAK +0 +5 +5 +Package_TO_SOT_THT +TO-264-2_Horizontal_TabDown +TO-264-2, Horizontal, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf +TO-264-2 Horizontal RM 10.9mm +0 +2 +2 +Package_TO_SOT_THT +TO-264-2_Horizontal_TabUp +TO-264-2, Horizontal, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf +TO-264-2 Horizontal RM 10.9mm +0 +2 +2 +Package_TO_SOT_THT +TO-264-2_Vertical +TO-264-2, Vertical, RM 10.9mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf +TO-264-2 Vertical RM 10.9mm +0 +2 +2 +Package_TO_SOT_THT +TO-264-3_Horizontal_TabDown +TO-264-3, Horizontal, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf +TO-264-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-264-3_Horizontal_TabUp +TO-264-3, Horizontal, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf +TO-264-3 Horizontal RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-264-3_Vertical +TO-264-3, Vertical, RM 5.45mm, see https://www.fairchildsemi.com/package-drawings/TO/TO264A03.pdf +TO-264-3 Vertical RM 5.45mm +0 +3 +3 +Package_TO_SOT_THT +TO-264-5_Horizontal_TabDown +TO-264-5, Horizontal, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF +TO-264-5 Horizontal RM 3.81mm +0 +5 +5 +Package_TO_SOT_THT +TO-264-5_Horizontal_TabUp +TO-264-5, Horizontal, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF +TO-264-5 Horizontal RM 3.81mm +0 +5 +5 +Package_TO_SOT_THT +TO-264-5_Vertical +TO-264-5, Vertical, RM 3.81mm, see https://www.onsemi.com/pub/Collateral/NJL3281D-D.PDF +TO-264-5 Vertical RM 3.81mm +0 +5 +5 +Potentiometer_SMD +Potentiometer_ACP_CA6-VSMD_Vertical +Potentiometer, vertical, ACP CA6-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf +Potentiometer vertical ACP CA6-VSMD +0 +3 +3 +Potentiometer_SMD +Potentiometer_ACP_CA6-VSMD_Vertical_Hole +Potentiometer, vertical, shaft hole, ACP CA6-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf +Potentiometer vertical hole ACP CA6-VSMD +0 +3 +3 +Potentiometer_SMD +Potentiometer_ACP_CA9-VSMD_Vertical +Potentiometer, vertical, ACP CA9-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer vertical ACP CA9-VSMD +0 +3 +3 +Potentiometer_SMD +Potentiometer_ACP_CA9-VSMD_Vertical_Hole +Potentiometer, vertical, shaft hole, ACP CA9-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer vertical hole ACP CA9-VSMD +0 +3 +3 +Potentiometer_SMD +Potentiometer_ACP_CA14-VSMD_Vertical +Potentiometer, vertical, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer vertical ACP CA14-VSMD +0 +3 +3 +Potentiometer_SMD +Potentiometer_ACP_CA14-VSMD_Vertical_Hole +Potentiometer, vertical, shaft hole, ACP CA14-VSMD, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer vertical hole ACP CA14-VSMD +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3214G_Horizontal +Potentiometer, horizontal, Bourns 3214G, https://www.bourns.com/docs/Product-Datasheets/3214.pdf +Potentiometer horizontal Bourns 3214G +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3214J_Horizontal +Potentiometer, horizontal, Bourns 3214J, https://www.bourns.com/docs/Product-Datasheets/3214.pdf +Potentiometer horizontal Bourns 3214J +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3214W_Vertical +Potentiometer, vertical, Bourns 3214W, https://www.bourns.com/docs/Product-Datasheets/3214.pdf +Potentiometer vertical Bourns 3214W +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3214X_Vertical +Potentiometer, vertical, Bourns 3214X, https://www.bourns.com/docs/Product-Datasheets/3214.pdf +Potentiometer vertical Bourns 3214X +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3224G_Horizontal +Potentiometer, horizontal, Bourns 3224G, https://www.bourns.com/docs/Product-Datasheets/3224.pdf +Potentiometer horizontal Bourns 3224G +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3224J_Horizontal +Potentiometer, horizontal, Bourns 3224J, https://www.bourns.com/docs/Product-Datasheets/3224.pdf +Potentiometer horizontal Bourns 3224J +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3224W_Vertical +Potentiometer, vertical, Bourns 3224W, https://www.bourns.com/docs/Product-Datasheets/3224.pdf +Potentiometer vertical Bourns 3224W +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3224X_Vertical +Potentiometer, vertical, Bourns 3224X, https://www.bourns.com/docs/Product-Datasheets/3224.pdf +Potentiometer vertical Bourns 3224X +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3269P_Horizontal +Potentiometer, horizontal, Bourns 3269P, https://www.bourns.com/docs/Product-Datasheets/3269.pdf +Potentiometer horizontal Bourns 3269P +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3269W_Vertical +Potentiometer, vertical, Bourns 3269W, https://www.bourns.com/docs/Product-Datasheets/3269.pdf +Potentiometer vertical Bourns 3269W +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3269X_Horizontal +Potentiometer, horizontal, Bourns 3269X, https://www.bourns.com/docs/Product-Datasheets/3269.pdf +Potentiometer horizontal Bourns 3269X +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3314G_Vertical +Potentiometer, vertical, Bourns 3314G, http://www.bourns.com/docs/Product-Datasheets/3314.pdf +Potentiometer vertical Bourns 3314G +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3314J_Vertical +Potentiometer, vertical, Bourns 3314J, http://www.bourns.com/docs/Product-Datasheets/3314.pdf +Potentiometer vertical Bourns 3314J +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3314R-1_Vertical_Hole +Potentiometer, vertical, shaft hole, Bourns 3314R-1, http://www.bourns.com/docs/Product-Datasheets/3314.pdf +Potentiometer vertical hole Bourns 3314R-1 +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3314R-GM5_Vertical +Potentiometer, vertical, Bourns 3314R-GM5, http://www.bourns.com/docs/Product-Datasheets/3314.pdf +Potentiometer vertical Bourns 3314R-GM5 +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_3314S_Horizontal +Potentiometer, horizontal, Bourns 3314S, http://www.bourns.com/docs/Product-Datasheets/3314.pdf +Potentiometer horizontal Bourns 3314S +0 +3 +3 +Potentiometer_SMD +Potentiometer_Bourns_PRS11S_Vertical +Potentiometer, vertical, Bourns PRS11S, http://www.bourns.com/docs/Product-Datasheets/PRS11S.pdf +Potentiometer vertical Bourns PRS11S +0 +5 +5 +Potentiometer_SMD +Potentiometer_Bourns_TC33X_Vertical +Potentiometer, Bourns, TC33X, Vertical, https://www.bourns.com/pdfs/TC33.pdf +Potentiometer Bourns TC33X Vertical +0 +3 +3 +Potentiometer_SMD +Potentiometer_Vishay_TS53YJ_Vertical +Potentiometer, vertical, Vishay TS53YJ, https://www.vishay.com/docs/51008/ts53.pdf +Potentiometer vertical Vishay TS53YJ +0 +3 +3 +Potentiometer_SMD +Potentiometer_Vishay_TS53YL_Vertical +Potentiometer, vertical, Vishay TS53YL, https://www.vishay.com/docs/51008/ts53.pdf +Potentiometer vertical Vishay TS53YL +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA6-H2,5_Horizontal +Potentiometer, horizontal, ACP CA6-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/06/01-ACP-CA6.pdf +Potentiometer horizontal ACP CA6-H2,5 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA9-H2,5_Horizontal +Potentiometer, horizontal, ACP CA9-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer horizontal ACP CA9-H2,5 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA9-H3,8_Horizontal +Potentiometer, horizontal, ACP CA9-H3,8, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer horizontal ACP CA9-H3,8 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA9-H5_Horizontal +Potentiometer, horizontal, ACP CA9-H5, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer horizontal ACP CA9-H5 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA9-V10_Vertical +Potentiometer, vertical, ACP CA9-V10, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer vertical ACP CA9-V10 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA9-V10_Vertical_Hole +Potentiometer, vertical, shaft hole, ACP CA9-V10, http://www.acptechnologies.com/wp-content/uploads/2017/05/02-ACP-CA9-CE9.pdf +Potentiometer vertical hole ACP CA9-V10 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA14-H2,5_Horizontal +Potentiometer, horizontal, ACP CA14-H2,5, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer horizontal ACP CA14-H2,5 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA14-H4_Horizontal +Potentiometer, horizontal, ACP CA14-H4, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer horizontal ACP CA14-H4 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA14-H5_Horizontal +Potentiometer, horizontal, ACP CA14-H5, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer horizontal ACP CA14-H5 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA14V-15_Vertical +Potentiometer, vertical, ACP CA14V-15, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer vertical ACP CA14V-15 +0 +3 +3 +Potentiometer_THT +Potentiometer_ACP_CA14V-15_Vertical_Hole +Potentiometer, vertical, shaft hole, ACP CA14V-15, http://www.acptechnologies.com/wp-content/uploads/2017/10/03-ACP-CA14-CE14.pdf +Potentiometer vertical hole ACP CA14V-15 +0 +3 +3 +Potentiometer_THT +Potentiometer_Alpha_RD901F-40-00D_Single_Vertical +Potentiometer, vertical, 9mm, single, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 +potentiometer vertical 9mm single +0 +5 +3 +Potentiometer_THT +Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles +Potentiometer, vertical, 9mm, single, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 +potentiometer vertical 9mm single +0 +5 +3 +Potentiometer_THT +Potentiometer_Alpha_RD902F-40-00D_Dual_Vertical +Potentiometer, vertical, 9mm, dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 +potentiometer vertical 9mm dual +0 +8 +6 +Potentiometer_THT +Potentiometer_Alpha_RD902F-40-00D_Dual_Vertical_CircularHoles +Potentiometer, vertical, 9mm, dual, http://www.taiwanalpha.com.tw/downloads?target=products&id=113 +potentiometer vertical 9mm dual +0 +8 +6 +Potentiometer_THT +Potentiometer_Alps_RK09K_Single_Horizontal +Potentiometer, horizontal, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html +Potentiometer horizontal Alps RK09K Single +0 +5 +3 +Potentiometer_THT +Potentiometer_Alps_RK09K_Single_Vertical +Potentiometer, vertical, Alps RK09K Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09K/RK09K_list.html +Potentiometer vertical Alps RK09K Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Alps_RK09L_Double_Horizontal +Potentiometer, horizontal, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html +Potentiometer horizontal Alps RK09L Double +0 +8 +6 +Potentiometer_THT +Potentiometer_Alps_RK09L_Double_Vertical +Potentiometer, vertical, Alps RK09L Double, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html +Potentiometer vertical Alps RK09L Double +0 +6 +6 +Potentiometer_THT +Potentiometer_Alps_RK09L_Single_Horizontal +Potentiometer, horizontal, Alps RK09L Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html +Potentiometer horizontal Alps RK09L Single +0 +5 +3 +Potentiometer_THT +Potentiometer_Alps_RK09L_Single_Vertical +Potentiometer, vertical, Alps RK09L Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09L/RK09L_list.html +Potentiometer vertical Alps RK09L Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Alps_RK09Y11_Single_Horizontal +Potentiometer, horizontal, Alps RK09Y11 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK09Y11/RK09Y11_list.html +Potentiometer horizontal Alps RK09Y11 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Alps_RK097_Dual_Horizontal +Potentiometer, horizontal, Alps RK097 Dual, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK097/RK097_list.html +Potentiometer horizontal Alps RK097 Dual +0 +6 +6 +Potentiometer_THT +Potentiometer_Alps_RK097_Single_Horizontal +Potentiometer, horizontal, Alps RK097 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK097/RK097_list.html +Potentiometer horizontal Alps RK097 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Alps_RK163_Dual_Horizontal +Potentiometer, horizontal, Alps RK163 Dual, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK16/RK16_list.html +Potentiometer horizontal Alps RK163 Dual +0 +6 +6 +Potentiometer_THT +Potentiometer_Alps_RK163_Single_Horizontal +Potentiometer, horizontal, Alps RK163 Single, http://www.alps.com/prod/info/E/HTML/Potentiometer/RotaryPotentiometers/RK16/RK16_list.html +Potentiometer horizontal Alps RK163 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3005_Horizontal +Potentiometer, horizontal, Bourns 3005, http://www.bourns.com/docs/Product-Datasheets/3005.pdf +Potentiometer horizontal Bourns 3005 +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3006P_Horizontal +Potentiometer, horizontal, Bourns 3006P, https://www.bourns.com/docs/Product-Datasheets/3006.pdf +Potentiometer horizontal Bourns 3006P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3006W_Horizontal +Potentiometer, horizontal, Bourns 3006W, https://www.bourns.com/docs/Product-Datasheets/3006.pdf +Potentiometer horizontal Bourns 3006W +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3006Y_Horizontal +Potentiometer, horizontal, Bourns 3006Y, https://www.bourns.com/docs/Product-Datasheets/3006.pdf +Potentiometer horizontal Bourns 3006Y +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3009P_Horizontal +Potentiometer, horizontal, Bourns 3009P, http://www.bourns.com/docs/Product-Datasheets/3009.pdf +Potentiometer horizontal Bourns 3009P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3009Y_Horizontal +Potentiometer, horizontal, Bourns 3009Y, http://www.bourns.com/docs/Product-Datasheets/3009.pdf +Potentiometer horizontal Bourns 3009Y +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3266P_Horizontal +Potentiometer, horizontal, Bourns 3266P, https://www.bourns.com/docs/Product-Datasheets/3266.pdf +Potentiometer horizontal Bourns 3266P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3266W_Vertical +Potentiometer, vertical, Bourns 3266W, https://www.bourns.com/docs/Product-Datasheets/3266.pdf +Potentiometer vertical Bourns 3266W +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3266X_Horizontal +Potentiometer, horizontal, Bourns 3266X, https://www.bourns.com/docs/Product-Datasheets/3266.pdf +Potentiometer horizontal Bourns 3266X +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3266Y_Vertical +Potentiometer, vertical, Bourns 3266Y, https://www.bourns.com/docs/Product-Datasheets/3266.pdf +Potentiometer vertical Bourns 3266Y +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3266Z_Horizontal +Potentiometer, horizontal, Bourns 3266Z, https://www.bourns.com/docs/Product-Datasheets/3266.pdf +Potentiometer horizontal Bourns 3266Z +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3296P_Horizontal +Potentiometer, horizontal, Bourns 3296P, https://www.bourns.com/pdfs/3296.pdf +Potentiometer horizontal Bourns 3296P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3296W_Vertical +Potentiometer, vertical, Bourns 3296W, https://www.bourns.com/pdfs/3296.pdf +Potentiometer vertical Bourns 3296W +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3296X_Horizontal +Potentiometer, horizontal, Bourns 3296X, https://www.bourns.com/pdfs/3296.pdf +Potentiometer horizontal Bourns 3296X +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3296Y_Vertical +Potentiometer, vertical, Bourns 3296Y, https://www.bourns.com/pdfs/3296.pdf +Potentiometer vertical Bourns 3296Y +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3296Z_Horizontal +Potentiometer, horizontal, Bourns 3296Z, https://www.bourns.com/pdfs/3296.pdf +Potentiometer horizontal Bourns 3296Z +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3299P_Horizontal +Potentiometer, horizontal, Bourns 3299P, https://www.bourns.com/pdfs/3299.pdf +Potentiometer horizontal Bourns 3299P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3299W_Vertical +Potentiometer, vertical, Bourns 3299W, https://www.bourns.com/pdfs/3299.pdf +Potentiometer vertical Bourns 3299W +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3299X_Horizontal +Potentiometer, horizontal, Bourns 3299X, https://www.bourns.com/pdfs/3299.pdf +Potentiometer horizontal Bourns 3299X +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3299Y_Vertical +Potentiometer, vertical, Bourns 3299Y, https://www.bourns.com/pdfs/3299.pdf +Potentiometer vertical Bourns 3299Y +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3299Z_Horizontal +Potentiometer, horizontal, Bourns 3299Z, https://www.bourns.com/pdfs/3299.pdf +Potentiometer horizontal Bourns 3299Z +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3339H_Vertical +Potentiometer, vertical, Bourns 3339H, http://www.bourns.com/docs/Product-Datasheets/3339.pdf +Potentiometer vertical Bourns 3339H +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3339P_Vertical +Potentiometer, vertical, Bourns 3339P, http://www.bourns.com/docs/Product-Datasheets/3339.pdf +Potentiometer vertical Bourns 3339P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3339P_Vertical_HandSoldering +Potentiometer, vertical, Bourns 3339P, hand-soldering, http://www.bourns.com/docs/Product-Datasheets/3339.pdf +Potentiometer vertical Bourns 3339P hand-soldering +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3339S_Horizontal +Potentiometer, horizontal, Bourns 3339S, http://www.bourns.com/docs/Product-Datasheets/3339.pdf +Potentiometer horizontal Bourns 3339S +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3339W_Horizontal +Potentiometer, horizontal, Bourns 3339W, http://www.bourns.com/docs/Product-Datasheets/3339.pdf +Potentiometer horizontal Bourns 3339W +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3386C_Horizontal +Potentiometer, horizontal, Bourns 3386C, https://www.bourns.com/pdfs/3386.pdf +Potentiometer horizontal Bourns 3386C +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3386F_Vertical +Potentiometer, vertical, Bourns 3386F, https://www.bourns.com/pdfs/3386.pdf +Potentiometer vertical Bourns 3386F +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3386P_Vertical +Potentiometer, vertical, Bourns 3386P, https://www.bourns.com/pdfs/3386.pdf +Potentiometer vertical Bourns 3386P +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_3386X_Horizontal +Potentiometer, horizontal, Bourns 3386X, https://www.bourns.com/pdfs/3386.pdf +Potentiometer horizontal Bourns 3386X +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_PTA1543_Single_Slide +Bourns single-gang slide potentiometer, 15.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf +Bourns single-gang slide potentiometer 15.0mm +0 +7 +4 +Potentiometer_THT +Potentiometer_Bourns_PTA2043_Single_Slide +Bourns single-gang slide potentiometer, 20.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf +Bourns single-gang slide potentiometer 20.0mm +0 +7 +4 +Potentiometer_THT +Potentiometer_Bourns_PTA3043_Single_Slide +Bourns single-gang slide potentiometer, 30.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf +Bourns single-gang slide potentiometer 30.0mm +0 +7 +4 +Potentiometer_THT +Potentiometer_Bourns_PTA4543_Single_Slide +Bourns single-gang slide potentiometer, 45.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf +Bourns single-gang slide potentiometer 45.0mm +0 +7 +4 +Potentiometer_THT +Potentiometer_Bourns_PTA6043_Single_Slide +Bourns single-gang slide potentiometer, 60.0mm travel, https://www.bourns.com/docs/Product-Datasheets/pta.pdf +Bourns single-gang slide potentiometer 60.0mm +0 +7 +4 +Potentiometer_THT +Potentiometer_Bourns_PTV09A-1_Single_Vertical +Potentiometer, vertical, Bourns PTV09A-1 Single, http://www.bourns.com/docs/Product-Datasheets/ptv09.pdf +Potentiometer vertical Bourns PTV09A-1 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Bourns_PTV09A-2_Single_Horizontal +Potentiometer, horizontal, Bourns PTV09A-2 Single, http://www.bourns.com/docs/Product-Datasheets/ptv09.pdf +Potentiometer horizontal Bourns PTV09A-2 Single +0 +5 +3 +Potentiometer_THT +Potentiometer_Omeg_PC16BU_Horizontal +Potentiometer, horizontal, Omeg PC16BU, http://www.omeg.co.uk/pc6bubrc.htm +Potentiometer horizontal Omeg PC16BU +0 +3 +3 +Potentiometer_THT +Potentiometer_Omeg_PC16BU_Vertical +Potentiometer, vertical, Omeg PC16BU, http://www.omeg.co.uk/pc6bubrc.htm +Potentiometer vertical Omeg PC16BU +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PC-16_Dual_Horizontal +Potentiometer, horizontal, Piher PC-16 Dual, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf +Potentiometer horizontal Piher PC-16 Dual +0 +6 +6 +Potentiometer_THT +Potentiometer_Piher_PC-16_Single_Horizontal +Potentiometer, horizontal, Piher PC-16 Single, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf +Potentiometer horizontal Piher PC-16 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PC-16_Single_Vertical +Potentiometer, vertical, Piher PC-16 Single, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf +Potentiometer vertical Piher PC-16 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PC-16_Triple_Horizontal +Potentiometer, horizontal, Piher PC-16 Triple, http://www.piher-nacesa.com/pdf/20-PC16v03.pdf +Potentiometer horizontal Piher PC-16 Triple +0 +9 +9 +Potentiometer_THT +Potentiometer_Piher_PT-6-H_Horizontal +Potentiometer, horizontal, Piher PT-6-H, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf +Potentiometer horizontal Piher PT-6-H +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-6-V_Vertical +Potentiometer, vertical, Piher PT-6-V, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf +Potentiometer vertical Piher PT-6-V +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-6-V_Vertical_Hole +Potentiometer, vertical, shaft hole, Piher PT-6-V, http://www.piher-nacesa.com/pdf/11-PT6v03.pdf +Potentiometer vertical hole Piher PT-6-V +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-10-H01_Horizontal +Potentiometer, horizontal, Piher PT-10-H01, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf +Potentiometer horizontal Piher PT-10-H01 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-10-H05_Horizontal +Potentiometer, horizontal, Piher PT-10-H05, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf +Potentiometer horizontal Piher PT-10-H05 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-10-V05_Vertical +Potentiometer, vertical, Piher PT-10-V05, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf +Potentiometer vertical Piher PT-10-V05 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-10-V10_Vertical +Potentiometer, vertical, Piher PT-10-V10, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf +Potentiometer vertical Piher PT-10-V10 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-10-V10_Vertical_Hole +Potentiometer, vertical, shaft hole, Piher PT-10-V10, http://www.piher-nacesa.com/pdf/12-PT10v03.pdf +Potentiometer vertical hole Piher PT-10-V10 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-H01_Horizontal +Potentiometer, horizontal, Piher PT-15-H01, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer horizontal Piher PT-15-H01 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-H05_Horizontal +Potentiometer, horizontal, Piher PT-15-H05, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer horizontal Piher PT-15-H05 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-H06_Horizontal +Potentiometer, horizontal, Piher PT-15-H06, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer horizontal Piher PT-15-H06 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-H25_Horizontal +Potentiometer, horizontal, Piher PT-15-H25, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer horizontal Piher PT-15-H25 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-V02_Vertical +Potentiometer, vertical, Piher PT-15-V02, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer vertical Piher PT-15-V02 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-V02_Vertical_Hole +Potentiometer, vertical, shaft hole, Piher PT-15-V02, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer vertical hole Piher PT-15-V02 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-V15_Vertical +Potentiometer, vertical, Piher PT-15-V15, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer vertical Piher PT-15-V15 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_PT-15-V15_Vertical_Hole +Potentiometer, vertical, shaft hole, Piher PT-15-V15, http://www.piher-nacesa.com/pdf/14-PT15v03.pdf +Potentiometer vertical hole Piher PT-15-V15 +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_T-16H_Double_Horizontal +Potentiometer, horizontal, Piher T-16H Double, http://www.piher-nacesa.com/pdf/22-T16v03.pdf +Potentiometer horizontal Piher T-16H Double +0 +6 +6 +Potentiometer_THT +Potentiometer_Piher_T-16H_Single_Horizontal +Potentiometer, horizontal, Piher T-16H Single, http://www.piher-nacesa.com/pdf/22-T16v03.pdf +Potentiometer horizontal Piher T-16H Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Piher_T-16L_Single_Vertical_Hole +Potentiometer, vertical, shaft hole, Piher T-16L Single, http://www.piher-nacesa.com/pdf/22-T16v03.pdf +Potentiometer vertical hole Piher T-16L Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Runtron_RM-063_Horizontal +Potentiometer, horizontal, Trimmer, RM-063 http://www.runtron.com/down/PDF%20Datasheet/Carbon%20Film%20Potentiometer/RM065%20RM063.pdf +Potentiometer Trimmer RM-063 +0 +3 +3 +Potentiometer_THT +Potentiometer_Runtron_RM-065_Vertical +Potentiometer, vertical, Trimmer, RM-065 http://www.runtron.com/down/PDF%20Datasheet/Carbon%20Film%20Potentiometer/RM065%20RM063.pdf +Potentiometer Trimmer RM-065 +0 +3 +3 +Potentiometer_THT +Potentiometer_TT_P0915N +http://www.ttelectronics.com/sites/default/files/download-files/Datasheet_PanelPot_P09xSeries.pdf +potentiometer vertical TT P0915N single +0 +5 +3 +Potentiometer_THT +Potentiometer_Vishay_43_Horizontal +Potentiometer, horizontal, Vishay 43, http://www.vishay.com/docs/57026/43.pdf +Potentiometer horizontal Vishay 43 +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_148-149_Dual_Horizontal +Potentiometer, horizontal, Vishay 148-149 Dual, http://www.vishay.com/docs/57040/148149.pdf +Potentiometer horizontal Vishay 148-149 Dual +0 +6 +6 +Potentiometer_THT +Potentiometer_Vishay_148-149_Single_Horizontal +Potentiometer, horizontal, Vishay 148-149 Single, http://www.vishay.com/docs/57040/148149.pdf +Potentiometer horizontal Vishay 148-149 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_148-149_Single_Vertical +Potentiometer, vertical, Vishay 148-149 Single, http://www.vishay.com/docs/57040/148149.pdf +Potentiometer vertical Vishay 148-149 Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_148E-149E_Dual_Horizontal +Potentiometer, horizontal, Vishay 148E-149E Dual, http://www.vishay.com/docs/57040/148149.pdf +Potentiometer horizontal Vishay 148E-149E Dual +0 +10 +6 +Potentiometer_THT +Potentiometer_Vishay_148E-149E_Single_Horizontal +Potentiometer, horizontal, Vishay 148E-149E Single, http://www.vishay.com/docs/57040/148149.pdf +Potentiometer horizontal Vishay 148E-149E Single +0 +7 +3 +Potentiometer_THT +Potentiometer_Vishay_248BH-249BH_Single_Horizontal +Potentiometer, horizontal, Vishay 248BH-249BH Single, http://www.vishay.com/docs/57054/248249.pdf +Potentiometer horizontal Vishay 248BH-249BH Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_248GJ-249GJ_Single_Horizontal +Potentiometer, horizontal, Vishay 248GJ-249GJ Single, http://www.vishay.com/docs/57054/248249.pdf +Potentiometer horizontal Vishay 248GJ-249GJ Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_248GJ-249GJ_Single_Vertical +Potentiometer, vertical, Vishay 248GJ-249GJ Single, http://www.vishay.com/docs/57054/248249.pdf +Potentiometer vertical Vishay 248GJ-249GJ Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_T7-YA_Single_Vertical +Potentiometer, vertical, Vishay T7-YA Single, http://www.vishay.com/docs/51015/t7.pdf +Potentiometer vertical Vishay T7-YA Single +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_T73XW_Horizontal +Potentiometer, horizontal, Vishay T73XW, http://www.vishay.com/docs/51016/t73.pdf +Potentiometer horizontal Vishay T73XW +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_T73XX_Horizontal +Potentiometer, horizontal, Vishay T73XX, http://www.vishay.com/docs/51016/t73.pdf +Potentiometer horizontal Vishay T73XX +0 +3 +3 +Potentiometer_THT +Potentiometer_Vishay_T73YP_Vertical +Potentiometer, vertical, Vishay T73YP, http://www.vishay.com/docs/51016/t73.pdf +Potentiometer vertical Vishay T73YP +0 +3 +3 +RF +Skyworks_SKY13575_639LF +http://www.skyworksinc.com/uploads/documents/SKY13575_639LF_203270D.pdf +Skyworks +0 +19 +15 +RF +Skyworks_SKY65404-31 +http://www.skyworksinc.com/uploads/documents/SKY65404_31_201512K.pdf +Skyworks +0 +7 +7 +RF_Antenna +Coilcraft_MA5532-AE_RFID +RFID Transponder Coil +antenna rfid coilcraft +0 +2 +2 +RF_Antenna +Pulse_W3011 +Pulse RF Antenna, 4mm Clearance +antenna rf +0 +3 +2 +RF_Antenna +Texas_SWRA117D_2.4GHz_Left +http://www.ti.com/lit/an/swra117d/swra117d.pdf +PCB antenna +0 +2 +2 +RF_Antenna +Texas_SWRA117D_2.4GHz_Right +http://www.ti.com/lit/an/swra117d/swra117d.pdf +PCB antenna +0 +2 +2 +RF_Antenna +Texas_SWRA416_868MHz_915MHz +http://www.ti.com/lit/an/swra416/swra416.pdf +PCB antenna +0 +20 +1 +RF_Converter +Anaren_0805_2012Metric-6 +https://cdn.anaren.com/product-documents/Xinger/DirectionalCouplers/DC4759J5020AHF/DC4759J5020AHF_DataSheet(Rev_E).pdf +coupler rf +0 +6 +6 +RF_Converter +Balun_Johanson_1.6x0.8mm +6-pin 1.6x0.8 mm balun footprint +Johanson balun filter +0 +6 +6 +RF_Converter +Balun_Johanson_5400BL15B050E +https://www.johansontechnology.com/datasheets/5400BL15B050/5400BL15B050.pdf +balun RF +0 +6 +6 +RF_Converter +RF_Attenuator_Susumu_PAT1220 +http://www.susumu-usa.com/pdf/Foot_Print_38.pdf, https://www.susumu.co.jp/common/pdf/n_catalog_partition16_en.pdf +2mm 1.2mm +0 +3 +3 +RF_GPS +Linx_RXM-GPS +GPS Module, Linx +gps linx +0 +22 +22 +RF_GPS +SIM28ML +https://simcom.ee/documents/SIM28ML/SIM28ML_Hardware%20Design_V1.01.pdf +SIM28ML GPS +0 +18 +18 +RF_GPS +Sierra_XA11X0 +QFN-24, Pitch 1.20 no EP, https://source.sierrawireless.com/resources/airprime/hardware_specs_user_guides/airprime_xm1100_product_technical_specification +QFN-24 P1.20 +0 +24 +24 +RF_GPS +Sierra_XM11X0 +QFN-20, Pitch 1.20 no EP, https://source.sierrawireless.com/resources/airprime/hardware_specs_user_guides/airprime_xm1100_product_technical_specification +QFN-20 P1.20 +0 +20 +20 +RF_GPS +ublox_LEA +ublox LEA 6/7/8, (https://www.u-blox.com/sites/default/files/LEA-M8S-M8T-FW3_HardwareIntegrationManual_%28UBX-15030060%29.pdf) +GPS ublox LEA 6/7/8 +0 +28 +28 +RF_GPS +ublox_MAX +ublox MAX 6/7/8, (https://www.u-blox.com/sites/default/files/MAX-8-M8-FW3_HardwareIntegrationManual_%28UBX-15030059%29.pdf) +GPS ublox MAX 6/7/8 +0 +18 +18 +RF_GPS +ublox_NEO +ublox NEO 6/7/8, (https://www.u-blox.com/sites/default/files/NEO-8Q-NEO-M8-FW3_HardwareIntegrationManual_%28UBX-15029985%29_0.pdf) +GPS ublox NEO 6/7/8 +0 +24 +24 +RF_GPS +ublox_SAM-M8Q +GPS Module, 15.5x15.5x6.3mm, https://www.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf +ublox SAM-M8Q +0 +100 +20 +RF_GPS +ublox_SAM-M8Q_HandSolder +GPS Module, 15.5x15.5x6.3mm, https://www.u-blox.com/sites/default/files/SAM-M8Q_HardwareIntegrationManual_%28UBX-16018358%29.pdf +ublox SAM-M8Q +0 +20 +20 +RF_GSM +Quectel_BC66 +GSM NB-IoT module, 15.8x17.7x2mm, https://www.quectel.com/UploadImage/Downlad/Quectel_BC66_Hardware_Design_V1.1.pdf +GSM NB-IoT Module BC66 M66 +0 +58 +58 +RF_GSM +SIMCom_SIM800C +Quad-Band GSM/GPRS module, 17.6x15.7x2.3mm, http://simcom.ee/documents/SIM800C/SIM800C_Hardware_Design_V1.05.pdf +GSM Module SIM800C +0 +42 +42 +RF_GSM +SIMCom_SIM900 +Quad-Band GSM/GPRS module, 24x24x3mm, http://simcom.ee/documents/SIM900/SIM900_Hardware%20Design_V2.05.pdf +GSM Module SIM900 +0 +68 +68 +RF_GSM +Telit_xL865 +Telit xL865 familly footprint, http://www.telit.com/fileadmin/user_upload/products/Downloads/3G/Telit_UL865_Hardware_User_Guide_r8.pdf +xL865 gsm umts +0 +52 +48 +RF_GSM +ublox_SARA-G3_LGA-96 +ublox Sara GSM/HSPA modem, https://www.u-blox.com/sites/default/files/SARA-G3-U2_SysIntegrManual_%28UBX-13000995%29.pdf, pag.162 +ublox SARA-G3 SARA-U2 GSM HSPA +0 +192 +96 +RF_Mini-Circuits +Mini-Circuits_BK377 +Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf) +Mini-circuits BK377 +0 +14 +14 +RF_Mini-Circuits +Mini-Circuits_BK377_LandPatternPL-005 +Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf) according to land-pattern PL-005, including GND vias (https://ww2.minicircuits.com/pcb/98-pl005.pdf) +Mini-circuits VCXO JTOS PL-005 +0 +50 +14 +RF_Mini-Circuits +Mini-Circuits_CD541_H2.08mm +https://ww2.minicircuits.com/case_style/CD541.pdf +RF Transformer +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_CD542_H2.84mm +https://ww2.minicircuits.com/case_style/CD542.pdf +RF Transformer +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_CD542_LandPatternPL-052 +Footprint for Mini-Circuits case CD542 (https://ww2.minicircuits.com/case_style/CD542.pdf) using land-pattern PL-052, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl052.pdf) +MiniCircuits PL-052 CD542 +0 +17 +6 +RF_Mini-Circuits +Mini-Circuits_CD542_LandPatternPL-094 +Footprint for mini circuit case CD542, Land pattern PL-094, pads 5 and 2 connected via insulated copper area below body, vias included (case drawing: https://ww2.minicircuits.com/case_style/CD542.pdf, land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl094.pdf) +mini-circuits CD542 pl-094 +0 +18 +6 +RF_Mini-Circuits +Mini-Circuits_CD636_H4.11mm +https://ww2.minicircuits.com/case_style/CD636.pdf +RF Transformer +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_CD636_LandPatternPL-035 +Footprint for Mini-Circuits case CD636 (https://ww2.minicircuits.com/case_style/CD636.pdf) following land pattern PL-035, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl035.pdf) +mini-circuits pl-035 CD636 +0 +13 +6 +RF_Mini-Circuits +Mini-Circuits_CD637_H5.23mm +https://ww2.minicircuits.com/case_style/CD637.pdf +RF Transformer +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_CK605 +Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf) +Mini-Circuits CK605 +0 +16 +16 +RF_Mini-Circuits +Mini-Circuits_CK605_LandPatternPL-012 +Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf) following land pattern PL-012, including GND vias (https://ww2.minicircuits.com/pcb/98-pl012.pdf) +Mini-Circuits PL-012 +0 +53 +16 +RF_Mini-Circuits +Mini-Circuits_DB1627 +Mini-Circuits top-hat case DB1627 (https://ww2.minicircuits.com/case_style/DB1627.pdf) +Mini-Circuits DB1627 +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_GP731 +Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) +Mini-Circuits GP731 +0 +8 +8 +RF_Mini-Circuits +Mini-Circuits_GP731_LandPatternPL-176 +Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf) +mini-circuits PL-176 +0 +21 +8 +RF_Mini-Circuits +Mini-Circuits_GP1212 +Footprint for Mini-Circuits case GP1212 (https://ww2.minicircuits.com/case_style/GP731.pdf) +mini-circuits GP1212 +0 +8 +8 +RF_Mini-Circuits +Mini-Circuits_GP1212_LandPatternPL-176 +Footprint for Mini-Circuits case GP1212 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-176, including GND vias (https://www.minicircuits.com/pcb/98-pl176.pdf) +mini-circuits PL-176 +0 +21 +8 +RF_Mini-Circuits +Mini-Circuits_HF1139 +Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf) +Mini-Circuits HF1139 +0 +8 +8 +RF_Mini-Circuits +Mini-Circuits_HF1139_LandPatternPL-230 +Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf) following land pattern PL-230, including GND vias (https://ww2.minicircuits.com/pcb/98-pl230.pdf) +Mini-Circuits PL-230 +0 +37 +8 +RF_Mini-Circuits +Mini-Circuits_HZ1198 +Footprint for Mini-Circuits case HZ1198 (https://ww2.minicircuits.com/case_style/HZ1198.pdf) +Mini-Circuits HZ1198 +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_HZ1198_LandPatternPL-247 +Footprint for Mini-Circuits cas HZ1198 (https://ww2.minicircuits.com/case_style/HZ1198.pdf) following land pattern PL-247, including GND-vias (https://www.minicircuits.com/pcb/98-pl247.pdf) +Mini-Circuits PL-247 HZ1198 +0 +40 +6 +RF_Mini-Circuits +Mini-Circuits_MMM168 +Footprint for Mini-Circuits case MMM168 (https://ww2.minicircuits.com/case_style/MMM168.pdf) +Mini-Circuits MMM168 +0 +4 +4 +RF_Mini-Circuits +Mini-Circuits_MMM168_LandPatternPL-225 +Footprint for Mini-Circuits case MMM168, Land pattern PL-225, vias included, (case drawing: https://ww2.minicircuits.com/case_style/MMM168.pdf, land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl225.pdf) +pl-225 +0 +10 +4 +RF_Mini-Circuits +Mini-Circuits_QQQ130_ClockwisePinNumbering +Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf) +Mini-Circuits QQQ130 +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_QQQ130_LandPattern_PL-236_ClockwisePinNumbering +Footprint for Mini-Circuits case QQQ130 (https://ww2.minicircuits.com/case_style/QQQ130.pdf) following land pattern PL-236, including GND vias (https://ww2.minicircuits.com/pcb/98-pl236.pdf) +Mini-Circuits PL-236 +0 +14 +6 +RF_Mini-Circuits +Mini-Circuits_TT1224_ClockwisePinNumbering +Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl258.pdf) +Mini-Circuits TT1224 +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_TT1224_LandPatternPL-258_ClockwisePinNumbering +Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://www.minicircuits.com/pcb/98-pl258.pdf) +PL-258 Mini-Circuits +0 +26 +6 +RF_Mini-Circuits +Mini-Circuits_TTT167 +Footprint for Mini-Circuits case TTT167 (https://ww2.minicircuits.com/case_style/TTT167.pdf) +Mini-Circuits TTT167 +0 +6 +6 +RF_Mini-Circuits +Mini-Circuits_TTT167_LandPatternPL-079 +Footprint for Mini-Circuits case TTT167 (Mini-Circuits_TTT167_LandPatternPL-079) following land pattern PL-079, including GND vias (https://ww2.minicircuits.com/pcb/98-pl079.pdf) +Mini-Circuits PL-079 +0 +36 +6 +RF_Mini-Circuits +Mini-Circuits_YY161 +Footprint for Mini-Circuits case YY161 (https://ww2.minicircuits.com/case_style/YY161.pdf) +Mini-Circuits YY161 +0 +8 +8 +RF_Mini-Circuits +Mini-Circuits_YY161_LandPatternPL-049 +Footprint for Mini-Circuits case YY161 (https://ww2.minicircuits.com/case_style/YY161.pdf) using land-pattern PL-049, including GND-connections and vias (https://ww2.minicircuits.com/pcb/98-pl049.pdf) +mini-circuits pl-049 +0 +36 +8 +RF_Module +Ai-Thinker-Ra-01-LoRa +Ai Thinker Ra-01 LoRa +LoRa Ra-01 +0 +16 +16 +RF_Module +Atmel_ATSAMR21G18-MR210UA_NoRFPads +http://ww1.microchip.com/downloads/en/devicedoc/atmel-42475-atsamr21g18-mr210ua_datasheet.pdf +module wireless zigbee 802.15.4 flash crypto ATSAMR21G18 AT45DB041E TECC508A U.Fi +0 +42 +42 +RF_Module +BLE112-A +Class 4 Bluetooth Module with on-board antenna +Bluetooth Module +0 +30 +30 +RF_Module +CMWX1ZZABZ +https://wireless.murata.com/RFM/data/type_abz.pdf +iot lora sigfox +0 +57 +57 +RF_Module +CYBLE-21Pin-10x10mm +Cypress EZ-BLE PRoC Module (Bluetooth Smart) 21 Pin Module +Cypress BT Bluetooth +0 +21 +21 +RF_Module +DWM1000 +IEEE802.15.4-2011 UWB +UWB Module +0 +24 +24 +RF_Module +DecaWave_DWM1001 +https://www.decawave.com/sites/default/files/dwm1001_datasheet.pdf +UWB module +0 +34 +34 +RF_Module +Digi_XBee_SMT +http://www.digi.com/resources/documentation/digidocs/pdfs/90002126.pdf http://ftp1.digi.com/support/documentation/90001020_F.pdf +Digi XBee SMT RF +0 +37 +37 +RF_Module +E18-MS1-PCB +http://www.cdebyte.com/en/downpdf.aspx?id=122 +Zigbee +0 +24 +24 +RF_Module +E73-2G4M04S +http://www.cdebyte.com/en/downpdf.aspx?id=243 +BLE BLE5 nRF52832 +0 +44 +44 +RF_Module +ESP-07 +Wi-Fi Module, http://wiki.ai-thinker.com/_media/esp8266/docs/a007ps01a2_esp-07_product_specification_v1.2.pdf +Wi-Fi Module +0 +16 +16 +RF_Module +ESP-12E +Wi-Fi Module, http://wiki.ai-thinker.com/_media/esp8266/docs/aithinker_esp_12f_datasheet_en.pdf +Wi-Fi Module +0 +22 +22 +RF_Module +ESP-WROOM-02 +http://espressif.com/sites/default/files/documentation/0c-esp-wroom-02_datasheet_en.pdf +ESP WROOM-02 espressif esp8266ex +0 +19 +19 +RF_Module +ESP32-WROOM-32 +Single 2.4 GHz Wi-Fi and Bluetooth combo chip https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32_datasheet_en.pdf +Single 2.4 GHz Wi-Fi and Bluetooth combo chip +0 +39 +39 +RF_Module +ESP32-WROOM-32U +Single 2.4 GHz Wi-Fi and Bluetooth combo chip with U.FL connector, https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32d_esp32-wroom-32u_datasheet_en.pdf +Single 2.4 GHz Wi-Fi and Bluetooth combo chip +0 +39 +39 +RF_Module +Garmin_M8-35_9.8x14.0mm_Layout6x6_P1.5mm +D52M ANT SoC Module https://www.thisisant.com/assets/resources/D00001687_D52_Module_Datasheet.v.2.3_(Garmin).pdf +RF SoC Radio ANT Bluetooth BLE D52 nRF52 Garmin Canada Dynastream Nordic +0 +35 +35 +RF_Module +HOPERF_RFM9XW_SMD +Low Power Long Range Transceiver Module SMD-16 (https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf) +LoRa Low Power Long Range Transceiver Module +0 +16 +16 +RF_Module +HOPERF_RFM9XW_THT +Low Power Long Range Transceiver Module THT-16 (https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf) +Low Power Long Range Transceiver Module LoRa +0 +16 +16 +RF_Module +HOPERF_RFM69HW +Radio, RF, Module, http://www.hoperf.com/upload/rf/RFM69HW-V1.3.pdf +Radio RF Module +0 +16 +16 +RF_Module +IQRF_TRx2DA_KON-SIM-01 +8 pin SIM connector for IQRF TR-x2DA(T) modules, http://iqrf.org/weben/downloads.php?id=104 +IQRF_KON-SIM-01 IQRF_TRx2DA +0 +10 +8 +RF_Module +IQRF_TRx2D_KON-SIM-01 +8 pin SIM connector for IQRF TR-x2D(C)(T) modules, http://iqrf.org/weben/downloads.php?id=104 +IQRF_KON-SIM-01 IQRF_TRx2D IQRF_TRx2DC +0 +10 +8 +RF_Module +Laird_BL652 +Bluetooth v4.2 + NFC module +Bluetooth BLE NFC +0 +39 +39 +RF_Module +MOD-nRF8001 +BLE module, https://www.olimex.com/Products/Modules/RF/MOD-nRF8001/ +BLE module +0 +11 +11 +RF_Module +Microchip_RN4871 +Microchip RN4871 footprint +RN4871 BLE +0 +16 +16 +RF_Module +Modtronix_inAir9 +Modtronix Wireless SX1276 LoRa Module (http://modtronix.com/img/prod/imod/inair9/inair_dimensions.gif) +Modtronix LoRa inAir inAir9 SX1276 RF 915MHz 868MHz Wireless +0 +14 +14 +RF_Module +MonoWireless_TWE-L-WX +https://www.mono-wireless.com/jp/products/TWE-LITE/MW-PDS-TWELITE-JP.pdf +TWE-L-WX +0 +32 +32 +RF_Module +Particle_P1 +https://docs.particle.io/datasheets/p1-datasheet/ +Particle P1 +0 +75 +75 +RF_Module +RFDigital_RFD77101 +RFDigital RFD77101 Simblee +RFDigital RFD77101 Simblee +0 +48 +45 +RF_Module +RN42 +Class 2 Bluetooth Module with on-board antenna +Bluetooth Module +0 +36 +33 +RF_Module +RN42N +Class 2 Bluetooth Module without antenna +Bluetooth Module +0 +39 +36 +RF_Module +RN2483 +Low-Power Long Range LoRa Transceiver Module +rf module lora lorawan +0 +47 +47 +RF_Module +ST_SPBTLE +Bluetooth Low Energy Module +ble module st bluetooth +0 +11 +11 +RF_Module +TD1205 +https://github.com/Telecom-Design/Documentation_TD_RF_Module/blob/master/TD1205%20Datasheet.pdf +SIGFOX Module +0 +9 +9 +RF_Module +TD1208 +https://github.com/Telecom-Design/Documentation_TD_RF_Module/blob/master/TD1208%20Datasheet.pdf +SIGFOX Module +0 +25 +25 +RF_Module +Taiyo-Yuden_EYSGJNZWY +Taiyo Yuden NRF51822 Module Bluetooth https://www.yuden.co.jp/wireless_module/document/datareport2/en/TY_BLE_EYSGJNZ_DataReport_V1_9_20180530E.pdf +Taiyo Yuden NRF51822 Module Bluetooth +0 +30 +28 +RF_Module +ZETA-433-SO_SMD +RF transceiver SMD style https://www.rfsolutions.co.uk/downloads/1456219226DS-ZETA.pdf +RF transceiver SMD style +0 +12 +12 +RF_Module +ZETA-433-SO_THT +RF transceiver THT style https://www.rfsolutions.co.uk/downloads/1456219226DS-ZETA.pdf +RF transceiver SMD style +0 +12 +12 +RF_Module +nRF24L01_Breakout +nRF24L01 breakout board +nRF24L01 adapter breakout +0 +8 +8 +RF_Shielding +Laird_Technologies_97-2002_25.40x25.40mm +Laird Technologies 97-2002 EZ PEEL Shielding Cabinet One Piece SMD 25.40x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +8 +1 +RF_Shielding +Laird_Technologies_97-2003_12.70x13.37mm +Laird Technologies 97-2003 EZ PEEL Shielding Cabinet One Piece SMD 12.70x13.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +8 +1 +RF_Shielding +Laird_Technologies_BMI-S-101_13.66x12.70mm +Laird Technologies BMI-S-101 Shielding Cabinet One Piece SMD 13.66x12.70mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +16 +1 +RF_Shielding +Laird_Technologies_BMI-S-102_16.50x16.50mm +Laird Technologies BMI-S-102 Shielding Cabinet One Piece SMD 16.50x16.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +16 +1 +RF_Shielding +Laird_Technologies_BMI-S-103_26.21x26.21mm +Laird Technologies BMI-S-103 Shielding Cabinet One Piece SMD 26.21x26.21mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +24 +1 +RF_Shielding +Laird_Technologies_BMI-S-104_32.00x32.00mm +Laird Technologies BMI-S-104 Shielding Cabinet One Piece SMD 32.00x32.00mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +28 +1 +RF_Shielding +Laird_Technologies_BMI-S-105_38.10x25.40mm +Laird Technologies BMI-S-105 Shielding Cabinet One Piece SMD 38.10x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +28 +1 +RF_Shielding +Laird_Technologies_BMI-S-106_36.83x33.68mm +Laird Technologies BMI-S-106 Shielding Cabinet One Piece SMD 36.83x33.68mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +28 +1 +RF_Shielding +Laird_Technologies_BMI-S-107_44.37x44.37mm +Laird Technologies BMI-S-107 Shielding Cabinet One Piece SMD 44.37x44.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +36 +1 +RF_Shielding +Laird_Technologies_BMI-S-201-F_13.66x12.70mm +Laird Technologies BMI-S-201-F Shielding Cabinet Two Piece SMD 13.66x12.70mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +16 +1 +RF_Shielding +Laird_Technologies_BMI-S-202-F_16.50x16.50mm +Laird Technologies BMI-S-202-F Shielding Cabinet Two Piece SMD 16.50x16.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +16 +1 +RF_Shielding +Laird_Technologies_BMI-S-203-F_26.21x26.21mm +Laird Technologies BMI-S-203-F Shielding Cabinet Two Piece SMD 26.21x26.21mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +24 +1 +RF_Shielding +Laird_Technologies_BMI-S-204-F_32.00x32.00mm +Laird Technologies BMI-S-204-F Shielding Cabinet Two Piece SMD 32.00x32.00mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +28 +1 +RF_Shielding +Laird_Technologies_BMI-S-205-F_38.10x25.40mm +Laird Technologies BMI-S-205-F Shielding Cabinet Two Piece SMD 38.10x25.40mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +28 +1 +RF_Shielding +Laird_Technologies_BMI-S-206-F_36.83x33.68mm +Laird Technologies BMI-S-206-F Shielding Cabinet Two Piece SMD 36.83x33.68mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +28 +1 +RF_Shielding +Laird_Technologies_BMI-S-207-F_44.37x44.37mm +Laird Technologies BMI-S-207-F Shielding Cabinet Two Piece SMD 44.37x44.37mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +36 +1 +RF_Shielding +Laird_Technologies_BMI-S-208-F_39.60x39.60mm +Laird Technologies BMI-S-208-F Shielding Cabinet Two Piece SMD 39.60x39.60mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +32 +1 +RF_Shielding +Laird_Technologies_BMI-S-209-F_29.36x18.50mm +Laird Technologies BMI-S-209-F Shielding Cabinet Two Piece SMD 29.36x18.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +20 +1 +RF_Shielding +Laird_Technologies_BMI-S-210-F_44.00x30.50mm +Laird Technologies BMI-S-210-F Shielding Cabinet Two Piece SMD 44.00x30.50mm (https://assets.lairdtech.com/home/brandworld/files/Board%20Level%20Shields%20Catalog%20Download.pdf) +Shielding Cabinet +0 +32 +1 +RF_Shielding +Laird_Technologies_BMI-S-230-F_50.8x38.1mm +Laird Technologies BMI-S-230-F Shielding Cabinet Two Piece SMD 50.8x38.1mm +Shielding Cabinet +0 +36 +1 +RF_Shielding +Wuerth_36103205_20x20mm +WE-SHC Shielding Cabinet SMD 20x20mm +Shielding Cabinet +0 +20 +1 +RF_Shielding +Wuerth_36103255_25x25mm +WE-SHC Shielding Cabinet SMD 25x25mm +Shielding Cabinet +0 +24 +1 +RF_Shielding +Wuerth_36103305_30x30mm +WE-SHC Shielding Cabinet SMD 30x30mm +Shielding Cabinet +0 +28 +1 +RF_Shielding +Wuerth_36103505_50x50mm +WE-SHC Shielding Cabinet SMD 50x50mm +Shielding Cabinet +0 +44 +1 +RF_Shielding +Wuerth_36103605_60x60mm +WE-SHC Shielding Cabinet SMD 60x60mm +Shielding Cabinet +0 +52 +1 +RF_Shielding +Wuerth_36503205_20x20mm +WE-SHC Shielding Cabinet THT 21x21mm +Shielding Cabinet +0 +16 +1 +RF_Shielding +Wuerth_36503255_25x25mm +WE-SHC Shielding Cabinet THT 26x26mm +Shielding Cabinet +0 +20 +1 +RF_Shielding +Wuerth_36503305_30x30mm +WE-SHC Shielding Cabinet THT 31x31mm +Shielding Cabinet +0 +24 +1 +RF_Shielding +Wuerth_36503505_50x50mm +WE-SHC Shielding Cabinet THT 51x51mm +Shielding Cabinet +0 +40 +1 +RF_Shielding +Wuerth_36503605_60x60mm +WE-SHC Shielding Cabinet THT 61x61mm +Shielding Cabinet +0 +48 +1 +RF_WiFi +USR-C322 +https://www.usriot.com/download/WIFI/USR-C322-Hardware-Manual_V1.2.01.pdf +WiFi IEEE802.11 b/g/n +0 +44 +44 +Relay_SMD +Relay_DPDT_AXICOM_IMSeries_JLeg +http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Specification+Or+Standard%7F108-98001%7FW5%7Fpdf%7FEnglish%7FENG_SS_108-98001_W5.pdf +AXICOM IM-Series Relay J JLeg +0 +8 +8 +Relay_SMD +Relay_DPDT_FRT5_SMD +IM Signal Relay DPDT FRT5 narrow footprint, SMD version of package +Relay DPDT IM-relay FRT5 +0 +10 +10 +Relay_SMD +Relay_DPDT_Omron_G6H-2F +package for Omron G6H-2F relais, see http://cdn-reichelt.de/documents/datenblatt/C300/G6H%23OMR.pdf +Omron G6H-2F relais +0 +10 +10 +Relay_SMD +Relay_DPDT_Omron_G6K-2F +Omron G6K-2F relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf +Omron G6K-2F relay +0 +8 +8 +Relay_SMD +Relay_DPDT_Omron_G6K-2F-Y +Omron G6K-2F-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf +Omron G6K-2F-Y relay +0 +8 +8 +Relay_SMD +Relay_DPDT_Omron_G6K-2G +Omron G6K-2G relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf +Omron G6K-2G relay +0 +8 +8 +Relay_SMD +Relay_DPDT_Omron_G6K-2G-Y +Omron G6K-2G-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf +Omron G6K-2G-Y relay +0 +8 +8 +Relay_SMD +Relay_DPDT_Omron_G6S-2F +Relay Omron G6S-2F, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf +Relay Omron G6S-2F +0 +8 +8 +Relay_SMD +Relay_DPDT_Omron_G6S-2G +Relay Omron G6S-2G, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf +Relay Omron G6S-2G +0 +8 +8 +Relay_SMD +Relay_DPDT_Omron_G6SK-2F +Relay Omron G6SK-2F, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf +Relay Omron G6SK-2F +0 +10 +10 +Relay_SMD +Relay_DPDT_Omron_G6SK-2G +Relay Omron G6SK-2G, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf +Relay Omron G6SK-2G +0 +10 +10 +Relay_SMD +Relay_SPDT_AXICOM_HF3Series_50ohms_Pitch1.27mm +hiqsdr.com/images/3/3e/Axicom-HF3.pdf +AXICOM HF3-Series Relay Pitch 1.27mm 50ohms +0 +16 +16 +Relay_SMD +Relay_SPDT_AXICOM_HF3Series_75ohms_Pitch1.27mm +hiqsdr.com/images/3/3e/Axicom-HF3.pdf +AXICOM HF3-Series Relay Pitch 1.27mm 75ohm +0 +16 +16 +Relay_THT +Relay_1-Form-A_Schrack-RYII_RM5mm +Relay, 1-Form-A, Schrack-RYII, RM5mm, SPST-NO +Relay 1-Form-A Schrack-RYII RM5mm SPST-NO +0 +4 +4 +Relay_THT +Relay_1-Form-B_Schrack-RYII_RM5mm +Relay, 1-Form-B, Schrack-RYII, RM5mm, SPST-NC +Relay 1-Form-B Schrack-RYII RM5mm SPST-NC +0 +4 +4 +Relay_THT +Relay_1-Form-C_Schrack-RYII_RM3.2mm +Relay, 1-Form-C, Schrack-RYII, RM3.2mm, SPDT +Relay 1-Form-C Schrack-RYII RM3.2mm SPDT +0 +5 +5 +Relay_THT +Relay_DPDT_AXICOM_IMSeries_Pitch3.2mm +AXICOM IM-Series Relays, DPDR, Pitch 3.2mm, http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Specification+Or+Standard%7F108-98001%7FV%7Fpdf%7FEnglish%7FENG_SS_108-98001_V_IM_0614_v1.pdf%7F4-1462039-1 +AXICOM IM-Series Relay DPDR Pitch 3.2mm +0 +8 +8 +Relay_THT +Relay_DPDT_AXICOM_IMSeries_Pitch5.08mm +AXICOM IM-Series Relays, DPDR, Pitch 5.08 +AXICOM IM-Series Relay DPDR Pitch 5.08 +0 +8 +8 +Relay_THT +Relay_DPDT_FRT5 +IM Signal Relay DPDT FRT5 narrow footprint +Relay DPDT IM-relay FRT5 +0 +10 +10 +Relay_THT +Relay_DPDT_Finder_30.22 +Finder 32.21-x000 Relay, DPDT, https://gfinder.findernet.com/public/attachments/30/EN/S30EN.pdf +AXICOM IM-Series Relay SPDT +0 +8 +8 +Relay_THT +Relay_DPDT_Finder_40.52 +Relay DPDT Finder 40.52, Pitch 5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf +Relay DPDT Finder 40.52 Pitch 5mm +0 +8 +8 +Relay_THT +Relay_DPDT_Fujitsu_FTR-F1C +https://www.fujitsu.com/downloads/MICRO/fcai/relays/ftr-f1.pdf +relay dpdt fujitsu tht +0 +8 +8 +Relay_THT +Relay_DPDT_Omron_G5V-2 +http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5v2.pdf +Omron G5V-2 Relay DPDT +0 +8 +8 +Relay_THT +Relay_DPDT_Omron_G6H-2 +Omron relay G6H-2, see http://cdn-reichelt.de/documents/datenblatt/C300/G6H%23OMR.pdf +Omron relay G6H-2 +0 +10 +10 +Relay_THT +Relay_DPDT_Omron_G6K-2P +Omron G6K-2P relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf +Omron G6K-2P relay +0 +8 +8 +Relay_THT +Relay_DPDT_Omron_G6K-2P-Y +Omron G6K-2P-Y relay package http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6k.pdf +Omron G6K-2P-Y relay +0 +8 +8 +Relay_THT +Relay_DPDT_Omron_G6S-2 +Relay Omron G6S-2, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf +Relay Omron G6S-2 +0 +8 +8 +Relay_THT +Relay_DPDT_Omron_G6SK-2 +Relay Omron G6SK-2, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g6s.pdf +Relay Omron G6SK-2 +0 +10 +10 +Relay_THT +Relay_DPDT_Panasonic_JW2 +Panasonic Relay DPDT, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok +Panasonic Relay DPDT +0 +8 +8 +Relay_THT +Relay_DPDT_Schrack-RT2-FormC-Dual-Coil_RM5mm +Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7FRT2_bistable%7F1116%7Fpdf%7FEnglish%7FENG_DS_RT2_bistable_1116.pdf%7F1-1415537-8 +Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Relay +0 +9 +9 +Relay_THT +Relay_DPDT_Schrack-RT2-FormC_RM5mm +Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN +Relay DPDT Schrack-RT2 RM5mm 16A 250V AC Relay +0 +8 +8 +Relay_THT +Relay_DPST_Fujitsu_FTR-F1A +https://www.fujitsu.com/downloads/MICRO/fcai/relays/ftr-f1.pdf +relay dpst fujitsu tht +0 +6 +6 +Relay_THT +Relay_DPST_Schrack-RT2-FormA_RM5mm +Relay DPST Schrack-RT2 RM5mm 16A 250V AC Form A http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN +Relay DPST Schrack-RT2 RM5mm 16A 250V AC Relay +0 +6 +6 +Relay_THT +Relay_SPDT_Finder_32.21-x000 +Finder 32.21-x000 Relay, SPDT, https://gfinder.findernet.com/assets/Series/355/S32EN.pdf +AXICOM IM-Series Relay SPDT +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_34.51_Horizontal +Relay SPDT, Finder Type34.51, horizontal form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf +Relay SPDT Finder +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_34.51_Vertical +Relay SPDT, Finder Type34.51, vertical/standing form, see https://gfinder.findernet.com/public/attachments/34/EN/S34USAEN.pdf +Relay SPDT Finder +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_36.11 +FINDER 36.11, SPDT relay, 10A, https://gfinder.findernet.com/public/attachments/36/EN/S36EN.pdf +spdt relay +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_40.11 +Relay SPDT Finder 40.11, https://www.finder-relais.net/de/finder-relais-serie-40.pdf +Relay SPDT Finder 40.11 +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_40.31 +Relay DPDT Finder 40.31, Pitch 3.5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf +Relay DPDT Finder 40.31 Pitch 3.5mm +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_40.41 +Relay DPDT Finder 40.41, Pitch 3.5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf +Relay DPDT Finder 40.41 Pitch 3.5mm +0 +5 +5 +Relay_THT +Relay_SPDT_Finder_40.51 +Relay DPDT Finder 40.51, Pitch 5mm/7.5mm, https://www.finder-relais.net/de/finder-relais-serie-40.pdf +Relay DPDT Finder 40.51 Pitch 5mm +0 +5 +5 +Relay_THT +Relay_SPDT_HJR-4102 +IM Signal Relay SPDT HJR-4102 +Relay SPDT IM-relay HJR-4102 +0 +6 +6 +Relay_THT +Relay_SPDT_HsinDa_Y14 +http://www.hsinda.com.cn/en/ProductShow.asp?ID=208 +Relay Y14 +0 +6 +6 +Relay_THT +Relay_SPDT_Omron-G5LE-1 +Omron Relay SPDT, http://www.omron.com/ecb/products/pdf/en-g5le.pdf +Omron Relay SPDT +0 +5 +5 +Relay_THT +Relay_SPDT_Omron-G5Q-1 +Relay SPDT Omron Serie G5Q, http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5q.pdf +Relay SPDT Omron Serie G5Q +0 +5 +5 +Relay_THT +Relay_SPDT_Omron_G5V-1 +Relay Omron G5V-1, see http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5v_1.pdf +Relay Omron G5V-1 +0 +6 +6 +Relay_THT +Relay_SPDT_Omron_G6E +Relay SPDT Omron Serie G6E +Relay SPDT Omron Serie G6E 1x um +0 +5 +5 +Relay_THT +Relay_SPDT_Omron_G6EK +Relay SPDT Omron Serie G6EK, see http://www.logosfoundation.org/instrum_gwr/pi/Omron_G6E_134P.pdf +Relay SPDT Omron Serie G6EK +0 +6 +6 +Relay_THT +Relay_SPDT_Panasonic_JW1_FormC +Panasonic Relay SPDT, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok +Panasonic Relay SPDT +0 +5 +5 +Relay_THT +Relay_SPDT_PotterBrumfield_T9AP5D52_12V30A +Relay SPDT Potter&Brumfield T9AP5D52 12V 30A 1xUn Connector Fast ON Only Dummy for Space NO Pads +Relay SPDT Potter&Brumfield T9AP5D52 12V 30A 1xUm Connector Fast ON Flachsteckeranschluss Only Dummy for Space NO Pads +0 +0 +0 +Relay_THT +Relay_SPDT_RAYEX-L90 +https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf +Relay RAYEX L90 SPDT +0 +6 +6 +Relay_THT +Relay_SPDT_RAYEX-L90S +https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf +Relay RAYEX L90S SPDT +0 +5 +5 +Relay_THT +Relay_SPDT_SANYOU_SRD_Series_Form_C +relay Sanyou SRD series Form C http://www.sanyourelay.ca/public/products/pdf/SRD.pdf +relay Sanyu SRD form C +0 +5 +5 +Relay_THT +Relay_SPDT_Schrack-RP-II-1-16A-FormC_RM5mm +Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf +Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Relay +0 +8 +5 +Relay_THT +Relay_SPDT_Schrack-RP-II-1-FormC_RM3.5mm +Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf +Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Relay +0 +5 +5 +Relay_THT +Relay_SPDT_Schrack-RP-II-1-FormC_RM5mm +Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rp810012-b.pdf +Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Relay +0 +5 +5 +Relay_THT +Relay_SPDT_Schrack-RT1-16A-FormC_RM5mm +Relay SPST Schrack-RT1 RM5mm 16A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf +Relay SPST Schrack-RT1 RM5mm 16A 250V AC Relay +0 +8 +5 +Relay_THT +Relay_SPDT_Schrack-RT1-FormC_RM3.5mm +Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf +Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Relay +0 +5 +5 +Relay_THT +Relay_SPDT_Schrack-RT1-FormC_RM5mm +Relay SPST Schrack-RT1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf +Relay SPST Schrack-RT1 RM5mm 8A 250V AC Relay +0 +5 +5 +Relay_THT +Relay_SPDT_StandexMeder_SIL_Form1C +Standex-Meder SIL-relais, Form 1C, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf +Standex Meder SIL reed relais +0 +5 +5 +Relay_THT +Relay_SPST_Finder_32.21-x300 +Finder 32.21-x300 Relay, SPST, https://gfinder.findernet.com/assets/Series/355/S32EN.pdf +Finder 32.21-x300 Relay SPST +0 +4 +4 +Relay_THT +Relay_SPST_Omron-G5Q-1A +Relay SPST-NO Omron Serie G5Q, http://omronfs.omron.com/en_US/ecb/products/pdf/en-g5q.pdf +Relay SPST-NO Omron Serie G5Q +0 +4 +4 +Relay_THT +Relay_SPST_Panasonic_JW1_FormA +Panasonic Relay SPST, http://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_jw.pdf?via=ok +Panasonic Relay SPST +0 +4 +4 +Relay_THT +Relay_SPST_PotterBrumfield_T9AP1D52_12V30A +Relay SPST Potter&Brumfield T9AP1D52 12V 30A 1xEin Connector Fast ON Only Dummy for Space NO Pads +Relau SPST Potter&Brumfield T9AP1D52 12V 30A 1xEin Connector Fast ON Flachsteckeranschluss Only Dummy for Space NO Pads +0 +0 +0 +Relay_THT +Relay_SPST_RAYEX-L90A +https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf +Relay RAYEX L90A SPST NO +0 +5 +5 +Relay_THT +Relay_SPST_RAYEX-L90AS +https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf +Relay RAYEX L90AS SPST NO +0 +4 +4 +Relay_THT +Relay_SPST_RAYEX-L90B +https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf +Relay RAYEX L90B SPST NC +0 +5 +5 +Relay_THT +Relay_SPST_RAYEX-L90BS +https://a3.sofastcdn.com/attachment/7jioKBjnRiiSrjrjknRiwS77gwbf3zmp/L90-SERIES.pdf +Relay RAYEX L90BS SPST NC +0 +4 +4 +Relay_THT +Relay_SPST_SANYOU_SRD_Series_Form_A +relay Sanyou SRD series Form A http://www.sanyourelay.ca/public/products/pdf/SRD.pdf +relay Sanyu SRD form A +0 +4 +4 +Relay_THT +Relay_SPST_SANYOU_SRD_Series_Form_B +relay Sanyou SRD series Form B opener http://www.sanyourelay.ca/public/products/pdf/SRD.pdf +relay Sanyu SRD form B opener +0 +4 +4 +Relay_THT +Relay_SPST_Schrack-RP-II-1-16A-FormA_RM5mm +Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Form A http://image.schrack.com/datenblaetter/h_rp810012-b.pdf +Relay SPST Schrack-RP-II/1 RM5mm 16A 250V AC Relay +0 +6 +4 +Relay_THT +Relay_SPST_Schrack-RP-II-1-FormA_RM3.5mm +Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Form A +Relay SPST Schrack-RP-II/1 RM3.5mm 8A 250V AC Relay +0 +4 +4 +Relay_THT +Relay_SPST_Schrack-RP-II-1-FormA_RM5mm +Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Form A http://image.schrack.com/datenblaetter/h_rp810012-b.pdf +Relay SPST Schrack-RP-II/1 RM5mm 8A 250V AC Relay +0 +4 +4 +Relay_THT +Relay_SPST_Schrack-RP3SL-1coil_RM5mm +Relay SPST Schrack-RP3SL, 1-coil-version, RM5mm 16A 250V AC Form A http://www.alliedelec.com/m/d/543c6bed18bf23a83ae5238947033ee0.pdf +Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Relay +0 +6 +4 +Relay_THT +Relay_SPST_Schrack-RP3SL_RM5mm +Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Form A http://www.alliedelec.com/m/d/543c6bed18bf23a83ae5238947033ee0.pdf +Relay SPST Schrack-RP3SL RM5mm 16A 250V AC Relay +0 +7 +5 +Relay_THT +Relay_SPST_Schrack-RT1-16A-FormA_RM5mm +Relay SPST Schrack-RT2 RM5mm 16A 250V AC Form C http://www.te.com/commerce/DocumentDelivery/DDEController?Action=srchrtrv&DocNm=RT2_reflow&DocType=DS&DocLang=EN +Relay SPST Schrack-RT2 RM5mm 16A 250V AC Relay +0 +6 +4 +Relay_THT +Relay_SPST_Schrack-RT1-FormA_RM3.5mm +Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Form A +Relay SPST Schrack-RT1 RM3.5mm 8A 250V AC Relay +0 +4 +4 +Relay_THT +Relay_SPST_Schrack-RT1-FormA_RM5mm +Relay SPST Schrack-RT1 RM5mm 8A 250V AC Form C http://image.schrack.com/datenblaetter/h_rt114012--_de.pdf +Relay SPST Schrack-RT1 RM5mm 8A 250V AC Relay +0 +4 +4 +Relay_THT +Relay_SPST_StandexMeder_MS_Form1AB +Standex-Meder MS SIL-relais, Form 1A/1B, see https://standexelectronics.com/de/produkte/ms-reed-relais/ +Standex Meder MS SIL reed relais +0 +4 +4 +Relay_THT +Relay_SPST_StandexMeder_SIL_Form1A +Standex-Meder SIL-relais, Form 1A, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf +Standex Meder SIL reed relais +0 +4 +4 +Relay_THT +Relay_SPST_StandexMeder_SIL_Form1B +Standex-Meder SIL-relais, Form 1B, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_SIL.pdf +Standex Meder SIL reed relais +0 +4 +4 +Relay_THT +Relay_SPST_TE_PCH-1xxx2M +Miniature PCB Relay, PCH Series, 1 Form A (NO), SPST http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Data+Sheet%7FPCH_series_relay_data_sheet_E%7F1215%7Fpdf%7FEnglish%7FENG_DS_PCH_series_relay_data_sheet_E_1215.pdf +Relay SPST NO +0 +4 +4 +Relay_THT +Relay_SPST_TE_PCN-1xxD3MHZ +https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F1461491%7FG2%7Fpdf%7FEnglish%7FENG_CD_1461491_G2.pdf%7F3-1461491-0 +SPST relay slim +0 +4 +4 +Relay_THT +Relay_Socket_DPDT_Finder_96.12 +https://gfinder.findernet.com/public/attachments/56/DE/S56DE.pdf +Relay socket DPDT Finder 96.12 56.32 +0 +8 +8 +Relay_THT +Relay_StandexMeder_DIP_HighProfile +package for Standex Meder DIP reed relay series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf +DIL DIP PDIP 2.54mm 7.62mm 300mil reed relay +0 +8 +8 +Relay_THT +Relay_StandexMeder_DIP_LowProfile +package for Standex Meder DIP reed relay series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf +DIL DIP PDIP 2.54mm 7.62mm 300mil reed relay +0 +8 +8 +Relay_THT +Relay_StandexMeder_UMS +Standex-Meder SIL-relais, UMS, see http://cdn-reichelt.de/documents/datenblatt/C300/UMS05_1A80_75L_DB.pdf +Standex Meder SIL reed relais +0 +4 +4 +Resistor_SMD +R_0201_0603Metric +Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +resistor +0 +4 +2 +Resistor_SMD +R_0402_1005Metric +Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_0603_1608Metric +Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_0603_1608Metric_Pad1.05x0.95mm_HandSolder +Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_0612_1632Metric +Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_0612_1632Metric_Pad1.18x3.40mm_HandSolder +Resistor SMD 0612 (1632 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_0805_2012Metric +Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_0805_2012Metric_Pad1.15x1.40mm_HandSolder +Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_0815_2038Metric +Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.yageo.com/documents/recent/PYu-PRPFPH_521_RoHS_L_0.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_0815_2038Metric_Pad1.53x4.00mm_HandSolder +Resistor SMD 0815 (2038 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.yageo.com/documents/recent/PYu-PRPFPH_521_RoHS_L_0.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_01005_0402Metric +Resistor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +resistor +0 +4 +2 +Resistor_SMD +R_1020_2550Metric +Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_1020_2550Metric_Pad1.33x5.20mm_HandSolder +Resistor SMD 1020 (2550 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20019/rcwe.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_1206_3216Metric +Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_1206_3216Metric_Pad1.42x1.75mm_HandSolder +Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_1210_3225Metric +Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_1210_3225Metric_Pad1.42x2.65mm_HandSolder +Resistor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_1218_3246Metric +Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_1218_3246Metric_Pad1.22x4.75mm_HandSolder +Resistor SMD 1218 (3246 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20035/dcrcwe3.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_1806_4516Metric +Resistor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_1806_4516Metric_Pad1.57x1.80mm_HandSolder +Resistor SMD 1806 (4516 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.modelithics.com/models/Vendor/MuRata/BLM41P.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_1812_4532Metric +Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_1812_4532Metric_Pad1.30x3.40mm_HandSolder +Resistor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.nikhef.nl/pub/departments/mt/projects/detectorR_D/dtddice/ERJ2G.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_2010_5025Metric +Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_2010_5025Metric_Pad1.52x2.65mm_HandSolder +Resistor SMD 2010 (5025 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_2512_6332Metric +Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_2512_6332Metric_Pad1.52x3.35mm_HandSolder +Resistor SMD 2512 (6332 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_2816_7142Metric +Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_2816_7142Metric_Pad3.20x4.45mm_HandSolder +Resistor SMD 2816 (7142 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: https://www.vishay.com/docs/30100/wsl.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_4020_10251Metric +Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator +resistor +0 +2 +2 +Resistor_SMD +R_4020_10251Metric_Pad1.65x5.30mm_HandSolder +Resistor SMD 4020 (10251 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://datasheet.octopart.com/HVC0603T5004FET-Ohmite-datasheet-26699797.pdf), generated with kicad-footprint-generator +resistor handsolder +0 +2 +2 +Resistor_SMD +R_Array_Concave_2x0603 +Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf) +resistor array +0 +4 +4 +Resistor_SMD +R_Array_Concave_4x0402 +Thick Film Chip Resistor Array, Wave soldering, Vishay CRA04P (see cra04p.pdf) +resistor array +0 +8 +8 +Resistor_SMD +R_Array_Concave_4x0603 +Thick Film Chip Resistor Array, Wave soldering, Vishay CRA06P (see cra06p.pdf) +resistor array +0 +8 +8 +Resistor_SMD +R_Array_Convex_2x0402 +Chip Resistor Network, ROHM MNR02 (see mnr_g.pdf) +resistor array +0 +4 +4 +Resistor_SMD +R_Array_Convex_2x0603 +Chip Resistor Network, ROHM MNR12 (see mnr_g.pdf) +resistor array +0 +4 +4 +Resistor_SMD +R_Array_Convex_2x0606 +Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf) +resistor array +0 +4 +4 +Resistor_SMD +R_Array_Convex_2x1206 +Chip Resistor Network, ROHM MNR32 (see mnr_g.pdf) +resistor array +0 +4 +4 +Resistor_SMD +R_Array_Convex_4x0402 +Chip Resistor Network, ROHM MNR04 (see mnr_g.pdf) +resistor array +0 +8 +8 +Resistor_SMD +R_Array_Convex_4x0603 +Chip Resistor Network, ROHM MNR14 (see mnr_g.pdf) +resistor array +0 +8 +8 +Resistor_SMD +R_Array_Convex_4x0612 +Precision Thin Film Chip Resistor Array, VISHAY (see http://www.vishay.com/docs/28770/acasat.pdf) +resistor array +0 +8 +8 +Resistor_SMD +R_Array_Convex_4x1206 +Chip Resistor Network, ROHM MNR34 (see mnr_g.pdf) +resistor array +0 +8 +8 +Resistor_SMD +R_Array_Convex_5x0603 +Chip Resistor Network, ROHM MNR15 (see mnr_g.pdf) +resistor array +0 +10 +10 +Resistor_SMD +R_Array_Convex_5x1206 +Chip Resistor Network, ROHM MNR35 (see mnr_g.pdf) +resistor array +0 +10 +10 +Resistor_SMD +R_Array_Convex_8x0602 +Chip Resistor Network, ROHM MNR18 (see mnr_g.pdf) +resistor array +0 +16 +16 +Resistor_SMD +R_Cat16-2 +SMT resistor net, Bourns CAT16 series, 2 way +SMT resistor net Bourns CAT16 series 2 way +0 +4 +4 +Resistor_SMD +R_Cat16-4 +SMT resistor net, Bourns CAT16 series, 4 way +SMT resistor net Bourns CAT16 series 4 way +0 +8 +8 +Resistor_SMD +R_Cat16-8 +SMT resistor net, Bourns CAT16 series, 8 way +SMT resistor net Bourns CAT16 series 8 way +0 +16 +16 +Resistor_SMD +R_MELF_MMB-0207 +Resistor, MELF, MMB-0207, http://www.vishay.com/docs/28713/melfprof.pdf +MELF Resistor +0 +2 +2 +Resistor_SMD +R_MicroMELF_MMU-0102 +Resistor, MicroMELF, MMU-0102, http://www.vishay.com/docs/28713/melfprof.pdf +MicroMELF Resistor +0 +2 +2 +Resistor_SMD +R_MiniMELF_MMA-0204 +Resistor, MiniMELF, MMA-0204, http://www.vishay.com/docs/28713/melfprof.pdf +MiniMELF Resistor +0 +2 +2 +Resistor_SMD +R_Shunt_Ohmite_LVK12 +4 contact shunt resistor +shunt resistor 4 contacts +0 +4 +4 +Resistor_SMD +R_Shunt_Ohmite_LVK20 +4 contacts shunt resistor, https://www.ohmite.com/assets/docs/res_lvk.pdf +4 contacts resistor smd +0 +4 +4 +Resistor_SMD +R_Shunt_Ohmite_LVK24 +4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf +4 contacts resistor smd +0 +4 +4 +Resistor_SMD +R_Shunt_Ohmite_LVK25 +4 contacts shunt resistor,https://www.ohmite.com/assets/docs/res_lvk.pdf +4 contacts resistor smd +0 +4 +4 +Resistor_SMD +R_Shunt_Vishay_WSK2512_6332Metric_T1.19mm +Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 1.19mm, 5 to 200 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf) +resistor shunt WSK2512 +0 +4 +4 +Resistor_SMD +R_Shunt_Vishay_WSK2512_6332Metric_T2.21mm +Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.21mm, 1 to 4.9 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf) +resistor shunt WSK2512 +0 +4 +4 +Resistor_SMD +R_Shunt_Vishay_WSK2512_6332Metric_T2.66mm +Shunt Resistor SMD 2512 (6332 Metric), 2.6mm thick, Vishay WKS2512, Terminal length (T) 2.66mm, 0.5 to 0.99 milli Ohm (http://http://www.vishay.com/docs/30108/wsk.pdf) +resistor shunt WSK2512 +0 +4 +4 +Resistor_SMD +R_Shunt_Vishay_WSKW0612 +https://www.vishay.com/docs/30332/wskw0612.pdf +4-Terminal SMD Shunt +0 +4 +4 +Resistor_SMD +R_Shunt_Vishay_WSR2_WSR3 +Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf +SMD Shunt Resistor +0 +2 +2 +Resistor_SMD +R_Shunt_Vishay_WSR2_WSR3_KelvinConnection +Power Metal Strip Resistors 0.005 to 0.2, https://www.vishay.com/docs/30101/wsr.pdf +SMD Shunt Resistor +0 +4 +2 +Resistor_THT +R_Array_SIP4 +4-pin Resistor SIP pack +R +0 +4 +4 +Resistor_THT +R_Array_SIP5 +5-pin Resistor SIP pack +R +0 +5 +5 +Resistor_THT +R_Array_SIP6 +6-pin Resistor SIP pack +R +0 +6 +6 +Resistor_THT +R_Array_SIP7 +7-pin Resistor SIP pack +R +0 +7 +7 +Resistor_THT +R_Array_SIP8 +8-pin Resistor SIP pack +R +0 +8 +8 +Resistor_THT +R_Array_SIP9 +9-pin Resistor SIP pack +R +0 +9 +9 +Resistor_THT +R_Array_SIP10 +10-pin Resistor SIP pack +R +0 +10 +10 +Resistor_THT +R_Array_SIP11 +11-pin Resistor SIP pack +R +0 +11 +11 +Resistor_THT +R_Array_SIP12 +12-pin Resistor SIP pack +R +0 +12 +12 +Resistor_THT +R_Array_SIP13 +13-pin Resistor SIP pack +R +0 +13 +13 +Resistor_THT +R_Array_SIP14 +14-pin Resistor SIP pack +R +0 +14 +14 +Resistor_THT +R_Axial_DIN0204_L3.6mm_D1.6mm_P1.90mm_Vertical +Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=1.9mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0204 series Axial Vertical pin pitch 1.9mm 0.167W length 3.6mm diameter 1.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0204_L3.6mm_D1.6mm_P2.54mm_Vertical +Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=2.54mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0204 series Axial Vertical pin pitch 2.54mm 0.167W length 3.6mm diameter 1.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal +Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0204 series Axial Horizontal pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Vertical +Resistor, Axial_DIN0204 series, Axial, Vertical, pin pitch=5.08mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0204 series Axial Vertical pin pitch 5.08mm 0.167W length 3.6mm diameter 1.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0204_L3.6mm_D1.6mm_P7.62mm_Horizontal +Resistor, Axial_DIN0204 series, Axial, Horizontal, pin pitch=7.62mm, 0.167W, length*diameter=3.6*1.6mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0204 series Axial Horizontal pin pitch 7.62mm 0.167W length 3.6mm diameter 1.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical +Resistor, Axial_DIN0207 series, Axial, Vertical, pin pitch=2.54mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0207 series Axial Vertical pin pitch 2.54mm 0.25W = 1/4W length 6.3mm diameter 2.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0207_L6.3mm_D2.5mm_P5.08mm_Vertical +Resistor, Axial_DIN0207 series, Axial, Vertical, pin pitch=5.08mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0207 series Axial Vertical pin pitch 5.08mm 0.25W = 1/4W length 6.3mm diameter 2.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal +Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=7.62mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0207 series Axial Horizontal pin pitch 7.62mm 0.25W = 1/4W length 6.3mm diameter 2.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal +Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0207_L6.3mm_D2.5mm_P15.24mm_Horizontal +Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=15.24mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0207 series Axial Horizontal pin pitch 15.24mm 0.25W = 1/4W length 6.3mm diameter 2.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0309_L9.0mm_D3.2mm_P2.54mm_Vertical +Resistor, Axial_DIN0309 series, Axial, Vertical, pin pitch=2.54mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0309 series Axial Vertical pin pitch 2.54mm 0.5W = 1/2W length 9mm diameter 3.2mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0309_L9.0mm_D3.2mm_P5.08mm_Vertical +Resistor, Axial_DIN0309 series, Axial, Vertical, pin pitch=5.08mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0309 series Axial Vertical pin pitch 5.08mm 0.5W = 1/2W length 9mm diameter 3.2mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal +Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=12.7mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0309 series Axial Horizontal pin pitch 12.7mm 0.5W = 1/2W length 9mm diameter 3.2mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0309_L9.0mm_D3.2mm_P15.24mm_Horizontal +Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=15.24mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0309 series Axial Horizontal pin pitch 15.24mm 0.5W = 1/2W length 9mm diameter 3.2mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0309_L9.0mm_D3.2mm_P20.32mm_Horizontal +Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=20.32mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0309 series Axial Horizontal pin pitch 20.32mm 0.5W = 1/2W length 9mm diameter 3.2mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0309_L9.0mm_D3.2mm_P25.40mm_Horizontal +Resistor, Axial_DIN0309 series, Axial, Horizontal, pin pitch=25.4mm, 0.5W = 1/2W, length*diameter=9*3.2mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0309 series Axial Horizontal pin pitch 25.4mm 0.5W = 1/2W length 9mm diameter 3.2mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0411_L9.9mm_D3.6mm_P5.08mm_Vertical +Resistor, Axial_DIN0411 series, Axial, Vertical, pin pitch=5.08mm, 1W, length*diameter=9.9*3.6mm^2 +Resistor Axial_DIN0411 series Axial Vertical pin pitch 5.08mm 1W length 9.9mm diameter 3.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0411_L9.9mm_D3.6mm_P7.62mm_Vertical +Resistor, Axial_DIN0411 series, Axial, Vertical, pin pitch=7.62mm, 1W, length*diameter=9.9*3.6mm^2 +Resistor Axial_DIN0411 series Axial Vertical pin pitch 7.62mm 1W length 9.9mm diameter 3.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0411_L9.9mm_D3.6mm_P12.70mm_Horizontal +Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=12.7mm, 1W, length*diameter=9.9*3.6mm^2 +Resistor Axial_DIN0411 series Axial Horizontal pin pitch 12.7mm 1W length 9.9mm diameter 3.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0411_L9.9mm_D3.6mm_P15.24mm_Horizontal +Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=15.24mm, 1W, length*diameter=9.9*3.6mm^2 +Resistor Axial_DIN0411 series Axial Horizontal pin pitch 15.24mm 1W length 9.9mm diameter 3.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0411_L9.9mm_D3.6mm_P20.32mm_Horizontal +Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=20.32mm, 1W, length*diameter=9.9*3.6mm^2 +Resistor Axial_DIN0411 series Axial Horizontal pin pitch 20.32mm 1W length 9.9mm diameter 3.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0411_L9.9mm_D3.6mm_P25.40mm_Horizontal +Resistor, Axial_DIN0411 series, Axial, Horizontal, pin pitch=25.4mm, 1W, length*diameter=9.9*3.6mm^2 +Resistor Axial_DIN0411 series Axial Horizontal pin pitch 25.4mm 1W length 9.9mm diameter 3.6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0414_L11.9mm_D4.5mm_P5.08mm_Vertical +Resistor, Axial_DIN0414 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0414 series Axial Vertical pin pitch 5.08mm 2W length 11.9mm diameter 4.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0414_L11.9mm_D4.5mm_P7.62mm_Vertical +Resistor, Axial_DIN0414 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0414 series Axial Vertical pin pitch 7.62mm 2W length 11.9mm diameter 4.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0414_L11.9mm_D4.5mm_P15.24mm_Horizontal +Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=15.24mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0414 series Axial Horizontal pin pitch 15.24mm 2W length 11.9mm diameter 4.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0414_L11.9mm_D4.5mm_P20.32mm_Horizontal +Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0414 series Axial Horizontal pin pitch 20.32mm 2W length 11.9mm diameter 4.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0414_L11.9mm_D4.5mm_P25.40mm_Horizontal +Resistor, Axial_DIN0414 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=11.9*4.5mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0414 series Axial Horizontal pin pitch 25.4mm 2W length 11.9mm diameter 4.5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0516_L15.5mm_D5.0mm_P5.08mm_Vertical +Resistor, Axial_DIN0516 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0516 series Axial Vertical pin pitch 5.08mm 2W length 15.5mm diameter 5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0516_L15.5mm_D5.0mm_P7.62mm_Vertical +Resistor, Axial_DIN0516 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0516 series Axial Vertical pin pitch 7.62mm 2W length 15.5mm diameter 5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0516_L15.5mm_D5.0mm_P20.32mm_Horizontal +Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0516 series Axial Horizontal pin pitch 20.32mm 2W length 15.5mm diameter 5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0516_L15.5mm_D5.0mm_P25.40mm_Horizontal +Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0516 series Axial Horizontal pin pitch 25.4mm 2W length 15.5mm diameter 5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0516_L15.5mm_D5.0mm_P30.48mm_Horizontal +Resistor, Axial_DIN0516 series, Axial, Horizontal, pin pitch=30.48mm, 2W, length*diameter=15.5*5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf +Resistor Axial_DIN0516 series Axial Horizontal pin pitch 30.48mm 2W length 15.5mm diameter 5mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0614_L14.3mm_D5.7mm_P5.08mm_Vertical +Resistor, Axial_DIN0614 series, Axial, Vertical, pin pitch=5.08mm, 1.5W, length*diameter=14.3*5.7mm^2 +Resistor Axial_DIN0614 series Axial Vertical pin pitch 5.08mm 1.5W length 14.3mm diameter 5.7mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0614_L14.3mm_D5.7mm_P7.62mm_Vertical +Resistor, Axial_DIN0614 series, Axial, Vertical, pin pitch=7.62mm, 1.5W, length*diameter=14.3*5.7mm^2 +Resistor Axial_DIN0614 series Axial Vertical pin pitch 7.62mm 1.5W length 14.3mm diameter 5.7mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0614_L14.3mm_D5.7mm_P15.24mm_Horizontal +Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=15.24mm, 1.5W, length*diameter=14.3*5.7mm^2 +Resistor Axial_DIN0614 series Axial Horizontal pin pitch 15.24mm 1.5W length 14.3mm diameter 5.7mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0614_L14.3mm_D5.7mm_P20.32mm_Horizontal +Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=20.32mm, 1.5W, length*diameter=14.3*5.7mm^2 +Resistor Axial_DIN0614 series Axial Horizontal pin pitch 20.32mm 1.5W length 14.3mm diameter 5.7mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0614_L14.3mm_D5.7mm_P25.40mm_Horizontal +Resistor, Axial_DIN0614 series, Axial, Horizontal, pin pitch=25.4mm, 1.5W, length*diameter=14.3*5.7mm^2 +Resistor Axial_DIN0614 series Axial Horizontal pin pitch 25.4mm 1.5W length 14.3mm diameter 5.7mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0617_L17.0mm_D6.0mm_P5.08mm_Vertical +Resistor, Axial_DIN0617 series, Axial, Vertical, pin pitch=5.08mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0617 series Axial Vertical pin pitch 5.08mm 2W length 17mm diameter 6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0617_L17.0mm_D6.0mm_P7.62mm_Vertical +Resistor, Axial_DIN0617 series, Axial, Vertical, pin pitch=7.62mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0617 series Axial Vertical pin pitch 7.62mm 2W length 17mm diameter 6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal +Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0617 series Axial Horizontal pin pitch 20.32mm 2W length 17mm diameter 6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0617_L17.0mm_D6.0mm_P25.40mm_Horizontal +Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=25.4mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0617 series Axial Horizontal pin pitch 25.4mm 2W length 17mm diameter 6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0617_L17.0mm_D6.0mm_P30.48mm_Horizontal +Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=30.48mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0617 series Axial Horizontal pin pitch 30.48mm 2W length 17mm diameter 6mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0918_L18.0mm_D9.0mm_P7.62mm_Vertical +Resistor, Axial_DIN0918 series, Axial, Vertical, pin pitch=7.62mm, 4W, length*diameter=18*9mm^2 +Resistor Axial_DIN0918 series Axial Vertical pin pitch 7.62mm 4W length 18mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0918_L18.0mm_D9.0mm_P22.86mm_Horizontal +Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=22.86mm, 4W, length*diameter=18*9mm^2 +Resistor Axial_DIN0918 series Axial Horizontal pin pitch 22.86mm 4W length 18mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0918_L18.0mm_D9.0mm_P25.40mm_Horizontal +Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=25.4mm, 4W, length*diameter=18*9mm^2 +Resistor Axial_DIN0918 series Axial Horizontal pin pitch 25.4mm 4W length 18mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0918_L18.0mm_D9.0mm_P30.48mm_Horizontal +Resistor, Axial_DIN0918 series, Axial, Horizontal, pin pitch=30.48mm, 4W, length*diameter=18*9mm^2 +Resistor Axial_DIN0918 series Axial Horizontal pin pitch 30.48mm 4W length 18mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0922_L20.0mm_D9.0mm_P7.62mm_Vertical +Resistor, Axial_DIN0922 series, Axial, Vertical, pin pitch=7.62mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0922 series Axial Vertical pin pitch 7.62mm 5W length 20mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0922_L20.0mm_D9.0mm_P25.40mm_Horizontal +Resistor, Axial_DIN0922 series, Axial, Horizontal, pin pitch=25.4mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0922 series Axial Horizontal pin pitch 25.4mm 5W length 20mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_DIN0922_L20.0mm_D9.0mm_P30.48mm_Horizontal +Resistor, Axial_DIN0922 series, Axial, Horizontal, pin pitch=30.48mm, 5W, length*diameter=20*9mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf +Resistor Axial_DIN0922 series Axial Horizontal pin pitch 30.48mm 5W length 20mm diameter 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L20.0mm_W6.4mm_P5.08mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=5.08mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 5.08mm 4W length 20mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L20.0mm_W6.4mm_P7.62mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 4W length 20mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L20.0mm_W6.4mm_P22.40mm +Resistor, Axial_Power series, Box, pin pitch=22.4mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 22.4mm 4W length 20mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L20.0mm_W6.4mm_P25.40mm +Resistor, Axial_Power series, Box, pin pitch=25.4mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 25.4mm 4W length 20mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L20.0mm_W6.4mm_P30.48mm +Resistor, Axial_Power series, Box, pin pitch=30.48mm, 4W, length*width*height=20*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 30.48mm 4W length 20mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L25.0mm_W6.4mm_P27.94mm +Resistor, Axial_Power series, Box, pin pitch=27.94mm, 5W, length*width*height=25*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 27.94mm 5W length 25mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L25.0mm_W6.4mm_P30.48mm +Resistor, Axial_Power series, Box, pin pitch=30.48mm, 5W, length*width*height=25*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 30.48mm 5W length 25mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L25.0mm_W9.0mm_P7.62mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 7W length 25mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L25.0mm_W9.0mm_P10.16mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 7W length 25mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L25.0mm_W9.0mm_P27.94mm +Resistor, Axial_Power series, Box, pin pitch=27.94mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 27.94mm 7W length 25mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L25.0mm_W9.0mm_P30.48mm +Resistor, Axial_Power series, Box, pin pitch=30.48mm, 7W, length*width*height=25*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 30.48mm 7W length 25mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L38.0mm_W6.4mm_P40.64mm +Resistor, Axial_Power series, Box, pin pitch=40.64mm, 7W, length*width*height=38*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 40.64mm 7W length 38mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L38.0mm_W6.4mm_P45.72mm +Resistor, Axial_Power series, Box, pin pitch=45.72mm, 7W, length*width*height=38*6.4*6.4mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 45.72mm 7W length 38mm width 6.4mm height 6.4mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L38.0mm_W9.0mm_P40.64mm +Resistor, Axial_Power series, Box, pin pitch=40.64mm, 9W, length*width*height=38*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 40.64mm 9W length 38mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L38.0mm_W9.0mm_P45.72mm +Resistor, Axial_Power series, Box, pin pitch=45.72mm, 9W, length*width*height=38*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 45.72mm 9W length 38mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L48.0mm_W12.5mm_P7.62mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=7.62mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 7.62mm 15W length 48mm width 12.5mm height 12.5mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L48.0mm_W12.5mm_P10.16mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 15W length 48mm width 12.5mm height 12.5mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L48.0mm_W12.5mm_P55.88mm +Resistor, Axial_Power series, Box, pin pitch=55.88mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 55.88mm 15W length 48mm width 12.5mm height 12.5mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L48.0mm_W12.5mm_P60.96mm +Resistor, Axial_Power series, Box, pin pitch=60.96mm, 15W, length*width*height=48*12.5*12.5mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 60.96mm 15W length 48mm width 12.5mm height 12.5mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L50.0mm_W9.0mm_P55.88mm +Resistor, Axial_Power series, Box, pin pitch=55.88mm, 11W, length*width*height=50*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 55.88mm 11W length 50mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L50.0mm_W9.0mm_P60.96mm +Resistor, Axial_Power series, Box, pin pitch=60.96mm, 11W, length*width*height=50*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 60.96mm 11W length 50mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L60.0mm_W14.0mm_P10.16mm_Vertical +Resistor, Axial_Power series, Axial, Vertical, pin pitch=10.16mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Axial Vertical pin pitch 10.16mm 25W length 60mm width 14mm height 14mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L60.0mm_W14.0mm_P66.04mm +Resistor, Axial_Power series, Box, pin pitch=66.04mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 66.04mm 25W length 60mm width 14mm height 14mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L60.0mm_W14.0mm_P71.12mm +Resistor, Axial_Power series, Box, pin pitch=71.12mm, 25W, length*width*height=60*14*14mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 71.12mm 25W length 60mm width 14mm height 14mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L75.0mm_W9.0mm_P81.28mm +Resistor, Axial_Power series, Box, pin pitch=81.28mm, 17W, length*width*height=75*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 81.28mm 17W length 75mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Power_L75.0mm_W9.0mm_P86.36mm +Resistor, Axial_Power series, Box, pin pitch=86.36mm, 17W, length*width*height=75*9*9mm^3, http://cdn-reichelt.de/documents/datenblatt/B400/5WAXIAL_9WAXIAL_11WAXIAL_17WAXIAL%23YAG.pdf +Resistor Axial_Power series Box pin pitch 86.36mm 17W length 75mm width 9mm height 9mm +0 +2 +2 +Resistor_THT +R_Axial_Shunt_L22.2mm_W8.0mm_PS14.30mm_P25.40mm +Resistor, Axial_Shunt series, Box, pin pitch=25.4mm, 3W, length*width*height=22.2*8*8mm^3, shunt pin pitch = 14.30mm, http://www.vishay.com/docs/30217/cpsl.pdf +Resistor Axial_Shunt series Box pin pitch 25.4mm 3W length 22.2mm width 8mm height 8mm shunt pin pitch 14.30mm +0 +4 +4 +Resistor_THT +R_Axial_Shunt_L22.2mm_W9.5mm_PS14.30mm_P25.40mm +Resistor, Axial_Shunt series, Box, pin pitch=25.4mm, 5W, length*width*height=22.2*9.5*9.5mm^3, shunt pin pitch = 14.30mm, http://www.vishay.com/docs/30217/cpsl.pdf +Resistor Axial_Shunt series Box pin pitch 25.4mm 5W length 22.2mm width 9.5mm height 9.5mm shunt pin pitch 14.30mm +0 +4 +4 +Resistor_THT +R_Axial_Shunt_L35.3mm_W9.5mm_PS25.40mm_P38.10mm +Resistor, Axial_Shunt series, Box, pin pitch=38.1mm, 7W, length*width*height=35.3*9.5*9.5mm^3, shunt pin pitch = 25.40mm, http://www.vishay.com/docs/30217/cpsl.pdf +Resistor Axial_Shunt series Box pin pitch 38.1mm 7W length 35.3mm width 9.5mm height 9.5mm shunt pin pitch 25.40mm +0 +4 +4 +Resistor_THT +R_Axial_Shunt_L47.6mm_W9.5mm_PS34.93mm_P50.80mm +Resistor, Axial_Shunt series, Box, pin pitch=50.8mm, 10W, length*width*height=47.6*9.5*9.5mm^3, shunt pin pitch = 34.93mm, http://www.vishay.com/docs/30217/cpsl.pdf +Resistor Axial_Shunt series Box pin pitch 50.8mm 10W length 47.6mm width 9.5mm height 9.5mm shunt pin pitch 34.93mm +0 +4 +4 +Resistor_THT +R_Axial_Shunt_L47.6mm_W12.7mm_PS34.93mm_P50.80mm +Resistor, Axial_Shunt series, Box, pin pitch=50.8mm, 15W, length*width*height=47.6*12.7*12.7mm^3, shunt pin pitch = 34.93mm, http://www.vishay.com/docs/30217/cpsl.pdf +Resistor Axial_Shunt series Box pin pitch 50.8mm 15W length 47.6mm width 12.7mm height 12.7mm shunt pin pitch 34.93mm +0 +4 +4 +Resistor_THT +R_Bare_Metal_Element_L12.4mm_W4.8mm_P11.40mm +Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=11.4mm, 1W, length*width=12.4*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf +Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 11.4mm 1W length 12.4mm width 4.8mm +0 +2 +2 +Resistor_THT +R_Bare_Metal_Element_L16.3mm_W4.8mm_P15.30mm +Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=15.3mm, 3W, length*width=16.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf +Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 15.3mm 3W length 16.3mm width 4.8mm +0 +2 +2 +Resistor_THT +R_Bare_Metal_Element_L21.3mm_W4.8mm_P20.30mm +Resistor, Bare_Metal_Element series, Bare Metal Strip/Wire, Horizontal, pin pitch=20.3mm, 5W, length*width=21.3*4.8mm^2, https://www.bourns.com/pdfs/PWR4412-2S.pdf +Resistor Bare_Metal_Element series Bare Metal Strip Wire Horizontal pin pitch 20.3mm 5W length 21.3mm width 4.8mm +0 +2 +2 +Resistor_THT +R_Box_L8.4mm_W2.5mm_P5.08mm +Resistor, Box series, Radial, pin pitch=5.08mm, 0.5W = 1/2W, length*width=8.38*2.54mm^2, http://www.vishay.com/docs/60051/cns020.pdf +Resistor Box series Radial pin pitch 5.08mm 0.5W = 1/2W length 8.38mm width 2.54mm +0 +2 +2 +Resistor_THT +R_Box_L13.0mm_W4.0mm_P9.00mm +Resistor, Box series, Radial, pin pitch=9.00mm, 2W, length*width=13.0*4.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf +Resistor Box series Radial pin pitch 9.00mm 2W length 13.0mm width 4.0mm +0 +2 +2 +Resistor_THT +R_Box_L14.0mm_W5.0mm_P9.00mm +Resistor, Box series, Radial, pin pitch=9.00mm, 5W, length*width=14.0*5.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf +Resistor Box series Radial pin pitch 9.00mm 5W length 14.0mm width 5.0mm +0 +2 +2 +Resistor_THT +R_Box_L26.0mm_W5.0mm_P20.00mm +Resistor, Box series, Radial, pin pitch=20.00mm, 10W, length*width=26.0*5.0mm^2, http://www.produktinfo.conrad.com/datenblaetter/425000-449999/443860-da-01-de-METALLBAND_WIDERSTAND_0_1_OHM_5W_5Pr.pdf +Resistor Box series Radial pin pitch 20.00mm 10W length 26.0mm width 5.0mm +0 +2 +2 +Resistor_THT +R_Radial_Power_L7.0mm_W8.0mm_Px2.40mm_Py2.30mm +Resistor, Radial_Power series, Radial, pin pitch=2.40*2.30mm^2, 7W, length*width=7*8mm^2, http://www.vitrohm.com/content/files/vitrohm_series_kv_-_201601.pdf +Resistor Radial_Power series Radial pin pitch 2.40*2.30mm^2 7W length 7mm width 8mm +0 +2 +2 +Resistor_THT +R_Radial_Power_L9.0mm_W10.0mm_Px2.70mm_Py2.30mm +Resistor, Radial_Power series, Radial, pin pitch=2.70*2.30mm^2, 17W, length*width=9*10mm^2, http://www.vitrohm.com/content/files/vitrohm_series_kv_-_201601.pdf +Resistor Radial_Power series Radial pin pitch 2.70*2.30mm^2 17W length 9mm width 10mm +0 +2 +2 +Resistor_THT +R_Radial_Power_L11.0mm_W7.0mm_P5.00mm +Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 2W, length*width=11.0*7.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf +Resistor Radial_Power series Radial pin pitch 5.00mm 2W length 11.0mm width 7.0mm +0 +2 +2 +Resistor_THT +R_Radial_Power_L12.0mm_W8.0mm_P5.00mm +Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 3W, length*width=12.0*8.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf +Resistor Radial_Power series Radial pin pitch 5.00mm 3W length 12.0mm width 8.0mm +0 +2 +2 +Resistor_THT +R_Radial_Power_L13.0mm_W9.0mm_P5.00mm +Resistor, Radial_Power series, Radial, pin pitch=5.00mm, 7W, length*width=13.0*9.0mm^2, http://www.vishay.com/docs/30218/cpcx.pdf +Resistor Radial_Power series Radial pin pitch 5.00mm 7W length 13.0mm width 9.0mm +0 +2 +2 +Resistor_THT +R_Radial_Power_L16.1mm_W9.0mm_P7.37mm +Resistor, Radial_Power series, Radial, pin pitch=7.37mm, 10W, length*width=16.1*9mm^2, http://www.vishay.com/docs/30218/cpcx.pdf +Resistor Radial_Power series Radial pin pitch 7.37mm 10W length 16.1mm width 9mm +0 +2 +2 +Rotary_Encoder +RotaryEncoder_Alps_EC11E-Switch_Vertical_H20mm +Alps rotary encoder, EC12E... with switch, vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html +rotary encoder +0 +7 +6 +Rotary_Encoder +RotaryEncoder_Alps_EC11E-Switch_Vertical_H20mm_CircularMountingHoles +Alps rotary encoder, EC12E... with switch, vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html +rotary encoder +0 +7 +6 +Rotary_Encoder +RotaryEncoder_Alps_EC11E_Vertical_H20mm +Alps rotary encoder, EC12E... without switch (pins are dummy), vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html +rotary encoder +0 +7 +4 +Rotary_Encoder +RotaryEncoder_Alps_EC11E_Vertical_H20mm_CircularMountingHoles +Alps rotary encoder, EC12E... without switch (pins are dummy), vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC11/EC11E15204A3.html +rotary encoder +0 +7 +4 +Rotary_Encoder +RotaryEncoder_Alps_EC12E-Switch_Vertical_H20mm +Alps rotary encoder, EC12E... with switch, vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html & http://cdn-reichelt.de/documents/datenblatt/F100/402097STEC12E08.PDF +rotary encoder +0 +7 +6 +Rotary_Encoder +RotaryEncoder_Alps_EC12E-Switch_Vertical_H20mm_CircularMountingHoles +Alps rotary encoder, EC12E... with switch, vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html & http://cdn-reichelt.de/documents/datenblatt/F100/402097STEC12E08.PDF +rotary encoder +0 +7 +6 +Rotary_Encoder +RotaryEncoder_Alps_EC12E_Vertical_H20mm +Alps rotary encoder, EC12E..., vertical shaft, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html +rotary encoder +0 +5 +4 +Rotary_Encoder +RotaryEncoder_Alps_EC12E_Vertical_H20mm_CircularMountingHoles +Alps rotary encoder, EC12E..., vertical shaft, mounting holes with circular drills, http://www.alps.com/prod/info/E/HTML/Encoder/Incremental/EC12E/EC12E1240405.html +rotary encoder +0 +5 +4 +Sensor +Aosong_DHT11_5.5x12.0_P2.54mm +Temperature and humidity module, http://akizukidenshi.com/download/ds/aosong/DHT11.pdf +Temperature and humidity module +0 +4 +4 +Sensor +MQ-6 +Gas Sensor, 6 pin, https://www.winsen-sensor.com/d/files/semiconductor/mq-6.pdf +gas sensor +0 +6 +6 +Sensor +SHT1x +SHT1x +SHT1x +0 +8 +8 +Sensor_Audio +Infineon_PG-LLGA-5-1 +Infineon_PG-LLGA-5-1 StepUp generated footprint, https://www.infineon.com/cms/en/product/packages/PG-LLGA/PG-LLGA-5-1/ +infineon mems microphone +0 +15 +5 +Sensor_Audio +ST_HLGA-6_3.76x4.72mm_P1.65mm +http://www.st.com/content/ccc/resource/technical/document/datasheet/group3/27/62/48/98/44/54/4d/36/DM00303211/files/DM00303211.pdf/jcr:content/translations/en.DM00303211.pdf +HLGA Sensor Audio +0 +6 +6 +Sensor_Current +AKM_CQ_7 +AKM Current Sensor, 7 pin, THT (http://www.akm.com/akm/en/file/datasheet/CQ-236B.pdf) +akm current sensor tht +0 +39 +7 +Sensor_Current +AKM_CQ_7S +AKM Current Sensor, 7 pin, SMD (http://www.akm.com/akm/en/file/datasheet/CQ-236B.pdf) +akm current sensor smd +0 +19 +7 +Sensor_Current +AKM_CQ_VSOP-24_5.6x7.9mm_P0.65mm +AKM VSOP-24 current sensor, 5.6x7.9mm body, 0.65mm pitch (http://www.akm.com/akm/en/file/datasheet/CQ-330J.pdf) +akm vsop 24 +0 +10 +10 +Sensor_Current +AKM_CZ_SSOP-10_6.5x8.1mm_P0.95mm +AKM CZ-381x current sensor, 6.5x8.1mm body, 0.95mm pitch (http://www.akm.com/akm/en/product/detail/0009/) +akm cz-381x 10 +0 +10 +10 +Sensor_Current +Allegro_CB_PFF +Allegro MicroSystems, CB-PFF Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) !PADS 4-5 DO NOT MATCH DATASHEET! +Allegro CB-PFF +0 +37 +5 +Sensor_Current +Allegro_CB_PSF +Allegro MicroSystems, CB-PSF Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) +Allegro CB-PSF +0 +5 +5 +Sensor_Current +Allegro_CB_PSS +Allegro MicroSystems, CB-PSS Package (http://www.allegromicro.com/en/Products/Current-Sensor-ICs/Fifty-To-Two-Hundred-Amp-Integrated-Conductor-Sensor-ICs/ACS758.aspx) +Allegro CB-PSS +0 +5 +5 +Sensor_Current +Allegro_PSOF-7_4.8x6.4mm_P1.60mm +Allegro Microsystems PSOF-7, 4.8x6.4mm Body, 1.60mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS780-Datasheet.ashx) +Allegro PSOF-7 +0 +7 +7 +Sensor_Current +Allegro_QFN-12-10-1EP_3x3mm_P0.5mm +Allegro Microsystems 12-Lead (10-Lead Populated) Quad Flat Pack, 3x3mm Body, 0.5mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/ACS711-Datasheet.ashx) +Allegro QFN 0.5 +0 +14 +10 +Sensor_Current +Allegro_QSOP-24_3.9x8.7mm_P0.635mm +Allegro Microsystems 24-Lead Plastic Shrink Small Outline Narrow Body Body [QSOP] (http://www.allegromicro.com/~/media/Files/Datasheets/ACS726-Datasheet.ashx?la=en) +Allegro QSOP 0.635 +0 +24 +24 +Sensor_Current +Allegro_SIP-3 +Allegro Microsystems SIP-3, 1.27mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/A1369-Datasheet.ashx) +Allegro SIP-3 +0 +3 +3 +Sensor_Current +Allegro_SIP-4 +Allegro Microsystems SIP-4, 1.27mm Pitch (http://www.allegromicro.com/~/media/Files/Datasheets/A1363-Datasheet.ashx) +Allegro SIP-4 +0 +4 +4 +Sensor_Current +Diodes_SIP-3_4.1x1.5mm_P1.27mm +Diodes SIP-3 Bulk Pack, 1.27mm Pitch (https://www.diodes.com/assets/Package-Files/SIP-3-Bulk-Pack.pdf) +Diodes SIP-3 Bulk Pack +0 +3 +3 +Sensor_Current +Diodes_SIP-3_4.1x1.5mm_P2.65mm +Diodes SIP-3 Ammo Pack, 2.65mm Pitch (https://www.diodes.com/assets/Package-Files/SIP-3-Ammo-Pack.pdf) +Diodes SIP-3 Ammo Pack +0 +3 +3 +Sensor_Current +Honeywell_CSLW +https://sensing.honeywell.com/honeywell-sensing-cslw-series-product-sheet-005861-1-en.pdf +Miniature Wired Open-Loop Current Sensor +0 +5 +5 +Sensor_Current +LEM_HO8-NP +LEM HO 8/15/25-NP Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-np-0000_series.pdf) +current transducer +0 +13 +13 +Sensor_Current +LEM_HO8-NSM +LEM HO 8/15/25-NSM Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-nsm-0000_series.pdf) +current transducer +0 +13 +13 +Sensor_Current +LEM_HO40-NP +LEM HO 40/60/120/150-NP Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/ho-np_0100__1100_series.pdf) +current transducer +0 +13 +13 +Sensor_Current +LEM_HTFS +LEM HTFS x00-P current transducer (https://www.lem.com/sites/default/files/products_datasheets/htfs_200_800-p.pdf) +HTFS current transducer +0 +4 +4 +Sensor_Current +LEM_HX02-P +LEM HX02-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX03-P-SP2 +LEM HX03-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX04-P +LEM HX04-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX05-NP +LEM HX05-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf) +hall current +0 +8 +8 +Sensor_Current +LEM_HX05-P-SP2 +LEM HX05-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX06-P +LEM HX06-P hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%202_6-p_e%20v5.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX10-NP +LEM HX10-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf) +hall current +0 +8 +8 +Sensor_Current +LEM_HX10-P-SP2 +LEM HX10-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX15-NP +LEM HX15-NP hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%205_15-np_e%20v10.pdf) +hall current +0 +8 +8 +Sensor_Current +LEM_HX15-P-SP2 +LEM HX15-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX20-P-SP2 +LEM HX20-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX25-P-SP2 +LEM HX25-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_HX50-P-SP2 +LEM HX50-P-SP2 hall effect current transducer (https://www.lem.com/sites/default/files/products_datasheets/hx%203_50-p_sp2_e%20v07.pdf) +hall current +0 +6 +6 +Sensor_Current +LEM_LA25-P +LEM Current Transducer (https://www.lem.com/sites/default/files/products_datasheets/la_25-p.pdf) +current transducer +0 +3 +3 +Sensor_Current +LEM_LTSR-NP +LEM current transducer LEM_LTSR-NP 5V supply voltage series https://www.lem.com/sites/default/files/products_datasheets/ltsr_6-np.pdf +Current transducer +0 +10 +10 +Sensor_Motion +InvenSense_QFN-24_3x3mm_P0.4mm +24-Lead Plastic QFN (3mm x 3mm); Pitch 0.4mm; EP 1.7x1.54mm; for InvenSense motion sensors; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU9250REV1.0.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) +QFN 0.4 +0 +24 +24 +Sensor_Motion +InvenSense_QFN-24_3x3mm_P0.4mm_NoMask +24-Lead Plastic QFN (3mm x 3mm); Pitch 0.4mm; EP 1.7x1.54mm; for InvenSense motion sensors; Mask removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU9250REV1.0.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) +QFN 0.4 +0 +25 +24 +Sensor_Motion +InvenSense_QFN-24_4x4mm_P0.5mm +24-Lead Plastic QFN (4mm x 4mm); Pitch 0.5mm; EP 2.7x2.6mm; for InvenSense motion sensors; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) +QFN 0.5 +0 +24 +24 +Sensor_Motion +InvenSense_QFN-24_4x4mm_P0.5mm_NoMask +24-Lead Plastic QFN (4mm x 4mm); Pitch 0.5mm; EP 2.7x2.6mm; for InvenSense motion sensors; Mask removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf) +QFN 0.5 +0 +25 +24 +Sensor_Pressure +Freescale_98ARH99066A +https://www.nxp.com/docs/en/data-sheet/MPXH6250A.pdf +sensor pressure ssop 98ARH99066A +0 +8 +8 +Sensor_Pressure +Freescale_98ARH99089A +https://www.nxp.com/docs/en/data-sheet/MPXH6250A.pdf +sensor pressure ssop 98ARH99089A +0 +8 +8 +Sensor_Pressure +Honeywell_40PCxxxG1A +https://www.honeywellscportal.com/index.php?ci_id=138832 +pressure sensor automotive honeywell +0 +3 +3 +Sensor_Voltage +LEM_LV25-P +LEM LV25-P Voltage transducer, https://www.lem.com/sites/default/files/products_datasheets/lv_25-p.pdf +LEM Hall Effect Voltage transducer +0 +5 +5 +Socket +3M_Textool_240-1288-00-0602J_2x20_P2.54mm +3M 40-pin zero insertion force socket, though-hole, row spacing 25.4 mm (1000 mils) +THT DIP DIL ZIF 25.4mm 1000mil Socket +0 +40 +40 +Socket +DIP_Socket-14_W4.3_W5.08_W7.62_W10.16_W10.9_3M_214-3339-00-0602J +3M 14-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 7.62mm 300mil Socket +0 +14 +14 +Socket +DIP_Socket-16_W4.3_W5.08_W7.62_W10.16_W10.9_3M_216-3340-00-0602J +3M 16-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 7.62mm 300mil Socket +0 +16 +16 +Socket +DIP_Socket-18_W4.3_W5.08_W7.62_W10.16_W10.9_3M_218-3341-00-0602J +3M 18-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 7.62mm 300mil Socket +0 +18 +18 +Socket +DIP_Socket-20_W4.3_W5.08_W7.62_W10.16_W10.9_3M_220-3342-00-0602J +3M 20-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 7.62mm 300mil Socket +0 +20 +20 +Socket +DIP_Socket-22_W6.9_W7.62_W10.16_W12.7_W13.5_3M_222-3343-00-0602J +3M 22-pin zero insertion force socket, through-hole, row spacing 10.16 mm (400 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 10.16mm 400mil Socket +0 +22 +22 +Socket +DIP_Socket-24_W4.3_W5.08_W7.62_W10.16_W10.9_3M_224-5248-00-0602J +3M 24-pin zero insertion force socket, through-hole, row spacing 7.62 mm (300 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 7.62mm 300mil Socket +0 +24 +24 +Socket +DIP_Socket-24_W11.9_W12.7_W15.24_W17.78_W18.5_3M_224-1275-00-0602J +3M 24-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 15.24mm 600mil Socket +0 +24 +24 +Socket +DIP_Socket-28_W6.9_W7.62_W10.16_W12.7_W13.5_3M_228-4817-00-0602J +3M 28-pin zero insertion force socket, through-hole, row spacing 10.16 mm (400 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 10.16mm 400mil Socket +0 +28 +28 +Socket +DIP_Socket-28_W11.9_W12.7_W15.24_W17.78_W18.5_3M_228-1277-00-0602J +3M 28-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 15.24mm 600mil Socket +0 +28 +28 +Socket +DIP_Socket-32_W11.9_W12.7_W15.24_W17.78_W18.5_3M_232-1285-00-0602J +3M 32-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 15.24mm 600mil Socket +0 +32 +32 +Socket +DIP_Socket-40_W11.9_W12.7_W15.24_W17.78_W18.5_3M_240-1280-00-0602J +3M 40-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 15.24mm 600mil Socket +0 +40 +40 +Socket +DIP_Socket-40_W22.1_W22.86_W25.4_W27.94_W28.7_3M_240-3639-00-0602J +3M 40-pin zero insertion force socket, through-hole, row spacing 25.4 mm (1000 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 25.4mm 1000mil Socket +0 +40 +40 +Socket +DIP_Socket-42_W11.9_W12.7_W15.24_W17.78_W18.5_3M_242-1281-00-0602J +3M 42-pin zero insertion force socket, through-hole, row spacing 15.24 mm (600 mils), http://multimedia.3m.com/mws/media/494546O/3mtm-dip-sockets-100-2-54-mm-ts0365.pdf +THT DIP DIL ZIF 15.24mm 600mil Socket +0 +42 +42 +Socket +Wells_648-0482211SA01 +https://www.farnell.com/cad/316865.pdf?_ga=2.37208032.177107060.1530611323-249019997.1498114824 +48pin TSOP Socket +0 +48 +48 +Symbol +CE-Logo_8.5x6mm_SilkScreen +CE marking +Logo CE certification +0 +0 +0 +Symbol +CE-Logo_11.2x8mm_SilkScreen +CE marking +Logo CE certification +0 +0 +0 +Symbol +CE-Logo_16.8x12mm_SilkScreen +CE marking +Logo CE certification +0 +0 +0 +Symbol +CE-Logo_28x20mm_SilkScreen +CE marking +Logo CE certification +0 +0 +0 +Symbol +CE-Logo_42x30mm_SilkScreen +CE marking +Logo CE certification +0 +0 +0 +Symbol +CE-Logo_56.1x40mm_SilkScreen +CE marking +Logo CE certification +0 +0 +0 +Symbol +ESD-Logo_6.6x6mm_SilkScreen +Electrostatic discharge Logo +Logo ESD +0 +0 +0 +Symbol +ESD-Logo_8.9x8mm_SilkScreen +Electrostatic discharge Logo +Logo ESD +0 +0 +0 +Symbol +ESD-Logo_13.2x12mm_SilkScreen +Electrostatic discharge Logo +Logo ESD +0 +0 +0 +Symbol +ESD-Logo_22x20mm_SilkScreen +Electrostatic discharge Logo +Logo ESD +0 +0 +0 +Symbol +ESD-Logo_33x30mm_SilkScreen +Electrostatic discharge Logo +Logo ESD +0 +0 +0 +Symbol +ESD-Logo_44.1x40mm_SilkScreen +Electrostatic discharge Logo +Logo ESD +0 +0 +0 +Symbol +FCC-Logo_7.3x6mm_SilkScreen +FCC marking +Logo FCC certification +0 +0 +0 +Symbol +FCC-Logo_9.6x8mm_SilkScreen +FCC marking +Logo FCC certification +0 +0 +0 +Symbol +FCC-Logo_14.6x12mm_SilkScreen +FCC marking +Logo FCC certification +0 +0 +0 +Symbol +FCC-Logo_24.2x20mm_SilkScreen +FCC marking +Logo FCC certification +0 +0 +0 +Symbol +FCC-Logo_36.3x30mm_SilkScreen +FCC marking +Logo FCC certification +0 +0 +0 +Symbol +FCC-Logo_48.3x40mm_SilkScreen +FCC marking +Logo FCC certification +0 +0 +0 +Symbol +KiCad-Logo2_5mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_5mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_6mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_6mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_8mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_8mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_12mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_12mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_20mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_20mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_30mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_30mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_40mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo2_40mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_5mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_5mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_6mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_6mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_8mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_8mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_12mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_12mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_20mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_20mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_30mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_30mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_40mm_Copper +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +KiCad-Logo_40mm_SilkScreen +KiCad Logo +Logo KiCad +0 +0 +0 +Symbol +OSHW-Logo2_7.3x6mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_7.3x6mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_9.8x8mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_9.8x8mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_14.6x12mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_14.6x12mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_24.3x20mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_24.3x20mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_36.5x30mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_36.5x30mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_48.7x40mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo2_48.7x40mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Logo_5.7x6mm_Copper +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_5.7x6mm_SilkScreen +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_7.5x8mm_Copper +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_7.5x8mm_SilkScreen +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_11.4x12mm_Copper +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_11.4x12mm_SilkScreen +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_19x20mm_Copper +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_19x20mm_SilkScreen +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_28.5x30mm_Copper +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_28.5x30mm_SilkScreen +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_38.1x40mm_Copper +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Logo_38.1x40mm_SilkScreen +Open Source Hardware Logo +Logo OSHW +0 +0 +0 +Symbol +OSHW-Symbol_6.7x6mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_6.7x6mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_8.9x8mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_8.9x8mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_13.4x12mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_13.4x12mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_22.3x20mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_22.3x20mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_33.5x30mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_33.5x30mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_44.5x40mm_Copper +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +OSHW-Symbol_44.5x40mm_SilkScreen +Open Source Hardware Symbol +Logo Symbol OSHW +0 +0 +0 +Symbol +Polarity_Center_Negative_6mm_SilkScreen +Polarity Logo, Center Negative +Logo Polarity Center Negative +0 +0 +0 +Symbol +Polarity_Center_Negative_8mm_SilkScreen +Polarity Logo, Center Negative +Logo Polarity Center Negative +0 +0 +0 +Symbol +Polarity_Center_Negative_12mm_SilkScreen +Polarity Logo, Center Negative +Logo Polarity Center Negative +0 +0 +0 +Symbol +Polarity_Center_Negative_20mm_SilkScreen +Polarity Logo, Center Negative +Logo Polarity Center Negative +0 +0 +0 +Symbol +Polarity_Center_Negative_30mm_SilkScreen +Polarity Logo, Center Negative +Logo Polarity Center Negative +0 +0 +0 +Symbol +Polarity_Center_Negative_40mm_SilkScreen +Polarity Logo, Center Negative +Logo Polarity Center Negative +0 +0 +0 +Symbol +Polarity_Center_Positive_6mm_SilkScreen +Polarity Logo, Center Positive +Logo Polarity Center Positive +0 +0 +0 +Symbol +Polarity_Center_Positive_8mm_SilkScreen +Polarity Logo, Center Positive +Logo Polarity Center Positive +0 +0 +0 +Symbol +Polarity_Center_Positive_12mm_SilkScreen +Polarity Logo, Center Positive +Logo Polarity Center Positive +0 +0 +0 +Symbol +Polarity_Center_Positive_20mm_SilkScreen +Polarity Logo, Center Positive +Logo Polarity Center Positive +0 +0 +0 +Symbol +Polarity_Center_Positive_30mm_SilkScreen +Polarity Logo, Center Positive +Logo Polarity Center Positive +0 +0 +0 +Symbol +Polarity_Center_Positive_40mm_SilkScreen +Polarity Logo, Center Positive +Logo Polarity Center Positive +0 +0 +0 +Symbol +RoHS-Logo_6mm_SilkScreen +Restriction of Hazardous Substances Directive Logo +Logo RoHS +0 +0 +0 +Symbol +RoHS-Logo_8mm_SilkScreen +Restriction of Hazardous Substances Directive Logo +Logo RoHS +0 +0 +0 +Symbol +RoHS-Logo_12mm_SilkScreen +Restriction of Hazardous Substances Directive Logo +Logo RoHS +0 +0 +0 +Symbol +RoHS-Logo_20mm_SilkScreen +Restriction of Hazardous Substances Directive Logo +Logo RoHS +0 +0 +0 +Symbol +RoHS-Logo_30mm_SilkScreen +Restriction of Hazardous Substances Directive Logo +Logo RoHS +0 +0 +0 +Symbol +RoHS-Logo_40mm_SilkScreen +Restriction of Hazardous Substances Directive Logo +Logo RoHS +0 +0 +0 +Symbol +Symbol_Attention_CopperTop_Big +Symbol, Attention, Copper Top, Big, +Symbol, Attention, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_Attention_CopperTop_Small +Symbol, Attention, Copper Top, Small, +Symbol, Attention, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_Barrel_Polarity +Barrel connector polarity indicator +barrel polarity +0 +0 +0 +Symbol +Symbol_CC-Attribution_CopperTop_Big +Symbol, CC-Attribution, Copper Top, Big, +Symbol, CC-Attribution, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_CC-Attribution_CopperTop_Small +Symbol, CC-Share Alike, Copper Top, Small, +Symbol, CC-Share Alike, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_CC-Noncommercial_CopperTop_Big +Symbol, CC-Noncommercial, Copper Top, Big, +Symbol, CC-Noncommercial, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_CC-Noncommercial_CopperTop_Small +Symbol, CC-Noncommercial Alike, Copper Top, Small, +Symbol, CC-Noncommercial Alike, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_CC-PublicDomain_CopperTop_Big +Symbol, CC-PublicDomain, Copper Top, Big, +Symbol, CC-PublicDomain, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_CC-PublicDomain_CopperTop_Small +Symbol, CC-Public Domain, Copper Top, Small, +Symbol, CC-Public Domain, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_CC-PublicDomain_SilkScreenTop_Big +Symbol, CC-PublicDomain, SilkScreen Top, Big, +Symbol, CC-PublicDomain, SilkScreen Top, Big, +0 +0 +0 +Symbol +Symbol_CC-ShareAlike_CopperTop_Big +Symbol, CC-Share Alike, Copper Top, Big, +Symbol, CC-Share Alike, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_CC-ShareAlike_CopperTop_Small +Symbol, CC-Share Alike, Copper Top, Small, +Symbol, CC-Share Alike, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_CreativeCommonsPublicDomain_CopperTop_Small +Symbol, Creative Commons Public Domain, CopperTop, Small, +Symbol, Creative Commons Public Domain, CopperTop, Small, +0 +0 +0 +Symbol +Symbol_CreativeCommonsPublicDomain_SilkScreenTop_Small +Symbol, Creative Commons Public Domain, SilkScreenTop, Small, +Symbol, Creative Commons Public Domain, SilkScreen Top, Small, +0 +0 +0 +Symbol +Symbol_CreativeCommons_CopperTop_Type1_Big +Symbol, Creative Commons, CopperTop, Type 1, Big, +Symbol, Creative Commons, CopperTop, Type 1, Big, +0 +0 +0 +Symbol +Symbol_CreativeCommons_CopperTop_Type2_Big +Symbol, Creative Commons, CopperTop, Type 2, Big, +Symbol, Creative Commons, CopperTop, Type 2, Big, +0 +0 +0 +Symbol +Symbol_CreativeCommons_CopperTop_Type2_Small +Symbol, Creative Commons, CopperTop, Type 2, Small, +Symbol, Creative Commons, CopperTop, Type 2, Small, +0 +0 +0 +Symbol +Symbol_CreativeCommons_SilkScreenTop_Type2_Big +Symbol, Creative Commons, SilkScreen Top, Type 2, Big, +Symbol, Creative Commons, SilkScreen Top, Type 2, Big, +0 +0 +0 +Symbol +Symbol_Danger_CopperTop_Big +Symbol, Danger, CopperTop, Big, +Symbol, Danger, CopperTop, Big, +0 +0 +0 +Symbol +Symbol_Danger_CopperTop_Small +Symbol, Danger, Copper Top, Small, +Symbol, Danger, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_ESD-Logo-Text_CopperTop + + +0 +0 +0 +Symbol +Symbol_ESD-Logo_CopperTop +ESD-Logo, similar JEDEC-14, without text, ohne Text, Copper Top, +ESD-Logo, similar JEDEC-14, without text, ohne Text, Copper Top, +0 +0 +0 +Symbol +Symbol_GNU-GPL_CopperTop_Big +Symbol, GNU-GPL, Copper Top, Big, +Symbol, GNU-GPL, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_GNU-GPL_CopperTop_Small +Symbol, GNU-GPL, Copper Top, Small, +Symbol, GNU-GPL, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_GNU-Logo_CopperTop +GNU-Logo, GNU-Head, GNU-Kopf, Copper Top, +GNU-Logo, GNU-Head, GNU-Kopf, Copper Top, +0 +0 +0 +Symbol +Symbol_GNU-Logo_SilkscreenTop +GNU-Logo, GNU-Head, GNU-Kopf, Silkscreen, +GNU-Logo, GNU-Head, GNU-Kopf, Silkscreen, +0 +0 +0 +Symbol +Symbol_HighVoltage_Type1_CopperTop_Big +Symbol, HighVoltage, Type1, Copper Top, Big, +Symbol, HighVoltage, Type1, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_HighVoltage_Type2_CopperTop_Big +Symbol, HighVoltage, Type2, Copper Top, Big, +Symbol, HighVoltage, Type2, Copper Top, Big, +0 +0 +0 +Symbol +Symbol_HighVoltage_Type2_CopperTop_VerySmall +Symbol, High Voltage, Type 2, Copper Top, Very Small, +Symbol, High Voltage, Type 2, Copper Top, Very Small, +0 +0 +0 +Symbol +Symbol_Highvoltage_Type1_CopperTop_Small +Symbol, Highvoltage, Type 1, Copper Top, Small, +Symbol, Highvoltage, Type 1, Copper Top, Small, +0 +0 +0 +Symbol +Symbol_Highvoltage_Type2_CopperTop_Small +Symbol, Highvoltage, Type 2, Copper Top, Small, +Symbol, Highvoltage, Type 2, Copper Top, Small, +0 +0 +0 +Symbol +WEEE-Logo_4.2x6mm_SilkScreen +Waste Electrical and Electronic Equipment Directive +Logo WEEE +0 +0 +0 +Symbol +WEEE-Logo_5.6x8mm_SilkScreen +Waste Electrical and Electronic Equipment Directive +Logo WEEE +0 +0 +0 +Symbol +WEEE-Logo_8.4x12mm_SilkScreen +Waste Electrical and Electronic Equipment Directive +Logo WEEE +0 +0 +0 +Symbol +WEEE-Logo_14x20mm_SilkScreen +Waste Electrical and Electronic Equipment Directive +Logo WEEE +0 +0 +0 +Symbol +WEEE-Logo_21x30mm_SilkScreen +Waste Electrical and Electronic Equipment Directive +Logo WEEE +0 +0 +0 +Symbol +WEEE-Logo_28.1x40mm_SilkScreen +Waste Electrical and Electronic Equipment Directive +Logo WEEE +0 +0 +0 +TerminalBlock +TerminalBlock_Altech_AK300-2_P5.00mm +Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf +Altech AK300 terminal block pitch 5.0mm +0 +2 +2 +TerminalBlock +TerminalBlock_Altech_AK300-3_P5.00mm +Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf +Altech AK300 terminal block pitch 5.0mm +0 +3 +3 +TerminalBlock +TerminalBlock_Altech_AK300-4_P5.00mm +Altech AK300 terminal block, pitch 5.0mm, 45 degree angled, see http://www.mouser.com/ds/2/16/PCBMETRC-24178.pdf +Altech AK300 terminal block pitch 5.0mm +0 +4 +4 +TerminalBlock +TerminalBlock_Wuerth_691311400102_P7.62mm +https://katalog.we-online.de/em/datasheet/6913114001xx.pdf +Wuerth WR-TBL Series 3114 terminal block pitch 7.62mm +0 +2 +2 +TerminalBlock +TerminalBlock_bornier-2_P5.08mm +simple 2-pin terminal block, pitch 5.08mm, revamped version of bornier2 +terminal block bornier2 +0 +2 +2 +TerminalBlock +TerminalBlock_bornier-3_P5.08mm +simple 3-pin terminal block, pitch 5.08mm, revamped version of bornier3 +terminal block bornier3 +0 +3 +3 +TerminalBlock +TerminalBlock_bornier-4_P5.08mm +simple 4-pin terminal block, pitch 5.08mm, revamped version of bornier4 +terminal block bornier4 +0 +4 +4 +TerminalBlock +TerminalBlock_bornier-5_P5.08mm +simple 5-pin terminal block, pitch 5.08mm, revamped version of bornier5 +terminal block bornier5 +0 +5 +5 +TerminalBlock +TerminalBlock_bornier-6_P5.08mm +simple 6pin terminal block, pitch 5.08mm, revamped version of bornier6 +terminal block bornier6 +0 +6 +6 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x02_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 19963, 2 pins, pitch 3.5mm, size 7.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19963.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 19963 pitch 3.5mm size 7.7x7mm^2 drill 1.2mm pad 2.4mm +0 +2 +2 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x02_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10693, vertical (cable from top), 2 pins, pitch 3.5mm, size 8x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10693.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10693 vertical pitch 3.5mm size 8x8.3mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x03_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 20193, 3 pins, pitch 3.5mm, size 11.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20193.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 20193 pitch 3.5mm size 11.2x7mm^2 drill 1.2mm pad 2.4mm +0 +3 +3 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x03_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10694, vertical (cable from top), 3 pins, pitch 3.5mm, size 11.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10694.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10694 vertical pitch 3.5mm size 11.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x04_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 20001, 4 pins, pitch 3.5mm, size 14.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20001.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 20001 pitch 3.5mm size 14.7x7mm^2 drill 1.2mm pad 2.4mm +0 +4 +4 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x04_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10695, vertical (cable from top), 4 pins, pitch 3.5mm, size 15x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10695.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10695 vertical pitch 3.5mm size 15x8.3mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x05_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 20223, 5 pins, pitch 3.5mm, size 18.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/20223.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 20223 pitch 3.5mm size 18.2x7mm^2 drill 1.2mm pad 2.4mm +0 +5 +5 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x05_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10696, vertical (cable from top), 5 pins, pitch 3.5mm, size 18.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10696.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10696 vertical pitch 3.5mm size 18.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x06_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 19964, 6 pins, pitch 3.5mm, size 21.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19964.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 19964 pitch 3.5mm size 21.7x7mm^2 drill 1.2mm pad 2.4mm +0 +6 +6 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x06_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10697, vertical (cable from top), 6 pins, pitch 3.5mm, size 22x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10697.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10697 vertical pitch 3.5mm size 22x8.3mm^2 drill 1.3mm pad 2.6mm +0 +6 +6 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x07_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10684, 7 pins, pitch 3.5mm, size 25.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10684.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10684 pitch 3.5mm size 25.2x7mm^2 drill 1.2mm pad 2.4mm +0 +7 +7 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x07_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10698, vertical (cable from top), 7 pins, pitch 3.5mm, size 25.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10698.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10698 vertical pitch 3.5mm size 25.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +7 +7 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x08_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 19965, 8 pins, pitch 3.5mm, size 28.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/19965.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 19965 pitch 3.5mm size 28.7x7mm^2 drill 1.2mm pad 2.4mm +0 +8 +8 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x08_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10699, vertical (cable from top), 8 pins, pitch 3.5mm, size 29x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10699.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10699 vertical pitch 3.5mm size 29x8.3mm^2 drill 1.3mm pad 2.6mm +0 +8 +8 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x09_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10686, 9 pins, pitch 3.5mm, size 32.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10686.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10686 pitch 3.5mm size 32.2x7mm^2 drill 1.2mm pad 2.4mm +0 +9 +9 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x09_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10700, vertical (cable from top), 9 pins, pitch 3.5mm, size 32.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10700.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10700 vertical pitch 3.5mm size 32.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +9 +9 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x10_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10687, 10 pins, pitch 3.5mm, size 35.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10687.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10687 pitch 3.5mm size 35.7x7mm^2 drill 1.2mm pad 2.4mm +0 +10 +10 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x10_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10701, vertical (cable from top), 10 pins, pitch 3.5mm, size 36x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10701.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10701 vertical pitch 3.5mm size 36x8.3mm^2 drill 1.3mm pad 2.6mm +0 +10 +10 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x11_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10688, 11 pins, pitch 3.5mm, size 39.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10688.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10688 pitch 3.5mm size 39.2x7mm^2 drill 1.2mm pad 2.4mm +0 +11 +11 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x11_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10702, vertical (cable from top), 11 pins, pitch 3.5mm, size 39.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10702.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10702 vertical pitch 3.5mm size 39.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +11 +11 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x12_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10689, 12 pins, pitch 3.5mm, size 42.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10689.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10689 pitch 3.5mm size 42.7x7mm^2 drill 1.2mm pad 2.4mm +0 +12 +12 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x12_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10703, vertical (cable from top), 12 pins, pitch 3.5mm, size 43x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10703.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10703 vertical pitch 3.5mm size 43x8.3mm^2 drill 1.3mm pad 2.6mm +0 +12 +12 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x13_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10690, 13 pins, pitch 3.5mm, size 46.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10690.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10690 pitch 3.5mm size 46.2x7mm^2 drill 1.2mm pad 2.4mm +0 +13 +13 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x13_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10704, vertical (cable from top), 13 pins, pitch 3.5mm, size 46.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10704.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10704 vertical pitch 3.5mm size 46.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +13 +13 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x14_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10691, 14 pins, pitch 3.5mm, size 49.7x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10691.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10691 pitch 3.5mm size 49.7x7mm^2 drill 1.2mm pad 2.4mm +0 +14 +14 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x14_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10705, vertical (cable from top), 14 pins, pitch 3.5mm, size 50x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10705.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10705 vertical pitch 3.5mm size 50x8.3mm^2 drill 1.3mm pad 2.6mm +0 +14 +14 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x15_P3.50mm_Horizontal +Terminal Block 4Ucon ItemNo. 10692, 15 pins, pitch 3.5mm, size 53.2x7mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.4uconnector.com/online/object/4udrawing/10692.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10692 pitch 3.5mm size 53.2x7mm^2 drill 1.2mm pad 2.4mm +0 +15 +15 +TerminalBlock_4Ucon +TerminalBlock_4Ucon_1x15_P3.50mm_Vertical +Terminal Block 4Ucon ItemNo. 10706, vertical (cable from top), 15 pins, pitch 3.5mm, size 53.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.4uconnector.com/online/object/4udrawing/10706.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_4Ucon +THT Terminal Block 4Ucon ItemNo. 10706 vertical pitch 3.5mm size 53.5x8.3mm^2 drill 1.3mm pad 2.6mm +0 +15 +15 +TerminalBlock_Altech +Altech_AK300_1x02_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +2 +2 +TerminalBlock_Altech +Altech_AK300_1x03_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +3 +3 +TerminalBlock_Altech +Altech_AK300_1x04_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +4 +4 +TerminalBlock_Altech +Altech_AK300_1x05_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +5 +5 +TerminalBlock_Altech +Altech_AK300_1x06_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +6 +6 +TerminalBlock_Altech +Altech_AK300_1x07_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +7 +7 +TerminalBlock_Altech +Altech_AK300_1x08_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +8 +8 +TerminalBlock_Altech +Altech_AK300_1x09_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +9 +9 +TerminalBlock_Altech +Altech_AK300_1x10_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +10 +10 +TerminalBlock_Altech +Altech_AK300_1x11_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +11 +11 +TerminalBlock_Altech +Altech_AK300_1x12_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +12 +12 +TerminalBlock_Altech +Altech_AK300_1x13_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +13 +13 +TerminalBlock_Altech +Altech_AK300_1x14_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +14 +14 +TerminalBlock_Altech +Altech_AK300_1x15_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +15 +15 +TerminalBlock_Altech +Altech_AK300_1x16_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +16 +16 +TerminalBlock_Altech +Altech_AK300_1x17_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +17 +17 +TerminalBlock_Altech +Altech_AK300_1x18_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +18 +18 +TerminalBlock_Altech +Altech_AK300_1x19_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +19 +19 +TerminalBlock_Altech +Altech_AK300_1x20_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +20 +20 +TerminalBlock_Altech +Altech_AK300_1x21_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +21 +21 +TerminalBlock_Altech +Altech_AK300_1x22_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +22 +22 +TerminalBlock_Altech +Altech_AK300_1x23_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +23 +23 +TerminalBlock_Altech +Altech_AK300_1x24_P5.00mm_45-Degree +Altech AK300 serie terminal block (Script generated with StandardBox.py) (http://www.altechcorp.com/PDFS/PCBMETRC.PDF) +Altech AK300 serie connector +0 +24 +24 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-02_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +2 +2 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-03_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +3 +3 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-04_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +4 +4 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-05_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +5 +5 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-06_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +6 +6 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-07_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +7 +7 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-08_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +8 +8 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-09_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +9 +9 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-10_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +10 +10 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-11_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +11 +11 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-12_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +12 +12 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-13_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +13 +13 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-14_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +14 +14 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-15_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +15 +15 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-16_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +16 +16 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-17_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +17 +17 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-18_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +18 +18 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-19_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +19 +19 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-20_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +20 +20 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-21_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +21 +21 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-22_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +22 +22 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-23_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +23 +23 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-24_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +24 +24 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-25_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +25 +25 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-26_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +26 +26 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-27_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +27 +27 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-28_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +28 +28 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-29_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +29 +29 +TerminalBlock_Dinkle +TerminalBlock_Dinkle_DT-55-B01X-30_P10.00mm +Dinkle DT-55-B01X Terminal Block pitch 10.00mm https://www.dinkle.com/en/terminal/DT-55-B01W-XX +Dinkle DT-55-B01X Terminal Block pitch 10.00mm +0 +30 +30 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360271_1x01_Horizontal_ScrewM3.0_Boxed +single screw terminal block Metz Connect 360271, block size 9x7.3mm^2, drill diamater 1.5mm, 1 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 134, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360271 size 9x7.3mm^2 drill 1.5mm pad 3mm +0 +1 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360272_1x01_Horizontal_ScrewM2.6 +single screw terminal block Metz Connect 360272, block size 4x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 131, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360272 size 4x4mm^2 drill 1.5mm pad 3mm +0 +2 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360273_1x01_Horizontal_ScrewM2.6_WireProtection +single screw terminal block Metz Connect 360273, block size 5x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 131, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360273 size 5x4mm^2 drill 1.5mm pad 3mm +0 +2 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360291_1x01_Horizontal_ScrewM3.0_Boxed +single screw terminal block Metz Connect 360291, block size 9x7.3mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360291 size 9x7.3mm^2 drill 1.5mm pad 3mm +0 +2 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360322_1x01_Horizontal_ScrewM3.0_WireProtection +single screw terminal block Metz Connect 360322, block size 6x4mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360322 size 6x4mm^2 drill 1.5mm pad 3mm +0 +2 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360381_1x01_Horizontal_ScrewM3.0 +single screw terminal block Metz Connect 360381, block size 5x5mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 133, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360381 size 5x5mm^2 drill 1.5mm pad 3mm +0 +2 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360410_1x01_Horizontal_ScrewM3.0 +single screw terminal block Metz Connect 360410, block size 5x5mm^2, drill diamater 1.5mm, 2 pads, pad diameter 3mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 132, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360410 size 5x5mm^2 drill 1.5mm pad 3mm +0 +2 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_360425_1x01_Horizontal_ScrewM4.0_Boxed +single screw terminal block Metz Connect 360425, block size 9x9mm^2, drill diamater 1.6mm, 4 pads, pad diameter 3.2mm, see http://www.metz-connect.com/de/system/files/METZ_CONNECT_U_Contact_Katalog_Anschlusssysteme_fuer_Leiterplatten_DE_31_07_2017_OFF_024803.pdf?language=en page 134, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT single screw terminal block Metz Connect 360425 size 9x9mm^2 drill 1.6mm pad 3.2mm +0 +4 +1 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type011_RT05502HBWC_1x02_P5.00mm_Horizontal +terminal block Metz Connect Type011_RT05502HBWC, 2 pins, pitch 5mm, size 10x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type011_RT05502HBWC pitch 5mm size 10x10.5mm^2 drill 1.4mm pad 2.8mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type011_RT05503HBWC_1x03_P5.00mm_Horizontal +terminal block Metz Connect Type011_RT05503HBWC, 3 pins, pitch 5mm, size 15x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type011_RT05503HBWC pitch 5mm size 15x10.5mm^2 drill 1.4mm pad 2.8mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type011_RT05504HBWC_1x04_P5.00mm_Horizontal +terminal block Metz Connect Type011_RT05504HBWC, 4 pins, pitch 5mm, size 20x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type011_RT05504HBWC pitch 5mm size 20x10.5mm^2 drill 1.4mm pad 2.8mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type011_RT05505HBWC_1x05_P5.00mm_Horizontal +terminal block Metz Connect Type011_RT05505HBWC, 5 pins, pitch 5mm, size 25x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type011_RT05505HBWC pitch 5mm size 25x10.5mm^2 drill 1.4mm pad 2.8mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type011_RT05506HBWC_1x06_P5.00mm_Horizontal +terminal block Metz Connect Type011_RT05506HBWC, 6 pins, pitch 5mm, size 30x10.5mm^2, drill diamater 1.4mm, pad diameter 2.8mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310111_RT055xxHBLC_OFF-022717S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type011_RT05506HBWC pitch 5mm size 30x10.5mm^2 drill 1.4mm pad 2.8mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type055_RT01502HDWU_1x02_P5.00mm_Horizontal +terminal block Metz Connect Type055_RT01502HDWU, 2 pins, pitch 5mm, size 10x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type055_RT01502HDWU pitch 5mm size 10x8mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type055_RT01503HDWU_1x03_P5.00mm_Horizontal +terminal block Metz Connect Type055_RT01503HDWU, 3 pins, pitch 5mm, size 15x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type055_RT01503HDWU pitch 5mm size 15x8mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type055_RT01504HDWU_1x04_P5.00mm_Horizontal +terminal block Metz Connect Type055_RT01504HDWU, 4 pins, pitch 5mm, size 20x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310551_RT015xxHDWU_OFF-022723S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type055_RT01504HDWU pitch 5mm size 20x8mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type059_RT06302HBWC_1x02_P3.50mm_Horizontal +terminal block Metz Connect Type059_RT06302HBWC, 2 pins, pitch 3.5mm, size 7x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type059_RT06302HBWC pitch 3.5mm size 7x6.5mm^2 drill 1.2mm pad 2.3mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type059_RT06303HBWC_1x03_P3.50mm_Horizontal +terminal block Metz Connect Type059_RT06303HBWC, 3 pins, pitch 3.5mm, size 10.5x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type059_RT06303HBWC pitch 3.5mm size 10.5x6.5mm^2 drill 1.2mm pad 2.3mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type059_RT06304HBWC_1x04_P3.50mm_Horizontal +terminal block Metz Connect Type059_RT06304HBWC, 4 pins, pitch 3.5mm, size 14x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type059_RT06304HBWC pitch 3.5mm size 14x6.5mm^2 drill 1.2mm pad 2.3mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type059_RT06305HBWC_1x05_P3.50mm_Horizontal +terminal block Metz Connect Type059_RT06305HBWC, 5 pins, pitch 3.5mm, size 17.5x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type059_RT06305HBWC pitch 3.5mm size 17.5x6.5mm^2 drill 1.2mm pad 2.3mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type059_RT06306HBWC_1x06_P3.50mm_Horizontal +terminal block Metz Connect Type059_RT06306HBWC, 6 pins, pitch 3.5mm, size 21x6.5mm^2, drill diamater 1.2mm, pad diameter 2.3mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310591_RT063xxHBWC_OFF-022684T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type059_RT06306HBWC pitch 3.5mm size 21x6.5mm^2 drill 1.2mm pad 2.3mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type067_RT01902HDWC_1x02_P10.00mm_Horizontal +terminal block Metz Connect Type067_RT01902HDWC, 2 pins, pitch 10mm, size 15.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type067_RT01902HDWC pitch 10mm size 15.8x8.2mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type067_RT01903HDWC_1x03_P10.00mm_Horizontal +terminal block Metz Connect Type067_RT01903HDWC, 3 pins, pitch 10mm, size 25.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type067_RT01903HDWC pitch 10mm size 25.8x8.2mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type067_RT01904HDWC_1x04_P10.00mm_Horizontal +terminal block Metz Connect Type067_RT01904HDWC, 4 pins, pitch 10mm, size 35.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type067_RT01904HDWC pitch 10mm size 35.8x8.2mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type067_RT01905HDWC_1x05_P10.00mm_Horizontal +terminal block Metz Connect Type067_RT01905HDWC, 5 pins, pitch 10mm, size 45.8x8.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310671_RT019xxHDWC_OFF-023605N.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type067_RT01905HDWC pitch 10mm size 45.8x8.2mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type073_RT02602HBLU_1x02_P5.08mm_Horizontal +terminal block Metz Connect Type073_RT02602HBLU, 2 pins, pitch 5.08mm, size 10.2x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310731_RT026xxHBLU_OFF-022792U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type073_RT02602HBLU pitch 5.08mm size 10.2x11mm^2 drill 1.4mm pad 2.6mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type073_RT02603HBLU_1x03_P5.08mm_Horizontal +terminal block Metz Connect Type073_RT02603HBLU, 3 pins, pitch 5.08mm, size 15.2x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310731_RT026xxHBLU_OFF-022792U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type073_RT02603HBLU pitch 5.08mm size 15.2x11mm^2 drill 1.4mm pad 2.6mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type086_RT03402HBLC_1x02_P3.81mm_Horizontal +terminal block Metz Connect Type086_RT03402HBLC, 2 pins, pitch 3.81mm, size 7.51x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type086_RT03402HBLC pitch 3.81mm size 7.51x7.3mm^2 drill 0.7mm pad 1.4mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type086_RT03403HBLC_1x03_P3.81mm_Horizontal +terminal block Metz Connect Type086_RT03403HBLC, 3 pins, pitch 3.81mm, size 11.3x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type086_RT03403HBLC pitch 3.81mm size 11.3x7.3mm^2 drill 0.7mm pad 1.4mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type086_RT03404HBLC_1x04_P3.81mm_Horizontal +terminal block Metz Connect Type086_RT03404HBLC, 4 pins, pitch 3.81mm, size 15.1x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type086_RT03404HBLC pitch 3.81mm size 15.1x7.3mm^2 drill 0.7mm pad 1.4mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type086_RT03405HBLC_1x05_P3.81mm_Horizontal +terminal block Metz Connect Type086_RT03405HBLC, 5 pins, pitch 3.81mm, size 18.9x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type086_RT03405HBLC pitch 3.81mm size 18.9x7.3mm^2 drill 0.7mm pad 1.4mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type086_RT03406HBLC_1x06_P3.81mm_Horizontal +terminal block Metz Connect Type086_RT03406HBLC, 6 pins, pitch 3.81mm, size 22.8x7.3mm^2, drill diamater 0.7mm, pad diameter 1.4mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_310861_RT034xxHBLC_OFF-026114K.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type086_RT03406HBLC pitch 3.81mm size 22.8x7.3mm^2 drill 0.7mm pad 1.4mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type094_RT03502HBLU_1x02_P5.00mm_Horizontal +terminal block Metz Connect Type094_RT03502HBLU, 2 pins, pitch 5mm, size 10x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type094_RT03502HBLU pitch 5mm size 10x8.3mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type094_RT03503HBLU_1x03_P5.00mm_Horizontal +terminal block Metz Connect Type094_RT03503HBLU, 3 pins, pitch 5mm, size 15x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type094_RT03503HBLU pitch 5mm size 15x8.3mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type094_RT03504HBLU_1x04_P5.00mm_Horizontal +terminal block Metz Connect Type094_RT03504HBLU, 4 pins, pitch 5mm, size 20x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type094_RT03504HBLU pitch 5mm size 20x8.3mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type094_RT03505HBLU_1x05_P5.00mm_Horizontal +terminal block Metz Connect Type094_RT03505HBLU, 5 pins, pitch 5mm, size 25x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type094_RT03505HBLU pitch 5mm size 25x8.3mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type094_RT03506HBLU_1x06_P5.00mm_Horizontal +terminal block Metz Connect Type094_RT03506HBLU, 6 pins, pitch 5mm, size 30x8.3mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/ru/system/files/productfiles/Data_sheet_310941_RT035xxHBLU_OFF-022742T.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type094_RT03506HBLU pitch 5mm size 30x8.3mm^2 drill 1.3mm pad 2.6mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type101_RT01602HBWC_1x02_P5.08mm_Horizontal +terminal block Metz Connect Type101_RT01602HBWC, 2 pins, pitch 5.08mm, size 10.2x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type101_RT01602HBWC pitch 5.08mm size 10.2x8mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type101_RT01603HBWC_1x03_P5.08mm_Horizontal +terminal block Metz Connect Type101_RT01603HBWC, 3 pins, pitch 5.08mm, size 15.2x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type101_RT01603HBWC pitch 5.08mm size 15.2x8mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type101_RT01604HBWC_1x04_P5.08mm_Horizontal +terminal block Metz Connect Type101_RT01604HBWC, 4 pins, pitch 5.08mm, size 20.3x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type101_RT01604HBWC pitch 5.08mm size 20.3x8mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type101_RT01605HBWC_1x05_P5.08mm_Horizontal +terminal block Metz Connect Type101_RT01605HBWC, 5 pins, pitch 5.08mm, size 25.4x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type101_RT01605HBWC pitch 5.08mm size 25.4x8mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type101_RT01606HBWC_1x06_P5.08mm_Horizontal +terminal block Metz Connect Type101_RT01606HBWC, 6 pins, pitch 5.08mm, size 30.5x8mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311011_RT016xxHBWC_OFF-022771S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type101_RT01606HBWC pitch 5.08mm size 30.5x8mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type171_RT13702HBWC_1x02_P7.50mm_Horizontal +terminal block Metz Connect Type171_RT13702HBWC, 2 pins, pitch 7.5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type171_RT13702HBWC pitch 7.5mm size 15x9mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type171_RT13703HBWC_1x03_P7.50mm_Horizontal +terminal block Metz Connect Type171_RT13703HBWC, 3 pins, pitch 7.5mm, size 22.5x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type171_RT13703HBWC pitch 7.5mm size 22.5x9mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type171_RT13704HBWC_1x04_P7.50mm_Horizontal +terminal block Metz Connect Type171_RT13704HBWC, 4 pins, pitch 7.5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type171_RT13704HBWC pitch 7.5mm size 30x9mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type171_RT13705HBWC_1x05_P7.50mm_Horizontal +terminal block Metz Connect Type171_RT13705HBWC, 5 pins, pitch 7.5mm, size 37.5x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type171_RT13705HBWC pitch 7.5mm size 37.5x9mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type171_RT13706HBWC_1x06_P7.50mm_Horizontal +terminal block Metz Connect Type171_RT13706HBWC, 6 pins, pitch 7.5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311711_RT137xxHBWC_OFF-022811Q.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type171_RT13706HBWC pitch 7.5mm size 45x9mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type175_RT02702HBLC_1x02_P7.50mm_Horizontal +terminal block Metz Connect Type175_RT02702HBLC, 2 pins, pitch 7.5mm, size 15x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type175_RT02702HBLC pitch 7.5mm size 15x11mm^2 drill 1.4mm pad 2.6mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type175_RT02703HBLC_1x03_P7.50mm_Horizontal +terminal block Metz Connect Type175_RT02703HBLC, 3 pins, pitch 7.5mm, size 22.5x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type175_RT02703HBLC pitch 7.5mm size 22.5x11mm^2 drill 1.4mm pad 2.6mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type175_RT02704HBLC_1x04_P7.50mm_Horizontal +terminal block Metz Connect Type175_RT02704HBLC, 4 pins, pitch 7.5mm, size 30x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type175_RT02704HBLC pitch 7.5mm size 30x11mm^2 drill 1.4mm pad 2.6mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type175_RT02705HBLC_1x05_P7.50mm_Horizontal +terminal block Metz Connect Type175_RT02705HBLC, 5 pins, pitch 7.5mm, size 37.5x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type175_RT02705HBLC pitch 7.5mm size 37.5x11mm^2 drill 1.4mm pad 2.6mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type175_RT02706HBLC_1x06_P7.50mm_Horizontal +terminal block Metz Connect Type175_RT02706HBLC, 6 pins, pitch 7.5mm, size 45x11mm^2, drill diamater 1.4mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_311751_RT027xxHBLC_OFF-022814U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type175_RT02706HBLC pitch 7.5mm size 45x11mm^2 drill 1.4mm pad 2.6mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type205_RT04502UBLC_1x02_P5.00mm_45Degree +terminal block Metz Connect Type205_RT04502UBLC, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 10x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type205_RT04502UBLC 45Degree pitch 5mm size 10x12.5mm^2 drill 1.4mm pad 2.7mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type205_RT04503UBLC_1x03_P5.00mm_45Degree +terminal block Metz Connect Type205_RT04503UBLC, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 15x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type205_RT04503UBLC 45Degree pitch 5mm size 15x12.5mm^2 drill 1.4mm pad 2.7mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type205_RT04504UBLC_1x04_P5.00mm_45Degree +terminal block Metz Connect Type205_RT04504UBLC, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 20x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type205_RT04504UBLC 45Degree pitch 5mm size 20x12.5mm^2 drill 1.4mm pad 2.7mm +0 +4 +4 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type205_RT04505UBLC_1x05_P5.00mm_45Degree +terminal block Metz Connect Type205_RT04505UBLC, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 25x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type205_RT04505UBLC 45Degree pitch 5mm size 25x12.5mm^2 drill 1.4mm pad 2.7mm +0 +5 +5 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type205_RT04506UBLC_1x06_P5.00mm_45Degree +terminal block Metz Connect Type205_RT04506UBLC, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 30x12.5mm^2, drill diamater 1.4mm, pad diameter 2.7mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_312051_RT045xxUBLC_OFF-022759T.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type205_RT04506UBLC 45Degree pitch 5mm size 30x12.5mm^2 drill 1.4mm pad 2.7mm +0 +6 +6 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type701_RT11L02HGLU_1x02_P6.35mm_Horizontal +terminal block Metz Connect Type701_RT11L02HGLU, 2 pins, pitch 6.35mm, size 12.7x12.5mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317011_RT11LxxHGLU_OFF-022798U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type701_RT11L02HGLU pitch 6.35mm size 12.7x12.5mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type701_RT11L03HGLU_1x03_P6.35mm_Horizontal +terminal block Metz Connect Type701_RT11L03HGLU, 3 pins, pitch 6.35mm, size 19x12.5mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317011_RT11LxxHGLU_OFF-022798U.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type701_RT11L03HGLU pitch 6.35mm size 19x12.5mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type703_RT10N02HGLU_1x02_P9.52mm_Horizontal +terminal block Metz Connect Type703_RT10N02HGLU, 2 pins, pitch 9.52mm, size 19x12.5mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317031_RT10NxxHGLU_OFF-022897S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type703_RT10N02HGLU pitch 9.52mm size 19x12.5mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_MetzConnect +TerminalBlock_MetzConnect_Type703_RT10N03HGLU_1x03_P9.52mm_Horizontal +terminal block Metz Connect Type703_RT10N03HGLU, 3 pins, pitch 9.52mm, size 28.6x12.5mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.metz-connect.com/de/system/files/productfiles/Datenblatt_317031_RT10NxxHGLU_OFF-022897S.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_MetzConnect +THT terminal block Metz Connect Type703_RT10N03HGLU pitch 9.52mm size 28.6x12.5mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_Philmore +TerminalBlock_Philmore_TB132_1x02_P5.00mm_Horizontal +Terminal Block Philmore , 2 pins, pitch 5mm, size 10x10.2mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Philmore +THT Terminal Block Philmore pitch 5mm size 10x10.2mm^2 drill 1.2mm pad 2.4mm +0 +2 +2 +TerminalBlock_Philmore +TerminalBlock_Philmore_TB133_1x03_P5.00mm_Horizontal +Terminal Block Philmore , 3 pins, pitch 5mm, size 15x10.2mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see http://www.philmore-datak.com/mc/Page%20197.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Philmore +THT Terminal Block Philmore pitch 5mm size 15x10.2mm^2 drill 1.2mm pad 2.4mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-2-5.08_1x02_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-2-5.08, 2 pins, pitch 5.08mm, size 10.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-2-5.08 pitch 5.08mm size 10.2x9.8mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-2, 2 pins, pitch 5mm, size 10x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-2 pitch 5mm size 10x9.8mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-3-5.08_1x03_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-3-5.08, 3 pins, pitch 5.08mm, size 15.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-3-5.08 pitch 5.08mm size 15.2x9.8mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-3_1x03_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-3, 3 pins, pitch 5mm, size 15x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-3 pitch 5mm size 15x9.8mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-4-5.08_1x04_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-4-5.08, 4 pins, pitch 5.08mm, size 20.3x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-4-5.08 pitch 5.08mm size 20.3x9.8mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-4_1x04_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-4, 4 pins, pitch 5mm, size 20x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-4 pitch 5mm size 20x9.8mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-5-5.08_1x05_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-5-5.08, 5 pins, pitch 5.08mm, size 25.4x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-5-5.08 pitch 5.08mm size 25.4x9.8mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-5_1x05_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-5, 5 pins, pitch 5mm, size 25x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-5 pitch 5mm size 25x9.8mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-6-5.08_1x06_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-6-5.08, 6 pins, pitch 5.08mm, size 30.5x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-6-5.08 pitch 5.08mm size 30.5x9.8mm^2 drill 1.3mm pad 2.6mm +0 +6 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-6_1x06_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-6, 6 pins, pitch 5mm, size 30x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-6 pitch 5mm size 30x9.8mm^2 drill 1.3mm pad 2.6mm +0 +6 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-7-5.08_1x07_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-7-5.08, 7 pins, pitch 5.08mm, size 35.6x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-7-5.08 pitch 5.08mm size 35.6x9.8mm^2 drill 1.3mm pad 2.6mm +0 +7 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-7_1x07_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-7, 7 pins, pitch 5mm, size 35x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-7 pitch 5mm size 35x9.8mm^2 drill 1.3mm pad 2.6mm +0 +7 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-8-5.08_1x08_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-8-5.08, 8 pins, pitch 5.08mm, size 40.6x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-8-5.08 pitch 5.08mm size 40.6x9.8mm^2 drill 1.3mm pad 2.6mm +0 +8 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-8_1x08_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-8, 8 pins, pitch 5mm, size 40x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-8 pitch 5mm size 40x9.8mm^2 drill 1.3mm pad 2.6mm +0 +8 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-9-5.08_1x09_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-9-5.08, 9 pins, pitch 5.08mm, size 45.7x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-9-5.08 pitch 5.08mm size 45.7x9.8mm^2 drill 1.3mm pad 2.6mm +0 +9 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-9_1x09_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-9, 9 pins, pitch 5mm, size 45x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-9 pitch 5mm size 45x9.8mm^2 drill 1.3mm pad 2.6mm +0 +9 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-10-5.08_1x10_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-10-5.08, 10 pins, pitch 5.08mm, size 50.8x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-10-5.08 pitch 5.08mm size 50.8x9.8mm^2 drill 1.3mm pad 2.6mm +0 +10 +10 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-10_1x10_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-10, 10 pins, pitch 5mm, size 50x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-10 pitch 5mm size 50x9.8mm^2 drill 1.3mm pad 2.6mm +0 +10 +10 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-11-5.08_1x11_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-11-5.08, 11 pins, pitch 5.08mm, size 55.9x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-11-5.08 pitch 5.08mm size 55.9x9.8mm^2 drill 1.3mm pad 2.6mm +0 +11 +11 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-11_1x11_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-11, 11 pins, pitch 5mm, size 55x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-11 pitch 5mm size 55x9.8mm^2 drill 1.3mm pad 2.6mm +0 +11 +11 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-12-5.08_1x12_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-12-5.08, 12 pins, pitch 5.08mm, size 61x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-12-5.08 pitch 5.08mm size 61x9.8mm^2 drill 1.3mm pad 2.6mm +0 +12 +12 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-12_1x12_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-12, 12 pins, pitch 5mm, size 60x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-12 pitch 5mm size 60x9.8mm^2 drill 1.3mm pad 2.6mm +0 +12 +12 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-13-5.08_1x13_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-13-5.08, 13 pins, pitch 5.08mm, size 66x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-13-5.08 pitch 5.08mm size 66x9.8mm^2 drill 1.3mm pad 2.6mm +0 +13 +13 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-13_1x13_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-13, 13 pins, pitch 5mm, size 65x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-13 pitch 5mm size 65x9.8mm^2 drill 1.3mm pad 2.6mm +0 +13 +13 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-14-5.08_1x14_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-14-5.08, 14 pins, pitch 5.08mm, size 71.1x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-14-5.08 pitch 5.08mm size 71.1x9.8mm^2 drill 1.3mm pad 2.6mm +0 +14 +14 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-14_1x14_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-14, 14 pins, pitch 5mm, size 70x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-14 pitch 5mm size 70x9.8mm^2 drill 1.3mm pad 2.6mm +0 +14 +14 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-15-5.08_1x15_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-15-5.08, 15 pins, pitch 5.08mm, size 76.2x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-15-5.08 pitch 5.08mm size 76.2x9.8mm^2 drill 1.3mm pad 2.6mm +0 +15 +15 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-15_1x15_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-15, 15 pins, pitch 5mm, size 75x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-15 pitch 5mm size 75x9.8mm^2 drill 1.3mm pad 2.6mm +0 +15 +15 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-16-5.08_1x16_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-1,5-16-5.08, 16 pins, pitch 5.08mm, size 81.3x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-16-5.08 pitch 5.08mm size 81.3x9.8mm^2 drill 1.3mm pad 2.6mm +0 +16 +16 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-1,5-16_1x16_P5.00mm_Horizontal +Terminal Block Phoenix MKDS-1,5-16, 16 pins, pitch 5mm, size 80x9.8mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-1,5-16 pitch 5mm size 80x9.8mm^2 drill 1.3mm pad 2.6mm +0 +16 +16 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-2-5.08_1x02_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-2-5.08, 2 pins, pitch 5.08mm, size 10.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-2-5.08 pitch 5.08mm size 10.2x11.2mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-3-5.08_1x03_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-3-5.08, 3 pins, pitch 5.08mm, size 15.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-3-5.08 pitch 5.08mm size 15.2x11.2mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-4-5.08_1x04_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-4-5.08, 4 pins, pitch 5.08mm, size 20.3x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-4-5.08 pitch 5.08mm size 20.3x11.2mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-5-5.08_1x05_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-5-5.08, 5 pins, pitch 5.08mm, size 25.4x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-5-5.08 pitch 5.08mm size 25.4x11.2mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-6-5.08_1x06_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-6-5.08, 6 pins, pitch 5.08mm, size 30.5x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-6-5.08 pitch 5.08mm size 30.5x11.2mm^2 drill 1.3mm pad 2.6mm +0 +6 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-7-5.08_1x07_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-7-5.08, 7 pins, pitch 5.08mm, size 35.6x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-7-5.08 pitch 5.08mm size 35.6x11.2mm^2 drill 1.3mm pad 2.6mm +0 +7 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-8-5.08_1x08_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-8-5.08, 8 pins, pitch 5.08mm, size 40.6x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-8-5.08 pitch 5.08mm size 40.6x11.2mm^2 drill 1.3mm pad 2.6mm +0 +8 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-9-5.08_1x09_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-9-5.08, 9 pins, pitch 5.08mm, size 45.7x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-9-5.08 pitch 5.08mm size 45.7x11.2mm^2 drill 1.3mm pad 2.6mm +0 +9 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-10-5.08_1x10_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-10-5.08, 10 pins, pitch 5.08mm, size 50.8x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-10-5.08 pitch 5.08mm size 50.8x11.2mm^2 drill 1.3mm pad 2.6mm +0 +10 +10 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-11-5.08_1x11_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-11-5.08, 11 pins, pitch 5.08mm, size 55.9x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-11-5.08 pitch 5.08mm size 55.9x11.2mm^2 drill 1.3mm pad 2.6mm +0 +11 +11 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-12-5.08_1x12_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-12-5.08, 12 pins, pitch 5.08mm, size 61x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-12-5.08 pitch 5.08mm size 61x11.2mm^2 drill 1.3mm pad 2.6mm +0 +12 +12 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-13-5.08_1x13_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-13-5.08, 13 pins, pitch 5.08mm, size 66x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-13-5.08 pitch 5.08mm size 66x11.2mm^2 drill 1.3mm pad 2.6mm +0 +13 +13 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-14-5.08_1x14_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-14-5.08, 14 pins, pitch 5.08mm, size 71.1x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-14-5.08 pitch 5.08mm size 71.1x11.2mm^2 drill 1.3mm pad 2.6mm +0 +14 +14 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-15-5.08_1x15_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-15-5.08, 15 pins, pitch 5.08mm, size 76.2x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-15-5.08 pitch 5.08mm size 76.2x11.2mm^2 drill 1.3mm pad 2.6mm +0 +15 +15 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MKDS-3-16-5.08_1x16_P5.08mm_Horizontal +Terminal Block Phoenix MKDS-3-16-5.08, 16 pins, pitch 5.08mm, size 81.3x11.2mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/2138224.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MKDS-3-16-5.08 pitch 5.08mm size 81.3x11.2mm^2 drill 1.3mm pad 2.6mm +0 +16 +16 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-2-2.54_1x02_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-2-2.54, 2 pins, pitch 2.54mm, size 5.54x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725656-920552.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-2-2.54 pitch 2.54mm size 5.54x6.2mm^2 drill 1.1mm pad 2.2mm +0 +2 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-3-2.54_1x03_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-3-2.54, 3 pins, pitch 2.54mm, size 8.08x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725656-920552.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-3-2.54 pitch 2.54mm size 8.08x6.2mm^2 drill 1.1mm pad 2.2mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-4-2.54_1x04_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-4-2.54, 4 pins, pitch 2.54mm, size 10.6x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-4-2.54 pitch 2.54mm size 10.6x6.2mm^2 drill 1.1mm pad 2.2mm +0 +4 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-5-2.54_1x05_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-5-2.54, 5 pins, pitch 2.54mm, size 13.2x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-5-2.54 pitch 2.54mm size 13.2x6.2mm^2 drill 1.1mm pad 2.2mm +0 +5 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-6-2.54_1x06_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-6-2.54, 6 pins, pitch 2.54mm, size 15.7x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-6-2.54 pitch 2.54mm size 15.7x6.2mm^2 drill 1.1mm pad 2.2mm +0 +6 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-7-2.54_1x07_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-7-2.54, 7 pins, pitch 2.54mm, size 18.2x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-7-2.54 pitch 2.54mm size 18.2x6.2mm^2 drill 1.1mm pad 2.2mm +0 +7 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-8-2.54_1x08_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-8-2.54, 8 pins, pitch 2.54mm, size 20.8x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-8-2.54 pitch 2.54mm size 20.8x6.2mm^2 drill 1.1mm pad 2.2mm +0 +8 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-9-2.54_1x09_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-9-2.54, 9 pins, pitch 2.54mm, size 23.3x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-9-2.54 pitch 2.54mm size 23.3x6.2mm^2 drill 1.1mm pad 2.2mm +0 +9 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-10-2.54_1x10_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-10-2.54, 10 pins, pitch 2.54mm, size 25.9x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-10-2.54 pitch 2.54mm size 25.9x6.2mm^2 drill 1.1mm pad 2.2mm +0 +10 +10 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-11-2.54_1x11_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-11-2.54, 11 pins, pitch 2.54mm, size 28.4x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-11-2.54 pitch 2.54mm size 28.4x6.2mm^2 drill 1.1mm pad 2.2mm +0 +11 +11 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_MPT-0,5-12-2.54_1x12_P2.54mm_Horizontal +Terminal Block Phoenix MPT-0,5-12-2.54, 12 pins, pitch 2.54mm, size 30.9x6.2mm^2, drill diamater 1.1mm, pad diameter 2.2mm, see http://www.mouser.com/ds/2/324/ItemDetail_1725672-916605.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix MPT-0,5-12-2.54 pitch 2.54mm size 30.9x6.2mm^2 drill 1.1mm pad 2.2mm +0 +12 +12 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-2-3.5-H_1x02_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-2-3.5-H, 2 pins, pitch 3.5mm, size 7x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-2-3.5-H pitch 3.5mm size 7x7.6mm^2 drill 1.2mm pad 2.4mm +0 +2 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-2-5.0-H_1x02_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-2-5.0-H, 2 pins, pitch 5mm, size 10x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-2-5.0-H pitch 5mm size 10x9mm^2 drill 1.3mm pad 2.6mm +0 +2 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-3-3.5-H_1x03_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-3-3.5-H, 3 pins, pitch 3.5mm, size 10.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-3-3.5-H pitch 3.5mm size 10.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-3-5.0-H_1x03_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-3-5.0-H, 3 pins, pitch 5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-3-5.0-H pitch 5mm size 15x9mm^2 drill 1.3mm pad 2.6mm +0 +3 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-4-3.5-H_1x04_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-4-3.5-H, 4 pins, pitch 3.5mm, size 14x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-4-3.5-H pitch 3.5mm size 14x7.6mm^2 drill 1.2mm pad 2.4mm +0 +4 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-4-5.0-H_1x04_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-4-5.0-H, 4 pins, pitch 5mm, size 20x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-4-5.0-H pitch 5mm size 20x9mm^2 drill 1.3mm pad 2.6mm +0 +4 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-5-3.5-H_1x05_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-5-3.5-H, 5 pins, pitch 3.5mm, size 17.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-5-3.5-H pitch 3.5mm size 17.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +5 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-5-5.0-H_1x05_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-5-5.0-H, 5 pins, pitch 5mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-5-5.0-H pitch 5mm size 25x9mm^2 drill 1.3mm pad 2.6mm +0 +5 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-6-3.5-H_1x06_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-6-3.5-H, 6 pins, pitch 3.5mm, size 21x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-6-3.5-H pitch 3.5mm size 21x7.6mm^2 drill 1.2mm pad 2.4mm +0 +6 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-6-5.0-H_1x06_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-6-5.0-H, 6 pins, pitch 5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-6-5.0-H pitch 5mm size 30x9mm^2 drill 1.3mm pad 2.6mm +0 +6 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-7-3.5-H_1x07_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-7-3.5-H, 7 pins, pitch 3.5mm, size 24.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-7-3.5-H pitch 3.5mm size 24.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +7 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-7-5.0-H_1x07_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-7-5.0-H, 7 pins, pitch 5mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-7-5.0-H pitch 5mm size 35x9mm^2 drill 1.3mm pad 2.6mm +0 +7 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-8-3.5-H_1x08_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-8-3.5-H, 8 pins, pitch 3.5mm, size 28x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-8-3.5-H pitch 3.5mm size 28x7.6mm^2 drill 1.2mm pad 2.4mm +0 +8 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-8-5.0-H_1x08_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-8-5.0-H, 8 pins, pitch 5mm, size 40x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-8-5.0-H pitch 5mm size 40x9mm^2 drill 1.3mm pad 2.6mm +0 +8 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-9-3.5-H_1x09_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-9-3.5-H, 9 pins, pitch 3.5mm, size 31.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-9-3.5-H pitch 3.5mm size 31.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +9 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-9-5.0-H_1x09_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-9-5.0-H, 9 pins, pitch 5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-9-5.0-H pitch 5mm size 45x9mm^2 drill 1.3mm pad 2.6mm +0 +9 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-10-3.5-H_1x10_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-10-3.5-H, 10 pins, pitch 3.5mm, size 35x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-10-3.5-H pitch 3.5mm size 35x7.6mm^2 drill 1.2mm pad 2.4mm +0 +10 +10 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-10-5.0-H_1x10_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-10-5.0-H, 10 pins, pitch 5mm, size 50x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-10-5.0-H pitch 5mm size 50x9mm^2 drill 1.3mm pad 2.6mm +0 +10 +10 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-11-3.5-H_1x11_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-11-3.5-H, 11 pins, pitch 3.5mm, size 38.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-11-3.5-H pitch 3.5mm size 38.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +11 +11 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-11-5.0-H_1x11_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-11-5.0-H, 11 pins, pitch 5mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-11-5.0-H pitch 5mm size 55x9mm^2 drill 1.3mm pad 2.6mm +0 +11 +11 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-12-3.5-H_1x12_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-12-3.5-H, 12 pins, pitch 3.5mm, size 42x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-12-3.5-H pitch 3.5mm size 42x7.6mm^2 drill 1.2mm pad 2.4mm +0 +12 +12 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-12-5.0-H_1x12_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-12-5.0-H, 12 pins, pitch 5mm, size 60x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-12-5.0-H pitch 5mm size 60x9mm^2 drill 1.3mm pad 2.6mm +0 +12 +12 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-13-3.5-H_1x13_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-13-3.5-H, 13 pins, pitch 3.5mm, size 45.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-13-3.5-H pitch 3.5mm size 45.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +13 +13 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-13-5.0-H_1x13_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-13-5.0-H, 13 pins, pitch 5mm, size 65x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-13-5.0-H pitch 5mm size 65x9mm^2 drill 1.3mm pad 2.6mm +0 +13 +13 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-14-3.5-H_1x14_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-14-3.5-H, 14 pins, pitch 3.5mm, size 49x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-14-3.5-H pitch 3.5mm size 49x7.6mm^2 drill 1.2mm pad 2.4mm +0 +14 +14 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-14-5.0-H_1x14_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-14-5.0-H, 14 pins, pitch 5mm, size 70x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-14-5.0-H pitch 5mm size 70x9mm^2 drill 1.3mm pad 2.6mm +0 +14 +14 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-15-3.5-H_1x15_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-15-3.5-H, 15 pins, pitch 3.5mm, size 52.5x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-15-3.5-H pitch 3.5mm size 52.5x7.6mm^2 drill 1.2mm pad 2.4mm +0 +15 +15 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-15-5.0-H_1x15_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-15-5.0-H, 15 pins, pitch 5mm, size 75x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-15-5.0-H pitch 5mm size 75x9mm^2 drill 1.3mm pad 2.6mm +0 +15 +15 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-16-3.5-H_1x16_P3.50mm_Horizontal +Terminal Block Phoenix PT-1,5-16-3.5-H, 16 pins, pitch 3.5mm, size 56x7.6mm^2, drill diamater 1.2mm, pad diameter 2.4mm, see , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-16-3.5-H pitch 3.5mm size 56x7.6mm^2 drill 1.2mm pad 2.4mm +0 +16 +16 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PT-1,5-16-5.0-H_1x16_P5.00mm_Horizontal +Terminal Block Phoenix PT-1,5-16-5.0-H, 16 pins, pitch 5mm, size 80x9mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.mouser.com/ds/2/324/ItemDetail_1935161-922578.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PT-1,5-16-5.0-H pitch 5mm size 80x9mm^2 drill 1.3mm pad 2.6mm +0 +16 +16 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-2-2,5-V-SMD_1x02-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 2 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814702/pdf +PhoenixContact PTSM0.5 2 2.5mm vertical SMD spring clamp terminal block connector +0 +4 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-2-2.5-H-THR_1x02_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR, 2 pins, pitch 2.5mm, size 7.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-2-2.5-H-THR pitch 2.5mm size 7.2x10mm^2 drill 1.2mm pad 3mm +0 +4 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-2-2.5-V-THR_1x02_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-2-2.5-V-THR, vertical (cable from top), 2 pins, pitch 2.5mm, size 5.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-2-2.5-V-THR vertical pitch 2.5mm size 5.5x5mm^2 drill 1.2mm pad 2mm +0 +4 +2 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-2-HV-2.5-SMD_1x02-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 2 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778696/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +4 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-3-2,5-V-SMD_1x03-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 3 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814715/pdf +PhoenixContact PTSM0.5 3 2.5mm vertical SMD spring clamp terminal block connector +0 +5 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-3-2.5-H-THR_1x03_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR, 3 pins, pitch 2.5mm, size 9.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-3-2.5-H-THR pitch 2.5mm size 9.7x10mm^2 drill 1.2mm pad 3mm +0 +6 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-3-2.5-V-THR_1x03_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-3-2.5-V-THR, vertical (cable from top), 3 pins, pitch 2.5mm, size 8x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-3-2.5-V-THR vertical pitch 2.5mm size 8x5mm^2 drill 1.2mm pad 2mm +0 +6 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-3-HV-2.5-SMD_1x03-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 3 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778706/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +5 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-4-2,5-V-SMD_1x04-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 4 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814728/pdf +PhoenixContact PTSM0.5 4 2.5mm vertical SMD spring clamp terminal block connector +0 +6 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-4-2.5-H-THR_1x04_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR, 4 pins, pitch 2.5mm, size 12.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-4-2.5-H-THR pitch 2.5mm size 12.2x10mm^2 drill 1.2mm pad 3mm +0 +8 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-4-2.5-V-THR_1x04_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-4-2.5-V-THR, vertical (cable from top), 4 pins, pitch 2.5mm, size 10.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-4-2.5-V-THR vertical pitch 2.5mm size 10.5x5mm^2 drill 1.2mm pad 2mm +0 +8 +4 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-4-HV-2.5-SMD_1x04-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 4 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778719/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +4 +3 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-5-2,5-V-SMD_1x05-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 5 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814731/pdf +PhoenixContact PTSM0.5 5 2.5mm vertical SMD spring clamp terminal block connector +0 +7 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-5-2.5-H-THR_1x05_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-5-2.5-H-THR, 5 pins, pitch 2.5mm, size 14.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-5-2.5-H-THR pitch 2.5mm size 14.7x10mm^2 drill 1.2mm pad 3mm +0 +10 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-5-2.5-V-THR_1x05_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-5-2.5-V-THR, vertical (cable from top), 5 pins, pitch 2.5mm, size 13x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-5-2.5-V-THR vertical pitch 2.5mm size 13x5mm^2 drill 1.2mm pad 2mm +0 +10 +5 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-5-HV-2.5-SMD_1x05-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 5 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778722/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +7 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-6-2,5-V-SMD_1x06-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 6 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814744/pdf +PhoenixContact PTSM0.5 6 2.5mm vertical SMD spring clamp terminal block connector +0 +8 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-6-2.5-H-THR_1x06_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-6-2.5-H-THR, 6 pins, pitch 2.5mm, size 17.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-6-2.5-H-THR pitch 2.5mm size 17.2x10mm^2 drill 1.2mm pad 3mm +0 +12 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-6-2.5-V-THR_1x06_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-6-2.5-V-THR, vertical (cable from top), 6 pins, pitch 2.5mm, size 15.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-6-2.5-V-THR vertical pitch 2.5mm size 15.5x5mm^2 drill 1.2mm pad 2mm +0 +12 +6 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-6-HV-2.5-SMD_1x06-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 6 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778735/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +8 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-7-2,5-V-SMD_1x07-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 7 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814757/pdf +PhoenixContact PTSM0.5 7 2.5mm vertical SMD spring clamp terminal block connector +0 +9 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-7-2.5-H-THR_1x07_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-7-2.5-H-THR, 7 pins, pitch 2.5mm, size 19.7x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-7-2.5-H-THR pitch 2.5mm size 19.7x10mm^2 drill 1.2mm pad 3mm +0 +14 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-7-2.5-V-THR_1x07_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-7-2.5-V-THR, vertical (cable from top), 7 pins, pitch 2.5mm, size 18x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-7-2.5-V-THR vertical pitch 2.5mm size 18x5mm^2 drill 1.2mm pad 2mm +0 +14 +7 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-7-HV-2.5-SMD_1x07-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 7 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778748/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +9 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-8-2,5-V-SMD_1x08-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 8 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1814760/pdf +PhoenixContact PTSM0.5 8 2.5mm vertical SMD spring clamp terminal block connector +0 +10 +9 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-8-2.5-H-THR_1x08_P2.50mm_Horizontal +Terminal Block Phoenix PTSM-0,5-8-2.5-H-THR, 8 pins, pitch 2.5mm, size 22.2x10mm^2, drill diamater 1.2mm, pad diameter 3mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556441-da-01-de-LEITERPLATTENKL__PTSM_0_5__8_2_5_H_THR.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-8-2.5-H-THR pitch 2.5mm size 22.2x10mm^2 drill 1.2mm pad 3mm +0 +16 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-8-2.5-V-THR_1x08_P2.50mm_Vertical +Terminal Block Phoenix PTSM-0,5-8-2.5-V-THR, vertical (cable from top), 8 pins, pitch 2.5mm, size 20.5x5mm^2, drill diamater 1.2mm, pad diameter 2mm, see http://www.produktinfo.conrad.com/datenblaetter/550000-574999/556444-da-01-de-LEITERPLATTENKL__PTSM_0_5__4_2_5_V_THR.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_Phoenix +THT Terminal Block Phoenix PTSM-0,5-8-2.5-V-THR vertical pitch 2.5mm size 20.5x5mm^2 drill 1.2mm pad 2mm +0 +16 +8 +TerminalBlock_Phoenix +TerminalBlock_Phoenix_PTSM-0,5-8-HV-2.5-SMD_1x08-1MP_P2.50mm_Vertical +PhoenixContact PTSM0,5 8 HV 2,5mm vertical SMD spring clamp terminal block connector http://www.phoenixcontact.com/us/products/1778751/pdf +2.5mm vertical SMD spring clamp terminal block connector +0 +10 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00001_1x02_P5.00mm_Horizontal +terminal block RND 205-00001, 2 pins, pitch 5mm, size 10x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00001 pitch 5mm size 10x9mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00002_1x03_P5.00mm_Horizontal +terminal block RND 205-00002, 3 pins, pitch 5mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00002 pitch 5mm size 15x9mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00003_1x04_P5.00mm_Horizontal +terminal block RND 205-00003, 4 pins, pitch 5mm, size 20x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00003 pitch 5mm size 20x9mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00004_1x05_P5.00mm_Horizontal +terminal block RND 205-00004, 5 pins, pitch 5mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00004 pitch 5mm size 25x9mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00005_1x06_P5.00mm_Horizontal +terminal block RND 205-00005, 6 pins, pitch 5mm, size 30x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00005 pitch 5mm size 30x9mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00006_1x07_P5.00mm_Horizontal +terminal block RND 205-00006, 7 pins, pitch 5mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00006 pitch 5mm size 35x9mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00007_1x08_P5.00mm_Horizontal +terminal block RND 205-00007, 8 pins, pitch 5mm, size 40x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00007 pitch 5mm size 40x9mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00008_1x09_P5.00mm_Horizontal +terminal block RND 205-00008, 9 pins, pitch 5mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00008 pitch 5mm size 45x9mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00009_1x10_P5.00mm_Horizontal +terminal block RND 205-00009, 10 pins, pitch 5mm, size 50x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00009 pitch 5mm size 50x9mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00010_1x11_P5.00mm_Horizontal +terminal block RND 205-00010, 11 pins, pitch 5mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00010 pitch 5mm size 55x9mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00011_1x12_P5.00mm_Horizontal +terminal block RND 205-00011, 12 pins, pitch 5mm, size 60x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00001_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00011 pitch 5mm size 60x9mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00012_1x02_P5.00mm_Horizontal +terminal block RND 205-00012, 2 pins, pitch 5mm, size 10x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00012 pitch 5mm size 10x7.6mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00013_1x03_P5.00mm_Horizontal +terminal block RND 205-00013, 3 pins, pitch 5mm, size 15x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00013 pitch 5mm size 15x7.6mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00014_1x04_P5.00mm_Horizontal +terminal block RND 205-00014, 4 pins, pitch 5mm, size 20x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00014 pitch 5mm size 20x7.6mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00015_1x05_P5.00mm_Horizontal +terminal block RND 205-00015, 5 pins, pitch 5mm, size 25x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00015 pitch 5mm size 25x7.6mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00016_1x06_P5.00mm_Horizontal +terminal block RND 205-00016, 6 pins, pitch 5mm, size 30x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00016 pitch 5mm size 30x7.6mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00017_1x07_P5.00mm_Horizontal +terminal block RND 205-00017, 7 pins, pitch 5mm, size 35x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00017 pitch 5mm size 35x7.6mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00018_1x08_P5.00mm_Horizontal +terminal block RND 205-00018, 8 pins, pitch 5mm, size 40x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00018 pitch 5mm size 40x7.6mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00019_1x09_P5.00mm_Horizontal +terminal block RND 205-00019, 9 pins, pitch 5mm, size 45x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00019 pitch 5mm size 45x7.6mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00020_1x10_P5.00mm_Horizontal +terminal block RND 205-00020, 10 pins, pitch 5mm, size 50x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00020 pitch 5mm size 50x7.6mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00021_1x11_P5.00mm_Horizontal +terminal block RND 205-00021, 11 pins, pitch 5mm, size 55x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00021 pitch 5mm size 55x7.6mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00022_1x12_P5.00mm_Horizontal +terminal block RND 205-00022, 12 pins, pitch 5mm, size 60x7.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00012_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00022 pitch 5mm size 60x7.6mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00023_1x02_P10.00mm_Horizontal +terminal block RND 205-00023, 2 pins, pitch 10mm, size 15x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00023 pitch 10mm size 15x9mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00024_1x03_P10.00mm_Horizontal +terminal block RND 205-00024, 3 pins, pitch 10mm, size 25x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00024 pitch 10mm size 25x9mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00025_1x04_P10.00mm_Horizontal +terminal block RND 205-00025, 4 pins, pitch 10mm, size 35x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00025 pitch 10mm size 35x9mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00026_1x05_P10.00mm_Horizontal +terminal block RND 205-00026, 5 pins, pitch 10mm, size 45x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00026 pitch 10mm size 45x9mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00027_1x06_P10.00mm_Horizontal +terminal block RND 205-00027, 6 pins, pitch 10mm, size 55x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00027 pitch 10mm size 55x9mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00028_1x07_P10.00mm_Horizontal +terminal block RND 205-00028, 7 pins, pitch 10mm, size 65x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00028 pitch 10mm size 65x9mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00029_1x08_P10.00mm_Horizontal +terminal block RND 205-00029, 8 pins, pitch 10mm, size 75x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00029 pitch 10mm size 75x9mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00030_1x09_P10.00mm_Horizontal +terminal block RND 205-00030, 9 pins, pitch 10mm, size 85x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00030 pitch 10mm size 85x9mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00031_1x10_P10.00mm_Horizontal +terminal block RND 205-00031, 10 pins, pitch 10mm, size 95x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00031 pitch 10mm size 95x9mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00032_1x11_P10.00mm_Horizontal +terminal block RND 205-00032, 11 pins, pitch 10mm, size 105x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00032 pitch 10mm size 105x9mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00033_1x12_P10.00mm_Horizontal +terminal block RND 205-00033, 12 pins, pitch 10mm, size 115x9mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00033 pitch 10mm size 115x9mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00045_1x02_P5.00mm_Horizontal +terminal block RND 205-00045, 2 pins, pitch 5mm, size 10x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00045 pitch 5mm size 10x8.1mm^2 drill 1.1mm pad 2.1mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00046_1x03_P5.00mm_Horizontal +terminal block RND 205-00046, 3 pins, pitch 5mm, size 15x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00046 pitch 5mm size 15x8.1mm^2 drill 1.1mm pad 2.1mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00047_1x04_P5.00mm_Horizontal +terminal block RND 205-00047, 4 pins, pitch 5mm, size 20x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00047 pitch 5mm size 20x8.1mm^2 drill 1.1mm pad 2.1mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00048_1x05_P5.00mm_Horizontal +terminal block RND 205-00048, 5 pins, pitch 5mm, size 25x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00048 pitch 5mm size 25x8.1mm^2 drill 1.1mm pad 2.1mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00049_1x06_P5.00mm_Horizontal +terminal block RND 205-00049, 6 pins, pitch 5mm, size 30x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00049 pitch 5mm size 30x8.1mm^2 drill 1.1mm pad 2.1mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00050_1x07_P5.00mm_Horizontal +terminal block RND 205-00050, 7 pins, pitch 5mm, size 35x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00050 pitch 5mm size 35x8.1mm^2 drill 1.1mm pad 2.1mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00051_1x08_P5.00mm_Horizontal +terminal block RND 205-00051, 8 pins, pitch 5mm, size 40x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00051 pitch 5mm size 40x8.1mm^2 drill 1.1mm pad 2.1mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00052_1x09_P5.00mm_Horizontal +terminal block RND 205-00052, 9 pins, pitch 5mm, size 45x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00052 pitch 5mm size 45x8.1mm^2 drill 1.1mm pad 2.1mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00053_1x10_P5.00mm_Horizontal +terminal block RND 205-00053, 10 pins, pitch 5mm, size 50x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00053 pitch 5mm size 50x8.1mm^2 drill 1.1mm pad 2.1mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00054_1x11_P5.00mm_Horizontal +terminal block RND 205-00054, 11 pins, pitch 5mm, size 55x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00054 pitch 5mm size 55x8.1mm^2 drill 1.1mm pad 2.1mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00055_1x12_P5.00mm_Horizontal +terminal block RND 205-00055, 12 pins, pitch 5mm, size 60x8.1mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00045_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00055 pitch 5mm size 60x8.1mm^2 drill 1.1mm pad 2.1mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00056_1x02_P5.00mm_45Degree +terminal block RND 205-00056, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 10x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00056 45Degree pitch 5mm size 10x12.6mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00057_1x03_P5.00mm_45Degree +terminal block RND 205-00057, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 15x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00057 45Degree pitch 5mm size 15x12.6mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00058_1x04_P5.00mm_45Degree +terminal block RND 205-00058, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 20x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00058 45Degree pitch 5mm size 20x12.6mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00059_1x05_P5.00mm_45Degree +terminal block RND 205-00059, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 25x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00059 45Degree pitch 5mm size 25x12.6mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00060_1x06_P5.00mm_45Degree +terminal block RND 205-00060, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 30x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00060 45Degree pitch 5mm size 30x12.6mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00061_1x07_P5.00mm_45Degree +terminal block RND 205-00061, 45Degree (cable under 45degree), 7 pins, pitch 5mm, size 35x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00061 45Degree pitch 5mm size 35x12.6mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00062_1x08_P5.00mm_45Degree +terminal block RND 205-00062, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 40x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00062 45Degree pitch 5mm size 40x12.6mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00063_1x09_P5.00mm_45Degree +terminal block RND 205-00063, 45Degree (cable under 45degree), 9 pins, pitch 5mm, size 45x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00063 45Degree pitch 5mm size 45x12.6mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00064_1x10_P5.00mm_45Degree +terminal block RND 205-00064, 45Degree (cable under 45degree), 10 pins, pitch 5mm, size 50x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00064 45Degree pitch 5mm size 50x12.6mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00065_1x11_P5.00mm_45Degree +terminal block RND 205-00065, 45Degree (cable under 45degree), 11 pins, pitch 5mm, size 55x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00065 45Degree pitch 5mm size 55x12.6mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00066_1x12_P5.00mm_45Degree +terminal block RND 205-00066, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 60x12.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00056_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00066 45Degree pitch 5mm size 60x12.6mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00067_1x02_P7.50mm_Horizontal +terminal block RND 205-00067, 2 pins, pitch 7.5mm, size 15x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00067 pitch 7.5mm size 15x10.3mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00068_1x03_P7.50mm_Horizontal +terminal block RND 205-00068, 3 pins, pitch 7.5mm, size 22.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00068 pitch 7.5mm size 22.5x10.3mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00069_1x04_P7.50mm_Horizontal +terminal block RND 205-00069, 4 pins, pitch 7.5mm, size 30x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00069 pitch 7.5mm size 30x10.3mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00070_1x05_P7.50mm_Horizontal +terminal block RND 205-00070, 5 pins, pitch 7.5mm, size 37.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00070 pitch 7.5mm size 37.5x10.3mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00071_1x06_P7.50mm_Horizontal +terminal block RND 205-00071, 6 pins, pitch 7.5mm, size 45x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00071 pitch 7.5mm size 45x10.3mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00072_1x07_P7.50mm_Horizontal +terminal block RND 205-00072, 7 pins, pitch 7.5mm, size 52.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00072 pitch 7.5mm size 52.5x10.3mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00073_1x08_P7.50mm_Horizontal +terminal block RND 205-00073, 8 pins, pitch 7.5mm, size 60x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00073 pitch 7.5mm size 60x10.3mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00074_1x09_P7.50mm_Horizontal +terminal block RND 205-00074, 9 pins, pitch 7.5mm, size 67.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00074 pitch 7.5mm size 67.5x10.3mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00075_1x10_P7.50mm_Horizontal +terminal block RND 205-00075, 10 pins, pitch 7.5mm, size 75x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00075 pitch 7.5mm size 75x10.3mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00076_1x11_P7.50mm_Horizontal +terminal block RND 205-00076, 11 pins, pitch 7.5mm, size 82.5x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00076 pitch 7.5mm size 82.5x10.3mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00077_1x12_P7.50mm_Horizontal +terminal block RND 205-00077, 12 pins, pitch 7.5mm, size 90x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00067_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00077 pitch 7.5mm size 90x10.3mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00078_1x02_P10.00mm_Horizontal +terminal block RND 205-00078, 2 pins, pitch 10mm, size 15x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00078 pitch 10mm size 15x10.3mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00079_1x03_P10.00mm_Horizontal +terminal block RND 205-00079, 3 pins, pitch 10mm, size 25x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00079 pitch 10mm size 25x10.3mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00080_1x04_P10.00mm_Horizontal +terminal block RND 205-00080, 4 pins, pitch 10mm, size 35x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00080 pitch 10mm size 35x10.3mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00081_1x05_P10.00mm_Horizontal +terminal block RND 205-00081, 5 pins, pitch 10mm, size 45x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00081 pitch 10mm size 45x10.3mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00082_1x06_P10.00mm_Horizontal +terminal block RND 205-00082, 6 pins, pitch 10mm, size 55x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00082 pitch 10mm size 55x10.3mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00083_1x07_P10.00mm_Horizontal +terminal block RND 205-00083, 7 pins, pitch 10mm, size 65x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00083 pitch 10mm size 65x10.3mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00084_1x08_P10.00mm_Horizontal +terminal block RND 205-00084, 8 pins, pitch 10mm, size 75x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00084 pitch 10mm size 75x10.3mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00085_1x09_P10.00mm_Horizontal +terminal block RND 205-00085, 9 pins, pitch 10mm, size 85x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00085 pitch 10mm size 85x10.3mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00086_1x10_P10.00mm_Horizontal +terminal block RND 205-00086, 10 pins, pitch 10mm, size 95x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00086 pitch 10mm size 95x10.3mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00087_1x11_P10.00mm_Horizontal +terminal block RND 205-00087, 11 pins, pitch 10mm, size 105x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00087 pitch 10mm size 105x10.3mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00088_1x12_P10.00mm_Horizontal +terminal block RND 205-00088, 12 pins, pitch 10mm, size 115x10.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00078_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00088 pitch 10mm size 115x10.3mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00232_1x02_P5.08mm_Horizontal +terminal block RND 205-00232, 2 pins, pitch 5.08mm, size 10.2x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00232 pitch 5.08mm size 10.2x8.45mm^2 drill 1.1mm pad 2.1mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00233_1x03_P5.08mm_Horizontal +terminal block RND 205-00233, 3 pins, pitch 5.08mm, size 15.2x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00233 pitch 5.08mm size 15.2x8.45mm^2 drill 1.1mm pad 2.1mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00234_1x04_P5.08mm_Horizontal +terminal block RND 205-00234, 4 pins, pitch 5.08mm, size 20.3x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00234 pitch 5.08mm size 20.3x8.45mm^2 drill 1.1mm pad 2.1mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00235_1x05_P5.08mm_Horizontal +terminal block RND 205-00235, 5 pins, pitch 5.08mm, size 25.4x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00235 pitch 5.08mm size 25.4x8.45mm^2 drill 1.1mm pad 2.1mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00236_1x06_P5.08mm_Horizontal +terminal block RND 205-00236, 6 pins, pitch 5.08mm, size 30.5x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00236 pitch 5.08mm size 30.5x8.45mm^2 drill 1.1mm pad 2.1mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00237_1x07_P5.08mm_Horizontal +terminal block RND 205-00237, 7 pins, pitch 5.08mm, size 35.6x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00237 pitch 5.08mm size 35.6x8.45mm^2 drill 1.1mm pad 2.1mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00238_1x08_P5.08mm_Horizontal +terminal block RND 205-00238, 8 pins, pitch 5.08mm, size 40.6x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00238 pitch 5.08mm size 40.6x8.45mm^2 drill 1.1mm pad 2.1mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00239_1x09_P5.08mm_Horizontal +terminal block RND 205-00239, 9 pins, pitch 5.08mm, size 45.7x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00239 pitch 5.08mm size 45.7x8.45mm^2 drill 1.1mm pad 2.1mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00240_1x10_P5.08mm_Horizontal +terminal block RND 205-00240, 10 pins, pitch 5.08mm, size 50.8x8.45mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00232_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00240 pitch 5.08mm size 50.8x8.45mm^2 drill 1.1mm pad 2.1mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00241_1x02_P10.16mm_Horizontal +terminal block RND 205-00241, 2 pins, pitch 10.2mm, size 15.2x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00241 pitch 10.2mm size 15.2x8.3mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00242_1x03_P10.16mm_Horizontal +terminal block RND 205-00242, 3 pins, pitch 10.2mm, size 25.4x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00242 pitch 10.2mm size 25.4x8.3mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00243_1x04_P10.16mm_Horizontal +terminal block RND 205-00243, 4 pins, pitch 10.2mm, size 35.6x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00243 pitch 10.2mm size 35.6x8.3mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00244_1x05_P10.16mm_Horizontal +terminal block RND 205-00244, 5 pins, pitch 10.2mm, size 45.7x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00244 pitch 10.2mm size 45.7x8.3mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00245_1x06_P10.16mm_Horizontal +terminal block RND 205-00245, 6 pins, pitch 10.2mm, size 55.9x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00245 pitch 10.2mm size 55.9x8.3mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00246_1x07_P10.16mm_Horizontal +terminal block RND 205-00246, 7 pins, pitch 10.2mm, size 66x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00246 pitch 10.2mm size 66x8.3mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00247_1x08_P10.16mm_Horizontal +terminal block RND 205-00247, 8 pins, pitch 10.2mm, size 76.2x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00247 pitch 10.2mm size 76.2x8.3mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00248_1x09_P10.16mm_Horizontal +terminal block RND 205-00248, 9 pins, pitch 10.2mm, size 86.4x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00248 pitch 10.2mm size 86.4x8.3mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00249_1x10_P10.16mm_Horizontal +terminal block RND 205-00249, 10 pins, pitch 10.2mm, size 96.5x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00249 pitch 10.2mm size 96.5x8.3mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00250_1x11_P10.16mm_Horizontal +terminal block RND 205-00250, 11 pins, pitch 10.2mm, size 107x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00250 pitch 10.2mm size 107x8.3mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00251_1x12_P10.16mm_Horizontal +terminal block RND 205-00251, 12 pins, pitch 10.2mm, size 117x8.3mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00023_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00251 pitch 10.2mm size 117x8.3mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00276_1x02_P5.00mm_Vertical +terminal block RND 205-00078, vertical (cable from top), 2 pins, pitch 5mm, size 10x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00078 vertical pitch 5mm size 10x10mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00277_1x03_P5.00mm_Vertical +terminal block RND 205-00079, vertical (cable from top), 3 pins, pitch 5mm, size 15x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00079 vertical pitch 5mm size 15x10mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00278_1x04_P5.00mm_Vertical +terminal block RND 205-00080, vertical (cable from top), 4 pins, pitch 5mm, size 20x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00080 vertical pitch 5mm size 20x10mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00279_1x05_P5.00mm_Vertical +terminal block RND 205-00081, vertical (cable from top), 5 pins, pitch 5mm, size 25x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00081 vertical pitch 5mm size 25x10mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00280_1x06_P5.00mm_Vertical +terminal block RND 205-00082, vertical (cable from top), 6 pins, pitch 5mm, size 30x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00082 vertical pitch 5mm size 30x10mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00281_1x07_P5.00mm_Vertical +terminal block RND 205-00083, vertical (cable from top), 7 pins, pitch 5mm, size 35x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00083 vertical pitch 5mm size 35x10mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00282_1x08_P5.00mm_Vertical +terminal block RND 205-00084, vertical (cable from top), 8 pins, pitch 5mm, size 40x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00084 vertical pitch 5mm size 40x10mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00283_1x09_P5.00mm_Vertical +terminal block RND 205-00085, vertical (cable from top), 9 pins, pitch 5mm, size 45x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00085 vertical pitch 5mm size 45x10mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00284_1x10_P5.00mm_Vertical +terminal block RND 205-00086, vertical (cable from top), 10 pins, pitch 5mm, size 50x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00086 vertical pitch 5mm size 50x10mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00285_1x11_P5.00mm_Vertical +terminal block RND 205-00087, vertical (cable from top), 11 pins, pitch 5mm, size 55x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00087 vertical pitch 5mm size 55x10mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00286_1x12_P5.00mm_Vertical +terminal block RND 205-00088, vertical (cable from top), 12 pins, pitch 5mm, size 60x10mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00276_DB_EN.pdf, script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00088 vertical pitch 5mm size 60x10mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00287_1x02_P5.08mm_Horizontal +terminal block RND 205-00287, 2 pins, pitch 5.08mm, size 10.2x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00287 pitch 5.08mm size 10.2x10.6mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00288_1x03_P5.08mm_Horizontal +terminal block RND 205-00288, 3 pins, pitch 5.08mm, size 15.2x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00288 pitch 5.08mm size 15.2x10.6mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00289_1x04_P5.08mm_Horizontal +terminal block RND 205-00289, 4 pins, pitch 5.08mm, size 20.3x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00289 pitch 5.08mm size 20.3x10.6mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00290_1x05_P5.08mm_Horizontal +terminal block RND 205-00290, 5 pins, pitch 5.08mm, size 25.4x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00290 pitch 5.08mm size 25.4x10.6mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00291_1x06_P5.08mm_Horizontal +terminal block RND 205-00291, 6 pins, pitch 5.08mm, size 30.5x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00291 pitch 5.08mm size 30.5x10.6mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00292_1x07_P5.08mm_Horizontal +terminal block RND 205-00292, 7 pins, pitch 5.08mm, size 35.6x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00292 pitch 5.08mm size 35.6x10.6mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00293_1x08_P5.08mm_Horizontal +terminal block RND 205-00293, 8 pins, pitch 5.08mm, size 40.6x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00293 pitch 5.08mm size 40.6x10.6mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00294_1x09_P5.08mm_Horizontal +terminal block RND 205-00294, 9 pins, pitch 5.08mm, size 45.7x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00294 pitch 5.08mm size 45.7x10.6mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00295_1x10_P5.08mm_Horizontal +terminal block RND 205-00295, 10 pins, pitch 5.08mm, size 50.8x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00295 pitch 5.08mm size 50.8x10.6mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00296_1x11_P5.08mm_Horizontal +terminal block RND 205-00296, 11 pins, pitch 5.08mm, size 55.9x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00296 pitch 5.08mm size 55.9x10.6mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00297_1x12_P5.08mm_Horizontal +terminal block RND 205-00297, 12 pins, pitch 5.08mm, size 61x10.6mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00287_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00297 pitch 5.08mm size 61x10.6mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_RND +TerminalBlock_RND_205-00298_1x02_P10.00mm_Horizontal +terminal block RND 205-00298, 2 pins, pitch 10mm, size 15x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00298 pitch 10mm size 15x8.1mm^2 drill 1.3mm pad 2.5mm +0 +2 +2 +TerminalBlock_RND +TerminalBlock_RND_205-00299_1x03_P10.00mm_Horizontal +terminal block RND 205-00299, 3 pins, pitch 10mm, size 25x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00299 pitch 10mm size 25x8.1mm^2 drill 1.3mm pad 2.5mm +0 +3 +3 +TerminalBlock_RND +TerminalBlock_RND_205-00300_1x04_P10.00mm_Horizontal +terminal block RND 205-00300, 4 pins, pitch 10mm, size 35x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00300 pitch 10mm size 35x8.1mm^2 drill 1.3mm pad 2.5mm +0 +4 +4 +TerminalBlock_RND +TerminalBlock_RND_205-00301_1x05_P10.00mm_Horizontal +terminal block RND 205-00301, 5 pins, pitch 10mm, size 45x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00301 pitch 10mm size 45x8.1mm^2 drill 1.3mm pad 2.5mm +0 +5 +5 +TerminalBlock_RND +TerminalBlock_RND_205-00302_1x06_P10.00mm_Horizontal +terminal block RND 205-00302, 6 pins, pitch 10mm, size 55x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00302 pitch 10mm size 55x8.1mm^2 drill 1.3mm pad 2.5mm +0 +6 +6 +TerminalBlock_RND +TerminalBlock_RND_205-00303_1x07_P10.00mm_Horizontal +terminal block RND 205-00303, 7 pins, pitch 10mm, size 65x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00303 pitch 10mm size 65x8.1mm^2 drill 1.3mm pad 2.5mm +0 +7 +7 +TerminalBlock_RND +TerminalBlock_RND_205-00304_1x08_P10.00mm_Horizontal +terminal block RND 205-00304, 8 pins, pitch 10mm, size 75x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00304 pitch 10mm size 75x8.1mm^2 drill 1.3mm pad 2.5mm +0 +8 +8 +TerminalBlock_RND +TerminalBlock_RND_205-00305_1x09_P10.00mm_Horizontal +terminal block RND 205-00305, 9 pins, pitch 10mm, size 85x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00305 pitch 10mm size 85x8.1mm^2 drill 1.3mm pad 2.5mm +0 +9 +9 +TerminalBlock_RND +TerminalBlock_RND_205-00306_1x10_P10.00mm_Horizontal +terminal block RND 205-00306, 10 pins, pitch 10mm, size 95x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00306 pitch 10mm size 95x8.1mm^2 drill 1.3mm pad 2.5mm +0 +10 +10 +TerminalBlock_RND +TerminalBlock_RND_205-00307_1x11_P10.00mm_Horizontal +terminal block RND 205-00307, 11 pins, pitch 10mm, size 105x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00307 pitch 10mm size 105x8.1mm^2 drill 1.3mm pad 2.5mm +0 +11 +11 +TerminalBlock_RND +TerminalBlock_RND_205-00308_1x12_P10.00mm_Horizontal +terminal block RND 205-00308, 12 pins, pitch 10mm, size 115x8.1mm^2, drill diamater 1.3mm, pad diameter 2.5mm, see http://cdn-reichelt.de/documents/datenblatt/C151/RND_205-00298_DB_EN.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND +THT terminal block RND 205-00308 pitch 10mm size 115x8.1mm^2 drill 1.3mm pad 2.5mm +0 +12 +12 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_1-282834-0_1x10_P2.54mm_Horizontal +Terminal Block TE 1-282834-0, 10 pins, pitch 2.54mm, size 25.86x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 1-282834-0 pitch 2.54mm size 25.86x6.5mm^2 drill 1.1mm pad 2.1mm +0 +10 +10 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_1-282834-1_1x11_P2.54mm_Horizontal +Terminal Block TE 1-282834-1, 11 pins, pitch 2.54mm, size 28.4x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 1-282834-1 pitch 2.54mm size 28.4x6.5mm^2 drill 1.1mm pad 2.1mm +0 +11 +11 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal +Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm +0 +12 +12 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-2_1x02_P2.54mm_Horizontal +Terminal Block TE 282834-2, 2 pins, pitch 2.54mm, size 5.54x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-2 pitch 2.54mm size 5.54x6.5mm^2 drill 1.1mm pad 2.1mm +0 +2 +2 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-3_1x03_P2.54mm_Horizontal +Terminal Block TE 282834-3, 3 pins, pitch 2.54mm, size 8.08x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-3 pitch 2.54mm size 8.08x6.5mm^2 drill 1.1mm pad 2.1mm +0 +3 +3 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-4_1x04_P2.54mm_Horizontal +Terminal Block TE 282834-4, 4 pins, pitch 2.54mm, size 10.620000000000001x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-4 pitch 2.54mm size 10.620000000000001x6.5mm^2 drill 1.1mm pad 2.1mm +0 +4 +4 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-5_1x05_P2.54mm_Horizontal +Terminal Block TE 282834-5, 5 pins, pitch 2.54mm, size 13.16x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-5 pitch 2.54mm size 13.16x6.5mm^2 drill 1.1mm pad 2.1mm +0 +5 +5 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-6_1x06_P2.54mm_Horizontal +Terminal Block TE 282834-6, 6 pins, pitch 2.54mm, size 15.7x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-6 pitch 2.54mm size 15.7x6.5mm^2 drill 1.1mm pad 2.1mm +0 +6 +6 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-7_1x07_P2.54mm_Horizontal +Terminal Block TE 282834-7, 7 pins, pitch 2.54mm, size 18.240000000000002x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-7 pitch 2.54mm size 18.240000000000002x6.5mm^2 drill 1.1mm pad 2.1mm +0 +7 +7 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-8_1x08_P2.54mm_Horizontal +Terminal Block TE 282834-8, 8 pins, pitch 2.54mm, size 20.78x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-8 pitch 2.54mm size 20.78x6.5mm^2 drill 1.1mm pad 2.1mm +0 +8 +8 +TerminalBlock_TE-Connectivity +TerminalBlock_TE_282834-9_1x09_P2.54mm_Horizontal +Terminal Block TE 282834-9, 9 pins, pitch 2.54mm, size 23.32x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity +THT Terminal Block TE 282834-9 pitch 2.54mm size 23.32x6.5mm^2 drill 1.1mm pad 2.1mm +0 +9 +9 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-101_1x01_P5.00mm_45Degree +Terminal Block WAGO 236-101, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 7.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-101 45Degree pitch 5mm size 7.3x14mm^2 drill 1.15mm pad 3mm +0 +1 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-102_1x02_P5.00mm_45Degree +Terminal Block WAGO 236-102, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-102 45Degree pitch 5mm size 12.3x14mm^2 drill 1.15mm pad 3mm +0 +2 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-103_1x03_P5.00mm_45Degree +Terminal Block WAGO 236-103, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-103 45Degree pitch 5mm size 17.3x14mm^2 drill 1.15mm pad 3mm +0 +3 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-104_1x04_P5.00mm_45Degree +Terminal Block WAGO 236-104, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-104 45Degree pitch 5mm size 22.3x14mm^2 drill 1.15mm pad 3mm +0 +4 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-106_1x06_P5.00mm_45Degree +Terminal Block WAGO 236-106, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-106 45Degree pitch 5mm size 32.3x14mm^2 drill 1.15mm pad 3mm +0 +6 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-108_1x08_P5.00mm_45Degree +Terminal Block WAGO 236-108, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-108 45Degree pitch 5mm size 42.3x14mm^2 drill 1.15mm pad 3mm +0 +8 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-112_1x12_P5.00mm_45Degree +Terminal Block WAGO 236-112, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-112 45Degree pitch 5mm size 62.3x14mm^2 drill 1.15mm pad 3mm +0 +12 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-116_1x16_P5.00mm_45Degree +Terminal Block WAGO 236-116, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-116 45Degree pitch 5mm size 82.3x14mm^2 drill 1.15mm pad 3mm +0 +16 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-124_1x24_P5.00mm_45Degree +Terminal Block WAGO 236-124, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-124 45Degree pitch 5mm size 122x14mm^2 drill 1.15mm pad 3mm +0 +24 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-136_1x36_P5.00mm_45Degree +Terminal Block WAGO 236-136, 45Degree (cable under 45degree), 36 pins, pitch 5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-136 45Degree pitch 5mm size 182x14mm^2 drill 1.15mm pad 3mm +0 +36 +36 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-148_1x48_P5.00mm_45Degree +Terminal Block WAGO 236-148, 45Degree (cable under 45degree), 48 pins, pitch 5mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-148 45Degree pitch 5mm size 242x14mm^2 drill 1.15mm pad 3mm +0 +48 +48 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-201_1x01_P7.50mm_45Degree +Terminal Block WAGO 236-201, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 9.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-201 45Degree pitch 7.5mm size 9.8x14mm^2 drill 1.15mm pad 3mm +0 +1 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-202_1x02_P7.50mm_45Degree +Terminal Block WAGO 236-202, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-202 45Degree pitch 7.5mm size 17.3x14mm^2 drill 1.15mm pad 3mm +0 +2 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-203_1x03_P7.50mm_45Degree +Terminal Block WAGO 236-203, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 24.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-203 45Degree pitch 7.5mm size 24.8x14mm^2 drill 1.15mm pad 3mm +0 +3 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-204_1x04_P7.50mm_45Degree +Terminal Block WAGO 236-204, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-204 45Degree pitch 7.5mm size 32.3x14mm^2 drill 1.15mm pad 3mm +0 +4 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-206_1x06_P7.50mm_45Degree +Terminal Block WAGO 236-206, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 47.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-206 45Degree pitch 7.5mm size 47.3x14mm^2 drill 1.15mm pad 3mm +0 +6 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-208_1x08_P7.50mm_45Degree +Terminal Block WAGO 236-208, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-208 45Degree pitch 7.5mm size 62.3x14mm^2 drill 1.15mm pad 3mm +0 +8 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-212_1x12_P7.50mm_45Degree +Terminal Block WAGO 236-212, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 92.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-212 45Degree pitch 7.5mm size 92.3x14mm^2 drill 1.15mm pad 3mm +0 +12 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-216_1x16_P7.50mm_45Degree +Terminal Block WAGO 236-216, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-216 45Degree pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm +0 +16 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-224_1x24_P7.50mm_45Degree +Terminal Block WAGO 236-224, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-224 45Degree pitch 7.5mm size 182x14mm^2 drill 1.15mm pad 3mm +0 +24 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-301_1x01_P10.00mm_45Degree +Terminal Block WAGO 236-301, 45Degree (cable under 45degree), 1 pins, pitch 10mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-301 45Degree pitch 10mm size 12.3x14mm^2 drill 1.15mm pad 3mm +0 +1 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-302_1x02_P10.00mm_45Degree +Terminal Block WAGO 236-302, 45Degree (cable under 45degree), 2 pins, pitch 10mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-302 45Degree pitch 10mm size 22.3x14mm^2 drill 1.15mm pad 3mm +0 +2 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-303_1x03_P10.00mm_45Degree +Terminal Block WAGO 236-303, 45Degree (cable under 45degree), 3 pins, pitch 10mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-303 45Degree pitch 10mm size 32.3x14mm^2 drill 1.15mm pad 3mm +0 +3 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-304_1x04_P10.00mm_45Degree +Terminal Block WAGO 236-304, 45Degree (cable under 45degree), 4 pins, pitch 10mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-304 45Degree pitch 10mm size 42.3x14mm^2 drill 1.15mm pad 3mm +0 +4 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-306_1x06_P10.00mm_45Degree +Terminal Block WAGO 236-306, 45Degree (cable under 45degree), 6 pins, pitch 10mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-306 45Degree pitch 10mm size 62.3x14mm^2 drill 1.15mm pad 3mm +0 +6 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-308_1x08_P10.00mm_45Degree +Terminal Block WAGO 236-308, 45Degree (cable under 45degree), 8 pins, pitch 10mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-308 45Degree pitch 10mm size 82.3x14mm^2 drill 1.15mm pad 3mm +0 +8 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-312_1x12_P10.00mm_45Degree +Terminal Block WAGO 236-312, 45Degree (cable under 45degree), 12 pins, pitch 10mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-312 45Degree pitch 10mm size 122x14mm^2 drill 1.15mm pad 3mm +0 +12 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-316_1x16_P10.00mm_45Degree +Terminal Block WAGO 236-316, 45Degree (cable under 45degree), 16 pins, pitch 10mm, size 162x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-316 45Degree pitch 10mm size 162x14mm^2 drill 1.15mm pad 3mm +0 +16 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-324_1x24_P10.00mm_45Degree +Terminal Block WAGO 236-324, 45Degree (cable under 45degree), 24 pins, pitch 10mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-324 45Degree pitch 10mm size 242x14mm^2 drill 1.15mm pad 3mm +0 +24 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-401_1x01_P5.00mm_45Degree +Terminal Block WAGO 236-401, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 7.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-401 45Degree pitch 5mm size 7.3x14mm^2 drill 1.15mm pad 3mm +0 +2 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-402_1x02_P5.00mm_45Degree +Terminal Block WAGO 236-402, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-402 45Degree pitch 5mm size 12.3x14mm^2 drill 1.15mm pad 3mm +0 +4 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-403_1x03_P5.00mm_45Degree +Terminal Block WAGO 236-403, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-403 45Degree pitch 5mm size 17.3x14mm^2 drill 1.15mm pad 3mm +0 +6 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-404_1x04_P5.00mm_45Degree +Terminal Block WAGO 236-404, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-404 45Degree pitch 5mm size 22.3x14mm^2 drill 1.15mm pad 3mm +0 +8 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-406_1x06_P5.00mm_45Degree +Terminal Block WAGO 236-406, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-406 45Degree pitch 5mm size 32.3x14mm^2 drill 1.15mm pad 3mm +0 +12 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-408_1x08_P5.00mm_45Degree +Terminal Block WAGO 236-408, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-408 45Degree pitch 5mm size 42.3x14mm^2 drill 1.15mm pad 3mm +0 +16 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-412_1x12_P5.00mm_45Degree +Terminal Block WAGO 236-412, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-412 45Degree pitch 5mm size 62.3x14mm^2 drill 1.15mm pad 3mm +0 +24 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-416_1x16_P5.00mm_45Degree +Terminal Block WAGO 236-416, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-416 45Degree pitch 5mm size 82.3x14mm^2 drill 1.15mm pad 3mm +0 +32 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-424_1x24_P5.00mm_45Degree +Terminal Block WAGO 236-424, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-424 45Degree pitch 5mm size 122x14mm^2 drill 1.15mm pad 3mm +0 +48 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-436_1x36_P5.00mm_45Degree +Terminal Block WAGO 236-436, 45Degree (cable under 45degree), 36 pins, pitch 5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-436 45Degree pitch 5mm size 182x14mm^2 drill 1.15mm pad 3mm +0 +72 +36 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-448_1x48_P5.00mm_45Degree +Terminal Block WAGO 236-448, 45Degree (cable under 45degree), 48 pins, pitch 5mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-448 45Degree pitch 5mm size 242x14mm^2 drill 1.15mm pad 3mm +0 +96 +48 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-501_1x01_P7.50mm_45Degree +Terminal Block WAGO 236-501, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 9.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-501 45Degree pitch 7.5mm size 9.8x14mm^2 drill 1.15mm pad 3mm +0 +2 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-502_1x02_P7.50mm_45Degree +Terminal Block WAGO 236-502, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 17.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-502 45Degree pitch 7.5mm size 17.3x14mm^2 drill 1.15mm pad 3mm +0 +4 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-503_1x03_P7.50mm_45Degree +Terminal Block WAGO 236-503, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 24.8x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-503 45Degree pitch 7.5mm size 24.8x14mm^2 drill 1.15mm pad 3mm +0 +6 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-504_1x04_P7.50mm_45Degree +Terminal Block WAGO 236-504, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-504 45Degree pitch 7.5mm size 32.3x14mm^2 drill 1.15mm pad 3mm +0 +8 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-506_1x06_P7.50mm_45Degree +Terminal Block WAGO 236-506, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 47.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-506 45Degree pitch 7.5mm size 47.3x14mm^2 drill 1.15mm pad 3mm +0 +12 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-508_1x08_P7.50mm_45Degree +Terminal Block WAGO 236-508, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-508 45Degree pitch 7.5mm size 62.3x14mm^2 drill 1.15mm pad 3mm +0 +16 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-512_1x12_P7.50mm_45Degree +Terminal Block WAGO 236-512, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 92.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-512 45Degree pitch 7.5mm size 92.3x14mm^2 drill 1.15mm pad 3mm +0 +24 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-516_1x16_P7.50mm_45Degree +Terminal Block WAGO 236-516, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-516 45Degree pitch 7.5mm size 122x14mm^2 drill 1.15mm pad 3mm +0 +32 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-524_1x24_P7.50mm_45Degree +Terminal Block WAGO 236-524, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 182x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-524 45Degree pitch 7.5mm size 182x14mm^2 drill 1.15mm pad 3mm +0 +48 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-601_1x01_P10.00mm_45Degree +Terminal Block WAGO 236-601, 45Degree (cable under 45degree), 1 pins, pitch 10mm, size 12.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-601 45Degree pitch 10mm size 12.3x14mm^2 drill 1.15mm pad 3mm +0 +2 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-602_1x02_P10.00mm_45Degree +Terminal Block WAGO 236-602, 45Degree (cable under 45degree), 2 pins, pitch 10mm, size 22.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-602 45Degree pitch 10mm size 22.3x14mm^2 drill 1.15mm pad 3mm +0 +4 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-603_1x03_P10.00mm_45Degree +Terminal Block WAGO 236-603, 45Degree (cable under 45degree), 3 pins, pitch 10mm, size 32.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-603 45Degree pitch 10mm size 32.3x14mm^2 drill 1.15mm pad 3mm +0 +6 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-604_1x04_P10.00mm_45Degree +Terminal Block WAGO 236-604, 45Degree (cable under 45degree), 4 pins, pitch 10mm, size 42.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-604 45Degree pitch 10mm size 42.3x14mm^2 drill 1.15mm pad 3mm +0 +8 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-606_1x06_P10.00mm_45Degree +Terminal Block WAGO 236-606, 45Degree (cable under 45degree), 6 pins, pitch 10mm, size 62.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-606 45Degree pitch 10mm size 62.3x14mm^2 drill 1.15mm pad 3mm +0 +12 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-608_1x08_P10.00mm_45Degree +Terminal Block WAGO 236-608, 45Degree (cable under 45degree), 8 pins, pitch 10mm, size 82.3x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-608 45Degree pitch 10mm size 82.3x14mm^2 drill 1.15mm pad 3mm +0 +16 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-612_1x12_P10.00mm_45Degree +Terminal Block WAGO 236-612, 45Degree (cable under 45degree), 12 pins, pitch 10mm, size 122x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-612 45Degree pitch 10mm size 122x14mm^2 drill 1.15mm pad 3mm +0 +24 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-616_1x16_P10.00mm_45Degree +Terminal Block WAGO 236-616, 45Degree (cable under 45degree), 16 pins, pitch 10mm, size 162x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-616 45Degree pitch 10mm size 162x14mm^2 drill 1.15mm pad 3mm +0 +32 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_236-624_1x24_P10.00mm_45Degree +Terminal Block WAGO 236-624, 45Degree (cable under 45degree), 24 pins, pitch 10mm, size 242x14mm^2, drill diamater 1.15mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 236-624 45Degree pitch 10mm size 242x14mm^2 drill 1.15mm pad 3mm +0 +48 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-101_1x01_P5.00mm_45Degree +Terminal Block WAGO 804-101, 45Degree (cable under 45degree), 1 pins, pitch 5mm, size 6.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-101 45Degree pitch 5mm size 6.5x15mm^2 drill 1.2mm pad 3mm +0 +2 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-102_1x02_P5.00mm_45Degree +Terminal Block WAGO 804-102, 45Degree (cable under 45degree), 2 pins, pitch 5mm, size 11.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-102 45Degree pitch 5mm size 11.5x15mm^2 drill 1.2mm pad 3mm +0 +4 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-103_1x03_P5.00mm_45Degree +Terminal Block WAGO 804-103, 45Degree (cable under 45degree), 3 pins, pitch 5mm, size 16.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-103 45Degree pitch 5mm size 16.5x15mm^2 drill 1.2mm pad 3mm +0 +6 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-104_1x04_P5.00mm_45Degree +Terminal Block WAGO 804-104, 45Degree (cable under 45degree), 4 pins, pitch 5mm, size 21.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-104 45Degree pitch 5mm size 21.5x15mm^2 drill 1.2mm pad 3mm +0 +8 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-105_1x05_P5.00mm_45Degree +Terminal Block WAGO 804-105, 45Degree (cable under 45degree), 5 pins, pitch 5mm, size 26.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-105 45Degree pitch 5mm size 26.5x15mm^2 drill 1.2mm pad 3mm +0 +10 +5 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-106_1x06_P5.00mm_45Degree +Terminal Block WAGO 804-106, 45Degree (cable under 45degree), 6 pins, pitch 5mm, size 31.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-106 45Degree pitch 5mm size 31.5x15mm^2 drill 1.2mm pad 3mm +0 +12 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-107_1x07_P5.00mm_45Degree +Terminal Block WAGO 804-107, 45Degree (cable under 45degree), 7 pins, pitch 5mm, size 36.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-107 45Degree pitch 5mm size 36.5x15mm^2 drill 1.2mm pad 3mm +0 +14 +7 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-108_1x08_P5.00mm_45Degree +Terminal Block WAGO 804-108, 45Degree (cable under 45degree), 8 pins, pitch 5mm, size 41.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-108 45Degree pitch 5mm size 41.5x15mm^2 drill 1.2mm pad 3mm +0 +16 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-109_1x09_P5.00mm_45Degree +Terminal Block WAGO 804-109, 45Degree (cable under 45degree), 9 pins, pitch 5mm, size 46.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-109 45Degree pitch 5mm size 46.5x15mm^2 drill 1.2mm pad 3mm +0 +18 +9 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-110_1x10_P5.00mm_45Degree +Terminal Block WAGO 804-110, 45Degree (cable under 45degree), 10 pins, pitch 5mm, size 51.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-110 45Degree pitch 5mm size 51.5x15mm^2 drill 1.2mm pad 3mm +0 +20 +10 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-112_1x12_P5.00mm_45Degree +Terminal Block WAGO 804-112, 45Degree (cable under 45degree), 12 pins, pitch 5mm, size 61.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-112 45Degree pitch 5mm size 61.5x15mm^2 drill 1.2mm pad 3mm +0 +24 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-116_1x16_P5.00mm_45Degree +Terminal Block WAGO 804-116, 45Degree (cable under 45degree), 16 pins, pitch 5mm, size 81.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-116 45Degree pitch 5mm size 81.5x15mm^2 drill 1.2mm pad 3mm +0 +32 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-124_1x24_P5.00mm_45Degree +Terminal Block WAGO 804-124, 45Degree (cable under 45degree), 24 pins, pitch 5mm, size 122x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-124 45Degree pitch 5mm size 122x15mm^2 drill 1.2mm pad 3mm +0 +48 +24 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-301_1x01_P7.50mm_45Degree +Terminal Block WAGO 804-301, 45Degree (cable under 45degree), 1 pins, pitch 7.5mm, size 6.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-301 45Degree pitch 7.5mm size 6.5x15mm^2 drill 1.2mm pad 3mm +0 +2 +1 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-302_1x02_P7.50mm_45Degree +Terminal Block WAGO 804-302, 45Degree (cable under 45degree), 2 pins, pitch 7.5mm, size 14x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-302 45Degree pitch 7.5mm size 14x15mm^2 drill 1.2mm pad 3mm +0 +4 +2 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-303_1x03_P7.50mm_45Degree +Terminal Block WAGO 804-303, 45Degree (cable under 45degree), 3 pins, pitch 7.5mm, size 21.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-303 45Degree pitch 7.5mm size 21.5x15mm^2 drill 1.2mm pad 3mm +0 +6 +3 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-304_1x04_P7.50mm_45Degree +Terminal Block WAGO 804-304, 45Degree (cable under 45degree), 4 pins, pitch 7.5mm, size 29x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-304 45Degree pitch 7.5mm size 29x15mm^2 drill 1.2mm pad 3mm +0 +8 +4 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-305_1x05_P7.50mm_45Degree +Terminal Block WAGO 804-305, 45Degree (cable under 45degree), 5 pins, pitch 7.5mm, size 36.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-305 45Degree pitch 7.5mm size 36.5x15mm^2 drill 1.2mm pad 3mm +0 +10 +5 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-306_1x06_P7.50mm_45Degree +Terminal Block WAGO 804-306, 45Degree (cable under 45degree), 6 pins, pitch 7.5mm, size 44x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-306 45Degree pitch 7.5mm size 44x15mm^2 drill 1.2mm pad 3mm +0 +12 +6 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-307_1x07_P7.50mm_45Degree +Terminal Block WAGO 804-307, 45Degree (cable under 45degree), 7 pins, pitch 7.5mm, size 51.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-307 45Degree pitch 7.5mm size 51.5x15mm^2 drill 1.2mm pad 3mm +0 +14 +7 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-308_1x08_P7.50mm_45Degree +Terminal Block WAGO 804-308, 45Degree (cable under 45degree), 8 pins, pitch 7.5mm, size 59x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-308 45Degree pitch 7.5mm size 59x15mm^2 drill 1.2mm pad 3mm +0 +16 +8 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-309_1x09_P7.50mm_45Degree +Terminal Block WAGO 804-309, 45Degree (cable under 45degree), 9 pins, pitch 7.5mm, size 66.5x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-309 45Degree pitch 7.5mm size 66.5x15mm^2 drill 1.2mm pad 3mm +0 +18 +9 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-310_1x10_P7.50mm_45Degree +Terminal Block WAGO 804-310, 45Degree (cable under 45degree), 10 pins, pitch 7.5mm, size 74x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-310 45Degree pitch 7.5mm size 74x15mm^2 drill 1.2mm pad 3mm +0 +20 +10 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-312_1x12_P7.50mm_45Degree +Terminal Block WAGO 804-312, 45Degree (cable under 45degree), 12 pins, pitch 7.5mm, size 89x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-312 45Degree pitch 7.5mm size 89x15mm^2 drill 1.2mm pad 3mm +0 +24 +12 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-316_1x16_P7.50mm_45Degree +Terminal Block WAGO 804-316, 45Degree (cable under 45degree), 16 pins, pitch 7.5mm, size 119x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-316 45Degree pitch 7.5mm size 119x15mm^2 drill 1.2mm pad 3mm +0 +32 +16 +TerminalBlock_WAGO +TerminalBlock_WAGO_804-324_1x24_P7.50mm_45Degree +Terminal Block WAGO 804-324, 45Degree (cable under 45degree), 24 pins, pitch 7.5mm, size 179x15mm^2, drill diamater 1.2mm, pad diameter 3mm, see , script-generated with , script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_WAGO +THT Terminal Block WAGO 804-324 45Degree pitch 7.5mm size 179x15mm^2 drill 1.2mm pad 3mm +0 +48 +24 +TestPoint +TestPoint_2Pads_Pitch2.54mm_Drill0.8mm +Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm +CONN DEV +0 +2 +2 +TestPoint +TestPoint_2Pads_Pitch5.08mm_Drill1.3mm +Test point with 2 pads, pitch 5.08mm, hole diameter 1.3mm, wire diameter 1.0mm +CONN DEV +0 +2 +2 +TestPoint +TestPoint_Bridge_Pitch2.0mm_Drill0.7mm +wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch2.54mm_Drill0.7mm +wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch2.54mm_Drill1.0mm +wire loop as test point, pitch 2.54mm, hole diameter 1.0mm, wire diameter 0.8mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch2.54mm_Drill1.3mm +wire loop as test point, pitch 2.54mm, hole diameter 1.3mm, wire diameter 1.0mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch3.81mm_Drill1.3mm +wire loop as test point, pitch 3.81mm, hole diameter 1.3mm, wire diameter 1.0mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch5.08mm_Drill0.7mm +wire loop as test point, pitch 5.08mm, hole diameter 0.7mm, wire diameter 1.0mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch5.08mm_Drill1.3mm +wire loop as test point, pitch 5.08mm, hole diameter 1.3mm, wire diameter 1.0mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch6.35mm_Drill1.3mm +wire loop as test point, pitch 6.35mm, hole diameter 1.3mm, wire diameter 1.0mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Bridge_Pitch7.62mm_Drill1.3mm +wire loop as test point, pitch 7.62mm, hole diameter 1.3mm, wire diameter 1.0mm +test point wire loop +0 +2 +1 +TestPoint +TestPoint_Keystone_5000-5004_Miniature +Keystone Miniature THM Test Point 5000-5004, http://www.keyelco.com/product-pdf.cfm?p=1309 +Through Hole Mount Test Points +0 +1 +1 +TestPoint +TestPoint_Keystone_5005-5009_Compact +Keystone Miniature THM Test Point 5005-5009, http://www.keyelco.com/product-pdf.cfm?p=1314 +Through Hole Mount Test Points +0 +1 +1 +TestPoint +TestPoint_Keystone_5010-5014_Multipurpose +Keystone Miniature THM Test Point 5010-5014, http://www.keyelco.com/product-pdf.cfm?p=1319 +Through Hole Mount Test Points +0 +1 +1 +TestPoint +TestPoint_Keystone_5015_Micro-Minature +SMT Test Point- Micro Miniature 5015, http://www.keyelco.com/product-pdf.cfm?p=1353 +Test Point +0 +1 +1 +TestPoint +TestPoint_Keystone_5019_Minature +SMT Test Point- Micro Miniature 5019, http://www.keyelco.com/product-pdf.cfm?p=1357 +Test Point +0 +1 +1 +TestPoint +TestPoint_Loop_D1.80mm_Drill1.0mm_Beaded +wire loop with bead as test point, loop diameter 1.8mm, hole diameter 1.0mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.50mm_Drill1.0mm +wire loop as test point, loop diameter 2.5mm, hole diameter 1.0mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.50mm_Drill1.0mm_LowProfile +low profile wire loop as test point, loop diameter 2.5mm, hole diameter 1.0mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.50mm_Drill1.85mm +wire loop as test point, loop diameter 2.5mm, hole diameter 1.85mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.54mm_Drill1.5mm_Beaded +wire loop with bead as test point, loop diameter2.548mm, hole diameter 1.5mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.60mm_Drill0.9mm_Beaded +wire loop with bead as test point, loop diameter2.6mm, hole diameter 0.9mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.60mm_Drill1.4mm_Beaded +wire loop with bead as test point, loop diameter2.6mm, hole diameter 1.4mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D2.60mm_Drill1.6mm_Beaded +wire loop with bead as test point, loop diameter2.6mm, hole diameter 1.6mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D3.50mm_Drill0.9mm_Beaded +wire loop with bead as test point, loop diameter2.6mm, hole diameter 0.9mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D3.50mm_Drill1.4mm_Beaded +wire loop with bead as test point, loop diameter 3.5mm, hole diameter 1.4mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D3.80mm_Drill2.0mm +wire loop as test point, loop diameter 3.8mm, hole diameter 2.0mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D3.80mm_Drill2.5mm +wire loop as test point, loop diameter 3.8mm, hole diameter 2.5mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Loop_D3.80mm_Drill2.8mm +wire loop as test point, loop diameter 3.8mm, hole diameter 2.8mm +test point wire loop bead +0 +1 +1 +TestPoint +TestPoint_Pad_1.0x1.0mm +SMD rectangular pad as test Point, square 1.0mm side length +test point SMD pad rectangle square +0 +1 +1 +TestPoint +TestPoint_Pad_1.5x1.5mm +SMD rectangular pad as test Point, square 1.5mm side length +test point SMD pad rectangle square +0 +1 +1 +TestPoint +TestPoint_Pad_2.0x2.0mm +SMD rectangular pad as test Point, square 2.0mm side length +test point SMD pad rectangle square +0 +1 +1 +TestPoint +TestPoint_Pad_2.5x2.5mm +SMD rectangular pad as test Point, square 2.5mm side length +test point SMD pad rectangle square +0 +1 +1 +TestPoint +TestPoint_Pad_3.0x3.0mm +SMD rectangular pad as test Point, square 3.0mm side length +test point SMD pad rectangle square +0 +1 +1 +TestPoint +TestPoint_Pad_4.0x4.0mm +SMD rectangular pad as test Point, square 4.0mm side length +test point SMD pad rectangle square +0 +1 +1 +TestPoint +TestPoint_Pad_D1.0mm +SMD pad as test Point, diameter 1.0mm +test point SMD pad +0 +1 +1 +TestPoint +TestPoint_Pad_D1.5mm +SMD pad as test Point, diameter 1.5mm +test point SMD pad +0 +1 +1 +TestPoint +TestPoint_Pad_D2.0mm +SMD pad as test Point, diameter 2.0mm +test point SMD pad +0 +1 +1 +TestPoint +TestPoint_Pad_D2.5mm +SMD pad as test Point, diameter 2.5mm +test point SMD pad +0 +1 +1 +TestPoint +TestPoint_Pad_D3.0mm +SMD pad as test Point, diameter 3.0mm +test point SMD pad +0 +1 +1 +TestPoint +TestPoint_Pad_D4.0mm +SMD pad as test Point, diameter 4.0mm +test point SMD pad +0 +1 +1 +TestPoint +TestPoint_Plated_Hole_D2.0mm +Plated Hole as test Point, diameter 2.0mm +test point plated hole +0 +1 +1 +TestPoint +TestPoint_Plated_Hole_D3.0mm +Plated Hole as test Point, diameter 3.0mm +test point plated hole +0 +1 +1 +TestPoint +TestPoint_Plated_Hole_D4.0mm +Plated Hole as test Point, diameter 4.0mm +test point plated hole +0 +1 +1 +TestPoint +TestPoint_Plated_Hole_D5.0mm +Plated Hole as test Point, diameter 5.0mm +test point plated hole +0 +1 +1 +TestPoint +TestPoint_THTPad_1.0x1.0mm_Drill0.5mm +THT rectangular pad as test Point, square 1.0mm side length, hole diameter 0.5mm +test point THT pad rectangle square +0 +1 +1 +TestPoint +TestPoint_THTPad_1.5x1.5mm_Drill0.7mm +THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm +test point THT pad rectangle square +0 +1 +1 +TestPoint +TestPoint_THTPad_2.0x2.0mm_Drill1.0mm +THT rectangular pad as test Point, square 2.0mm_Drill1.0mm side length, hole diameter 1.0mm +test point THT pad rectangle square +0 +1 +1 +TestPoint +TestPoint_THTPad_2.5x2.5mm_Drill1.2mm +THT rectangular pad as test Point, square 2.5mm side length, hole diameter 1.2mm +test point THT pad rectangle square +0 +1 +1 +TestPoint +TestPoint_THTPad_3.0x3.0mm_Drill1.5mm +THT rectangular pad as test Point, square 3.0mm side length, hole diameter 1.5mm +test point THT pad rectangle square +0 +1 +1 +TestPoint +TestPoint_THTPad_4.0x4.0mm_Drill2.0mm +THT rectangular pad as test Point, square 4.0mm side length, hole diameter 2.0mm +test point THT pad rectangle square +0 +1 +1 +TestPoint +TestPoint_THTPad_D1.0mm_Drill0.5mm +THT pad as test Point, diameter 1.0mm, hole diameter 0.5mm +test point THT pad +0 +1 +1 +TestPoint +TestPoint_THTPad_D1.5mm_Drill0.7mm +THT pad as test Point, diameter 1.5mm, hole diameter 0.7mm +test point THT pad +0 +1 +1 +TestPoint +TestPoint_THTPad_D2.0mm_Drill1.0mm +THT pad as test Point, diameter 2.0mm, hole diameter 1.0mm +test point THT pad +0 +1 +1 +TestPoint +TestPoint_THTPad_D2.5mm_Drill1.2mm +THT pad as test Point, diameter 2.5mm, hole diameter 1.2mm +test point THT pad +0 +1 +1 +TestPoint +TestPoint_THTPad_D3.0mm_Drill1.5mm +THT pad as test Point, diameter 3.0mm, hole diameter 1.5mm +test point THT pad +0 +1 +1 +TestPoint +TestPoint_THTPad_D4.0mm_Drill2.0mm +THT pad as test Point, diameter 4.0mm, hole diameter 2.0mm +test point THT pad +0 +1 +1 +Transformer_SMD +Pulse_P0926NL +SMT Gate Drive Transformer, 1:1:1, 8.0x6.3x5.3mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) +pulse pa0926nl +0 +6 +6 +Transformer_SMD +Pulse_PA1323NL +SMT Gate Drive Transformer, 1:1, 9.5x7.1x5.3mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) +pulse pa1323nl +0 +6 +6 +Transformer_SMD +Pulse_PA2001NL +SMT Gate Drive Transformer, 1:1, 8.6x6.7x2.5mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) +pulse pa2001nl pe-68386nl +0 +4 +4 +Transformer_SMD +Pulse_PA2002NL-PA2008NL-PA2009NL +SMT Gate Drive Transformer, 1:1:1 or 2:1:1 or 2.5:1:1 or 1:1, 9.0x8.6x7.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) +pulse pa2002nl pa2008nl pa2009nl p0544nl pa0184nl pa0297nl pa0510nl +0 +6 +6 +Transformer_SMD +Pulse_PA2004NL +SMT Gate Drive Transformer, 1:1:1, 8.6x6.7x3.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) +pulse pa2004nl pa0264nl +0 +6 +6 +Transformer_SMD +Pulse_PA2005NL +SMT Gate Drive Transformer, 1:1:1, 11.8x8.8x4.0mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) +pulse pa2005nl pa0173nl +0 +6 +6 +Transformer_SMD +Pulse_PA2006NL +SMT Gate Drive Transformer, 1:1, 11.8x8.8x4.0mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) +pulse pa2006nl pa0186nl +0 +4 +4 +Transformer_SMD +Pulse_PA2007NL +SMT Gate Drive Transformer, 1:1, 9.0x8.6x7.6mm (https://productfinder.pulseeng.com/products/datasheets/P663.pdf) +pulse pa2007nl +0 +4 +4 +Transformer_SMD +Pulse_PA2777NL +SMT Gate Drive Transformer, 1:1, 7.1x6.1x5.5mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) +pulse pa2777nl +0 +8 +8 +Transformer_SMD +Pulse_PA3493NL +SMT Gate Drive Transformer, 1.25:1, 10.9x9.7x2.7mm (https://productfinder.pulseeng.com/products/datasheets/SPM2007_61.pdf) +pulse pa3493nl +0 +4 +4 +Transformer_SMD +Transformer_Coilcraft_CST1 +Current sense transformer, SMD, 8.0x8.13x5.3mm (https://www.coilcraft.com/pdfs/cst.pdf) +Transformer current sense SMD +0 +8 +8 +Transformer_SMD +Transformer_Coilcraft_CST2 +Current sense transformer, SMD, 8.0x8.13x5.3mm (https://www.coilcraft.com/pdfs/cst.pdf) +Transformer current sense SMD +0 +8 +8 +Transformer_SMD +Transformer_Coilcraft_CST2010 +Current sense transformer, SMD, 14.55x19.91x10.50mm (https://www.coilcraft.com/pdfs/cst2010.pdf) +Transformer current sense SMD +0 +12 +12 +Transformer_SMD +Transformer_CurrentSense_8.4x7.2mm +Transformer current sense SMD 8.4x7.2mm +Transformer current sense SMD +0 +8 +8 +Transformer_SMD +Transformer_Ethernet_Bel_S558-5999-T7-F +Ethernet Transformer, Bel S558-5999-T7-F, https://www.belfuse.com/resources/ICMs/lan-/S558-5999-T7-F.pdf +Ethernet Transformer +0 +16 +16 +Transformer_SMD +Transformer_Ethernet_Bourns_PT61017PEL +https://www.bourns.com/docs/Product-Datasheets/PT61017PEL.pdf +Transformer Ethernet Single Center-Tap +0 +16 +16 +Transformer_SMD +Transformer_Ethernet_HALO_TG111-MSC13 +Transformer Ethernet SMD, https://www.haloelectronics.com/pdf/discrete-genesus.pdf +Transformer Ethernet SMD +0 +24 +24 +Transformer_SMD +Transformer_MACOM_SM-22 +https://cdn.macom.com/datasheets/ETC1-1-13.pdf +RF Transformer +0 +5 +5 +Transformer_SMD +Transformer_NF_ETAL_P2781 +NF-Transformer, ETAL, P2781, SMD, +NF-Transformer ETAL P2781 SMD +0 +8 +7 +Transformer_SMD +Transformer_NF_ETAL_P2781_HandSoldering +NF-Transformer, ETAL, P2781, SMD, Handsoldering +NF-Transformer ETAL P2781 SMD Handsoldering +0 +8 +7 +Transformer_SMD +Transformer_NF_ETAL_P3000 +NF-Reansformer, ETAL, P3000, SMD, +NF-Reansformer ETAL P3000 SMD +0 +15 +13 +Transformer_SMD +Transformer_NF_ETAL_P3000_HandSoldering +NF-Reansformer, ETAL, P3000, SMD, Handsoldering, +NF-Reansformer ETAL P3000 SMD Handsoldering +0 +15 +13 +Transformer_SMD +Transformer_NF_ETAL_P3181 +NF-Transformer, ETAL, P3181, SMD, +NF-Transformer ETAL P3181 SMD +0 +7 +6 +Transformer_SMD +Transformer_NF_ETAL_P3181_HandSoldering +NF-Transformer, ETAL, P3181, SMD, Hand Soldering, +NF-Transformer ETAL P3181 SMD Hand Soldering +0 +7 +6 +Transformer_SMD +Transformer_NF_ETAL_P3188 +NF-Transformer, ETAL, P3188, SMD, +NF-Transformer ETAL P3188 SMD +0 +8 +6 +Transformer_SMD +Transformer_NF_ETAL_P3188_HandSoldering +NF-Transformer, ETAL, P3188, SMD, Handsoldering, +NF-Transformer ETAL P3188 SMD Handsoldering +0 +8 +6 +Transformer_SMD +Transformer_NF_ETAL_P3191 +NF-Transformer, ETAL, P3191, SMD, +NF-Transformer ETAL P3191 SMD +0 +8 +6 +Transformer_SMD +Transformer_NF_ETAL_P3191_HandSoldering +NF-Transformer, ETAL, P3191, SMD, Handsoldering, +NF-Transformer ETAL P3191 SMD Handsoldering +0 +8 +6 +Transformer_SMD +Transformer_Pulse_H1100NL +For H1100NL, H1101NL, H1102NL, H1121NL, H1183NL, H1199NL, HX1188NL, HX1198NL and H1302NL. https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/H1102NL/doc_part/H1102NL.pdf +H1100NL H1101NL H1102NL H1121NL H1183NL H1199NL HX1188NL HX1198NL H1302N +0 +16 +16 +Transformer_THT +Autotransformer_Toroid_1Tap_Horizontal_D9.0mm_Amidon-T30 +Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 9mm, Amidon T30, +Autotransformer Toroid horizontal laying 1 Tap Diameter 9mm Amidon T30 +0 +3 +3 +Transformer_THT +Autotransformer_Toroid_1Tap_Horizontal_D10.5mm_Amidon-T37 +Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 10,5mm, Amidon T37, +Autotransformer Toroid horizontal laying 1 Tap Diameter 10 5mm Amidon T37 +0 +3 +3 +Transformer_THT +Autotransformer_Toroid_1Tap_Horizontal_D12.5mm_Amidon-T44 +Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 12,5mm, Amidon T44, +Autotransformer Toroid horizontal laying 1 Tap Diameter 12 5mm Amidon T44 +0 +3 +3 +Transformer_THT +Autotransformer_Toroid_1Tap_Horizontal_D14.0mm_Amidon-T50 +Choke, Inductance, Autotransformer, Toroid, horizontal, laying, 1 Tap, Diameter 14mm, Amidon T50, +Choke Inductance Autotransformer Toroid horizontal laying 1 Tap Diameter 14mm Amidon T50 +0 +3 +3 +Transformer_THT +Autotransformer_ZS1052-AC +Ignition coil for xenon flash, http://www.excelitas.com/downloads/ZS1052ACH.pdf +ignition coil autotransformer +0 +3 +3 +Transformer_THT +Transformer_37x44 +transformer 37x44mm² +transformer 37x44mm² +0 +12 +4 +Transformer_THT +Transformer_Breve_TEZ-22x24 +http://www.breve.pl/pdf/ANG/TEZ_ang.pdf +TEZ PCB Transformer +0 +7 +7 +Transformer_THT +Transformer_Breve_TEZ-28x33 +http://www.breve.pl/pdf/ANG/TEZ_ang.pdf +TEZ PCB Transformer +0 +9 +9 +Transformer_THT +Transformer_Breve_TEZ-35x42 +http://www.breve.pl/pdf/ANG/TEZ_ang.pdf +TEZ PCB Transformer +0 +9 +9 +Transformer_THT +Transformer_Breve_TEZ-38x45 +http://www.breve.pl/pdf/ANG/TEZ_ang.pdf +TEZ PCB Transformer +0 +9 +9 +Transformer_THT +Transformer_Breve_TEZ-44x52 +http://www.breve.pl/pdf/ANG/TEZ_ang.pdf +TEZ PCB Transformer +0 +10 +10 +Transformer_THT +Transformer_Breve_TEZ-47x57 +http://www.breve.pl/pdf/ANG/TEZ_ang.pdf +TEZ PCB Transformer +0 +13 +13 +Transformer_THT +Transformer_CHK_EI30-2VA_1xSec +Trafo, Printtrafo, CHK, EI30, 2VA, 1x Sec,http://www.eratransformers.com/downloads/030-7585.0.pdf +Trafo Printtrafo CHK EI30 2VA 1x Sec +0 +10 +10 +Transformer_THT +Transformer_CHK_EI30-2VA_2xSec +Trafo, Printtrafo, CHK, EI30, 2VA, 2x Sec, +Trafo Printtrafo CHK EI30 2VA 2x Sec +0 +10 +10 +Transformer_THT +Transformer_CHK_EI30-2VA_Neutral +Trafo, Printtrafo, CHK, EI30, 2VA, neutral, +Trafo Printtrafo CHK EI30 2VA neutral +0 +10 +10 +Transformer_THT +Transformer_CHK_EI38-3VA_1xSec +Trafo, Printtrafo, CHK, EI38, 3VA, 1x Sec, http://www.eratransformers.com/product-detail/20 +Trafo Printtrafo CHK EI38 3VA 1x Sec +0 +10 +10 +Transformer_THT +Transformer_CHK_EI38-3VA_2xSec +Trafo, Printtrafo, CHK, EI38, 3VA, 2x Sec, http://www.eratransformers.com/product-detail/20 +Trafo Printtrafo CHK EI38 3VA 2x Sec +0 +10 +10 +Transformer_THT +Transformer_CHK_EI38-3VA_Neutral +Trafo, Printtrafo, CHK, EI38, 3VA, neutral, http://www.eratransformers.com/product-detail/20 +Trafo Printtrafo CHK EI42 3VA neutral +0 +10 +10 +Transformer_THT +Transformer_CHK_EI42-5VA_1xSec +Trafo, Printtrafo, CHK, EI42, 5VA, 1x Sec, +Trafo Printtrafo CHK EI42 5VA 1x Sec +0 +10 +10 +Transformer_THT +Transformer_CHK_EI42-5VA_2xSec +Trafo, Printtrafo, CHK, EI42, 5VA, 2x Sec, +Trafo Printtrafo CHK EI42 5VA 2x Sec +0 +10 +10 +Transformer_THT +Transformer_CHK_EI42-5VA_Neutral +Trafo, Printtrafo, CHK, EI42, 5VA, neutral, +Trafo Printtrafo CHK EI42 5VA neutral +0 +10 +10 +Transformer_THT +Transformer_CHK_EI48-8VA_1xSec +Trafo, Printtrafo, CHK, EI48, 8VA, 1x Sec, http://www.eratransformers.com/product-detail/18 +Trafo Printtrafo CHK EI48 8VA 1x Sec +0 +12 +12 +Transformer_THT +Transformer_CHK_EI48-8VA_2xSec +Trafo, Printtrafo, CHK, EI48, 8VA, 2x Sec, http://www.eratransformers.com/product-detail/18 +Trafo Printtrafo CHK EI48 8VA 2x Sec +0 +12 +12 +Transformer_THT +Transformer_CHK_EI48-8VA_Neutral +Trafo, Printtrafo, CHK, EI48, 8VA, neutral, http://www.eratransformers.com/product-detail/18 +Trafo Printtrafo CHK EI48 8VA neutral +0 +12 +12 +Transformer_THT +Transformer_CHK_EI48-10VA_1xSec +Trafo, Printtrafo, CHK, EI48, 10VA, 1x Sec, +Trafo Printtrafo CHK EI48 10VA 1x Sec +0 +12 +12 +Transformer_THT +Transformer_CHK_EI48-10VA_2xSec +Trafo, Printtrafo, CHK, EI48, 10VA, 2x Sec, http://www.eratransformers.com/product-detail/18 +Trafo Printtrafo CHK EI48 10VA 2x Sec +0 +12 +12 +Transformer_THT +Transformer_CHK_EI48-10VA_Neutral +Trafo, Printtrafo, CHK, EI48, 10VA, neutral, http://www.eratransformers.com/product-detail/18 +Trafo Printtrafo CHK EI48 10VA neutral +0 +12 +12 +Transformer_THT +Transformer_CHK_EI54-12VA_1xSec +Trafo, Printtrafo, CHK, EI54, 12VA, 1x Sec,http://www.eratransformers.com/product-detail/19 +Trafo Printtrafo CHK EI54 12VA 1x Sec +0 +14 +14 +Transformer_THT +Transformer_CHK_EI54-12VA_2xSec +Trafo, Printtrafo, CHK, EI54, 12VA, 2x Sec,http://www.eratransformers.com/product-detail/19 +Trafo Printtrafo CHK EI54 12VA 2x Sec +0 +14 +14 +Transformer_THT +Transformer_CHK_EI54-12VA_Neutral +Trafo, Printtrafo, CHK, EI54, 12VA, neutral,http://www.eratransformers.com/product-detail/19 +Trafo Printtrafo CHK EI54 12VA neutral +0 +14 +14 +Transformer_THT +Transformer_CHK_EI54-16VA_1xSec +Trafo, Printtrafo, CHK, EI54, 16VA, 1x Sec,http://www.eratransformers.com/product-detail/19 +Trafo Printtrafo CHK EI54 16VA 1x Sec +0 +14 +14 +Transformer_THT +Transformer_CHK_EI54-16VA_2xSec +Trafo, Printtrafo, CHK, EI54, 16VA, 2x Sec,http://www.eratransformers.com/product-detail/19 +Trafo Printtrafo CHK EI54 16VA 2x Sec +0 +14 +14 +Transformer_THT +Transformer_CHK_EI54-16VA_Neutral +Trafo, Printtrafo, CHK, EI54, 16VA, neutral,http://www.eratransformers.com/product-detail/19 +Trafo Printtrafo CHK EI54 16VA neutral +0 +14 +14 +Transformer_THT +Transformer_CHK_UI30-4VA_Flat +Trafo, Flattrafo, CHK, UI30, 4VA, +Trafo Flattrafo CHK UI30 4VA +0 +16 +16 +Transformer_THT +Transformer_CHK_UI39-10VA_Flat +Trafo, Flattrafo, CHK, UI39, 10VA, +Trafo Flattrafo CHK UI39 10VA +0 +20 +20 +Transformer_THT +Transformer_Coilcraft_Q4434-B_Rhombus-T1311 +Transformator, Transformer, Flyback, Coilcraft Q4434-B, Rgombus T1311, +Transformator Transformer Flyback Coilcraft Q4434-B Rgombus T1311 +0 +8 +8 +Transformer_THT +Transformer_EPCOS_B66359A1013T_Horizontal +Transformer, Transformator, ETD29, 13 Pin, Horizontal, EPCOS-B66359A1013T, +Transformer Transformator ETD29 13 Pin Horizontal EPCOS-B66359A1013T +0 +13 +13 +Transformer_THT +Transformer_EPCOS_B66359J1014T_Vertical +Transformer, Transformator, ETD29, 14 Pin, Vertical, EPCOS-B66359J1014T, +Transformer Transformator ETD29 14 Pin Vertical EPCOS-B66359J1014T +0 +14 +14 +Transformer_THT +Transformer_Microphone_Lundahl_LL1538 +AUDIO TRAFO LUNDAHL, https://www.lundahltransformers.com/wp-content/uploads/datasheets/1538_8xl.pdf +AUDIO TRAFO LUNDAHL +0 +7 +7 +Transformer_THT +Transformer_Microphone_Lundahl_LL1587 +AUDIO TRAFO LUNDAHL, https://www.lundahltransformers.com/wp-content/uploads/datasheets/1587.pdf +AUDIO TRAFO LUNDAHL +0 +7 +7 +Transformer_THT +Transformer_Myrra_74040_Horizontal +Transformer, Transformator, ETD29, 13 Pin, Horizontal, Myrra-74040, +Transformer Transformator ETD29 13 Pin Horizontal Myrra-74040 +0 +13 +13 +Transformer_THT +Transformer_Myrra_EF20_7408x +EF20 flyback transformer,http://myrra.com/wp-content/uploads/2017/09/Datasheet-74087-74088-74089-rev-A.pdf +transformer flyback SMPS +0 +9 +9 +Transformer_THT +Transformer_NF_ETAL_1-1_P1200 +NF-Transformer, 1:1, ETAL P1200,http://www.etalgroup.com/sites/default/files/products/P1200_April_2005.pdf +NF-Transformer 1to1 ETAL P1200 +0 +4 +4 +Transformer_THT +Transformer_NF_ETAL_P1165 +NF-Transformer, ETAL, P1165,http://www.etalgroup.com/sites/default/files/products/P1165_February_2006.pdf +NF-Transformer ETAL P1165 +0 +4 +4 +Transformer_THT +Transformer_NF_ETAL_P3324 +NF-Transformer, ETAL P3324,http://www.etalgroup.com/sites/default/files/products/P3324_April_2005.pdf +NF-Transformer ETAL P3324 +0 +4 +4 +Transformer_THT +Transformer_NF_ETAL_P3356 +NF-Transformer, ETAL P3356, http://www.etalgroup.com/sites/default/files/products/P3356_December_2005.pdf +NF-Transformer ETAL P3356 +0 +4 +4 +Transformer_THT +Transformer_Toroid_Horizontal_D9.0mm_Amidon-T30 +Transformer, Toroid, horizontal, laying, Diameter 9mm, Amidon, T30, +Transformer Toroid horizontal laying Diameter 9mm Amidon T30 +0 +4 +4 +Transformer_THT +Transformer_Toroid_Horizontal_D10.5mm_Amidon-T37 +Transformer, Toroid, horizontal, laying, Diameter 10,5mm, Amidon T37, +Transformer Toroid horizontal laying Diameter 10 5mm Amidon T37 +0 +4 +4 +Transformer_THT +Transformer_Toroid_Horizontal_D12.5mm_Amidon-T44 +Transformer, Toroid, horizontal, laying, Diameter 12,5mm, Amidon T44, +Transformer Toroid horizontal laying Diameter 12 5mm Amidon T44 +0 +4 +4 +Transformer_THT +Transformer_Toroid_Horizontal_D14.0mm_Amidon-T50 +Transformer, Toroid, horizontal, laying, Diameter 14mm, Amidon T50, +Transformer Toroid horizontal laying Diameter 14mm Amidon T50 +0 +4 +4 +Transformer_THT +Transformer_Toroid_Horizontal_D18.0mm +Transformer, Toroid, tapped, horizontal, laying, Diameter 18mm, +Transformer Toroid tapped horizontal laying Diameter 18mm +0 +5 +4 +Transformer_THT +Transformer_Toroid_Tapped_Horizontal_D9.0mm_Amidon-T30 +Transformer, Toroid, tapped, horizontal, laying, Diameter 9mm, Amidon, T30, +Transformer Toroid tapped horizontal laying Diameter 9mm Amidon T30 +0 +6 +6 +Transformer_THT +Transformer_Toroid_Tapped_Horizontal_D10.5mm_Amidon-T37 +Transformer, Toroid, tapped, horizontal, laying, Diameter 10,5mm, Amidon, T37, +Transformer Toroid tapped horizontal laying Diameter 10 5mm Amidon T37 +0 +6 +6 +Transformer_THT +Transformer_Toroid_Tapped_Horizontal_D12.5mm_Amidon-T44 +Transformer, Toroid, tapped, horizontal, laying, Diameter 12,5mm, Amidon, T44, +Transformer Toroid tapped horizontal laying Diameter 12 5mm Amidon T44 +0 +6 +6 +Transformer_THT +Transformer_Toroid_Tapped_Horizontal_D14.0mm_Amidon-T50 +Transformer, Toroid, tapped, horizontal, laying, Diameter 14mm, Amidon T50, +Transformer Toroid tapped horizontal laying Diameter 14mm Amidon T50 +0 +6 +6 +Transformer_THT +Transformer_Wuerth_750343373 +Transformer, horizontal core with bobbin, 10 pin, 3.81mm pitch, 15.24mm row spacing, 22x23x17.53mm (https://katalog.we-online.com/ctm/datasheet/750343373.pdf) +transformer flyback +0 +10 +10 +Valve +Valve_ECC-83-1 +Valve ECC-83-1 round pins +Valve ECC-83-1 round pins +0 +9 +9 +Valve +Valve_ECC-83-2 +Valve ECC-83-2 flat pins +Valve ECC-83-2 flat pins +0 +10 +9 +Valve +Valve_EURO +Valve Euro +Valve Euro +0 +7 +5 +Valve +Valve_Glimm +Valve Glimm +Valve Glimm +0 +2 +2 +Valve +Valve_Mini_G +Valve mini G +Valve mini G +0 +9 +7 +Valve +Valve_Mini_P +Valve mini P +Valve mini P +0 +7 +7 +Valve +Valve_Mini_Pentode_Linear +Mini-Pentode, 5-pin, e.g. JAN6418 +Valve Mini-Pentode 5-pin JAN6418 +0 +5 +5 +Valve +Valve_Noval_G +Valve NOVAL G +Valve NOVAL G +0 +11 +9 +Valve +Valve_Noval_P +Valve NOVAL P +Valve NOVAL P +0 +9 +9 +Valve +Valve_Octal +8-pin round valve +valve +0 +9 +8 +Varistor +RV_Disc_D7mm_W3.4mm_P5mm +Varistor, diameter 7mm, width 3.4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W3.5mm_P5mm +Varistor, diameter 7mm, width 3.5mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W3.6mm_P5mm +Varistor, diameter 7mm, width 3.6mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W3.7mm_P5mm +Varistor, diameter 7mm, width 3.7mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W3.8mm_P5mm +Varistor, diameter 7mm, width 3.8mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W3.9mm_P5mm +Varistor, diameter 7mm, width 3.9mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W4.2mm_P5mm +Varistor, diameter 7mm, width 4.2mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W4.3mm_P5mm +Varistor, diameter 7mm, width 4.3mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W4.5mm_P5mm +Varistor, diameter 7mm, width 4.5mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W4.8mm_P5mm +Varistor, diameter 7mm, width 4.8mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W4.9mm_P5mm +Varistor, diameter 7mm, width 4.9mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W4mm_P5mm +Varistor, diameter 7mm, width 4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W5.1mm_P5mm +Varistor, diameter 7mm, width 5.1mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W5.4mm_P5mm +Varistor, diameter 7mm, width 5.4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W5.5mm_P5mm +Varistor, diameter 7mm, width 5.5mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D7mm_W5.7mm_P5mm +Varistor, diameter 7mm, width 5.7mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.3mm_P5mm +Varistor, diameter 9mm, width 3.3mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.4mm_P5mm +Varistor, diameter 9mm, width 3.4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.5mm_P5mm +Varistor, diameter 9mm, width 3.5mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.6mm_P5mm +Varistor, diameter 9mm, width 3.6mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.7mm_P5mm +Varistor, diameter 9mm, width 3.7mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.8mm_P5mm +Varistor, diameter 9mm, width 3.8mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W3.9mm_P5mm +Varistor, diameter 9mm, width 3.9mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W4.1mm_P5mm +Varistor, diameter 9mm, width 4.1mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W4.2mm_P5mm +Varistor, diameter 9mm, width 4.2mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W4.4mm_P5mm +Varistor, diameter 9mm, width 4.4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W4.5mm_P5mm +Varistor, diameter 9mm, width 4.5mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W4.8mm_P5mm +Varistor, diameter 9mm, width 4.8mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W4mm_P5mm +Varistor, diameter 9mm, width 4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W5.2mm_P5mm +Varistor, diameter 9mm, width 5.2mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W5.4mm_P5mm +Varistor, diameter 9mm, width 5.4mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W5.5mm_P5mm +Varistor, diameter 9mm, width 5.5mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W5.7mm_P5mm +Varistor, diameter 9mm, width 5.7mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D9mm_W6.1mm_P5mm +Varistor, diameter 9mm, width 6.1mm, pitch 5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W3.9mm_P7.5mm +Varistor, diameter 12mm, width 3.9mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.2mm_P7.5mm +Varistor, diameter 12mm, width 4.2mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.3mm_P7.5mm +Varistor, diameter 12mm, width 4.3mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.4mm_P7.5mm +Varistor, diameter 12mm, width 4.4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.5mm_P7.5mm +Varistor, diameter 12mm, width 4.5mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.6mm_P7.5mm +Varistor, diameter 12mm, width 4.6mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.7mm_P7.5mm +Varistor, diameter 12mm, width 4.7mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4.8mm_P7.5mm +Varistor, diameter 12mm, width 4.8mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W4mm_P7.5mm +Varistor, diameter 12mm, width 4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W5.1mm_P7.5mm +Varistor, diameter 12mm, width 5.1mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W5.4mm_P7.5mm +Varistor, diameter 12mm, width 5.4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W5.8mm_P7.5mm +Varistor, diameter 12mm, width 5.8mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W5mm_P7.5mm +Varistor, diameter 12mm, width 5mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W6.1mm_P7.5mm +Varistor, diameter 12mm, width 6.1mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W6.2mm_P7.5mm +Varistor, diameter 12mm, width 6.2mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W6.3mm_P7.5mm +Varistor, diameter 12mm, width 6.3mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W6.7mm_P7.5mm +Varistor, diameter 12mm, width 6.7mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W7.1mm_P7.5mm +Varistor, diameter 12mm, width 7.1mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W7.5mm_P7.5mm +Varistor, diameter 12mm, width 7.5mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D12mm_W7.9mm_P7.5mm +Varistor, diameter 12mm, width 7.9mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W3.9mm_P7.5mm +Varistor, diameter 15.5mm, width 3.9mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.2mm_P7.5mm +Varistor, diameter 15.5mm, width 4.2mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.3mm_P7.5mm +Varistor, diameter 15.5mm, width 4.3mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.4mm_P7.5mm +Varistor, diameter 15.5mm, width 4.4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.5mm_P7.5mm +Varistor, diameter 15.5mm, width 4.5mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.6mm_P7.5mm +Varistor, diameter 15.5mm, width 4.6mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.7mm_P7.5mm +Varistor, diameter 15.5mm, width 4.7mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.8mm_P7.5mm +Varistor, diameter 15.5mm, width 4.8mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4.9mm_P7.5mm +Varistor, diameter 15.5mm, width 4.9mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W4mm_P7.5mm +Varistor, diameter 15.5mm, width 4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W5.2mm_P7.5mm +Varistor, diameter 15.5mm, width 5.2mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W5.4mm_P7.5mm +Varistor, diameter 15.5mm, width 5.4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W5.9mm_P7.5mm +Varistor, diameter 15.5mm, width 5.9mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W5mm_P7.5mm +Varistor, diameter 15.5mm, width 5mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W6.1mm_P7.5mm +Varistor, diameter 15.5mm, width 6.1mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W6.3mm_P7.5mm +Varistor, diameter 15.5mm, width 6.3mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W6.4mm_P7.5mm +Varistor, diameter 15.5mm, width 6.4mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W6.8mm_P7.5mm +Varistor, diameter 15.5mm, width 6.8mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W7.2mm_P7.5mm +Varistor, diameter 15.5mm, width 7.2mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W7.5mm_P7.5mm +Varistor, diameter 15.5mm, width 7.5mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W8mm_P7.5mm +Varistor, diameter 15.5mm, width 8mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D15.5mm_W11mm_P7.5mm +Varistor, diameter 15.5mm, width 11mm, pitch 7.5mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D16.5mm_W6.7mm_P7.5mm +Varistor, diameter 16.5mm, width 6.7mm, pitch 5mm, https://katalog.we-online.de/pbs/datasheet/820542711.pdf +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D21.5mm_W4.3mm_P10mm +Varistor, diameter 21.5mm, width 4.3mm, pitch 10mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D21.5mm_W4.4mm_P10mm +Varistor, diameter 21.5mm, width 4.4mm, pitch 10mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D21.5mm_W4.5mm_P10mm +Varistor, diameter 21.5mm, width 4.5mm, pitch 10mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D21.5mm_W4.6mm_P10mm +Varistor, diameter 21.5mm, width 4.6mm, pitch 10mm +varistor SIOV +0 +2 +2 +Varistor +RV_Disc_D21.5mm_W4.7mm_P10mm +Varistor, diameter 21.5mm, width 4.7mm, pitch 10mm +varistor SIOV +0 +2 +2 +Varistor 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+penguin +TE_MS860702BA01-50 + + +0 +8 +8 +penguin +finaltesthopefully + + +0 +0 +0 +penguin +ggsgfdsgfdg + + +0 +0 +0 +penguin +penguinkicad + + +0 +0 +0 +penguin +penguinlogo + + +0 +0 +0 +penguin +penguinlogofinal + + +0 +0 +0 +penguin +pin_array + + +0 +0 +0 +penguin +test2 + + +0 +0 +0 +penguin +test3 + + +0 +0 +0 +penguin +test4 + + +0 +0 +0 +penguin +test5 + + +0 +0 +0 +penguin +test6 + + +0 +0 +0 +penguin +test7 + + +0 +0 +0 +penguin +test8 + + +0 +0 +0 +penguin +test9 + + +0 +0 +0 +penguin +test10 + + +0 +0 +0 +penguin +test11 + + +0 +0 +0 +penguin +test12 + + +0 +0 +0 +penguin +test13 + + +0 +0 +0 +penguin +test14 + + +0 +0 +0 +penguin +test15 + + +0 +0 +0 +penguin +test99 + + +0 +0 +0 +penguin +test100 + + +0 +0 +0 +penguin +test101 + + +0 +0 +0 +penguin +test102 + + +0 +0 +0 +penguin +test103 + + +0 +0 +0 +penguin +test104 + + +0 +0 +0 +penguin +test105 + + +0 +0 +0 +penguin +test106 + + +0 +0 +0 +proj_modules +SOP80P1030X264-36N + + +0 +36 +36 diff --git a/electrical/same54_dev_board/fp-lib-table b/electrical/same54_dev_board/fp-lib-table index 241db4d..1a41225 100644 --- a/electrical/same54_dev_board/fp-lib-table +++ b/electrical/same54_dev_board/fp-lib-table @@ -1,3 +1,3 @@ -(fp_lib_table - (lib (name proj_modules)(type KiCad)(uri ${KIPRJMOD}/modules/proj_modules.pretty)(options "")(descr "")) -) +(fp_lib_table + (lib (name proj_modules)(type KiCad)(uri ${KIPRJMOD}/modules/proj_modules.pretty)(options "")(descr "")) +) diff --git a/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.bck b/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.bck index 6592e62..dc90181 100644 --- a/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.bck +++ b/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.bck @@ -1,9 +1,9 @@ -EESchema-DOCLIB Version 2.0 -# -$CMP Conn_02x20_Odd_Even_LCD_INTF -D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/) -K connector -F ~ -$ENDCMP -# -#End Doc Library +EESchema-DOCLIB Version 2.0 +# +$CMP Conn_02x20_Odd_Even_LCD_INTF +D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/) +K connector +F ~ +$ENDCMP +# +#End Doc Library diff --git a/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.dcm b/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.dcm index 6592e62..dc90181 100644 --- a/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.dcm +++ b/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.dcm @@ -1,9 +1,9 @@ -EESchema-DOCLIB Version 2.0 -# -$CMP Conn_02x20_Odd_Even_LCD_INTF -D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/) -K connector -F ~ -$ENDCMP -# -#End Doc Library +EESchema-DOCLIB Version 2.0 +# +$CMP Conn_02x20_Odd_Even_LCD_INTF +D Generic connectable mounting pin connector, double row, 02x20, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/) +K connector +F ~ +$ENDCMP +# +#End Doc Library diff --git a/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.lib b/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.lib index 8433445..702e68a 100644 --- a/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.lib +++ b/electrical/same54_dev_board/libraries/Conn_02x20_LCD_INTF.lib @@ -1,99 +1,99 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# Conn_02x20_Odd_Even_LCD_INTF -# -DEF Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N -F0 "J" 0 -1100 50 H V C CNN -F1 "Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN -F2 "" -400 0 50 H I C CNN -F3 "" -400 0 50 H I C CNN -$FPLIST - Connector*:*_2x??-1MP* -$ENDFPLIST -DRAW -S -450 -995 -400 -1005 1 1 6 N -S -450 -895 -400 -905 1 1 6 N -S -450 -795 -400 -805 1 1 6 N -S -450 -695 -400 -705 1 1 6 N -S -450 -595 -400 -605 1 1 6 N -S -450 -495 -400 -505 1 1 6 N -S -450 -395 -400 -405 1 1 6 N -S -450 -295 -400 -305 1 1 6 N -S -450 -195 -400 -205 1 1 6 N -S -450 -95 -400 -105 1 1 6 N -S -450 5 -400 -5 1 1 6 N -S -450 105 -400 95 1 1 6 N -S -450 205 -400 195 1 1 6 N -S -450 305 -400 295 1 1 6 N -S -450 405 -400 395 1 1 6 N -S -450 505 -400 495 1 1 6 N -S -450 605 -400 595 1 1 6 N -S -450 705 -400 695 1 1 6 N -S -450 805 -400 795 1 1 6 N -S -450 905 -400 895 1 1 6 N -S -450 950 450 -1050 1 1 10 f -S 450 -995 400 -1005 1 1 6 N -S 450 -895 400 -905 1 1 6 N -S 450 -795 400 -805 1 1 6 N -S 450 -695 400 -705 1 1 6 N -S 450 -595 400 -605 1 1 6 N -S 450 -495 400 -505 1 1 6 N -S 450 -395 400 -405 1 1 6 N -S 450 -295 400 -305 1 1 6 N -S 450 -195 400 -205 1 1 6 N -S 450 -95 400 -105 1 1 6 N -S 450 5 400 -5 1 1 6 N -S 450 105 400 95 1 1 6 N -S 450 205 400 195 1 1 6 N -S 450 305 400 295 1 1 6 N -S 450 405 400 395 1 1 6 N -S 450 505 400 495 1 1 6 N -S 450 605 400 595 1 1 6 N -S 450 705 400 695 1 1 6 N -S 450 805 400 795 1 1 6 N -S 450 905 400 895 1 1 6 N -X VCC 1 -600 900 150 R 50 50 1 1 W -X ~TFT_WR 10 600 500 150 L 50 50 1 1 P -X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P -X TFT_TE 12 600 400 150 L 50 50 1 1 I -X TFT_D0 13 -600 300 150 R 50 50 1 1 P -X TFT_D1 14 600 300 150 L 50 50 1 1 P -X TFT_D2 15 -600 200 150 R 50 50 1 1 P -X TFT_D3 16 600 200 150 L 50 50 1 1 P -X TFT_D4 17 -600 100 150 R 50 50 1 1 P -X TFT_D5 18 600 100 150 L 50 50 1 1 P -X TFT_D6 19 -600 0 150 R 50 50 1 1 P -X GND 2 600 900 150 L 50 50 1 1 P -X TFT_D7 20 600 0 150 L 50 50 1 1 P -X TFT_D8 21 -600 -100 150 R 50 50 1 1 P -X TFT_D9 22 600 -100 150 L 50 50 1 1 P -X TFT_D10 23 -600 -200 150 R 50 50 1 1 P -X TFT_D11 24 600 -200 150 L 50 50 1 1 P -X TFT_D12 25 -600 -300 150 R 50 50 1 1 P -X TFT_D13 26 600 -300 150 L 50 50 1 1 P -X TFT_D14 27 -600 -400 150 R 50 50 1 1 P -X TFT_D15 28 600 -400 150 L 50 50 1 1 P -X TFT_D16 29 -600 -500 150 R 50 50 1 1 P -X CPT_SCL 3 -600 800 150 R 50 50 1 1 P -X TFT_D17 30 600 -500 150 L 50 50 1 1 P -X TFT_D18 31 -600 -600 150 R 50 50 1 1 P -X TFT_D19 32 600 -600 150 L 50 50 1 1 P -X TFT_D20 33 -600 -700 150 R 50 50 1 1 P -X TFT_D21 34 600 -700 150 L 50 50 1 1 P -X TFT_D22 35 -600 -800 150 R 50 50 1 1 P -X TFT_D23 36 600 -800 150 L 50 50 1 1 P -X TFT_STB 37 -600 -900 150 R 50 50 1 1 P -X NC 38 600 -900 150 L 50 50 1 1 N -X Pin_39 39 -600 -1000 150 R 50 50 1 1 P -X CPT_SDA 4 600 800 150 L 50 50 1 1 P -X NC 40 600 -1000 150 L 50 50 1 1 N -X CPT_INT 5 -600 700 150 R 50 50 1 1 P -X TFT_GPO 6 600 700 150 L 50 50 1 1 O -X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P -X TFT_D/C 8 600 600 150 L 50 50 1 1 P -X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P -ENDDRAW -ENDDEF -# -#End Library +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Conn_02x20_Odd_Even_LCD_INTF +# +DEF Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N +F0 "J" 0 -1100 50 H V C CNN +F1 "Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN +F2 "" -400 0 50 H I C CNN +F3 "" -400 0 50 H I C CNN +$FPLIST + Connector*:*_2x??-1MP* +$ENDFPLIST +DRAW +S -450 -995 -400 -1005 1 1 6 N +S -450 -895 -400 -905 1 1 6 N +S -450 -795 -400 -805 1 1 6 N +S -450 -695 -400 -705 1 1 6 N +S -450 -595 -400 -605 1 1 6 N +S -450 -495 -400 -505 1 1 6 N +S -450 -395 -400 -405 1 1 6 N +S -450 -295 -400 -305 1 1 6 N +S -450 -195 -400 -205 1 1 6 N +S -450 -95 -400 -105 1 1 6 N +S -450 5 -400 -5 1 1 6 N +S -450 105 -400 95 1 1 6 N +S -450 205 -400 195 1 1 6 N +S -450 305 -400 295 1 1 6 N +S -450 405 -400 395 1 1 6 N +S -450 505 -400 495 1 1 6 N +S -450 605 -400 595 1 1 6 N +S -450 705 -400 695 1 1 6 N +S -450 805 -400 795 1 1 6 N +S -450 905 -400 895 1 1 6 N +S -450 950 450 -1050 1 1 10 f +S 450 -995 400 -1005 1 1 6 N +S 450 -895 400 -905 1 1 6 N +S 450 -795 400 -805 1 1 6 N +S 450 -695 400 -705 1 1 6 N +S 450 -595 400 -605 1 1 6 N +S 450 -495 400 -505 1 1 6 N +S 450 -395 400 -405 1 1 6 N +S 450 -295 400 -305 1 1 6 N +S 450 -195 400 -205 1 1 6 N +S 450 -95 400 -105 1 1 6 N +S 450 5 400 -5 1 1 6 N +S 450 105 400 95 1 1 6 N +S 450 205 400 195 1 1 6 N +S 450 305 400 295 1 1 6 N +S 450 405 400 395 1 1 6 N +S 450 505 400 495 1 1 6 N +S 450 605 400 595 1 1 6 N +S 450 705 400 695 1 1 6 N +S 450 805 400 795 1 1 6 N +S 450 905 400 895 1 1 6 N +X VCC 1 -600 900 150 R 50 50 1 1 W +X ~TFT_WR 10 600 500 150 L 50 50 1 1 P +X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P +X TFT_TE 12 600 400 150 L 50 50 1 1 I +X TFT_D0 13 -600 300 150 R 50 50 1 1 P +X TFT_D1 14 600 300 150 L 50 50 1 1 P +X TFT_D2 15 -600 200 150 R 50 50 1 1 P +X TFT_D3 16 600 200 150 L 50 50 1 1 P +X TFT_D4 17 -600 100 150 R 50 50 1 1 P +X TFT_D5 18 600 100 150 L 50 50 1 1 P +X TFT_D6 19 -600 0 150 R 50 50 1 1 P +X GND 2 600 900 150 L 50 50 1 1 P +X TFT_D7 20 600 0 150 L 50 50 1 1 P +X TFT_D8 21 -600 -100 150 R 50 50 1 1 P +X TFT_D9 22 600 -100 150 L 50 50 1 1 P +X TFT_D10 23 -600 -200 150 R 50 50 1 1 P +X TFT_D11 24 600 -200 150 L 50 50 1 1 P +X TFT_D12 25 -600 -300 150 R 50 50 1 1 P +X TFT_D13 26 600 -300 150 L 50 50 1 1 P +X TFT_D14 27 -600 -400 150 R 50 50 1 1 P +X TFT_D15 28 600 -400 150 L 50 50 1 1 P +X TFT_D16 29 -600 -500 150 R 50 50 1 1 P +X CPT_SCL 3 -600 800 150 R 50 50 1 1 P +X TFT_D17 30 600 -500 150 L 50 50 1 1 P +X TFT_D18 31 -600 -600 150 R 50 50 1 1 P +X TFT_D19 32 600 -600 150 L 50 50 1 1 P +X TFT_D20 33 -600 -700 150 R 50 50 1 1 P +X TFT_D21 34 600 -700 150 L 50 50 1 1 P +X TFT_D22 35 -600 -800 150 R 50 50 1 1 P +X TFT_D23 36 600 -800 150 L 50 50 1 1 P +X TFT_STB 37 -600 -900 150 R 50 50 1 1 P +X NC 38 600 -900 150 L 50 50 1 1 N +X Pin_39 39 -600 -1000 150 R 50 50 1 1 P +X CPT_SDA 4 600 800 150 L 50 50 1 1 P +X NC 40 600 -1000 150 L 50 50 1 1 N +X CPT_INT 5 -600 700 150 R 50 50 1 1 P +X TFT_GPO 6 600 700 150 L 50 50 1 1 O +X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P +X TFT_D/C 8 600 600 150 L 50 50 1 1 P +X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm b/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm index 5f3ed79..5dd71cb 100644 --- a/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm +++ b/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm @@ -1,3 +1,3 @@ -EESchema-DOCLIB Version 2.0 -# -#End Doc Library +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/electrical/same54_dev_board/libraries/MAX7301AAX_.lib b/electrical/same54_dev_board/libraries/MAX7301AAX_.lib index 7889ab1..aeb3822 100644 --- a/electrical/same54_dev_board/libraries/MAX7301AAX_.lib +++ b/electrical/same54_dev_board/libraries/MAX7301AAX_.lib @@ -1,60 +1,60 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# MAX7301AAX+ -# -DEF MAX7301AAX+ U 0 40 Y Y 1 L N -F0 "U" -500 1339 50 H V L BNN -F1 "MAX7301AAX+" -500 -1457 50 H V L BNN -F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN -F3 "Maxim Integrated" 0 0 50 H I L BNN -F4 "None" 0 0 50 H I L BNN -F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN -F6 "SSOP-36 Maxim" 0 0 50 H I L BNN -F7 "Unavailable" 0 0 50 H I L BNN -F8 "MAX7301AAX+" 0 0 50 H I L BNN -DRAW -P 2 0 0 16 -500 -1300 -500 1300 N -P 2 0 0 16 -500 1300 500 1300 N -P 2 0 0 16 500 -1300 -500 -1300 N -P 2 0 0 16 500 1300 500 -1300 N -X ISET 1 -700 1000 200 R 40 40 0 0 I -X P9 10 -700 0 200 R 40 40 0 0 B -X P10 11 -700 -100 200 R 40 40 0 0 B -X P11 12 -700 -200 200 R 40 40 0 0 B -X P12 13 -700 -300 200 R 40 40 0 0 B -X P13 14 -700 -400 200 R 40 40 0 0 B -X P14 15 -700 -500 200 R 40 40 0 0 B -X P15 16 -700 -600 200 R 40 40 0 0 B -X P16 17 -700 -700 200 R 40 40 0 0 B -X P17 18 -700 -800 200 R 40 40 0 0 B -X P18 19 700 500 200 L 40 40 0 0 B -X GND 2 700 -1100 200 L 40 40 0 0 W -X P19 20 700 400 200 L 40 40 0 0 B -X P20 21 700 300 200 L 40 40 0 0 B -X P21 22 700 200 200 L 40 40 0 0 B -X P22 23 700 100 200 L 40 40 0 0 B -X P23 24 700 0 200 L 40 40 0 0 B -X P24 25 700 -100 200 L 40 40 0 0 B -X P25 26 700 -200 200 L 40 40 0 0 B -X P26 27 700 -300 200 L 40 40 0 0 B -X P27 28 700 -400 200 L 40 40 0 0 B -X P28 29 700 -500 200 L 40 40 0 0 B -X GND 3 700 -1000 200 L 40 40 0 0 W -X P29 30 700 -600 200 L 40 40 0 0 B -X P30 31 700 -700 200 L 40 40 0 0 B -X P31 32 700 -800 200 L 40 40 0 0 B -X SCLK 33 700 900 200 L 40 40 0 0 I C -X DIN 34 700 800 200 L 40 40 0 0 I -X CS 35 700 1000 200 L 40 40 0 0 I -X V+ 36 700 1200 200 L 40 40 0 0 W -X DOUT 4 700 700 200 L 40 40 0 0 O -X P4 5 -700 500 200 R 40 40 0 0 B -X P5 6 -700 400 200 R 40 40 0 0 B -X P6 7 -700 300 200 R 40 40 0 0 B -X P7 8 -700 200 200 R 40 40 0 0 B -X P8 9 -700 100 200 R 40 40 0 0 B -ENDDRAW -ENDDEF -# -#End Library +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# MAX7301AAX+ +# +DEF MAX7301AAX+ U 0 40 Y Y 1 L N +F0 "U" -500 1339 50 H V L BNN +F1 "MAX7301AAX+" -500 -1457 50 H V L BNN +F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN +F3 "Maxim Integrated" 0 0 50 H I L BNN +F4 "None" 0 0 50 H I L BNN +F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN +F6 "SSOP-36 Maxim" 0 0 50 H I L BNN +F7 "Unavailable" 0 0 50 H I L BNN +F8 "MAX7301AAX+" 0 0 50 H I L BNN +DRAW +P 2 0 0 16 -500 -1300 -500 1300 N +P 2 0 0 16 -500 1300 500 1300 N +P 2 0 0 16 500 -1300 -500 -1300 N +P 2 0 0 16 500 1300 500 -1300 N +X ISET 1 -700 1000 200 R 40 40 0 0 I +X P9 10 -700 0 200 R 40 40 0 0 B +X P10 11 -700 -100 200 R 40 40 0 0 B +X P11 12 -700 -200 200 R 40 40 0 0 B +X P12 13 -700 -300 200 R 40 40 0 0 B +X P13 14 -700 -400 200 R 40 40 0 0 B +X P14 15 -700 -500 200 R 40 40 0 0 B +X P15 16 -700 -600 200 R 40 40 0 0 B +X P16 17 -700 -700 200 R 40 40 0 0 B +X P17 18 -700 -800 200 R 40 40 0 0 B +X P18 19 700 500 200 L 40 40 0 0 B +X GND 2 700 -1100 200 L 40 40 0 0 W +X P19 20 700 400 200 L 40 40 0 0 B +X P20 21 700 300 200 L 40 40 0 0 B +X P21 22 700 200 200 L 40 40 0 0 B +X P22 23 700 100 200 L 40 40 0 0 B +X P23 24 700 0 200 L 40 40 0 0 B +X P24 25 700 -100 200 L 40 40 0 0 B +X P25 26 700 -200 200 L 40 40 0 0 B +X P26 27 700 -300 200 L 40 40 0 0 B +X P27 28 700 -400 200 L 40 40 0 0 B +X P28 29 700 -500 200 L 40 40 0 0 B +X GND 3 700 -1000 200 L 40 40 0 0 W +X P29 30 700 -600 200 L 40 40 0 0 B +X P30 31 700 -700 200 L 40 40 0 0 B +X P31 32 700 -800 200 L 40 40 0 0 B +X SCLK 33 700 900 200 L 40 40 0 0 I C +X DIN 34 700 800 200 L 40 40 0 0 I +X CS 35 700 1000 200 L 40 40 0 0 I +X V+ 36 700 1200 200 L 40 40 0 0 W +X DOUT 4 700 700 200 L 40 40 0 0 O +X P4 5 -700 500 200 R 40 40 0 0 B +X P5 6 -700 400 200 R 40 40 0 0 B +X P6 7 -700 300 200 R 40 40 0 0 B +X P7 8 -700 200 200 R 40 40 0 0 B +X P8 9 -700 100 200 R 40 40 0 0 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.dcm b/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.dcm index 5f3ed79..5dd71cb 100644 --- a/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.dcm +++ b/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.dcm @@ -1,3 +1,3 @@ -EESchema-DOCLIB Version 2.0 -# -#End Doc Library +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.lib b/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.lib index b466ded..524e543 100644 --- a/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.lib +++ b/electrical/same54_dev_board/libraries/TPS73733QDRBRQ1.lib @@ -1,15 +1,15 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# TPS73733QDRBRQ1 -# -DEF TPS73733QDRBRQ1 U 0 40 Y Y 1 F N -F0 "U" 0 -400 50 H V C CNN -F1 "TPS73733QDRBRQ1" 0 450 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -ENDDRAW -ENDDEF -# -#End Library +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# TPS73733QDRBRQ1 +# +DEF TPS73733QDRBRQ1 U 0 40 Y Y 1 F N +F0 "U" 0 -400 50 H V C CNN +F1 "TPS73733QDRBRQ1" 0 450 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +ENDDRAW +ENDDEF +# +#End Library diff --git a/electrical/same54_dev_board/modules/proj_modules.pretty/SOP80P1030X264-36N.kicad_mod b/electrical/same54_dev_board/modules/proj_modules.pretty/SOP80P1030X264-36N.kicad_mod index 4262db3..f25d8be 100644 --- a/electrical/same54_dev_board/modules/proj_modules.pretty/SOP80P1030X264-36N.kicad_mod +++ b/electrical/same54_dev_board/modules/proj_modules.pretty/SOP80P1030X264-36N.kicad_mod @@ -1,58 +1,58 @@ - -(module SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418) - (descr "") - (fp_text reference REF** (at -2.415 -8.587 0) (layer F.SilkS) - (effects (font (size 1.0 1.0) (thickness 0.015))) - ) - (fp_text value SOP80P1030X264-36N (at 5.84 8.587 0) (layer F.Fab) - (effects (font (size 1.0 1.0) (thickness 0.015))) - ) - (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2)) - (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2)) - (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 2 smd rect (at -4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 7 smd rect (at -4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 12 smd rect (at -4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 17 smd rect (at -4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 20 smd rect (at 4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 25 smd rect (at 4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 30 smd rect (at 4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 35 smd rect (at 4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) - (pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + +(module SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418) + (descr "") + (fp_text reference REF** (at -2.415 -8.587 0) (layer F.SilkS) + (effects (font (size 1.0 1.0) (thickness 0.015))) + ) + (fp_text value SOP80P1030X264-36N (at 5.84 8.587 0) (layer F.Fab) + (effects (font (size 1.0 1.0) (thickness 0.015))) + ) + (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2)) + (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2)) + (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 2 smd rect (at -4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 7 smd rect (at -4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 12 smd rect (at -4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 17 smd rect (at -4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 20 smd rect (at 4.72 6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 25 smd rect (at 4.72 2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 30 smd rect (at 4.72 -2.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 35 smd rect (at 4.72 -6.0) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) + (pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Mask F.Paste)) ) \ No newline at end of file diff --git a/electrical/same54_dev_board/same54_dev_board-cache.lib b/electrical/same54_dev_board/same54_dev_board-cache.lib index e22c375..e7a54f7 100644 --- a/electrical/same54_dev_board/same54_dev_board-cache.lib +++ b/electrical/same54_dev_board/same54_dev_board-cache.lib @@ -1,671 +1,671 @@ -EESchema-LIBRARY Version 2.4 -#encoding utf-8 -# -# Conn_02x20_LCD_INTF_Conn_02x20_Odd_Even_LCD_INTF -# -DEF Conn_02x20_LCD_INTF_Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N -F0 "J" 0 -1100 50 H V C CNN -F1 "Conn_02x20_LCD_INTF_Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN -F2 "" -400 0 50 H I C CNN -F3 "" -400 0 50 H I C CNN -$FPLIST - Connector*:*_2x??-1MP* -$ENDFPLIST -DRAW -S -450 -995 -400 -1005 1 1 6 N -S -450 -895 -400 -905 1 1 6 N -S -450 -795 -400 -805 1 1 6 N -S -450 -695 -400 -705 1 1 6 N -S -450 -595 -400 -605 1 1 6 N -S -450 -495 -400 -505 1 1 6 N -S -450 -395 -400 -405 1 1 6 N -S -450 -295 -400 -305 1 1 6 N -S -450 -195 -400 -205 1 1 6 N -S -450 -95 -400 -105 1 1 6 N -S -450 5 -400 -5 1 1 6 N -S -450 105 -400 95 1 1 6 N -S -450 205 -400 195 1 1 6 N -S -450 305 -400 295 1 1 6 N -S -450 405 -400 395 1 1 6 N -S -450 505 -400 495 1 1 6 N -S -450 605 -400 595 1 1 6 N -S -450 705 -400 695 1 1 6 N -S -450 805 -400 795 1 1 6 N -S -450 905 -400 895 1 1 6 N -S -450 950 450 -1050 1 1 10 f -S 450 -995 400 -1005 1 1 6 N -S 450 -895 400 -905 1 1 6 N -S 450 -795 400 -805 1 1 6 N -S 450 -695 400 -705 1 1 6 N -S 450 -595 400 -605 1 1 6 N -S 450 -495 400 -505 1 1 6 N -S 450 -395 400 -405 1 1 6 N -S 450 -295 400 -305 1 1 6 N -S 450 -195 400 -205 1 1 6 N -S 450 -95 400 -105 1 1 6 N -S 450 5 400 -5 1 1 6 N -S 450 105 400 95 1 1 6 N -S 450 205 400 195 1 1 6 N -S 450 305 400 295 1 1 6 N -S 450 405 400 395 1 1 6 N -S 450 505 400 495 1 1 6 N -S 450 605 400 595 1 1 6 N -S 450 705 400 695 1 1 6 N -S 450 805 400 795 1 1 6 N -S 450 905 400 895 1 1 6 N -X VCC 1 -600 900 150 R 50 50 1 1 W -X ~TFT_WR 10 600 500 150 L 50 50 1 1 P -X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P -X TFT_TE 12 600 400 150 L 50 50 1 1 I -X TFT_D0 13 -600 300 150 R 50 50 1 1 P -X TFT_D1 14 600 300 150 L 50 50 1 1 P -X TFT_D2 15 -600 200 150 R 50 50 1 1 P -X TFT_D3 16 600 200 150 L 50 50 1 1 P -X TFT_D4 17 -600 100 150 R 50 50 1 1 P -X TFT_D5 18 600 100 150 L 50 50 1 1 P -X TFT_D6 19 -600 0 150 R 50 50 1 1 P -X GND 2 600 900 150 L 50 50 1 1 P -X TFT_D7 20 600 0 150 L 50 50 1 1 P -X TFT_D8 21 -600 -100 150 R 50 50 1 1 P -X TFT_D9 22 600 -100 150 L 50 50 1 1 P -X TFT_D10 23 -600 -200 150 R 50 50 1 1 P -X TFT_D11 24 600 -200 150 L 50 50 1 1 P -X TFT_D12 25 -600 -300 150 R 50 50 1 1 P -X TFT_D13 26 600 -300 150 L 50 50 1 1 P -X TFT_D14 27 -600 -400 150 R 50 50 1 1 P -X TFT_D15 28 600 -400 150 L 50 50 1 1 P -X TFT_D16 29 -600 -500 150 R 50 50 1 1 P -X CPT_SCL 3 -600 800 150 R 50 50 1 1 P -X TFT_D17 30 600 -500 150 L 50 50 1 1 P -X TFT_D18 31 -600 -600 150 R 50 50 1 1 P -X TFT_D19 32 600 -600 150 L 50 50 1 1 P -X TFT_D20 33 -600 -700 150 R 50 50 1 1 P -X TFT_D21 34 600 -700 150 L 50 50 1 1 P -X TFT_D22 35 -600 -800 150 R 50 50 1 1 P -X TFT_D23 36 600 -800 150 L 50 50 1 1 P -X TFT_STB 37 -600 -900 150 R 50 50 1 1 P -X NC 38 600 -900 150 L 50 50 1 1 N -X Pin_39 39 -600 -1000 150 R 50 50 1 1 P -X CPT_SDA 4 600 800 150 L 50 50 1 1 P -X NC 40 600 -1000 150 L 50 50 1 1 N -X CPT_INT 5 -600 700 150 R 50 50 1 1 P -X TFT_GPO 6 600 700 150 L 50 50 1 1 O -X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P -X TFT_D/C 8 600 600 150 L 50 50 1 1 P -X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Connector_Barrel_Jack_Switch -# -DEF Connector_Barrel_Jack_Switch J 0 20 Y N 1 F N -F0 "J" 0 210 50 H V C CNN -F1 "Connector_Barrel_Jack_Switch" 0 -200 50 H V C CNN -F2 "" 50 -40 50 H I C CNN -F3 "" 50 -40 50 H I C CNN -$FPLIST - BarrelJack* -$ENDFPLIST -DRAW -A -130 100 25 901 -901 0 1 10 F -130 125 -130 75 -A -130 100 25 901 -901 0 1 10 N -130 125 -130 75 -S -200 150 200 -150 0 1 10 f -S 145 125 -130 75 0 1 10 F -P 2 0 1 10 50 -90 75 -65 N -P 2 0 1 10 200 100 150 100 N -P 4 0 1 10 200 0 50 0 50 -90 25 -65 N -P 6 0 1 10 -150 -100 -100 -100 -50 -50 0 -100 100 -100 200 -100 N -X ~ 1 300 100 100 L 50 50 1 1 P -X ~ 2 300 -100 100 L 50 50 1 1 P -X ~ 3 300 0 100 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Connector_Conn_ARM_JTAG_SWD_10 -# -DEF Connector_Conn_ARM_JTAG_SWD_10 J 0 40 Y Y 1 F N -F0 "J" -100 650 50 H V R CNN -F1 "Connector_Conn_ARM_JTAG_SWD_10" -100 550 50 H V R BNN -F2 "" 0 0 50 H I C CNN -F3 "" -350 -1250 50 V I C CNN -$FPLIST - PinHeader?2x05?P1.27mm* -$ENDFPLIST -DRAW -S -400 500 400 -500 0 1 10 f -S -110 -500 -90 -460 0 1 0 N -S -10 -500 10 -460 0 1 0 N -S -10 500 10 460 0 1 0 N -S 360 90 400 110 0 1 0 N -S 400 -110 360 -90 0 1 0 N -S 400 -10 360 10 0 1 0 N -S 400 310 360 290 0 1 0 N -S 360 -210 400 -190 1 1 0 N -X VTref 1 0 600 100 D 50 50 1 1 W -X ~RESET~ 10 500 300 100 L 50 50 1 1 C -X SWDIO/TMS 2 500 0 100 L 50 50 1 1 B -X GND 3 0 -600 100 U 50 50 1 1 W -X SWDCLK/TCK 4 500 100 100 L 50 50 1 1 O -X GND 5 0 -600 100 U 50 50 1 1 P N -X SWO/TDO 6 500 -100 100 L 50 50 1 1 I -X KEY 7 -400 0 100 R 50 50 1 1 N N -X NC/TDI 8 500 -200 100 L 50 50 1 1 O -X GNDDetect 9 -100 -600 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Connector_USB_B_Micro -# -DEF Connector_USB_B_Micro J 0 40 Y Y 1 F N -F0 "J" -200 450 50 H V L CNN -F1 "Connector_USB_B_Micro" -200 350 50 H V L CNN -F2 "" 150 -50 50 H I C CNN -F3 "" 150 -50 50 H I C CNN -ALIAS USB_B_Mini -$FPLIST - USB* -$ENDFPLIST -DRAW -C -150 85 25 0 1 10 F -C -25 135 15 0 1 10 F -S -200 -300 200 300 0 1 10 f -S -5 -300 5 -270 0 1 0 N -S 10 50 -20 20 0 1 10 F -S 200 -205 170 -195 0 1 0 N -S 200 -105 170 -95 0 1 0 N -S 200 -5 170 5 0 1 0 N -S 200 195 170 205 0 1 0 N -P 2 0 1 10 -75 85 25 85 N -P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N -P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N -P 4 0 1 10 25 110 25 60 75 85 25 110 F -P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F -P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N -X VBUS 1 300 200 100 L 50 50 1 1 w -X D- 2 300 -100 100 L 50 50 1 1 P -X D+ 3 300 0 100 L 50 50 1 1 P -X ID 4 300 -200 100 L 50 50 1 1 P -X GND 5 0 -400 100 U 50 50 1 1 w -X Shield 6 -100 -400 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_C_Small -# -DEF Device_C_Small C 0 10 N N 1 F N -F0 "C" 10 70 50 H V L CNN -F1 "Device_C_Small" 10 -80 50 H V L CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - C_* -$ENDFPLIST -DRAW -P 2 0 1 13 -60 -20 60 -20 N -P 2 0 1 12 -60 20 60 20 N -X ~ 1 0 100 80 D 50 50 1 1 P -X ~ 2 0 -100 80 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Crystal -# -DEF Device_Crystal Y 0 40 N N 1 F N -F0 "Y" 0 150 50 H V C CNN -F1 "Device_Crystal" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Crystal* -$ENDFPLIST -DRAW -S -45 100 45 -100 0 1 12 N -P 2 0 1 0 -100 0 -75 0 N -P 2 0 1 20 -75 -50 -75 50 N -P 2 0 1 20 75 -50 75 50 N -P 2 0 1 0 100 0 75 0 N -X 1 1 -150 0 50 R 50 50 1 1 P -X 2 2 150 0 50 L 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Crystal_GND24 -# -DEF Device_Crystal_GND24 Y 0 40 Y N 1 F N -F0 "Y" 125 200 50 H V L CNN -F1 "Device_Crystal_GND24" 125 125 50 H V L CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Crystal* -$ENDFPLIST -DRAW -S -45 100 45 -100 0 1 12 N -P 2 0 1 0 -100 0 -80 0 N -P 2 0 1 20 -80 -50 -80 50 N -P 2 0 1 0 0 -150 0 -140 N -P 2 0 1 0 0 140 0 150 N -P 2 0 1 20 80 -50 80 50 N -P 2 0 1 0 80 0 100 0 N -P 4 0 1 0 -100 -90 -100 -140 100 -140 100 -90 N -P 4 0 1 0 -100 90 -100 140 100 140 100 90 N -X 1 1 -150 0 50 R 50 50 1 1 P -X 2 2 0 200 50 D 50 50 1 1 P -X 3 3 150 0 50 L 50 50 1 1 P -X 4 4 0 -200 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_Ferrite_Bead_Small -# -DEF Device_Ferrite_Bead_Small FB 0 0 N Y 1 F N -F0 "FB" 75 50 50 H V L CNN -F1 "Device_Ferrite_Bead_Small" 75 -50 50 H V L CNN -F2 "" -70 0 50 V I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - Inductor_* - L_* - *Ferrite* -$ENDFPLIST -DRAW -P 2 0 1 0 0 -50 0 -31 N -P 2 0 1 0 0 35 0 51 N -P 5 0 1 0 -72 11 -44 59 72 -8 44 -56 -72 11 N -X ~ 1 0 100 50 D 50 50 1 1 P -X ~ 2 0 -100 50 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# Device_R_Small -# -DEF Device_R_Small R 0 10 N N 1 F N -F0 "R" 30 20 50 H V L CNN -F1 "Device_R_Small" 30 -40 50 H V L CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -$FPLIST - R_* -$ENDFPLIST -DRAW -S -30 70 30 -70 0 1 8 N -X ~ 1 0 100 30 D 50 50 1 1 P -X ~ 2 0 -100 30 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# MAX7301AAX__MAX7301AAX+ -# -DEF MAX7301AAX__MAX7301AAX+ U 0 40 Y Y 1 L N -F0 "U" -500 1339 50 H V L BNN -F1 "MAX7301AAX__MAX7301AAX+" -500 -1457 50 H V L BNN -F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN -F3 "Maxim Integrated" 0 0 50 H I L BNN -F4 "None" 0 0 50 H I L BNN -F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN -F6 "SSOP-36 Maxim" 0 0 50 H I L BNN -F7 "Unavailable" 0 0 50 H I L BNN -F8 "MAX7301AAX+" 0 0 50 H I L BNN -DRAW -P 2 0 0 16 -500 -1300 -500 1300 N -P 2 0 0 16 -500 1300 500 1300 N -P 2 0 0 16 500 -1300 -500 -1300 N -P 2 0 0 16 500 1300 500 -1300 N -X ISET 1 -700 1000 200 R 40 40 0 0 I -X P9 10 -700 0 200 R 40 40 0 0 B -X P10 11 -700 -100 200 R 40 40 0 0 B -X P11 12 -700 -200 200 R 40 40 0 0 B -X P12 13 -700 -300 200 R 40 40 0 0 B -X P13 14 -700 -400 200 R 40 40 0 0 B -X P14 15 -700 -500 200 R 40 40 0 0 B -X P15 16 -700 -600 200 R 40 40 0 0 B -X P16 17 -700 -700 200 R 40 40 0 0 B -X P17 18 -700 -800 200 R 40 40 0 0 B -X P18 19 700 500 200 L 40 40 0 0 B -X GND 2 700 -1100 200 L 40 40 0 0 W -X P19 20 700 400 200 L 40 40 0 0 B -X P20 21 700 300 200 L 40 40 0 0 B -X P21 22 700 200 200 L 40 40 0 0 B -X P22 23 700 100 200 L 40 40 0 0 B -X P23 24 700 0 200 L 40 40 0 0 B -X P24 25 700 -100 200 L 40 40 0 0 B -X P25 26 700 -200 200 L 40 40 0 0 B -X P26 27 700 -300 200 L 40 40 0 0 B -X P27 28 700 -400 200 L 40 40 0 0 B -X P28 29 700 -500 200 L 40 40 0 0 B -X GND 3 700 -1000 200 L 40 40 0 0 W -X P29 30 700 -600 200 L 40 40 0 0 B -X P30 31 700 -700 200 L 40 40 0 0 B -X P31 32 700 -800 200 L 40 40 0 0 B -X SCLK 33 700 900 200 L 40 40 0 0 I C -X DIN 34 700 800 200 L 40 40 0 0 I -X CS 35 700 1000 200 L 40 40 0 0 I -X V+ 36 700 1200 200 L 40 40 0 0 W -X DOUT 4 700 700 200 L 40 40 0 0 O -X P4 5 -700 500 200 R 40 40 0 0 B -X P5 6 -700 400 200 R 40 40 0 0 B -X P6 7 -700 300 200 R 40 40 0 0 B -X P7 8 -700 200 200 R 40 40 0 0 B -X P8 9 -700 100 200 R 40 40 0 0 B -ENDDRAW -ENDDEF -# -# dk_Interface-Controllers_FT232RQ-REEL -# -DEF dk_Interface-Controllers_FT232RQ-REEL U 0 40 Y Y 1 F N -F0 "U" -600 50 60 H V L CNN -F1 "dk_Interface-Controllers_FT232RQ-REEL" -200 -1300 60 V V L CNN -F2 "digikey-footprints:QFN-32-1EP_5x5mm" 200 200 60 H I L CNN -F3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" 200 300 60 H I L CNN -F4 "768-1008-1-ND" 200 400 60 H I L CNN "Digi-Key_PN" -F5 "FT232RQ-REEL" 200 500 60 H I L CNN "MPN" -F6 "Integrated Circuits (ICs)" 200 600 60 H I L CNN "Category" -F7 "Interface - Controllers" 200 700 60 H I L CNN "Family" -F8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" 200 800 60 H I L CNN "DK_Datasheet_Link" -F9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" 200 900 60 H I L CNN "DK_Detail_Page" -F10 "IC USB FS SERIAL UART 32-QFN" 200 1000 60 H I L CNN "Description" -F11 "FTDI, Future Technology Devices International Ltd" 200 1100 60 H I L CNN "Manufacturer" -F12 "Active" 200 1200 60 H I L CNN "Status" -DRAW -S -600 0 200 -1600 0 1 0 f -X VCCIO 1 -200 100 100 D 50 50 1 1 W -X CBUS2 10 -700 -700 100 R 50 50 1 1 B -X CBUS3 11 -700 -800 100 R 50 50 1 1 B -X NC 12 200 -900 100 L 50 50 1 1 N N -X NC 13 200 -1000 100 L 50 50 1 1 N N -X USBDP 14 -700 -900 100 R 50 50 1 1 B -X USBDM 15 -700 -1000 100 R 50 50 1 1 B -X 3V3OUT 16 300 -300 100 L 50 50 1 1 O -X GND 17 -200 -1700 100 U 50 50 1 1 W -X RESET# 18 -700 -1100 100 R 50 50 1 1 I -X VCC 19 -100 100 100 D 50 50 1 1 W -X RXD 2 -700 -100 100 R 50 50 1 1 I -X GND 20 -100 -1700 100 U 50 50 1 1 W -X CBUS1 21 -700 -1200 100 R 50 50 1 1 B -X CBUS0 22 -700 -1300 100 R 50 50 1 1 B -X NC 23 200 -1100 100 L 50 50 1 1 N N -X AGND 24 0 -1700 100 U 50 50 1 1 W -X NC 25 200 -1200 100 L 50 50 1 1 N N -X TEST 26 -700 -1400 100 R 50 50 1 1 I -X OSCI 27 -700 -1500 100 R 50 50 1 1 I -X OSCO 28 300 -400 100 L 50 50 1 1 O -X NC 29 200 -1300 100 L 50 50 1 1 N N -X RI# 3 -700 -200 100 R 50 50 1 1 I -X TXD 30 300 -500 100 L 50 50 1 1 O -X DTR# 31 300 -600 100 L 50 50 1 1 O -X RTS# 32 300 -700 100 L 50 50 1 1 O -X EP 33 100 -1700 100 U 50 50 1 1 U -X GND 4 -300 -1700 100 U 50 50 1 1 W -X NC 5 200 -800 100 L 50 50 1 1 N N -X DSR# 6 -700 -300 100 R 50 50 1 1 I -X DCD# 7 -700 -400 100 R 50 50 1 1 I -X CTS# 8 -700 -500 100 R 50 50 1 1 I -X CBUS4 9 -700 -600 100 R 50 50 1 1 B -ENDDRAW -ENDDEF -# -# dk_Transistors-FETs-MOSFETs-Single_IRLML6402TRPBF -# -DEF dk_Transistors-FETs-MOSFETs-Single_IRLML6402TRPBF Q 0 0 Y Y 1 F N -F0 "Q" -106 143 60 H V R CNN -F1 "dk_Transistors-FETs-MOSFETs-Single_IRLML6402TRPBF" 136 0 60 V V C CNN -F2 "digikey-footprints:SOT-23-3" 200 200 60 H I L CNN -F3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" 200 300 60 H I L CNN -F4 "IRLML6402PBFCT-ND" 200 400 60 H I L CNN "Digi-Key_PN" -F5 "IRLML6402TRPBF" 200 500 60 H I L CNN "MPN" -F6 "Discrete Semiconductor Products" 200 600 60 H I L CNN "Category" -F7 "Transistors - FETs, MOSFETs - Single" 200 700 60 H I L CNN "Family" -F8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" 200 800 60 H I L CNN "DK_Datasheet_Link" -F9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" 200 900 60 H I L CNN "DK_Detail_Page" -F10 "MOSFET P-CH 20V 3.7A SOT-23" 200 1000 60 H I L CNN "Description" -F11 "Infineon Technologies" 200 1100 60 H I L CNN "Manufacturer" -F12 "Active" 200 1200 60 H I L CNN "Status" -DRAW -C -50 0 130 0 1 0 f -C 0 -75 5 0 1 0 N -C 0 -55 5 0 1 0 N -C 0 75 5 0 1 0 N -P 2 0 1 0 0 -55 -100 -55 N -P 3 0 1 0 -200 -100 -120 -100 -120 55 N -P 3 0 1 0 0 -100 0 0 -100 0 N -P 3 0 1 0 0 100 0 55 -100 55 N -P 5 0 1 0 -5 -75 40 -75 40 55 40 75 -5 75 N -P 2 1 1 0 -100 -55 -100 -75 N -P 2 1 1 0 -100 -55 -100 -35 N -P 2 1 1 0 -100 0 -100 -20 N -P 2 1 1 0 -100 0 -100 20 N -P 2 1 1 0 -100 75 -100 35 N -P 2 1 1 0 60 -8 20 -8 N -P 4 1 1 0 -15 0 -45 20 -45 -20 -15 0 F -P 4 1 1 0 40 -10 60 20 20 20 40 -10 F -X G 1 -300 -100 100 R 50 50 1 1 B -X S 2 0 -200 100 U 50 50 1 1 B -X D 3 0 200 100 D 50 50 1 1 B -ENDDRAW -ENDDEF -# -# p_ATSAME54P20A-AU_p_ATSAME54P20A-AU -# -DEF p_ATSAME54P20A-AU_p_ATSAME54P20A-AU U 0 40 Y Y 5 L N -F0 "U" 0 -2600 50 H V C CNN -F1 "p_ATSAME54P20A-AU_p_ATSAME54P20A-AU" 0 1050 50 H V C CNN -F2 "" -1200 1250 50 H I C CNN -F3 "" -1200 1250 50 H I C CNN -DRAW -T 0 0 950 50 0 1 0 "Port A" Normal 0 C C -T 0 0 800 50 0 2 0 "Port B" Normal 0 C C -T 0 0 750 50 0 3 0 "Port C" Normal 0 C C -T 0 0 850 50 0 4 0 "Port D" Normal 0 C C -T 0 50 650 50 0 5 0 "Power Bus" Normal 0 C C -S -450 1000 400 -2150 1 1 0 f -S -500 900 500 -2550 2 1 0 f -S -450 850 450 -2250 3 1 0 f -S -400 900 400 -150 4 1 0 f -S -800 750 800 -1450 5 1 0 f -X XIN32/PA00 1 600 750 200 L 50 50 1 1 B -X PA03 10 600 450 200 L 50 50 1 1 B -X PA27 113 600 -1850 200 L 50 50 1 1 B -X SWCLK/PA30 119 600 -1950 200 L 50 50 1 1 B -X SWDIO/PA31 120 600 -2050 200 L 50 50 1 1 B -X XOUT32/PA01 2 600 650 200 L 50 50 1 1 B -X PA04 21 600 350 200 L 50 50 1 1 B -X PA05 22 600 250 200 L 50 50 1 1 B -X PA06 23 600 150 200 L 50 50 1 1 B -X PA07 24 600 50 200 L 50 50 1 1 B -X PA08 33 600 -50 200 L 50 50 1 1 B -X PA09 34 600 -150 200 L 50 50 1 1 B -X PA10 35 600 -250 200 L 50 50 1 1 B -X PA11 36 600 -350 200 L 50 50 1 1 B -X PA12 60 600 -450 200 L 50 50 1 1 B -X PA13 61 600 -550 200 L 50 50 1 1 B -X XIN0/PA14 62 600 -650 200 L 50 50 1 1 B -X XOUT0/PA15 63 600 -750 200 L 50 50 1 1 B -X PA16 66 600 -850 200 L 50 50 1 1 B -X PA17 67 600 -950 200 L 50 50 1 1 B -X PA18 68 600 -1050 200 L 50 50 1 1 B -X PA19 69 600 -1150 200 L 50 50 1 1 B -X PA20 88 600 -1250 200 L 50 50 1 1 B -X PA21 89 600 -1350 200 L 50 50 1 1 B -X PA02 9 600 550 200 L 50 50 1 1 B -X PA22 92 600 -1450 200 L 50 50 1 1 B -X PA23 93 600 -1550 200 L 50 50 1 1 B -X PA24 94 600 -1650 200 L 50 50 1 1 B -X PA25 95 600 -1750 200 L 50 50 1 1 B -X PB24 100 700 -1750 197 L 50 50 2 1 B -X PB25 101 700 -1850 197 L 50 50 2 1 B -X PB26 102 700 -1950 197 L 50 50 2 1 B -X PB27 103 700 -2050 197 L 50 50 2 1 B -X PB28 104 700 -2150 197 L 50 50 2 1 B -X PB29 105 700 -2250 197 L 50 50 2 1 B -X PB04 11 700 250 197 L 50 50 2 1 B -X PB05 12 700 150 197 L 50 50 2 1 B -X SWO/PB30 121 700 -2350 197 L 50 50 2 1 B -X PB31 122 700 -2450 197 L 50 50 2 1 B -X PB00 125 700 650 197 L 50 50 2 1 B -X PB01 126 700 550 197 L 50 50 2 1 B -X PB02 127 700 450 197 L 50 50 2 1 B -X PB03 128 700 350 197 L 50 50 2 1 B -X PB06 17 700 50 197 L 50 50 2 1 B -X PB07 18 700 -50 197 L 50 50 2 1 B -X PB08 19 700 -150 197 L 50 50 2 1 B -X PB09 20 700 -250 197 L 50 50 2 1 B -X PB10 39 700 -350 197 L 50 50 2 1 B -X PB11 40 700 -450 197 L 50 50 2 1 B -X PB12 41 700 -550 197 L 50 50 2 1 B -X PB13 42 700 -650 197 L 50 50 2 1 B -X PB14 43 700 -750 197 L 50 50 2 1 B -X PB15 44 700 -850 197 L 50 50 2 1 B -X PB16 82 700 -950 197 L 50 50 2 1 B -X PB17 83 700 -1050 197 L 50 50 2 1 B -X PB18 84 700 -1150 197 L 50 50 2 1 B -X PB19 85 700 -1250 197 L 50 50 2 1 B -X PB20 86 700 -1350 197 L 50 50 2 1 B -X PB21 87 700 -1450 197 L 50 50 2 1 B -X XIN1/PB22 98 700 -1550 197 L 50 50 2 1 B -X XOUT1/PB23 99 700 -1650 197 L 50 50 2 1 B -X PC24 108 650 -1550 197 L 50 50 3 1 B -X PC25 109 650 -1650 197 L 50 50 3 1 B -X PC26 110 650 -1750 197 L 50 50 3 1 B -X PC27 111 650 -1850 197 L 50 50 3 1 B -X PC28 112 650 -1950 197 L 50 50 3 1 B -X PC30 123 650 -2050 197 L 50 50 3 1 B -X PC31 124 650 -2150 197 L 50 50 3 1 B -X PC04 27 650 250 197 L 50 50 3 1 B -X PC05 28 650 150 197 L 50 50 3 1 B -X PC06 29 650 50 197 L 50 50 3 1 B -X PC00 3 650 650 197 L 50 50 3 1 B -X PC07 30 650 -50 197 L 50 50 3 1 B -X PC01 4 650 550 197 L 50 50 3 1 B -X PC10 52 650 -150 197 L 50 50 3 1 B -X PC11 55 650 -250 197 L 50 50 3 1 B -X PC12 56 650 -350 197 L 50 50 3 1 B -X PC13 57 650 -450 197 L 50 50 3 1 B -X PC14 58 650 -550 197 L 50 50 3 1 B -X PC15 59 650 -650 197 L 50 50 3 1 B -X PC02 7 650 450 197 L 50 50 3 1 B -X PC16 70 650 -750 197 L 50 50 3 1 B -X PC17 71 650 -850 197 L 50 50 3 1 B -X PC18 72 650 -950 197 L 50 50 3 1 B -X PC19 73 650 -1050 197 L 50 50 3 1 B -X PC20 74 650 -1150 197 L 50 50 3 1 B -X PC21 75 650 -1250 197 L 50 50 3 1 B -X PC22 76 650 -1350 197 L 50 50 3 1 B -X PC23 77 650 -1450 197 L 50 50 3 1 B -X PC03 8 650 350 197 L 50 50 3 1 B -X PD00 13 600 750 197 L 50 50 4 1 B -X PD01 16 600 650 197 L 50 50 4 1 B -X PD08 47 600 550 197 L 50 50 4 1 B -X PD09 48 600 450 197 L 50 50 4 1 B -X PD10 49 600 350 197 L 50 50 4 1 B -X PD11 50 600 250 197 L 50 50 4 1 B -X PD12 51 600 150 197 L 50 50 4 1 B -X PD20 80 600 50 197 L 50 50 4 1 B -X PD21 81 600 -50 197 L 50 50 4 1 B -X VDDIO7 107 -1000 -900 197 R 50 50 5 1 W -X ~RESET 114 -1000 650 197 R 50 50 5 1 B -X VDDCORE 115 -1000 -1150 197 R 50 50 5 1 W -X GNDIO 116 1000 -850 197 L 50 50 5 1 W -X VSW 117 -1000 -1300 197 R 50 50 5 1 W -X VDDIO8 118 -1000 -1000 197 R 50 50 5 1 W -X GNDANA1 14 1000 -500 197 L 50 50 5 1 W -X VDDANA2 15 -1000 300 197 R 50 50 5 1 B -X GNDANA2 25 1000 -600 197 L 50 50 5 1 W -X VDDANA3 26 -1000 200 197 R 50 50 5 1 B -X VDDIOB1 32 -1000 0 197 R 50 50 5 1 B -X VDDIOB2 37 -1000 -100 197 R 50 50 5 1 B -X VDDIO1 46 -1000 -300 197 R 50 50 5 1 W -X GND1 5 1000 650 197 L 50 50 5 1 W -X GND10 5 1000 -250 197 L 50 50 5 1 W -X GND2 5 1000 550 197 L 50 50 5 1 W -X GND3 5 1000 450 197 L 50 50 5 1 W -X GND4 5 1000 350 197 L 50 50 5 1 W -X GND5 5 1000 250 197 L 50 50 5 1 W -X GND6 5 1000 150 197 L 50 50 5 1 W -X GND7 5 1000 50 197 L 50 50 5 1 W -X GND8 5 1000 -50 197 L 50 50 5 1 W -X GND9 5 1000 -150 197 L 50 50 5 1 W -X VDDIO2 54 -1000 -400 197 R 50 50 5 1 W -X VDDANA1 6 -1000 400 197 R 50 50 5 1 B -X VDDIO3 65 -1000 -500 197 R 50 50 5 1 W -X VDDIO4 79 -1000 -600 197 R 50 50 5 1 W -X VDDIO5 91 -1000 -700 197 R 50 50 5 1 W -X VDDIO6 97 -1000 -800 197 R 50 50 5 1 W -ENDDRAW -ENDDEF -# -# power_+3V3 -# -DEF power_+3V3 #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -150 50 H I C CNN -F1 "power_+3V3" 0 140 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -ALIAS +3.3V -DRAW -P 2 0 1 0 -30 50 0 100 N -P 2 0 1 0 0 0 0 100 N -P 2 0 1 0 0 100 30 50 N -X +3V3 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_+5V -# -DEF power_+5V #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -150 50 H I C CNN -F1 "power_+5V" 0 140 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 2 0 1 0 -30 50 0 100 N -P 2 0 1 0 0 0 0 100 N -P 2 0 1 0 0 100 30 50 N -X +5V 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_GND -# -DEF power_GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "power_GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# power_PWR_FLAG -# -DEF power_PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 75 50 H I C CNN -F1 "power_PWR_FLAG" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N -X pwr 1 0 0 0 U 50 50 0 0 w -ENDDRAW -ENDDEF -# -# same54_dev_board-rescue_NCP349MNAETBG-NCP349MNAETBG -# -DEF same54_dev_board-rescue_NCP349MNAETBG-NCP349MNAETBG U 0 40 Y Y 1 F N -F0 "U" 0 -200 50 H V C CNN -F1 "same54_dev_board-rescue_NCP349MNAETBG-NCP349MNAETBG" 0 350 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -S -300 250 300 -150 0 1 0 f -X VIN 1 -400 150 100 R 50 50 1 1 I -X GND 2 -400 50 100 R 50 50 1 1 I -X ~FLAG 3 400 150 100 L 50 50 1 1 I -X ~EN 4 -400 -50 100 R 50 50 1 1 I -X OUT 5 400 50 100 L 50 50 1 1 I -X OUT 6 400 -50 100 L 50 50 1 1 I -ENDDRAW -ENDDEF -# -#End Library +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Conn_02x20_LCD_INTF_Conn_02x20_Odd_Even_LCD_INTF +# +DEF Conn_02x20_LCD_INTF_Conn_02x20_Odd_Even_LCD_INTF J 0 40 Y Y 1 F N +F0 "J" 0 -1100 50 H V C CNN +F1 "Conn_02x20_LCD_INTF_Conn_02x20_Odd_Even_LCD_INTF" -600 1050 50 H V L CNN +F2 "" -400 0 50 H I C CNN +F3 "" -400 0 50 H I C CNN +$FPLIST + Connector*:*_2x??-1MP* +$ENDFPLIST +DRAW +S -450 -995 -400 -1005 1 1 6 N +S -450 -895 -400 -905 1 1 6 N +S -450 -795 -400 -805 1 1 6 N +S -450 -695 -400 -705 1 1 6 N +S -450 -595 -400 -605 1 1 6 N +S -450 -495 -400 -505 1 1 6 N +S -450 -395 -400 -405 1 1 6 N +S -450 -295 -400 -305 1 1 6 N +S -450 -195 -400 -205 1 1 6 N +S -450 -95 -400 -105 1 1 6 N +S -450 5 -400 -5 1 1 6 N +S -450 105 -400 95 1 1 6 N +S -450 205 -400 195 1 1 6 N +S -450 305 -400 295 1 1 6 N +S -450 405 -400 395 1 1 6 N +S -450 505 -400 495 1 1 6 N +S -450 605 -400 595 1 1 6 N +S -450 705 -400 695 1 1 6 N +S -450 805 -400 795 1 1 6 N +S -450 905 -400 895 1 1 6 N +S -450 950 450 -1050 1 1 10 f +S 450 -995 400 -1005 1 1 6 N +S 450 -895 400 -905 1 1 6 N +S 450 -795 400 -805 1 1 6 N +S 450 -695 400 -705 1 1 6 N +S 450 -595 400 -605 1 1 6 N +S 450 -495 400 -505 1 1 6 N +S 450 -395 400 -405 1 1 6 N +S 450 -295 400 -305 1 1 6 N +S 450 -195 400 -205 1 1 6 N +S 450 -95 400 -105 1 1 6 N +S 450 5 400 -5 1 1 6 N +S 450 105 400 95 1 1 6 N +S 450 205 400 195 1 1 6 N +S 450 305 400 295 1 1 6 N +S 450 405 400 395 1 1 6 N +S 450 505 400 495 1 1 6 N +S 450 605 400 595 1 1 6 N +S 450 705 400 695 1 1 6 N +S 450 805 400 795 1 1 6 N +S 450 905 400 895 1 1 6 N +X VCC 1 -600 900 150 R 50 50 1 1 W +X ~TFT_WR 10 600 500 150 L 50 50 1 1 P +X ~TFT_RD 11 -600 400 150 R 50 50 1 1 P +X TFT_TE 12 600 400 150 L 50 50 1 1 I +X TFT_D0 13 -600 300 150 R 50 50 1 1 P +X TFT_D1 14 600 300 150 L 50 50 1 1 P +X TFT_D2 15 -600 200 150 R 50 50 1 1 P +X TFT_D3 16 600 200 150 L 50 50 1 1 P +X TFT_D4 17 -600 100 150 R 50 50 1 1 P +X TFT_D5 18 600 100 150 L 50 50 1 1 P +X TFT_D6 19 -600 0 150 R 50 50 1 1 P +X GND 2 600 900 150 L 50 50 1 1 P +X TFT_D7 20 600 0 150 L 50 50 1 1 P +X TFT_D8 21 -600 -100 150 R 50 50 1 1 P +X TFT_D9 22 600 -100 150 L 50 50 1 1 P +X TFT_D10 23 -600 -200 150 R 50 50 1 1 P +X TFT_D11 24 600 -200 150 L 50 50 1 1 P +X TFT_D12 25 -600 -300 150 R 50 50 1 1 P +X TFT_D13 26 600 -300 150 L 50 50 1 1 P +X TFT_D14 27 -600 -400 150 R 50 50 1 1 P +X TFT_D15 28 600 -400 150 L 50 50 1 1 P +X TFT_D16 29 -600 -500 150 R 50 50 1 1 P +X CPT_SCL 3 -600 800 150 R 50 50 1 1 P +X TFT_D17 30 600 -500 150 L 50 50 1 1 P +X TFT_D18 31 -600 -600 150 R 50 50 1 1 P +X TFT_D19 32 600 -600 150 L 50 50 1 1 P +X TFT_D20 33 -600 -700 150 R 50 50 1 1 P +X TFT_D21 34 600 -700 150 L 50 50 1 1 P +X TFT_D22 35 -600 -800 150 R 50 50 1 1 P +X TFT_D23 36 600 -800 150 L 50 50 1 1 P +X TFT_STB 37 -600 -900 150 R 50 50 1 1 P +X NC 38 600 -900 150 L 50 50 1 1 N +X Pin_39 39 -600 -1000 150 R 50 50 1 1 P +X CPT_SDA 4 600 800 150 L 50 50 1 1 P +X NC 40 600 -1000 150 L 50 50 1 1 N +X CPT_INT 5 -600 700 150 R 50 50 1 1 P +X TFT_GPO 6 600 700 150 L 50 50 1 1 O +X ~TFT_RST 7 -600 600 150 R 50 50 1 1 P +X TFT_D/C 8 600 600 150 L 50 50 1 1 P +X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Connector_Barrel_Jack_Switch +# +DEF Connector_Barrel_Jack_Switch J 0 20 Y N 1 F N +F0 "J" 0 210 50 H V C CNN +F1 "Connector_Barrel_Jack_Switch" 0 -200 50 H V C CNN +F2 "" 50 -40 50 H I C CNN +F3 "" 50 -40 50 H I C CNN +$FPLIST + BarrelJack* +$ENDFPLIST +DRAW +A -130 100 25 901 -901 0 1 10 F -130 125 -130 75 +A -130 100 25 901 -901 0 1 10 N -130 125 -130 75 +S -200 150 200 -150 0 1 10 f +S 145 125 -130 75 0 1 10 F +P 2 0 1 10 50 -90 75 -65 N +P 2 0 1 10 200 100 150 100 N +P 4 0 1 10 200 0 50 0 50 -90 25 -65 N +P 6 0 1 10 -150 -100 -100 -100 -50 -50 0 -100 100 -100 200 -100 N +X ~ 1 300 100 100 L 50 50 1 1 P +X ~ 2 300 -100 100 L 50 50 1 1 P +X ~ 3 300 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Connector_Conn_ARM_JTAG_SWD_10 +# +DEF Connector_Conn_ARM_JTAG_SWD_10 J 0 40 Y Y 1 F N +F0 "J" -100 650 50 H V R CNN +F1 "Connector_Conn_ARM_JTAG_SWD_10" -100 550 50 H V R BNN +F2 "" 0 0 50 H I C CNN +F3 "" -350 -1250 50 V I C CNN +$FPLIST + PinHeader?2x05?P1.27mm* +$ENDFPLIST +DRAW +S -400 500 400 -500 0 1 10 f +S -110 -500 -90 -460 0 1 0 N +S -10 -500 10 -460 0 1 0 N +S -10 500 10 460 0 1 0 N +S 360 90 400 110 0 1 0 N +S 400 -110 360 -90 0 1 0 N +S 400 -10 360 10 0 1 0 N +S 400 310 360 290 0 1 0 N +S 360 -210 400 -190 1 1 0 N +X VTref 1 0 600 100 D 50 50 1 1 W +X ~RESET~ 10 500 300 100 L 50 50 1 1 C +X SWDIO/TMS 2 500 0 100 L 50 50 1 1 B +X GND 3 0 -600 100 U 50 50 1 1 W +X SWDCLK/TCK 4 500 100 100 L 50 50 1 1 O +X GND 5 0 -600 100 U 50 50 1 1 P N +X SWO/TDO 6 500 -100 100 L 50 50 1 1 I +X KEY 7 -400 0 100 R 50 50 1 1 N N +X NC/TDI 8 500 -200 100 L 50 50 1 1 O +X GNDDetect 9 -100 -600 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Connector_USB_B_Micro +# +DEF Connector_USB_B_Micro J 0 40 Y Y 1 F N +F0 "J" -200 450 50 H V L CNN +F1 "Connector_USB_B_Micro" -200 350 50 H V L CNN +F2 "" 150 -50 50 H I C CNN +F3 "" 150 -50 50 H I C CNN +ALIAS USB_B_Mini +$FPLIST + USB* +$ENDFPLIST +DRAW +C -150 85 25 0 1 10 F +C -25 135 15 0 1 10 F +S -200 -300 200 300 0 1 10 f +S -5 -300 5 -270 0 1 0 N +S 10 50 -20 20 0 1 10 F +S 200 -205 170 -195 0 1 0 N +S 200 -105 170 -95 0 1 0 N +S 200 -5 170 5 0 1 0 N +S 200 195 170 205 0 1 0 N +P 2 0 1 10 -75 85 25 85 N +P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N +P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N +P 4 0 1 10 25 110 25 60 75 85 25 110 F +P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F +P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N +X VBUS 1 300 200 100 L 50 50 1 1 w +X D- 2 300 -100 100 L 50 50 1 1 P +X D+ 3 300 0 100 L 50 50 1 1 P +X ID 4 300 -200 100 L 50 50 1 1 P +X GND 5 0 -400 100 U 50 50 1 1 w +X Shield 6 -100 -400 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_C_Small +# +DEF Device_C_Small C 0 10 N N 1 F N +F0 "C" 10 70 50 H V L CNN +F1 "Device_C_Small" 10 -80 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 13 -60 -20 60 -20 N +P 2 0 1 12 -60 20 60 20 N +X ~ 1 0 100 80 D 50 50 1 1 P +X ~ 2 0 -100 80 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_Crystal +# +DEF Device_Crystal Y 0 40 N N 1 F N +F0 "Y" 0 150 50 H V C CNN +F1 "Device_Crystal" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Crystal* +$ENDFPLIST +DRAW +S -45 100 45 -100 0 1 12 N +P 2 0 1 0 -100 0 -75 0 N +P 2 0 1 20 -75 -50 -75 50 N +P 2 0 1 20 75 -50 75 50 N +P 2 0 1 0 100 0 75 0 N +X 1 1 -150 0 50 R 50 50 1 1 P +X 2 2 150 0 50 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_Crystal_GND24 +# +DEF Device_Crystal_GND24 Y 0 40 Y N 1 F N +F0 "Y" 125 200 50 H V L CNN +F1 "Device_Crystal_GND24" 125 125 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Crystal* +$ENDFPLIST +DRAW +S -45 100 45 -100 0 1 12 N +P 2 0 1 0 -100 0 -80 0 N +P 2 0 1 20 -80 -50 -80 50 N +P 2 0 1 0 0 -150 0 -140 N +P 2 0 1 0 0 140 0 150 N +P 2 0 1 20 80 -50 80 50 N +P 2 0 1 0 80 0 100 0 N +P 4 0 1 0 -100 -90 -100 -140 100 -140 100 -90 N +P 4 0 1 0 -100 90 -100 140 100 140 100 90 N +X 1 1 -150 0 50 R 50 50 1 1 P +X 2 2 0 200 50 D 50 50 1 1 P +X 3 3 150 0 50 L 50 50 1 1 P +X 4 4 0 -200 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_Ferrite_Bead_Small +# +DEF Device_Ferrite_Bead_Small FB 0 0 N Y 1 F N +F0 "FB" 75 50 50 H V L CNN +F1 "Device_Ferrite_Bead_Small" 75 -50 50 H V L CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Inductor_* + L_* + *Ferrite* +$ENDFPLIST +DRAW +P 2 0 1 0 0 -50 0 -31 N +P 2 0 1 0 0 35 0 51 N +P 5 0 1 0 -72 11 -44 59 72 -8 44 -56 -72 11 N +X ~ 1 0 100 50 D 50 50 1 1 P +X ~ 2 0 -100 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_R_Small +# +DEF Device_R_Small R 0 10 N N 1 F N +F0 "R" 30 20 50 H V L CNN +F1 "Device_R_Small" 30 -40 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -30 70 30 -70 0 1 8 N +X ~ 1 0 100 30 D 50 50 1 1 P +X ~ 2 0 -100 30 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# MAX7301AAX__MAX7301AAX+ +# +DEF MAX7301AAX__MAX7301AAX+ U 0 40 Y Y 1 L N +F0 "U" -500 1339 50 H V L BNN +F1 "MAX7301AAX__MAX7301AAX+" -500 -1457 50 H V L BNN +F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN +F3 "Maxim Integrated" 0 0 50 H I L BNN +F4 "None" 0 0 50 H I L BNN +F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN +F6 "SSOP-36 Maxim" 0 0 50 H I L BNN +F7 "Unavailable" 0 0 50 H I L BNN +F8 "MAX7301AAX+" 0 0 50 H I L BNN +DRAW +P 2 0 0 16 -500 -1300 -500 1300 N +P 2 0 0 16 -500 1300 500 1300 N +P 2 0 0 16 500 -1300 -500 -1300 N +P 2 0 0 16 500 1300 500 -1300 N +X ISET 1 -700 1000 200 R 40 40 0 0 I +X P9 10 -700 0 200 R 40 40 0 0 B +X P10 11 -700 -100 200 R 40 40 0 0 B +X P11 12 -700 -200 200 R 40 40 0 0 B +X P12 13 -700 -300 200 R 40 40 0 0 B +X P13 14 -700 -400 200 R 40 40 0 0 B +X P14 15 -700 -500 200 R 40 40 0 0 B +X P15 16 -700 -600 200 R 40 40 0 0 B +X P16 17 -700 -700 200 R 40 40 0 0 B +X P17 18 -700 -800 200 R 40 40 0 0 B +X P18 19 700 500 200 L 40 40 0 0 B +X GND 2 700 -1100 200 L 40 40 0 0 W +X P19 20 700 400 200 L 40 40 0 0 B +X P20 21 700 300 200 L 40 40 0 0 B +X P21 22 700 200 200 L 40 40 0 0 B +X P22 23 700 100 200 L 40 40 0 0 B +X P23 24 700 0 200 L 40 40 0 0 B +X P24 25 700 -100 200 L 40 40 0 0 B +X P25 26 700 -200 200 L 40 40 0 0 B +X P26 27 700 -300 200 L 40 40 0 0 B +X P27 28 700 -400 200 L 40 40 0 0 B +X P28 29 700 -500 200 L 40 40 0 0 B +X GND 3 700 -1000 200 L 40 40 0 0 W +X P29 30 700 -600 200 L 40 40 0 0 B +X P30 31 700 -700 200 L 40 40 0 0 B +X P31 32 700 -800 200 L 40 40 0 0 B +X SCLK 33 700 900 200 L 40 40 0 0 I C +X DIN 34 700 800 200 L 40 40 0 0 I +X CS 35 700 1000 200 L 40 40 0 0 I +X V+ 36 700 1200 200 L 40 40 0 0 W +X DOUT 4 700 700 200 L 40 40 0 0 O +X P4 5 -700 500 200 R 40 40 0 0 B +X P5 6 -700 400 200 R 40 40 0 0 B +X P6 7 -700 300 200 R 40 40 0 0 B +X P7 8 -700 200 200 R 40 40 0 0 B +X P8 9 -700 100 200 R 40 40 0 0 B +ENDDRAW +ENDDEF +# +# dk_Interface-Controllers_FT232RQ-REEL +# +DEF dk_Interface-Controllers_FT232RQ-REEL U 0 40 Y Y 1 F N +F0 "U" -600 50 60 H V L CNN +F1 "dk_Interface-Controllers_FT232RQ-REEL" -200 -1300 60 V V L CNN +F2 "digikey-footprints:QFN-32-1EP_5x5mm" 200 200 60 H I L CNN +F3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" 200 300 60 H I L CNN +F4 "768-1008-1-ND" 200 400 60 H I L CNN "Digi-Key_PN" +F5 "FT232RQ-REEL" 200 500 60 H I L CNN "MPN" +F6 "Integrated Circuits (ICs)" 200 600 60 H I L CNN "Category" +F7 "Interface - Controllers" 200 700 60 H I L CNN "Family" +F8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" 200 800 60 H I L CNN "DK_Datasheet_Link" +F9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" 200 900 60 H I L CNN "DK_Detail_Page" +F10 "IC USB FS SERIAL UART 32-QFN" 200 1000 60 H I L CNN "Description" +F11 "FTDI, Future Technology Devices International Ltd" 200 1100 60 H I L CNN "Manufacturer" +F12 "Active" 200 1200 60 H I L CNN "Status" +DRAW +S -600 0 200 -1600 0 1 0 f +X VCCIO 1 -200 100 100 D 50 50 1 1 W +X CBUS2 10 -700 -700 100 R 50 50 1 1 B +X CBUS3 11 -700 -800 100 R 50 50 1 1 B +X NC 12 200 -900 100 L 50 50 1 1 N N +X NC 13 200 -1000 100 L 50 50 1 1 N N +X USBDP 14 -700 -900 100 R 50 50 1 1 B +X USBDM 15 -700 -1000 100 R 50 50 1 1 B +X 3V3OUT 16 300 -300 100 L 50 50 1 1 O +X GND 17 -200 -1700 100 U 50 50 1 1 W +X RESET# 18 -700 -1100 100 R 50 50 1 1 I +X VCC 19 -100 100 100 D 50 50 1 1 W +X RXD 2 -700 -100 100 R 50 50 1 1 I +X GND 20 -100 -1700 100 U 50 50 1 1 W +X CBUS1 21 -700 -1200 100 R 50 50 1 1 B +X CBUS0 22 -700 -1300 100 R 50 50 1 1 B +X NC 23 200 -1100 100 L 50 50 1 1 N N +X AGND 24 0 -1700 100 U 50 50 1 1 W +X NC 25 200 -1200 100 L 50 50 1 1 N N +X TEST 26 -700 -1400 100 R 50 50 1 1 I +X OSCI 27 -700 -1500 100 R 50 50 1 1 I +X OSCO 28 300 -400 100 L 50 50 1 1 O +X NC 29 200 -1300 100 L 50 50 1 1 N N +X RI# 3 -700 -200 100 R 50 50 1 1 I +X TXD 30 300 -500 100 L 50 50 1 1 O +X DTR# 31 300 -600 100 L 50 50 1 1 O +X RTS# 32 300 -700 100 L 50 50 1 1 O +X EP 33 100 -1700 100 U 50 50 1 1 U +X GND 4 -300 -1700 100 U 50 50 1 1 W +X NC 5 200 -800 100 L 50 50 1 1 N N +X DSR# 6 -700 -300 100 R 50 50 1 1 I +X DCD# 7 -700 -400 100 R 50 50 1 1 I +X CTS# 8 -700 -500 100 R 50 50 1 1 I +X CBUS4 9 -700 -600 100 R 50 50 1 1 B +ENDDRAW +ENDDEF +# +# dk_Transistors-FETs-MOSFETs-Single_IRLML6402TRPBF +# +DEF dk_Transistors-FETs-MOSFETs-Single_IRLML6402TRPBF Q 0 0 Y Y 1 F N +F0 "Q" -106 143 60 H V R CNN +F1 "dk_Transistors-FETs-MOSFETs-Single_IRLML6402TRPBF" 136 0 60 V V C CNN +F2 "digikey-footprints:SOT-23-3" 200 200 60 H I L CNN +F3 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" 200 300 60 H I L CNN +F4 "IRLML6402PBFCT-ND" 200 400 60 H I L CNN "Digi-Key_PN" +F5 "IRLML6402TRPBF" 200 500 60 H I L CNN "MPN" +F6 "Discrete Semiconductor Products" 200 600 60 H I L CNN "Category" +F7 "Transistors - FETs, MOSFETs - Single" 200 700 60 H I L CNN "Family" +F8 "https://www.infineon.com/dgdl/irlml6402pbf.pdf?fileId=5546d462533600a401535668d5c2263c" 200 800 60 H I L CNN "DK_Datasheet_Link" +F9 "/product-detail/en/infineon-technologies/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500" 200 900 60 H I L CNN "DK_Detail_Page" +F10 "MOSFET P-CH 20V 3.7A SOT-23" 200 1000 60 H I L CNN "Description" +F11 "Infineon Technologies" 200 1100 60 H I L CNN "Manufacturer" +F12 "Active" 200 1200 60 H I L CNN "Status" +DRAW +C -50 0 130 0 1 0 f +C 0 -75 5 0 1 0 N +C 0 -55 5 0 1 0 N +C 0 75 5 0 1 0 N +P 2 0 1 0 0 -55 -100 -55 N +P 3 0 1 0 -200 -100 -120 -100 -120 55 N +P 3 0 1 0 0 -100 0 0 -100 0 N +P 3 0 1 0 0 100 0 55 -100 55 N +P 5 0 1 0 -5 -75 40 -75 40 55 40 75 -5 75 N +P 2 1 1 0 -100 -55 -100 -75 N +P 2 1 1 0 -100 -55 -100 -35 N +P 2 1 1 0 -100 0 -100 -20 N +P 2 1 1 0 -100 0 -100 20 N +P 2 1 1 0 -100 75 -100 35 N +P 2 1 1 0 60 -8 20 -8 N +P 4 1 1 0 -15 0 -45 20 -45 -20 -15 0 F +P 4 1 1 0 40 -10 60 20 20 20 40 -10 F +X G 1 -300 -100 100 R 50 50 1 1 B +X S 2 0 -200 100 U 50 50 1 1 B +X D 3 0 200 100 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# p_ATSAME54P20A-AU_p_ATSAME54P20A-AU +# +DEF p_ATSAME54P20A-AU_p_ATSAME54P20A-AU U 0 40 Y Y 5 L N +F0 "U" 0 -2600 50 H V C CNN +F1 "p_ATSAME54P20A-AU_p_ATSAME54P20A-AU" 0 1050 50 H V C CNN +F2 "" -1200 1250 50 H I C CNN +F3 "" -1200 1250 50 H I C CNN +DRAW +T 0 0 950 50 0 1 0 "Port A" Normal 0 C C +T 0 0 800 50 0 2 0 "Port B" Normal 0 C C +T 0 0 750 50 0 3 0 "Port C" Normal 0 C C +T 0 0 850 50 0 4 0 "Port D" Normal 0 C C +T 0 50 650 50 0 5 0 "Power Bus" Normal 0 C C +S -450 1000 400 -2150 1 1 0 f +S -500 900 500 -2550 2 1 0 f +S -450 850 450 -2250 3 1 0 f +S -400 900 400 -150 4 1 0 f +S -800 750 800 -1450 5 1 0 f +X XIN32/PA00 1 600 750 200 L 50 50 1 1 B +X PA03 10 600 450 200 L 50 50 1 1 B +X PA27 113 600 -1850 200 L 50 50 1 1 B +X SWCLK/PA30 119 600 -1950 200 L 50 50 1 1 B +X SWDIO/PA31 120 600 -2050 200 L 50 50 1 1 B +X XOUT32/PA01 2 600 650 200 L 50 50 1 1 B +X PA04 21 600 350 200 L 50 50 1 1 B +X PA05 22 600 250 200 L 50 50 1 1 B +X PA06 23 600 150 200 L 50 50 1 1 B +X PA07 24 600 50 200 L 50 50 1 1 B +X PA08 33 600 -50 200 L 50 50 1 1 B +X PA09 34 600 -150 200 L 50 50 1 1 B +X PA10 35 600 -250 200 L 50 50 1 1 B +X PA11 36 600 -350 200 L 50 50 1 1 B +X PA12 60 600 -450 200 L 50 50 1 1 B +X PA13 61 600 -550 200 L 50 50 1 1 B +X XIN0/PA14 62 600 -650 200 L 50 50 1 1 B +X XOUT0/PA15 63 600 -750 200 L 50 50 1 1 B +X PA16 66 600 -850 200 L 50 50 1 1 B +X PA17 67 600 -950 200 L 50 50 1 1 B +X PA18 68 600 -1050 200 L 50 50 1 1 B +X PA19 69 600 -1150 200 L 50 50 1 1 B +X PA20 88 600 -1250 200 L 50 50 1 1 B +X PA21 89 600 -1350 200 L 50 50 1 1 B +X PA02 9 600 550 200 L 50 50 1 1 B +X PA22 92 600 -1450 200 L 50 50 1 1 B +X PA23 93 600 -1550 200 L 50 50 1 1 B +X PA24 94 600 -1650 200 L 50 50 1 1 B +X PA25 95 600 -1750 200 L 50 50 1 1 B +X PB24 100 700 -1750 197 L 50 50 2 1 B +X PB25 101 700 -1850 197 L 50 50 2 1 B +X PB26 102 700 -1950 197 L 50 50 2 1 B +X PB27 103 700 -2050 197 L 50 50 2 1 B +X PB28 104 700 -2150 197 L 50 50 2 1 B +X PB29 105 700 -2250 197 L 50 50 2 1 B +X PB04 11 700 250 197 L 50 50 2 1 B +X PB05 12 700 150 197 L 50 50 2 1 B +X SWO/PB30 121 700 -2350 197 L 50 50 2 1 B +X PB31 122 700 -2450 197 L 50 50 2 1 B +X PB00 125 700 650 197 L 50 50 2 1 B +X PB01 126 700 550 197 L 50 50 2 1 B +X PB02 127 700 450 197 L 50 50 2 1 B +X PB03 128 700 350 197 L 50 50 2 1 B +X PB06 17 700 50 197 L 50 50 2 1 B +X PB07 18 700 -50 197 L 50 50 2 1 B +X PB08 19 700 -150 197 L 50 50 2 1 B +X PB09 20 700 -250 197 L 50 50 2 1 B +X PB10 39 700 -350 197 L 50 50 2 1 B +X PB11 40 700 -450 197 L 50 50 2 1 B +X PB12 41 700 -550 197 L 50 50 2 1 B +X PB13 42 700 -650 197 L 50 50 2 1 B +X PB14 43 700 -750 197 L 50 50 2 1 B +X PB15 44 700 -850 197 L 50 50 2 1 B +X PB16 82 700 -950 197 L 50 50 2 1 B +X PB17 83 700 -1050 197 L 50 50 2 1 B +X PB18 84 700 -1150 197 L 50 50 2 1 B +X PB19 85 700 -1250 197 L 50 50 2 1 B +X PB20 86 700 -1350 197 L 50 50 2 1 B +X PB21 87 700 -1450 197 L 50 50 2 1 B +X XIN1/PB22 98 700 -1550 197 L 50 50 2 1 B +X XOUT1/PB23 99 700 -1650 197 L 50 50 2 1 B +X PC24 108 650 -1550 197 L 50 50 3 1 B +X PC25 109 650 -1650 197 L 50 50 3 1 B +X PC26 110 650 -1750 197 L 50 50 3 1 B +X PC27 111 650 -1850 197 L 50 50 3 1 B +X PC28 112 650 -1950 197 L 50 50 3 1 B +X PC30 123 650 -2050 197 L 50 50 3 1 B +X PC31 124 650 -2150 197 L 50 50 3 1 B +X PC04 27 650 250 197 L 50 50 3 1 B +X PC05 28 650 150 197 L 50 50 3 1 B +X PC06 29 650 50 197 L 50 50 3 1 B +X PC00 3 650 650 197 L 50 50 3 1 B +X PC07 30 650 -50 197 L 50 50 3 1 B +X PC01 4 650 550 197 L 50 50 3 1 B +X PC10 52 650 -150 197 L 50 50 3 1 B +X PC11 55 650 -250 197 L 50 50 3 1 B +X PC12 56 650 -350 197 L 50 50 3 1 B +X PC13 57 650 -450 197 L 50 50 3 1 B +X PC14 58 650 -550 197 L 50 50 3 1 B +X PC15 59 650 -650 197 L 50 50 3 1 B +X PC02 7 650 450 197 L 50 50 3 1 B +X PC16 70 650 -750 197 L 50 50 3 1 B +X PC17 71 650 -850 197 L 50 50 3 1 B +X PC18 72 650 -950 197 L 50 50 3 1 B +X PC19 73 650 -1050 197 L 50 50 3 1 B +X PC20 74 650 -1150 197 L 50 50 3 1 B +X PC21 75 650 -1250 197 L 50 50 3 1 B +X PC22 76 650 -1350 197 L 50 50 3 1 B +X PC23 77 650 -1450 197 L 50 50 3 1 B +X PC03 8 650 350 197 L 50 50 3 1 B +X PD00 13 600 750 197 L 50 50 4 1 B +X PD01 16 600 650 197 L 50 50 4 1 B +X PD08 47 600 550 197 L 50 50 4 1 B +X PD09 48 600 450 197 L 50 50 4 1 B +X PD10 49 600 350 197 L 50 50 4 1 B +X PD11 50 600 250 197 L 50 50 4 1 B +X PD12 51 600 150 197 L 50 50 4 1 B +X PD20 80 600 50 197 L 50 50 4 1 B +X PD21 81 600 -50 197 L 50 50 4 1 B +X VDDIO7 107 -1000 -900 197 R 50 50 5 1 W +X ~RESET 114 -1000 650 197 R 50 50 5 1 B +X VDDCORE 115 -1000 -1150 197 R 50 50 5 1 W +X GNDIO 116 1000 -850 197 L 50 50 5 1 W +X VSW 117 -1000 -1300 197 R 50 50 5 1 W +X VDDIO8 118 -1000 -1000 197 R 50 50 5 1 W +X GNDANA1 14 1000 -500 197 L 50 50 5 1 W +X VDDANA2 15 -1000 300 197 R 50 50 5 1 B +X GNDANA2 25 1000 -600 197 L 50 50 5 1 W +X VDDANA3 26 -1000 200 197 R 50 50 5 1 B +X VDDIOB1 32 -1000 0 197 R 50 50 5 1 B +X VDDIOB2 37 -1000 -100 197 R 50 50 5 1 B +X VDDIO1 46 -1000 -300 197 R 50 50 5 1 W +X GND1 5 1000 650 197 L 50 50 5 1 W +X GND10 5 1000 -250 197 L 50 50 5 1 W +X GND2 5 1000 550 197 L 50 50 5 1 W +X GND3 5 1000 450 197 L 50 50 5 1 W +X GND4 5 1000 350 197 L 50 50 5 1 W +X GND5 5 1000 250 197 L 50 50 5 1 W +X GND6 5 1000 150 197 L 50 50 5 1 W +X GND7 5 1000 50 197 L 50 50 5 1 W +X GND8 5 1000 -50 197 L 50 50 5 1 W +X GND9 5 1000 -150 197 L 50 50 5 1 W +X VDDIO2 54 -1000 -400 197 R 50 50 5 1 W +X VDDANA1 6 -1000 400 197 R 50 50 5 1 B +X VDDIO3 65 -1000 -500 197 R 50 50 5 1 W +X VDDIO4 79 -1000 -600 197 R 50 50 5 1 W +X VDDIO5 91 -1000 -700 197 R 50 50 5 1 W +X VDDIO6 97 -1000 -800 197 R 50 50 5 1 W +ENDDRAW +ENDDEF +# +# power_+3V3 +# +DEF power_+3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+3V3" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS +3.3V +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_+5V +# +DEF power_+5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+5V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_GND +# +DEF power_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_PWR_FLAG +# +DEF power_PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "power_PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +X pwr 1 0 0 0 U 50 50 0 0 w +ENDDRAW +ENDDEF +# +# same54_dev_board-rescue_NCP349MNAETBG-NCP349MNAETBG +# +DEF same54_dev_board-rescue_NCP349MNAETBG-NCP349MNAETBG U 0 40 Y Y 1 F N +F0 "U" 0 -200 50 H V C CNN +F1 "same54_dev_board-rescue_NCP349MNAETBG-NCP349MNAETBG" 0 350 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -300 250 300 -150 0 1 0 f +X VIN 1 -400 150 100 R 50 50 1 1 I +X GND 2 -400 50 100 R 50 50 1 1 I +X ~FLAG 3 400 150 100 L 50 50 1 1 I +X ~EN 4 -400 -50 100 R 50 50 1 1 I +X OUT 5 400 50 100 L 50 50 1 1 I +X OUT 6 400 -50 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/electrical/same54_dev_board/same54_dev_board.kicad_pcb b/electrical/same54_dev_board/same54_dev_board.kicad_pcb index 7191e3f..9300e15 100644 --- a/electrical/same54_dev_board/same54_dev_board.kicad_pcb +++ b/electrical/same54_dev_board/same54_dev_board.kicad_pcb @@ -1,1591 +1,1591 @@ -(kicad_pcb (version 20171130) (host pcbnew 5.1.5) - - (general - (thickness 1.6) - (drawings 5) - (tracks 0) - (zones 0) - (modules 13) - (nets 196) - ) - - (page A4) - (layers - (0 F.Cu signal) - (31 B.Cu signal) - (32 B.Adhes user) - (33 F.Adhes user) - (34 B.Paste user) - (35 F.Paste user) - (36 B.SilkS user) - (37 F.SilkS user) - (38 B.Mask user) - (39 F.Mask user) - (40 Dwgs.User user) - (41 Cmts.User user) - (42 Eco1.User user) - (43 Eco2.User user) - (44 Edge.Cuts user) - (45 Margin user) - (46 B.CrtYd user) - (47 F.CrtYd user) - (48 B.Fab user) - (49 F.Fab user) - ) - - (setup - (last_trace_width 0.25) - (trace_clearance 0.2) - (zone_clearance 0.508) - (zone_45_only no) - (trace_min 0.2) - (via_size 0.8) - (via_drill 0.4) - (via_min_size 0.4) - (via_min_drill 0.3) - (uvia_size 0.3) - (uvia_drill 0.1) - (uvias_allowed no) - (uvia_min_size 0.2) - (uvia_min_drill 0.1) - (edge_width 0.05) - (segment_width 0.2) - (pcb_text_width 0.3) - (pcb_text_size 1.5 1.5) - (mod_edge_width 0.12) - (mod_text_size 1 1) - (mod_text_width 0.15) - (pad_size 3.45 3.45) - (pad_drill 0) - (pad_to_mask_clearance 0.051) - (solder_mask_min_width 0.25) - (aux_axis_origin 0 0) - (visible_elements 7FFFFFFF) - (pcbplotparams - (layerselection 0x010fc_ffffffff) - (usegerberextensions false) - (usegerberattributes false) - (usegerberadvancedattributes false) - (creategerberjobfile false) - (excludeedgelayer true) - (linewidth 0.100000) - (plotframeref false) - (viasonmask false) - (mode 1) - (useauxorigin false) - (hpglpennumber 1) - (hpglpenspeed 20) - (hpglpendiameter 15.000000) - (psnegative false) - (psa4output false) - (plotreference true) - (plotvalue true) - (plotinvisibletext false) - (padsonsilk false) - (subtractmaskfromsilk false) - (outputformat 1) - (mirror false) - (drillshape 1) - (scaleselection 1) - (outputdirectory "")) - ) - - (net 0 "") - (net 1 "Net-(J1-Pad4)") - (net 2 "Net-(J2-Pad8)") - (net 3 "Net-(J2-Pad7)") - (net 4 "Net-(J2-Pad1)") - (net 5 "Net-(J3-Pad40)") - (net 6 "Net-(J3-Pad39)") - (net 7 "Net-(J3-Pad38)") - (net 8 "Net-(J3-Pad6)") - (net 9 "Net-(U1-Pad95)") - (net 10 "Net-(U1-Pad94)") - (net 11 "Net-(U1-Pad93)") - (net 12 "Net-(U1-Pad92)") - (net 13 "Net-(U1-Pad89)") - (net 14 "Net-(U1-Pad88)") - (net 15 "Net-(U1-Pad87)") - (net 16 "Net-(U1-Pad86)") - (net 17 "Net-(U1-Pad85)") - (net 18 "Net-(U1-Pad84)") - (net 19 "Net-(U1-Pad83)") - (net 20 "Net-(U1-Pad82)") - (net 21 "Net-(U1-Pad81)") - (net 22 "Net-(U1-Pad80)") - (net 23 "Net-(U1-Pad77)") - (net 24 "Net-(U1-Pad76)") - (net 25 "Net-(U1-Pad75)") - (net 26 "Net-(U1-Pad74)") - (net 27 "Net-(U1-Pad73)") - (net 28 "Net-(U1-Pad72)") - (net 29 "Net-(U1-Pad71)") - (net 30 "Net-(U1-Pad70)") - (net 31 "Net-(U1-Pad69)") - (net 32 "Net-(U1-Pad68)") - (net 33 "Net-(U1-Pad32)") - (net 34 "Net-(U1-Pad30)") - (net 35 "Net-(U1-Pad29)") - (net 36 "Net-(U1-Pad28)") - (net 37 "Net-(U1-Pad27)") - (net 38 "Net-(U1-Pad26)") - (net 39 "Net-(U1-Pad24)") - (net 40 "Net-(U1-Pad20)") - (net 41 "Net-(U1-Pad19)") - (net 42 "Net-(U1-Pad18)") - (net 43 "Net-(U1-Pad16)") - (net 44 "Net-(U1-Pad15)") - (net 45 "Net-(U1-Pad14)") - (net 46 "Net-(U1-Pad13)") - (net 47 "Net-(U1-Pad10)") - (net 48 "Net-(U1-Pad9)") - (net 49 "Net-(U1-Pad8)") - (net 50 "Net-(U1-Pad7)") - (net 51 "Net-(U1-Pad6)") - (net 52 "Net-(U1-Pad5)") - (net 53 "Net-(U1-Pad4)") - (net 54 "Net-(U1-Pad3)") - (net 55 "Net-(C1-Pad2)") - (net 56 "Net-(U1-Pad124)") - (net 57 "Net-(U1-Pad123)") - (net 58 "Net-(U1-Pad122)") - (net 59 "Net-(U1-Pad121)") - (net 60 "Net-(U1-Pad120)") - (net 61 "Net-(U1-Pad119)") - (net 62 "Net-(U1-Pad117)") - (net 63 "Net-(U1-Pad116)") - (net 64 "Net-(U1-Pad115)") - (net 65 "Net-(U1-Pad114)") - (net 66 "Net-(U1-Pad113)") - (net 67 "Net-(U1-Pad112)") - (net 68 "Net-(U1-Pad111)") - (net 69 "Net-(U1-Pad110)") - (net 70 "Net-(U1-Pad109)") - (net 71 "Net-(U1-Pad108)") - (net 72 "Net-(U1-Pad107)") - (net 73 "Net-(U1-Pad105)") - (net 74 "Net-(U1-Pad104)") - (net 75 "Net-(U1-Pad103)") - (net 76 "Net-(U1-Pad102)") - (net 77 "Net-(U1-Pad99)") - (net 78 "Net-(U1-Pad98)") - (net 79 "Net-(U1-Pad61)") - (net 80 "Net-(U1-Pad60)") - (net 81 "Net-(U1-Pad59)") - (net 82 "Net-(U1-Pad58)") - (net 83 "Net-(U1-Pad57)") - (net 84 "Net-(U1-Pad56)") - (net 85 "Net-(U1-Pad55)") - (net 86 "Net-(U1-Pad52)") - (net 87 "Net-(U1-Pad51)") - (net 88 "Net-(U1-Pad50)") - (net 89 "Net-(U1-Pad49)") - (net 90 "Net-(U1-Pad48)") - (net 91 "Net-(U1-Pad47)") - (net 92 "Net-(U1-Pad44)") - (net 93 "Net-(U1-Pad43)") - (net 94 "Net-(U1-Pad42)") - (net 95 "Net-(U1-Pad41)") - (net 96 "Net-(U1-Pad40)") - (net 97 "Net-(U1-Pad39)") - (net 98 "Net-(U1-Pad37)") - (net 99 "Net-(U1-Pad36)") - (net 100 "Net-(U1-Pad35)") - (net 101 "Net-(U1-Pad34)") - (net 102 "Net-(U1-Pad33)") - (net 103 "Net-(U2-Pad32)") - (net 104 "Net-(U2-Pad31)") - (net 105 "Net-(U2-Pad29)") - (net 106 "Net-(U2-Pad28)") - (net 107 "Net-(U2-Pad27)") - (net 108 "Net-(U2-Pad23)") - (net 109 "Net-(U2-Pad22)") - (net 110 "Net-(U2-Pad21)") - (net 111 "Net-(U2-Pad18)") - (net 112 "Net-(U2-Pad13)") - (net 113 "Net-(U2-Pad12)") - (net 114 "Net-(U2-Pad11)") - (net 115 "Net-(U2-Pad10)") - (net 116 "Net-(U2-Pad8)") - (net 117 "Net-(U2-Pad7)") - (net 118 "Net-(U2-Pad6)") - (net 119 "Net-(U2-Pad5)") - (net 120 "Net-(U2-Pad3)") - (net 121 "Net-(U2-Pad25)") - (net 122 g_3v3) - (net 123 "Net-(U3-Pad32)") - (net 124 "Net-(U3-Pad31)") - (net 125 "Net-(U3-Pad30)") - (net 126 "Net-(U3-Pad29)") - (net 127 GND) - (net 128 "Net-(R1-Pad1)") - (net 129 /s_USB_INTF.sch/USB_D+) - (net 130 /s_USB_INTF.sch/USB_D-) - (net 131 "Net-(C2-Pad1)") - (net 132 "Net-(C5-Pad2)") - (net 133 "Net-(C4-Pad2)") - (net 134 /DEBUG_RX) - (net 135 /DEBUG_TX) - (net 136 /s_SCREEN_INTF/TFT_STB) - (net 137 /s_SCREEN_INTF/D23) - (net 138 /s_SCREEN_INTF/D22) - (net 139 /s_SCREEN_INTF/D21) - (net 140 /s_SCREEN_INTF/D20) - (net 141 /s_SCREEN_INTF/D19) - (net 142 /s_SCREEN_INTF/D18) - (net 143 /s_SCREEN_INTF/D17) - (net 144 /s_SCREEN_INTF/D16) - (net 145 /s_SCREEN_INTF/D15) - (net 146 /s_SCREEN_INTF/D14) - (net 147 /s_SCREEN_INTF/D13) - (net 148 /s_SCREEN_INTF/D12) - (net 149 /s_SCREEN_INTF/D11) - (net 150 /s_SCREEN_INTF/D10) - (net 151 /s_SCREEN_INTF/D9) - (net 152 /s_SCREEN_INTF/D8) - (net 153 /s_SCREEN_INTF/D7) - (net 154 /s_SCREEN_INTF/D6) - (net 155 /s_SCREEN_INTF/D5) - (net 156 /s_SCREEN_INTF/D4) - (net 157 /s_SCREEN_INTF/D3) - (net 158 /s_SCREEN_INTF/D2) - (net 159 /s_SCREEN_INTF/D1) - (net 160 /s_SCREEN_INTF/D0) - (net 161 /s_SCREEN_INTF/TFT_TE) - (net 162 /s_SCREEN_INTF/~TFT_RD) - (net 163 /s_SCREEN_INTF/~TFT_WR) - (net 164 /s_SCREEN_INTF/TFT_RSDC) - (net 165 /s_SCREEN_INTF/~TFT_RST) - (net 166 /s_SCREEN_INTF/TFT_TOUCH_INT) - (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS) - (net 168 "Net-(C7-Pad1)") - (net 169 /~TFT_CS) - (net 170 /MASTER_I2C_SDA) - (net 171 /MASTER_I2C_SCL) - (net 172 /s_Power/USB_5v) - (net 173 /s_Power/USB_3v3) - (net 174 /MASTER_SPI_MISO) - (net 175 /MASTER_SPI_CLK) - (net 176 /s_USB_INTF.sch/FTDI_5V) - (net 177 /s_USB_INTF.sch/FTDI_3V3) - (net 178 /MASTER_SPI_MOSI) - (net 179 "Net-(U4-Pad5)") - (net 180 "Net-(U4-Pad3)") - (net 181 "Net-(Q1-Pad3)") - (net 182 "Net-(Q2-Pad3)") - (net 183 "Net-(C10-Pad1)") - (net 184 /s_BRAIN/~SYS_RST) - (net 185 /s_BRAIN/SWO) - (net 186 /s_BRAIN/SWCLK) - (net 187 /s_BRAIN/SWDIO) - (net 188 /s_Power/Wall_5V) - (net 189 "Net-(J4-Pad3)") - (net 190 /s_BRAIN/EXT_IRQ_5) - (net 191 /s_BRAIN/EXT_IRQ_4) - (net 192 /s_BRAIN/EXT_IRQ_3) - (net 193 /s_BRAIN/EXT_IRQ_2) - (net 194 /s_BRAIN/EXT_IRQ_1) - (net 195 /s_BRAIN/EXT_IRQ_0) - - (net_class Default "This is the default net class." - (clearance 0.2) - (trace_width 0.25) - (via_dia 0.8) - (via_drill 0.4) - (uvia_dia 0.3) - (uvia_drill 0.1) - (add_net /DEBUG_RX) - (add_net /DEBUG_TX) - (add_net /MASTER_I2C_SCL) - (add_net /MASTER_I2C_SDA) - (add_net /MASTER_SPI_CLK) - (add_net /MASTER_SPI_MISO) - (add_net /MASTER_SPI_MOSI) - (add_net /s_BRAIN/EXT_IRQ_0) - (add_net /s_BRAIN/EXT_IRQ_1) - (add_net /s_BRAIN/EXT_IRQ_2) - (add_net /s_BRAIN/EXT_IRQ_3) - (add_net /s_BRAIN/EXT_IRQ_4) - (add_net /s_BRAIN/EXT_IRQ_5) - (add_net /s_BRAIN/SWCLK) - (add_net /s_BRAIN/SWDIO) - (add_net /s_BRAIN/SWO) - (add_net /s_BRAIN/~SYS_RST) - (add_net /s_Power/USB_3v3) - (add_net /s_Power/USB_5v) - (add_net /s_Power/Wall_5V) - (add_net /s_SCREEN_INTF/D0) - (add_net /s_SCREEN_INTF/D1) - (add_net /s_SCREEN_INTF/D10) - (add_net /s_SCREEN_INTF/D11) - (add_net /s_SCREEN_INTF/D12) - (add_net /s_SCREEN_INTF/D13) - (add_net /s_SCREEN_INTF/D14) - (add_net /s_SCREEN_INTF/D15) - (add_net /s_SCREEN_INTF/D16) - (add_net /s_SCREEN_INTF/D17) - (add_net /s_SCREEN_INTF/D18) - (add_net /s_SCREEN_INTF/D19) - (add_net /s_SCREEN_INTF/D2) - (add_net /s_SCREEN_INTF/D20) - (add_net /s_SCREEN_INTF/D21) - (add_net /s_SCREEN_INTF/D22) - (add_net /s_SCREEN_INTF/D23) - (add_net /s_SCREEN_INTF/D3) - (add_net /s_SCREEN_INTF/D4) - (add_net /s_SCREEN_INTF/D5) - (add_net /s_SCREEN_INTF/D6) - (add_net /s_SCREEN_INTF/D7) - (add_net /s_SCREEN_INTF/D8) - (add_net /s_SCREEN_INTF/D9) - (add_net /s_SCREEN_INTF/TFT_RSDC) - (add_net /s_SCREEN_INTF/TFT_STB) - (add_net /s_SCREEN_INTF/TFT_TE) - (add_net /s_SCREEN_INTF/TFT_TOUCH_INT) - (add_net /s_SCREEN_INTF/~IO_EXPANDER_CS) - (add_net /s_SCREEN_INTF/~TFT_RD) - (add_net /s_SCREEN_INTF/~TFT_RST) - (add_net /s_SCREEN_INTF/~TFT_WR) - (add_net /s_USB_INTF.sch/FTDI_3V3) - (add_net /s_USB_INTF.sch/FTDI_5V) - (add_net /s_USB_INTF.sch/USB_D+) - (add_net /s_USB_INTF.sch/USB_D-) - (add_net /~TFT_CS) - (add_net GND) - (add_net "Net-(C1-Pad2)") - (add_net "Net-(C10-Pad1)") - (add_net "Net-(C2-Pad1)") - (add_net "Net-(C4-Pad2)") - (add_net "Net-(C5-Pad2)") - (add_net "Net-(C7-Pad1)") - (add_net "Net-(J1-Pad4)") - (add_net "Net-(J2-Pad1)") - (add_net "Net-(J2-Pad7)") - (add_net "Net-(J2-Pad8)") - (add_net "Net-(J3-Pad38)") - (add_net "Net-(J3-Pad39)") - (add_net "Net-(J3-Pad40)") - (add_net "Net-(J3-Pad6)") - (add_net "Net-(J4-Pad3)") - (add_net "Net-(Q1-Pad3)") - (add_net "Net-(Q2-Pad3)") - (add_net "Net-(R1-Pad1)") - (add_net "Net-(U1-Pad10)") - (add_net "Net-(U1-Pad102)") - (add_net "Net-(U1-Pad103)") - (add_net "Net-(U1-Pad104)") - (add_net "Net-(U1-Pad105)") - (add_net "Net-(U1-Pad107)") - (add_net "Net-(U1-Pad108)") - (add_net "Net-(U1-Pad109)") - (add_net "Net-(U1-Pad110)") - (add_net "Net-(U1-Pad111)") - (add_net "Net-(U1-Pad112)") - (add_net "Net-(U1-Pad113)") - (add_net "Net-(U1-Pad114)") - (add_net "Net-(U1-Pad115)") - (add_net "Net-(U1-Pad116)") - (add_net "Net-(U1-Pad117)") - (add_net "Net-(U1-Pad119)") - (add_net "Net-(U1-Pad120)") - (add_net "Net-(U1-Pad121)") - (add_net "Net-(U1-Pad122)") - (add_net "Net-(U1-Pad123)") - (add_net "Net-(U1-Pad124)") - (add_net "Net-(U1-Pad13)") - (add_net "Net-(U1-Pad14)") - (add_net "Net-(U1-Pad15)") - (add_net "Net-(U1-Pad16)") - (add_net "Net-(U1-Pad18)") - (add_net "Net-(U1-Pad19)") - (add_net "Net-(U1-Pad20)") - (add_net "Net-(U1-Pad24)") - (add_net "Net-(U1-Pad26)") - (add_net "Net-(U1-Pad27)") - (add_net "Net-(U1-Pad28)") - (add_net "Net-(U1-Pad29)") - (add_net "Net-(U1-Pad3)") - (add_net "Net-(U1-Pad30)") - (add_net "Net-(U1-Pad32)") - (add_net "Net-(U1-Pad33)") - (add_net "Net-(U1-Pad34)") - (add_net "Net-(U1-Pad35)") - (add_net "Net-(U1-Pad36)") - (add_net "Net-(U1-Pad37)") - (add_net "Net-(U1-Pad39)") - (add_net "Net-(U1-Pad4)") - (add_net "Net-(U1-Pad40)") - (add_net "Net-(U1-Pad41)") - (add_net "Net-(U1-Pad42)") - (add_net "Net-(U1-Pad43)") - (add_net "Net-(U1-Pad44)") - (add_net "Net-(U1-Pad47)") - (add_net "Net-(U1-Pad48)") - (add_net "Net-(U1-Pad49)") - (add_net "Net-(U1-Pad5)") - (add_net "Net-(U1-Pad50)") - (add_net "Net-(U1-Pad51)") - (add_net "Net-(U1-Pad52)") - (add_net "Net-(U1-Pad55)") - (add_net "Net-(U1-Pad56)") - (add_net "Net-(U1-Pad57)") - (add_net "Net-(U1-Pad58)") - (add_net "Net-(U1-Pad59)") - (add_net "Net-(U1-Pad6)") - (add_net "Net-(U1-Pad60)") - (add_net "Net-(U1-Pad61)") - (add_net "Net-(U1-Pad68)") - (add_net "Net-(U1-Pad69)") - (add_net "Net-(U1-Pad7)") - (add_net "Net-(U1-Pad70)") - (add_net "Net-(U1-Pad71)") - (add_net "Net-(U1-Pad72)") - (add_net "Net-(U1-Pad73)") - (add_net "Net-(U1-Pad74)") - (add_net "Net-(U1-Pad75)") - (add_net "Net-(U1-Pad76)") - (add_net "Net-(U1-Pad77)") - (add_net "Net-(U1-Pad8)") - (add_net "Net-(U1-Pad80)") - (add_net "Net-(U1-Pad81)") - (add_net "Net-(U1-Pad82)") - (add_net "Net-(U1-Pad83)") - (add_net "Net-(U1-Pad84)") - (add_net "Net-(U1-Pad85)") - (add_net "Net-(U1-Pad86)") - (add_net "Net-(U1-Pad87)") - (add_net "Net-(U1-Pad88)") - (add_net "Net-(U1-Pad89)") - (add_net "Net-(U1-Pad9)") - (add_net "Net-(U1-Pad92)") - (add_net "Net-(U1-Pad93)") - (add_net "Net-(U1-Pad94)") - (add_net "Net-(U1-Pad95)") - (add_net "Net-(U1-Pad98)") - (add_net "Net-(U1-Pad99)") - (add_net "Net-(U2-Pad10)") - (add_net "Net-(U2-Pad11)") - (add_net "Net-(U2-Pad12)") - (add_net "Net-(U2-Pad13)") - (add_net "Net-(U2-Pad18)") - (add_net "Net-(U2-Pad21)") - (add_net "Net-(U2-Pad22)") - (add_net "Net-(U2-Pad23)") - (add_net "Net-(U2-Pad25)") - (add_net "Net-(U2-Pad27)") - (add_net "Net-(U2-Pad28)") - (add_net "Net-(U2-Pad29)") - (add_net "Net-(U2-Pad3)") - (add_net "Net-(U2-Pad31)") - (add_net "Net-(U2-Pad32)") - (add_net "Net-(U2-Pad5)") - (add_net "Net-(U2-Pad6)") - (add_net "Net-(U2-Pad7)") - (add_net "Net-(U2-Pad8)") - (add_net "Net-(U3-Pad29)") - (add_net "Net-(U3-Pad30)") - (add_net "Net-(U3-Pad31)") - (add_net "Net-(U3-Pad32)") - (add_net "Net-(U4-Pad3)") - (add_net "Net-(U4-Pad5)") - (add_net g_3v3) - ) - - (module digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A (layer F.Cu) (tedit 5CAD146F) (tstamp 5E7AD729) - (at 62.23 60.96 90) - (path /5E7872D3/5E88DD8C) - (fp_text reference J4 (at 0 -12.1 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Barrel_Jack_Switch (at 0 5.8 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -4.5 3.7) (end 4.5 3.7) (layer F.Fab) (width 0.1)) - (fp_line (start -4.5 3.7) (end -4.5 -10.7) (layer F.Fab) (width 0.1)) - (fp_line (start 4.5 3.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) - (fp_line (start -4.5 -10.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) - (fp_line (start 4.6 3.8) (end 4.1 3.8) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 3.8) (end 4.6 3.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 3.8) (end -4.1 3.8) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 3.8) (end -4.6 3.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -1.2 -1.8) (end 1.2 -1.8) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 -10.8) (end -4.6 -10.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 -10.8) (end -4.1 -10.8) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 -10.8) (end 4.1 -10.8) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 -10.8) (end 4.6 -10.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 -3.5) (end -4.6 -4.5) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 -3.5) (end 4.6 -4.5) (layer F.SilkS) (width 0.1)) - (fp_line (start -5.9 -10.95) (end 4.8 -10.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.9 -10.95) (end -5.9 4.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start 4.8 -10.95) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.9 4.25) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) - (pad 2 thru_hole rect (at 0 -3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 1 thru_hole rect (at 0 3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) - (net 188 /s_Power/Wall_5V)) - (pad 3 thru_hole rect (at -4.7 0 90) (size 2 2.6) (drill oval 1 1.6) (layers *.Cu *.Mask) - (net 189 "Net-(J4-Pad3)")) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6F9) - (at 72.9 97.79) - (path /5E7872D3/5E9DB598) - (attr smd) - (fp_text reference Q4 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Alt PFET_B" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6DD) - (at 68.2 97.79) - (path /5E7872D3/5E9CBFD6) - (attr smd) - (fp_text reference Q3 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Default PFET_B" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6C1) - (at 63.5 102.74) - (path /5E7872D3/5E9D56A5) - (attr smd) - (fp_text reference Q2 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Alt PFET_A" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6A5) - (at 69.85 82.55) - (path /5E7872D3/5E9B8E9E) - (attr smd) - (fp_text reference Q1 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Default PFET_A" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 172 /s_Power/USB_5v) (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - ) - - (module Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm (layer F.Cu) (tedit 5A64E13E) (tstamp 5E7A9FEB) - (at 80.01 71.12) - (descr "6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)") - (tags "DFN 0.65") - (path /5E7872D3/5E7F2428) - (attr smd) - (fp_text reference U4 (at 0 -2.025) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value NCP349MNAETBG (at 0 2.025) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -1.45 -1.1) (end 0.725 -1.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -0.725 1.1) (end 0.725 1.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.65 1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.65 -1.25) (end 1.65 -1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.65 -1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.65 -1.25) (end -1.65 1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1 0) (end 0 -1) (layer F.Fab) (width 0.15)) - (fp_line (start -1 1) (end -1 0) (layer F.Fab) (width 0.15)) - (fp_line (start 1 1) (end -1 1) (layer F.Fab) (width 0.15)) - (fp_line (start 1 -1) (end 1 1) (layer F.Fab) (width 0.15)) - (fp_line (start 0 -1) (end 1 -1) (layer F.Fab) (width 0.15)) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.075))) - ) - (pad "" smd rect (at 0 0.4) (size 0.82 0.63) (layers F.Paste)) - (pad "" smd rect (at 0 -0.4) (size 0.82 0.63) (layers F.Paste)) - (pad 7 smd rect (at 0 0) (size 1 1.6) (layers F.Cu F.Mask)) - (pad 6 smd rect (at 1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 179 "Net-(U4-Pad5)")) - (pad 5 smd rect (at 1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 179 "Net-(U4-Pad5)")) - (pad 4 smd rect (at 1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 3 smd rect (at -1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 180 "Net-(U4-Pad3)")) - (pad 2 smd rect (at -1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 1 smd rect (at -1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 183 "Net-(C10-Pad1)")) - (model ${KISYS3DMOD}/Package_DFN_QFN.3dshapes/DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical (layer F.Cu) (tedit 59FED6E3) (tstamp 5E75429F) - (at 128.27 83.82) - (descr "Through hole straight pin header, 2x05, 1.27mm pitch, double rows") - (tags "Through hole pin header THT 2x05 1.27mm double row") - (path /5E805E4F/5EA1E350) - (fp_text reference J2 (at 0.635 -1.695) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Conn_ARM_JTAG_SWD_10 (at 0.635 6.775) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user %R (at 0.635 2.54 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 2.85 -1.15) (end -1.6 -1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start 2.85 6.25) (end 2.85 -1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.6 6.25) (end 2.85 6.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.6 -1.15) (end -1.6 6.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.13 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 0) (end -1.13 -0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.57753 -0.695) (end 2.4 -0.695) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.76 -0.695) (end 0.96247 -0.695) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.76 -0.563471) (end 0.76 -0.695) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.76 0.706529) (end 0.76 0.563471) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.563471 0.76) (end 0.706529 0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start 2.4 -0.695) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 0.76) (end -1.13 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.30753 5.775) (end 0.96247 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.57753 5.775) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 5.775) (end -0.30753 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.07 0.2175) (end -0.2175 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start -1.07 5.715) (end -1.07 0.2175) (layer F.Fab) (width 0.1)) - (fp_line (start 2.34 5.715) (end -1.07 5.715) (layer F.Fab) (width 0.1)) - (fp_line (start 2.34 -0.635) (end 2.34 5.715) (layer F.Fab) (width 0.1)) - (fp_line (start -0.2175 -0.635) (end 2.34 -0.635) (layer F.Fab) (width 0.1)) - (pad 10 thru_hole oval (at 1.27 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 184 /s_BRAIN/~SYS_RST)) - (pad 9 thru_hole oval (at 0 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 8 thru_hole oval (at 1.27 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 2 "Net-(J2-Pad8)")) - (pad 7 thru_hole oval (at 0 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 3 "Net-(J2-Pad7)")) - (pad 6 thru_hole oval (at 1.27 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 185 /s_BRAIN/SWO)) - (pad 5 thru_hole oval (at 0 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 4 thru_hole oval (at 1.27 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 186 /s_BRAIN/SWCLK)) - (pad 3 thru_hole oval (at 0 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 2 thru_hole oval (at 1.27 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 187 /s_BRAIN/SWDIO)) - (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 4 "Net-(J2-Pad1)")) - (model ${KISYS3DMOD}/Connector_PinHeader_1.27mm.3dshapes/PinHeader_2x05_P1.27mm_Vertical.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm (layer F.Cu) (tedit 5A0FD1B2) (tstamp 5E752FF8) - (at 63.5 86.36) - (descr "SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf") - (tags "SMD SMT Crystal") - (path /5E805E4F/5E75D825) - (attr smd) - (fp_text reference Y1 (at 0 -2) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value XOSC32 (at 0 2) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 2 -1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -2 -1.15) (end -2 1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -2 1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.6 0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) - (fp_line (start -1.6 -0.75) (end 1.6 -0.75) (layer F.Fab) (width 0.1)) - (fp_line (start 1.6 -0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) - (fp_line (start -0.675 -0.875) (end 0.675 -0.875) (layer F.SilkS) (width 0.12)) - (fp_line (start -0.675 0.875) (end 0.675 0.875) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.6 -0.75) (end -1.6 0.75) (layer F.Fab) (width 0.1)) - (fp_line (start -2 -1.15) (end 2 -1.15) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 -2) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 2 smd rect (at -1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) - (net 55 "Net-(C1-Pad2)")) - (pad 1 smd rect (at 1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) - (net 131 "Net-(C2-Pad1)")) - (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_3215-2Pin_3.2x1.5mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module proj_modules:SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418) (tstamp 5E752FE7) - (at 106.68 77.47) - (path /5E8589A7/5E86D6D7) - (fp_text reference U3 (at -2.415 -8.587) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.015))) - ) - (fp_text value MAX7301AAX+ (at 5.84 8.587) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.015))) - ) - (fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127)) - (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2)) - (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2)) - (pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 122 g_3v3)) - (pad 35 smd rect (at 4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS)) - (pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 178 /MASTER_SPI_MOSI)) - (pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 175 /MASTER_SPI_CLK)) - (pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 123 "Net-(U3-Pad32)")) - (pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 124 "Net-(U3-Pad31)")) - (pad 30 smd rect (at 4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 125 "Net-(U3-Pad30)")) - (pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 126 "Net-(U3-Pad29)")) - (pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 137 /s_SCREEN_INTF/D23)) - (pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 138 /s_SCREEN_INTF/D22)) - (pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 139 /s_SCREEN_INTF/D21)) - (pad 25 smd rect (at 4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 140 /s_SCREEN_INTF/D20)) - (pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 141 /s_SCREEN_INTF/D19)) - (pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 142 /s_SCREEN_INTF/D18)) - (pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 143 /s_SCREEN_INTF/D17)) - (pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 144 /s_SCREEN_INTF/D16)) - (pad 20 smd rect (at 4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 145 /s_SCREEN_INTF/D15)) - (pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 146 /s_SCREEN_INTF/D14)) - (pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 147 /s_SCREEN_INTF/D13)) - (pad 17 smd rect (at -4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 148 /s_SCREEN_INTF/D12)) - (pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 149 /s_SCREEN_INTF/D11)) - (pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 150 /s_SCREEN_INTF/D10)) - (pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 151 /s_SCREEN_INTF/D9)) - (pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 152 /s_SCREEN_INTF/D8)) - (pad 12 smd rect (at -4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 153 /s_SCREEN_INTF/D7)) - (pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 154 /s_SCREEN_INTF/D6)) - (pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 155 /s_SCREEN_INTF/D5)) - (pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 156 /s_SCREEN_INTF/D4)) - (pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 157 /s_SCREEN_INTF/D3)) - (pad 7 smd rect (at -4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 158 /s_SCREEN_INTF/D2)) - (pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 159 /s_SCREEN_INTF/D1)) - (pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 160 /s_SCREEN_INTF/D0)) - (pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 174 /MASTER_SPI_MISO)) - (pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 2 smd rect (at -4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 128 "Net-(R1-Pad1)")) - ) - - (module digikey-footprints:QFN-32-1EP_5x5mm (layer F.Cu) (tedit 5D2895FE) (tstamp 5E752FB3) - (at 71.12 73.66) - (path /5E7C0F59/5E84744C) - (attr smd) - (fp_text reference U2 (at 0 -4.71) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value FT232RQ-REEL (at 0 4.51) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 1.98 2.05) (end -3.02 2.05) (layer F.Fab) (width 0.1)) - (fp_line (start 1.98 -2.95) (end 1.98 2.05) (layer F.Fab) (width 0.1)) - (fp_line (start 2.08 2.15) (end 1.68 2.15) (layer F.SilkS) (width 0.1)) - (fp_line (start 2.08 1.75) (end 2.08 2.15) (layer F.SilkS) (width 0.1)) - (fp_line (start 2.08 -3.05) (end 2.08 -2.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 2.08 -3.05) (end 1.68 -3.05) (layer F.SilkS) (width 0.1)) - (fp_line (start -3.12 2.15) (end -3.12 1.75) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.72 2.15) (end -3.12 2.15) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.62 -2.95) (end -3.02 -2.55) (layer F.Fab) (width 0.1)) - (fp_line (start -3.02 -2.55) (end -3.02 2.05) (layer F.Fab) (width 0.1)) - (fp_line (start -2.62 -2.95) (end 1.98 -2.95) (layer F.Fab) (width 0.1)) - (fp_line (start -3.12 -2.45) (end -3.32 -2.45) (layer F.SilkS) (width 0.1)) - (fp_line (start -3.12 -2.65) (end -3.12 -2.45) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.72 -3.05) (end -3.12 -2.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.52 -3.05) (end -2.72 -3.05) (layer F.SilkS) (width 0.1)) - (fp_text user %R (at -0.52 -0.45) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 2.61 2.68) (end -3.65 2.68) (layer F.CrtYd) (width 0.05)) - (fp_line (start 2.61 -3.58) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) - (fp_line (start 2.61 -3.58) (end 2.61 2.68) (layer F.CrtYd) (width 0.05)) - (fp_line (start -3.65 2.68) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) - (pad 32 smd rect (at -2.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 103 "Net-(U2-Pad32)") (solder_mask_margin 0.07)) - (pad 31 smd rect (at -1.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 104 "Net-(U2-Pad31)") (solder_mask_margin 0.07)) - (pad 30 smd rect (at -1.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 134 /DEBUG_RX) (solder_mask_margin 0.07)) - (pad 29 smd rect (at -0.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 105 "Net-(U2-Pad29)") (solder_mask_margin 0.07)) - (pad 28 smd rect (at -0.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 106 "Net-(U2-Pad28)") (solder_mask_margin 0.07)) - (pad 27 smd rect (at 0.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 107 "Net-(U2-Pad27)") (solder_mask_margin 0.07)) - (pad 26 smd rect (at 0.73 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 24 smd rect (at 1.955 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 23 smd rect (at 1.955 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 108 "Net-(U2-Pad23)") (solder_mask_margin 0.07)) - (pad 22 smd rect (at 1.955 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 109 "Net-(U2-Pad22)") (solder_mask_margin 0.07)) - (pad 21 smd rect (at 1.955 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 110 "Net-(U2-Pad21)") (solder_mask_margin 0.07)) - (pad 20 smd rect (at 1.955 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 19 smd rect (at 1.955 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 176 /s_USB_INTF.sch/FTDI_5V) (solder_mask_margin 0.07)) - (pad 18 smd rect (at 1.955 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 111 "Net-(U2-Pad18)") (solder_mask_margin 0.07)) - (pad 16 smd rect (at 1.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) - (pad 15 smd rect (at 0.73 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 130 /s_USB_INTF.sch/USB_D-) (solder_mask_margin 0.07)) - (pad 14 smd rect (at 0.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 129 /s_USB_INTF.sch/USB_D+) (solder_mask_margin 0.07)) - (pad 13 smd rect (at -0.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 112 "Net-(U2-Pad13)") (solder_mask_margin 0.07)) - (pad 12 smd rect (at -0.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 113 "Net-(U2-Pad12)") (solder_mask_margin 0.07)) - (pad 11 smd rect (at -1.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 114 "Net-(U2-Pad11)") (solder_mask_margin 0.07)) - (pad 10 smd rect (at -1.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 115 "Net-(U2-Pad10)") (solder_mask_margin 0.07)) - (pad 8 smd rect (at -2.995 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 116 "Net-(U2-Pad8)") (solder_mask_margin 0.07)) - (pad 7 smd rect (at -2.995 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 117 "Net-(U2-Pad7)") (solder_mask_margin 0.07)) - (pad 6 smd rect (at -2.995 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 118 "Net-(U2-Pad6)") (solder_mask_margin 0.07)) - (pad 5 smd rect (at -2.995 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 119 "Net-(U2-Pad5)") (solder_mask_margin 0.07)) - (pad 4 smd rect (at -2.995 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 3 smd rect (at -2.995 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 120 "Net-(U2-Pad3)") (solder_mask_margin 0.07)) - (pad 2 smd rect (at -2.995 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 135 /DEBUG_TX) (solder_mask_margin 0.07)) - (pad 1 smd rect (at -2.995 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) - (pad 33 thru_hole circle (at -1.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -1.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -1.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -0.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -0.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -0.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at 0.48 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at 0.48 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at 0.48 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 smd rect (at -0.52 -0.45 270) (size 3.45 3.45) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 9 smd rect (at -2.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) - (pad 17 smd rect (at 1.955 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 25 smd rect (at 1.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 121 "Net-(U2-Pad25)") (solder_mask_margin 0.07)) - ) - - (module penguin:QFP40P1600X1600X120-128N_ATSAME54P20A (layer F.Cu) (tedit 5E6D9777) (tstamp 5E752F71) - (at 90.17 109.22 45) - (path /5E7872D3/5E84F3B3) - (fp_text reference U1 (at -4.500975 -9.803025 45) (layer F.SilkS) - (effects (font (size 1.001331 1.001331) (thickness 0.015))) - ) - (fp_text value p_ATSAME54P20A-AU (at 6.78639 10.114365 45) (layer F.Fab) - (effects (font (size 1.002417 1.002417) (thickness 0.015))) - ) - (fp_line (start -7 7) (end -7 6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start -6.6 7) (end -7 7) (layer F.SilkS) (width 0.127)) - (fp_line (start 7 7) (end 7 6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.6 7) (end 7 7) (layer F.SilkS) (width 0.127)) - (fp_line (start 7 -7) (end 7 -6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.6 -7) (end 7 -7) (layer F.SilkS) (width 0.127)) - (fp_line (start -7 -7) (end -7 -6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start -6.6 -7) (end -7 -7) (layer F.SilkS) (width 0.127)) - (fp_line (start 8.655 8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -8.655 8.655) (end -8.655 -8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -8.655 -8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -8.655 8.655) (end 8.655 8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -7 7) (end -7 -7) (layer F.Fab) (width 0.127)) - (fp_line (start 7 7) (end 7 -7) (layer F.Fab) (width 0.127)) - (fp_line (start 7 -7) (end -7 -7) (layer F.Fab) (width 0.127)) - (fp_line (start 7 7) (end -7 7) (layer F.Fab) (width 0.127)) - (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.Fab) (width 0.1)) - (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.SilkS) (width 0.1)) - (pad 96 smd rect (at 7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 95 smd rect (at 7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 9 "Net-(U1-Pad95)")) - (pad 94 smd rect (at 7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 10 "Net-(U1-Pad94)")) - (pad 93 smd rect (at 7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 11 "Net-(U1-Pad93)")) - (pad 92 smd rect (at 7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 12 "Net-(U1-Pad92)")) - (pad 91 smd rect (at 7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 90 smd rect (at 7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 89 smd rect (at 7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 13 "Net-(U1-Pad89)")) - (pad 88 smd rect (at 7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 14 "Net-(U1-Pad88)")) - (pad 87 smd rect (at 7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 15 "Net-(U1-Pad87)")) - (pad 86 smd rect (at 7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 16 "Net-(U1-Pad86)")) - (pad 85 smd rect (at 7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 17 "Net-(U1-Pad85)")) - (pad 84 smd rect (at 7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 18 "Net-(U1-Pad84)")) - (pad 83 smd rect (at 7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 19 "Net-(U1-Pad83)")) - (pad 82 smd rect (at 7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 20 "Net-(U1-Pad82)")) - (pad 81 smd rect (at 7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 21 "Net-(U1-Pad81)")) - (pad 80 smd rect (at 7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 22 "Net-(U1-Pad80)")) - (pad 79 smd rect (at 7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 78 smd rect (at 7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 77 smd rect (at 7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 23 "Net-(U1-Pad77)")) - (pad 76 smd rect (at 7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 24 "Net-(U1-Pad76)")) - (pad 75 smd rect (at 7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 25 "Net-(U1-Pad75)")) - (pad 74 smd rect (at 7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 26 "Net-(U1-Pad74)")) - (pad 73 smd rect (at 7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 27 "Net-(U1-Pad73)")) - (pad 72 smd rect (at 7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 28 "Net-(U1-Pad72)")) - (pad 71 smd rect (at 7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 29 "Net-(U1-Pad71)")) - (pad 70 smd rect (at 7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 30 "Net-(U1-Pad70)")) - (pad 69 smd rect (at 7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 31 "Net-(U1-Pad69)")) - (pad 68 smd rect (at 7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 32 "Net-(U1-Pad68)")) - (pad 67 smd rect (at 7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 171 /MASTER_I2C_SCL)) - (pad 66 smd rect (at 7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 170 /MASTER_I2C_SDA)) - (pad 65 smd rect (at 7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 32 smd rect (at -7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 33 "Net-(U1-Pad32)")) - (pad 31 smd rect (at -7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 30 smd rect (at -7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 34 "Net-(U1-Pad30)")) - (pad 29 smd rect (at -7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 35 "Net-(U1-Pad29)")) - (pad 28 smd rect (at -7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 36 "Net-(U1-Pad28)")) - (pad 27 smd rect (at -7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 37 "Net-(U1-Pad27)")) - (pad 26 smd rect (at -7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 38 "Net-(U1-Pad26)")) - (pad 25 smd rect (at -7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 45 "Net-(U1-Pad14)")) - (pad 24 smd rect (at -7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 39 "Net-(U1-Pad24)")) - (pad 23 smd rect (at -7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 174 /MASTER_SPI_MISO)) - (pad 22 smd rect (at -7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 175 /MASTER_SPI_CLK)) - (pad 21 smd rect (at -7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 174 /MASTER_SPI_MISO)) - (pad 20 smd rect (at -7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 40 "Net-(U1-Pad20)")) - (pad 19 smd rect (at -7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 41 "Net-(U1-Pad19)")) - (pad 18 smd rect (at -7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 42 "Net-(U1-Pad18)")) - (pad 17 smd rect (at -7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 190 /s_BRAIN/EXT_IRQ_5)) - (pad 16 smd rect (at -7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 43 "Net-(U1-Pad16)")) - (pad 15 smd rect (at -7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 44 "Net-(U1-Pad15)")) - (pad 14 smd rect (at -7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 45 "Net-(U1-Pad14)")) - (pad 13 smd rect (at -7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 46 "Net-(U1-Pad13)")) - (pad 12 smd rect (at -7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 191 /s_BRAIN/EXT_IRQ_4)) - (pad 11 smd rect (at -7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 192 /s_BRAIN/EXT_IRQ_3)) - (pad 10 smd rect (at -7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 47 "Net-(U1-Pad10)")) - (pad 9 smd rect (at -7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 48 "Net-(U1-Pad9)")) - (pad 8 smd rect (at -7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 49 "Net-(U1-Pad8)")) - (pad 7 smd rect (at -7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 50 "Net-(U1-Pad7)")) - (pad 6 smd rect (at -7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 51 "Net-(U1-Pad6)")) - (pad 5 smd rect (at -7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 52 "Net-(U1-Pad5)")) - (pad 4 smd rect (at -7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 53 "Net-(U1-Pad4)")) - (pad 3 smd rect (at -7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 54 "Net-(U1-Pad3)")) - (pad 2 smd rect (at -7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 131 "Net-(C2-Pad1)")) - (pad 1 smd rect (at -7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 55 "Net-(C1-Pad2)")) - (pad 128 smd rect (at -6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 122 g_3v3)) - (pad 127 smd rect (at -5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 193 /s_BRAIN/EXT_IRQ_2)) - (pad 126 smd rect (at -5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 194 /s_BRAIN/EXT_IRQ_1)) - (pad 125 smd rect (at -5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 195 /s_BRAIN/EXT_IRQ_0)) - (pad 124 smd rect (at -4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 56 "Net-(U1-Pad124)")) - (pad 123 smd rect (at -4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 57 "Net-(U1-Pad123)")) - (pad 122 smd rect (at -3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 58 "Net-(U1-Pad122)")) - (pad 121 smd rect (at -3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 59 "Net-(U1-Pad121)")) - (pad 120 smd rect (at -3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 60 "Net-(U1-Pad120)")) - (pad 119 smd rect (at -2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 61 "Net-(U1-Pad119)")) - (pad 118 smd rect (at -2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 117 smd rect (at -1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 62 "Net-(U1-Pad117)")) - (pad 116 smd rect (at -1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 63 "Net-(U1-Pad116)")) - (pad 115 smd rect (at -1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 64 "Net-(U1-Pad115)")) - (pad 114 smd rect (at -0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 65 "Net-(U1-Pad114)")) - (pad 113 smd rect (at -0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 66 "Net-(U1-Pad113)")) - (pad 112 smd rect (at 0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 67 "Net-(U1-Pad112)")) - (pad 111 smd rect (at 0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 68 "Net-(U1-Pad111)")) - (pad 110 smd rect (at 1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 69 "Net-(U1-Pad110)")) - (pad 109 smd rect (at 1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 70 "Net-(U1-Pad109)")) - (pad 108 smd rect (at 1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 71 "Net-(U1-Pad108)")) - (pad 107 smd rect (at 2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 106 smd rect (at 2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 105 smd rect (at 3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 73 "Net-(U1-Pad105)")) - (pad 104 smd rect (at 3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 74 "Net-(U1-Pad104)")) - (pad 103 smd rect (at 3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 75 "Net-(U1-Pad103)")) - (pad 102 smd rect (at 4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 76 "Net-(U1-Pad102)")) - (pad 101 smd rect (at 4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 135 /DEBUG_TX)) - (pad 100 smd rect (at 5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 134 /DEBUG_RX)) - (pad 99 smd rect (at 5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 77 "Net-(U1-Pad99)")) - (pad 98 smd rect (at 5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 78 "Net-(U1-Pad98)")) - (pad 97 smd rect (at 6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 64 smd rect (at 6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 63 smd rect (at 5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 132 "Net-(C5-Pad2)")) - (pad 62 smd rect (at 5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 133 "Net-(C4-Pad2)")) - (pad 61 smd rect (at 5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 79 "Net-(U1-Pad61)")) - (pad 60 smd rect (at 4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 80 "Net-(U1-Pad60)")) - (pad 59 smd rect (at 4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 81 "Net-(U1-Pad59)")) - (pad 58 smd rect (at 3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 82 "Net-(U1-Pad58)")) - (pad 57 smd rect (at 3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 83 "Net-(U1-Pad57)")) - (pad 56 smd rect (at 3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 84 "Net-(U1-Pad56)")) - (pad 55 smd rect (at 2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 85 "Net-(U1-Pad55)")) - (pad 54 smd rect (at 2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 53 smd rect (at 1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 52 smd rect (at 1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 86 "Net-(U1-Pad52)")) - (pad 51 smd rect (at 1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 87 "Net-(U1-Pad51)")) - (pad 50 smd rect (at 0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 88 "Net-(U1-Pad50)")) - (pad 49 smd rect (at 0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 89 "Net-(U1-Pad49)")) - (pad 48 smd rect (at -0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 90 "Net-(U1-Pad48)")) - (pad 47 smd rect (at -0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 91 "Net-(U1-Pad47)")) - (pad 46 smd rect (at -1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 45 smd rect (at -1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 44 smd rect (at -1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 92 "Net-(U1-Pad44)")) - (pad 43 smd rect (at -2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 93 "Net-(U1-Pad43)")) - (pad 42 smd rect (at -2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 94 "Net-(U1-Pad42)")) - (pad 41 smd rect (at -3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 95 "Net-(U1-Pad41)")) - (pad 40 smd rect (at -3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 96 "Net-(U1-Pad40)")) - (pad 39 smd rect (at -3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 97 "Net-(U1-Pad39)")) - (pad 38 smd rect (at -4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 37 smd rect (at -4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 98 "Net-(U1-Pad37)")) - (pad 36 smd rect (at -5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 99 "Net-(U1-Pad36)")) - (pad 35 smd rect (at -5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 100 "Net-(U1-Pad35)")) - (pad 34 smd rect (at -5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 101 "Net-(U1-Pad34)")) - (pad 33 smd rect (at -6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 102 "Net-(U1-Pad33)")) - ) - - (module Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal (layer F.Cu) (tedit 59DE239E) (tstamp 5E752EDB) - (at 78.74 64.77 90) - (descr "Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows") - (tags "Through hole IDC box header THT 2x20 2.54mm double row") - (path /5E8589A7/5E858ED6) - (fp_text reference J3 (at 6.105 -6.35 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Conn_02x20_Odd_Even_LCD_INTF (at 6.105 54.864 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 13.48 53.61) (end -1.12 53.61) (layer F.CrtYd) (width 0.05)) - (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.12 53.61) (end -1.12 -5.35) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.12 -5.35) (end 13.48 -5.35) (layer F.CrtYd) (width 0.05)) - (fp_line (start 4.13 53.61) (end 4.13 -5.35) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 53.61) (end 13.48 53.61) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 26.38) (end 13.48 26.38) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 21.88) (end 13.48 21.88) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 -5.35) (end 13.48 -5.35) (layer F.SilkS) (width 0.12)) - (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.SilkS) (width 0.12)) - (fp_line (start 0 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.27 -1.27) (end -1.27 0) (layer F.SilkS) (width 0.12)) - (fp_line (start 5.38 -5.1) (end 13.23 -5.1) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 9.84) (end -0.32 9.84) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 7.3) (end -0.32 7.3) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 53.36) (end 4.38 -4.1) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 53.36) (end 13.23 53.36) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 47.94) (end -0.32 47.94) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 45.4) (end -0.32 45.4) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 42.86) (end -0.32 42.86) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 40.32) (end -0.32 40.32) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 4.76) (end -0.32 4.76) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 37.78) (end -0.32 37.78) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 35.24) (end -0.32 35.24) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 32.7) (end -0.32 32.7) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 30.16) (end -0.32 30.16) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 27.62) (end -0.32 27.62) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 26.38) (end 13.23 26.38) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 25.08) (end -0.32 25.08) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 22.54) (end -0.32 22.54) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 21.88) (end 13.23 21.88) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 20) (end -0.32 20) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 2.22) (end -0.32 2.22) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 17.46) (end -0.32 17.46) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 14.92) (end -0.32 14.92) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 12.38) (end -0.32 12.38) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 -4.1) (end 5.38 -5.1) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 -0.32) (end -0.32 -0.32) (layer F.Fab) (width 0.1)) - (fp_line (start 13.23 53.36) (end 13.23 -5.1) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 9.84) (end -0.32 10.48) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 7.94) (end 4.38 7.94) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 7.3) (end -0.32 7.94) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 5.4) (end 4.38 5.4) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 48.58) (end 4.38 48.58) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 47.94) (end -0.32 48.58) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 46.04) (end 4.38 46.04) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 45.4) (end -0.32 46.04) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 43.5) (end 4.38 43.5) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 42.86) (end -0.32 43.5) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 40.96) (end 4.38 40.96) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 40.32) (end -0.32 40.96) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 4.76) (end -0.32 5.4) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 38.42) (end 4.38 38.42) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 37.78) (end -0.32 38.42) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 35.88) (end 4.38 35.88) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 35.24) (end -0.32 35.88) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 33.34) (end 4.38 33.34) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 32.7) (end -0.32 33.34) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 30.8) (end 4.38 30.8) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 30.16) (end -0.32 30.8) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 28.26) (end 4.38 28.26) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 27.62) (end -0.32 28.26) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 25.72) (end 4.38 25.72) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 25.08) (end -0.32 25.72) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 23.18) (end 4.38 23.18) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 22.54) (end -0.32 23.18) (layer F.Fab) (width 0.1)) - (fp_line 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F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 40 thru_hole oval (at 2.54 48.26 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 5 "Net-(J3-Pad40)")) - (pad 39 thru_hole oval (at 0 48.26 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 6 "Net-(J3-Pad39)")) - (pad 38 thru_hole oval (at 2.54 45.72 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 7 "Net-(J3-Pad38)")) - (pad 37 thru_hole oval (at 0 45.72 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 136 /s_SCREEN_INTF/TFT_STB)) - (pad 36 thru_hole oval (at 2.54 43.18 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 137 /s_SCREEN_INTF/D23)) - (pad 35 thru_hole oval (at 0 43.18 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 138 /s_SCREEN_INTF/D22)) - (pad 34 thru_hole oval (at 2.54 40.64 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 139 /s_SCREEN_INTF/D21)) - (pad 33 thru_hole oval (at 0 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"Net-(U1-Pad109)") + (net 71 "Net-(U1-Pad108)") + (net 72 "Net-(U1-Pad107)") + (net 73 "Net-(U1-Pad105)") + (net 74 "Net-(U1-Pad104)") + (net 75 "Net-(U1-Pad103)") + (net 76 "Net-(U1-Pad102)") + (net 77 "Net-(U1-Pad99)") + (net 78 "Net-(U1-Pad98)") + (net 79 "Net-(U1-Pad61)") + (net 80 "Net-(U1-Pad60)") + (net 81 "Net-(U1-Pad59)") + (net 82 "Net-(U1-Pad58)") + (net 83 "Net-(U1-Pad57)") + (net 84 "Net-(U1-Pad56)") + (net 85 "Net-(U1-Pad55)") + (net 86 "Net-(U1-Pad52)") + (net 87 "Net-(U1-Pad51)") + (net 88 "Net-(U1-Pad50)") + (net 89 "Net-(U1-Pad49)") + (net 90 "Net-(U1-Pad48)") + (net 91 "Net-(U1-Pad47)") + (net 92 "Net-(U1-Pad44)") + (net 93 "Net-(U1-Pad43)") + (net 94 "Net-(U1-Pad42)") + (net 95 "Net-(U1-Pad41)") + (net 96 "Net-(U1-Pad40)") + (net 97 "Net-(U1-Pad39)") + (net 98 "Net-(U1-Pad37)") + (net 99 "Net-(U1-Pad36)") + (net 100 "Net-(U1-Pad35)") + (net 101 "Net-(U1-Pad34)") + (net 102 "Net-(U1-Pad33)") + (net 103 "Net-(U2-Pad32)") + (net 104 "Net-(U2-Pad31)") + (net 105 "Net-(U2-Pad29)") + (net 106 "Net-(U2-Pad28)") + (net 107 "Net-(U2-Pad27)") + (net 108 "Net-(U2-Pad23)") + (net 109 "Net-(U2-Pad22)") + (net 110 "Net-(U2-Pad21)") + (net 111 "Net-(U2-Pad18)") + (net 112 "Net-(U2-Pad13)") + (net 113 "Net-(U2-Pad12)") + (net 114 "Net-(U2-Pad11)") + (net 115 "Net-(U2-Pad10)") + (net 116 "Net-(U2-Pad8)") + (net 117 "Net-(U2-Pad7)") + (net 118 "Net-(U2-Pad6)") + (net 119 "Net-(U2-Pad5)") + (net 120 "Net-(U2-Pad3)") + (net 121 "Net-(U2-Pad25)") + (net 122 g_3v3) + (net 123 "Net-(U3-Pad32)") + (net 124 "Net-(U3-Pad31)") + (net 125 "Net-(U3-Pad30)") + (net 126 "Net-(U3-Pad29)") + (net 127 GND) + (net 128 "Net-(R1-Pad1)") + (net 129 /s_USB_INTF.sch/USB_D+) + (net 130 /s_USB_INTF.sch/USB_D-) + (net 131 "Net-(C2-Pad1)") + (net 132 "Net-(C5-Pad2)") + (net 133 "Net-(C4-Pad2)") + (net 134 /DEBUG_RX) + (net 135 /DEBUG_TX) + (net 136 /s_SCREEN_INTF/TFT_STB) + (net 137 /s_SCREEN_INTF/D23) + (net 138 /s_SCREEN_INTF/D22) + (net 139 /s_SCREEN_INTF/D21) + (net 140 /s_SCREEN_INTF/D20) + (net 141 /s_SCREEN_INTF/D19) + (net 142 /s_SCREEN_INTF/D18) + (net 143 /s_SCREEN_INTF/D17) + (net 144 /s_SCREEN_INTF/D16) + (net 145 /s_SCREEN_INTF/D15) + (net 146 /s_SCREEN_INTF/D14) + (net 147 /s_SCREEN_INTF/D13) + (net 148 /s_SCREEN_INTF/D12) + (net 149 /s_SCREEN_INTF/D11) + (net 150 /s_SCREEN_INTF/D10) + (net 151 /s_SCREEN_INTF/D9) + (net 152 /s_SCREEN_INTF/D8) + (net 153 /s_SCREEN_INTF/D7) + (net 154 /s_SCREEN_INTF/D6) + (net 155 /s_SCREEN_INTF/D5) + (net 156 /s_SCREEN_INTF/D4) + (net 157 /s_SCREEN_INTF/D3) + (net 158 /s_SCREEN_INTF/D2) + (net 159 /s_SCREEN_INTF/D1) + (net 160 /s_SCREEN_INTF/D0) + (net 161 /s_SCREEN_INTF/TFT_TE) + (net 162 /s_SCREEN_INTF/~TFT_RD) + (net 163 /s_SCREEN_INTF/~TFT_WR) + (net 164 /s_SCREEN_INTF/TFT_RSDC) + (net 165 /s_SCREEN_INTF/~TFT_RST) + (net 166 /s_SCREEN_INTF/TFT_TOUCH_INT) + (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS) + (net 168 "Net-(C7-Pad1)") + (net 169 /~TFT_CS) + (net 170 /MASTER_I2C_SDA) + (net 171 /MASTER_I2C_SCL) + (net 172 /s_Power/USB_5v) + (net 173 /s_Power/USB_3v3) + (net 174 /MASTER_SPI_MISO) + (net 175 /MASTER_SPI_CLK) + (net 176 /s_USB_INTF.sch/FTDI_5V) + (net 177 /s_USB_INTF.sch/FTDI_3V3) + (net 178 /MASTER_SPI_MOSI) + (net 179 "Net-(U4-Pad5)") + (net 180 "Net-(U4-Pad3)") + (net 181 "Net-(Q1-Pad3)") + (net 182 "Net-(Q2-Pad3)") + (net 183 "Net-(C10-Pad1)") + (net 184 /s_BRAIN/~SYS_RST) + (net 185 /s_BRAIN/SWO) + (net 186 /s_BRAIN/SWCLK) + (net 187 /s_BRAIN/SWDIO) + (net 188 /s_Power/Wall_5V) + (net 189 "Net-(J4-Pad3)") + (net 190 /s_BRAIN/EXT_IRQ_5) + (net 191 /s_BRAIN/EXT_IRQ_4) + (net 192 /s_BRAIN/EXT_IRQ_3) + (net 193 /s_BRAIN/EXT_IRQ_2) + (net 194 /s_BRAIN/EXT_IRQ_1) + (net 195 /s_BRAIN/EXT_IRQ_0) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net /DEBUG_RX) + (add_net /DEBUG_TX) + (add_net /MASTER_I2C_SCL) + (add_net /MASTER_I2C_SDA) + (add_net /MASTER_SPI_CLK) + (add_net /MASTER_SPI_MISO) + (add_net /MASTER_SPI_MOSI) + (add_net /s_BRAIN/EXT_IRQ_0) + (add_net /s_BRAIN/EXT_IRQ_1) + (add_net /s_BRAIN/EXT_IRQ_2) + (add_net /s_BRAIN/EXT_IRQ_3) + (add_net /s_BRAIN/EXT_IRQ_4) + (add_net /s_BRAIN/EXT_IRQ_5) + (add_net /s_BRAIN/SWCLK) + (add_net /s_BRAIN/SWDIO) + (add_net /s_BRAIN/SWO) + (add_net /s_BRAIN/~SYS_RST) + (add_net /s_Power/USB_3v3) + (add_net /s_Power/USB_5v) + (add_net /s_Power/Wall_5V) + (add_net /s_SCREEN_INTF/D0) + (add_net /s_SCREEN_INTF/D1) + (add_net /s_SCREEN_INTF/D10) + (add_net /s_SCREEN_INTF/D11) + (add_net /s_SCREEN_INTF/D12) + (add_net /s_SCREEN_INTF/D13) + (add_net /s_SCREEN_INTF/D14) + (add_net /s_SCREEN_INTF/D15) + (add_net /s_SCREEN_INTF/D16) + (add_net /s_SCREEN_INTF/D17) + (add_net /s_SCREEN_INTF/D18) + (add_net /s_SCREEN_INTF/D19) + (add_net /s_SCREEN_INTF/D2) + (add_net /s_SCREEN_INTF/D20) + (add_net /s_SCREEN_INTF/D21) + (add_net /s_SCREEN_INTF/D22) + (add_net /s_SCREEN_INTF/D23) + (add_net /s_SCREEN_INTF/D3) + (add_net /s_SCREEN_INTF/D4) + (add_net /s_SCREEN_INTF/D5) + (add_net /s_SCREEN_INTF/D6) + (add_net /s_SCREEN_INTF/D7) + (add_net /s_SCREEN_INTF/D8) + (add_net /s_SCREEN_INTF/D9) + (add_net /s_SCREEN_INTF/TFT_RSDC) + (add_net /s_SCREEN_INTF/TFT_STB) + (add_net /s_SCREEN_INTF/TFT_TE) + (add_net /s_SCREEN_INTF/TFT_TOUCH_INT) + (add_net /s_SCREEN_INTF/~IO_EXPANDER_CS) + (add_net /s_SCREEN_INTF/~TFT_RD) + (add_net /s_SCREEN_INTF/~TFT_RST) + (add_net /s_SCREEN_INTF/~TFT_WR) + (add_net /s_USB_INTF.sch/FTDI_3V3) + (add_net /s_USB_INTF.sch/FTDI_5V) + (add_net /s_USB_INTF.sch/USB_D+) + (add_net /s_USB_INTF.sch/USB_D-) + (add_net /~TFT_CS) + (add_net GND) + (add_net "Net-(C1-Pad2)") + (add_net "Net-(C10-Pad1)") + (add_net "Net-(C2-Pad1)") + (add_net "Net-(C4-Pad2)") + (add_net "Net-(C5-Pad2)") + (add_net "Net-(C7-Pad1)") + (add_net "Net-(J1-Pad4)") + (add_net "Net-(J2-Pad1)") + (add_net "Net-(J2-Pad7)") + (add_net "Net-(J2-Pad8)") + (add_net "Net-(J3-Pad38)") + (add_net "Net-(J3-Pad39)") + (add_net "Net-(J3-Pad40)") + (add_net "Net-(J3-Pad6)") + (add_net "Net-(J4-Pad3)") + (add_net "Net-(Q1-Pad3)") + (add_net "Net-(Q2-Pad3)") + (add_net "Net-(R1-Pad1)") + (add_net "Net-(U1-Pad10)") + (add_net "Net-(U1-Pad102)") + (add_net "Net-(U1-Pad103)") + (add_net "Net-(U1-Pad104)") + (add_net "Net-(U1-Pad105)") + (add_net "Net-(U1-Pad107)") + (add_net "Net-(U1-Pad108)") + (add_net "Net-(U1-Pad109)") + (add_net "Net-(U1-Pad110)") + (add_net "Net-(U1-Pad111)") + (add_net "Net-(U1-Pad112)") + (add_net "Net-(U1-Pad113)") + (add_net "Net-(U1-Pad114)") + (add_net "Net-(U1-Pad115)") + (add_net "Net-(U1-Pad116)") + (add_net "Net-(U1-Pad117)") + (add_net "Net-(U1-Pad119)") + (add_net "Net-(U1-Pad120)") + (add_net "Net-(U1-Pad121)") + (add_net "Net-(U1-Pad122)") + (add_net "Net-(U1-Pad123)") + (add_net "Net-(U1-Pad124)") + (add_net "Net-(U1-Pad13)") + (add_net "Net-(U1-Pad14)") + (add_net "Net-(U1-Pad15)") + (add_net "Net-(U1-Pad16)") + (add_net "Net-(U1-Pad18)") + (add_net "Net-(U1-Pad19)") + (add_net "Net-(U1-Pad20)") + (add_net "Net-(U1-Pad24)") + (add_net "Net-(U1-Pad26)") + (add_net "Net-(U1-Pad27)") + (add_net "Net-(U1-Pad28)") + (add_net "Net-(U1-Pad29)") + (add_net "Net-(U1-Pad3)") + (add_net "Net-(U1-Pad30)") + (add_net "Net-(U1-Pad32)") + (add_net "Net-(U1-Pad33)") + (add_net "Net-(U1-Pad34)") + (add_net "Net-(U1-Pad35)") + (add_net "Net-(U1-Pad36)") + (add_net "Net-(U1-Pad37)") + (add_net "Net-(U1-Pad39)") + (add_net "Net-(U1-Pad4)") + (add_net "Net-(U1-Pad40)") + (add_net "Net-(U1-Pad41)") + (add_net "Net-(U1-Pad42)") + (add_net "Net-(U1-Pad43)") + (add_net "Net-(U1-Pad44)") + (add_net "Net-(U1-Pad47)") + (add_net "Net-(U1-Pad48)") + (add_net "Net-(U1-Pad49)") + (add_net "Net-(U1-Pad5)") + (add_net "Net-(U1-Pad50)") + (add_net "Net-(U1-Pad51)") + (add_net "Net-(U1-Pad52)") + (add_net "Net-(U1-Pad55)") + (add_net "Net-(U1-Pad56)") + (add_net "Net-(U1-Pad57)") + (add_net "Net-(U1-Pad58)") + (add_net "Net-(U1-Pad59)") + (add_net "Net-(U1-Pad6)") + (add_net "Net-(U1-Pad60)") + (add_net "Net-(U1-Pad61)") + (add_net "Net-(U1-Pad68)") + (add_net "Net-(U1-Pad69)") + (add_net "Net-(U1-Pad7)") + (add_net "Net-(U1-Pad70)") + (add_net "Net-(U1-Pad71)") + (add_net "Net-(U1-Pad72)") + (add_net "Net-(U1-Pad73)") + (add_net "Net-(U1-Pad74)") + (add_net "Net-(U1-Pad75)") + (add_net "Net-(U1-Pad76)") + (add_net "Net-(U1-Pad77)") + (add_net "Net-(U1-Pad8)") + (add_net "Net-(U1-Pad80)") + (add_net "Net-(U1-Pad81)") + (add_net "Net-(U1-Pad82)") + (add_net "Net-(U1-Pad83)") + (add_net "Net-(U1-Pad84)") + (add_net "Net-(U1-Pad85)") + (add_net "Net-(U1-Pad86)") + (add_net "Net-(U1-Pad87)") + (add_net "Net-(U1-Pad88)") + (add_net "Net-(U1-Pad89)") + (add_net "Net-(U1-Pad9)") + (add_net "Net-(U1-Pad92)") + (add_net "Net-(U1-Pad93)") + (add_net "Net-(U1-Pad94)") + (add_net "Net-(U1-Pad95)") + (add_net "Net-(U1-Pad98)") + (add_net "Net-(U1-Pad99)") + (add_net "Net-(U2-Pad10)") + (add_net "Net-(U2-Pad11)") + (add_net "Net-(U2-Pad12)") + (add_net "Net-(U2-Pad13)") + (add_net "Net-(U2-Pad18)") + (add_net "Net-(U2-Pad21)") + (add_net "Net-(U2-Pad22)") + (add_net "Net-(U2-Pad23)") + (add_net "Net-(U2-Pad25)") + (add_net "Net-(U2-Pad27)") + (add_net "Net-(U2-Pad28)") + (add_net "Net-(U2-Pad29)") + (add_net "Net-(U2-Pad3)") + (add_net "Net-(U2-Pad31)") + (add_net "Net-(U2-Pad32)") + (add_net "Net-(U2-Pad5)") + (add_net "Net-(U2-Pad6)") + (add_net "Net-(U2-Pad7)") + (add_net "Net-(U2-Pad8)") + (add_net "Net-(U3-Pad29)") + (add_net "Net-(U3-Pad30)") + (add_net "Net-(U3-Pad31)") + (add_net "Net-(U3-Pad32)") + (add_net "Net-(U4-Pad3)") + (add_net "Net-(U4-Pad5)") + (add_net g_3v3) + ) + + (module digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A (layer F.Cu) (tedit 5CAD146F) (tstamp 5E7AD729) + (at 62.23 60.96 90) + (path /5E7872D3/5E88DD8C) + (fp_text reference J4 (at 0 -12.1 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Barrel_Jack_Switch (at 0 5.8 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -4.5 3.7) (end 4.5 3.7) (layer F.Fab) (width 0.1)) + (fp_line (start -4.5 3.7) (end -4.5 -10.7) (layer F.Fab) (width 0.1)) + (fp_line (start 4.5 3.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) + (fp_line (start -4.5 -10.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) + (fp_line (start 4.6 3.8) (end 4.1 3.8) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 3.8) (end 4.6 3.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 3.8) (end -4.1 3.8) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 3.8) (end -4.6 3.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -1.2 -1.8) (end 1.2 -1.8) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 -10.8) (end -4.6 -10.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 -10.8) (end -4.1 -10.8) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 -10.8) (end 4.1 -10.8) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 -10.8) (end 4.6 -10.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 -3.5) (end -4.6 -4.5) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 -3.5) (end 4.6 -4.5) (layer F.SilkS) (width 0.1)) + (fp_line (start -5.9 -10.95) (end 4.8 -10.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.9 -10.95) (end -5.9 4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.8 -10.95) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.9 4.25) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) + (pad 2 thru_hole rect (at 0 -3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 1 thru_hole rect (at 0 3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) + (net 188 /s_Power/Wall_5V)) + (pad 3 thru_hole rect (at -4.7 0 90) (size 2 2.6) (drill oval 1 1.6) (layers *.Cu *.Mask) + (net 189 "Net-(J4-Pad3)")) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6F9) + (at 72.9 97.79) + (path /5E7872D3/5E9DB598) + (attr smd) + (fp_text reference Q4 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Alt PFET_B" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6DD) + (at 68.2 97.79) + (path /5E7872D3/5E9CBFD6) + (attr smd) + (fp_text reference Q3 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Default PFET_B" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6C1) + (at 63.5 102.74) + (path /5E7872D3/5E9D56A5) + (attr smd) + (fp_text reference Q2 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Alt PFET_A" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6A5) + (at 69.85 82.55) + (path /5E7872D3/5E9B8E9E) + (attr smd) + (fp_text reference Q1 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Default PFET_A" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 172 /s_Power/USB_5v) (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + ) + + (module Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm (layer F.Cu) (tedit 5A64E13E) (tstamp 5E7A9FEB) + (at 80.01 71.12) + (descr "6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "DFN 0.65") + (path /5E7872D3/5E7F2428) + (attr smd) + (fp_text reference U4 (at 0 -2.025) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value NCP349MNAETBG (at 0 2.025) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.45 -1.1) (end 0.725 -1.1) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.725 1.1) (end 0.725 1.1) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.65 1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.65 -1.25) (end 1.65 -1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.65 -1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.65 -1.25) (end -1.65 1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0) (end 0 -1) (layer F.Fab) (width 0.15)) + (fp_line (start -1 1) (end -1 0) (layer F.Fab) (width 0.15)) + (fp_line (start 1 1) (end -1 1) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -1) (end 1 1) (layer F.Fab) (width 0.15)) + (fp_line (start 0 -1) (end 1 -1) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.075))) + ) + (pad "" smd rect (at 0 0.4) (size 0.82 0.63) (layers F.Paste)) + (pad "" smd rect (at 0 -0.4) (size 0.82 0.63) (layers F.Paste)) + (pad 7 smd rect (at 0 0) (size 1 1.6) (layers F.Cu F.Mask)) + (pad 6 smd rect (at 1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 179 "Net-(U4-Pad5)")) + (pad 5 smd rect (at 1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 179 "Net-(U4-Pad5)")) + (pad 4 smd rect (at 1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 3 smd rect (at -1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 180 "Net-(U4-Pad3)")) + (pad 2 smd rect (at -1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 1 smd rect (at -1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(C10-Pad1)")) + (model ${KISYS3DMOD}/Package_DFN_QFN.3dshapes/DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical (layer F.Cu) (tedit 59FED6E3) (tstamp 5E75429F) + (at 128.27 83.82) + (descr "Through hole straight pin header, 2x05, 1.27mm pitch, double rows") + (tags "Through hole pin header THT 2x05 1.27mm double row") + (path /5E805E4F/5EA1E350) + (fp_text reference J2 (at 0.635 -1.695) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_ARM_JTAG_SWD_10 (at 0.635 6.775) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0.635 2.54 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.85 -1.15) (end -1.6 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.85 6.25) (end 2.85 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 6.25) (end 2.85 6.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 -1.15) (end -1.6 6.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.13 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 0) (end -1.13 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.57753 -0.695) (end 2.4 -0.695) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.76 -0.695) (end 0.96247 -0.695) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.76 -0.563471) (end 0.76 -0.695) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.76 0.706529) (end 0.76 0.563471) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.563471 0.76) (end 0.706529 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.4 -0.695) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 0.76) (end -1.13 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.30753 5.775) (end 0.96247 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.57753 5.775) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 5.775) (end -0.30753 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.07 0.2175) (end -0.2175 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.07 5.715) (end -1.07 0.2175) (layer F.Fab) (width 0.1)) + (fp_line (start 2.34 5.715) (end -1.07 5.715) (layer F.Fab) (width 0.1)) + (fp_line (start 2.34 -0.635) (end 2.34 5.715) (layer F.Fab) (width 0.1)) + (fp_line (start -0.2175 -0.635) (end 2.34 -0.635) (layer F.Fab) (width 0.1)) + (pad 10 thru_hole oval (at 1.27 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 184 /s_BRAIN/~SYS_RST)) + (pad 9 thru_hole oval (at 0 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 8 thru_hole oval (at 1.27 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 2 "Net-(J2-Pad8)")) + (pad 7 thru_hole oval (at 0 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 3 "Net-(J2-Pad7)")) + (pad 6 thru_hole oval (at 1.27 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 185 /s_BRAIN/SWO)) + (pad 5 thru_hole oval (at 0 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 4 thru_hole oval (at 1.27 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 186 /s_BRAIN/SWCLK)) + (pad 3 thru_hole oval (at 0 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 2 thru_hole oval (at 1.27 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 187 /s_BRAIN/SWDIO)) + (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 4 "Net-(J2-Pad1)")) + (model ${KISYS3DMOD}/Connector_PinHeader_1.27mm.3dshapes/PinHeader_2x05_P1.27mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm (layer F.Cu) (tedit 5A0FD1B2) (tstamp 5E752FF8) + (at 63.5 86.36) + (descr "SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf") + (tags "SMD SMT Crystal") + (path /5E805E4F/5E75D825) + (attr smd) + (fp_text reference Y1 (at 0 -2) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value XOSC32 (at 0 2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2 -1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2 -1.15) (end -2 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2 1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.75) (end 1.6 -0.75) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start -0.675 -0.875) (end 0.675 -0.875) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.675 0.875) (end 0.675 0.875) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.6 -0.75) (end -1.6 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start -2 -1.15) (end 2 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 2 smd rect (at -1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) + (net 55 "Net-(C1-Pad2)")) + (pad 1 smd rect (at 1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) + (net 131 "Net-(C2-Pad1)")) + (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_3215-2Pin_3.2x1.5mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module proj_modules:SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418) (tstamp 5E752FE7) + (at 106.68 77.47) + (path /5E8589A7/5E86D6D7) + (fp_text reference U3 (at -2.415 -8.587) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.015))) + ) + (fp_text value MAX7301AAX+ (at 5.84 8.587) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.015))) + ) + (fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127)) + (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2)) + (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2)) + (pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 122 g_3v3)) + (pad 35 smd rect (at 4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS)) + (pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 178 /MASTER_SPI_MOSI)) + (pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 175 /MASTER_SPI_CLK)) + (pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 123 "Net-(U3-Pad32)")) + (pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 124 "Net-(U3-Pad31)")) + (pad 30 smd rect (at 4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 125 "Net-(U3-Pad30)")) + (pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 126 "Net-(U3-Pad29)")) + (pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 137 /s_SCREEN_INTF/D23)) + (pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 138 /s_SCREEN_INTF/D22)) + (pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 139 /s_SCREEN_INTF/D21)) + (pad 25 smd rect (at 4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 140 /s_SCREEN_INTF/D20)) + (pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 141 /s_SCREEN_INTF/D19)) + (pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 142 /s_SCREEN_INTF/D18)) + (pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 143 /s_SCREEN_INTF/D17)) + (pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 144 /s_SCREEN_INTF/D16)) + (pad 20 smd rect (at 4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 145 /s_SCREEN_INTF/D15)) + (pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 146 /s_SCREEN_INTF/D14)) + (pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 147 /s_SCREEN_INTF/D13)) + (pad 17 smd rect (at -4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 148 /s_SCREEN_INTF/D12)) + (pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 149 /s_SCREEN_INTF/D11)) + (pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 150 /s_SCREEN_INTF/D10)) + (pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 151 /s_SCREEN_INTF/D9)) + (pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 152 /s_SCREEN_INTF/D8)) + (pad 12 smd rect (at -4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 153 /s_SCREEN_INTF/D7)) + (pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 154 /s_SCREEN_INTF/D6)) + (pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 155 /s_SCREEN_INTF/D5)) + (pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 156 /s_SCREEN_INTF/D4)) + (pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 157 /s_SCREEN_INTF/D3)) + (pad 7 smd rect (at -4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 158 /s_SCREEN_INTF/D2)) + (pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 159 /s_SCREEN_INTF/D1)) + (pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 160 /s_SCREEN_INTF/D0)) + (pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 174 /MASTER_SPI_MISO)) + (pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 2 smd rect (at -4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 128 "Net-(R1-Pad1)")) + ) + + (module digikey-footprints:QFN-32-1EP_5x5mm (layer F.Cu) (tedit 5D2895FE) (tstamp 5E752FB3) + (at 71.12 73.66) + (path /5E7C0F59/5E84744C) + (attr smd) + (fp_text reference U2 (at 0 -4.71) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value FT232RQ-REEL (at 0 4.51) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.98 2.05) (end -3.02 2.05) (layer F.Fab) (width 0.1)) + (fp_line (start 1.98 -2.95) (end 1.98 2.05) (layer F.Fab) (width 0.1)) + (fp_line (start 2.08 2.15) (end 1.68 2.15) (layer F.SilkS) (width 0.1)) + (fp_line (start 2.08 1.75) (end 2.08 2.15) (layer F.SilkS) (width 0.1)) + (fp_line (start 2.08 -3.05) (end 2.08 -2.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 2.08 -3.05) (end 1.68 -3.05) (layer F.SilkS) (width 0.1)) + (fp_line (start -3.12 2.15) (end -3.12 1.75) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.72 2.15) (end -3.12 2.15) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.62 -2.95) (end -3.02 -2.55) (layer F.Fab) (width 0.1)) + (fp_line (start -3.02 -2.55) (end -3.02 2.05) (layer F.Fab) (width 0.1)) + (fp_line (start -2.62 -2.95) (end 1.98 -2.95) (layer F.Fab) (width 0.1)) + (fp_line (start -3.12 -2.45) (end -3.32 -2.45) (layer F.SilkS) (width 0.1)) + (fp_line (start -3.12 -2.65) (end -3.12 -2.45) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.72 -3.05) (end -3.12 -2.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.52 -3.05) (end -2.72 -3.05) (layer F.SilkS) (width 0.1)) + (fp_text user %R (at -0.52 -0.45) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.61 2.68) (end -3.65 2.68) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.61 -3.58) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.61 -3.58) (end 2.61 2.68) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.65 2.68) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) + (pad 32 smd rect (at -2.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 103 "Net-(U2-Pad32)") (solder_mask_margin 0.07)) + (pad 31 smd rect (at -1.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 104 "Net-(U2-Pad31)") (solder_mask_margin 0.07)) + (pad 30 smd rect (at -1.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 134 /DEBUG_RX) (solder_mask_margin 0.07)) + (pad 29 smd rect (at -0.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 105 "Net-(U2-Pad29)") (solder_mask_margin 0.07)) + (pad 28 smd rect (at -0.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 106 "Net-(U2-Pad28)") (solder_mask_margin 0.07)) + (pad 27 smd rect (at 0.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 107 "Net-(U2-Pad27)") (solder_mask_margin 0.07)) + (pad 26 smd rect (at 0.73 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 24 smd rect (at 1.955 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 23 smd rect (at 1.955 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 108 "Net-(U2-Pad23)") (solder_mask_margin 0.07)) + (pad 22 smd rect (at 1.955 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 109 "Net-(U2-Pad22)") (solder_mask_margin 0.07)) + (pad 21 smd rect (at 1.955 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 110 "Net-(U2-Pad21)") (solder_mask_margin 0.07)) + (pad 20 smd rect (at 1.955 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 19 smd rect (at 1.955 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 176 /s_USB_INTF.sch/FTDI_5V) (solder_mask_margin 0.07)) + (pad 18 smd rect (at 1.955 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 111 "Net-(U2-Pad18)") (solder_mask_margin 0.07)) + (pad 16 smd rect (at 1.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) + (pad 15 smd rect (at 0.73 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 130 /s_USB_INTF.sch/USB_D-) (solder_mask_margin 0.07)) + (pad 14 smd rect (at 0.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 129 /s_USB_INTF.sch/USB_D+) (solder_mask_margin 0.07)) + (pad 13 smd rect (at -0.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 112 "Net-(U2-Pad13)") (solder_mask_margin 0.07)) + (pad 12 smd rect (at -0.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 113 "Net-(U2-Pad12)") (solder_mask_margin 0.07)) + (pad 11 smd rect (at -1.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 114 "Net-(U2-Pad11)") (solder_mask_margin 0.07)) + (pad 10 smd rect (at -1.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 115 "Net-(U2-Pad10)") (solder_mask_margin 0.07)) + (pad 8 smd rect (at -2.995 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 116 "Net-(U2-Pad8)") (solder_mask_margin 0.07)) + (pad 7 smd rect (at -2.995 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 117 "Net-(U2-Pad7)") (solder_mask_margin 0.07)) + (pad 6 smd rect (at -2.995 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 118 "Net-(U2-Pad6)") (solder_mask_margin 0.07)) + (pad 5 smd rect (at -2.995 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 119 "Net-(U2-Pad5)") (solder_mask_margin 0.07)) + (pad 4 smd rect (at -2.995 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 3 smd rect (at -2.995 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 120 "Net-(U2-Pad3)") (solder_mask_margin 0.07)) + (pad 2 smd rect (at -2.995 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 135 /DEBUG_TX) (solder_mask_margin 0.07)) + (pad 1 smd rect (at -2.995 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) + (pad 33 thru_hole circle (at -1.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -1.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -1.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -0.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -0.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -0.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at 0.48 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at 0.48 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at 0.48 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 smd rect (at -0.52 -0.45 270) (size 3.45 3.45) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 9 smd rect (at -2.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) + (pad 17 smd rect (at 1.955 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 25 smd rect (at 1.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 121 "Net-(U2-Pad25)") (solder_mask_margin 0.07)) + ) + + (module penguin:QFP40P1600X1600X120-128N_ATSAME54P20A (layer F.Cu) (tedit 5E6D9777) (tstamp 5E752F71) + (at 90.17 109.22 45) + (path /5E7872D3/5E84F3B3) + (fp_text reference U1 (at -4.500975 -9.803025 45) (layer F.SilkS) + (effects (font (size 1.001331 1.001331) (thickness 0.015))) + ) + (fp_text value p_ATSAME54P20A-AU (at 6.78639 10.114365 45) (layer F.Fab) + (effects (font (size 1.002417 1.002417) (thickness 0.015))) + ) + (fp_line (start -7 7) (end -7 6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start -6.6 7) (end -7 7) (layer F.SilkS) (width 0.127)) + (fp_line (start 7 7) (end 7 6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.6 7) (end 7 7) (layer F.SilkS) (width 0.127)) + (fp_line (start 7 -7) (end 7 -6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.6 -7) (end 7 -7) (layer F.SilkS) (width 0.127)) + (fp_line (start -7 -7) (end -7 -6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start -6.6 -7) (end -7 -7) (layer F.SilkS) (width 0.127)) + (fp_line (start 8.655 8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.655 8.655) (end -8.655 -8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.655 -8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.655 8.655) (end 8.655 8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -7 7) (end -7 -7) (layer F.Fab) (width 0.127)) + (fp_line (start 7 7) (end 7 -7) (layer F.Fab) (width 0.127)) + (fp_line (start 7 -7) (end -7 -7) (layer F.Fab) (width 0.127)) + (fp_line (start 7 7) (end -7 7) (layer F.Fab) (width 0.127)) + (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.Fab) (width 0.1)) + (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.SilkS) (width 0.1)) + (pad 96 smd rect (at 7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 95 smd rect (at 7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 9 "Net-(U1-Pad95)")) + (pad 94 smd rect (at 7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 10 "Net-(U1-Pad94)")) + (pad 93 smd rect (at 7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 11 "Net-(U1-Pad93)")) + (pad 92 smd rect (at 7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 12 "Net-(U1-Pad92)")) + (pad 91 smd rect (at 7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 90 smd rect (at 7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 89 smd rect (at 7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 13 "Net-(U1-Pad89)")) + (pad 88 smd rect (at 7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 14 "Net-(U1-Pad88)")) + (pad 87 smd rect (at 7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 15 "Net-(U1-Pad87)")) + (pad 86 smd rect (at 7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 16 "Net-(U1-Pad86)")) + (pad 85 smd rect (at 7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 17 "Net-(U1-Pad85)")) + (pad 84 smd rect (at 7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 18 "Net-(U1-Pad84)")) + (pad 83 smd rect (at 7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 19 "Net-(U1-Pad83)")) + (pad 82 smd rect (at 7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 20 "Net-(U1-Pad82)")) + (pad 81 smd rect (at 7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 21 "Net-(U1-Pad81)")) + (pad 80 smd rect (at 7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 22 "Net-(U1-Pad80)")) + (pad 79 smd rect (at 7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 78 smd rect (at 7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 77 smd rect (at 7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 23 "Net-(U1-Pad77)")) + (pad 76 smd rect (at 7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 24 "Net-(U1-Pad76)")) + (pad 75 smd rect (at 7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 25 "Net-(U1-Pad75)")) + (pad 74 smd rect (at 7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 26 "Net-(U1-Pad74)")) + (pad 73 smd rect (at 7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 27 "Net-(U1-Pad73)")) + (pad 72 smd rect (at 7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 28 "Net-(U1-Pad72)")) + (pad 71 smd rect (at 7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 29 "Net-(U1-Pad71)")) + (pad 70 smd rect (at 7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 30 "Net-(U1-Pad70)")) + (pad 69 smd rect (at 7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 31 "Net-(U1-Pad69)")) + (pad 68 smd rect (at 7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 32 "Net-(U1-Pad68)")) + (pad 67 smd rect (at 7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 171 /MASTER_I2C_SCL)) + (pad 66 smd rect (at 7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 170 /MASTER_I2C_SDA)) + (pad 65 smd rect (at 7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 32 smd rect (at -7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 33 "Net-(U1-Pad32)")) + (pad 31 smd rect (at -7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 34 "Net-(U1-Pad30)")) + (pad 29 smd rect (at -7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 35 "Net-(U1-Pad29)")) + (pad 28 smd rect (at -7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 36 "Net-(U1-Pad28)")) + (pad 27 smd rect (at -7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 37 "Net-(U1-Pad27)")) + (pad 26 smd rect (at -7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 38 "Net-(U1-Pad26)")) + (pad 25 smd rect (at -7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 45 "Net-(U1-Pad14)")) + (pad 24 smd rect (at -7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 39 "Net-(U1-Pad24)")) + (pad 23 smd rect (at -7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 174 /MASTER_SPI_MISO)) + (pad 22 smd rect (at -7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 175 /MASTER_SPI_CLK)) + (pad 21 smd rect (at -7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 174 /MASTER_SPI_MISO)) + (pad 20 smd rect (at -7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 40 "Net-(U1-Pad20)")) + (pad 19 smd rect (at -7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 41 "Net-(U1-Pad19)")) + (pad 18 smd rect (at -7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 42 "Net-(U1-Pad18)")) + (pad 17 smd rect (at -7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 190 /s_BRAIN/EXT_IRQ_5)) + (pad 16 smd rect (at -7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 43 "Net-(U1-Pad16)")) + (pad 15 smd rect (at -7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 44 "Net-(U1-Pad15)")) + (pad 14 smd rect (at -7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 45 "Net-(U1-Pad14)")) + (pad 13 smd rect (at -7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 46 "Net-(U1-Pad13)")) + (pad 12 smd rect (at -7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 191 /s_BRAIN/EXT_IRQ_4)) + (pad 11 smd rect (at -7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 192 /s_BRAIN/EXT_IRQ_3)) + (pad 10 smd rect (at -7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 47 "Net-(U1-Pad10)")) + (pad 9 smd rect (at -7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 48 "Net-(U1-Pad9)")) + (pad 8 smd rect (at -7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 49 "Net-(U1-Pad8)")) + (pad 7 smd rect (at -7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 50 "Net-(U1-Pad7)")) + (pad 6 smd rect (at -7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 51 "Net-(U1-Pad6)")) + (pad 5 smd rect (at -7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 52 "Net-(U1-Pad5)")) + (pad 4 smd rect (at -7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 53 "Net-(U1-Pad4)")) + (pad 3 smd rect (at -7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 54 "Net-(U1-Pad3)")) + (pad 2 smd rect (at -7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 131 "Net-(C2-Pad1)")) + (pad 1 smd rect (at -7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 55 "Net-(C1-Pad2)")) + (pad 128 smd rect (at -6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 122 g_3v3)) + (pad 127 smd rect (at -5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 193 /s_BRAIN/EXT_IRQ_2)) + (pad 126 smd rect (at -5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 194 /s_BRAIN/EXT_IRQ_1)) + (pad 125 smd rect (at -5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 195 /s_BRAIN/EXT_IRQ_0)) + (pad 124 smd rect (at -4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 56 "Net-(U1-Pad124)")) + (pad 123 smd rect (at -4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 57 "Net-(U1-Pad123)")) + (pad 122 smd rect (at -3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 58 "Net-(U1-Pad122)")) + (pad 121 smd rect (at -3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 59 "Net-(U1-Pad121)")) + (pad 120 smd rect (at -3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 60 "Net-(U1-Pad120)")) + (pad 119 smd rect (at -2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 61 "Net-(U1-Pad119)")) + (pad 118 smd rect (at -2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 117 smd rect (at -1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 62 "Net-(U1-Pad117)")) + (pad 116 smd rect (at -1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 63 "Net-(U1-Pad116)")) + (pad 115 smd rect (at -1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 64 "Net-(U1-Pad115)")) + (pad 114 smd rect (at -0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 65 "Net-(U1-Pad114)")) + (pad 113 smd rect (at -0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 66 "Net-(U1-Pad113)")) + (pad 112 smd rect (at 0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 67 "Net-(U1-Pad112)")) + (pad 111 smd rect (at 0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 68 "Net-(U1-Pad111)")) + (pad 110 smd rect (at 1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 69 "Net-(U1-Pad110)")) + (pad 109 smd rect (at 1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 70 "Net-(U1-Pad109)")) + (pad 108 smd rect (at 1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 71 "Net-(U1-Pad108)")) + (pad 107 smd rect (at 2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 106 smd rect (at 2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 105 smd rect (at 3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 73 "Net-(U1-Pad105)")) + (pad 104 smd rect (at 3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 74 "Net-(U1-Pad104)")) + (pad 103 smd rect (at 3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 75 "Net-(U1-Pad103)")) + (pad 102 smd rect (at 4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 76 "Net-(U1-Pad102)")) + (pad 101 smd rect (at 4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 135 /DEBUG_TX)) + (pad 100 smd rect (at 5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 134 /DEBUG_RX)) + (pad 99 smd rect (at 5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 77 "Net-(U1-Pad99)")) + (pad 98 smd rect (at 5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 78 "Net-(U1-Pad98)")) + (pad 97 smd rect (at 6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 64 smd rect (at 6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 63 smd rect (at 5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 132 "Net-(C5-Pad2)")) + (pad 62 smd rect (at 5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 133 "Net-(C4-Pad2)")) + (pad 61 smd rect (at 5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 79 "Net-(U1-Pad61)")) + (pad 60 smd rect (at 4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 80 "Net-(U1-Pad60)")) + (pad 59 smd rect (at 4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 81 "Net-(U1-Pad59)")) + (pad 58 smd rect (at 3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 82 "Net-(U1-Pad58)")) + (pad 57 smd rect (at 3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 83 "Net-(U1-Pad57)")) + (pad 56 smd rect (at 3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 84 "Net-(U1-Pad56)")) + (pad 55 smd rect (at 2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 85 "Net-(U1-Pad55)")) + (pad 54 smd rect (at 2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 53 smd rect (at 1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 52 smd rect (at 1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 86 "Net-(U1-Pad52)")) + (pad 51 smd rect (at 1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 87 "Net-(U1-Pad51)")) + (pad 50 smd rect (at 0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 88 "Net-(U1-Pad50)")) + (pad 49 smd rect (at 0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 89 "Net-(U1-Pad49)")) + (pad 48 smd rect (at -0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 90 "Net-(U1-Pad48)")) + (pad 47 smd rect (at -0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 91 "Net-(U1-Pad47)")) + (pad 46 smd rect (at -1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 45 smd rect (at -1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at -1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 92 "Net-(U1-Pad44)")) + (pad 43 smd rect (at -2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 93 "Net-(U1-Pad43)")) + (pad 42 smd rect (at -2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 94 "Net-(U1-Pad42)")) + (pad 41 smd rect (at -3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 95 "Net-(U1-Pad41)")) + (pad 40 smd rect (at -3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 96 "Net-(U1-Pad40)")) + (pad 39 smd rect (at -3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 97 "Net-(U1-Pad39)")) + (pad 38 smd rect (at -4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd rect (at -4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 98 "Net-(U1-Pad37)")) + (pad 36 smd rect (at -5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 99 "Net-(U1-Pad36)")) + (pad 35 smd rect (at -5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 100 "Net-(U1-Pad35)")) + (pad 34 smd rect (at -5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 101 "Net-(U1-Pad34)")) + (pad 33 smd rect (at -6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 102 "Net-(U1-Pad33)")) + ) + + (module Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal (layer F.Cu) (tedit 59DE239E) (tstamp 5E752EDB) + (at 78.74 64.77 90) + (descr "Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows") + (tags "Through hole IDC box header THT 2x20 2.54mm double row") + (path /5E8589A7/5E858ED6) + (fp_text reference J3 (at 6.105 -6.35 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_02x20_Odd_Even_LCD_INTF (at 6.105 54.864 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 13.48 53.61) (end -1.12 53.61) (layer F.CrtYd) (width 0.05)) + (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.12 53.61) (end -1.12 -5.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.12 -5.35) (end 13.48 -5.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.13 53.61) (end 4.13 -5.35) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 53.61) (end 13.48 53.61) (layer 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5A142044) (tstamp 5E752E24) + (at 54.61 73.66 270) + (descr "USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf") + (tags "usb micro receptacle") + (path /5E7C0F59/5E8480AD) + (attr smd) + (fp_text reference J1 (at 0 -3.5 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value USB_B_Micro (at 0 5.6 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user "PCB Edge" (at 0 3.75 90) (layer Dwgs.User) + (effects (font (size 0.5 0.5) (thickness 0.08))) + ) + (fp_text user %R (at 0 1.05 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 4.95 -3.34) (end -4.94 -3.34) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.95 4.85) (end 4.95 -3.34) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.94 4.85) (end 4.95 4.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.94 -3.34) (end -4.94 4.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -2.4) (end 2.8 -2.4) (layer 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F.Fab) (width 0.15)) + (fp_line (start -1.525 -2.725) (end -1.525 -2.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.3 -2.55) (end -1.525 -2.725) (layer F.Fab) (width 0.15)) + (fp_line (start -1.075 -2.725) (end -1.3 -2.55) (layer F.Fab) (width 0.15)) + (fp_line (start -2.7 3.75) (end 2.7 3.75) (layer F.Fab) (width 0.15)) + (fp_line (start 4 -2.25) (end -4 -2.25) (layer F.Fab) (width 0.15)) + (fp_line (start 4 3.15) (end 4 -2.25) (layer F.Fab) (width 0.15)) + (fp_line (start 3.7 3.15) (end 4 3.15) (layer F.Fab) (width 0.15)) + (fp_line (start 3.7 4.35) (end 3.7 3.15) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 4.35) (end 3.7 4.35) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 3.15) (end -3.7 4.35) (layer F.Fab) (width 0.15)) + (fp_line (start -4 3.15) (end -3.7 3.15) (layer F.Fab) (width 0.15)) + (fp_line (start -4 -2.25) (end -4 3.15) (layer F.Fab) (width 0.15)) + (pad "" np_thru_hole oval (at 2.5 -0.8 270) (size 0.8 0.8) (drill 0.8) (layers *.Cu *.Mask)) + (pad "" np_thru_hole oval (at -2.5 -0.8 270) (size 0.8 0.8) (drill 0.8) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 3.875 1.95 270) (size 1.15 1.8) (drill oval 0.55 1.2) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 6 thru_hole oval (at -3.875 1.95 270) (size 1.15 1.8) (drill oval 0.55 1.2) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 6 thru_hole oval (at 3.725 -1.85 270) (size 1.45 2) (drill oval 0.85 1.4) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 6 thru_hole oval (at -3.725 -1.85 270) (size 1.45 2) (drill oval 0.85 1.4) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 5 smd rect (at 1.3 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 4 smd rect (at 0.65 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 1 "Net-(J1-Pad4)")) + (pad 3 smd rect (at 0 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 129 /s_USB_INTF.sch/USB_D+)) + (pad 2 smd rect (at -0.65 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 130 /s_USB_INTF.sch/USB_D-)) + (pad 1 smd rect (at -1.3 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 168 "Net-(C7-Pad1)")) + (model ${KISYS3DMOD}/Connector_USB.3dshapes/USB_Micro-B_Wuerth_629105150521.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_line (start 50.8 130.81) (end 50.8 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E7ADE31)) + (gr_line (start 152.4 130.81) (end 50.8 130.81) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 152.4 50.8) (end 152.4 130.81) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 53.34 50.8) (end 152.4 50.8) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 50.8 50.8) (end 53.34 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E6E9EBC)) + +) diff --git a/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak b/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak index 46da243..39b3c78 100644 --- a/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak +++ b/electrical/same54_dev_board/same54_dev_board.kicad_pcb-bak @@ -1,1591 +1,1591 @@ -(kicad_pcb (version 20171130) (host pcbnew 5.1.5) - - (general - (thickness 1.6) - (drawings 5) - (tracks 0) - (zones 0) - (modules 13) - (nets 196) - ) - - (page A4) - (layers - (0 F.Cu signal) - (31 B.Cu signal) - (32 B.Adhes user) - (33 F.Adhes user) - (34 B.Paste user) - (35 F.Paste user) - (36 B.SilkS user) - (37 F.SilkS user) - (38 B.Mask user) - (39 F.Mask user) - (40 Dwgs.User user) - (41 Cmts.User user) - (42 Eco1.User user) - (43 Eco2.User user) - (44 Edge.Cuts user) - (45 Margin user) - (46 B.CrtYd user) - (47 F.CrtYd user) - (48 B.Fab user) - (49 F.Fab user) - ) - - (setup - (last_trace_width 0.25) - (trace_clearance 0.2) - (zone_clearance 0.508) - (zone_45_only no) - (trace_min 0.2) - (via_size 0.8) - (via_drill 0.4) - (via_min_size 0.4) - (via_min_drill 0.3) - (uvia_size 0.3) - (uvia_drill 0.1) - (uvias_allowed no) - (uvia_min_size 0.2) - (uvia_min_drill 0.1) - (edge_width 0.05) - (segment_width 0.2) - (pcb_text_width 0.3) - (pcb_text_size 1.5 1.5) - (mod_edge_width 0.12) - (mod_text_size 1 1) - (mod_text_width 0.15) - (pad_size 3.45 3.45) - (pad_drill 0) - (pad_to_mask_clearance 0.051) - (solder_mask_min_width 0.25) - (aux_axis_origin 0 0) - (visible_elements 7FFFFFFF) - (pcbplotparams - (layerselection 0x010fc_ffffffff) - (usegerberextensions false) - (usegerberattributes false) - (usegerberadvancedattributes false) - (creategerberjobfile false) - (excludeedgelayer true) - (linewidth 0.100000) - (plotframeref false) - (viasonmask false) - (mode 1) - (useauxorigin false) - (hpglpennumber 1) - (hpglpenspeed 20) - (hpglpendiameter 15.000000) - (psnegative false) - (psa4output false) - (plotreference true) - (plotvalue true) - (plotinvisibletext false) - (padsonsilk false) - (subtractmaskfromsilk false) - (outputformat 1) - (mirror false) - (drillshape 1) - (scaleselection 1) - (outputdirectory "")) - ) - - (net 0 "") - (net 1 "Net-(J1-Pad4)") - (net 2 "Net-(J2-Pad8)") - (net 3 "Net-(J2-Pad7)") - (net 4 "Net-(J2-Pad1)") - (net 5 "Net-(J3-Pad40)") - (net 6 "Net-(J3-Pad39)") - (net 7 "Net-(J3-Pad38)") - (net 8 "Net-(J3-Pad6)") - (net 9 "Net-(U1-Pad95)") - (net 10 "Net-(U1-Pad94)") - (net 11 "Net-(U1-Pad93)") - (net 12 "Net-(U1-Pad92)") - (net 13 "Net-(U1-Pad89)") - (net 14 "Net-(U1-Pad88)") - (net 15 "Net-(U1-Pad87)") - (net 16 "Net-(U1-Pad86)") - (net 17 "Net-(U1-Pad85)") - (net 18 "Net-(U1-Pad84)") - (net 19 "Net-(U1-Pad83)") - (net 20 "Net-(U1-Pad82)") - (net 21 "Net-(U1-Pad81)") - (net 22 "Net-(U1-Pad80)") - (net 23 "Net-(U1-Pad77)") - (net 24 "Net-(U1-Pad76)") - (net 25 "Net-(U1-Pad75)") - (net 26 "Net-(U1-Pad74)") - (net 27 "Net-(U1-Pad73)") - (net 28 "Net-(U1-Pad72)") - (net 29 "Net-(U1-Pad71)") - (net 30 "Net-(U1-Pad70)") - (net 31 "Net-(U1-Pad69)") - (net 32 "Net-(U1-Pad68)") - (net 33 "Net-(U1-Pad32)") - (net 34 "Net-(U1-Pad30)") - (net 35 "Net-(U1-Pad29)") - (net 36 "Net-(U1-Pad28)") - (net 37 "Net-(U1-Pad27)") - (net 38 "Net-(U1-Pad26)") - (net 39 "Net-(U1-Pad24)") - (net 40 "Net-(U1-Pad20)") - (net 41 "Net-(U1-Pad19)") - (net 42 "Net-(U1-Pad18)") - (net 43 "Net-(U1-Pad16)") - (net 44 "Net-(U1-Pad15)") - (net 45 "Net-(U1-Pad14)") - (net 46 "Net-(U1-Pad13)") - (net 47 "Net-(U1-Pad10)") - (net 48 "Net-(U1-Pad9)") - (net 49 "Net-(U1-Pad8)") - (net 50 "Net-(U1-Pad7)") - (net 51 "Net-(U1-Pad6)") - (net 52 "Net-(U1-Pad5)") - (net 53 "Net-(U1-Pad4)") - (net 54 "Net-(U1-Pad3)") - (net 55 "Net-(C1-Pad2)") - (net 56 "Net-(U1-Pad124)") - (net 57 "Net-(U1-Pad123)") - (net 58 "Net-(U1-Pad122)") - (net 59 "Net-(U1-Pad121)") - (net 60 "Net-(U1-Pad120)") - (net 61 "Net-(U1-Pad119)") - (net 62 "Net-(U1-Pad117)") - (net 63 "Net-(U1-Pad116)") - (net 64 "Net-(U1-Pad115)") - (net 65 "Net-(U1-Pad114)") - (net 66 "Net-(U1-Pad113)") - (net 67 "Net-(U1-Pad112)") - (net 68 "Net-(U1-Pad111)") - (net 69 "Net-(U1-Pad110)") - (net 70 "Net-(U1-Pad109)") - (net 71 "Net-(U1-Pad108)") - (net 72 "Net-(U1-Pad107)") - (net 73 "Net-(U1-Pad105)") - (net 74 "Net-(U1-Pad104)") - (net 75 "Net-(U1-Pad103)") - (net 76 "Net-(U1-Pad102)") - (net 77 "Net-(U1-Pad99)") - (net 78 "Net-(U1-Pad98)") - (net 79 "Net-(U1-Pad61)") - (net 80 "Net-(U1-Pad60)") - (net 81 "Net-(U1-Pad59)") - (net 82 "Net-(U1-Pad58)") - (net 83 "Net-(U1-Pad57)") - (net 84 "Net-(U1-Pad56)") - (net 85 "Net-(U1-Pad55)") - (net 86 "Net-(U1-Pad52)") - (net 87 "Net-(U1-Pad51)") - (net 88 "Net-(U1-Pad50)") - (net 89 "Net-(U1-Pad49)") - (net 90 "Net-(U1-Pad48)") - (net 91 "Net-(U1-Pad47)") - (net 92 "Net-(U1-Pad44)") - (net 93 "Net-(U1-Pad43)") - (net 94 "Net-(U1-Pad42)") - (net 95 "Net-(U1-Pad41)") - (net 96 "Net-(U1-Pad40)") - (net 97 "Net-(U1-Pad39)") - (net 98 "Net-(U1-Pad37)") - (net 99 "Net-(U1-Pad36)") - (net 100 "Net-(U1-Pad35)") - (net 101 "Net-(U1-Pad34)") - (net 102 "Net-(U1-Pad33)") - (net 103 "Net-(U2-Pad32)") - (net 104 "Net-(U2-Pad31)") - (net 105 "Net-(U2-Pad29)") - (net 106 "Net-(U2-Pad28)") - (net 107 "Net-(U2-Pad27)") - (net 108 "Net-(U2-Pad23)") - (net 109 "Net-(U2-Pad22)") - (net 110 "Net-(U2-Pad21)") - (net 111 "Net-(U2-Pad18)") - (net 112 "Net-(U2-Pad13)") - (net 113 "Net-(U2-Pad12)") - (net 114 "Net-(U2-Pad11)") - (net 115 "Net-(U2-Pad10)") - (net 116 "Net-(U2-Pad8)") - (net 117 "Net-(U2-Pad7)") - (net 118 "Net-(U2-Pad6)") - (net 119 "Net-(U2-Pad5)") - (net 120 "Net-(U2-Pad3)") - (net 121 "Net-(U2-Pad25)") - (net 122 g_3v3) - (net 123 "Net-(U3-Pad32)") - (net 124 "Net-(U3-Pad31)") - (net 125 "Net-(U3-Pad30)") - (net 126 "Net-(U3-Pad29)") - (net 127 GND) - (net 128 "Net-(R1-Pad1)") - (net 129 /s_USB_INTF.sch/USB_D+) - (net 130 /s_USB_INTF.sch/USB_D-) - (net 131 "Net-(C2-Pad1)") - (net 132 "Net-(C5-Pad2)") - (net 133 "Net-(C4-Pad2)") - (net 134 /DEBUG_RX) - (net 135 /DEBUG_TX) - (net 136 /s_SCREEN_INTF/TFT_STB) - (net 137 /s_SCREEN_INTF/D23) - (net 138 /s_SCREEN_INTF/D22) - (net 139 /s_SCREEN_INTF/D21) - (net 140 /s_SCREEN_INTF/D20) - (net 141 /s_SCREEN_INTF/D19) - (net 142 /s_SCREEN_INTF/D18) - (net 143 /s_SCREEN_INTF/D17) - (net 144 /s_SCREEN_INTF/D16) - (net 145 /s_SCREEN_INTF/D15) - (net 146 /s_SCREEN_INTF/D14) - (net 147 /s_SCREEN_INTF/D13) - (net 148 /s_SCREEN_INTF/D12) - (net 149 /s_SCREEN_INTF/D11) - (net 150 /s_SCREEN_INTF/D10) - (net 151 /s_SCREEN_INTF/D9) - (net 152 /s_SCREEN_INTF/D8) - (net 153 /s_SCREEN_INTF/D7) - (net 154 /s_SCREEN_INTF/D6) - (net 155 /s_SCREEN_INTF/D5) - (net 156 /s_SCREEN_INTF/D4) - (net 157 /s_SCREEN_INTF/D3) - (net 158 /s_SCREEN_INTF/D2) - (net 159 /s_SCREEN_INTF/D1) - (net 160 /s_SCREEN_INTF/D0) - (net 161 /s_SCREEN_INTF/TFT_TE) - (net 162 /s_SCREEN_INTF/~TFT_RD) - (net 163 /s_SCREEN_INTF/~TFT_WR) - (net 164 /s_SCREEN_INTF/TFT_RSDC) - (net 165 /s_SCREEN_INTF/~TFT_RST) - (net 166 /s_SCREEN_INTF/TFT_TOUCH_INT) - (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS) - (net 168 "Net-(C7-Pad1)") - (net 169 /~TFT_CS) - (net 170 /MASTER_I2C_SDA) - (net 171 /MASTER_I2C_SCL) - (net 172 /s_Power/USB_5v) - (net 173 /s_Power/USB_3v3) - (net 174 /MASTER_SPI_MISO) - (net 175 /MASTER_SPI_CLK) - (net 176 /s_USB_INTF.sch/FTDI_5V) - (net 177 /s_USB_INTF.sch/FTDI_3V3) - (net 178 /MASTER_SPI_MOSI) - (net 179 "Net-(U4-Pad5)") - (net 180 "Net-(U4-Pad3)") - (net 181 "Net-(Q1-Pad3)") - (net 182 "Net-(Q2-Pad3)") - (net 183 "Net-(C10-Pad1)") - (net 184 /s_BRAIN/~SYS_RST) - (net 185 /s_BRAIN/SWO) - (net 186 /s_BRAIN/SWCLK) - (net 187 /s_BRAIN/SWDIO) - (net 188 /s_Power/Wall_5V) - (net 189 "Net-(J4-Pad3)") - (net 190 /s_BRAIN/EXT_IRQ_5) - (net 191 /s_BRAIN/EXT_IRQ_4) - (net 192 /s_BRAIN/EXT_IRQ_3) - (net 193 /s_BRAIN/EXT_IRQ_2) - (net 194 /s_BRAIN/EXT_IRQ_1) - (net 195 /s_BRAIN/EXT_IRQ_0) - - (net_class Default "This is the default net class." - (clearance 0.2) - (trace_width 0.25) - (via_dia 0.8) - (via_drill 0.4) - (uvia_dia 0.3) - (uvia_drill 0.1) - (add_net /DEBUG_RX) - (add_net /DEBUG_TX) - (add_net /MASTER_I2C_SCL) - (add_net /MASTER_I2C_SDA) - (add_net /MASTER_SPI_CLK) - (add_net /MASTER_SPI_MISO) - (add_net /MASTER_SPI_MOSI) - (add_net /s_BRAIN/EXT_IRQ_0) - (add_net /s_BRAIN/EXT_IRQ_1) - (add_net /s_BRAIN/EXT_IRQ_2) - (add_net /s_BRAIN/EXT_IRQ_3) - (add_net /s_BRAIN/EXT_IRQ_4) - (add_net /s_BRAIN/EXT_IRQ_5) - (add_net /s_BRAIN/SWCLK) - (add_net /s_BRAIN/SWDIO) - (add_net /s_BRAIN/SWO) - (add_net /s_BRAIN/~SYS_RST) - (add_net /s_Power/USB_3v3) - (add_net /s_Power/USB_5v) - (add_net /s_Power/Wall_5V) - (add_net /s_SCREEN_INTF/D0) - (add_net /s_SCREEN_INTF/D1) - (add_net /s_SCREEN_INTF/D10) - (add_net /s_SCREEN_INTF/D11) - (add_net /s_SCREEN_INTF/D12) - (add_net /s_SCREEN_INTF/D13) - (add_net /s_SCREEN_INTF/D14) - (add_net /s_SCREEN_INTF/D15) - (add_net /s_SCREEN_INTF/D16) - (add_net /s_SCREEN_INTF/D17) - (add_net /s_SCREEN_INTF/D18) - (add_net /s_SCREEN_INTF/D19) - (add_net /s_SCREEN_INTF/D2) - (add_net /s_SCREEN_INTF/D20) - (add_net /s_SCREEN_INTF/D21) - (add_net /s_SCREEN_INTF/D22) - (add_net /s_SCREEN_INTF/D23) - (add_net /s_SCREEN_INTF/D3) - (add_net /s_SCREEN_INTF/D4) - (add_net /s_SCREEN_INTF/D5) - (add_net /s_SCREEN_INTF/D6) - (add_net /s_SCREEN_INTF/D7) - (add_net /s_SCREEN_INTF/D8) - (add_net /s_SCREEN_INTF/D9) - (add_net /s_SCREEN_INTF/TFT_RSDC) - (add_net /s_SCREEN_INTF/TFT_STB) - (add_net /s_SCREEN_INTF/TFT_TE) - (add_net /s_SCREEN_INTF/TFT_TOUCH_INT) - (add_net /s_SCREEN_INTF/~IO_EXPANDER_CS) - (add_net /s_SCREEN_INTF/~TFT_RD) - (add_net /s_SCREEN_INTF/~TFT_RST) - (add_net /s_SCREEN_INTF/~TFT_WR) - (add_net /s_USB_INTF.sch/FTDI_3V3) - (add_net /s_USB_INTF.sch/FTDI_5V) - (add_net /s_USB_INTF.sch/USB_D+) - (add_net /s_USB_INTF.sch/USB_D-) - (add_net /~TFT_CS) - (add_net GND) - (add_net "Net-(C1-Pad2)") - (add_net "Net-(C10-Pad1)") - (add_net "Net-(C2-Pad1)") - (add_net "Net-(C4-Pad2)") - (add_net "Net-(C5-Pad2)") - (add_net "Net-(C7-Pad1)") - (add_net "Net-(J1-Pad4)") - (add_net "Net-(J2-Pad1)") - (add_net "Net-(J2-Pad7)") - (add_net "Net-(J2-Pad8)") - (add_net "Net-(J3-Pad38)") - (add_net "Net-(J3-Pad39)") - (add_net "Net-(J3-Pad40)") - (add_net "Net-(J3-Pad6)") - (add_net "Net-(J4-Pad3)") - (add_net "Net-(Q1-Pad3)") - (add_net "Net-(Q2-Pad3)") - (add_net "Net-(R1-Pad1)") - (add_net "Net-(U1-Pad10)") - (add_net "Net-(U1-Pad102)") - (add_net "Net-(U1-Pad103)") - (add_net "Net-(U1-Pad104)") - (add_net "Net-(U1-Pad105)") - (add_net "Net-(U1-Pad107)") - (add_net "Net-(U1-Pad108)") - (add_net "Net-(U1-Pad109)") - (add_net "Net-(U1-Pad110)") - (add_net "Net-(U1-Pad111)") - (add_net "Net-(U1-Pad112)") - (add_net "Net-(U1-Pad113)") - (add_net "Net-(U1-Pad114)") - (add_net "Net-(U1-Pad115)") - (add_net "Net-(U1-Pad116)") - (add_net "Net-(U1-Pad117)") - (add_net "Net-(U1-Pad119)") - (add_net "Net-(U1-Pad120)") - (add_net "Net-(U1-Pad121)") - (add_net "Net-(U1-Pad122)") - (add_net "Net-(U1-Pad123)") - (add_net "Net-(U1-Pad124)") - (add_net "Net-(U1-Pad13)") - (add_net "Net-(U1-Pad14)") - (add_net "Net-(U1-Pad15)") - (add_net "Net-(U1-Pad16)") - (add_net "Net-(U1-Pad18)") - (add_net "Net-(U1-Pad19)") - (add_net "Net-(U1-Pad20)") - (add_net "Net-(U1-Pad24)") - (add_net "Net-(U1-Pad26)") - (add_net "Net-(U1-Pad27)") - (add_net "Net-(U1-Pad28)") - (add_net "Net-(U1-Pad29)") - (add_net "Net-(U1-Pad3)") - (add_net "Net-(U1-Pad30)") - (add_net "Net-(U1-Pad32)") - (add_net "Net-(U1-Pad33)") - (add_net "Net-(U1-Pad34)") - (add_net "Net-(U1-Pad35)") - (add_net "Net-(U1-Pad36)") - (add_net "Net-(U1-Pad37)") - (add_net "Net-(U1-Pad39)") - (add_net "Net-(U1-Pad4)") - (add_net "Net-(U1-Pad40)") - (add_net "Net-(U1-Pad41)") - (add_net "Net-(U1-Pad42)") - (add_net "Net-(U1-Pad43)") - (add_net "Net-(U1-Pad44)") - (add_net "Net-(U1-Pad47)") - (add_net "Net-(U1-Pad48)") - (add_net "Net-(U1-Pad49)") - (add_net "Net-(U1-Pad5)") - (add_net "Net-(U1-Pad50)") - (add_net "Net-(U1-Pad51)") - (add_net "Net-(U1-Pad52)") - (add_net "Net-(U1-Pad55)") - (add_net "Net-(U1-Pad56)") - (add_net "Net-(U1-Pad57)") - (add_net "Net-(U1-Pad58)") - (add_net "Net-(U1-Pad59)") - (add_net "Net-(U1-Pad6)") - (add_net "Net-(U1-Pad60)") - (add_net "Net-(U1-Pad61)") - (add_net "Net-(U1-Pad68)") - (add_net "Net-(U1-Pad69)") - (add_net "Net-(U1-Pad7)") - (add_net "Net-(U1-Pad70)") - (add_net "Net-(U1-Pad71)") - (add_net "Net-(U1-Pad72)") - (add_net "Net-(U1-Pad73)") - (add_net "Net-(U1-Pad74)") - (add_net "Net-(U1-Pad75)") - (add_net "Net-(U1-Pad76)") - (add_net "Net-(U1-Pad77)") - (add_net "Net-(U1-Pad8)") - (add_net "Net-(U1-Pad80)") - (add_net "Net-(U1-Pad81)") - (add_net "Net-(U1-Pad82)") - (add_net "Net-(U1-Pad83)") - (add_net "Net-(U1-Pad84)") - (add_net "Net-(U1-Pad85)") - (add_net "Net-(U1-Pad86)") - (add_net "Net-(U1-Pad87)") - (add_net "Net-(U1-Pad88)") - (add_net "Net-(U1-Pad89)") - (add_net "Net-(U1-Pad9)") - (add_net "Net-(U1-Pad92)") - (add_net "Net-(U1-Pad93)") - (add_net "Net-(U1-Pad94)") - (add_net "Net-(U1-Pad95)") - (add_net "Net-(U1-Pad98)") - (add_net "Net-(U1-Pad99)") - (add_net "Net-(U2-Pad10)") - (add_net "Net-(U2-Pad11)") - (add_net "Net-(U2-Pad12)") - (add_net "Net-(U2-Pad13)") - (add_net "Net-(U2-Pad18)") - (add_net "Net-(U2-Pad21)") - (add_net "Net-(U2-Pad22)") - (add_net "Net-(U2-Pad23)") - (add_net "Net-(U2-Pad25)") - (add_net "Net-(U2-Pad27)") - (add_net "Net-(U2-Pad28)") - (add_net "Net-(U2-Pad29)") - (add_net "Net-(U2-Pad3)") - (add_net "Net-(U2-Pad31)") - (add_net "Net-(U2-Pad32)") - (add_net "Net-(U2-Pad5)") - (add_net "Net-(U2-Pad6)") - (add_net "Net-(U2-Pad7)") - (add_net "Net-(U2-Pad8)") - (add_net "Net-(U3-Pad29)") - (add_net "Net-(U3-Pad30)") - (add_net "Net-(U3-Pad31)") - (add_net "Net-(U3-Pad32)") - (add_net "Net-(U4-Pad3)") - (add_net "Net-(U4-Pad5)") - (add_net g_3v3) - ) - - (module digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A (layer F.Cu) (tedit 5CAD146F) (tstamp 5E7AD729) - (at 62.23 60.96 90) - (path /5E7872D3/5E88DD8C) - (fp_text reference J4 (at 0 -12.1 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Barrel_Jack_Switch (at 0 5.8 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -4.5 3.7) (end 4.5 3.7) (layer F.Fab) (width 0.1)) - (fp_line (start -4.5 3.7) (end -4.5 -10.7) (layer F.Fab) (width 0.1)) - (fp_line (start 4.5 3.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) - (fp_line (start -4.5 -10.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) - (fp_line (start 4.6 3.8) (end 4.1 3.8) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 3.8) (end 4.6 3.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 3.8) (end -4.1 3.8) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 3.8) (end -4.6 3.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -1.2 -1.8) (end 1.2 -1.8) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 -10.8) (end -4.6 -10.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 -10.8) (end -4.1 -10.8) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 -10.8) (end 4.1 -10.8) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 -10.8) (end 4.6 -10.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -4.6 -3.5) (end -4.6 -4.5) (layer F.SilkS) (width 0.1)) - (fp_line (start 4.6 -3.5) (end 4.6 -4.5) (layer F.SilkS) (width 0.1)) - (fp_line (start -5.9 -10.95) (end 4.8 -10.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.9 -10.95) (end -5.9 4.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start 4.8 -10.95) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.9 4.25) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) - (pad 2 thru_hole rect (at 0 -3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 1 thru_hole rect (at 0 3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) - (net 188 /s_Power/Wall_5V)) - (pad 3 thru_hole rect (at -4.7 0 90) (size 2 2.6) (drill oval 1 1.6) (layers *.Cu *.Mask) - (net 189 "Net-(J4-Pad3)")) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6F9) - (at 72.9 97.79) - (path /5E7872D3/5E9DB598) - (attr smd) - (fp_text reference Q4 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Alt PFET_B" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6DD) - (at 68.2 97.79) - (path /5E7872D3/5E9CBFD6) - (attr smd) - (fp_text reference Q3 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Default PFET_B" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6C1) - (at 63.5 102.74) - (path /5E7872D3/5E9D56A5) - (attr smd) - (fp_text reference Q2 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Alt PFET_A" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) - ) - - (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6A5) - (at 69.85 82.55) - (path /5E7872D3/5E9B8E9E) - (attr smd) - (fp_text reference Q1 (at 0.025 -3.375) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value "Default PFET_A" (at 0.025 3.25) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) - (fp_text user %R (at -0.125 0.15) (layer F.Fab) - (effects (font (size 0.25 0.25) (thickness 0.05))) - ) - (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) - (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) - (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) - (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) - (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) - (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 172 /s_Power/USB_5v) (solder_mask_margin 0.07)) - (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) - ) - - (module Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm (layer F.Cu) (tedit 5A64E13E) (tstamp 5E7A9FEB) - (at 80.01 71.12) - (descr "6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)") - (tags "DFN 0.65") - (path /5E7872D3/5E7F2428) - (attr smd) - (fp_text reference U4 (at 0 -2.025) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value NCP349MNAETBG (at 0 2.025) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -1.45 -1.1) (end 0.725 -1.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -0.725 1.1) (end 0.725 1.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.65 1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.65 -1.25) (end 1.65 -1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.65 -1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.65 -1.25) (end -1.65 1.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1 0) (end 0 -1) (layer F.Fab) (width 0.15)) - (fp_line (start -1 1) (end -1 0) (layer F.Fab) (width 0.15)) - (fp_line (start 1 1) (end -1 1) (layer F.Fab) (width 0.15)) - (fp_line (start 1 -1) (end 1 1) (layer F.Fab) (width 0.15)) - (fp_line (start 0 -1) (end 1 -1) (layer F.Fab) (width 0.15)) - (fp_text user %R (at 0 0) (layer F.Fab) - (effects (font (size 0.5 0.5) (thickness 0.075))) - ) - (pad "" smd rect (at 0 0.4) (size 0.82 0.63) (layers F.Paste)) - (pad "" smd rect (at 0 -0.4) (size 0.82 0.63) (layers F.Paste)) - (pad 7 smd rect (at 0 0) (size 1 1.6) (layers F.Cu F.Mask)) - (pad 6 smd rect (at 1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 179 "Net-(U4-Pad5)")) - (pad 5 smd rect (at 1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 179 "Net-(U4-Pad5)")) - (pad 4 smd rect (at 1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 3 smd rect (at -1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 180 "Net-(U4-Pad3)")) - (pad 2 smd rect (at -1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 1 smd rect (at -1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) - (net 183 "Net-(C10-Pad1)")) - (model ${KISYS3DMOD}/Package_DFN_QFN.3dshapes/DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical (layer F.Cu) (tedit 59FED6E3) (tstamp 5E75429F) - (at 128.27 83.82) - (descr "Through hole straight pin header, 2x05, 1.27mm pitch, double rows") - (tags "Through hole pin header THT 2x05 1.27mm double row") - (path /5E805E4F/5EA1E350) - (fp_text reference J2 (at 0.635 -1.695) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Conn_ARM_JTAG_SWD_10 (at 0.635 6.775) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user %R (at 0.635 2.54 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 2.85 -1.15) (end -1.6 -1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start 2.85 6.25) (end 2.85 -1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.6 6.25) (end 2.85 6.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.6 -1.15) (end -1.6 6.25) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.13 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 0) (end -1.13 -0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.57753 -0.695) (end 2.4 -0.695) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.76 -0.695) (end 0.96247 -0.695) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.76 -0.563471) (end 0.76 -0.695) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.76 0.706529) (end 0.76 0.563471) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.563471 0.76) (end 0.706529 0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) - (fp_line (start 2.4 -0.695) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 0.76) (end -1.13 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start 0.30753 5.775) (end 0.96247 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.57753 5.775) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.13 5.775) (end -0.30753 5.775) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.07 0.2175) (end -0.2175 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start -1.07 5.715) (end -1.07 0.2175) (layer F.Fab) (width 0.1)) - (fp_line (start 2.34 5.715) (end -1.07 5.715) (layer F.Fab) (width 0.1)) - (fp_line (start 2.34 -0.635) (end 2.34 5.715) (layer F.Fab) (width 0.1)) - (fp_line (start -0.2175 -0.635) (end 2.34 -0.635) (layer F.Fab) (width 0.1)) - (pad 10 thru_hole oval (at 1.27 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 184 /s_BRAIN/~SYS_RST)) - (pad 9 thru_hole oval (at 0 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 8 thru_hole oval (at 1.27 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 2 "Net-(J2-Pad8)")) - (pad 7 thru_hole oval (at 0 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 3 "Net-(J2-Pad7)")) - (pad 6 thru_hole oval (at 1.27 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 185 /s_BRAIN/SWO)) - (pad 5 thru_hole oval (at 0 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 4 thru_hole oval (at 1.27 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 186 /s_BRAIN/SWCLK)) - (pad 3 thru_hole oval (at 0 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 127 GND)) - (pad 2 thru_hole oval (at 1.27 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 187 /s_BRAIN/SWDIO)) - (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) - (net 4 "Net-(J2-Pad1)")) - (model ${KISYS3DMOD}/Connector_PinHeader_1.27mm.3dshapes/PinHeader_2x05_P1.27mm_Vertical.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm (layer F.Cu) (tedit 5A0FD1B2) (tstamp 5E752FF8) - (at 63.5 86.36) - (descr "SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf") - (tags "SMD SMT Crystal") - (path /5E805E4F/5E75D825) - (attr smd) - (fp_text reference Y1 (at 0 -2) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value XOSC32 (at 0 2) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 2 -1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -2 -1.15) (end -2 1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -2 1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.6 0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) - (fp_line (start -1.6 -0.75) (end 1.6 -0.75) (layer F.Fab) (width 0.1)) - (fp_line (start 1.6 -0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) - (fp_line (start -0.675 -0.875) (end 0.675 -0.875) (layer F.SilkS) (width 0.12)) - (fp_line (start -0.675 0.875) (end 0.675 0.875) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.6 -0.75) (end -1.6 0.75) (layer F.Fab) (width 0.1)) - (fp_line (start -2 -1.15) (end 2 -1.15) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 -2) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 2 smd rect (at -1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) - (net 55 "Net-(C1-Pad2)")) - (pad 1 smd rect (at 1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) - (net 131 "Net-(C2-Pad1)")) - (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_3215-2Pin_3.2x1.5mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module proj_modules:SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418) (tstamp 5E752FE7) - (at 106.68 77.47) - (path /5E8589A7/5E86D6D7) - (fp_text reference U3 (at -2.415 -8.587) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.015))) - ) - (fp_text value MAX7301AAX+ (at 5.84 8.587) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.015))) - ) - (fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05)) - (fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127)) - (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) - (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127)) - (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2)) - (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2)) - (pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 122 g_3v3)) - (pad 35 smd rect (at 4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS)) - (pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 178 /MASTER_SPI_MOSI)) - (pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 175 /MASTER_SPI_CLK)) - (pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 123 "Net-(U3-Pad32)")) - (pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 124 "Net-(U3-Pad31)")) - (pad 30 smd rect (at 4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 125 "Net-(U3-Pad30)")) - (pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 126 "Net-(U3-Pad29)")) - (pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 137 /s_SCREEN_INTF/D23)) - (pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 138 /s_SCREEN_INTF/D22)) - (pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 139 /s_SCREEN_INTF/D21)) - (pad 25 smd rect (at 4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 140 /s_SCREEN_INTF/D20)) - (pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 141 /s_SCREEN_INTF/D19)) - (pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 142 /s_SCREEN_INTF/D18)) - (pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 143 /s_SCREEN_INTF/D17)) - (pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 144 /s_SCREEN_INTF/D16)) - (pad 20 smd rect (at 4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 145 /s_SCREEN_INTF/D15)) - (pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 146 /s_SCREEN_INTF/D14)) - (pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 147 /s_SCREEN_INTF/D13)) - (pad 17 smd rect (at -4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 148 /s_SCREEN_INTF/D12)) - (pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 149 /s_SCREEN_INTF/D11)) - (pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 150 /s_SCREEN_INTF/D10)) - (pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 151 /s_SCREEN_INTF/D9)) - (pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 152 /s_SCREEN_INTF/D8)) - (pad 12 smd rect (at -4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 153 /s_SCREEN_INTF/D7)) - (pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 154 /s_SCREEN_INTF/D6)) - (pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 155 /s_SCREEN_INTF/D5)) - (pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 156 /s_SCREEN_INTF/D4)) - (pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 157 /s_SCREEN_INTF/D3)) - (pad 7 smd rect (at -4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 158 /s_SCREEN_INTF/D2)) - (pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 159 /s_SCREEN_INTF/D1)) - (pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 160 /s_SCREEN_INTF/D0)) - (pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 174 /MASTER_SPI_MISO)) - (pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 2 smd rect (at -4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) - (net 128 "Net-(R1-Pad1)")) - ) - - (module digikey-footprints:QFN-32-1EP_5x5mm (layer F.Cu) (tedit 5D2895FE) (tstamp 5E752FB3) - (at 71.12 73.66) - (path /5E7C0F59/5E84744C) - (attr smd) - (fp_text reference U2 (at 0 -4.71) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value FT232RQ-REEL (at 0 4.51) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 1.98 2.05) (end -3.02 2.05) (layer F.Fab) (width 0.1)) - (fp_line (start 1.98 -2.95) (end 1.98 2.05) (layer F.Fab) (width 0.1)) - (fp_line (start 2.08 2.15) (end 1.68 2.15) (layer F.SilkS) (width 0.1)) - (fp_line (start 2.08 1.75) (end 2.08 2.15) (layer F.SilkS) (width 0.1)) - (fp_line (start 2.08 -3.05) (end 2.08 -2.65) (layer F.SilkS) (width 0.1)) - (fp_line (start 2.08 -3.05) (end 1.68 -3.05) (layer F.SilkS) (width 0.1)) - (fp_line (start -3.12 2.15) (end -3.12 1.75) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.72 2.15) (end -3.12 2.15) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.62 -2.95) (end -3.02 -2.55) (layer F.Fab) (width 0.1)) - (fp_line (start -3.02 -2.55) (end -3.02 2.05) (layer F.Fab) (width 0.1)) - (fp_line (start -2.62 -2.95) (end 1.98 -2.95) (layer F.Fab) (width 0.1)) - (fp_line (start -3.12 -2.45) (end -3.32 -2.45) (layer F.SilkS) (width 0.1)) - (fp_line (start -3.12 -2.65) (end -3.12 -2.45) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.72 -3.05) (end -3.12 -2.65) (layer F.SilkS) (width 0.1)) - (fp_line (start -2.52 -3.05) (end -2.72 -3.05) (layer F.SilkS) (width 0.1)) - (fp_text user %R (at -0.52 -0.45) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 2.61 2.68) (end -3.65 2.68) (layer F.CrtYd) (width 0.05)) - (fp_line (start 2.61 -3.58) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) - (fp_line (start 2.61 -3.58) (end 2.61 2.68) (layer F.CrtYd) (width 0.05)) - (fp_line (start -3.65 2.68) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) - (pad 32 smd rect (at -2.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 103 "Net-(U2-Pad32)") (solder_mask_margin 0.07)) - (pad 31 smd rect (at -1.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 104 "Net-(U2-Pad31)") (solder_mask_margin 0.07)) - (pad 30 smd rect (at -1.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 134 /DEBUG_RX) (solder_mask_margin 0.07)) - (pad 29 smd rect (at -0.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 105 "Net-(U2-Pad29)") (solder_mask_margin 0.07)) - (pad 28 smd rect (at -0.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 106 "Net-(U2-Pad28)") (solder_mask_margin 0.07)) - (pad 27 smd rect (at 0.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 107 "Net-(U2-Pad27)") (solder_mask_margin 0.07)) - (pad 26 smd rect (at 0.73 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 24 smd rect (at 1.955 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 23 smd rect (at 1.955 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 108 "Net-(U2-Pad23)") (solder_mask_margin 0.07)) - (pad 22 smd rect (at 1.955 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 109 "Net-(U2-Pad22)") (solder_mask_margin 0.07)) - (pad 21 smd rect (at 1.955 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 110 "Net-(U2-Pad21)") (solder_mask_margin 0.07)) - (pad 20 smd rect (at 1.955 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 19 smd rect (at 1.955 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 176 /s_USB_INTF.sch/FTDI_5V) (solder_mask_margin 0.07)) - (pad 18 smd rect (at 1.955 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 111 "Net-(U2-Pad18)") (solder_mask_margin 0.07)) - (pad 16 smd rect (at 1.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) - (pad 15 smd rect (at 0.73 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 130 /s_USB_INTF.sch/USB_D-) (solder_mask_margin 0.07)) - (pad 14 smd rect (at 0.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 129 /s_USB_INTF.sch/USB_D+) (solder_mask_margin 0.07)) - (pad 13 smd rect (at -0.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 112 "Net-(U2-Pad13)") (solder_mask_margin 0.07)) - (pad 12 smd rect (at -0.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 113 "Net-(U2-Pad12)") (solder_mask_margin 0.07)) - (pad 11 smd rect (at -1.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 114 "Net-(U2-Pad11)") (solder_mask_margin 0.07)) - (pad 10 smd rect (at -1.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 115 "Net-(U2-Pad10)") (solder_mask_margin 0.07)) - (pad 8 smd rect (at -2.995 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 116 "Net-(U2-Pad8)") (solder_mask_margin 0.07)) - (pad 7 smd rect (at -2.995 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 117 "Net-(U2-Pad7)") (solder_mask_margin 0.07)) - (pad 6 smd rect (at -2.995 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 118 "Net-(U2-Pad6)") (solder_mask_margin 0.07)) - (pad 5 smd rect (at -2.995 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 119 "Net-(U2-Pad5)") (solder_mask_margin 0.07)) - (pad 4 smd rect (at -2.995 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 3 smd rect (at -2.995 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 120 "Net-(U2-Pad3)") (solder_mask_margin 0.07)) - (pad 2 smd rect (at -2.995 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 135 /DEBUG_TX) (solder_mask_margin 0.07)) - (pad 1 smd rect (at -2.995 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) - (pad 33 thru_hole circle (at -1.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -1.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -1.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -0.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -0.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at -0.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at 0.48 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at 0.48 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 thru_hole circle (at 0.48 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) - (net 127 GND) (solder_mask_margin 0.1)) - (pad 33 smd rect (at -0.52 -0.45 270) (size 3.45 3.45) (layers F.Cu F.Paste F.Mask) - (net 127 GND)) - (pad 9 smd rect (at -2.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) - (pad 17 smd rect (at 1.955 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) - (net 127 GND) (solder_mask_margin 0.07)) - (pad 25 smd rect (at 1.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) - (net 121 "Net-(U2-Pad25)") (solder_mask_margin 0.07)) - ) - - (module penguin:QFP40P1600X1600X120-128N_ATSAME54P20A (layer F.Cu) (tedit 5E6D9777) (tstamp 5E752F71) - (at 86.36 109.22 45) - (path /5E7872D3/5E84F3B3) - (fp_text reference U1 (at -4.500975 -9.803025 45) (layer F.SilkS) - (effects (font (size 1.001331 1.001331) (thickness 0.015))) - ) - (fp_text value p_ATSAME54P20A-AU (at 6.78639 10.114365 45) (layer F.Fab) - (effects (font (size 1.002417 1.002417) (thickness 0.015))) - ) - (fp_line (start -7 7) (end -7 6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start -6.6 7) (end -7 7) (layer F.SilkS) (width 0.127)) - (fp_line (start 7 7) (end 7 6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.6 7) (end 7 7) (layer F.SilkS) (width 0.127)) - (fp_line (start 7 -7) (end 7 -6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start 6.6 -7) (end 7 -7) (layer F.SilkS) (width 0.127)) - (fp_line (start -7 -7) (end -7 -6.6) (layer F.SilkS) (width 0.127)) - (fp_line (start -6.6 -7) (end -7 -7) (layer F.SilkS) (width 0.127)) - (fp_line (start 8.655 8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -8.655 8.655) (end -8.655 -8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -8.655 -8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -8.655 8.655) (end 8.655 8.655) (layer F.CrtYd) (width 0.05)) - (fp_line (start -7 7) (end -7 -7) (layer F.Fab) (width 0.127)) - (fp_line (start 7 7) (end 7 -7) (layer F.Fab) (width 0.127)) - (fp_line (start 7 -7) (end -7 -7) (layer F.Fab) (width 0.127)) - (fp_line (start 7 7) (end -7 7) (layer F.Fab) (width 0.127)) - (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.Fab) (width 0.1)) - (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.SilkS) (width 0.1)) - (pad 96 smd rect (at 7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 95 smd rect (at 7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 9 "Net-(U1-Pad95)")) - (pad 94 smd rect (at 7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 10 "Net-(U1-Pad94)")) - (pad 93 smd rect (at 7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 11 "Net-(U1-Pad93)")) - (pad 92 smd rect (at 7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 12 "Net-(U1-Pad92)")) - (pad 91 smd rect (at 7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 90 smd rect (at 7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 89 smd rect (at 7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 13 "Net-(U1-Pad89)")) - (pad 88 smd rect (at 7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 14 "Net-(U1-Pad88)")) - (pad 87 smd rect (at 7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 15 "Net-(U1-Pad87)")) - (pad 86 smd rect (at 7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 16 "Net-(U1-Pad86)")) - (pad 85 smd rect (at 7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 17 "Net-(U1-Pad85)")) - (pad 84 smd rect (at 7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 18 "Net-(U1-Pad84)")) - (pad 83 smd rect (at 7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 19 "Net-(U1-Pad83)")) - (pad 82 smd rect (at 7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 20 "Net-(U1-Pad82)")) - (pad 81 smd rect (at 7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 21 "Net-(U1-Pad81)")) - (pad 80 smd rect (at 7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 22 "Net-(U1-Pad80)")) - (pad 79 smd rect (at 7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 78 smd rect (at 7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 77 smd rect (at 7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 23 "Net-(U1-Pad77)")) - (pad 76 smd rect (at 7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 24 "Net-(U1-Pad76)")) - (pad 75 smd rect (at 7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 25 "Net-(U1-Pad75)")) - (pad 74 smd rect (at 7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 26 "Net-(U1-Pad74)")) - (pad 73 smd rect (at 7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 27 "Net-(U1-Pad73)")) - (pad 72 smd rect (at 7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 28 "Net-(U1-Pad72)")) - (pad 71 smd rect (at 7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 29 "Net-(U1-Pad71)")) - (pad 70 smd rect (at 7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 30 "Net-(U1-Pad70)")) - (pad 69 smd rect (at 7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 31 "Net-(U1-Pad69)")) - (pad 68 smd rect (at 7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 32 "Net-(U1-Pad68)")) - (pad 67 smd rect (at 7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 171 /MASTER_I2C_SCL)) - (pad 66 smd rect (at 7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 170 /MASTER_I2C_SDA)) - (pad 65 smd rect (at 7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 32 smd rect (at -7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 33 "Net-(U1-Pad32)")) - (pad 31 smd rect (at -7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) - (pad 30 smd rect (at -7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 34 "Net-(U1-Pad30)")) - (pad 29 smd rect (at -7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 35 "Net-(U1-Pad29)")) - (pad 28 smd rect (at -7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 36 "Net-(U1-Pad28)")) - (pad 27 smd rect (at -7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 37 "Net-(U1-Pad27)")) - (pad 26 smd rect (at -7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 38 "Net-(U1-Pad26)")) - (pad 25 smd rect (at -7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 45 "Net-(U1-Pad14)")) - (pad 24 smd rect (at -7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 39 "Net-(U1-Pad24)")) - (pad 23 smd rect (at -7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 174 /MASTER_SPI_MISO)) - (pad 22 smd rect (at -7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 175 /MASTER_SPI_CLK)) - (pad 21 smd rect (at -7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 174 /MASTER_SPI_MISO)) - (pad 20 smd rect (at -7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 40 "Net-(U1-Pad20)")) - (pad 19 smd rect (at -7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 41 "Net-(U1-Pad19)")) - (pad 18 smd rect (at -7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 42 "Net-(U1-Pad18)")) - (pad 17 smd rect (at -7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 190 /s_BRAIN/EXT_IRQ_5)) - (pad 16 smd rect (at -7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 43 "Net-(U1-Pad16)")) - (pad 15 smd rect (at -7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 44 "Net-(U1-Pad15)")) - (pad 14 smd rect (at -7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 45 "Net-(U1-Pad14)")) - (pad 13 smd rect (at -7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 46 "Net-(U1-Pad13)")) - (pad 12 smd rect (at -7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 191 /s_BRAIN/EXT_IRQ_4)) - (pad 11 smd rect (at -7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 192 /s_BRAIN/EXT_IRQ_3)) - (pad 10 smd rect (at -7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 47 "Net-(U1-Pad10)")) - (pad 9 smd rect (at -7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 48 "Net-(U1-Pad9)")) - (pad 8 smd rect (at -7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 49 "Net-(U1-Pad8)")) - (pad 7 smd rect (at -7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 50 "Net-(U1-Pad7)")) - (pad 6 smd rect (at -7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 51 "Net-(U1-Pad6)")) - (pad 5 smd rect (at -7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 52 "Net-(U1-Pad5)")) - (pad 4 smd rect (at -7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 53 "Net-(U1-Pad4)")) - (pad 3 smd rect (at -7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 54 "Net-(U1-Pad3)")) - (pad 2 smd rect (at -7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 131 "Net-(C2-Pad1)")) - (pad 1 smd rect (at -7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) - (net 55 "Net-(C1-Pad2)")) - (pad 128 smd rect (at -6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 122 g_3v3)) - (pad 127 smd rect (at -5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 193 /s_BRAIN/EXT_IRQ_2)) - (pad 126 smd rect (at -5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 194 /s_BRAIN/EXT_IRQ_1)) - (pad 125 smd rect (at -5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 195 /s_BRAIN/EXT_IRQ_0)) - (pad 124 smd rect (at -4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 56 "Net-(U1-Pad124)")) - (pad 123 smd rect (at -4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 57 "Net-(U1-Pad123)")) - (pad 122 smd rect (at -3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 58 "Net-(U1-Pad122)")) - (pad 121 smd rect (at -3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 59 "Net-(U1-Pad121)")) - (pad 120 smd rect (at -3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 60 "Net-(U1-Pad120)")) - (pad 119 smd rect (at -2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 61 "Net-(U1-Pad119)")) - (pad 118 smd rect (at -2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 117 smd rect (at -1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 62 "Net-(U1-Pad117)")) - (pad 116 smd rect (at -1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 63 "Net-(U1-Pad116)")) - (pad 115 smd rect (at -1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 64 "Net-(U1-Pad115)")) - (pad 114 smd rect (at -0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 65 "Net-(U1-Pad114)")) - (pad 113 smd rect (at -0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 66 "Net-(U1-Pad113)")) - (pad 112 smd rect (at 0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 67 "Net-(U1-Pad112)")) - (pad 111 smd rect (at 0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 68 "Net-(U1-Pad111)")) - (pad 110 smd rect (at 1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 69 "Net-(U1-Pad110)")) - (pad 109 smd rect (at 1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 70 "Net-(U1-Pad109)")) - (pad 108 smd rect (at 1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 71 "Net-(U1-Pad108)")) - (pad 107 smd rect (at 2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 106 smd rect (at 2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 105 smd rect (at 3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 73 "Net-(U1-Pad105)")) - (pad 104 smd rect (at 3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 74 "Net-(U1-Pad104)")) - (pad 103 smd rect (at 3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 75 "Net-(U1-Pad103)")) - (pad 102 smd rect (at 4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 76 "Net-(U1-Pad102)")) - (pad 101 smd rect (at 4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 135 /DEBUG_TX)) - (pad 100 smd rect (at 5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 134 /DEBUG_RX)) - (pad 99 smd rect (at 5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 77 "Net-(U1-Pad99)")) - (pad 98 smd rect (at 5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 78 "Net-(U1-Pad98)")) - (pad 97 smd rect (at 6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 64 smd rect (at 6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 63 smd rect (at 5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 132 "Net-(C5-Pad2)")) - (pad 62 smd rect (at 5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 133 "Net-(C4-Pad2)")) - (pad 61 smd rect (at 5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 79 "Net-(U1-Pad61)")) - (pad 60 smd rect (at 4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 80 "Net-(U1-Pad60)")) - (pad 59 smd rect (at 4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 81 "Net-(U1-Pad59)")) - (pad 58 smd rect (at 3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 82 "Net-(U1-Pad58)")) - (pad 57 smd rect (at 3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 83 "Net-(U1-Pad57)")) - (pad 56 smd rect (at 3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 84 "Net-(U1-Pad56)")) - (pad 55 smd rect (at 2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 85 "Net-(U1-Pad55)")) - (pad 54 smd rect (at 2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 53 smd rect (at 1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 52 smd rect (at 1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 86 "Net-(U1-Pad52)")) - (pad 51 smd rect (at 1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 87 "Net-(U1-Pad51)")) - (pad 50 smd rect (at 0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 88 "Net-(U1-Pad50)")) - (pad 49 smd rect (at 0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 89 "Net-(U1-Pad49)")) - (pad 48 smd rect (at -0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 90 "Net-(U1-Pad48)")) - (pad 47 smd rect (at -0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 91 "Net-(U1-Pad47)")) - (pad 46 smd rect (at -1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U1-Pad107)")) - (pad 45 smd rect (at -1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 44 smd rect (at -1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 92 "Net-(U1-Pad44)")) - (pad 43 smd rect (at -2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 93 "Net-(U1-Pad43)")) - (pad 42 smd rect (at -2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 94 "Net-(U1-Pad42)")) - (pad 41 smd rect (at -3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 95 "Net-(U1-Pad41)")) - (pad 40 smd rect (at -3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 96 "Net-(U1-Pad40)")) - (pad 39 smd rect (at -3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 97 "Net-(U1-Pad39)")) - (pad 38 smd rect (at -4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) - (pad 37 smd rect (at -4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 98 "Net-(U1-Pad37)")) - (pad 36 smd rect (at -5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 99 "Net-(U1-Pad36)")) - (pad 35 smd rect (at -5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 100 "Net-(U1-Pad35)")) - (pad 34 smd rect (at -5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 101 "Net-(U1-Pad34)")) - (pad 33 smd rect (at -6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) - (net 102 "Net-(U1-Pad33)")) - ) - - (module Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal (layer F.Cu) (tedit 59DE239E) (tstamp 5E752EDB) - (at 78.74 64.77 90) - (descr "Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows") - (tags "Through hole IDC box header THT 2x20 2.54mm double row") - (path /5E8589A7/5E858ED6) - (fp_text reference J3 (at 6.105 -6.35 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Conn_02x20_Odd_Even_LCD_INTF (at 6.105 54.864 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 13.48 53.61) (end -1.12 53.61) (layer F.CrtYd) (width 0.05)) - (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.12 53.61) (end -1.12 -5.35) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.12 -5.35) (end 13.48 -5.35) (layer F.CrtYd) (width 0.05)) - (fp_line (start 4.13 53.61) (end 4.13 -5.35) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 53.61) (end 13.48 53.61) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 26.38) (end 13.48 26.38) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 21.88) (end 13.48 21.88) (layer F.SilkS) (width 0.12)) - (fp_line (start 4.13 -5.35) (end 13.48 -5.35) (layer F.SilkS) (width 0.12)) - (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.SilkS) (width 0.12)) - (fp_line (start 0 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.27 -1.27) (end -1.27 0) (layer F.SilkS) (width 0.12)) - (fp_line (start 5.38 -5.1) (end 13.23 -5.1) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 9.84) (end -0.32 9.84) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 7.3) (end -0.32 7.3) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 53.36) (end 4.38 -4.1) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 53.36) (end 13.23 53.36) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 47.94) (end -0.32 47.94) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 45.4) (end -0.32 45.4) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 42.86) (end -0.32 42.86) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 40.32) (end -0.32 40.32) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 4.76) (end -0.32 4.76) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 37.78) (end -0.32 37.78) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 35.24) (end -0.32 35.24) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 32.7) (end -0.32 32.7) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 30.16) (end -0.32 30.16) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 27.62) (end -0.32 27.62) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 26.38) (end 13.23 26.38) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 25.08) (end -0.32 25.08) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 22.54) (end -0.32 22.54) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 21.88) (end 13.23 21.88) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 20) (end -0.32 20) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 2.22) (end -0.32 2.22) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 17.46) (end -0.32 17.46) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 14.92) (end -0.32 14.92) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 12.38) (end -0.32 12.38) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 -4.1) (end 5.38 -5.1) (layer F.Fab) (width 0.1)) - (fp_line (start 4.38 -0.32) (end -0.32 -0.32) (layer F.Fab) (width 0.1)) - (fp_line (start 13.23 53.36) (end 13.23 -5.1) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 9.84) (end -0.32 10.48) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 7.94) (end 4.38 7.94) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 7.3) (end -0.32 7.94) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 5.4) (end 4.38 5.4) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 48.58) (end 4.38 48.58) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 47.94) (end -0.32 48.58) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 46.04) (end 4.38 46.04) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 45.4) (end -0.32 46.04) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 43.5) (end 4.38 43.5) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 42.86) (end -0.32 43.5) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 40.96) (end 4.38 40.96) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 40.32) (end -0.32 40.96) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 4.76) (end -0.32 5.4) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 38.42) (end 4.38 38.42) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 37.78) (end -0.32 38.42) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 35.88) (end 4.38 35.88) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 35.24) (end -0.32 35.88) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 33.34) (end 4.38 33.34) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 32.7) (end -0.32 33.34) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 30.8) (end 4.38 30.8) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 30.16) (end -0.32 30.8) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 28.26) (end 4.38 28.26) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 27.62) (end -0.32 28.26) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 25.72) (end 4.38 25.72) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 25.08) (end -0.32 25.72) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 23.18) (end 4.38 23.18) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 22.54) (end -0.32 23.18) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 20.64) (end 4.38 20.64) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 20) (end -0.32 20.64) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 2.86) (end 4.38 2.86) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 2.22) (end -0.32 2.86) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 18.1) (end 4.38 18.1) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 17.46) (end -0.32 18.1) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 15.56) (end 4.38 15.56) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 14.92) (end -0.32 15.56) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 13.02) (end 4.38 13.02) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 12.38) (end -0.32 13.02) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 10.48) (end 4.38 10.48) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 0.32) (end 4.38 0.32) (layer F.Fab) (width 0.1)) - (fp_line (start -0.32 -0.32) (end -0.32 0.32) (layer F.Fab) (width 0.1)) - (fp_text user %R (at 8.805 24.13) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 40 thru_hole oval (at 2.54 48.26 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 5 "Net-(J3-Pad40)")) - (pad 39 thru_hole oval (at 0 48.26 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 6 "Net-(J3-Pad39)")) - (pad 38 thru_hole oval (at 2.54 45.72 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 7 "Net-(J3-Pad38)")) - (pad 37 thru_hole oval (at 0 45.72 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 136 /s_SCREEN_INTF/TFT_STB)) - (pad 36 thru_hole oval (at 2.54 43.18 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 137 /s_SCREEN_INTF/D23)) - (pad 35 thru_hole oval (at 0 43.18 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 138 /s_SCREEN_INTF/D22)) - (pad 34 thru_hole oval (at 2.54 40.64 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 139 /s_SCREEN_INTF/D21)) - (pad 33 thru_hole oval (at 0 40.64 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 140 /s_SCREEN_INTF/D20)) - (pad 32 thru_hole oval (at 2.54 38.1 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 141 /s_SCREEN_INTF/D19)) - (pad 31 thru_hole oval (at 0 38.1 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 142 /s_SCREEN_INTF/D18)) - (pad 30 thru_hole oval (at 2.54 35.56 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 143 /s_SCREEN_INTF/D17)) - (pad 29 thru_hole oval (at 0 35.56 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 144 /s_SCREEN_INTF/D16)) - (pad 28 thru_hole oval (at 2.54 33.02 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 145 /s_SCREEN_INTF/D15)) - (pad 27 thru_hole oval (at 0 33.02 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 146 /s_SCREEN_INTF/D14)) - (pad 26 thru_hole oval (at 2.54 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 147 /s_SCREEN_INTF/D13)) - (pad 25 thru_hole oval (at 0 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 148 /s_SCREEN_INTF/D12)) - (pad 24 thru_hole oval (at 2.54 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 149 /s_SCREEN_INTF/D11)) - (pad 23 thru_hole oval (at 0 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 150 /s_SCREEN_INTF/D10)) - (pad 22 thru_hole oval (at 2.54 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 151 /s_SCREEN_INTF/D9)) - (pad 21 thru_hole oval (at 0 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 152 /s_SCREEN_INTF/D8)) - (pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 153 /s_SCREEN_INTF/D7)) - (pad 19 thru_hole oval (at 0 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 154 /s_SCREEN_INTF/D6)) - (pad 18 thru_hole oval (at 2.54 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 155 /s_SCREEN_INTF/D5)) - (pad 17 thru_hole oval (at 0 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 156 /s_SCREEN_INTF/D4)) - (pad 16 thru_hole oval (at 2.54 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 157 /s_SCREEN_INTF/D3)) - (pad 15 thru_hole oval (at 0 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 158 /s_SCREEN_INTF/D2)) - (pad 14 thru_hole oval (at 2.54 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 159 /s_SCREEN_INTF/D1)) - (pad 13 thru_hole oval (at 0 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 160 /s_SCREEN_INTF/D0)) - (pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 161 /s_SCREEN_INTF/TFT_TE)) - (pad 11 thru_hole oval (at 0 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 162 /s_SCREEN_INTF/~TFT_RD)) - (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 163 /s_SCREEN_INTF/~TFT_WR)) - (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 169 /~TFT_CS)) - (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 164 /s_SCREEN_INTF/TFT_RSDC)) - (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) - (net 165 /s_SCREEN_INTF/~TFT_RST)) - (pad 6 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54.61 73.66 270) - (descr "USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf") - (tags "usb micro receptacle") - (path /5E7C0F59/5E8480AD) - (attr smd) - (fp_text reference J1 (at 0 -3.5 90) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value USB_B_Micro (at 0 5.6 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "PCB Edge" (at 0 3.75 90) (layer Dwgs.User) - (effects (font (size 0.5 0.5) (thickness 0.08))) - ) - (fp_text user %R (at 0 1.05 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 4.95 -3.34) (end -4.94 -3.34) (layer F.CrtYd) (width 0.05)) - (fp_line (start 4.95 4.85) (end 4.95 -3.34) (layer F.CrtYd) (width 0.05)) - (fp_line (start -4.94 4.85) (end 4.95 4.85) (layer F.CrtYd) (width 0.05)) - (fp_line (start -4.94 -3.34) (end -4.94 4.85) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 -2.4) (end 2.8 -2.4) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.8 -2.4) (end -2.8 -2.4) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.8 -2.825) (end -1.8 -2.4) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.075 -2.825) (end -1.8 -2.825) (layer F.SilkS) (width 0.15)) - (fp_line (start 4.15 0.75) (end 4.15 -0.65) (layer F.SilkS) (width 0.15)) - (fp_line (start 4.15 3.3) (end 4.15 3.15) (layer F.SilkS) (width 0.15)) - (fp_line (start 3.85 3.3) (end 4.15 3.3) (layer F.SilkS) (width 0.15)) - (fp_line (start 3.85 3.75) (end 3.85 3.3) (layer F.SilkS) (width 0.15)) - (fp_line (start -3.85 3.3) (end -3.85 3.75) (layer F.SilkS) (width 0.15)) - (fp_line (start -4.15 3.3) (end -3.85 3.3) (layer F.SilkS) (width 0.15)) - (fp_line (start -4.15 3.15) (end -4.15 3.3) (layer F.SilkS) (width 0.15)) - (fp_line (start -4.15 -0.65) (end -4.15 0.75) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.075 -2.95) (end -1.075 -2.725) (layer F.Fab) (width 0.15)) - (fp_line (start -1.525 -2.95) (end -1.075 -2.95) (layer F.Fab) (width 0.15)) - (fp_line (start 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-1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) - (net 168 "Net-(C7-Pad1)")) - (model ${KISYS3DMOD}/Connector_USB.3dshapes/USB_Micro-B_Wuerth_629105150521.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (gr_line (start 50.8 130.81) (end 50.8 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E7ADE31)) - (gr_line (start 152.4 130.81) (end 50.8 130.81) (layer Edge.Cuts) (width 0.05)) - (gr_line (start 152.4 50.8) (end 152.4 130.81) (layer Edge.Cuts) (width 0.05)) - (gr_line (start 53.34 50.8) (end 152.4 50.8) (layer Edge.Cuts) (width 0.05)) - (gr_line (start 50.8 50.8) (end 53.34 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E6E9EBC)) - -) +(kicad_pcb (version 20171130) (host pcbnew 5.1.5) + + (general + (thickness 1.6) + (drawings 5) + (tracks 0) + (zones 0) + (modules 13) + (nets 196) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 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(usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 "Net-(J1-Pad4)") + (net 2 "Net-(J2-Pad8)") + (net 3 "Net-(J2-Pad7)") + (net 4 "Net-(J2-Pad1)") + (net 5 "Net-(J3-Pad40)") + (net 6 "Net-(J3-Pad39)") + (net 7 "Net-(J3-Pad38)") + (net 8 "Net-(J3-Pad6)") + (net 9 "Net-(U1-Pad95)") + (net 10 "Net-(U1-Pad94)") + (net 11 "Net-(U1-Pad93)") + (net 12 "Net-(U1-Pad92)") + (net 13 "Net-(U1-Pad89)") + (net 14 "Net-(U1-Pad88)") + (net 15 "Net-(U1-Pad87)") + (net 16 "Net-(U1-Pad86)") + (net 17 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"Net-(U3-Pad32)") + (net 124 "Net-(U3-Pad31)") + (net 125 "Net-(U3-Pad30)") + (net 126 "Net-(U3-Pad29)") + (net 127 GND) + (net 128 "Net-(R1-Pad1)") + (net 129 /s_USB_INTF.sch/USB_D+) + (net 130 /s_USB_INTF.sch/USB_D-) + (net 131 "Net-(C2-Pad1)") + (net 132 "Net-(C5-Pad2)") + (net 133 "Net-(C4-Pad2)") + (net 134 /DEBUG_RX) + (net 135 /DEBUG_TX) + (net 136 /s_SCREEN_INTF/TFT_STB) + (net 137 /s_SCREEN_INTF/D23) + (net 138 /s_SCREEN_INTF/D22) + (net 139 /s_SCREEN_INTF/D21) + (net 140 /s_SCREEN_INTF/D20) + (net 141 /s_SCREEN_INTF/D19) + (net 142 /s_SCREEN_INTF/D18) + (net 143 /s_SCREEN_INTF/D17) + (net 144 /s_SCREEN_INTF/D16) + (net 145 /s_SCREEN_INTF/D15) + (net 146 /s_SCREEN_INTF/D14) + (net 147 /s_SCREEN_INTF/D13) + (net 148 /s_SCREEN_INTF/D12) + (net 149 /s_SCREEN_INTF/D11) + (net 150 /s_SCREEN_INTF/D10) + (net 151 /s_SCREEN_INTF/D9) + (net 152 /s_SCREEN_INTF/D8) + (net 153 /s_SCREEN_INTF/D7) + (net 154 /s_SCREEN_INTF/D6) + (net 155 /s_SCREEN_INTF/D5) + (net 156 /s_SCREEN_INTF/D4) + (net 157 /s_SCREEN_INTF/D3) + (net 158 /s_SCREEN_INTF/D2) + (net 159 /s_SCREEN_INTF/D1) + (net 160 /s_SCREEN_INTF/D0) + (net 161 /s_SCREEN_INTF/TFT_TE) + (net 162 /s_SCREEN_INTF/~TFT_RD) + (net 163 /s_SCREEN_INTF/~TFT_WR) + (net 164 /s_SCREEN_INTF/TFT_RSDC) + (net 165 /s_SCREEN_INTF/~TFT_RST) + (net 166 /s_SCREEN_INTF/TFT_TOUCH_INT) + (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS) + (net 168 "Net-(C7-Pad1)") + (net 169 /~TFT_CS) + (net 170 /MASTER_I2C_SDA) + (net 171 /MASTER_I2C_SCL) + (net 172 /s_Power/USB_5v) + (net 173 /s_Power/USB_3v3) + (net 174 /MASTER_SPI_MISO) + (net 175 /MASTER_SPI_CLK) + (net 176 /s_USB_INTF.sch/FTDI_5V) + (net 177 /s_USB_INTF.sch/FTDI_3V3) + (net 178 /MASTER_SPI_MOSI) + (net 179 "Net-(U4-Pad5)") + (net 180 "Net-(U4-Pad3)") + (net 181 "Net-(Q1-Pad3)") + (net 182 "Net-(Q2-Pad3)") + (net 183 "Net-(C10-Pad1)") + (net 184 /s_BRAIN/~SYS_RST) + (net 185 /s_BRAIN/SWO) + (net 186 /s_BRAIN/SWCLK) + (net 187 /s_BRAIN/SWDIO) + (net 188 /s_Power/Wall_5V) + (net 189 "Net-(J4-Pad3)") + (net 190 /s_BRAIN/EXT_IRQ_5) + (net 191 /s_BRAIN/EXT_IRQ_4) + (net 192 /s_BRAIN/EXT_IRQ_3) + (net 193 /s_BRAIN/EXT_IRQ_2) + (net 194 /s_BRAIN/EXT_IRQ_1) + (net 195 /s_BRAIN/EXT_IRQ_0) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net /DEBUG_RX) + (add_net /DEBUG_TX) + (add_net /MASTER_I2C_SCL) + (add_net /MASTER_I2C_SDA) + (add_net /MASTER_SPI_CLK) + (add_net /MASTER_SPI_MISO) + (add_net /MASTER_SPI_MOSI) + (add_net /s_BRAIN/EXT_IRQ_0) + (add_net /s_BRAIN/EXT_IRQ_1) + (add_net /s_BRAIN/EXT_IRQ_2) + (add_net /s_BRAIN/EXT_IRQ_3) + (add_net /s_BRAIN/EXT_IRQ_4) + (add_net /s_BRAIN/EXT_IRQ_5) + (add_net /s_BRAIN/SWCLK) + (add_net /s_BRAIN/SWDIO) + (add_net /s_BRAIN/SWO) + (add_net /s_BRAIN/~SYS_RST) + (add_net /s_Power/USB_3v3) + (add_net /s_Power/USB_5v) + (add_net /s_Power/Wall_5V) + (add_net /s_SCREEN_INTF/D0) + (add_net /s_SCREEN_INTF/D1) + (add_net /s_SCREEN_INTF/D10) + (add_net /s_SCREEN_INTF/D11) + (add_net /s_SCREEN_INTF/D12) + (add_net /s_SCREEN_INTF/D13) + (add_net /s_SCREEN_INTF/D14) + (add_net /s_SCREEN_INTF/D15) + (add_net /s_SCREEN_INTF/D16) + (add_net /s_SCREEN_INTF/D17) + (add_net /s_SCREEN_INTF/D18) + (add_net /s_SCREEN_INTF/D19) + (add_net /s_SCREEN_INTF/D2) + (add_net /s_SCREEN_INTF/D20) + (add_net /s_SCREEN_INTF/D21) + (add_net /s_SCREEN_INTF/D22) + (add_net /s_SCREEN_INTF/D23) + (add_net /s_SCREEN_INTF/D3) + (add_net /s_SCREEN_INTF/D4) + (add_net /s_SCREEN_INTF/D5) + (add_net /s_SCREEN_INTF/D6) + (add_net /s_SCREEN_INTF/D7) + (add_net /s_SCREEN_INTF/D8) + (add_net /s_SCREEN_INTF/D9) + (add_net /s_SCREEN_INTF/TFT_RSDC) + (add_net /s_SCREEN_INTF/TFT_STB) + (add_net /s_SCREEN_INTF/TFT_TE) + (add_net /s_SCREEN_INTF/TFT_TOUCH_INT) + (add_net /s_SCREEN_INTF/~IO_EXPANDER_CS) + (add_net /s_SCREEN_INTF/~TFT_RD) + (add_net /s_SCREEN_INTF/~TFT_RST) + (add_net /s_SCREEN_INTF/~TFT_WR) + (add_net /s_USB_INTF.sch/FTDI_3V3) + (add_net /s_USB_INTF.sch/FTDI_5V) + (add_net /s_USB_INTF.sch/USB_D+) + (add_net /s_USB_INTF.sch/USB_D-) + (add_net /~TFT_CS) + (add_net GND) + (add_net "Net-(C1-Pad2)") + (add_net "Net-(C10-Pad1)") + (add_net "Net-(C2-Pad1)") + (add_net "Net-(C4-Pad2)") + (add_net "Net-(C5-Pad2)") + (add_net "Net-(C7-Pad1)") + (add_net "Net-(J1-Pad4)") + (add_net "Net-(J2-Pad1)") + (add_net "Net-(J2-Pad7)") + (add_net "Net-(J2-Pad8)") + (add_net "Net-(J3-Pad38)") + (add_net "Net-(J3-Pad39)") + (add_net "Net-(J3-Pad40)") + (add_net "Net-(J3-Pad6)") + (add_net "Net-(J4-Pad3)") + (add_net "Net-(Q1-Pad3)") + (add_net "Net-(Q2-Pad3)") + (add_net "Net-(R1-Pad1)") + (add_net "Net-(U1-Pad10)") + (add_net "Net-(U1-Pad102)") + (add_net "Net-(U1-Pad103)") + (add_net "Net-(U1-Pad104)") + (add_net "Net-(U1-Pad105)") + (add_net "Net-(U1-Pad107)") + (add_net "Net-(U1-Pad108)") + (add_net "Net-(U1-Pad109)") + (add_net "Net-(U1-Pad110)") + (add_net "Net-(U1-Pad111)") + (add_net "Net-(U1-Pad112)") + (add_net "Net-(U1-Pad113)") + (add_net "Net-(U1-Pad114)") + (add_net "Net-(U1-Pad115)") + (add_net "Net-(U1-Pad116)") + (add_net "Net-(U1-Pad117)") + (add_net "Net-(U1-Pad119)") + (add_net "Net-(U1-Pad120)") + (add_net "Net-(U1-Pad121)") + (add_net "Net-(U1-Pad122)") + (add_net "Net-(U1-Pad123)") + (add_net "Net-(U1-Pad124)") + (add_net "Net-(U1-Pad13)") + (add_net "Net-(U1-Pad14)") + (add_net "Net-(U1-Pad15)") + (add_net "Net-(U1-Pad16)") + (add_net "Net-(U1-Pad18)") + (add_net "Net-(U1-Pad19)") + (add_net "Net-(U1-Pad20)") + (add_net "Net-(U1-Pad24)") + (add_net "Net-(U1-Pad26)") + (add_net "Net-(U1-Pad27)") + (add_net "Net-(U1-Pad28)") + (add_net "Net-(U1-Pad29)") + (add_net "Net-(U1-Pad3)") + (add_net "Net-(U1-Pad30)") + (add_net "Net-(U1-Pad32)") + (add_net "Net-(U1-Pad33)") + (add_net "Net-(U1-Pad34)") + (add_net "Net-(U1-Pad35)") + (add_net "Net-(U1-Pad36)") + (add_net "Net-(U1-Pad37)") + (add_net "Net-(U1-Pad39)") + (add_net "Net-(U1-Pad4)") + (add_net "Net-(U1-Pad40)") + (add_net "Net-(U1-Pad41)") + (add_net "Net-(U1-Pad42)") + (add_net "Net-(U1-Pad43)") + (add_net "Net-(U1-Pad44)") + (add_net "Net-(U1-Pad47)") + (add_net "Net-(U1-Pad48)") + (add_net "Net-(U1-Pad49)") + (add_net "Net-(U1-Pad5)") + (add_net "Net-(U1-Pad50)") + (add_net "Net-(U1-Pad51)") + (add_net "Net-(U1-Pad52)") + (add_net "Net-(U1-Pad55)") + (add_net "Net-(U1-Pad56)") + (add_net "Net-(U1-Pad57)") + (add_net "Net-(U1-Pad58)") + (add_net "Net-(U1-Pad59)") + (add_net "Net-(U1-Pad6)") + (add_net "Net-(U1-Pad60)") + (add_net "Net-(U1-Pad61)") + (add_net "Net-(U1-Pad68)") + (add_net "Net-(U1-Pad69)") + (add_net "Net-(U1-Pad7)") + (add_net "Net-(U1-Pad70)") + (add_net "Net-(U1-Pad71)") + (add_net "Net-(U1-Pad72)") + (add_net "Net-(U1-Pad73)") + (add_net "Net-(U1-Pad74)") + (add_net "Net-(U1-Pad75)") + (add_net "Net-(U1-Pad76)") + (add_net "Net-(U1-Pad77)") + (add_net "Net-(U1-Pad8)") + (add_net "Net-(U1-Pad80)") + (add_net "Net-(U1-Pad81)") + (add_net "Net-(U1-Pad82)") + (add_net "Net-(U1-Pad83)") + (add_net "Net-(U1-Pad84)") + (add_net "Net-(U1-Pad85)") + (add_net "Net-(U1-Pad86)") + (add_net "Net-(U1-Pad87)") + (add_net "Net-(U1-Pad88)") + (add_net "Net-(U1-Pad89)") + (add_net "Net-(U1-Pad9)") + (add_net "Net-(U1-Pad92)") + (add_net "Net-(U1-Pad93)") + (add_net "Net-(U1-Pad94)") + (add_net "Net-(U1-Pad95)") + (add_net "Net-(U1-Pad98)") + (add_net "Net-(U1-Pad99)") + (add_net "Net-(U2-Pad10)") + (add_net "Net-(U2-Pad11)") + (add_net "Net-(U2-Pad12)") + (add_net "Net-(U2-Pad13)") + (add_net "Net-(U2-Pad18)") + (add_net "Net-(U2-Pad21)") + (add_net "Net-(U2-Pad22)") + (add_net "Net-(U2-Pad23)") + (add_net "Net-(U2-Pad25)") + (add_net "Net-(U2-Pad27)") + (add_net "Net-(U2-Pad28)") + (add_net "Net-(U2-Pad29)") + (add_net "Net-(U2-Pad3)") + (add_net "Net-(U2-Pad31)") + (add_net "Net-(U2-Pad32)") + (add_net "Net-(U2-Pad5)") + (add_net "Net-(U2-Pad6)") + (add_net "Net-(U2-Pad7)") + (add_net "Net-(U2-Pad8)") + (add_net "Net-(U3-Pad29)") + (add_net "Net-(U3-Pad30)") + (add_net "Net-(U3-Pad31)") + (add_net "Net-(U3-Pad32)") + (add_net "Net-(U4-Pad3)") + (add_net "Net-(U4-Pad5)") + (add_net g_3v3) + ) + + (module digikey-footprints:Barrel_Jack_5.5mmODx2.1mmID_PJ-102A (layer F.Cu) (tedit 5CAD146F) (tstamp 5E7AD729) + (at 62.23 60.96 90) + (path /5E7872D3/5E88DD8C) + (fp_text reference J4 (at 0 -12.1 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Barrel_Jack_Switch (at 0 5.8 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -4.5 3.7) (end 4.5 3.7) (layer F.Fab) (width 0.1)) + (fp_line (start -4.5 3.7) (end -4.5 -10.7) (layer F.Fab) (width 0.1)) + (fp_line (start 4.5 3.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) + (fp_line (start -4.5 -10.7) (end 4.5 -10.7) (layer F.Fab) (width 0.1)) + (fp_line (start 4.6 3.8) (end 4.1 3.8) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 3.8) (end 4.6 3.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 3.8) (end -4.1 3.8) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 3.8) (end -4.6 3.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -1.2 -1.8) (end 1.2 -1.8) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 -10.8) (end -4.6 -10.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 -10.8) (end -4.1 -10.8) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 -10.8) (end 4.1 -10.8) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 -10.8) (end 4.6 -10.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -4.6 -3.5) (end -4.6 -4.5) (layer F.SilkS) (width 0.1)) + (fp_line (start 4.6 -3.5) (end 4.6 -4.5) (layer F.SilkS) (width 0.1)) + (fp_line (start -5.9 -10.95) (end 4.8 -10.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.9 -10.95) (end -5.9 4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.8 -10.95) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.9 4.25) (end 4.8 4.25) (layer F.CrtYd) (width 0.05)) + (pad 2 thru_hole rect (at 0 -3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 1 thru_hole rect (at 0 3 90) (size 2.6 2) (drill oval 1.6 1) (layers *.Cu *.Mask) + (net 188 /s_Power/Wall_5V)) + (pad 3 thru_hole rect (at -4.7 0 90) (size 2 2.6) (drill oval 1 1.6) (layers *.Cu *.Mask) + (net 189 "Net-(J4-Pad3)")) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6F9) + (at 72.9 97.79) + (path /5E7872D3/5E9DB598) + (attr smd) + (fp_text reference Q4 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Alt PFET_B" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6DD) + (at 68.2 97.79) + (path /5E7872D3/5E9CBFD6) + (attr smd) + (fp_text reference Q3 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Default PFET_B" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(C10-Pad1)") (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6C1) + (at 63.5 102.74) + (path /5E7872D3/5E9D56A5) + (attr smd) + (fp_text reference Q2 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Alt PFET_A" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 182 "Net-(Q2-Pad3)") (solder_mask_margin 0.07)) + ) + + (module digikey-footprints:SOT-23-3 (layer F.Cu) (tedit 5D28A5E3) (tstamp 5E7AA6A5) + (at 69.85 82.55) + (path /5E7872D3/5E9B8E9E) + (attr smd) + (fp_text reference Q1 (at 0.025 -3.375) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Default PFET_A" (at 0.025 3.25) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.7 1.52) (end 0.7 -1.52) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 1.52) (end 0.7 1.52) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -0.125 0.15) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.05))) + ) + (fp_line (start 0.825 -1.65) (end 0.825 -1.35) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.45 -1.65) (end 0.825 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.65) (end 0.375 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.35) (end 0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 0.825 1.425) (end 0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 1.65) (end -0.825 1.3) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.35 1.65) (end -0.825 1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.425 -1.525) (end -0.7 -1.325) (layer F.Fab) (width 0.1)) + (fp_line (start -0.425 -1.525) (end 0.7 -1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.7 -1.325) (end -0.7 1.525) (layer F.Fab) (width 0.1)) + (fp_line (start -0.825 -1.325) (end -1.6 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.825 -1.375) (end -0.825 -1.325) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.45 -1.65) (end -0.825 -1.375) (layer F.SilkS) (width 0.1)) + (fp_line (start -0.175 -1.65) (end -0.45 -1.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 1.825 -1.95) (end 1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.825 1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end -1.825 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.825 -1.95) (end 1.825 -1.95) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at -1.05 -0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 173 /s_Power/USB_3v3) (solder_mask_margin 0.07)) + (pad 2 smd rect (at -1.05 0.95) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 172 /s_Power/USB_5v) (solder_mask_margin 0.07)) + (pad 3 smd rect (at 1.05 0) (size 1.3 0.6) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(Q1-Pad3)") (solder_mask_margin 0.07)) + ) + + (module Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm (layer F.Cu) (tedit 5A64E13E) (tstamp 5E7A9FEB) + (at 80.01 71.12) + (descr "6-Lead Plastic Dual Flat, No Lead Package (MA) - 2x2x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "DFN 0.65") + (path /5E7872D3/5E7F2428) + (attr smd) + (fp_text reference U4 (at 0 -2.025) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value NCP349MNAETBG (at 0 2.025) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.45 -1.1) (end 0.725 -1.1) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.725 1.1) (end 0.725 1.1) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.65 1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.65 -1.25) (end 1.65 -1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.65 -1.25) (end 1.65 1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.65 -1.25) (end -1.65 1.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0) (end 0 -1) (layer F.Fab) (width 0.15)) + (fp_line (start -1 1) (end -1 0) (layer F.Fab) (width 0.15)) + (fp_line (start 1 1) (end -1 1) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -1) (end 1 1) (layer F.Fab) (width 0.15)) + (fp_line (start 0 -1) (end 1 -1) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.5 0.5) (thickness 0.075))) + ) + (pad "" smd rect (at 0 0.4) (size 0.82 0.63) (layers F.Paste)) + (pad "" smd rect (at 0 -0.4) (size 0.82 0.63) (layers F.Paste)) + (pad 7 smd rect (at 0 0) (size 1 1.6) (layers F.Cu F.Mask)) + (pad 6 smd rect (at 1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 179 "Net-(U4-Pad5)")) + (pad 5 smd rect (at 1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 179 "Net-(U4-Pad5)")) + (pad 4 smd rect (at 1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 3 smd rect (at -1.05 0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 180 "Net-(U4-Pad3)")) + (pad 2 smd rect (at -1.05 0) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 1 smd rect (at -1.05 -0.65) (size 0.65 0.35) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(C10-Pad1)")) + (model ${KISYS3DMOD}/Package_DFN_QFN.3dshapes/DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_PinHeader_1.27mm:PinHeader_2x05_P1.27mm_Vertical (layer F.Cu) (tedit 59FED6E3) (tstamp 5E75429F) + (at 128.27 83.82) + (descr "Through hole straight pin header, 2x05, 1.27mm pitch, double rows") + (tags "Through hole pin header THT 2x05 1.27mm double row") + (path /5E805E4F/5EA1E350) + (fp_text reference J2 (at 0.635 -1.695) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_ARM_JTAG_SWD_10 (at 0.635 6.775) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0.635 2.54 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.85 -1.15) (end -1.6 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.85 6.25) (end 2.85 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 6.25) (end 2.85 6.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 -1.15) (end -1.6 6.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.13 -0.76) (end 0 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 0) (end -1.13 -0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.57753 -0.695) (end 2.4 -0.695) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.76 -0.695) (end 0.96247 -0.695) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.76 -0.563471) (end 0.76 -0.695) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.76 0.706529) (end 0.76 0.563471) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.563471 0.76) (end 0.706529 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 0.76) (end -0.563471 0.76) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.4 -0.695) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 0.76) (end -1.13 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.30753 5.775) (end 0.96247 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.57753 5.775) (end 2.4 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.13 5.775) (end -0.30753 5.775) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.07 0.2175) (end -0.2175 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.07 5.715) (end -1.07 0.2175) (layer F.Fab) (width 0.1)) + (fp_line (start 2.34 5.715) (end -1.07 5.715) (layer F.Fab) (width 0.1)) + (fp_line (start 2.34 -0.635) (end 2.34 5.715) (layer F.Fab) (width 0.1)) + (fp_line (start -0.2175 -0.635) (end 2.34 -0.635) (layer F.Fab) (width 0.1)) + (pad 10 thru_hole oval (at 1.27 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 184 /s_BRAIN/~SYS_RST)) + (pad 9 thru_hole oval (at 0 5.08) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 8 thru_hole oval (at 1.27 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 2 "Net-(J2-Pad8)")) + (pad 7 thru_hole oval (at 0 3.81) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 3 "Net-(J2-Pad7)")) + (pad 6 thru_hole oval (at 1.27 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 185 /s_BRAIN/SWO)) + (pad 5 thru_hole oval (at 0 2.54) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 4 thru_hole oval (at 1.27 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 186 /s_BRAIN/SWCLK)) + (pad 3 thru_hole oval (at 0 1.27) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 2 thru_hole oval (at 1.27 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 187 /s_BRAIN/SWDIO)) + (pad 1 thru_hole rect (at 0 0) (size 1 1) (drill 0.65) (layers *.Cu *.Mask) + (net 4 "Net-(J2-Pad1)")) + (model ${KISYS3DMOD}/Connector_PinHeader_1.27mm.3dshapes/PinHeader_2x05_P1.27mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Crystal:Crystal_SMD_3215-2Pin_3.2x1.5mm (layer F.Cu) (tedit 5A0FD1B2) (tstamp 5E752FF8) + (at 63.5 86.36) + (descr "SMD Crystal FC-135 https://support.epson.biz/td/api/doc_check.php?dl=brief_FC-135R_en.pdf") + (tags "SMD SMT Crystal") + (path /5E805E4F/5E75D825) + (attr smd) + (fp_text reference Y1 (at 0 -2) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value XOSC32 (at 0 2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2 -1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2 -1.15) (end -2 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2 1.15) (end 2 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.75) (end 1.6 -0.75) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.75) (end 1.6 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start -0.675 -0.875) (end 0.675 -0.875) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.675 0.875) (end 0.675 0.875) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.6 -0.75) (end -1.6 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start -2 -1.15) (end 2 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -2) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 2 smd rect (at -1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) + (net 55 "Net-(C1-Pad2)")) + (pad 1 smd rect (at 1.25 0) (size 1 1.8) (layers F.Cu F.Paste F.Mask) + (net 131 "Net-(C2-Pad1)")) + (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_3215-2Pin_3.2x1.5mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module proj_modules:SOP80P1030X264-36N (layer F.Cu) (tedit 5E702418) (tstamp 5E752FE7) + (at 106.68 77.47) + (path /5E8589A7/5E86D6D7) + (fp_text reference U3 (at -2.415 -8.587) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.015))) + ) + (fp_text value MAX7301AAX+ (at 5.84 8.587) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.015))) + ) + (fp_line (start 5.865 -8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 -8.025) (end -5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 8.025) (end 5.865 8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.865 -8.025) (end 5.865 -8.025) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.8 -7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 -7.775) (end -3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.SilkS) (width 0.127)) + (fp_line (start -3.8 7.775) (end 3.8 7.775) (layer F.Fab) (width 0.127)) + (fp_line (start -3.8 -7.775) (end 3.8 -7.775) (layer F.Fab) (width 0.127)) + (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.Fab) (width 0.2)) + (fp_circle (center -6.51 -7.34) (end -6.41 -7.34) (layer F.SilkS) (width 0.2)) + (pad 36 smd rect (at 4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 122 g_3v3)) + (pad 35 smd rect (at 4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 167 /s_SCREEN_INTF/~IO_EXPANDER_CS)) + (pad 34 smd rect (at 4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 178 /MASTER_SPI_MOSI)) + (pad 33 smd rect (at 4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 175 /MASTER_SPI_CLK)) + (pad 32 smd rect (at 4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 123 "Net-(U3-Pad32)")) + (pad 31 smd rect (at 4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 124 "Net-(U3-Pad31)")) + (pad 30 smd rect (at 4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 125 "Net-(U3-Pad30)")) + (pad 29 smd rect (at 4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 126 "Net-(U3-Pad29)")) + (pad 28 smd rect (at 4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 137 /s_SCREEN_INTF/D23)) + (pad 27 smd rect (at 4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 138 /s_SCREEN_INTF/D22)) + (pad 26 smd rect (at 4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 139 /s_SCREEN_INTF/D21)) + (pad 25 smd rect (at 4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 140 /s_SCREEN_INTF/D20)) + (pad 24 smd rect (at 4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 141 /s_SCREEN_INTF/D19)) + (pad 23 smd rect (at 4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 142 /s_SCREEN_INTF/D18)) + (pad 22 smd rect (at 4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 143 /s_SCREEN_INTF/D17)) + (pad 21 smd rect (at 4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 144 /s_SCREEN_INTF/D16)) + (pad 20 smd rect (at 4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 145 /s_SCREEN_INTF/D15)) + (pad 19 smd rect (at 4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 146 /s_SCREEN_INTF/D14)) + (pad 18 smd rect (at -4.72 6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 147 /s_SCREEN_INTF/D13)) + (pad 17 smd rect (at -4.72 6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 148 /s_SCREEN_INTF/D12)) + (pad 16 smd rect (at -4.72 5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 149 /s_SCREEN_INTF/D11)) + (pad 15 smd rect (at -4.72 4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 150 /s_SCREEN_INTF/D10)) + (pad 14 smd rect (at -4.72 3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 151 /s_SCREEN_INTF/D9)) + (pad 13 smd rect (at -4.72 2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 152 /s_SCREEN_INTF/D8)) + (pad 12 smd rect (at -4.72 2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 153 /s_SCREEN_INTF/D7)) + (pad 11 smd rect (at -4.72 1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 154 /s_SCREEN_INTF/D6)) + (pad 10 smd rect (at -4.72 0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 155 /s_SCREEN_INTF/D5)) + (pad 9 smd rect (at -4.72 -0.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 156 /s_SCREEN_INTF/D4)) + (pad 8 smd rect (at -4.72 -1.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 157 /s_SCREEN_INTF/D3)) + (pad 7 smd rect (at -4.72 -2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 158 /s_SCREEN_INTF/D2)) + (pad 6 smd rect (at -4.72 -2.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 159 /s_SCREEN_INTF/D1)) + (pad 5 smd rect (at -4.72 -3.6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 160 /s_SCREEN_INTF/D0)) + (pad 4 smd rect (at -4.72 -4.4) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 174 /MASTER_SPI_MISO)) + (pad 3 smd rect (at -4.72 -5.2) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 2 smd rect (at -4.72 -6) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 1 smd rect (at -4.72 -6.8) (size 1.79 0.54) (layers F.Cu F.Paste F.Mask) + (net 128 "Net-(R1-Pad1)")) + ) + + (module digikey-footprints:QFN-32-1EP_5x5mm (layer F.Cu) (tedit 5D2895FE) (tstamp 5E752FB3) + (at 71.12 73.66) + (path /5E7C0F59/5E84744C) + (attr smd) + (fp_text reference U2 (at 0 -4.71) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value FT232RQ-REEL (at 0 4.51) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.98 2.05) (end -3.02 2.05) (layer F.Fab) (width 0.1)) + (fp_line (start 1.98 -2.95) (end 1.98 2.05) (layer F.Fab) (width 0.1)) + (fp_line (start 2.08 2.15) (end 1.68 2.15) (layer F.SilkS) (width 0.1)) + (fp_line (start 2.08 1.75) (end 2.08 2.15) (layer F.SilkS) (width 0.1)) + (fp_line (start 2.08 -3.05) (end 2.08 -2.65) (layer F.SilkS) (width 0.1)) + (fp_line (start 2.08 -3.05) (end 1.68 -3.05) (layer F.SilkS) (width 0.1)) + (fp_line (start -3.12 2.15) (end -3.12 1.75) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.72 2.15) (end -3.12 2.15) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.62 -2.95) (end -3.02 -2.55) (layer F.Fab) (width 0.1)) + (fp_line (start -3.02 -2.55) (end -3.02 2.05) (layer F.Fab) (width 0.1)) + (fp_line (start -2.62 -2.95) (end 1.98 -2.95) (layer F.Fab) (width 0.1)) + (fp_line (start -3.12 -2.45) (end -3.32 -2.45) (layer F.SilkS) (width 0.1)) + (fp_line (start -3.12 -2.65) (end -3.12 -2.45) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.72 -3.05) (end -3.12 -2.65) (layer F.SilkS) (width 0.1)) + (fp_line (start -2.52 -3.05) (end -2.72 -3.05) (layer F.SilkS) (width 0.1)) + (fp_text user %R (at -0.52 -0.45) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.61 2.68) (end -3.65 2.68) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.61 -3.58) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.61 -3.58) (end 2.61 2.68) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.65 2.68) (end -3.65 -3.58) (layer F.CrtYd) (width 0.05)) + (pad 32 smd rect (at -2.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 103 "Net-(U2-Pad32)") (solder_mask_margin 0.07)) + (pad 31 smd rect (at -1.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 104 "Net-(U2-Pad31)") (solder_mask_margin 0.07)) + (pad 30 smd rect (at -1.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 134 /DEBUG_RX) (solder_mask_margin 0.07)) + (pad 29 smd rect (at -0.77 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 105 "Net-(U2-Pad29)") (solder_mask_margin 0.07)) + (pad 28 smd rect (at -0.27 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 106 "Net-(U2-Pad28)") (solder_mask_margin 0.07)) + (pad 27 smd rect (at 0.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 107 "Net-(U2-Pad27)") (solder_mask_margin 0.07)) + (pad 26 smd rect (at 0.73 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 24 smd rect (at 1.955 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 23 smd rect (at 1.955 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 108 "Net-(U2-Pad23)") (solder_mask_margin 0.07)) + (pad 22 smd rect (at 1.955 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 109 "Net-(U2-Pad22)") (solder_mask_margin 0.07)) + (pad 21 smd rect (at 1.955 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 110 "Net-(U2-Pad21)") (solder_mask_margin 0.07)) + (pad 20 smd rect (at 1.955 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 19 smd rect (at 1.955 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 176 /s_USB_INTF.sch/FTDI_5V) (solder_mask_margin 0.07)) + (pad 18 smd rect (at 1.955 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 111 "Net-(U2-Pad18)") (solder_mask_margin 0.07)) + (pad 16 smd rect (at 1.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) + (pad 15 smd rect (at 0.73 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 130 /s_USB_INTF.sch/USB_D-) (solder_mask_margin 0.07)) + (pad 14 smd rect (at 0.23 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 129 /s_USB_INTF.sch/USB_D+) (solder_mask_margin 0.07)) + (pad 13 smd rect (at -0.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 112 "Net-(U2-Pad13)") (solder_mask_margin 0.07)) + (pad 12 smd rect (at -0.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 113 "Net-(U2-Pad12)") (solder_mask_margin 0.07)) + (pad 11 smd rect (at -1.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 114 "Net-(U2-Pad11)") (solder_mask_margin 0.07)) + (pad 10 smd rect (at -1.77 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 115 "Net-(U2-Pad10)") (solder_mask_margin 0.07)) + (pad 8 smd rect (at -2.995 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 116 "Net-(U2-Pad8)") (solder_mask_margin 0.07)) + (pad 7 smd rect (at -2.995 0.8 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 117 "Net-(U2-Pad7)") (solder_mask_margin 0.07)) + (pad 6 smd rect (at -2.995 0.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 118 "Net-(U2-Pad6)") (solder_mask_margin 0.07)) + (pad 5 smd rect (at -2.995 -0.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 119 "Net-(U2-Pad5)") (solder_mask_margin 0.07)) + (pad 4 smd rect (at -2.995 -0.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 3 smd rect (at -2.995 -1.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 120 "Net-(U2-Pad3)") (solder_mask_margin 0.07)) + (pad 2 smd rect (at -2.995 -1.7 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 135 /DEBUG_TX) (solder_mask_margin 0.07)) + (pad 1 smd rect (at -2.995 -2.2 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) + (pad 33 thru_hole circle (at -1.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -1.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -1.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -0.52 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -0.52 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at -0.52 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at 0.48 0.55 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at 0.48 -0.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 thru_hole circle (at 0.48 -1.45 270) (size 0.2 0.2) (drill 0.2) (layers *.Cu *.Mask) + (net 127 GND) (solder_mask_margin 0.1)) + (pad 33 smd rect (at -0.52 -0.45 270) (size 3.45 3.45) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 9 smd rect (at -2.27 2.025 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 177 /s_USB_INTF.sch/FTDI_3V3) (solder_mask_margin 0.07)) + (pad 17 smd rect (at 1.955 1.3 270) (size 0.28 0.85) (layers F.Cu F.Paste F.Mask) + (net 127 GND) (solder_mask_margin 0.07)) + (pad 25 smd rect (at 1.23 -2.925 270) (size 0.85 0.28) (layers F.Cu F.Paste F.Mask) + (net 121 "Net-(U2-Pad25)") (solder_mask_margin 0.07)) + ) + + (module penguin:QFP40P1600X1600X120-128N_ATSAME54P20A (layer F.Cu) (tedit 5E6D9777) (tstamp 5E752F71) + (at 86.36 109.22 45) + (path /5E7872D3/5E84F3B3) + (fp_text reference U1 (at -4.500975 -9.803025 45) (layer F.SilkS) + (effects (font (size 1.001331 1.001331) (thickness 0.015))) + ) + (fp_text value p_ATSAME54P20A-AU (at 6.78639 10.114365 45) (layer F.Fab) + (effects (font (size 1.002417 1.002417) (thickness 0.015))) + ) + (fp_line (start -7 7) (end -7 6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start -6.6 7) (end -7 7) (layer F.SilkS) (width 0.127)) + (fp_line (start 7 7) (end 7 6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.6 7) (end 7 7) (layer F.SilkS) (width 0.127)) + (fp_line (start 7 -7) (end 7 -6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 6.6 -7) (end 7 -7) (layer F.SilkS) (width 0.127)) + (fp_line (start -7 -7) (end -7 -6.6) (layer F.SilkS) (width 0.127)) + (fp_line (start -6.6 -7) (end -7 -7) (layer F.SilkS) (width 0.127)) + (fp_line (start 8.655 8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.655 8.655) (end -8.655 -8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.655 -8.655) (end 8.655 -8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.655 8.655) (end 8.655 8.655) (layer F.CrtYd) (width 0.05)) + (fp_line (start -7 7) (end -7 -7) (layer F.Fab) (width 0.127)) + (fp_line (start 7 7) (end 7 -7) (layer F.Fab) (width 0.127)) + (fp_line (start 7 -7) (end -7 -7) (layer F.Fab) (width 0.127)) + (fp_line (start 7 7) (end -7 7) (layer F.Fab) (width 0.127)) + (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.Fab) (width 0.1)) + (fp_circle (center -9.14 -6.44) (end -8.94 -6.44) (layer F.SilkS) (width 0.1)) + (pad 96 smd rect (at 7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 95 smd rect (at 7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 9 "Net-(U1-Pad95)")) + (pad 94 smd rect (at 7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 10 "Net-(U1-Pad94)")) + (pad 93 smd rect (at 7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 11 "Net-(U1-Pad93)")) + (pad 92 smd rect (at 7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 12 "Net-(U1-Pad92)")) + (pad 91 smd rect (at 7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 90 smd rect (at 7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 89 smd rect (at 7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 13 "Net-(U1-Pad89)")) + (pad 88 smd rect (at 7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 14 "Net-(U1-Pad88)")) + (pad 87 smd rect (at 7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 15 "Net-(U1-Pad87)")) + (pad 86 smd rect (at 7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 16 "Net-(U1-Pad86)")) + (pad 85 smd rect (at 7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 17 "Net-(U1-Pad85)")) + (pad 84 smd rect (at 7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 18 "Net-(U1-Pad84)")) + (pad 83 smd rect (at 7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 19 "Net-(U1-Pad83)")) + (pad 82 smd rect (at 7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 20 "Net-(U1-Pad82)")) + (pad 81 smd rect (at 7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 21 "Net-(U1-Pad81)")) + (pad 80 smd rect (at 7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 22 "Net-(U1-Pad80)")) + (pad 79 smd rect (at 7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 78 smd rect (at 7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 77 smd rect (at 7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 23 "Net-(U1-Pad77)")) + (pad 76 smd rect (at 7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 24 "Net-(U1-Pad76)")) + (pad 75 smd rect (at 7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 25 "Net-(U1-Pad75)")) + (pad 74 smd rect (at 7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 26 "Net-(U1-Pad74)")) + (pad 73 smd rect (at 7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 27 "Net-(U1-Pad73)")) + (pad 72 smd rect (at 7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 28 "Net-(U1-Pad72)")) + (pad 71 smd rect (at 7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 29 "Net-(U1-Pad71)")) + (pad 70 smd rect (at 7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 30 "Net-(U1-Pad70)")) + (pad 69 smd rect (at 7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 31 "Net-(U1-Pad69)")) + (pad 68 smd rect (at 7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 32 "Net-(U1-Pad68)")) + (pad 67 smd rect (at 7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 171 /MASTER_I2C_SCL)) + (pad 66 smd rect (at 7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 170 /MASTER_I2C_SDA)) + (pad 65 smd rect (at 7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 32 smd rect (at -7.67 6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 33 "Net-(U1-Pad32)")) + (pad 31 smd rect (at -7.67 5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -7.67 5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 34 "Net-(U1-Pad30)")) + (pad 29 smd rect (at -7.67 5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 35 "Net-(U1-Pad29)")) + (pad 28 smd rect (at -7.67 4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 36 "Net-(U1-Pad28)")) + (pad 27 smd rect (at -7.67 4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 37 "Net-(U1-Pad27)")) + (pad 26 smd rect (at -7.67 3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 38 "Net-(U1-Pad26)")) + (pad 25 smd rect (at -7.67 3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 45 "Net-(U1-Pad14)")) + (pad 24 smd rect (at -7.67 3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 39 "Net-(U1-Pad24)")) + (pad 23 smd rect (at -7.67 2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 174 /MASTER_SPI_MISO)) + (pad 22 smd rect (at -7.67 2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 175 /MASTER_SPI_CLK)) + (pad 21 smd rect (at -7.67 1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 174 /MASTER_SPI_MISO)) + (pad 20 smd rect (at -7.67 1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 40 "Net-(U1-Pad20)")) + (pad 19 smd rect (at -7.67 1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 41 "Net-(U1-Pad19)")) + (pad 18 smd rect (at -7.67 0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 42 "Net-(U1-Pad18)")) + (pad 17 smd rect (at -7.67 0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 190 /s_BRAIN/EXT_IRQ_5)) + (pad 16 smd rect (at -7.67 -0.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 43 "Net-(U1-Pad16)")) + (pad 15 smd rect (at -7.67 -0.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 44 "Net-(U1-Pad15)")) + (pad 14 smd rect (at -7.67 -1 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 45 "Net-(U1-Pad14)")) + (pad 13 smd rect (at -7.67 -1.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 46 "Net-(U1-Pad13)")) + (pad 12 smd rect (at -7.67 -1.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 191 /s_BRAIN/EXT_IRQ_4)) + (pad 11 smd rect (at -7.67 -2.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 192 /s_BRAIN/EXT_IRQ_3)) + (pad 10 smd rect (at -7.67 -2.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 47 "Net-(U1-Pad10)")) + (pad 9 smd rect (at -7.67 -3 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 48 "Net-(U1-Pad9)")) + (pad 8 smd rect (at -7.67 -3.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 49 "Net-(U1-Pad8)")) + (pad 7 smd rect (at -7.67 -3.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 50 "Net-(U1-Pad7)")) + (pad 6 smd rect (at -7.67 -4.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 51 "Net-(U1-Pad6)")) + (pad 5 smd rect (at -7.67 -4.6 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 52 "Net-(U1-Pad5)")) + (pad 4 smd rect (at -7.67 -5 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 53 "Net-(U1-Pad4)")) + (pad 3 smd rect (at -7.67 -5.4 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 54 "Net-(U1-Pad3)")) + (pad 2 smd rect (at -7.67 -5.8 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 131 "Net-(C2-Pad1)")) + (pad 1 smd rect (at -7.67 -6.2 45) (size 1.47 0.24) (layers F.Cu F.Paste F.Mask) + (net 55 "Net-(C1-Pad2)")) + (pad 128 smd rect (at -6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 122 g_3v3)) + (pad 127 smd rect (at -5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 193 /s_BRAIN/EXT_IRQ_2)) + (pad 126 smd rect (at -5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 194 /s_BRAIN/EXT_IRQ_1)) + (pad 125 smd rect (at -5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 195 /s_BRAIN/EXT_IRQ_0)) + (pad 124 smd rect (at -4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 56 "Net-(U1-Pad124)")) + (pad 123 smd rect (at -4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 57 "Net-(U1-Pad123)")) + (pad 122 smd rect (at -3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 58 "Net-(U1-Pad122)")) + (pad 121 smd rect (at -3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 59 "Net-(U1-Pad121)")) + (pad 120 smd rect (at -3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 60 "Net-(U1-Pad120)")) + (pad 119 smd rect (at -2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 61 "Net-(U1-Pad119)")) + (pad 118 smd rect (at -2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 117 smd rect (at -1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 62 "Net-(U1-Pad117)")) + (pad 116 smd rect (at -1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 63 "Net-(U1-Pad116)")) + (pad 115 smd rect (at -1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 64 "Net-(U1-Pad115)")) + (pad 114 smd rect (at -0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 65 "Net-(U1-Pad114)")) + (pad 113 smd rect (at -0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 66 "Net-(U1-Pad113)")) + (pad 112 smd rect (at 0.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 67 "Net-(U1-Pad112)")) + (pad 111 smd rect (at 0.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 68 "Net-(U1-Pad111)")) + (pad 110 smd rect (at 1 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 69 "Net-(U1-Pad110)")) + (pad 109 smd rect (at 1.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 70 "Net-(U1-Pad109)")) + (pad 108 smd rect (at 1.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 71 "Net-(U1-Pad108)")) + (pad 107 smd rect (at 2.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 106 smd rect (at 2.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 105 smd rect (at 3 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 73 "Net-(U1-Pad105)")) + (pad 104 smd rect (at 3.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 74 "Net-(U1-Pad104)")) + (pad 103 smd rect (at 3.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 75 "Net-(U1-Pad103)")) + (pad 102 smd rect (at 4.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 76 "Net-(U1-Pad102)")) + (pad 101 smd rect (at 4.6 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 135 /DEBUG_TX)) + (pad 100 smd rect (at 5 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 134 /DEBUG_RX)) + (pad 99 smd rect (at 5.4 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 77 "Net-(U1-Pad99)")) + (pad 98 smd rect (at 5.8 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 78 "Net-(U1-Pad98)")) + (pad 97 smd rect (at 6.2 -7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 64 smd rect (at 6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 63 smd rect (at 5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 132 "Net-(C5-Pad2)")) + (pad 62 smd rect (at 5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 133 "Net-(C4-Pad2)")) + (pad 61 smd rect (at 5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 79 "Net-(U1-Pad61)")) + (pad 60 smd rect (at 4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 80 "Net-(U1-Pad60)")) + (pad 59 smd rect (at 4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 81 "Net-(U1-Pad59)")) + (pad 58 smd rect (at 3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 82 "Net-(U1-Pad58)")) + (pad 57 smd rect (at 3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 83 "Net-(U1-Pad57)")) + (pad 56 smd rect (at 3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 84 "Net-(U1-Pad56)")) + (pad 55 smd rect (at 2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 85 "Net-(U1-Pad55)")) + (pad 54 smd rect (at 2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 53 smd rect (at 1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 52 smd rect (at 1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 86 "Net-(U1-Pad52)")) + (pad 51 smd rect (at 1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 87 "Net-(U1-Pad51)")) + (pad 50 smd rect (at 0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 88 "Net-(U1-Pad50)")) + (pad 49 smd rect (at 0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 89 "Net-(U1-Pad49)")) + (pad 48 smd rect (at -0.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 90 "Net-(U1-Pad48)")) + (pad 47 smd rect (at -0.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 91 "Net-(U1-Pad47)")) + (pad 46 smd rect (at -1 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U1-Pad107)")) + (pad 45 smd rect (at -1.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at -1.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 92 "Net-(U1-Pad44)")) + (pad 43 smd rect (at -2.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 93 "Net-(U1-Pad43)")) + (pad 42 smd rect (at -2.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 94 "Net-(U1-Pad42)")) + (pad 41 smd rect (at -3 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 95 "Net-(U1-Pad41)")) + (pad 40 smd rect (at -3.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 96 "Net-(U1-Pad40)")) + (pad 39 smd rect (at -3.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 97 "Net-(U1-Pad39)")) + (pad 38 smd rect (at -4.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd rect (at -4.6 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 98 "Net-(U1-Pad37)")) + (pad 36 smd rect (at -5 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 99 "Net-(U1-Pad36)")) + (pad 35 smd rect (at -5.4 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 100 "Net-(U1-Pad35)")) + (pad 34 smd rect (at -5.8 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 101 "Net-(U1-Pad34)")) + (pad 33 smd rect (at -6.2 7.67 45) (size 0.24 1.47) (layers F.Cu F.Paste F.Mask) + (net 102 "Net-(U1-Pad33)")) + ) + + (module Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal (layer F.Cu) (tedit 59DE239E) (tstamp 5E752EDB) + (at 78.74 64.77 90) + (descr "Through hole angled IDC box header, 2x20, 2.54mm pitch, double rows") + (tags "Through hole IDC box header THT 2x20 2.54mm double row") + (path /5E8589A7/5E858ED6) + (fp_text reference J3 (at 6.105 -6.35 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_02x20_Odd_Even_LCD_INTF (at 6.105 54.864 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 13.48 53.61) (end -1.12 53.61) (layer F.CrtYd) (width 0.05)) + (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.12 53.61) (end -1.12 -5.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.12 -5.35) (end 13.48 -5.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.13 53.61) (end 4.13 -5.35) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 53.61) (end 13.48 53.61) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 26.38) (end 13.48 26.38) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 21.88) (end 13.48 21.88) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 -5.35) (end 13.48 -5.35) (layer F.SilkS) (width 0.12)) + (fp_line (start 13.48 -5.35) (end 13.48 53.61) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.27 -1.27) (end -1.27 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.38 -5.1) (end 13.23 -5.1) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 9.84) (end -0.32 9.84) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 7.3) (end -0.32 7.3) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 53.36) (end 4.38 -4.1) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 53.36) (end 13.23 53.36) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 47.94) (end -0.32 47.94) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 45.4) (end -0.32 45.4) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 42.86) (end -0.32 42.86) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 40.32) (end -0.32 40.32) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 4.76) (end -0.32 4.76) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 37.78) (end -0.32 37.78) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 35.24) (end -0.32 35.24) (layer F.Fab) (width 0.1)) + (fp_line (start 4.38 32.7) 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1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 162 /s_SCREEN_INTF/~TFT_RD)) + (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 163 /s_SCREEN_INTF/~TFT_WR)) + (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 169 /~TFT_CS)) + (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 164 /s_SCREEN_INTF/TFT_RSDC)) + (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 165 /s_SCREEN_INTF/~TFT_RST)) + (pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 8 "Net-(J3-Pad6)")) + (pad 5 thru_hole oval (at 0 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 166 /s_SCREEN_INTF/TFT_TOUCH_INT)) + (pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 170 /MASTER_I2C_SDA)) + (pad 3 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 171 /MASTER_I2C_SCL)) + (pad 2 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask) + (net 122 g_3v3)) + (model ${KISYS3DMOD}/Connector_IDC.3dshapes/IDC-Header_2x20_P2.54mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_USB:USB_Micro-B_Wuerth_629105150521 (layer F.Cu) (tedit 5A142044) (tstamp 5E752E24) + (at 54.61 73.66 270) + (descr "USB Micro-B receptacle, http://www.mouser.com/ds/2/445/629105150521-469306.pdf") + (tags "usb micro receptacle") + (path /5E7C0F59/5E8480AD) + (attr smd) + (fp_text reference J1 (at 0 -3.5 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value USB_B_Micro (at 0 5.6 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user "PCB Edge" (at 0 3.75 90) (layer Dwgs.User) + (effects (font (size 0.5 0.5) (thickness 0.08))) + ) + (fp_text user %R (at 0 1.05 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 4.95 -3.34) (end -4.94 -3.34) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.95 4.85) (end 4.95 -3.34) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.94 4.85) (end 4.95 4.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.94 -3.34) (end -4.94 4.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -2.4) (end 2.8 -2.4) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.8 -2.4) (end -2.8 -2.4) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.8 -2.825) (end -1.8 -2.4) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.075 -2.825) (end -1.8 -2.825) (layer F.SilkS) (width 0.15)) + (fp_line (start 4.15 0.75) (end 4.15 -0.65) (layer F.SilkS) (width 0.15)) + (fp_line (start 4.15 3.3) (end 4.15 3.15) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.85 3.3) (end 4.15 3.3) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.85 3.75) (end 3.85 3.3) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.85 3.3) (end -3.85 3.75) (layer F.SilkS) (width 0.15)) + (fp_line (start -4.15 3.3) (end -3.85 3.3) (layer F.SilkS) (width 0.15)) + (fp_line (start -4.15 3.15) (end -4.15 3.3) (layer F.SilkS) (width 0.15)) + (fp_line (start -4.15 -0.65) (end -4.15 0.75) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.075 -2.95) (end -1.075 -2.725) (layer F.Fab) (width 0.15)) + (fp_line (start -1.525 -2.95) (end -1.075 -2.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.525 -2.725) (end -1.525 -2.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.3 -2.55) (end -1.525 -2.725) (layer F.Fab) (width 0.15)) + (fp_line (start -1.075 -2.725) (end -1.3 -2.55) (layer F.Fab) (width 0.15)) + (fp_line (start -2.7 3.75) (end 2.7 3.75) (layer F.Fab) (width 0.15)) + (fp_line (start 4 -2.25) (end -4 -2.25) (layer F.Fab) (width 0.15)) + (fp_line (start 4 3.15) (end 4 -2.25) (layer F.Fab) (width 0.15)) + (fp_line (start 3.7 3.15) (end 4 3.15) (layer F.Fab) (width 0.15)) + (fp_line (start 3.7 4.35) (end 3.7 3.15) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 4.35) (end 3.7 4.35) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 3.15) (end -3.7 4.35) (layer F.Fab) (width 0.15)) + (fp_line (start -4 3.15) (end -3.7 3.15) (layer F.Fab) (width 0.15)) + (fp_line (start -4 -2.25) (end -4 3.15) (layer F.Fab) (width 0.15)) + (pad "" np_thru_hole oval (at 2.5 -0.8 270) (size 0.8 0.8) (drill 0.8) (layers *.Cu *.Mask)) + (pad "" np_thru_hole oval (at -2.5 -0.8 270) (size 0.8 0.8) (drill 0.8) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 3.875 1.95 270) (size 1.15 1.8) (drill oval 0.55 1.2) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 6 thru_hole oval (at -3.875 1.95 270) (size 1.15 1.8) (drill oval 0.55 1.2) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 6 thru_hole oval (at 3.725 -1.85 270) (size 1.45 2) (drill oval 0.85 1.4) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 6 thru_hole oval (at -3.725 -1.85 270) (size 1.45 2) (drill oval 0.85 1.4) (layers *.Cu *.Mask) + (net 127 GND)) + (pad 5 smd rect (at 1.3 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 127 GND)) + (pad 4 smd rect (at 0.65 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 1 "Net-(J1-Pad4)")) + (pad 3 smd rect (at 0 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 129 /s_USB_INTF.sch/USB_D+)) + (pad 2 smd rect (at -0.65 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 130 /s_USB_INTF.sch/USB_D-)) + (pad 1 smd rect (at -1.3 -1.9 270) (size 0.45 1.3) (layers F.Cu F.Paste F.Mask) + (net 168 "Net-(C7-Pad1)")) + (model ${KISYS3DMOD}/Connector_USB.3dshapes/USB_Micro-B_Wuerth_629105150521.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_line (start 50.8 130.81) (end 50.8 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E7ADE31)) + (gr_line (start 152.4 130.81) (end 50.8 130.81) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 152.4 50.8) (end 152.4 130.81) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 53.34 50.8) (end 152.4 50.8) (layer Edge.Cuts) (width 0.05)) + (gr_line (start 50.8 50.8) (end 53.34 50.8) (layer Edge.Cuts) (width 0.05) (tstamp 5E6E9EBC)) + +) diff --git a/electrical/same54_dev_board/same54_dev_board.pro b/electrical/same54_dev_board/same54_dev_board.pro index 7d32da7..99f1738 100644 --- a/electrical/same54_dev_board/same54_dev_board.pro +++ b/electrical/same54_dev_board/same54_dev_board.pro @@ -1,43 +1,43 @@ -update=Sun 19 Apr 2020 04:53:03 PM CDT -version=1 -last_client=kicad -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -[schematic_editor] -version=1 -PageLayoutDescrFile= -PlotDirectoryName= -SubpartIdSeparator=0 -SubpartFirstId=65 -NetFmtName= -SpiceAjustPassiveValues=0 -LabSize=50 -ERC_TestSimilarLabels=1 +update=Sun 19 Apr 2020 04:53:03 PM CDT +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 diff --git a/electrical/same54_dev_board/same54_dev_board.sch b/electrical/same54_dev_board/same54_dev_board.sch index efea6bd..5c24b36 100644 --- a/electrical/same54_dev_board/same54_dev_board.sch +++ b/electrical/same54_dev_board/same54_dev_board.sch @@ -1,228 +1,228 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A 11000 8500 -encoding utf-8 -Sheet 1 5 -Title "Project Oracle" -Date "2020-03-16" -Rev "v0.1" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Sheet -S 5800 3900 3000 2000 -U 5E7872D3 -F0 "s_Power" 50 -F1 "Power.sch" 50 -$EndSheet -Text Notes 800 1500 0 50 ~ 0 -Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain. -Text GLabel 900 6250 0 50 Input ~ 0 -g_3v3 -Text GLabel 1800 6250 0 50 Input ~ 0 -g_5v -$Sheet -S 5750 850 3100 2000 -U 5E8589A7 -F0 "s_SCREEN_INTF" 50 -F1 "SCREEN_INTF.sch" 50 -F2 "MASTER_SPI_CLK" I L 5750 1100 50 -F3 "MASTER_SPI_MISO" I L 5750 1200 50 -F4 "MASTER_SPI_MOSI" I L 5750 1300 50 -F5 "~IO_EXPANDER_CS" I L 5750 1450 50 -F6 "~TFT_CS" I L 5750 1550 50 -F7 "~TFT_RD" I L 5750 1650 50 -F8 "~TFT_WR" I L 5750 1750 50 -F9 "TFT_RSDC" I L 5750 1850 50 -F10 "~TFT_RST" I L 5750 2000 50 -F11 "TFT_STB" I L 5750 2100 50 -F12 "TFT_TOUCH_SDA" I L 5750 2200 50 -F13 "TFT_TOUCH_SCL" I L 5750 2300 50 -F14 "TFT_TOUCH_INT" I L 5750 2550 50 -F15 "TFT_TE" I L 5750 2650 50 -$EndSheet -Wire Wire Line - 900 6250 950 6250 -$Comp -L power:+3V3 #PWR0101 -U 1 1 5E97BC15 -P 1200 6250 -F 0 "#PWR0101" H 1200 6100 50 0001 C CNN -F 1 "+3V3" H 1215 6423 50 0000 C CNN -F 2 "" H 1200 6250 50 0001 C CNN -F 3 "" H 1200 6250 50 0001 C CNN - 1 1200 6250 - 1 0 0 -1 -$EndComp -$Comp -L power:+5V #PWR0102 -U 1 1 5E97C21D -P 2150 6250 -F 0 "#PWR0102" H 2150 6100 50 0001 C CNN -F 1 "+5V" H 2165 6423 50 0000 C CNN -F 2 "" H 2150 6250 50 0001 C CNN -F 3 "" H 2150 6250 50 0001 C CNN - 1 2150 6250 - 1 0 0 -1 -$EndComp -$Comp -L power:PWR_FLAG #FLG0101 -U 1 1 5E97C674 -P 950 5850 -F 0 "#FLG0101" H 950 5925 50 0001 C CNN -F 1 "PWR_FLAG" H 950 6023 50 0000 C CNN -F 2 "" H 950 5850 50 0001 C CNN -F 3 "~" H 950 5850 50 0001 C CNN - 1 950 5850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 950 6250 950 5850 -Connection ~ 950 6250 -Wire Wire Line - 950 6250 1200 6250 -$Comp -L power:GND #PWR0103 -U 1 1 5E97DBEE -P 2600 6250 -F 0 "#PWR0103" H 2600 6000 50 0001 C CNN -F 1 "GND" H 2605 6077 50 0000 C CNN -F 2 "" H 2600 6250 50 0001 C CNN -F 3 "" H 2600 6250 50 0001 C CNN - 1 2600 6250 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1800 6250 1900 6250 -$Comp -L power:PWR_FLAG #FLG0102 -U 1 1 5E97F87F -P 1900 5850 -F 0 "#FLG0102" H 1900 5925 50 0001 C CNN -F 1 "PWR_FLAG" H 1900 6023 50 0000 C CNN -F 2 "" H 1900 5850 50 0001 C CNN -F 3 "~" H 1900 5850 50 0001 C CNN - 1 1900 5850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1900 6250 1900 5850 -Connection ~ 1900 6250 -Wire Wire Line - 1900 6250 2150 6250 -$Comp -L power:PWR_FLAG #FLG0103 -U 1 1 5E980A5B -P 2600 5850 -F 0 "#FLG0103" H 2600 5925 50 0001 C CNN -F 1 "PWR_FLAG" H 2600 6023 50 0000 C CNN -F 2 "" H 2600 5850 50 0001 C CNN -F 3 "~" H 2600 5850 50 0001 C CNN - 1 2600 5850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2600 6250 2600 5850 -Text Label 4050 1150 0 50 ~ 0 -DEBUG_TX -Wire Wire Line - 4000 1150 4050 1150 -Wire Wire Line - 4000 1250 4050 1250 -Text Label 4050 1250 0 50 ~ 0 -DEBUG_RX -Wire Wire Line - 4000 1350 4050 1350 -Wire Wire Line - 4000 1450 4050 1450 -Wire Wire Line - 4000 1550 4050 1550 -Wire Wire Line - 4000 1650 4050 1650 -Wire Wire Line - 4000 1750 4050 1750 -Wire Wire Line - 4000 1850 4050 1850 -Wire Wire Line - 4000 1950 4050 1950 -Wire Wire Line - 4000 2050 4050 2050 -Text Label 4050 1350 0 50 ~ 0 -MASTER_SPI_MOSI -Text Label 4050 1450 0 50 ~ 0 -MASTER_SPI_MISO -Text Label 4050 1550 0 50 ~ 0 -MASTER_SPI_CLK -Text Label 4050 1650 0 50 ~ 0 -~TFT_CS -Text Label 5700 1300 2 50 ~ 0 -MASTER_SPI_MOSI -Wire Wire Line - 5700 1200 5750 1200 -Text Label 5700 1200 2 50 ~ 0 -MASTER_SPI_MISO -Wire Wire Line - 5700 1300 5750 1300 -Text Label 5700 1100 2 50 ~ 0 -MASTER_SPI_CLK -Wire Wire Line - 5700 1100 5750 1100 -Text Label 5700 1550 2 50 ~ 0 -~TFT_CS -Wire Wire Line - 5700 1550 5750 1550 -Text Label 4050 1950 0 50 ~ 0 -MASTER_I2C_SDA -Text Label 4050 2050 0 50 ~ 0 -MASTER_I2C_SCL -Text Label 5700 2200 2 50 ~ 0 -MASTER_I2C_SDA -Text Label 5700 2300 2 50 ~ 0 -MASTER_I2C_SCL -Wire Wire Line - 5750 2200 5700 2200 -Wire Wire Line - 5750 2300 5700 2300 -Wire Wire Line - 3950 3550 4050 3550 -Wire Wire Line - 3950 3450 4050 3450 -Text Label 4050 3550 0 50 ~ 0 -DEBUG_RX -Text Label 4050 3450 0 50 ~ 0 -DEBUG_TX -$Sheet -S 650 3350 3300 1900 -U 5E7C0F59 -F0 "s_USB_INTF.sch" 50 -F1 "USB_INTF.sch" 50 -F2 "DEBUG_TX" I R 3950 3450 50 -F3 "DEBUG_RX" I R 3950 3550 50 -F4 "FTDI_5V" I R 3950 3750 50 -F5 "FTDI_3V3" I R 3950 3850 50 -$EndSheet -$Sheet -S 750 800 3250 2350 -U 5E805E4F -F0 "s_BRAIN" 50 -F1 "BRAIN.sch" 50 -F2 "DEBUG_TX" I R 4000 1150 50 -F3 "DEBUG_RX" I R 4000 1250 50 -F4 "MASTER_SPI_MOSI" I R 4000 1350 50 -F5 "MASTER_SPI_MISO" I R 4000 1450 50 -F6 "MASTER_SPI_CLK" I R 4000 1550 50 -F7 "~FLASH_MEM_CS" I R 4000 1750 50 -F8 "MASTER_I2C_SDA" I R 4000 1950 50 -F9 "MASTER_I2C_SCL" I R 4000 2050 50 -F10 "~IO_EXPANDER_CS" I R 4000 1850 50 -F11 "~TFT_CS" I R 4000 1650 50 -F12 "~TFT_WR" I R 4000 2150 50 -F13 "~TFT_RD" I R 4000 2250 50 -F14 "TFT_RSDC" I R 4000 2350 50 -F15 "~TFT_RST" I R 4000 2450 50 -$EndSheet -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A 11000 8500 +encoding utf-8 +Sheet 1 5 +Title "Project Oracle" +Date "2020-03-16" +Rev "v0.1" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Sheet +S 5800 3900 3000 2000 +U 5E7872D3 +F0 "s_Power" 50 +F1 "Power.sch" 50 +$EndSheet +Text Notes 800 1500 0 50 ~ 0 +Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain. +Text GLabel 900 6250 0 50 Input ~ 0 +g_3v3 +Text GLabel 1800 6250 0 50 Input ~ 0 +g_5v +$Sheet +S 5750 850 3100 2000 +U 5E8589A7 +F0 "s_SCREEN_INTF" 50 +F1 "SCREEN_INTF.sch" 50 +F2 "MASTER_SPI_CLK" I L 5750 1100 50 +F3 "MASTER_SPI_MISO" I L 5750 1200 50 +F4 "MASTER_SPI_MOSI" I L 5750 1300 50 +F5 "~IO_EXPANDER_CS" I L 5750 1450 50 +F6 "~TFT_CS" I L 5750 1550 50 +F7 "~TFT_RD" I L 5750 1650 50 +F8 "~TFT_WR" I L 5750 1750 50 +F9 "TFT_RSDC" I L 5750 1850 50 +F10 "~TFT_RST" I L 5750 2000 50 +F11 "TFT_STB" I L 5750 2100 50 +F12 "TFT_TOUCH_SDA" I L 5750 2200 50 +F13 "TFT_TOUCH_SCL" I L 5750 2300 50 +F14 "TFT_TOUCH_INT" I L 5750 2550 50 +F15 "TFT_TE" I L 5750 2650 50 +$EndSheet +Wire Wire Line + 900 6250 950 6250 +$Comp +L power:+3V3 #PWR0101 +U 1 1 5E97BC15 +P 1200 6250 +F 0 "#PWR0101" H 1200 6100 50 0001 C CNN +F 1 "+3V3" H 1215 6423 50 0000 C CNN +F 2 "" H 1200 6250 50 0001 C CNN +F 3 "" H 1200 6250 50 0001 C CNN + 1 1200 6250 + 1 0 0 -1 +$EndComp +$Comp +L power:+5V #PWR0102 +U 1 1 5E97C21D +P 2150 6250 +F 0 "#PWR0102" H 2150 6100 50 0001 C CNN +F 1 "+5V" H 2165 6423 50 0000 C CNN +F 2 "" H 2150 6250 50 0001 C CNN +F 3 "" H 2150 6250 50 0001 C CNN + 1 2150 6250 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5E97C674 +P 950 5850 +F 0 "#FLG0101" H 950 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 950 6023 50 0000 C CNN +F 2 "" H 950 5850 50 0001 C CNN +F 3 "~" H 950 5850 50 0001 C CNN + 1 950 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 6250 950 5850 +Connection ~ 950 6250 +Wire Wire Line + 950 6250 1200 6250 +$Comp +L power:GND #PWR0103 +U 1 1 5E97DBEE +P 2600 6250 +F 0 "#PWR0103" H 2600 6000 50 0001 C CNN +F 1 "GND" H 2605 6077 50 0000 C CNN +F 2 "" H 2600 6250 50 0001 C CNN +F 3 "" H 2600 6250 50 0001 C CNN + 1 2600 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1800 6250 1900 6250 +$Comp +L power:PWR_FLAG #FLG0102 +U 1 1 5E97F87F +P 1900 5850 +F 0 "#FLG0102" H 1900 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 1900 6023 50 0000 C CNN +F 2 "" H 1900 5850 50 0001 C CNN +F 3 "~" H 1900 5850 50 0001 C CNN + 1 1900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 6250 1900 5850 +Connection ~ 1900 6250 +Wire Wire Line + 1900 6250 2150 6250 +$Comp +L power:PWR_FLAG #FLG0103 +U 1 1 5E980A5B +P 2600 5850 +F 0 "#FLG0103" H 2600 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 2600 6023 50 0000 C CNN +F 2 "" H 2600 5850 50 0001 C CNN +F 3 "~" H 2600 5850 50 0001 C CNN + 1 2600 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 6250 2600 5850 +Text Label 4050 1150 0 50 ~ 0 +DEBUG_TX +Wire Wire Line + 4000 1150 4050 1150 +Wire Wire Line + 4000 1250 4050 1250 +Text Label 4050 1250 0 50 ~ 0 +DEBUG_RX +Wire Wire Line + 4000 1350 4050 1350 +Wire Wire Line + 4000 1450 4050 1450 +Wire Wire Line + 4000 1550 4050 1550 +Wire Wire Line + 4000 1650 4050 1650 +Wire Wire Line + 4000 1750 4050 1750 +Wire Wire Line + 4000 1850 4050 1850 +Wire Wire Line + 4000 1950 4050 1950 +Wire Wire Line + 4000 2050 4050 2050 +Text Label 4050 1350 0 50 ~ 0 +MASTER_SPI_MOSI +Text Label 4050 1450 0 50 ~ 0 +MASTER_SPI_MISO +Text Label 4050 1550 0 50 ~ 0 +MASTER_SPI_CLK +Text Label 4050 1650 0 50 ~ 0 +~TFT_CS +Text Label 5700 1300 2 50 ~ 0 +MASTER_SPI_MOSI +Wire Wire Line + 5700 1200 5750 1200 +Text Label 5700 1200 2 50 ~ 0 +MASTER_SPI_MISO +Wire Wire Line + 5700 1300 5750 1300 +Text Label 5700 1100 2 50 ~ 0 +MASTER_SPI_CLK +Wire Wire Line + 5700 1100 5750 1100 +Text Label 5700 1550 2 50 ~ 0 +~TFT_CS +Wire Wire Line + 5700 1550 5750 1550 +Text Label 4050 1950 0 50 ~ 0 +MASTER_I2C_SDA +Text Label 4050 2050 0 50 ~ 0 +MASTER_I2C_SCL +Text Label 5700 2200 2 50 ~ 0 +MASTER_I2C_SDA +Text Label 5700 2300 2 50 ~ 0 +MASTER_I2C_SCL +Wire Wire Line + 5750 2200 5700 2200 +Wire Wire Line + 5750 2300 5700 2300 +Wire Wire Line + 3950 3550 4050 3550 +Wire Wire Line + 3950 3450 4050 3450 +Text Label 4050 3550 0 50 ~ 0 +DEBUG_RX +Text Label 4050 3450 0 50 ~ 0 +DEBUG_TX +$Sheet +S 650 3350 3300 1900 +U 5E7C0F59 +F0 "s_USB_INTF.sch" 50 +F1 "USB_INTF.sch" 50 +F2 "DEBUG_TX" I R 3950 3450 50 +F3 "DEBUG_RX" I R 3950 3550 50 +F4 "FTDI_5V" I R 3950 3750 50 +F5 "FTDI_3V3" I R 3950 3850 50 +$EndSheet +$Sheet +S 750 800 3250 2350 +U 5E805E4F +F0 "s_BRAIN" 50 +F1 "BRAIN.sch" 50 +F2 "DEBUG_TX" I R 4000 1150 50 +F3 "DEBUG_RX" I R 4000 1250 50 +F4 "MASTER_SPI_MOSI" I R 4000 1350 50 +F5 "MASTER_SPI_MISO" I R 4000 1450 50 +F6 "MASTER_SPI_CLK" I R 4000 1550 50 +F7 "~FLASH_MEM_CS" I R 4000 1750 50 +F8 "MASTER_I2C_SDA" I R 4000 1950 50 +F9 "MASTER_I2C_SCL" I R 4000 2050 50 +F10 "~IO_EXPANDER_CS" I R 4000 1850 50 +F11 "~TFT_CS" I R 4000 1650 50 +F12 "~TFT_WR" I R 4000 2150 50 +F13 "~TFT_RD" I R 4000 2250 50 +F14 "TFT_RSDC" I R 4000 2350 50 +F15 "~TFT_RST" I R 4000 2450 50 +$EndSheet +$EndSCHEMATC diff --git a/electrical/same54_dev_board/same54_dev_board.sch-bak b/electrical/same54_dev_board/same54_dev_board.sch-bak index efea6bd..5c24b36 100644 --- a/electrical/same54_dev_board/same54_dev_board.sch-bak +++ b/electrical/same54_dev_board/same54_dev_board.sch-bak @@ -1,228 +1,228 @@ -EESchema Schematic File Version 4 -EELAYER 30 0 -EELAYER END -$Descr A 11000 8500 -encoding utf-8 -Sheet 1 5 -Title "Project Oracle" -Date "2020-03-16" -Rev "v0.1" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Sheet -S 5800 3900 3000 2000 -U 5E7872D3 -F0 "s_Power" 50 -F1 "Power.sch" 50 -$EndSheet -Text Notes 800 1500 0 50 ~ 0 -Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain. -Text GLabel 900 6250 0 50 Input ~ 0 -g_3v3 -Text GLabel 1800 6250 0 50 Input ~ 0 -g_5v -$Sheet -S 5750 850 3100 2000 -U 5E8589A7 -F0 "s_SCREEN_INTF" 50 -F1 "SCREEN_INTF.sch" 50 -F2 "MASTER_SPI_CLK" I L 5750 1100 50 -F3 "MASTER_SPI_MISO" I L 5750 1200 50 -F4 "MASTER_SPI_MOSI" I L 5750 1300 50 -F5 "~IO_EXPANDER_CS" I L 5750 1450 50 -F6 "~TFT_CS" I L 5750 1550 50 -F7 "~TFT_RD" I L 5750 1650 50 -F8 "~TFT_WR" I L 5750 1750 50 -F9 "TFT_RSDC" I L 5750 1850 50 -F10 "~TFT_RST" I L 5750 2000 50 -F11 "TFT_STB" I L 5750 2100 50 -F12 "TFT_TOUCH_SDA" I L 5750 2200 50 -F13 "TFT_TOUCH_SCL" I L 5750 2300 50 -F14 "TFT_TOUCH_INT" I L 5750 2550 50 -F15 "TFT_TE" I L 5750 2650 50 -$EndSheet -Wire Wire Line - 900 6250 950 6250 -$Comp -L power:+3V3 #PWR0101 -U 1 1 5E97BC15 -P 1200 6250 -F 0 "#PWR0101" H 1200 6100 50 0001 C CNN -F 1 "+3V3" H 1215 6423 50 0000 C CNN -F 2 "" H 1200 6250 50 0001 C CNN -F 3 "" H 1200 6250 50 0001 C CNN - 1 1200 6250 - 1 0 0 -1 -$EndComp -$Comp -L power:+5V #PWR0102 -U 1 1 5E97C21D -P 2150 6250 -F 0 "#PWR0102" H 2150 6100 50 0001 C CNN -F 1 "+5V" H 2165 6423 50 0000 C CNN -F 2 "" H 2150 6250 50 0001 C CNN -F 3 "" H 2150 6250 50 0001 C CNN - 1 2150 6250 - 1 0 0 -1 -$EndComp -$Comp -L power:PWR_FLAG #FLG0101 -U 1 1 5E97C674 -P 950 5850 -F 0 "#FLG0101" H 950 5925 50 0001 C CNN -F 1 "PWR_FLAG" H 950 6023 50 0000 C CNN -F 2 "" H 950 5850 50 0001 C CNN -F 3 "~" H 950 5850 50 0001 C CNN - 1 950 5850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 950 6250 950 5850 -Connection ~ 950 6250 -Wire Wire Line - 950 6250 1200 6250 -$Comp -L power:GND #PWR0103 -U 1 1 5E97DBEE -P 2600 6250 -F 0 "#PWR0103" H 2600 6000 50 0001 C CNN -F 1 "GND" H 2605 6077 50 0000 C CNN -F 2 "" H 2600 6250 50 0001 C CNN -F 3 "" H 2600 6250 50 0001 C CNN - 1 2600 6250 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1800 6250 1900 6250 -$Comp -L power:PWR_FLAG #FLG0102 -U 1 1 5E97F87F -P 1900 5850 -F 0 "#FLG0102" H 1900 5925 50 0001 C CNN -F 1 "PWR_FLAG" H 1900 6023 50 0000 C CNN -F 2 "" H 1900 5850 50 0001 C CNN -F 3 "~" H 1900 5850 50 0001 C CNN - 1 1900 5850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1900 6250 1900 5850 -Connection ~ 1900 6250 -Wire Wire Line - 1900 6250 2150 6250 -$Comp -L power:PWR_FLAG #FLG0103 -U 1 1 5E980A5B -P 2600 5850 -F 0 "#FLG0103" H 2600 5925 50 0001 C CNN -F 1 "PWR_FLAG" H 2600 6023 50 0000 C CNN -F 2 "" H 2600 5850 50 0001 C CNN -F 3 "~" H 2600 5850 50 0001 C CNN - 1 2600 5850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2600 6250 2600 5850 -Text Label 4050 1150 0 50 ~ 0 -DEBUG_TX -Wire Wire Line - 4000 1150 4050 1150 -Wire Wire Line - 4000 1250 4050 1250 -Text Label 4050 1250 0 50 ~ 0 -DEBUG_RX -Wire Wire Line - 4000 1350 4050 1350 -Wire Wire Line - 4000 1450 4050 1450 -Wire Wire Line - 4000 1550 4050 1550 -Wire Wire Line - 4000 1650 4050 1650 -Wire Wire Line - 4000 1750 4050 1750 -Wire Wire Line - 4000 1850 4050 1850 -Wire Wire Line - 4000 1950 4050 1950 -Wire Wire Line - 4000 2050 4050 2050 -Text Label 4050 1350 0 50 ~ 0 -MASTER_SPI_MOSI -Text Label 4050 1450 0 50 ~ 0 -MASTER_SPI_MISO -Text Label 4050 1550 0 50 ~ 0 -MASTER_SPI_CLK -Text Label 4050 1650 0 50 ~ 0 -~TFT_CS -Text Label 5700 1300 2 50 ~ 0 -MASTER_SPI_MOSI -Wire Wire Line - 5700 1200 5750 1200 -Text Label 5700 1200 2 50 ~ 0 -MASTER_SPI_MISO -Wire Wire Line - 5700 1300 5750 1300 -Text Label 5700 1100 2 50 ~ 0 -MASTER_SPI_CLK -Wire Wire Line - 5700 1100 5750 1100 -Text Label 5700 1550 2 50 ~ 0 -~TFT_CS -Wire Wire Line - 5700 1550 5750 1550 -Text Label 4050 1950 0 50 ~ 0 -MASTER_I2C_SDA -Text Label 4050 2050 0 50 ~ 0 -MASTER_I2C_SCL -Text Label 5700 2200 2 50 ~ 0 -MASTER_I2C_SDA -Text Label 5700 2300 2 50 ~ 0 -MASTER_I2C_SCL -Wire Wire Line - 5750 2200 5700 2200 -Wire Wire Line - 5750 2300 5700 2300 -Wire Wire Line - 3950 3550 4050 3550 -Wire Wire Line - 3950 3450 4050 3450 -Text Label 4050 3550 0 50 ~ 0 -DEBUG_RX -Text Label 4050 3450 0 50 ~ 0 -DEBUG_TX -$Sheet -S 650 3350 3300 1900 -U 5E7C0F59 -F0 "s_USB_INTF.sch" 50 -F1 "USB_INTF.sch" 50 -F2 "DEBUG_TX" I R 3950 3450 50 -F3 "DEBUG_RX" I R 3950 3550 50 -F4 "FTDI_5V" I R 3950 3750 50 -F5 "FTDI_3V3" I R 3950 3850 50 -$EndSheet -$Sheet -S 750 800 3250 2350 -U 5E805E4F -F0 "s_BRAIN" 50 -F1 "BRAIN.sch" 50 -F2 "DEBUG_TX" I R 4000 1150 50 -F3 "DEBUG_RX" I R 4000 1250 50 -F4 "MASTER_SPI_MOSI" I R 4000 1350 50 -F5 "MASTER_SPI_MISO" I R 4000 1450 50 -F6 "MASTER_SPI_CLK" I R 4000 1550 50 -F7 "~FLASH_MEM_CS" I R 4000 1750 50 -F8 "MASTER_I2C_SDA" I R 4000 1950 50 -F9 "MASTER_I2C_SCL" I R 4000 2050 50 -F10 "~IO_EXPANDER_CS" I R 4000 1850 50 -F11 "~TFT_CS" I R 4000 1650 50 -F12 "~TFT_WR" I R 4000 2150 50 -F13 "~TFT_RD" I R 4000 2250 50 -F14 "TFT_RSDC" I R 4000 2350 50 -F15 "~TFT_RST" I R 4000 2450 50 -$EndSheet -$EndSCHEMATC +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A 11000 8500 +encoding utf-8 +Sheet 1 5 +Title "Project Oracle" +Date "2020-03-16" +Rev "v0.1" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Sheet +S 5800 3900 3000 2000 +U 5E7872D3 +F0 "s_Power" 50 +F1 "Power.sch" 50 +$EndSheet +Text Notes 800 1500 0 50 ~ 0 +Brain -- ATSAME54P20A will controll peripherals, \nincluding an IO extender which,\n will handler the control of the screen \n(mikroe board with SSD1963)\n\n\nEverything in this schematic is relative to the \nbrain. As in, MASTER means brain. +Text GLabel 900 6250 0 50 Input ~ 0 +g_3v3 +Text GLabel 1800 6250 0 50 Input ~ 0 +g_5v +$Sheet +S 5750 850 3100 2000 +U 5E8589A7 +F0 "s_SCREEN_INTF" 50 +F1 "SCREEN_INTF.sch" 50 +F2 "MASTER_SPI_CLK" I L 5750 1100 50 +F3 "MASTER_SPI_MISO" I L 5750 1200 50 +F4 "MASTER_SPI_MOSI" I L 5750 1300 50 +F5 "~IO_EXPANDER_CS" I L 5750 1450 50 +F6 "~TFT_CS" I L 5750 1550 50 +F7 "~TFT_RD" I L 5750 1650 50 +F8 "~TFT_WR" I L 5750 1750 50 +F9 "TFT_RSDC" I L 5750 1850 50 +F10 "~TFT_RST" I L 5750 2000 50 +F11 "TFT_STB" I L 5750 2100 50 +F12 "TFT_TOUCH_SDA" I L 5750 2200 50 +F13 "TFT_TOUCH_SCL" I L 5750 2300 50 +F14 "TFT_TOUCH_INT" I L 5750 2550 50 +F15 "TFT_TE" I L 5750 2650 50 +$EndSheet +Wire Wire Line + 900 6250 950 6250 +$Comp +L power:+3V3 #PWR0101 +U 1 1 5E97BC15 +P 1200 6250 +F 0 "#PWR0101" H 1200 6100 50 0001 C CNN +F 1 "+3V3" H 1215 6423 50 0000 C CNN +F 2 "" H 1200 6250 50 0001 C CNN +F 3 "" H 1200 6250 50 0001 C CNN + 1 1200 6250 + 1 0 0 -1 +$EndComp +$Comp +L power:+5V #PWR0102 +U 1 1 5E97C21D +P 2150 6250 +F 0 "#PWR0102" H 2150 6100 50 0001 C CNN +F 1 "+5V" H 2165 6423 50 0000 C CNN +F 2 "" H 2150 6250 50 0001 C CNN +F 3 "" H 2150 6250 50 0001 C CNN + 1 2150 6250 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG0101 +U 1 1 5E97C674 +P 950 5850 +F 0 "#FLG0101" H 950 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 950 6023 50 0000 C CNN +F 2 "" H 950 5850 50 0001 C CNN +F 3 "~" H 950 5850 50 0001 C CNN + 1 950 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 6250 950 5850 +Connection ~ 950 6250 +Wire Wire Line + 950 6250 1200 6250 +$Comp +L power:GND #PWR0103 +U 1 1 5E97DBEE +P 2600 6250 +F 0 "#PWR0103" H 2600 6000 50 0001 C CNN +F 1 "GND" H 2605 6077 50 0000 C CNN +F 2 "" H 2600 6250 50 0001 C CNN +F 3 "" H 2600 6250 50 0001 C CNN + 1 2600 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1800 6250 1900 6250 +$Comp +L power:PWR_FLAG #FLG0102 +U 1 1 5E97F87F +P 1900 5850 +F 0 "#FLG0102" H 1900 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 1900 6023 50 0000 C CNN +F 2 "" H 1900 5850 50 0001 C CNN +F 3 "~" H 1900 5850 50 0001 C CNN + 1 1900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 6250 1900 5850 +Connection ~ 1900 6250 +Wire Wire Line + 1900 6250 2150 6250 +$Comp +L power:PWR_FLAG #FLG0103 +U 1 1 5E980A5B +P 2600 5850 +F 0 "#FLG0103" H 2600 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 2600 6023 50 0000 C CNN +F 2 "" H 2600 5850 50 0001 C CNN +F 3 "~" H 2600 5850 50 0001 C CNN + 1 2600 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 6250 2600 5850 +Text Label 4050 1150 0 50 ~ 0 +DEBUG_TX +Wire Wire Line + 4000 1150 4050 1150 +Wire Wire Line + 4000 1250 4050 1250 +Text Label 4050 1250 0 50 ~ 0 +DEBUG_RX +Wire Wire Line + 4000 1350 4050 1350 +Wire Wire Line + 4000 1450 4050 1450 +Wire Wire Line + 4000 1550 4050 1550 +Wire Wire Line + 4000 1650 4050 1650 +Wire Wire Line + 4000 1750 4050 1750 +Wire Wire Line + 4000 1850 4050 1850 +Wire Wire Line + 4000 1950 4050 1950 +Wire Wire Line + 4000 2050 4050 2050 +Text Label 4050 1350 0 50 ~ 0 +MASTER_SPI_MOSI +Text Label 4050 1450 0 50 ~ 0 +MASTER_SPI_MISO +Text Label 4050 1550 0 50 ~ 0 +MASTER_SPI_CLK +Text Label 4050 1650 0 50 ~ 0 +~TFT_CS +Text Label 5700 1300 2 50 ~ 0 +MASTER_SPI_MOSI +Wire Wire Line + 5700 1200 5750 1200 +Text Label 5700 1200 2 50 ~ 0 +MASTER_SPI_MISO +Wire Wire Line + 5700 1300 5750 1300 +Text Label 5700 1100 2 50 ~ 0 +MASTER_SPI_CLK +Wire Wire Line + 5700 1100 5750 1100 +Text Label 5700 1550 2 50 ~ 0 +~TFT_CS +Wire Wire Line + 5700 1550 5750 1550 +Text Label 4050 1950 0 50 ~ 0 +MASTER_I2C_SDA +Text Label 4050 2050 0 50 ~ 0 +MASTER_I2C_SCL +Text Label 5700 2200 2 50 ~ 0 +MASTER_I2C_SDA +Text Label 5700 2300 2 50 ~ 0 +MASTER_I2C_SCL +Wire Wire Line + 5750 2200 5700 2200 +Wire Wire Line + 5750 2300 5700 2300 +Wire Wire Line + 3950 3550 4050 3550 +Wire Wire Line + 3950 3450 4050 3450 +Text Label 4050 3550 0 50 ~ 0 +DEBUG_RX +Text Label 4050 3450 0 50 ~ 0 +DEBUG_TX +$Sheet +S 650 3350 3300 1900 +U 5E7C0F59 +F0 "s_USB_INTF.sch" 50 +F1 "USB_INTF.sch" 50 +F2 "DEBUG_TX" I R 3950 3450 50 +F3 "DEBUG_RX" I R 3950 3550 50 +F4 "FTDI_5V" I R 3950 3750 50 +F5 "FTDI_3V3" I R 3950 3850 50 +$EndSheet +$Sheet +S 750 800 3250 2350 +U 5E805E4F +F0 "s_BRAIN" 50 +F1 "BRAIN.sch" 50 +F2 "DEBUG_TX" I R 4000 1150 50 +F3 "DEBUG_RX" I R 4000 1250 50 +F4 "MASTER_SPI_MOSI" I R 4000 1350 50 +F5 "MASTER_SPI_MISO" I R 4000 1450 50 +F6 "MASTER_SPI_CLK" I R 4000 1550 50 +F7 "~FLASH_MEM_CS" I R 4000 1750 50 +F8 "MASTER_I2C_SDA" I R 4000 1950 50 +F9 "MASTER_I2C_SCL" I R 4000 2050 50 +F10 "~IO_EXPANDER_CS" I R 4000 1850 50 +F11 "~TFT_CS" I R 4000 1650 50 +F12 "~TFT_WR" I R 4000 2150 50 +F13 "~TFT_RD" I R 4000 2250 50 +F14 "TFT_RSDC" I R 4000 2350 50 +F15 "~TFT_RST" I R 4000 2450 50 +$EndSheet +$EndSCHEMATC diff --git a/electrical/same54_dev_board/sym-lib-table b/electrical/same54_dev_board/sym-lib-table index 510a379..7065bea 100644 --- a/electrical/same54_dev_board/sym-lib-table +++ b/electrical/same54_dev_board/sym-lib-table @@ -1,6 +1,6 @@ -(sym_lib_table - (lib (name same54_dev_board-rescue)(type Legacy)(uri ${KIPRJMOD}/same54_dev_board-rescue.lib)(options "")(descr "")) - (lib (name Conn_02x20_LCD_INTF)(type Legacy)(uri ${KIPRJMOD}/libraries/Conn_02x20_LCD_INTF.lib)(options "")(descr "")) - (lib (name MAX7301AAX_)(type Legacy)(uri ${KIPRJMOD}/libraries/MAX7301AAX_.lib)(options "")(descr "")) - (lib (name TPS73733QDRBRQ1)(type Legacy)(uri ${KIPRJMOD}/libraries/TPS73733QDRBRQ1.lib)(options "")(descr "")) -) +(sym_lib_table + (lib (name same54_dev_board-rescue)(type Legacy)(uri ${KIPRJMOD}/same54_dev_board-rescue.lib)(options "")(descr "")) + (lib (name Conn_02x20_LCD_INTF)(type Legacy)(uri ${KIPRJMOD}/libraries/Conn_02x20_LCD_INTF.lib)(options "")(descr "")) + (lib (name MAX7301AAX_)(type Legacy)(uri ${KIPRJMOD}/libraries/MAX7301AAX_.lib)(options "")(descr "")) + (lib (name TPS73733QDRBRQ1)(type Legacy)(uri ${KIPRJMOD}/libraries/TPS73733QDRBRQ1.lib)(options "")(descr "")) +) diff --git a/software/README.md b/software/README.md index f070059..770948e 100644 --- a/software/README.md +++ b/software/README.md @@ -1,17 +1,17 @@ -# Software Readme - - - -## Goals - - Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???) - -## To Do - - PCB - - Decide on core reqs (ex: do i want wifi or NOT) - - map pins - - create bare software for pin mappings - - fix asf4 vomit <<>> - - Get make based asf4 project to compile (i have toolchains wtf why no work) -## Info - - +# Software Readme + + + +## Goals + - Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???) + +## To Do + - PCB + - Decide on core reqs (ex: do i want wifi or NOT) + - map pins + - create bare software for pin mappings + - fix asf4 vomit <<>> + - Get make based asf4 project to compile (i have toolchains wtf why no work) +## Info + + diff --git a/software/conf/project_oractle_config.atstart b/software/conf/project_oractle_config.atstart index 71e239f..fad5d10 100644 --- a/software/conf/project_oractle_config.atstart +++ b/software/conf/project_oractle_config.atstart @@ -1,1177 +1,1177 @@ -format_version: '2' -name: My Project -versions: - api: '1.0' - backend: 1.7.303 - commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 - content: unknown - content_pack_name: unknown - format: '2' - frontend: 1.7.303 - packs_version_avr8: 1.0.1410 - packs_version_qtouch: unknown - packs_version_sam: 1.0.1554 - version_backend: 1.7.303 - version_frontend: '' -board: - identifier: SAME54XplainedPro - device: SAME54P20A-AU -details: null -application: null -middlewares: {} -drivers: - CMCC: - user_label: CMCC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC - functionality: System - api: HAL:HPL:CMCC - configuration: - cache_size: 4 KB - cmcc_advanced_configuration: false - cmcc_clock_gating_disable: false - cmcc_data_cache_disable: false - cmcc_enable: false - cmcc_inst_cache_disable: false - optional_signals: [] - variant: null - clocks: - domain_group: null - DMAC: - user_label: DMAC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC - functionality: System - api: HAL:HPL:DMAC - configuration: - dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer - dmac_beatsize_10: 8-bit bus transfer - dmac_beatsize_11: 8-bit bus transfer - dmac_beatsize_12: 8-bit bus transfer - dmac_beatsize_13: 8-bit bus transfer - dmac_beatsize_14: 8-bit bus transfer - dmac_beatsize_15: 8-bit bus transfer - dmac_beatsize_16: 8-bit bus transfer - dmac_beatsize_17: 8-bit bus transfer - dmac_beatsize_18: 8-bit bus transfer - dmac_beatsize_19: 8-bit bus transfer - dmac_beatsize_2: 8-bit bus transfer - dmac_beatsize_20: 8-bit bus transfer - dmac_beatsize_21: 8-bit bus transfer - dmac_beatsize_22: 8-bit bus transfer - dmac_beatsize_23: 8-bit bus transfer - dmac_beatsize_24: 8-bit bus transfer - dmac_beatsize_25: 8-bit bus transfer - dmac_beatsize_26: 8-bit bus transfer - dmac_beatsize_27: 8-bit bus transfer - dmac_beatsize_28: 8-bit bus transfer - dmac_beatsize_29: 8-bit bus transfer - dmac_beatsize_3: 8-bit bus transfer - dmac_beatsize_30: 8-bit bus transfer - dmac_beatsize_31: 8-bit bus transfer - dmac_beatsize_4: 8-bit bus transfer - dmac_beatsize_5: 8-bit bus transfer - dmac_beatsize_6: 8-bit bus transfer - dmac_beatsize_7: 8-bit bus transfer - dmac_beatsize_8: 8-bit bus transfer - dmac_beatsize_9: 8-bit bus transfer - dmac_blockact_0: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_10: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_11: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_12: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_13: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_14: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_15: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_16: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_17: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_18: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_19: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_2: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_20: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_21: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_22: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_23: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_24: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_25: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_26: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_27: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_28: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_29: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_30: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_31: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_4: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_5: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_6: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_7: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_8: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_9: Channel will be disabled if it is the last block transfer in - the transaction - dmac_channel_0_settings: false - dmac_channel_10_settings: false - dmac_channel_11_settings: false - dmac_channel_12_settings: false - dmac_channel_13_settings: false - dmac_channel_14_settings: false - dmac_channel_15_settings: false - dmac_channel_16_settings: false - dmac_channel_17_settings: false - dmac_channel_18_settings: false - dmac_channel_19_settings: false - dmac_channel_1_settings: false - dmac_channel_20_settings: false - dmac_channel_21_settings: false - dmac_channel_22_settings: false - dmac_channel_23_settings: false - dmac_channel_24_settings: false - dmac_channel_25_settings: false - dmac_channel_26_settings: false - dmac_channel_27_settings: false - dmac_channel_28_settings: false - dmac_channel_29_settings: false - dmac_channel_2_settings: false - dmac_channel_30_settings: false - dmac_channel_31_settings: false - dmac_channel_3_settings: false - dmac_channel_4_settings: false - dmac_channel_5_settings: false - dmac_channel_6_settings: false - dmac_channel_7_settings: false - dmac_channel_8_settings: false - dmac_channel_9_settings: false - dmac_dbgrun: false - dmac_dstinc_0: false - dmac_dstinc_1: false - dmac_dstinc_10: false - dmac_dstinc_11: false - dmac_dstinc_12: false - dmac_dstinc_13: false - dmac_dstinc_14: false - dmac_dstinc_15: false - dmac_dstinc_16: false - dmac_dstinc_17: false - dmac_dstinc_18: false - dmac_dstinc_19: false - dmac_dstinc_2: false - dmac_dstinc_20: false - dmac_dstinc_21: false - dmac_dstinc_22: false - dmac_dstinc_23: false - dmac_dstinc_24: false - dmac_dstinc_25: false - dmac_dstinc_26: false - dmac_dstinc_27: false - dmac_dstinc_28: false - dmac_dstinc_29: false - dmac_dstinc_3: false - dmac_dstinc_30: false - dmac_dstinc_31: false - dmac_dstinc_4: false - dmac_dstinc_5: false - dmac_dstinc_6: false - dmac_dstinc_7: false - dmac_dstinc_8: false - dmac_dstinc_9: false - dmac_enable: false - dmac_evact_0: No action - dmac_evact_1: No action - dmac_evact_10: No action - dmac_evact_11: No action - dmac_evact_12: No action - dmac_evact_13: No action - dmac_evact_14: No action - dmac_evact_15: No action - dmac_evact_16: No action - dmac_evact_17: No action - dmac_evact_18: No action - dmac_evact_19: No action - dmac_evact_2: No action - dmac_evact_20: No action - dmac_evact_21: No action - dmac_evact_22: No action - dmac_evact_23: No action - dmac_evact_24: No action - dmac_evact_25: No action - dmac_evact_26: No action - dmac_evact_27: No action - dmac_evact_28: No action - dmac_evact_29: No action - dmac_evact_3: No action - dmac_evact_30: No action - dmac_evact_31: No action - dmac_evact_4: No action - dmac_evact_5: No action - dmac_evact_6: No action - dmac_evact_7: No action - dmac_evact_8: No action - dmac_evact_9: No action - dmac_evie_0: false - dmac_evie_1: false - dmac_evie_10: false - dmac_evie_11: false - dmac_evie_12: false - dmac_evie_13: false - dmac_evie_14: false - dmac_evie_15: false - dmac_evie_16: false - dmac_evie_17: false - dmac_evie_18: false - dmac_evie_19: false - dmac_evie_2: false - dmac_evie_20: false - dmac_evie_21: false - dmac_evie_22: false - dmac_evie_23: false - dmac_evie_24: false - dmac_evie_25: false - dmac_evie_26: false - dmac_evie_27: false - dmac_evie_28: false - dmac_evie_29: false - dmac_evie_3: false - dmac_evie_30: false - dmac_evie_31: false - dmac_evie_4: false - dmac_evie_5: false - dmac_evie_6: false - dmac_evie_7: false - dmac_evie_8: false - dmac_evie_9: false - dmac_evoe_0: false - dmac_evoe_1: false - dmac_evoe_10: false - dmac_evoe_11: false - dmac_evoe_12: false - dmac_evoe_13: false - dmac_evoe_14: false - dmac_evoe_15: false - dmac_evoe_16: false - dmac_evoe_17: false - dmac_evoe_18: false - dmac_evoe_19: false - dmac_evoe_2: false - dmac_evoe_20: false - dmac_evoe_21: false - dmac_evoe_22: false - dmac_evoe_23: false - dmac_evoe_24: false - dmac_evoe_25: false - dmac_evoe_26: false - dmac_evoe_27: false - dmac_evoe_28: false - dmac_evoe_29: false - dmac_evoe_3: false - dmac_evoe_30: false - dmac_evoe_31: false - dmac_evoe_4: false - dmac_evoe_5: false - dmac_evoe_6: false - dmac_evoe_7: false - dmac_evoe_8: false - dmac_evoe_9: false - dmac_evosel_0: Event generation disabled - dmac_evosel_1: Event generation disabled - dmac_evosel_10: Event generation disabled - dmac_evosel_11: Event generation disabled - dmac_evosel_12: Event generation disabled - dmac_evosel_13: Event generation disabled - dmac_evosel_14: Event generation disabled - dmac_evosel_15: Event generation disabled - dmac_evosel_16: Event generation disabled - dmac_evosel_17: Event generation disabled - dmac_evosel_18: Event generation disabled - dmac_evosel_19: Event generation disabled - dmac_evosel_2: Event generation disabled - dmac_evosel_20: Event generation disabled - dmac_evosel_21: Event generation disabled - dmac_evosel_22: Event generation disabled - dmac_evosel_23: Event generation disabled - dmac_evosel_24: Event generation disabled - dmac_evosel_25: Event generation disabled - dmac_evosel_26: Event generation disabled - dmac_evosel_27: Event generation disabled - dmac_evosel_28: Event generation disabled - dmac_evosel_29: Event generation disabled - dmac_evosel_3: Event generation disabled - dmac_evosel_30: Event generation disabled - dmac_evosel_31: Event generation disabled - dmac_evosel_4: Event generation disabled - dmac_evosel_5: Event generation disabled - dmac_evosel_6: Event generation disabled - dmac_evosel_7: Event generation disabled - dmac_evosel_8: Event generation disabled - dmac_evosel_9: Event generation disabled - dmac_lvl_0: Channel priority 0 - dmac_lvl_1: Channel priority 0 - dmac_lvl_10: Channel priority 0 - dmac_lvl_11: Channel priority 0 - dmac_lvl_12: Channel priority 0 - dmac_lvl_13: Channel priority 0 - dmac_lvl_14: Channel priority 0 - dmac_lvl_15: Channel priority 0 - dmac_lvl_16: Channel priority 0 - dmac_lvl_17: Channel priority 0 - dmac_lvl_18: Channel priority 0 - dmac_lvl_19: Channel priority 0 - dmac_lvl_2: Channel priority 0 - dmac_lvl_20: Channel priority 0 - dmac_lvl_21: Channel priority 0 - dmac_lvl_22: Channel priority 0 - dmac_lvl_23: Channel priority 0 - dmac_lvl_24: Channel priority 0 - dmac_lvl_25: Channel priority 0 - dmac_lvl_26: Channel priority 0 - dmac_lvl_27: Channel priority 0 - dmac_lvl_28: Channel priority 0 - dmac_lvl_29: Channel priority 0 - dmac_lvl_3: Channel priority 0 - dmac_lvl_30: Channel priority 0 - dmac_lvl_31: Channel priority 0 - dmac_lvl_4: Channel priority 0 - dmac_lvl_5: Channel priority 0 - dmac_lvl_6: Channel priority 0 - dmac_lvl_7: Channel priority 0 - dmac_lvl_8: Channel priority 0 - dmac_lvl_9: Channel priority 0 - dmac_lvlen0: true - dmac_lvlen1: true - dmac_lvlen2: true - dmac_lvlen3: true - dmac_lvlpri0: 0 - dmac_lvlpri1: 0 - dmac_lvlpri2: 0 - dmac_lvlpri3: 0 - dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 - dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 - dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 - dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_runstdby_0: false - dmac_runstdby_1: false - dmac_runstdby_10: false - dmac_runstdby_11: false - dmac_runstdby_12: false - dmac_runstdby_13: false - dmac_runstdby_14: false - dmac_runstdby_15: false - dmac_runstdby_16: false - dmac_runstdby_17: false - dmac_runstdby_18: false - dmac_runstdby_19: false - dmac_runstdby_2: false - dmac_runstdby_20: false - dmac_runstdby_21: false - dmac_runstdby_22: false - dmac_runstdby_23: false - dmac_runstdby_24: false - dmac_runstdby_25: false - dmac_runstdby_26: false - dmac_runstdby_27: false - dmac_runstdby_28: false - dmac_runstdby_29: false - dmac_runstdby_3: false - dmac_runstdby_30: false - dmac_runstdby_31: false - dmac_runstdby_4: false - dmac_runstdby_5: false - dmac_runstdby_6: false - dmac_runstdby_7: false - dmac_runstdby_8: false - dmac_runstdby_9: false - dmac_srcinc_0: false - dmac_srcinc_1: false - dmac_srcinc_10: false - dmac_srcinc_11: false - dmac_srcinc_12: false - dmac_srcinc_13: false - dmac_srcinc_14: false - dmac_srcinc_15: false - dmac_srcinc_16: false - dmac_srcinc_17: false - dmac_srcinc_18: false - dmac_srcinc_19: false - dmac_srcinc_2: false - dmac_srcinc_20: false - dmac_srcinc_21: false - dmac_srcinc_22: false - dmac_srcinc_23: false - dmac_srcinc_24: false - dmac_srcinc_25: false - dmac_srcinc_26: false - dmac_srcinc_27: false - dmac_srcinc_28: false - dmac_srcinc_29: false - dmac_srcinc_3: false - dmac_srcinc_30: false - dmac_srcinc_31: false - dmac_srcinc_4: false - dmac_srcinc_5: false - dmac_srcinc_6: false - dmac_srcinc_7: false - dmac_srcinc_8: false - dmac_srcinc_9: false - dmac_stepsel_0: Step size settings apply to the destination address - dmac_stepsel_1: Step size settings apply to the destination address - dmac_stepsel_10: Step size settings apply to the destination address - dmac_stepsel_11: Step size settings apply to the destination address - dmac_stepsel_12: Step size settings apply to the destination address - dmac_stepsel_13: Step size settings apply to the destination address - dmac_stepsel_14: Step size settings apply to the destination address - dmac_stepsel_15: Step size settings apply to the destination address - dmac_stepsel_16: Step size settings apply to the destination address - dmac_stepsel_17: Step size settings apply to the destination address - dmac_stepsel_18: Step size settings apply to the destination address - dmac_stepsel_19: Step size settings apply to the destination address - dmac_stepsel_2: Step size settings apply to the destination address - dmac_stepsel_20: Step size settings apply to the destination address - dmac_stepsel_21: Step size settings apply to the destination address - dmac_stepsel_22: Step size settings apply to the destination address - dmac_stepsel_23: Step size settings apply to the destination address - dmac_stepsel_24: Step size settings apply to the destination address - dmac_stepsel_25: Step size settings apply to the destination address - dmac_stepsel_26: Step size settings apply to the destination address - dmac_stepsel_27: Step size settings apply to the destination address - dmac_stepsel_28: Step size settings apply to the destination address - dmac_stepsel_29: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address - dmac_stepsel_30: Step size settings apply to the destination address - dmac_stepsel_31: Step size settings apply to the destination address - dmac_stepsel_4: Step size settings apply to the destination address - dmac_stepsel_5: Step size settings apply to the destination address - dmac_stepsel_6: Step size settings apply to the destination address - dmac_stepsel_7: Step size settings apply to the destination address - dmac_stepsel_8: Step size settings apply to the destination address - dmac_stepsel_9: Step size settings apply to the destination address - dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_trifsrc_0: Only software/event triggers - dmac_trifsrc_1: Only software/event triggers - dmac_trifsrc_10: Only software/event triggers - dmac_trifsrc_11: Only software/event triggers - dmac_trifsrc_12: Only software/event triggers - dmac_trifsrc_13: Only software/event triggers - dmac_trifsrc_14: Only software/event triggers - dmac_trifsrc_15: Only software/event triggers - dmac_trifsrc_16: Only software/event triggers - dmac_trifsrc_17: Only software/event triggers - dmac_trifsrc_18: Only software/event triggers - dmac_trifsrc_19: Only software/event triggers - dmac_trifsrc_2: Only software/event triggers - dmac_trifsrc_20: Only software/event triggers - dmac_trifsrc_21: Only software/event triggers - dmac_trifsrc_22: Only software/event triggers - dmac_trifsrc_23: Only software/event triggers - dmac_trifsrc_24: Only software/event triggers - dmac_trifsrc_25: Only software/event triggers - dmac_trifsrc_26: Only software/event triggers - dmac_trifsrc_27: Only software/event triggers - dmac_trifsrc_28: Only software/event triggers - dmac_trifsrc_29: Only software/event triggers - dmac_trifsrc_3: Only software/event triggers - dmac_trifsrc_30: Only software/event triggers - dmac_trifsrc_31: Only software/event triggers - dmac_trifsrc_4: Only software/event triggers - dmac_trifsrc_5: Only software/event triggers - dmac_trifsrc_6: Only software/event triggers - dmac_trifsrc_7: Only software/event triggers - dmac_trifsrc_8: Only software/event triggers - dmac_trifsrc_9: Only software/event triggers - dmac_trigact_0: One trigger required for each block transfer - dmac_trigact_1: One trigger required for each block transfer - dmac_trigact_10: One trigger required for each block transfer - dmac_trigact_11: One trigger required for each block transfer - dmac_trigact_12: One trigger required for each block transfer - dmac_trigact_13: One trigger required for each block transfer - dmac_trigact_14: One trigger required for each block transfer - dmac_trigact_15: One trigger required for each block transfer - dmac_trigact_16: One trigger required for each block transfer - dmac_trigact_17: One trigger required for each block transfer - dmac_trigact_18: One trigger required for each block transfer - dmac_trigact_19: One trigger required for each block transfer - dmac_trigact_2: One trigger required for each block transfer - dmac_trigact_20: One trigger required for each block transfer - dmac_trigact_21: One trigger required for each block transfer - dmac_trigact_22: One trigger required for each block transfer - dmac_trigact_23: One trigger required for each block transfer - dmac_trigact_24: One trigger required for each block transfer - dmac_trigact_25: One trigger required for each block transfer - dmac_trigact_26: One trigger required for each block transfer - dmac_trigact_27: One trigger required for each block transfer - dmac_trigact_28: One trigger required for each block transfer - dmac_trigact_29: One trigger required for each block transfer - dmac_trigact_3: One trigger required for each block transfer - dmac_trigact_30: One trigger required for each block transfer - dmac_trigact_31: One trigger required for each block transfer - dmac_trigact_4: One trigger required for each block transfer - dmac_trigact_5: One trigger required for each block transfer - dmac_trigact_6: One trigger required for each block transfer - dmac_trigact_7: One trigger required for each block transfer - dmac_trigact_8: One trigger required for each block transfer - dmac_trigact_9: One trigger required for each block transfer - optional_signals: [] - variant: null - clocks: - domain_group: null - EXTERNAL_IRQ_0: - user_label: EXTERNAL_IRQ_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ - functionality: External_IRQ - api: HAL:Driver:Ext_IRQ - configuration: - eic_arch_asynch0: false - eic_arch_asynch1: false - eic_arch_asynch10: false - eic_arch_asynch11: false - eic_arch_asynch12: false - eic_arch_asynch13: false - eic_arch_asynch14: false - eic_arch_asynch15: false - eic_arch_asynch2: false - eic_arch_asynch3: false - eic_arch_asynch4: false - eic_arch_asynch5: false - eic_arch_asynch6: false - eic_arch_asynch7: false - eic_arch_asynch8: false - eic_arch_asynch9: false - eic_arch_cksel: Clocked by GCLK - eic_arch_debounce_enable0: false - eic_arch_debounce_enable1: false - eic_arch_debounce_enable10: false - eic_arch_debounce_enable11: false - eic_arch_debounce_enable12: false - eic_arch_debounce_enable13: false - eic_arch_debounce_enable14: false - eic_arch_debounce_enable15: false - eic_arch_debounce_enable2: false - eic_arch_debounce_enable3: false - eic_arch_debounce_enable4: false - eic_arch_debounce_enable5: false - eic_arch_debounce_enable6: false - eic_arch_debounce_enable7: false - eic_arch_debounce_enable8: false - eic_arch_debounce_enable9: false - eic_arch_enable_irq_setting0: false - eic_arch_enable_irq_setting1: false - eic_arch_enable_irq_setting10: false - eic_arch_enable_irq_setting11: false - eic_arch_enable_irq_setting12: false - eic_arch_enable_irq_setting13: false - eic_arch_enable_irq_setting14: false - eic_arch_enable_irq_setting15: false - eic_arch_enable_irq_setting2: false - eic_arch_enable_irq_setting3: false - eic_arch_enable_irq_setting4: false - eic_arch_enable_irq_setting5: false - eic_arch_enable_irq_setting6: false - eic_arch_enable_irq_setting7: false - eic_arch_enable_irq_setting8: false - eic_arch_enable_irq_setting9: false - eic_arch_extinteo0: false - eic_arch_extinteo1: false - eic_arch_extinteo10: false - eic_arch_extinteo11: false - eic_arch_extinteo12: false - eic_arch_extinteo13: false - eic_arch_extinteo14: false - eic_arch_extinteo15: false - eic_arch_extinteo2: false - eic_arch_extinteo3: false - eic_arch_extinteo4: false - eic_arch_extinteo5: false - eic_arch_extinteo6: false - eic_arch_extinteo7: false - eic_arch_extinteo8: false - eic_arch_extinteo9: false - eic_arch_filten0: false - eic_arch_filten1: false - eic_arch_filten10: false - eic_arch_filten11: false - eic_arch_filten12: false - eic_arch_filten13: false - eic_arch_filten14: false - eic_arch_filten15: false - eic_arch_filten2: false - eic_arch_filten3: false - eic_arch_filten4: false - eic_arch_filten5: false - eic_arch_filten6: false - eic_arch_filten7: false - eic_arch_filten8: false - eic_arch_filten9: false - eic_arch_nmi_ctrl: false - eic_arch_nmiasynch: false - eic_arch_nmifilten: false - eic_arch_nmisense: No detection - eic_arch_prescaler0: Divided by 2 - eic_arch_prescaler1: Divided by 2 - eic_arch_sense0: No detection - eic_arch_sense1: No detection - eic_arch_sense10: No detection - eic_arch_sense11: No detection - eic_arch_sense12: No detection - eic_arch_sense13: No detection - eic_arch_sense14: No detection - eic_arch_sense15: No detection - eic_arch_sense2: No detection - eic_arch_sense3: No detection - eic_arch_sense4: No detection - eic_arch_sense5: No detection - eic_arch_sense6: No detection - eic_arch_sense7: No detection - eic_arch_sense8: No detection - eic_arch_sense9: No detection - eic_arch_states0: '3' - eic_arch_states1: '3' - eic_arch_tickon: The sampling rate is EIC clock - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: EIC - input: Generic clock generator 0 - external: false - external_frequency: 0 - configuration: - eic_gclk_selection: Generic clock generator 0 - GCLK: - user_label: GCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK - functionality: System - api: HAL:HPL:GCLK - configuration: - enable_gclk_gen_0: true - enable_gclk_gen_0__externalclock: 1000000 - enable_gclk_gen_1: false - enable_gclk_gen_10: false - enable_gclk_gen_10__externalclock: 1000000 - enable_gclk_gen_11: false - enable_gclk_gen_11__externalclock: 1000000 - enable_gclk_gen_1__externalclock: 1000000 - enable_gclk_gen_2: false - enable_gclk_gen_2__externalclock: 1000000 - enable_gclk_gen_3: false - enable_gclk_gen_3__externalclock: 1000000 - enable_gclk_gen_4: false - enable_gclk_gen_4__externalclock: 1000000 - enable_gclk_gen_5: false - enable_gclk_gen_5__externalclock: 1000000 - enable_gclk_gen_6: false - enable_gclk_gen_6__externalclock: 1000000 - enable_gclk_gen_7: false - enable_gclk_gen_7__externalclock: 1000000 - enable_gclk_gen_8: false - enable_gclk_gen_8__externalclock: 1000000 - enable_gclk_gen_9: false - enable_gclk_gen_9__externalclock: 1000000 - gclk_arch_gen_0_enable: true - gclk_arch_gen_0_idc: false - gclk_arch_gen_0_oe: false - gclk_arch_gen_0_oov: false - gclk_arch_gen_0_runstdby: false - gclk_arch_gen_10_enable: false - gclk_arch_gen_10_idc: false - gclk_arch_gen_10_oe: false - gclk_arch_gen_10_oov: false - gclk_arch_gen_10_runstdby: false - gclk_arch_gen_11_enable: false - gclk_arch_gen_11_idc: false - gclk_arch_gen_11_oe: false - gclk_arch_gen_11_oov: false - gclk_arch_gen_11_runstdby: false - gclk_arch_gen_1_enable: false - gclk_arch_gen_1_idc: false - gclk_arch_gen_1_oe: false - gclk_arch_gen_1_oov: false - gclk_arch_gen_1_runstdby: false - gclk_arch_gen_2_enable: false - gclk_arch_gen_2_idc: false - gclk_arch_gen_2_oe: false - gclk_arch_gen_2_oov: false - gclk_arch_gen_2_runstdby: false - gclk_arch_gen_3_enable: false - gclk_arch_gen_3_idc: false - gclk_arch_gen_3_oe: false - gclk_arch_gen_3_oov: false - gclk_arch_gen_3_runstdby: false - gclk_arch_gen_4_enable: false - gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false - gclk_arch_gen_4_oov: false - gclk_arch_gen_4_runstdby: false - gclk_arch_gen_5_enable: false - gclk_arch_gen_5_idc: false - gclk_arch_gen_5_oe: false - gclk_arch_gen_5_oov: false - gclk_arch_gen_5_runstdby: false - gclk_arch_gen_6_enable: false - gclk_arch_gen_6_idc: false - gclk_arch_gen_6_oe: false - gclk_arch_gen_6_oov: false - gclk_arch_gen_6_runstdby: false - gclk_arch_gen_7_enable: false - gclk_arch_gen_7_idc: false - gclk_arch_gen_7_oe: false - gclk_arch_gen_7_oov: false - gclk_arch_gen_7_runstdby: false - gclk_arch_gen_8_enable: false - gclk_arch_gen_8_idc: false - gclk_arch_gen_8_oe: false - gclk_arch_gen_8_oov: false - gclk_arch_gen_8_runstdby: false - gclk_arch_gen_9_enable: false - gclk_arch_gen_9_idc: false - gclk_arch_gen_9_oe: false - gclk_arch_gen_9_oov: false - gclk_arch_gen_9_runstdby: false - gclk_gen_0_div: 1 - gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) - gclk_gen_10_div: 1 - gclk_gen_10_div_sel: false - gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_11_div: 1 - gclk_gen_11_div_sel: false - gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_1_div: 1 - gclk_gen_1_div_sel: false - gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) - gclk_gen_2_div: 1 - gclk_gen_2_div_sel: true - gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_3_div: 1 - gclk_gen_3_div_sel: false - gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) - gclk_gen_4_div: 1 - gclk_gen_4_div_sel: false - gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_5_div: 1 - gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_6_div: 1 - gclk_gen_6_div_sel: false - gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_7_div: 1 - gclk_gen_7_div_sel: false - gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_8_div: 1 - gclk_gen_8_div_sel: false - gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_9_div: 1 - gclk_gen_9_div_sel: false - gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - optional_signals: [] - variant: null - clocks: - domain_group: null - MCLK: - user_label: MCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK - functionality: System - api: HAL:HPL:MCLK - configuration: - cpu_clock_source: Generic clock generator 0 - cpu_div: '1' - enable_cpu_clock: true - mclk_arch_bupdiv: Divide by 8 - mclk_arch_hsdiv: Divide by 1 - mclk_arch_lpdiv: Divide by 4 - nvm_wait_states: '5' - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: CPU - input: CPU - external: false - external_frequency: 0 - configuration: {} - OSC32KCTRL: - user_label: OSC32KCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL - functionality: System - api: HAL:HPL:OSC32KCTRL - configuration: - enable_osculp32k: true - enable_rtc_source: false - enable_xosc32k: true - osculp32k_calib: 0 - osculp32k_calib_enable: false - rtc_1khz_selection: false - rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) - xosc32k_arch_cfden: false - xosc32k_arch_cfdeo: false - xosc32k_arch_cgm: Standard mode - xosc32k_arch_en1k: false - xosc32k_arch_en32k: true - xosc32k_arch_enable: true - xosc32k_arch_ondemand: true - xosc32k_arch_runstdby: false - xosc32k_arch_startup: 1000092us - xosc32k_arch_swben: false - xosc32k_arch_xtalen: true - optional_signals: [] - variant: null - clocks: - domain_group: null - OSCCTRL: - user_label: OSCCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL - functionality: System - api: HAL:HPL:OSCCTRL - configuration: - dfll_arch_bplckc: false - dfll_arch_calibration: false - dfll_arch_ccdis: false - dfll_arch_coarse: 31 - dfll_arch_cstep: 1 - dfll_arch_enable: false - dfll_arch_fine: 128 - dfll_arch_fstep: 1 - dfll_arch_llaw: false - dfll_arch_ondemand: false - dfll_arch_qldis: false - dfll_arch_runstdby: false - dfll_arch_stable: false - dfll_arch_usbcrm: false - dfll_arch_waitlock: true - dfll_mode: Open Loop Mode - dfll_mul: 0 - dfll_ref_clock: Generic clock generator 3 - enable_dfll: false - enable_fdpll0: true - enable_fdpll1: false - enable_xosc0: false - enable_xosc1: false - fdpll0_arch_dcoen: false - fdpll0_arch_enable: true - fdpll0_arch_filter: 0 - fdpll0_arch_lbypass: true - fdpll0_arch_ltime: No time-out, automatic lock - fdpll0_arch_ondemand: false - fdpll0_arch_refclk: XOSC32K clock reference - fdpll0_arch_runstdby: false - fdpll0_arch_wuf: false - fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 0 - fdpll0_ldr: 3661 - fdpll0_ldrfrac: 1 - fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - fdpll1_arch_dcoen: false - fdpll1_arch_enable: false - fdpll1_arch_filter: 0 - fdpll1_arch_lbypass: false - fdpll1_arch_ltime: No time-out, automatic lock - fdpll1_arch_ondemand: false - fdpll1_arch_refclk: XOSC32K clock reference - fdpll1_arch_runstdby: false - fdpll1_arch_wuf: false - fdpll1_clock_dcofilter: 0 - fdpll1_clock_div: 0 - fdpll1_ldr: 1463 - fdpll1_ldrfrac: 13 - fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - xosc0_arch_cfden: false - xosc0_arch_enable: false - xosc0_arch_enalc: false - xosc0_arch_lowbufgain: false - xosc0_arch_ondemand: false - xosc0_arch_runstdby: false - xosc0_arch_startup: 31us - xosc0_arch_swben: false - xosc0_arch_xtalen: false - xosc0_frequency: 12000000 - xosc1_arch_cfden: false - xosc1_arch_enable: false - xosc1_arch_enalc: false - xosc1_arch_lowbufgain: false - xosc1_arch_ondemand: false - xosc1_arch_runstdby: false - xosc1_arch_startup: 31us - xosc1_arch_swben: false - xosc1_arch_xtalen: true - xosc1_frequency: 12000000 - optional_signals: [] - variant: null - clocks: - domain_group: null - PORT: - user_label: PORT - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT - functionality: System - api: HAL:HPL:PORT - configuration: - enable_port_input_event_0: false - enable_port_input_event_1: false - enable_port_input_event_2: false - enable_port_input_event_3: false - porta_event_action_0: Output register of pin will be set to level of event - porta_event_action_1: Output register of pin will be set to level of event - porta_event_action_2: Output register of pin will be set to level of event - porta_event_action_3: Output register of pin will be set to level of event - porta_event_pin_identifier_0: 0 - porta_event_pin_identifier_1: 0 - porta_event_pin_identifier_2: 0 - porta_event_pin_identifier_3: 0 - porta_input_event_enable_0: false - porta_input_event_enable_1: false - porta_input_event_enable_2: false - porta_input_event_enable_3: false - portb_event_action_0: Output register of pin will be set to level of event - portb_event_action_1: Output register of pin will be set to level of event - portb_event_action_2: Output register of pin will be set to level of event - portb_event_action_3: Output register of pin will be set to level of event - portb_event_pin_identifier_0: 0 - portb_event_pin_identifier_1: 0 - portb_event_pin_identifier_2: 0 - portb_event_pin_identifier_3: 0 - portb_input_event_enable_0: false - portb_input_event_enable_1: false - portb_input_event_enable_2: false - portb_input_event_enable_3: false - portc_event_action_0: Output register of pin will be set to level of event - portc_event_action_1: Output register of pin will be set to level of event - portc_event_action_2: Output register of pin will be set to level of event - portc_event_action_3: Output register of pin will be set to level of event - portc_event_pin_identifier_0: 0 - portc_event_pin_identifier_1: 0 - portc_event_pin_identifier_2: 0 - portc_event_pin_identifier_3: 0 - portc_input_event_enable_0: false - portc_input_event_enable_1: false - portc_input_event_enable_2: false - portc_input_event_enable_3: false - portd_event_action_0: Output register of pin will be set to level of event - portd_event_action_1: Output register of pin will be set to level of event - portd_event_action_2: Output register of pin will be set to level of event - portd_event_action_3: Output register of pin will be set to level of event - portd_event_pin_identifier_0: 0 - portd_event_pin_identifier_1: 0 - portd_event_pin_identifier_2: 0 - portd_event_pin_identifier_3: 0 - portd_input_event_enable_0: false - portd_input_event_enable_1: false - portd_input_event_enable_2: false - portd_input_event_enable_3: false - optional_signals: [] - variant: null - clocks: - domain_group: null - RAMECC: - user_label: RAMECC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC - functionality: System - api: HAL:HPL:RAMECC - configuration: {} - optional_signals: [] - variant: null - clocks: - domain_group: null - USART_0: - user_label: USART_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async - functionality: USART - api: HAL:Driver:USART_Async - configuration: - usart_advanced: false - usart_arch_clock_mode: USART with internal clock - usart_arch_cloden: false - usart_arch_dbgstop: Keep running - usart_arch_dord: LSB is transmitted first - usart_arch_enc: No encoding - usart_arch_fractional: 0 - usart_arch_ibon: false - usart_arch_lin_slave_enable: Disable - usart_arch_runstdby: false - usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) - usart_arch_sampr: 16x arithmetic - usart_arch_sfde: false - usart_baud_rate: 115200 - usart_character_size: 8 bits - usart_parity: No parity - usart_rx_enable: true - usart_stop_bit: One stop bit - usart_tx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=1, CMODE=0 - required_signals: - - name: SERCOM2/PAD/0 - pad: PB25 - label: TX - - name: SERCOM2/PAD/1 - pad: PB24 - label: RX - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - external: false - external_frequency: 0 - - name: Slow - input: Generic clock generator 3 - external: false - external_frequency: 0 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - I2C_0: - user_label: I2C_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync - functionality: I2C - api: HAL:Driver:I2C_Master_Sync - configuration: - i2c_master_advanced: false - i2c_master_arch_dbgstop: Keep running - i2c_master_arch_inactout: Disabled - i2c_master_arch_lowtout: false - i2c_master_arch_mexttoen: false - i2c_master_arch_runstdby: false - i2c_master_arch_sdahold: 300-600ns hold time - i2c_master_arch_sexttoen: false - i2c_master_arch_trise: 215 - i2c_master_baud_rate: 100000 - optional_signals: [] - variant: - specification: SDA=0, SCL=1 - required_signals: - - name: SERCOM3/PAD/0 - pad: PA22 - label: SDA - - name: SERCOM3/PAD/1 - pad: PA23 - label: SCL - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - external: false - external_frequency: 0 - - name: Slow - input: Generic clock generator 3 - external: false - external_frequency: 0 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - tc_arch_dbgrun: false - tc_arch_evact: Event action disabled - tc_arch_mceo0: false - tc_arch_mceo1: false - tc_arch_ondemand: false - tc_arch_ovfeo: false - tc_arch_presync: Reload or reset counter on next GCLK - tc_arch_runstdby: false - tc_arch_tcei: false - tc_arch_tcinv: false - timer_advanced_configuration: false - timer_event_control: false - timer_prescaler: Divide by 8 - timer_tick: 1000 - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: TC - input: Generic clock generator 0 - external: false - external_frequency: 0 - configuration: - tc_gclk_selection: Generic clock generator 0 -pads: - PA22: - name: PA22 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22 - mode: I2C - user_label: PA22 - configuration: null - PA23: - name: PA23 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23 - mode: I2C - user_label: PA23 - configuration: null - PB24: - name: PB24 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 - mode: Peripheral IO - user_label: PB24 - configuration: null - PB25: - name: PB25 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 - mode: Peripheral IO - user_label: PB25 - configuration: null -toolchain_options: [] +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.7.303 + commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.7.303 + packs_version_avr8: 1.0.1410 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1554 + version_backend: 1.7.303 + version_frontend: '' +board: + identifier: SAME54XplainedPro + device: SAME54P20A-AU +details: null +application: null +middlewares: {} +drivers: + CMCC: + user_label: CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: false + cmcc_clock_gating_disable: false + cmcc_data_cache_disable: false + cmcc_enable: false + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: false + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: false + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: true + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EXTERNAL_IRQ_0: + user_label: EXTERNAL_IRQ_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + functionality: External_IRQ + api: HAL:Driver:Ext_IRQ + configuration: + eic_arch_asynch0: false + eic_arch_asynch1: false + eic_arch_asynch10: false + eic_arch_asynch11: false + eic_arch_asynch12: false + eic_arch_asynch13: false + eic_arch_asynch14: false + eic_arch_asynch15: false + eic_arch_asynch2: false + eic_arch_asynch3: false + eic_arch_asynch4: false + eic_arch_asynch5: false + eic_arch_asynch6: false + eic_arch_asynch7: false + eic_arch_asynch8: false + eic_arch_asynch9: false + eic_arch_cksel: Clocked by GCLK + eic_arch_debounce_enable0: false + eic_arch_debounce_enable1: false + eic_arch_debounce_enable10: false + eic_arch_debounce_enable11: false + eic_arch_debounce_enable12: false + eic_arch_debounce_enable13: false + eic_arch_debounce_enable14: false + eic_arch_debounce_enable15: false + eic_arch_debounce_enable2: false + eic_arch_debounce_enable3: false + eic_arch_debounce_enable4: false + eic_arch_debounce_enable5: false + eic_arch_debounce_enable6: false + eic_arch_debounce_enable7: false + eic_arch_debounce_enable8: false + eic_arch_debounce_enable9: false + eic_arch_enable_irq_setting0: false + eic_arch_enable_irq_setting1: false + eic_arch_enable_irq_setting10: false + eic_arch_enable_irq_setting11: false + eic_arch_enable_irq_setting12: false + eic_arch_enable_irq_setting13: false + eic_arch_enable_irq_setting14: false + eic_arch_enable_irq_setting15: false + eic_arch_enable_irq_setting2: false + eic_arch_enable_irq_setting3: false + eic_arch_enable_irq_setting4: false + eic_arch_enable_irq_setting5: false + eic_arch_enable_irq_setting6: false + eic_arch_enable_irq_setting7: false + eic_arch_enable_irq_setting8: false + eic_arch_enable_irq_setting9: false + eic_arch_extinteo0: false + eic_arch_extinteo1: false + eic_arch_extinteo10: false + eic_arch_extinteo11: false + eic_arch_extinteo12: false + eic_arch_extinteo13: false + eic_arch_extinteo14: false + eic_arch_extinteo15: false + eic_arch_extinteo2: false + eic_arch_extinteo3: false + eic_arch_extinteo4: false + eic_arch_extinteo5: false + eic_arch_extinteo6: false + eic_arch_extinteo7: false + eic_arch_extinteo8: false + eic_arch_extinteo9: false + eic_arch_filten0: false + eic_arch_filten1: false + eic_arch_filten10: false + eic_arch_filten11: false + eic_arch_filten12: false + eic_arch_filten13: false + eic_arch_filten14: false + eic_arch_filten15: false + eic_arch_filten2: false + eic_arch_filten3: false + eic_arch_filten4: false + eic_arch_filten5: false + eic_arch_filten6: false + eic_arch_filten7: false + eic_arch_filten8: false + eic_arch_filten9: false + eic_arch_nmi_ctrl: false + eic_arch_nmiasynch: false + eic_arch_nmifilten: false + eic_arch_nmisense: No detection + eic_arch_prescaler0: Divided by 2 + eic_arch_prescaler1: Divided by 2 + eic_arch_sense0: No detection + eic_arch_sense1: No detection + eic_arch_sense10: No detection + eic_arch_sense11: No detection + eic_arch_sense12: No detection + eic_arch_sense13: No detection + eic_arch_sense14: No detection + eic_arch_sense15: No detection + eic_arch_sense2: No detection + eic_arch_sense3: No detection + eic_arch_sense4: No detection + eic_arch_sense5: No detection + eic_arch_sense6: No detection + eic_arch_sense7: No detection + eic_arch_sense8: No detection + eic_arch_sense9: No detection + eic_arch_states0: '3' + eic_arch_states1: '3' + eic_arch_tickon: The sampling rate is EIC clock + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: EIC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + eic_gclk_selection: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: false + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: true + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '5' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: true + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: true + xosc32k_arch_enable: true + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 1000092us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: true + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: false + fdpll0_arch_dcoen: false + fdpll0_arch_enable: true + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: true + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 3661 + fdpll0_ldrfrac: 1 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: false + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + portc_event_action_0: Output register of pin will be set to level of event + portc_event_action_1: Output register of pin will be set to level of event + portc_event_action_2: Output register of pin will be set to level of event + portc_event_action_3: Output register of pin will be set to level of event + portc_event_pin_identifier_0: 0 + portc_event_pin_identifier_1: 0 + portc_event_pin_identifier_2: 0 + portc_event_pin_identifier_3: 0 + portc_input_event_enable_0: false + portc_input_event_enable_1: false + portc_input_event_enable_2: false + portc_input_event_enable_3: false + portd_event_action_0: Output register of pin will be set to level of event + portd_event_action_1: Output register of pin will be set to level of event + portd_event_action_2: Output register of pin will be set to level of event + portd_event_action_3: Output register of pin will be set to level of event + portd_event_pin_identifier_0: 0 + portd_event_pin_identifier_1: 0 + portd_event_pin_identifier_2: 0 + portd_event_pin_identifier_3: 0 + portd_input_event_enable_0: false + portd_input_event_enable_1: false + portd_input_event_enable_2: false + portd_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + USART_0: + user_label: USART_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async + functionality: USART + api: HAL:Driver:USART_Async + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 115200 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM2/PAD/0 + pad: PB25 + label: TX + - name: SERCOM2/PAD/1 + pad: PB24 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM3/PAD/0 + pad: PA22 + label: SDA + - name: SERCOM3/PAD/1 + pad: PA23 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + timer_advanced_configuration: false + timer_event_control: false + timer_prescaler: Divide by 8 + timer_tick: 1000 + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 +pads: + PA22: + name: PA22 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22 + mode: I2C + user_label: PA22 + configuration: null + PA23: + name: PA23 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23 + mode: I2C + user_label: PA23 + configuration: null + PB24: + name: PB24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 + mode: Peripheral IO + user_label: PB24 + configuration: null + PB25: + name: PB25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + mode: Peripheral IO + user_label: PB25 + configuration: null +toolchain_options: [] diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf index 2033451..b9ec847 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.env_conf @@ -1,6 +1,6 @@ - - - - - - + + + + + + diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc index a891ba7..df67f02 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/AtmelStart.gpdsc @@ -1,215 +1,215 @@ - - Atmel - My Project - Project generated by Atmel Start - http://start.atmel.com/ - - Initial version - - - Configuration Files generated by Atmel Start - - - - Atmel Start - + http://start.atmel.com/ + + + + + + + + + Dependency on CMSIS core and Device Startup components + + + + + + + + + + + + + + + + + Atmel Start Framework + #define ATMEL_START + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart index 71e239f..fad5d10 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/.atmelstart/atmel_start_config.atstart @@ -1,1177 +1,1177 @@ -format_version: '2' -name: My Project -versions: - api: '1.0' - backend: 1.7.303 - commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 - content: unknown - content_pack_name: unknown - format: '2' - frontend: 1.7.303 - packs_version_avr8: 1.0.1410 - packs_version_qtouch: unknown - packs_version_sam: 1.0.1554 - version_backend: 1.7.303 - version_frontend: '' -board: - identifier: SAME54XplainedPro - device: SAME54P20A-AU -details: null -application: null -middlewares: {} -drivers: - CMCC: - user_label: CMCC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC - functionality: System - api: HAL:HPL:CMCC - configuration: - cache_size: 4 KB - cmcc_advanced_configuration: false - cmcc_clock_gating_disable: false - cmcc_data_cache_disable: false - cmcc_enable: false - cmcc_inst_cache_disable: false - optional_signals: [] - variant: null - clocks: - domain_group: null - DMAC: - user_label: DMAC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC - functionality: System - api: HAL:HPL:DMAC - configuration: - dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer - dmac_beatsize_10: 8-bit bus transfer - dmac_beatsize_11: 8-bit bus transfer - dmac_beatsize_12: 8-bit bus transfer - dmac_beatsize_13: 8-bit bus transfer - dmac_beatsize_14: 8-bit bus transfer - dmac_beatsize_15: 8-bit bus transfer - dmac_beatsize_16: 8-bit bus transfer - dmac_beatsize_17: 8-bit bus transfer - dmac_beatsize_18: 8-bit bus transfer - dmac_beatsize_19: 8-bit bus transfer - dmac_beatsize_2: 8-bit bus transfer - dmac_beatsize_20: 8-bit bus transfer - dmac_beatsize_21: 8-bit bus transfer - dmac_beatsize_22: 8-bit bus transfer - dmac_beatsize_23: 8-bit bus transfer - dmac_beatsize_24: 8-bit bus transfer - dmac_beatsize_25: 8-bit bus transfer - dmac_beatsize_26: 8-bit bus transfer - dmac_beatsize_27: 8-bit bus transfer - dmac_beatsize_28: 8-bit bus transfer - dmac_beatsize_29: 8-bit bus transfer - dmac_beatsize_3: 8-bit bus transfer - dmac_beatsize_30: 8-bit bus transfer - dmac_beatsize_31: 8-bit bus transfer - dmac_beatsize_4: 8-bit bus transfer - dmac_beatsize_5: 8-bit bus transfer - dmac_beatsize_6: 8-bit bus transfer - dmac_beatsize_7: 8-bit bus transfer - dmac_beatsize_8: 8-bit bus transfer - dmac_beatsize_9: 8-bit bus transfer - dmac_blockact_0: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_10: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_11: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_12: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_13: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_14: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_15: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_16: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_17: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_18: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_19: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_2: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_20: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_21: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_22: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_23: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_24: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_25: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_26: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_27: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_28: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_29: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_30: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_31: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_4: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_5: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_6: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_7: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_8: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_9: Channel will be disabled if it is the last block transfer in - the transaction - dmac_channel_0_settings: false - dmac_channel_10_settings: false - dmac_channel_11_settings: false - dmac_channel_12_settings: false - dmac_channel_13_settings: false - dmac_channel_14_settings: false - dmac_channel_15_settings: false - dmac_channel_16_settings: false - dmac_channel_17_settings: false - dmac_channel_18_settings: false - dmac_channel_19_settings: false - dmac_channel_1_settings: false - dmac_channel_20_settings: false - dmac_channel_21_settings: false - dmac_channel_22_settings: false - dmac_channel_23_settings: false - dmac_channel_24_settings: false - dmac_channel_25_settings: false - dmac_channel_26_settings: false - dmac_channel_27_settings: false - dmac_channel_28_settings: false - dmac_channel_29_settings: false - dmac_channel_2_settings: false - dmac_channel_30_settings: false - dmac_channel_31_settings: false - dmac_channel_3_settings: false - dmac_channel_4_settings: false - dmac_channel_5_settings: false - dmac_channel_6_settings: false - dmac_channel_7_settings: false - dmac_channel_8_settings: false - dmac_channel_9_settings: false - dmac_dbgrun: false - dmac_dstinc_0: false - dmac_dstinc_1: false - dmac_dstinc_10: false - dmac_dstinc_11: false - dmac_dstinc_12: false - dmac_dstinc_13: false - dmac_dstinc_14: false - dmac_dstinc_15: false - dmac_dstinc_16: false - dmac_dstinc_17: false - dmac_dstinc_18: false - dmac_dstinc_19: false - dmac_dstinc_2: false - dmac_dstinc_20: false - dmac_dstinc_21: false - dmac_dstinc_22: false - dmac_dstinc_23: false - dmac_dstinc_24: false - dmac_dstinc_25: false - dmac_dstinc_26: false - dmac_dstinc_27: false - dmac_dstinc_28: false - dmac_dstinc_29: false - dmac_dstinc_3: false - dmac_dstinc_30: false - dmac_dstinc_31: false - dmac_dstinc_4: false - dmac_dstinc_5: false - dmac_dstinc_6: false - dmac_dstinc_7: false - dmac_dstinc_8: false - dmac_dstinc_9: false - dmac_enable: false - dmac_evact_0: No action - dmac_evact_1: No action - dmac_evact_10: No action - dmac_evact_11: No action - dmac_evact_12: No action - dmac_evact_13: No action - dmac_evact_14: No action - dmac_evact_15: No action - dmac_evact_16: No action - dmac_evact_17: No action - dmac_evact_18: No action - dmac_evact_19: No action - dmac_evact_2: No action - dmac_evact_20: No action - dmac_evact_21: No action - dmac_evact_22: No action - dmac_evact_23: No action - dmac_evact_24: No action - dmac_evact_25: No action - dmac_evact_26: No action - dmac_evact_27: No action - dmac_evact_28: No action - dmac_evact_29: No action - dmac_evact_3: No action - dmac_evact_30: No action - dmac_evact_31: No action - dmac_evact_4: No action - dmac_evact_5: No action - dmac_evact_6: No action - dmac_evact_7: No action - dmac_evact_8: No action - dmac_evact_9: No action - dmac_evie_0: false - dmac_evie_1: false - dmac_evie_10: false - dmac_evie_11: false - dmac_evie_12: false - dmac_evie_13: false - dmac_evie_14: false - dmac_evie_15: false - dmac_evie_16: false - dmac_evie_17: false - dmac_evie_18: false - dmac_evie_19: false - dmac_evie_2: false - dmac_evie_20: false - dmac_evie_21: false - dmac_evie_22: false - dmac_evie_23: false - dmac_evie_24: false - dmac_evie_25: false - dmac_evie_26: false - dmac_evie_27: false - dmac_evie_28: false - dmac_evie_29: false - dmac_evie_3: false - dmac_evie_30: false - dmac_evie_31: false - dmac_evie_4: false - dmac_evie_5: false - dmac_evie_6: false - dmac_evie_7: false - dmac_evie_8: false - dmac_evie_9: false - dmac_evoe_0: false - dmac_evoe_1: false - dmac_evoe_10: false - dmac_evoe_11: false - dmac_evoe_12: false - dmac_evoe_13: false - dmac_evoe_14: false - dmac_evoe_15: false - dmac_evoe_16: false - dmac_evoe_17: false - dmac_evoe_18: false - dmac_evoe_19: false - dmac_evoe_2: false - dmac_evoe_20: false - dmac_evoe_21: false - dmac_evoe_22: false - dmac_evoe_23: false - dmac_evoe_24: false - dmac_evoe_25: false - dmac_evoe_26: false - dmac_evoe_27: false - dmac_evoe_28: false - dmac_evoe_29: false - dmac_evoe_3: false - dmac_evoe_30: false - dmac_evoe_31: false - dmac_evoe_4: false - dmac_evoe_5: false - dmac_evoe_6: false - dmac_evoe_7: false - dmac_evoe_8: false - dmac_evoe_9: false - dmac_evosel_0: Event generation disabled - dmac_evosel_1: Event generation disabled - dmac_evosel_10: Event generation disabled - dmac_evosel_11: Event generation disabled - dmac_evosel_12: Event generation disabled - dmac_evosel_13: Event generation disabled - dmac_evosel_14: Event generation disabled - dmac_evosel_15: Event generation disabled - dmac_evosel_16: Event generation disabled - dmac_evosel_17: Event generation disabled - dmac_evosel_18: Event generation disabled - dmac_evosel_19: Event generation disabled - dmac_evosel_2: Event generation disabled - dmac_evosel_20: Event generation disabled - dmac_evosel_21: Event generation disabled - dmac_evosel_22: Event generation disabled - dmac_evosel_23: Event generation disabled - dmac_evosel_24: Event generation disabled - dmac_evosel_25: Event generation disabled - dmac_evosel_26: Event generation disabled - dmac_evosel_27: Event generation disabled - dmac_evosel_28: Event generation disabled - dmac_evosel_29: Event generation disabled - dmac_evosel_3: Event generation disabled - dmac_evosel_30: Event generation disabled - dmac_evosel_31: Event generation disabled - dmac_evosel_4: Event generation disabled - dmac_evosel_5: Event generation disabled - dmac_evosel_6: Event generation disabled - dmac_evosel_7: Event generation disabled - dmac_evosel_8: Event generation disabled - dmac_evosel_9: Event generation disabled - dmac_lvl_0: Channel priority 0 - dmac_lvl_1: Channel priority 0 - dmac_lvl_10: Channel priority 0 - dmac_lvl_11: Channel priority 0 - dmac_lvl_12: Channel priority 0 - dmac_lvl_13: Channel priority 0 - dmac_lvl_14: Channel priority 0 - dmac_lvl_15: Channel priority 0 - dmac_lvl_16: Channel priority 0 - dmac_lvl_17: Channel priority 0 - dmac_lvl_18: Channel priority 0 - dmac_lvl_19: Channel priority 0 - dmac_lvl_2: Channel priority 0 - dmac_lvl_20: Channel priority 0 - dmac_lvl_21: Channel priority 0 - dmac_lvl_22: Channel priority 0 - dmac_lvl_23: Channel priority 0 - dmac_lvl_24: Channel priority 0 - dmac_lvl_25: Channel priority 0 - dmac_lvl_26: Channel priority 0 - dmac_lvl_27: Channel priority 0 - dmac_lvl_28: Channel priority 0 - dmac_lvl_29: Channel priority 0 - dmac_lvl_3: Channel priority 0 - dmac_lvl_30: Channel priority 0 - dmac_lvl_31: Channel priority 0 - dmac_lvl_4: Channel priority 0 - dmac_lvl_5: Channel priority 0 - dmac_lvl_6: Channel priority 0 - dmac_lvl_7: Channel priority 0 - dmac_lvl_8: Channel priority 0 - dmac_lvl_9: Channel priority 0 - dmac_lvlen0: true - dmac_lvlen1: true - dmac_lvlen2: true - dmac_lvlen3: true - dmac_lvlpri0: 0 - dmac_lvlpri1: 0 - dmac_lvlpri2: 0 - dmac_lvlpri3: 0 - dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 - dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 - dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 - dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_runstdby_0: false - dmac_runstdby_1: false - dmac_runstdby_10: false - dmac_runstdby_11: false - dmac_runstdby_12: false - dmac_runstdby_13: false - dmac_runstdby_14: false - dmac_runstdby_15: false - dmac_runstdby_16: false - dmac_runstdby_17: false - dmac_runstdby_18: false - dmac_runstdby_19: false - dmac_runstdby_2: false - dmac_runstdby_20: false - dmac_runstdby_21: false - dmac_runstdby_22: false - dmac_runstdby_23: false - dmac_runstdby_24: false - dmac_runstdby_25: false - dmac_runstdby_26: false - dmac_runstdby_27: false - dmac_runstdby_28: false - dmac_runstdby_29: false - dmac_runstdby_3: false - dmac_runstdby_30: false - dmac_runstdby_31: false - dmac_runstdby_4: false - dmac_runstdby_5: false - dmac_runstdby_6: false - dmac_runstdby_7: false - dmac_runstdby_8: false - dmac_runstdby_9: false - dmac_srcinc_0: false - dmac_srcinc_1: false - dmac_srcinc_10: false - dmac_srcinc_11: false - dmac_srcinc_12: false - dmac_srcinc_13: false - dmac_srcinc_14: false - dmac_srcinc_15: false - dmac_srcinc_16: false - dmac_srcinc_17: false - dmac_srcinc_18: false - dmac_srcinc_19: false - dmac_srcinc_2: false - dmac_srcinc_20: false - dmac_srcinc_21: false - dmac_srcinc_22: false - dmac_srcinc_23: false - dmac_srcinc_24: false - dmac_srcinc_25: false - dmac_srcinc_26: false - dmac_srcinc_27: false - dmac_srcinc_28: false - dmac_srcinc_29: false - dmac_srcinc_3: false - dmac_srcinc_30: false - dmac_srcinc_31: false - dmac_srcinc_4: false - dmac_srcinc_5: false - dmac_srcinc_6: false - dmac_srcinc_7: false - dmac_srcinc_8: false - dmac_srcinc_9: false - dmac_stepsel_0: Step size settings apply to the destination address - dmac_stepsel_1: Step size settings apply to the destination address - dmac_stepsel_10: Step size settings apply to the destination address - dmac_stepsel_11: Step size settings apply to the destination address - dmac_stepsel_12: Step size settings apply to the destination address - dmac_stepsel_13: Step size settings apply to the destination address - dmac_stepsel_14: Step size settings apply to the destination address - dmac_stepsel_15: Step size settings apply to the destination address - dmac_stepsel_16: Step size settings apply to the destination address - dmac_stepsel_17: Step size settings apply to the destination address - dmac_stepsel_18: Step size settings apply to the destination address - dmac_stepsel_19: Step size settings apply to the destination address - dmac_stepsel_2: Step size settings apply to the destination address - dmac_stepsel_20: Step size settings apply to the destination address - dmac_stepsel_21: Step size settings apply to the destination address - dmac_stepsel_22: Step size settings apply to the destination address - dmac_stepsel_23: Step size settings apply to the destination address - dmac_stepsel_24: Step size settings apply to the destination address - dmac_stepsel_25: Step size settings apply to the destination address - dmac_stepsel_26: Step size settings apply to the destination address - dmac_stepsel_27: Step size settings apply to the destination address - dmac_stepsel_28: Step size settings apply to the destination address - dmac_stepsel_29: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address - dmac_stepsel_30: Step size settings apply to the destination address - dmac_stepsel_31: Step size settings apply to the destination address - dmac_stepsel_4: Step size settings apply to the destination address - dmac_stepsel_5: Step size settings apply to the destination address - dmac_stepsel_6: Step size settings apply to the destination address - dmac_stepsel_7: Step size settings apply to the destination address - dmac_stepsel_8: Step size settings apply to the destination address - dmac_stepsel_9: Step size settings apply to the destination address - dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_trifsrc_0: Only software/event triggers - dmac_trifsrc_1: Only software/event triggers - dmac_trifsrc_10: Only software/event triggers - dmac_trifsrc_11: Only software/event triggers - dmac_trifsrc_12: Only software/event triggers - dmac_trifsrc_13: Only software/event triggers - dmac_trifsrc_14: Only software/event triggers - dmac_trifsrc_15: Only software/event triggers - dmac_trifsrc_16: Only software/event triggers - dmac_trifsrc_17: Only software/event triggers - dmac_trifsrc_18: Only software/event triggers - dmac_trifsrc_19: Only software/event triggers - dmac_trifsrc_2: Only software/event triggers - dmac_trifsrc_20: Only software/event triggers - dmac_trifsrc_21: Only software/event triggers - dmac_trifsrc_22: Only software/event triggers - dmac_trifsrc_23: Only software/event triggers - dmac_trifsrc_24: Only software/event triggers - dmac_trifsrc_25: Only software/event triggers - dmac_trifsrc_26: Only software/event triggers - dmac_trifsrc_27: Only software/event triggers - dmac_trifsrc_28: Only software/event triggers - dmac_trifsrc_29: Only software/event triggers - dmac_trifsrc_3: Only software/event triggers - dmac_trifsrc_30: Only software/event triggers - dmac_trifsrc_31: Only software/event triggers - dmac_trifsrc_4: Only software/event triggers - dmac_trifsrc_5: Only software/event triggers - dmac_trifsrc_6: Only software/event triggers - dmac_trifsrc_7: Only software/event triggers - dmac_trifsrc_8: Only software/event triggers - dmac_trifsrc_9: Only software/event triggers - dmac_trigact_0: One trigger required for each block transfer - dmac_trigact_1: One trigger required for each block transfer - dmac_trigact_10: One trigger required for each block transfer - dmac_trigact_11: One trigger required for each block transfer - dmac_trigact_12: One trigger required for each block transfer - dmac_trigact_13: One trigger required for each block transfer - dmac_trigact_14: One trigger required for each block transfer - dmac_trigact_15: One trigger required for each block transfer - dmac_trigact_16: One trigger required for each block transfer - dmac_trigact_17: One trigger required for each block transfer - dmac_trigact_18: One trigger required for each block transfer - dmac_trigact_19: One trigger required for each block transfer - dmac_trigact_2: One trigger required for each block transfer - dmac_trigact_20: One trigger required for each block transfer - dmac_trigact_21: One trigger required for each block transfer - dmac_trigact_22: One trigger required for each block transfer - dmac_trigact_23: One trigger required for each block transfer - dmac_trigact_24: One trigger required for each block transfer - dmac_trigact_25: One trigger required for each block transfer - dmac_trigact_26: One trigger required for each block transfer - dmac_trigact_27: One trigger required for each block transfer - dmac_trigact_28: One trigger required for each block transfer - dmac_trigact_29: One trigger required for each block transfer - dmac_trigact_3: One trigger required for each block transfer - dmac_trigact_30: One trigger required for each block transfer - dmac_trigact_31: One trigger required for each block transfer - dmac_trigact_4: One trigger required for each block transfer - dmac_trigact_5: One trigger required for each block transfer - dmac_trigact_6: One trigger required for each block transfer - dmac_trigact_7: One trigger required for each block transfer - dmac_trigact_8: One trigger required for each block transfer - dmac_trigact_9: One trigger required for each block transfer - optional_signals: [] - variant: null - clocks: - domain_group: null - EXTERNAL_IRQ_0: - user_label: EXTERNAL_IRQ_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ - functionality: External_IRQ - api: HAL:Driver:Ext_IRQ - configuration: - eic_arch_asynch0: false - eic_arch_asynch1: false - eic_arch_asynch10: false - eic_arch_asynch11: false - eic_arch_asynch12: false - eic_arch_asynch13: false - eic_arch_asynch14: false - eic_arch_asynch15: false - eic_arch_asynch2: false - eic_arch_asynch3: false - eic_arch_asynch4: false - eic_arch_asynch5: false - eic_arch_asynch6: false - eic_arch_asynch7: false - eic_arch_asynch8: false - eic_arch_asynch9: false - eic_arch_cksel: Clocked by GCLK - eic_arch_debounce_enable0: false - eic_arch_debounce_enable1: false - eic_arch_debounce_enable10: false - eic_arch_debounce_enable11: false - eic_arch_debounce_enable12: false - eic_arch_debounce_enable13: false - eic_arch_debounce_enable14: false - eic_arch_debounce_enable15: false - eic_arch_debounce_enable2: false - eic_arch_debounce_enable3: false - eic_arch_debounce_enable4: false - eic_arch_debounce_enable5: false - eic_arch_debounce_enable6: false - eic_arch_debounce_enable7: false - eic_arch_debounce_enable8: false - eic_arch_debounce_enable9: false - eic_arch_enable_irq_setting0: false - eic_arch_enable_irq_setting1: false - eic_arch_enable_irq_setting10: false - eic_arch_enable_irq_setting11: false - eic_arch_enable_irq_setting12: false - eic_arch_enable_irq_setting13: false - eic_arch_enable_irq_setting14: false - eic_arch_enable_irq_setting15: false - eic_arch_enable_irq_setting2: false - eic_arch_enable_irq_setting3: false - eic_arch_enable_irq_setting4: false - eic_arch_enable_irq_setting5: false - eic_arch_enable_irq_setting6: false - eic_arch_enable_irq_setting7: false - eic_arch_enable_irq_setting8: false - eic_arch_enable_irq_setting9: false - eic_arch_extinteo0: false - eic_arch_extinteo1: false - eic_arch_extinteo10: false - eic_arch_extinteo11: false - eic_arch_extinteo12: false - eic_arch_extinteo13: false - eic_arch_extinteo14: false - eic_arch_extinteo15: false - eic_arch_extinteo2: false - eic_arch_extinteo3: false - eic_arch_extinteo4: false - eic_arch_extinteo5: false - eic_arch_extinteo6: false - eic_arch_extinteo7: false - eic_arch_extinteo8: false - eic_arch_extinteo9: false - eic_arch_filten0: false - eic_arch_filten1: false - eic_arch_filten10: false - eic_arch_filten11: false - eic_arch_filten12: false - eic_arch_filten13: false - eic_arch_filten14: false - eic_arch_filten15: false - eic_arch_filten2: false - eic_arch_filten3: false - eic_arch_filten4: false - eic_arch_filten5: false - eic_arch_filten6: false - eic_arch_filten7: false - eic_arch_filten8: false - eic_arch_filten9: false - eic_arch_nmi_ctrl: false - eic_arch_nmiasynch: false - eic_arch_nmifilten: false - eic_arch_nmisense: No detection - eic_arch_prescaler0: Divided by 2 - eic_arch_prescaler1: Divided by 2 - eic_arch_sense0: No detection - eic_arch_sense1: No detection - eic_arch_sense10: No detection - eic_arch_sense11: No detection - eic_arch_sense12: No detection - eic_arch_sense13: No detection - eic_arch_sense14: No detection - eic_arch_sense15: No detection - eic_arch_sense2: No detection - eic_arch_sense3: No detection - eic_arch_sense4: No detection - eic_arch_sense5: No detection - eic_arch_sense6: No detection - eic_arch_sense7: No detection - eic_arch_sense8: No detection - eic_arch_sense9: No detection - eic_arch_states0: '3' - eic_arch_states1: '3' - eic_arch_tickon: The sampling rate is EIC clock - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: EIC - input: Generic clock generator 0 - external: false - external_frequency: 0 - configuration: - eic_gclk_selection: Generic clock generator 0 - GCLK: - user_label: GCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK - functionality: System - api: HAL:HPL:GCLK - configuration: - enable_gclk_gen_0: true - enable_gclk_gen_0__externalclock: 1000000 - enable_gclk_gen_1: false - enable_gclk_gen_10: false - enable_gclk_gen_10__externalclock: 1000000 - enable_gclk_gen_11: false - enable_gclk_gen_11__externalclock: 1000000 - enable_gclk_gen_1__externalclock: 1000000 - enable_gclk_gen_2: false - enable_gclk_gen_2__externalclock: 1000000 - enable_gclk_gen_3: false - enable_gclk_gen_3__externalclock: 1000000 - enable_gclk_gen_4: false - enable_gclk_gen_4__externalclock: 1000000 - enable_gclk_gen_5: false - enable_gclk_gen_5__externalclock: 1000000 - enable_gclk_gen_6: false - enable_gclk_gen_6__externalclock: 1000000 - enable_gclk_gen_7: false - enable_gclk_gen_7__externalclock: 1000000 - enable_gclk_gen_8: false - enable_gclk_gen_8__externalclock: 1000000 - enable_gclk_gen_9: false - enable_gclk_gen_9__externalclock: 1000000 - gclk_arch_gen_0_enable: true - gclk_arch_gen_0_idc: false - gclk_arch_gen_0_oe: false - gclk_arch_gen_0_oov: false - gclk_arch_gen_0_runstdby: false - gclk_arch_gen_10_enable: false - gclk_arch_gen_10_idc: false - gclk_arch_gen_10_oe: false - gclk_arch_gen_10_oov: false - gclk_arch_gen_10_runstdby: false - gclk_arch_gen_11_enable: false - gclk_arch_gen_11_idc: false - gclk_arch_gen_11_oe: false - gclk_arch_gen_11_oov: false - gclk_arch_gen_11_runstdby: false - gclk_arch_gen_1_enable: false - gclk_arch_gen_1_idc: false - gclk_arch_gen_1_oe: false - gclk_arch_gen_1_oov: false - gclk_arch_gen_1_runstdby: false - gclk_arch_gen_2_enable: false - gclk_arch_gen_2_idc: false - gclk_arch_gen_2_oe: false - gclk_arch_gen_2_oov: false - gclk_arch_gen_2_runstdby: false - gclk_arch_gen_3_enable: false - gclk_arch_gen_3_idc: false - gclk_arch_gen_3_oe: false - gclk_arch_gen_3_oov: false - gclk_arch_gen_3_runstdby: false - gclk_arch_gen_4_enable: false - gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false - gclk_arch_gen_4_oov: false - gclk_arch_gen_4_runstdby: false - gclk_arch_gen_5_enable: false - gclk_arch_gen_5_idc: false - gclk_arch_gen_5_oe: false - gclk_arch_gen_5_oov: false - gclk_arch_gen_5_runstdby: false - gclk_arch_gen_6_enable: false - gclk_arch_gen_6_idc: false - gclk_arch_gen_6_oe: false - gclk_arch_gen_6_oov: false - gclk_arch_gen_6_runstdby: false - gclk_arch_gen_7_enable: false - gclk_arch_gen_7_idc: false - gclk_arch_gen_7_oe: false - gclk_arch_gen_7_oov: false - gclk_arch_gen_7_runstdby: false - gclk_arch_gen_8_enable: false - gclk_arch_gen_8_idc: false - gclk_arch_gen_8_oe: false - gclk_arch_gen_8_oov: false - gclk_arch_gen_8_runstdby: false - gclk_arch_gen_9_enable: false - gclk_arch_gen_9_idc: false - gclk_arch_gen_9_oe: false - gclk_arch_gen_9_oov: false - gclk_arch_gen_9_runstdby: false - gclk_gen_0_div: 1 - gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) - gclk_gen_10_div: 1 - gclk_gen_10_div_sel: false - gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_11_div: 1 - gclk_gen_11_div_sel: false - gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_1_div: 1 - gclk_gen_1_div_sel: false - gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) - gclk_gen_2_div: 1 - gclk_gen_2_div_sel: true - gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_3_div: 1 - gclk_gen_3_div_sel: false - gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) - gclk_gen_4_div: 1 - gclk_gen_4_div_sel: false - gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_5_div: 1 - gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_6_div: 1 - gclk_gen_6_div_sel: false - gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_7_div: 1 - gclk_gen_7_div_sel: false - gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_8_div: 1 - gclk_gen_8_div_sel: false - gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_9_div: 1 - gclk_gen_9_div_sel: false - gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - optional_signals: [] - variant: null - clocks: - domain_group: null - MCLK: - user_label: MCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK - functionality: System - api: HAL:HPL:MCLK - configuration: - cpu_clock_source: Generic clock generator 0 - cpu_div: '1' - enable_cpu_clock: true - mclk_arch_bupdiv: Divide by 8 - mclk_arch_hsdiv: Divide by 1 - mclk_arch_lpdiv: Divide by 4 - nvm_wait_states: '5' - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: CPU - input: CPU - external: false - external_frequency: 0 - configuration: {} - OSC32KCTRL: - user_label: OSC32KCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL - functionality: System - api: HAL:HPL:OSC32KCTRL - configuration: - enable_osculp32k: true - enable_rtc_source: false - enable_xosc32k: true - osculp32k_calib: 0 - osculp32k_calib_enable: false - rtc_1khz_selection: false - rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) - xosc32k_arch_cfden: false - xosc32k_arch_cfdeo: false - xosc32k_arch_cgm: Standard mode - xosc32k_arch_en1k: false - xosc32k_arch_en32k: true - xosc32k_arch_enable: true - xosc32k_arch_ondemand: true - xosc32k_arch_runstdby: false - xosc32k_arch_startup: 1000092us - xosc32k_arch_swben: false - xosc32k_arch_xtalen: true - optional_signals: [] - variant: null - clocks: - domain_group: null - OSCCTRL: - user_label: OSCCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL - functionality: System - api: HAL:HPL:OSCCTRL - configuration: - dfll_arch_bplckc: false - dfll_arch_calibration: false - dfll_arch_ccdis: false - dfll_arch_coarse: 31 - dfll_arch_cstep: 1 - dfll_arch_enable: false - dfll_arch_fine: 128 - dfll_arch_fstep: 1 - dfll_arch_llaw: false - dfll_arch_ondemand: false - dfll_arch_qldis: false - dfll_arch_runstdby: false - dfll_arch_stable: false - dfll_arch_usbcrm: false - dfll_arch_waitlock: true - dfll_mode: Open Loop Mode - dfll_mul: 0 - dfll_ref_clock: Generic clock generator 3 - enable_dfll: false - enable_fdpll0: true - enable_fdpll1: false - enable_xosc0: false - enable_xosc1: false - fdpll0_arch_dcoen: false - fdpll0_arch_enable: true - fdpll0_arch_filter: 0 - fdpll0_arch_lbypass: true - fdpll0_arch_ltime: No time-out, automatic lock - fdpll0_arch_ondemand: false - fdpll0_arch_refclk: XOSC32K clock reference - fdpll0_arch_runstdby: false - fdpll0_arch_wuf: false - fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 0 - fdpll0_ldr: 3661 - fdpll0_ldrfrac: 1 - fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - fdpll1_arch_dcoen: false - fdpll1_arch_enable: false - fdpll1_arch_filter: 0 - fdpll1_arch_lbypass: false - fdpll1_arch_ltime: No time-out, automatic lock - fdpll1_arch_ondemand: false - fdpll1_arch_refclk: XOSC32K clock reference - fdpll1_arch_runstdby: false - fdpll1_arch_wuf: false - fdpll1_clock_dcofilter: 0 - fdpll1_clock_div: 0 - fdpll1_ldr: 1463 - fdpll1_ldrfrac: 13 - fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - xosc0_arch_cfden: false - xosc0_arch_enable: false - xosc0_arch_enalc: false - xosc0_arch_lowbufgain: false - xosc0_arch_ondemand: false - xosc0_arch_runstdby: false - xosc0_arch_startup: 31us - xosc0_arch_swben: false - xosc0_arch_xtalen: false - xosc0_frequency: 12000000 - xosc1_arch_cfden: false - xosc1_arch_enable: false - xosc1_arch_enalc: false - xosc1_arch_lowbufgain: false - xosc1_arch_ondemand: false - xosc1_arch_runstdby: false - xosc1_arch_startup: 31us - xosc1_arch_swben: false - xosc1_arch_xtalen: true - xosc1_frequency: 12000000 - optional_signals: [] - variant: null - clocks: - domain_group: null - PORT: - user_label: PORT - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT - functionality: System - api: HAL:HPL:PORT - configuration: - enable_port_input_event_0: false - enable_port_input_event_1: false - enable_port_input_event_2: false - enable_port_input_event_3: false - porta_event_action_0: Output register of pin will be set to level of event - porta_event_action_1: Output register of pin will be set to level of event - porta_event_action_2: Output register of pin will be set to level of event - porta_event_action_3: Output register of pin will be set to level of event - porta_event_pin_identifier_0: 0 - porta_event_pin_identifier_1: 0 - porta_event_pin_identifier_2: 0 - porta_event_pin_identifier_3: 0 - porta_input_event_enable_0: false - porta_input_event_enable_1: false - porta_input_event_enable_2: false - porta_input_event_enable_3: false - portb_event_action_0: Output register of pin will be set to level of event - portb_event_action_1: Output register of pin will be set to level of event - portb_event_action_2: Output register of pin will be set to level of event - portb_event_action_3: Output register of pin will be set to level of event - portb_event_pin_identifier_0: 0 - portb_event_pin_identifier_1: 0 - portb_event_pin_identifier_2: 0 - portb_event_pin_identifier_3: 0 - portb_input_event_enable_0: false - portb_input_event_enable_1: false - portb_input_event_enable_2: false - portb_input_event_enable_3: false - portc_event_action_0: Output register of pin will be set to level of event - portc_event_action_1: Output register of pin will be set to level of event - portc_event_action_2: Output register of pin will be set to level of event - portc_event_action_3: Output register of pin will be set to level of event - portc_event_pin_identifier_0: 0 - portc_event_pin_identifier_1: 0 - portc_event_pin_identifier_2: 0 - portc_event_pin_identifier_3: 0 - portc_input_event_enable_0: false - portc_input_event_enable_1: false - portc_input_event_enable_2: false - portc_input_event_enable_3: false - portd_event_action_0: Output register of pin will be set to level of event - portd_event_action_1: Output register of pin will be set to level of event - portd_event_action_2: Output register of pin will be set to level of event - portd_event_action_3: Output register of pin will be set to level of event - portd_event_pin_identifier_0: 0 - portd_event_pin_identifier_1: 0 - portd_event_pin_identifier_2: 0 - portd_event_pin_identifier_3: 0 - portd_input_event_enable_0: false - portd_input_event_enable_1: false - portd_input_event_enable_2: false - portd_input_event_enable_3: false - optional_signals: [] - variant: null - clocks: - domain_group: null - RAMECC: - user_label: RAMECC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC - functionality: System - api: HAL:HPL:RAMECC - configuration: {} - optional_signals: [] - variant: null - clocks: - domain_group: null - USART_0: - user_label: USART_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async - functionality: USART - api: HAL:Driver:USART_Async - configuration: - usart_advanced: false - usart_arch_clock_mode: USART with internal clock - usart_arch_cloden: false - usart_arch_dbgstop: Keep running - usart_arch_dord: LSB is transmitted first - usart_arch_enc: No encoding - usart_arch_fractional: 0 - usart_arch_ibon: false - usart_arch_lin_slave_enable: Disable - usart_arch_runstdby: false - usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) - usart_arch_sampr: 16x arithmetic - usart_arch_sfde: false - usart_baud_rate: 115200 - usart_character_size: 8 bits - usart_parity: No parity - usart_rx_enable: true - usart_stop_bit: One stop bit - usart_tx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=1, CMODE=0 - required_signals: - - name: SERCOM2/PAD/0 - pad: PB25 - label: TX - - name: SERCOM2/PAD/1 - pad: PB24 - label: RX - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - external: false - external_frequency: 0 - - name: Slow - input: Generic clock generator 3 - external: false - external_frequency: 0 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - I2C_0: - user_label: I2C_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync - functionality: I2C - api: HAL:Driver:I2C_Master_Sync - configuration: - i2c_master_advanced: false - i2c_master_arch_dbgstop: Keep running - i2c_master_arch_inactout: Disabled - i2c_master_arch_lowtout: false - i2c_master_arch_mexttoen: false - i2c_master_arch_runstdby: false - i2c_master_arch_sdahold: 300-600ns hold time - i2c_master_arch_sexttoen: false - i2c_master_arch_trise: 215 - i2c_master_baud_rate: 100000 - optional_signals: [] - variant: - specification: SDA=0, SCL=1 - required_signals: - - name: SERCOM3/PAD/0 - pad: PA22 - label: SDA - - name: SERCOM3/PAD/1 - pad: PA23 - label: SCL - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - external: false - external_frequency: 0 - - name: Slow - input: Generic clock generator 3 - external: false - external_frequency: 0 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - tc_arch_dbgrun: false - tc_arch_evact: Event action disabled - tc_arch_mceo0: false - tc_arch_mceo1: false - tc_arch_ondemand: false - tc_arch_ovfeo: false - tc_arch_presync: Reload or reset counter on next GCLK - tc_arch_runstdby: false - tc_arch_tcei: false - tc_arch_tcinv: false - timer_advanced_configuration: false - timer_event_control: false - timer_prescaler: Divide by 8 - timer_tick: 1000 - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: TC - input: Generic clock generator 0 - external: false - external_frequency: 0 - configuration: - tc_gclk_selection: Generic clock generator 0 -pads: - PA22: - name: PA22 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22 - mode: I2C - user_label: PA22 - configuration: null - PA23: - name: PA23 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23 - mode: I2C - user_label: PA23 - configuration: null - PB24: - name: PB24 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 - mode: Peripheral IO - user_label: PB24 - configuration: null - PB25: - name: PB25 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 - mode: Peripheral IO - user_label: PB25 - configuration: null -toolchain_options: [] +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.7.303 + commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.7.303 + packs_version_avr8: 1.0.1410 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1554 + version_backend: 1.7.303 + version_frontend: '' +board: + identifier: SAME54XplainedPro + device: SAME54P20A-AU +details: null +application: null +middlewares: {} +drivers: + CMCC: + user_label: CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: false + cmcc_clock_gating_disable: false + cmcc_data_cache_disable: false + cmcc_enable: false + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: false + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: false + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: true + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EXTERNAL_IRQ_0: + user_label: EXTERNAL_IRQ_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + functionality: External_IRQ + api: HAL:Driver:Ext_IRQ + configuration: + eic_arch_asynch0: false + eic_arch_asynch1: false + eic_arch_asynch10: false + eic_arch_asynch11: false + eic_arch_asynch12: false + eic_arch_asynch13: false + eic_arch_asynch14: false + eic_arch_asynch15: false + eic_arch_asynch2: false + eic_arch_asynch3: false + eic_arch_asynch4: false + eic_arch_asynch5: false + eic_arch_asynch6: false + eic_arch_asynch7: false + eic_arch_asynch8: false + eic_arch_asynch9: false + eic_arch_cksel: Clocked by GCLK + eic_arch_debounce_enable0: false + eic_arch_debounce_enable1: false + eic_arch_debounce_enable10: false + eic_arch_debounce_enable11: false + eic_arch_debounce_enable12: false + eic_arch_debounce_enable13: false + eic_arch_debounce_enable14: false + eic_arch_debounce_enable15: false + eic_arch_debounce_enable2: false + eic_arch_debounce_enable3: false + eic_arch_debounce_enable4: false + eic_arch_debounce_enable5: false + eic_arch_debounce_enable6: false + eic_arch_debounce_enable7: false + eic_arch_debounce_enable8: false + eic_arch_debounce_enable9: false + eic_arch_enable_irq_setting0: false + eic_arch_enable_irq_setting1: false + eic_arch_enable_irq_setting10: false + eic_arch_enable_irq_setting11: false + eic_arch_enable_irq_setting12: false + eic_arch_enable_irq_setting13: false + eic_arch_enable_irq_setting14: false + eic_arch_enable_irq_setting15: false + eic_arch_enable_irq_setting2: false + eic_arch_enable_irq_setting3: false + eic_arch_enable_irq_setting4: false + eic_arch_enable_irq_setting5: false + eic_arch_enable_irq_setting6: false + eic_arch_enable_irq_setting7: false + eic_arch_enable_irq_setting8: false + eic_arch_enable_irq_setting9: false + eic_arch_extinteo0: false + eic_arch_extinteo1: false + eic_arch_extinteo10: false + eic_arch_extinteo11: false + eic_arch_extinteo12: false + eic_arch_extinteo13: false + eic_arch_extinteo14: false + eic_arch_extinteo15: false + eic_arch_extinteo2: false + eic_arch_extinteo3: false + eic_arch_extinteo4: false + eic_arch_extinteo5: false + eic_arch_extinteo6: false + eic_arch_extinteo7: false + eic_arch_extinteo8: false + eic_arch_extinteo9: false + eic_arch_filten0: false + eic_arch_filten1: false + eic_arch_filten10: false + eic_arch_filten11: false + eic_arch_filten12: false + eic_arch_filten13: false + eic_arch_filten14: false + eic_arch_filten15: false + eic_arch_filten2: false + eic_arch_filten3: false + eic_arch_filten4: false + eic_arch_filten5: false + eic_arch_filten6: false + eic_arch_filten7: false + eic_arch_filten8: false + eic_arch_filten9: false + eic_arch_nmi_ctrl: false + eic_arch_nmiasynch: false + eic_arch_nmifilten: false + eic_arch_nmisense: No detection + eic_arch_prescaler0: Divided by 2 + eic_arch_prescaler1: Divided by 2 + eic_arch_sense0: No detection + eic_arch_sense1: No detection + eic_arch_sense10: No detection + eic_arch_sense11: No detection + eic_arch_sense12: No detection + eic_arch_sense13: No detection + eic_arch_sense14: No detection + eic_arch_sense15: No detection + eic_arch_sense2: No detection + eic_arch_sense3: No detection + eic_arch_sense4: No detection + eic_arch_sense5: No detection + eic_arch_sense6: No detection + eic_arch_sense7: No detection + eic_arch_sense8: No detection + eic_arch_sense9: No detection + eic_arch_states0: '3' + eic_arch_states1: '3' + eic_arch_tickon: The sampling rate is EIC clock + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: EIC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + eic_gclk_selection: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: false + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: true + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '5' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: true + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: true + xosc32k_arch_enable: true + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 1000092us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: true + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: false + fdpll0_arch_dcoen: false + fdpll0_arch_enable: true + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: true + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 3661 + fdpll0_ldrfrac: 1 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: false + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + portc_event_action_0: Output register of pin will be set to level of event + portc_event_action_1: Output register of pin will be set to level of event + portc_event_action_2: Output register of pin will be set to level of event + portc_event_action_3: Output register of pin will be set to level of event + portc_event_pin_identifier_0: 0 + portc_event_pin_identifier_1: 0 + portc_event_pin_identifier_2: 0 + portc_event_pin_identifier_3: 0 + portc_input_event_enable_0: false + portc_input_event_enable_1: false + portc_input_event_enable_2: false + portc_input_event_enable_3: false + portd_event_action_0: Output register of pin will be set to level of event + portd_event_action_1: Output register of pin will be set to level of event + portd_event_action_2: Output register of pin will be set to level of event + portd_event_action_3: Output register of pin will be set to level of event + portd_event_pin_identifier_0: 0 + portd_event_pin_identifier_1: 0 + portd_event_pin_identifier_2: 0 + portd_event_pin_identifier_3: 0 + portd_input_event_enable_0: false + portd_input_event_enable_1: false + portd_input_event_enable_2: false + portd_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + USART_0: + user_label: USART_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async + functionality: USART + api: HAL:Driver:USART_Async + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 115200 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM2/PAD/0 + pad: PB25 + label: TX + - name: SERCOM2/PAD/1 + pad: PB24 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM3/PAD/0 + pad: PA22 + label: SDA + - name: SERCOM3/PAD/1 + pad: PA23 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::TC0::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + timer_advanced_configuration: false + timer_event_control: false + timer_prescaler: Divide by 8 + timer_tick: 1000 + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 +pads: + PA22: + name: PA22 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA22 + mode: I2C + user_label: PA22 + configuration: null + PA23: + name: PA23 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA23 + mode: I2C + user_label: PA23 + configuration: null + PB24: + name: PB24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 + mode: Peripheral IO + user_label: PB24 + configuration: null + PB25: + name: PB25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + mode: Peripheral IO + user_label: PB25 + configuration: null +toolchain_options: [] diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h index 8590736..42c1d6b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_cmcc_config.h @@ -1,54 +1,54 @@ -/* Auto-generated config file hpl_cmcc_config.h */ -#ifndef HPL_CMCC_CONFIG_H -#define HPL_CMCC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Configuration - -// Cache enable -// Defines the cache should be enabled or not. -// cmcc_enable -#ifndef CONF_CMCC_ENABLE -#define CONF_CMCC_ENABLE 0x0 -#endif - -// Cache Size -// Defines the cache memory size to be configured. -// <0x0=>1 KB -// <0x1=>2 KB -// <0x2=>4 KB -// cache_size -#ifndef CONF_CMCC_CACHE_SIZE -#define CONF_CMCC_CACHE_SIZE 0x2 -#endif - -// Advanced Configuration -// cmcc_advanced_configuration -// Data cache disable -// Defines the data cache should be disabled or not. -// cmcc_data_cache_disable -#ifndef CONF_CMCC_DATA_CACHE_DISABLE -#define CONF_CMCC_DATA_CACHE_DISABLE 0x0 -#endif - -// Instruction cache disable -// Defines the Instruction cache should be disabled or not. -// cmcc_inst_cache_disable -#ifndef CONF_CMCC_INST_CACHE_DISABLE -#define CONF_CMCC_INST_CACHE_DISABLE 0x0 -#endif - -// Clock Gating disable -// Defines the clock gating should be disabled or not. -// cmcc_clock_gating_disable -#ifndef CONF_CMCC_CLK_GATING_DISABLE -#define CONF_CMCC_CLK_GATING_DISABLE 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_CMCC_CONFIG_H +/* Auto-generated config file hpl_cmcc_config.h */ +#ifndef HPL_CMCC_CONFIG_H +#define HPL_CMCC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration + +// Cache enable +// Defines the cache should be enabled or not. +// cmcc_enable +#ifndef CONF_CMCC_ENABLE +#define CONF_CMCC_ENABLE 0x0 +#endif + +// Cache Size +// Defines the cache memory size to be configured. +// <0x0=>1 KB +// <0x1=>2 KB +// <0x2=>4 KB +// cache_size +#ifndef CONF_CMCC_CACHE_SIZE +#define CONF_CMCC_CACHE_SIZE 0x2 +#endif + +// Advanced Configuration +// cmcc_advanced_configuration +// Data cache disable +// Defines the data cache should be disabled or not. +// cmcc_data_cache_disable +#ifndef CONF_CMCC_DATA_CACHE_DISABLE +#define CONF_CMCC_DATA_CACHE_DISABLE 0x0 +#endif + +// Instruction cache disable +// Defines the Instruction cache should be disabled or not. +// cmcc_inst_cache_disable +#ifndef CONF_CMCC_INST_CACHE_DISABLE +#define CONF_CMCC_INST_CACHE_DISABLE 0x0 +#endif + +// Clock Gating disable +// Defines the clock gating should be disabled or not. +// cmcc_clock_gating_disable +#ifndef CONF_CMCC_CLK_GATING_DISABLE +#define CONF_CMCC_CLK_GATING_DISABLE 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_CMCC_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h index 90499fc..3ff3930 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_dmac_config.h @@ -1,7277 +1,7277 @@ -/* Auto-generated config file hpl_dmac_config.h */ -#ifndef HPL_DMAC_CONFIG_H -#define HPL_DMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMAC enable -// Indicates whether dmac is enabled or not -// dmac_enable -#ifndef CONF_DMAC_ENABLE -#define CONF_DMAC_ENABLE 0 -#endif - -// Priority Level 0 -// Indicates whether Priority Level 0 is enabled or not -// dmac_lvlen0 -#ifndef CONF_DMAC_LVLEN0 -#define CONF_DMAC_LVLEN0 1 -#endif - -// Level 0 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 0 -// <1=> Round-robin arbitration scheme for channel with priority 0 -// Defines Level 0 Arbitration for DMA channels -// dmac_rrlvlen0 -#ifndef CONF_DMAC_RRLVLEN0 -#define CONF_DMAC_RRLVLEN0 0 -#endif - -// Level 0 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri0 -#ifndef CONF_DMAC_LVLPRI0 -#define CONF_DMAC_LVLPRI0 0 -#endif -// Priority Level 1 -// Indicates whether Priority Level 1 is enabled or not -// dmac_lvlen1 -#ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 1 -#endif - -// Level 1 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 1 -// <1=> Round-robin arbitration scheme for channel with priority 1 -// Defines Level 1 Arbitration for DMA channels -// dmac_rrlvlen1 -#ifndef CONF_DMAC_RRLVLEN1 -#define CONF_DMAC_RRLVLEN1 0 -#endif - -// Level 1 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri1 -#ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 0 -#endif -// Priority Level 2 -// Indicates whether Priority Level 2 is enabled or not -// dmac_lvlen2 -#ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 1 -#endif - -// Level 2 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 2 -// <1=> Round-robin arbitration scheme for channel with priority 2 -// Defines Level 2 Arbitration for DMA channels -// dmac_rrlvlen2 -#ifndef CONF_DMAC_RRLVLEN2 -#define CONF_DMAC_RRLVLEN2 0 -#endif - -// Level 2 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri2 -#ifndef CONF_DMAC_LVLPRI2 -#define CONF_DMAC_LVLPRI2 0 -#endif -// Priority Level 3 -// Indicates whether Priority Level 3 is enabled or not -// dmac_lvlen3 -#ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 1 -#endif - -// Level 3 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 3 -// <1=> Round-robin arbitration scheme for channel with priority 3 -// Defines Level 3 Arbitration for DMA channels -// dmac_rrlvlen3 -#ifndef CONF_DMAC_RRLVLEN3 -#define CONF_DMAC_RRLVLEN3 0 -#endif - -// Level 3 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri3 -#ifndef CONF_DMAC_LVLPRI3 -#define CONF_DMAC_LVLPRI3 0 -#endif -// Debug Run -// Indicates whether Debug Run is enabled or not -// dmac_dbgrun -#ifndef CONF_DMAC_DBGRUN -#define CONF_DMAC_DBGRUN 0 -#endif - -// Channel 0 settings -// dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 0 is running in standby mode or not -// dmac_runstdby_0 -#ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_0 -#ifndef CONF_DMAC_TRIGACT_0 -#define CONF_DMAC_TRIGACT_0 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_0 -#ifndef CONF_DMAC_LVL_0 -#define CONF_DMAC_LVL_0 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_0 -#ifndef CONF_DMAC_EVOE_0 -#define CONF_DMAC_EVOE_0 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_0 -#ifndef CONF_DMAC_EVIE_0 -#define CONF_DMAC_EVIE_0 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_0 -#ifndef CONF_DMAC_EVACT_0 -#define CONF_DMAC_EVACT_0 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_0 -#ifndef CONF_DMAC_STEPSIZE_0 -#define CONF_DMAC_STEPSIZE_0 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_0 -#ifndef CONF_DMAC_STEPSEL_0 -#define CONF_DMAC_STEPSEL_0 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_0 -#ifndef CONF_DMAC_BLOCKACT_0 -#define CONF_DMAC_BLOCKACT_0 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_0 -#ifndef CONF_DMAC_EVOSEL_0 -#define CONF_DMAC_EVOSEL_0 0 -#endif -// - -// Channel 1 settings -// dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 1 is running in standby mode or not -// dmac_runstdby_1 -#ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_1 -#ifndef CONF_DMAC_TRIGACT_1 -#define CONF_DMAC_TRIGACT_1 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_1 -#ifndef CONF_DMAC_LVL_1 -#define CONF_DMAC_LVL_1 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_1 -#ifndef CONF_DMAC_EVOE_1 -#define CONF_DMAC_EVOE_1 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_1 -#ifndef CONF_DMAC_EVIE_1 -#define CONF_DMAC_EVIE_1 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_1 -#ifndef CONF_DMAC_EVACT_1 -#define CONF_DMAC_EVACT_1 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_1 -#ifndef CONF_DMAC_STEPSIZE_1 -#define CONF_DMAC_STEPSIZE_1 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_1 -#ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_1 -#ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_1 -#ifndef CONF_DMAC_EVOSEL_1 -#define CONF_DMAC_EVOSEL_1 0 -#endif -// - -// Channel 2 settings -// dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 2 is running in standby mode or not -// dmac_runstdby_2 -#ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_2 -#ifndef CONF_DMAC_TRIGACT_2 -#define CONF_DMAC_TRIGACT_2 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_2 -#ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_2 -#ifndef CONF_DMAC_EVOE_2 -#define CONF_DMAC_EVOE_2 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_2 -#ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_2 -#ifndef CONF_DMAC_EVACT_2 -#define CONF_DMAC_EVACT_2 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_2 -#ifndef CONF_DMAC_STEPSIZE_2 -#define CONF_DMAC_STEPSIZE_2 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_2 -#ifndef CONF_DMAC_STEPSEL_2 -#define CONF_DMAC_STEPSEL_2 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_2 -#ifndef CONF_DMAC_BLOCKACT_2 -#define CONF_DMAC_BLOCKACT_2 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_2 -#ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 0 -#endif -// - -// Channel 3 settings -// dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 3 is running in standby mode or not -// dmac_runstdby_3 -#ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_3 -#ifndef CONF_DMAC_TRIGACT_3 -#define CONF_DMAC_TRIGACT_3 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_3 -#ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_3 -#ifndef CONF_DMAC_EVOE_3 -#define CONF_DMAC_EVOE_3 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_3 -#ifndef CONF_DMAC_EVIE_3 -#define CONF_DMAC_EVIE_3 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_3 -#ifndef CONF_DMAC_EVACT_3 -#define CONF_DMAC_EVACT_3 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_3 -#ifndef CONF_DMAC_STEPSIZE_3 -#define CONF_DMAC_STEPSIZE_3 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_3 -#ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_3 -#ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_3 -#ifndef CONF_DMAC_EVOSEL_3 -#define CONF_DMAC_EVOSEL_3 0 -#endif -// - -// Channel 4 settings -// dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 4 is running in standby mode or not -// dmac_runstdby_4 -#ifndef CONF_DMAC_RUNSTDBY_4 -#define CONF_DMAC_RUNSTDBY_4 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_4 -#ifndef CONF_DMAC_TRIGACT_4 -#define CONF_DMAC_TRIGACT_4 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_4 -#ifndef CONF_DMAC_LVL_4 -#define CONF_DMAC_LVL_4 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_4 -#ifndef CONF_DMAC_EVOE_4 -#define CONF_DMAC_EVOE_4 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_4 -#ifndef CONF_DMAC_EVIE_4 -#define CONF_DMAC_EVIE_4 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_4 -#ifndef CONF_DMAC_EVACT_4 -#define CONF_DMAC_EVACT_4 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_4 -#ifndef CONF_DMAC_STEPSIZE_4 -#define CONF_DMAC_STEPSIZE_4 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_4 -#ifndef CONF_DMAC_STEPSEL_4 -#define CONF_DMAC_STEPSEL_4 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_4 -#ifndef CONF_DMAC_BLOCKACT_4 -#define CONF_DMAC_BLOCKACT_4 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_4 -#ifndef CONF_DMAC_EVOSEL_4 -#define CONF_DMAC_EVOSEL_4 0 -#endif -// - -// Channel 5 settings -// dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 5 is running in standby mode or not -// dmac_runstdby_5 -#ifndef CONF_DMAC_RUNSTDBY_5 -#define CONF_DMAC_RUNSTDBY_5 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_5 -#ifndef CONF_DMAC_TRIGACT_5 -#define CONF_DMAC_TRIGACT_5 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_5 -#ifndef CONF_DMAC_LVL_5 -#define CONF_DMAC_LVL_5 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_5 -#ifndef CONF_DMAC_EVOE_5 -#define CONF_DMAC_EVOE_5 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_5 -#ifndef CONF_DMAC_EVIE_5 -#define CONF_DMAC_EVIE_5 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_5 -#ifndef CONF_DMAC_EVACT_5 -#define CONF_DMAC_EVACT_5 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_5 -#ifndef CONF_DMAC_STEPSIZE_5 -#define CONF_DMAC_STEPSIZE_5 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_5 -#ifndef CONF_DMAC_STEPSEL_5 -#define CONF_DMAC_STEPSEL_5 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_5 -#ifndef CONF_DMAC_BLOCKACT_5 -#define CONF_DMAC_BLOCKACT_5 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_5 -#ifndef CONF_DMAC_EVOSEL_5 -#define CONF_DMAC_EVOSEL_5 0 -#endif -// - -// Channel 6 settings -// dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 6 is running in standby mode or not -// dmac_runstdby_6 -#ifndef CONF_DMAC_RUNSTDBY_6 -#define CONF_DMAC_RUNSTDBY_6 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_6 -#ifndef CONF_DMAC_TRIGACT_6 -#define CONF_DMAC_TRIGACT_6 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_6 -#ifndef CONF_DMAC_LVL_6 -#define CONF_DMAC_LVL_6 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_6 -#ifndef CONF_DMAC_EVOE_6 -#define CONF_DMAC_EVOE_6 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_6 -#ifndef CONF_DMAC_EVIE_6 -#define CONF_DMAC_EVIE_6 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_6 -#ifndef CONF_DMAC_EVACT_6 -#define CONF_DMAC_EVACT_6 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_6 -#ifndef CONF_DMAC_STEPSIZE_6 -#define CONF_DMAC_STEPSIZE_6 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_6 -#ifndef CONF_DMAC_STEPSEL_6 -#define CONF_DMAC_STEPSEL_6 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_6 -#ifndef CONF_DMAC_BLOCKACT_6 -#define CONF_DMAC_BLOCKACT_6 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_6 -#ifndef CONF_DMAC_EVOSEL_6 -#define CONF_DMAC_EVOSEL_6 0 -#endif -// - -// Channel 7 settings -// dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 7 is running in standby mode or not -// dmac_runstdby_7 -#ifndef CONF_DMAC_RUNSTDBY_7 -#define CONF_DMAC_RUNSTDBY_7 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_7 -#ifndef CONF_DMAC_TRIGACT_7 -#define CONF_DMAC_TRIGACT_7 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_7 -#ifndef CONF_DMAC_LVL_7 -#define CONF_DMAC_LVL_7 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_7 -#ifndef CONF_DMAC_EVOE_7 -#define CONF_DMAC_EVOE_7 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_7 -#ifndef CONF_DMAC_EVIE_7 -#define CONF_DMAC_EVIE_7 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_7 -#ifndef CONF_DMAC_EVACT_7 -#define CONF_DMAC_EVACT_7 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_7 -#ifndef CONF_DMAC_STEPSIZE_7 -#define CONF_DMAC_STEPSIZE_7 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_7 -#ifndef CONF_DMAC_STEPSEL_7 -#define CONF_DMAC_STEPSEL_7 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_7 -#ifndef CONF_DMAC_BLOCKACT_7 -#define CONF_DMAC_BLOCKACT_7 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_7 -#ifndef CONF_DMAC_EVOSEL_7 -#define CONF_DMAC_EVOSEL_7 0 -#endif -// - -// Channel 8 settings -// dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 8 is running in standby mode or not -// dmac_runstdby_8 -#ifndef CONF_DMAC_RUNSTDBY_8 -#define CONF_DMAC_RUNSTDBY_8 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_8 -#ifndef CONF_DMAC_TRIGACT_8 -#define CONF_DMAC_TRIGACT_8 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_8 -#ifndef CONF_DMAC_LVL_8 -#define CONF_DMAC_LVL_8 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_8 -#ifndef CONF_DMAC_EVOE_8 -#define CONF_DMAC_EVOE_8 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_8 -#ifndef CONF_DMAC_EVIE_8 -#define CONF_DMAC_EVIE_8 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_8 -#ifndef CONF_DMAC_EVACT_8 -#define CONF_DMAC_EVACT_8 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_8 -#ifndef CONF_DMAC_STEPSIZE_8 -#define CONF_DMAC_STEPSIZE_8 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_8 -#ifndef CONF_DMAC_STEPSEL_8 -#define CONF_DMAC_STEPSEL_8 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_8 -#ifndef CONF_DMAC_BLOCKACT_8 -#define CONF_DMAC_BLOCKACT_8 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_8 -#ifndef CONF_DMAC_EVOSEL_8 -#define CONF_DMAC_EVOSEL_8 0 -#endif -// - -// Channel 9 settings -// dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 9 is running in standby mode or not -// dmac_runstdby_9 -#ifndef CONF_DMAC_RUNSTDBY_9 -#define CONF_DMAC_RUNSTDBY_9 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_9 -#ifndef CONF_DMAC_TRIGACT_9 -#define CONF_DMAC_TRIGACT_9 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_9 -#ifndef CONF_DMAC_LVL_9 -#define CONF_DMAC_LVL_9 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_9 -#ifndef CONF_DMAC_EVOE_9 -#define CONF_DMAC_EVOE_9 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_9 -#ifndef CONF_DMAC_EVIE_9 -#define CONF_DMAC_EVIE_9 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_9 -#ifndef CONF_DMAC_EVACT_9 -#define CONF_DMAC_EVACT_9 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_9 -#ifndef CONF_DMAC_STEPSIZE_9 -#define CONF_DMAC_STEPSIZE_9 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_9 -#ifndef CONF_DMAC_STEPSEL_9 -#define CONF_DMAC_STEPSEL_9 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_9 -#ifndef CONF_DMAC_BLOCKACT_9 -#define CONF_DMAC_BLOCKACT_9 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_9 -#ifndef CONF_DMAC_EVOSEL_9 -#define CONF_DMAC_EVOSEL_9 0 -#endif -// - -// Channel 10 settings -// dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 10 is running in standby mode or not -// dmac_runstdby_10 -#ifndef CONF_DMAC_RUNSTDBY_10 -#define CONF_DMAC_RUNSTDBY_10 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_10 -#ifndef CONF_DMAC_TRIGACT_10 -#define CONF_DMAC_TRIGACT_10 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_10 -#ifndef CONF_DMAC_LVL_10 -#define CONF_DMAC_LVL_10 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_10 -#ifndef CONF_DMAC_EVOE_10 -#define CONF_DMAC_EVOE_10 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_10 -#ifndef CONF_DMAC_EVIE_10 -#define CONF_DMAC_EVIE_10 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_10 -#ifndef CONF_DMAC_EVACT_10 -#define CONF_DMAC_EVACT_10 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_10 -#ifndef CONF_DMAC_STEPSIZE_10 -#define CONF_DMAC_STEPSIZE_10 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_10 -#ifndef CONF_DMAC_STEPSEL_10 -#define CONF_DMAC_STEPSEL_10 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_10 -#ifndef CONF_DMAC_BLOCKACT_10 -#define CONF_DMAC_BLOCKACT_10 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_10 -#ifndef CONF_DMAC_EVOSEL_10 -#define CONF_DMAC_EVOSEL_10 0 -#endif -// - -// Channel 11 settings -// dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 11 is running in standby mode or not -// dmac_runstdby_11 -#ifndef CONF_DMAC_RUNSTDBY_11 -#define CONF_DMAC_RUNSTDBY_11 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_11 -#ifndef CONF_DMAC_TRIGACT_11 -#define CONF_DMAC_TRIGACT_11 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_11 -#ifndef CONF_DMAC_LVL_11 -#define CONF_DMAC_LVL_11 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_11 -#ifndef CONF_DMAC_EVOE_11 -#define CONF_DMAC_EVOE_11 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_11 -#ifndef CONF_DMAC_EVIE_11 -#define CONF_DMAC_EVIE_11 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_11 -#ifndef CONF_DMAC_EVACT_11 -#define CONF_DMAC_EVACT_11 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_11 -#ifndef CONF_DMAC_STEPSIZE_11 -#define CONF_DMAC_STEPSIZE_11 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_11 -#ifndef CONF_DMAC_STEPSEL_11 -#define CONF_DMAC_STEPSEL_11 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_11 -#ifndef CONF_DMAC_BLOCKACT_11 -#define CONF_DMAC_BLOCKACT_11 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_11 -#ifndef CONF_DMAC_EVOSEL_11 -#define CONF_DMAC_EVOSEL_11 0 -#endif -// - -// Channel 12 settings -// dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 12 is running in standby mode or not -// dmac_runstdby_12 -#ifndef CONF_DMAC_RUNSTDBY_12 -#define CONF_DMAC_RUNSTDBY_12 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_12 -#ifndef CONF_DMAC_TRIGACT_12 -#define CONF_DMAC_TRIGACT_12 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_12 -#ifndef CONF_DMAC_LVL_12 -#define CONF_DMAC_LVL_12 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_12 -#ifndef CONF_DMAC_EVOE_12 -#define CONF_DMAC_EVOE_12 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_12 -#ifndef CONF_DMAC_EVIE_12 -#define CONF_DMAC_EVIE_12 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_12 -#ifndef CONF_DMAC_EVACT_12 -#define CONF_DMAC_EVACT_12 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_12 -#ifndef CONF_DMAC_STEPSIZE_12 -#define CONF_DMAC_STEPSIZE_12 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_12 -#ifndef CONF_DMAC_STEPSEL_12 -#define CONF_DMAC_STEPSEL_12 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_12 -#ifndef CONF_DMAC_BLOCKACT_12 -#define CONF_DMAC_BLOCKACT_12 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_12 -#ifndef CONF_DMAC_EVOSEL_12 -#define CONF_DMAC_EVOSEL_12 0 -#endif -// - -// Channel 13 settings -// dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 13 is running in standby mode or not -// dmac_runstdby_13 -#ifndef CONF_DMAC_RUNSTDBY_13 -#define CONF_DMAC_RUNSTDBY_13 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_13 -#ifndef CONF_DMAC_TRIGACT_13 -#define CONF_DMAC_TRIGACT_13 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_13 -#ifndef CONF_DMAC_LVL_13 -#define CONF_DMAC_LVL_13 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_13 -#ifndef CONF_DMAC_EVOE_13 -#define CONF_DMAC_EVOE_13 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_13 -#ifndef CONF_DMAC_EVIE_13 -#define CONF_DMAC_EVIE_13 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_13 -#ifndef CONF_DMAC_EVACT_13 -#define CONF_DMAC_EVACT_13 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_13 -#ifndef CONF_DMAC_STEPSIZE_13 -#define CONF_DMAC_STEPSIZE_13 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_13 -#ifndef CONF_DMAC_STEPSEL_13 -#define CONF_DMAC_STEPSEL_13 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_13 -#ifndef CONF_DMAC_BLOCKACT_13 -#define CONF_DMAC_BLOCKACT_13 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_13 -#ifndef CONF_DMAC_EVOSEL_13 -#define CONF_DMAC_EVOSEL_13 0 -#endif -// - -// Channel 14 settings -// dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 14 is running in standby mode or not -// dmac_runstdby_14 -#ifndef CONF_DMAC_RUNSTDBY_14 -#define CONF_DMAC_RUNSTDBY_14 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_14 -#ifndef CONF_DMAC_TRIGACT_14 -#define CONF_DMAC_TRIGACT_14 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_14 -#ifndef CONF_DMAC_LVL_14 -#define CONF_DMAC_LVL_14 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_14 -#ifndef CONF_DMAC_EVOE_14 -#define CONF_DMAC_EVOE_14 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_14 -#ifndef CONF_DMAC_EVIE_14 -#define CONF_DMAC_EVIE_14 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_14 -#ifndef CONF_DMAC_EVACT_14 -#define CONF_DMAC_EVACT_14 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_14 -#ifndef CONF_DMAC_STEPSIZE_14 -#define CONF_DMAC_STEPSIZE_14 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_14 -#ifndef CONF_DMAC_STEPSEL_14 -#define CONF_DMAC_STEPSEL_14 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_14 -#ifndef CONF_DMAC_BLOCKACT_14 -#define CONF_DMAC_BLOCKACT_14 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_14 -#ifndef CONF_DMAC_EVOSEL_14 -#define CONF_DMAC_EVOSEL_14 0 -#endif -// - -// Channel 15 settings -// dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 15 is running in standby mode or not -// dmac_runstdby_15 -#ifndef CONF_DMAC_RUNSTDBY_15 -#define CONF_DMAC_RUNSTDBY_15 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_15 -#ifndef CONF_DMAC_TRIGACT_15 -#define CONF_DMAC_TRIGACT_15 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_15 -#ifndef CONF_DMAC_LVL_15 -#define CONF_DMAC_LVL_15 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_15 -#ifndef CONF_DMAC_EVOE_15 -#define CONF_DMAC_EVOE_15 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_15 -#ifndef CONF_DMAC_EVIE_15 -#define CONF_DMAC_EVIE_15 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_15 -#ifndef CONF_DMAC_EVACT_15 -#define CONF_DMAC_EVACT_15 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_15 -#ifndef CONF_DMAC_STEPSIZE_15 -#define CONF_DMAC_STEPSIZE_15 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_15 -#ifndef CONF_DMAC_STEPSEL_15 -#define CONF_DMAC_STEPSEL_15 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_15 -#ifndef CONF_DMAC_BLOCKACT_15 -#define CONF_DMAC_BLOCKACT_15 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_15 -#ifndef CONF_DMAC_EVOSEL_15 -#define CONF_DMAC_EVOSEL_15 0 -#endif -// - -// Channel 16 settings -// dmac_channel_16_settings -#ifndef CONF_DMAC_CHANNEL_16_SETTINGS -#define CONF_DMAC_CHANNEL_16_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 16 is running in standby mode or not -// dmac_runstdby_16 -#ifndef CONF_DMAC_RUNSTDBY_16 -#define CONF_DMAC_RUNSTDBY_16 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_16 -#ifndef CONF_DMAC_TRIGACT_16 -#define CONF_DMAC_TRIGACT_16 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_16 -#ifndef CONF_DMAC_TRIGSRC_16 -#define CONF_DMAC_TRIGSRC_16 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_16 -#ifndef CONF_DMAC_LVL_16 -#define CONF_DMAC_LVL_16 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_16 -#ifndef CONF_DMAC_EVOE_16 -#define CONF_DMAC_EVOE_16 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_16 -#ifndef CONF_DMAC_EVIE_16 -#define CONF_DMAC_EVIE_16 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_16 -#ifndef CONF_DMAC_EVACT_16 -#define CONF_DMAC_EVACT_16 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_16 -#ifndef CONF_DMAC_STEPSIZE_16 -#define CONF_DMAC_STEPSIZE_16 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_16 -#ifndef CONF_DMAC_STEPSEL_16 -#define CONF_DMAC_STEPSEL_16 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_16 -#ifndef CONF_DMAC_SRCINC_16 -#define CONF_DMAC_SRCINC_16 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_16 -#ifndef CONF_DMAC_DSTINC_16 -#define CONF_DMAC_DSTINC_16 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_16 -#ifndef CONF_DMAC_BEATSIZE_16 -#define CONF_DMAC_BEATSIZE_16 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_16 -#ifndef CONF_DMAC_BLOCKACT_16 -#define CONF_DMAC_BLOCKACT_16 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_16 -#ifndef CONF_DMAC_EVOSEL_16 -#define CONF_DMAC_EVOSEL_16 0 -#endif -// - -// Channel 17 settings -// dmac_channel_17_settings -#ifndef CONF_DMAC_CHANNEL_17_SETTINGS -#define CONF_DMAC_CHANNEL_17_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 17 is running in standby mode or not -// dmac_runstdby_17 -#ifndef CONF_DMAC_RUNSTDBY_17 -#define CONF_DMAC_RUNSTDBY_17 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_17 -#ifndef CONF_DMAC_TRIGACT_17 -#define CONF_DMAC_TRIGACT_17 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_17 -#ifndef CONF_DMAC_TRIGSRC_17 -#define CONF_DMAC_TRIGSRC_17 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_17 -#ifndef CONF_DMAC_LVL_17 -#define CONF_DMAC_LVL_17 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_17 -#ifndef CONF_DMAC_EVOE_17 -#define CONF_DMAC_EVOE_17 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_17 -#ifndef CONF_DMAC_EVIE_17 -#define CONF_DMAC_EVIE_17 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_17 -#ifndef CONF_DMAC_EVACT_17 -#define CONF_DMAC_EVACT_17 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_17 -#ifndef CONF_DMAC_STEPSIZE_17 -#define CONF_DMAC_STEPSIZE_17 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_17 -#ifndef CONF_DMAC_STEPSEL_17 -#define CONF_DMAC_STEPSEL_17 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_17 -#ifndef CONF_DMAC_SRCINC_17 -#define CONF_DMAC_SRCINC_17 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_17 -#ifndef CONF_DMAC_DSTINC_17 -#define CONF_DMAC_DSTINC_17 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_17 -#ifndef CONF_DMAC_BEATSIZE_17 -#define CONF_DMAC_BEATSIZE_17 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_17 -#ifndef CONF_DMAC_BLOCKACT_17 -#define CONF_DMAC_BLOCKACT_17 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_17 -#ifndef CONF_DMAC_EVOSEL_17 -#define CONF_DMAC_EVOSEL_17 0 -#endif -// - -// Channel 18 settings -// dmac_channel_18_settings -#ifndef CONF_DMAC_CHANNEL_18_SETTINGS -#define CONF_DMAC_CHANNEL_18_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 18 is running in standby mode or not -// dmac_runstdby_18 -#ifndef CONF_DMAC_RUNSTDBY_18 -#define CONF_DMAC_RUNSTDBY_18 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_18 -#ifndef CONF_DMAC_TRIGACT_18 -#define CONF_DMAC_TRIGACT_18 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_18 -#ifndef CONF_DMAC_TRIGSRC_18 -#define CONF_DMAC_TRIGSRC_18 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_18 -#ifndef CONF_DMAC_LVL_18 -#define CONF_DMAC_LVL_18 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_18 -#ifndef CONF_DMAC_EVOE_18 -#define CONF_DMAC_EVOE_18 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_18 -#ifndef CONF_DMAC_EVIE_18 -#define CONF_DMAC_EVIE_18 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_18 -#ifndef CONF_DMAC_EVACT_18 -#define CONF_DMAC_EVACT_18 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_18 -#ifndef CONF_DMAC_STEPSIZE_18 -#define CONF_DMAC_STEPSIZE_18 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_18 -#ifndef CONF_DMAC_STEPSEL_18 -#define CONF_DMAC_STEPSEL_18 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_18 -#ifndef CONF_DMAC_SRCINC_18 -#define CONF_DMAC_SRCINC_18 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_18 -#ifndef CONF_DMAC_DSTINC_18 -#define CONF_DMAC_DSTINC_18 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_18 -#ifndef CONF_DMAC_BEATSIZE_18 -#define CONF_DMAC_BEATSIZE_18 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_18 -#ifndef CONF_DMAC_BLOCKACT_18 -#define CONF_DMAC_BLOCKACT_18 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_18 -#ifndef CONF_DMAC_EVOSEL_18 -#define CONF_DMAC_EVOSEL_18 0 -#endif -// - -// Channel 19 settings -// dmac_channel_19_settings -#ifndef CONF_DMAC_CHANNEL_19_SETTINGS -#define CONF_DMAC_CHANNEL_19_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 19 is running in standby mode or not -// dmac_runstdby_19 -#ifndef CONF_DMAC_RUNSTDBY_19 -#define CONF_DMAC_RUNSTDBY_19 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_19 -#ifndef CONF_DMAC_TRIGACT_19 -#define CONF_DMAC_TRIGACT_19 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_19 -#ifndef CONF_DMAC_TRIGSRC_19 -#define CONF_DMAC_TRIGSRC_19 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_19 -#ifndef CONF_DMAC_LVL_19 -#define CONF_DMAC_LVL_19 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_19 -#ifndef CONF_DMAC_EVOE_19 -#define CONF_DMAC_EVOE_19 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_19 -#ifndef CONF_DMAC_EVIE_19 -#define CONF_DMAC_EVIE_19 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_19 -#ifndef CONF_DMAC_EVACT_19 -#define CONF_DMAC_EVACT_19 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_19 -#ifndef CONF_DMAC_STEPSIZE_19 -#define CONF_DMAC_STEPSIZE_19 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_19 -#ifndef CONF_DMAC_STEPSEL_19 -#define CONF_DMAC_STEPSEL_19 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_19 -#ifndef CONF_DMAC_SRCINC_19 -#define CONF_DMAC_SRCINC_19 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_19 -#ifndef CONF_DMAC_DSTINC_19 -#define CONF_DMAC_DSTINC_19 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_19 -#ifndef CONF_DMAC_BEATSIZE_19 -#define CONF_DMAC_BEATSIZE_19 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_19 -#ifndef CONF_DMAC_BLOCKACT_19 -#define CONF_DMAC_BLOCKACT_19 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_19 -#ifndef CONF_DMAC_EVOSEL_19 -#define CONF_DMAC_EVOSEL_19 0 -#endif -// - -// Channel 20 settings -// dmac_channel_20_settings -#ifndef CONF_DMAC_CHANNEL_20_SETTINGS -#define CONF_DMAC_CHANNEL_20_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 20 is running in standby mode or not -// dmac_runstdby_20 -#ifndef CONF_DMAC_RUNSTDBY_20 -#define CONF_DMAC_RUNSTDBY_20 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_20 -#ifndef CONF_DMAC_TRIGACT_20 -#define CONF_DMAC_TRIGACT_20 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_20 -#ifndef CONF_DMAC_TRIGSRC_20 -#define CONF_DMAC_TRIGSRC_20 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_20 -#ifndef CONF_DMAC_LVL_20 -#define CONF_DMAC_LVL_20 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_20 -#ifndef CONF_DMAC_EVOE_20 -#define CONF_DMAC_EVOE_20 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_20 -#ifndef CONF_DMAC_EVIE_20 -#define CONF_DMAC_EVIE_20 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_20 -#ifndef CONF_DMAC_EVACT_20 -#define CONF_DMAC_EVACT_20 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_20 -#ifndef CONF_DMAC_STEPSIZE_20 -#define CONF_DMAC_STEPSIZE_20 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_20 -#ifndef CONF_DMAC_STEPSEL_20 -#define CONF_DMAC_STEPSEL_20 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_20 -#ifndef CONF_DMAC_SRCINC_20 -#define CONF_DMAC_SRCINC_20 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_20 -#ifndef CONF_DMAC_DSTINC_20 -#define CONF_DMAC_DSTINC_20 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_20 -#ifndef CONF_DMAC_BEATSIZE_20 -#define CONF_DMAC_BEATSIZE_20 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_20 -#ifndef CONF_DMAC_BLOCKACT_20 -#define CONF_DMAC_BLOCKACT_20 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_20 -#ifndef CONF_DMAC_EVOSEL_20 -#define CONF_DMAC_EVOSEL_20 0 -#endif -// - -// Channel 21 settings -// dmac_channel_21_settings -#ifndef CONF_DMAC_CHANNEL_21_SETTINGS -#define CONF_DMAC_CHANNEL_21_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 21 is running in standby mode or not -// dmac_runstdby_21 -#ifndef CONF_DMAC_RUNSTDBY_21 -#define CONF_DMAC_RUNSTDBY_21 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_21 -#ifndef CONF_DMAC_TRIGACT_21 -#define CONF_DMAC_TRIGACT_21 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_21 -#ifndef CONF_DMAC_TRIGSRC_21 -#define CONF_DMAC_TRIGSRC_21 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_21 -#ifndef CONF_DMAC_LVL_21 -#define CONF_DMAC_LVL_21 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_21 -#ifndef CONF_DMAC_EVOE_21 -#define CONF_DMAC_EVOE_21 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_21 -#ifndef CONF_DMAC_EVIE_21 -#define CONF_DMAC_EVIE_21 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_21 -#ifndef CONF_DMAC_EVACT_21 -#define CONF_DMAC_EVACT_21 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_21 -#ifndef CONF_DMAC_STEPSIZE_21 -#define CONF_DMAC_STEPSIZE_21 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_21 -#ifndef CONF_DMAC_STEPSEL_21 -#define CONF_DMAC_STEPSEL_21 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_21 -#ifndef CONF_DMAC_SRCINC_21 -#define CONF_DMAC_SRCINC_21 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_21 -#ifndef CONF_DMAC_DSTINC_21 -#define CONF_DMAC_DSTINC_21 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_21 -#ifndef CONF_DMAC_BEATSIZE_21 -#define CONF_DMAC_BEATSIZE_21 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_21 -#ifndef CONF_DMAC_BLOCKACT_21 -#define CONF_DMAC_BLOCKACT_21 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_21 -#ifndef CONF_DMAC_EVOSEL_21 -#define CONF_DMAC_EVOSEL_21 0 -#endif -// - -// Channel 22 settings -// dmac_channel_22_settings -#ifndef CONF_DMAC_CHANNEL_22_SETTINGS -#define CONF_DMAC_CHANNEL_22_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 22 is running in standby mode or not -// dmac_runstdby_22 -#ifndef CONF_DMAC_RUNSTDBY_22 -#define CONF_DMAC_RUNSTDBY_22 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_22 -#ifndef CONF_DMAC_TRIGACT_22 -#define CONF_DMAC_TRIGACT_22 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_22 -#ifndef CONF_DMAC_TRIGSRC_22 -#define CONF_DMAC_TRIGSRC_22 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_22 -#ifndef CONF_DMAC_LVL_22 -#define CONF_DMAC_LVL_22 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_22 -#ifndef CONF_DMAC_EVOE_22 -#define CONF_DMAC_EVOE_22 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_22 -#ifndef CONF_DMAC_EVIE_22 -#define CONF_DMAC_EVIE_22 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_22 -#ifndef CONF_DMAC_EVACT_22 -#define CONF_DMAC_EVACT_22 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_22 -#ifndef CONF_DMAC_STEPSIZE_22 -#define CONF_DMAC_STEPSIZE_22 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_22 -#ifndef CONF_DMAC_STEPSEL_22 -#define CONF_DMAC_STEPSEL_22 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_22 -#ifndef CONF_DMAC_SRCINC_22 -#define CONF_DMAC_SRCINC_22 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_22 -#ifndef CONF_DMAC_DSTINC_22 -#define CONF_DMAC_DSTINC_22 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_22 -#ifndef CONF_DMAC_BEATSIZE_22 -#define CONF_DMAC_BEATSIZE_22 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_22 -#ifndef CONF_DMAC_BLOCKACT_22 -#define CONF_DMAC_BLOCKACT_22 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_22 -#ifndef CONF_DMAC_EVOSEL_22 -#define CONF_DMAC_EVOSEL_22 0 -#endif -// - -// Channel 23 settings -// dmac_channel_23_settings -#ifndef CONF_DMAC_CHANNEL_23_SETTINGS -#define CONF_DMAC_CHANNEL_23_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 23 is running in standby mode or not -// dmac_runstdby_23 -#ifndef CONF_DMAC_RUNSTDBY_23 -#define CONF_DMAC_RUNSTDBY_23 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_23 -#ifndef CONF_DMAC_TRIGACT_23 -#define CONF_DMAC_TRIGACT_23 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_23 -#ifndef CONF_DMAC_TRIGSRC_23 -#define CONF_DMAC_TRIGSRC_23 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_23 -#ifndef CONF_DMAC_LVL_23 -#define CONF_DMAC_LVL_23 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_23 -#ifndef CONF_DMAC_EVOE_23 -#define CONF_DMAC_EVOE_23 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_23 -#ifndef CONF_DMAC_EVIE_23 -#define CONF_DMAC_EVIE_23 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_23 -#ifndef CONF_DMAC_EVACT_23 -#define CONF_DMAC_EVACT_23 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_23 -#ifndef CONF_DMAC_STEPSIZE_23 -#define CONF_DMAC_STEPSIZE_23 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_23 -#ifndef CONF_DMAC_STEPSEL_23 -#define CONF_DMAC_STEPSEL_23 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_23 -#ifndef CONF_DMAC_SRCINC_23 -#define CONF_DMAC_SRCINC_23 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_23 -#ifndef CONF_DMAC_DSTINC_23 -#define CONF_DMAC_DSTINC_23 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_23 -#ifndef CONF_DMAC_BEATSIZE_23 -#define CONF_DMAC_BEATSIZE_23 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_23 -#ifndef CONF_DMAC_BLOCKACT_23 -#define CONF_DMAC_BLOCKACT_23 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_23 -#ifndef CONF_DMAC_EVOSEL_23 -#define CONF_DMAC_EVOSEL_23 0 -#endif -// - -// Channel 24 settings -// dmac_channel_24_settings -#ifndef CONF_DMAC_CHANNEL_24_SETTINGS -#define CONF_DMAC_CHANNEL_24_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 24 is running in standby mode or not -// dmac_runstdby_24 -#ifndef CONF_DMAC_RUNSTDBY_24 -#define CONF_DMAC_RUNSTDBY_24 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_24 -#ifndef CONF_DMAC_TRIGACT_24 -#define CONF_DMAC_TRIGACT_24 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_24 -#ifndef CONF_DMAC_TRIGSRC_24 -#define CONF_DMAC_TRIGSRC_24 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_24 -#ifndef CONF_DMAC_LVL_24 -#define CONF_DMAC_LVL_24 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_24 -#ifndef CONF_DMAC_EVOE_24 -#define CONF_DMAC_EVOE_24 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_24 -#ifndef CONF_DMAC_EVIE_24 -#define CONF_DMAC_EVIE_24 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_24 -#ifndef CONF_DMAC_EVACT_24 -#define CONF_DMAC_EVACT_24 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_24 -#ifndef CONF_DMAC_STEPSIZE_24 -#define CONF_DMAC_STEPSIZE_24 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_24 -#ifndef CONF_DMAC_STEPSEL_24 -#define CONF_DMAC_STEPSEL_24 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_24 -#ifndef CONF_DMAC_SRCINC_24 -#define CONF_DMAC_SRCINC_24 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_24 -#ifndef CONF_DMAC_DSTINC_24 -#define CONF_DMAC_DSTINC_24 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_24 -#ifndef CONF_DMAC_BEATSIZE_24 -#define CONF_DMAC_BEATSIZE_24 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_24 -#ifndef CONF_DMAC_BLOCKACT_24 -#define CONF_DMAC_BLOCKACT_24 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_24 -#ifndef CONF_DMAC_EVOSEL_24 -#define CONF_DMAC_EVOSEL_24 0 -#endif -// - -// Channel 25 settings -// dmac_channel_25_settings -#ifndef CONF_DMAC_CHANNEL_25_SETTINGS -#define CONF_DMAC_CHANNEL_25_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 25 is running in standby mode or not -// dmac_runstdby_25 -#ifndef CONF_DMAC_RUNSTDBY_25 -#define CONF_DMAC_RUNSTDBY_25 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_25 -#ifndef CONF_DMAC_TRIGACT_25 -#define CONF_DMAC_TRIGACT_25 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_25 -#ifndef CONF_DMAC_TRIGSRC_25 -#define CONF_DMAC_TRIGSRC_25 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_25 -#ifndef CONF_DMAC_LVL_25 -#define CONF_DMAC_LVL_25 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_25 -#ifndef CONF_DMAC_EVOE_25 -#define CONF_DMAC_EVOE_25 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_25 -#ifndef CONF_DMAC_EVIE_25 -#define CONF_DMAC_EVIE_25 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_25 -#ifndef CONF_DMAC_EVACT_25 -#define CONF_DMAC_EVACT_25 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_25 -#ifndef CONF_DMAC_STEPSIZE_25 -#define CONF_DMAC_STEPSIZE_25 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_25 -#ifndef CONF_DMAC_STEPSEL_25 -#define CONF_DMAC_STEPSEL_25 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_25 -#ifndef CONF_DMAC_SRCINC_25 -#define CONF_DMAC_SRCINC_25 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_25 -#ifndef CONF_DMAC_DSTINC_25 -#define CONF_DMAC_DSTINC_25 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_25 -#ifndef CONF_DMAC_BEATSIZE_25 -#define CONF_DMAC_BEATSIZE_25 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_25 -#ifndef CONF_DMAC_BLOCKACT_25 -#define CONF_DMAC_BLOCKACT_25 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_25 -#ifndef CONF_DMAC_EVOSEL_25 -#define CONF_DMAC_EVOSEL_25 0 -#endif -// - -// Channel 26 settings -// dmac_channel_26_settings -#ifndef CONF_DMAC_CHANNEL_26_SETTINGS -#define CONF_DMAC_CHANNEL_26_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 26 is running in standby mode or not -// dmac_runstdby_26 -#ifndef CONF_DMAC_RUNSTDBY_26 -#define CONF_DMAC_RUNSTDBY_26 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_26 -#ifndef CONF_DMAC_TRIGACT_26 -#define CONF_DMAC_TRIGACT_26 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_26 -#ifndef CONF_DMAC_TRIGSRC_26 -#define CONF_DMAC_TRIGSRC_26 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_26 -#ifndef CONF_DMAC_LVL_26 -#define CONF_DMAC_LVL_26 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_26 -#ifndef CONF_DMAC_EVOE_26 -#define CONF_DMAC_EVOE_26 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_26 -#ifndef CONF_DMAC_EVIE_26 -#define CONF_DMAC_EVIE_26 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_26 -#ifndef CONF_DMAC_EVACT_26 -#define CONF_DMAC_EVACT_26 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_26 -#ifndef CONF_DMAC_STEPSIZE_26 -#define CONF_DMAC_STEPSIZE_26 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_26 -#ifndef CONF_DMAC_STEPSEL_26 -#define CONF_DMAC_STEPSEL_26 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_26 -#ifndef CONF_DMAC_SRCINC_26 -#define CONF_DMAC_SRCINC_26 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_26 -#ifndef CONF_DMAC_DSTINC_26 -#define CONF_DMAC_DSTINC_26 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_26 -#ifndef CONF_DMAC_BEATSIZE_26 -#define CONF_DMAC_BEATSIZE_26 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_26 -#ifndef CONF_DMAC_BLOCKACT_26 -#define CONF_DMAC_BLOCKACT_26 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_26 -#ifndef CONF_DMAC_EVOSEL_26 -#define CONF_DMAC_EVOSEL_26 0 -#endif -// - -// Channel 27 settings -// dmac_channel_27_settings -#ifndef CONF_DMAC_CHANNEL_27_SETTINGS -#define CONF_DMAC_CHANNEL_27_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 27 is running in standby mode or not -// dmac_runstdby_27 -#ifndef CONF_DMAC_RUNSTDBY_27 -#define CONF_DMAC_RUNSTDBY_27 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_27 -#ifndef CONF_DMAC_TRIGACT_27 -#define CONF_DMAC_TRIGACT_27 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_27 -#ifndef CONF_DMAC_TRIGSRC_27 -#define CONF_DMAC_TRIGSRC_27 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_27 -#ifndef CONF_DMAC_LVL_27 -#define CONF_DMAC_LVL_27 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_27 -#ifndef CONF_DMAC_EVOE_27 -#define CONF_DMAC_EVOE_27 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_27 -#ifndef CONF_DMAC_EVIE_27 -#define CONF_DMAC_EVIE_27 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_27 -#ifndef CONF_DMAC_EVACT_27 -#define CONF_DMAC_EVACT_27 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_27 -#ifndef CONF_DMAC_STEPSIZE_27 -#define CONF_DMAC_STEPSIZE_27 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_27 -#ifndef CONF_DMAC_STEPSEL_27 -#define CONF_DMAC_STEPSEL_27 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_27 -#ifndef CONF_DMAC_SRCINC_27 -#define CONF_DMAC_SRCINC_27 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_27 -#ifndef CONF_DMAC_DSTINC_27 -#define CONF_DMAC_DSTINC_27 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_27 -#ifndef CONF_DMAC_BEATSIZE_27 -#define CONF_DMAC_BEATSIZE_27 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_27 -#ifndef CONF_DMAC_BLOCKACT_27 -#define CONF_DMAC_BLOCKACT_27 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_27 -#ifndef CONF_DMAC_EVOSEL_27 -#define CONF_DMAC_EVOSEL_27 0 -#endif -// - -// Channel 28 settings -// dmac_channel_28_settings -#ifndef CONF_DMAC_CHANNEL_28_SETTINGS -#define CONF_DMAC_CHANNEL_28_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 28 is running in standby mode or not -// dmac_runstdby_28 -#ifndef CONF_DMAC_RUNSTDBY_28 -#define CONF_DMAC_RUNSTDBY_28 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_28 -#ifndef CONF_DMAC_TRIGACT_28 -#define CONF_DMAC_TRIGACT_28 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_28 -#ifndef CONF_DMAC_TRIGSRC_28 -#define CONF_DMAC_TRIGSRC_28 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_28 -#ifndef CONF_DMAC_LVL_28 -#define CONF_DMAC_LVL_28 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_28 -#ifndef CONF_DMAC_EVOE_28 -#define CONF_DMAC_EVOE_28 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_28 -#ifndef CONF_DMAC_EVIE_28 -#define CONF_DMAC_EVIE_28 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_28 -#ifndef CONF_DMAC_EVACT_28 -#define CONF_DMAC_EVACT_28 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_28 -#ifndef CONF_DMAC_STEPSIZE_28 -#define CONF_DMAC_STEPSIZE_28 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_28 -#ifndef CONF_DMAC_STEPSEL_28 -#define CONF_DMAC_STEPSEL_28 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_28 -#ifndef CONF_DMAC_SRCINC_28 -#define CONF_DMAC_SRCINC_28 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_28 -#ifndef CONF_DMAC_DSTINC_28 -#define CONF_DMAC_DSTINC_28 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_28 -#ifndef CONF_DMAC_BEATSIZE_28 -#define CONF_DMAC_BEATSIZE_28 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_28 -#ifndef CONF_DMAC_BLOCKACT_28 -#define CONF_DMAC_BLOCKACT_28 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_28 -#ifndef CONF_DMAC_EVOSEL_28 -#define CONF_DMAC_EVOSEL_28 0 -#endif -// - -// Channel 29 settings -// dmac_channel_29_settings -#ifndef CONF_DMAC_CHANNEL_29_SETTINGS -#define CONF_DMAC_CHANNEL_29_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 29 is running in standby mode or not -// dmac_runstdby_29 -#ifndef CONF_DMAC_RUNSTDBY_29 -#define CONF_DMAC_RUNSTDBY_29 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_29 -#ifndef CONF_DMAC_TRIGACT_29 -#define CONF_DMAC_TRIGACT_29 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_29 -#ifndef CONF_DMAC_TRIGSRC_29 -#define CONF_DMAC_TRIGSRC_29 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_29 -#ifndef CONF_DMAC_LVL_29 -#define CONF_DMAC_LVL_29 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_29 -#ifndef CONF_DMAC_EVOE_29 -#define CONF_DMAC_EVOE_29 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_29 -#ifndef CONF_DMAC_EVIE_29 -#define CONF_DMAC_EVIE_29 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_29 -#ifndef CONF_DMAC_EVACT_29 -#define CONF_DMAC_EVACT_29 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_29 -#ifndef CONF_DMAC_STEPSIZE_29 -#define CONF_DMAC_STEPSIZE_29 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_29 -#ifndef CONF_DMAC_STEPSEL_29 -#define CONF_DMAC_STEPSEL_29 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_29 -#ifndef CONF_DMAC_SRCINC_29 -#define CONF_DMAC_SRCINC_29 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_29 -#ifndef CONF_DMAC_DSTINC_29 -#define CONF_DMAC_DSTINC_29 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_29 -#ifndef CONF_DMAC_BEATSIZE_29 -#define CONF_DMAC_BEATSIZE_29 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_29 -#ifndef CONF_DMAC_BLOCKACT_29 -#define CONF_DMAC_BLOCKACT_29 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_29 -#ifndef CONF_DMAC_EVOSEL_29 -#define CONF_DMAC_EVOSEL_29 0 -#endif -// - -// Channel 30 settings -// dmac_channel_30_settings -#ifndef CONF_DMAC_CHANNEL_30_SETTINGS -#define CONF_DMAC_CHANNEL_30_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 30 is running in standby mode or not -// dmac_runstdby_30 -#ifndef CONF_DMAC_RUNSTDBY_30 -#define CONF_DMAC_RUNSTDBY_30 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_30 -#ifndef CONF_DMAC_TRIGACT_30 -#define CONF_DMAC_TRIGACT_30 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_30 -#ifndef CONF_DMAC_TRIGSRC_30 -#define CONF_DMAC_TRIGSRC_30 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_30 -#ifndef CONF_DMAC_LVL_30 -#define CONF_DMAC_LVL_30 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_30 -#ifndef CONF_DMAC_EVOE_30 -#define CONF_DMAC_EVOE_30 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_30 -#ifndef CONF_DMAC_EVIE_30 -#define CONF_DMAC_EVIE_30 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_30 -#ifndef CONF_DMAC_EVACT_30 -#define CONF_DMAC_EVACT_30 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_30 -#ifndef CONF_DMAC_STEPSIZE_30 -#define CONF_DMAC_STEPSIZE_30 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_30 -#ifndef CONF_DMAC_STEPSEL_30 -#define CONF_DMAC_STEPSEL_30 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_30 -#ifndef CONF_DMAC_SRCINC_30 -#define CONF_DMAC_SRCINC_30 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_30 -#ifndef CONF_DMAC_DSTINC_30 -#define CONF_DMAC_DSTINC_30 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_30 -#ifndef CONF_DMAC_BEATSIZE_30 -#define CONF_DMAC_BEATSIZE_30 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_30 -#ifndef CONF_DMAC_BLOCKACT_30 -#define CONF_DMAC_BLOCKACT_30 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_30 -#ifndef CONF_DMAC_EVOSEL_30 -#define CONF_DMAC_EVOSEL_30 0 -#endif -// - -// Channel 31 settings -// dmac_channel_31_settings -#ifndef CONF_DMAC_CHANNEL_31_SETTINGS -#define CONF_DMAC_CHANNEL_31_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 31 is running in standby mode or not -// dmac_runstdby_31 -#ifndef CONF_DMAC_RUNSTDBY_31 -#define CONF_DMAC_RUNSTDBY_31 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_31 -#ifndef CONF_DMAC_TRIGACT_31 -#define CONF_DMAC_TRIGACT_31 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_31 -#ifndef CONF_DMAC_TRIGSRC_31 -#define CONF_DMAC_TRIGSRC_31 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_31 -#ifndef CONF_DMAC_LVL_31 -#define CONF_DMAC_LVL_31 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_31 -#ifndef CONF_DMAC_EVOE_31 -#define CONF_DMAC_EVOE_31 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_31 -#ifndef CONF_DMAC_EVIE_31 -#define CONF_DMAC_EVIE_31 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_31 -#ifndef CONF_DMAC_EVACT_31 -#define CONF_DMAC_EVACT_31 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_31 -#ifndef CONF_DMAC_STEPSIZE_31 -#define CONF_DMAC_STEPSIZE_31 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_31 -#ifndef CONF_DMAC_STEPSEL_31 -#define CONF_DMAC_STEPSEL_31 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_31 -#ifndef CONF_DMAC_SRCINC_31 -#define CONF_DMAC_SRCINC_31 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_31 -#ifndef CONF_DMAC_DSTINC_31 -#define CONF_DMAC_DSTINC_31 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_31 -#ifndef CONF_DMAC_BEATSIZE_31 -#define CONF_DMAC_BEATSIZE_31 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_31 -#ifndef CONF_DMAC_BLOCKACT_31 -#define CONF_DMAC_BLOCKACT_31 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_31 -#ifndef CONF_DMAC_EVOSEL_31 -#define CONF_DMAC_EVOSEL_31 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_DMAC_CONFIG_H +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_eic_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_eic_config.h index 12946df..eea11e3 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_eic_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_eic_config.h @@ -1,911 +1,911 @@ -/* Auto-generated config file hpl_eic_config.h */ -#ifndef HPL_EIC_CONFIG_H -#define HPL_EIC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Settings -// Clock Selection -// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or -// either by CLK_ULP32K when power consumption is the priority. -// <0x0=> Clocked by GCLK -// <0x1=> Clocked by ULPOSC32K -// eic_arch_cksel -#ifndef CONF_EIC_CKSEL -#define CONF_EIC_CKSEL 0 -#endif - -// Pin Sampler frequency selection -// Indicates the sampling rate of the EXTINT pin. -// <0x0=> The sampling rate is EIC clock -// <0x1=> The sampling rate is the prescaled clock -// eic_arch_tickon -#ifndef CONF_EIC_TICKON -#define CONF_EIC_TICKON 0 -#endif - -// - -// Non-Maskable Interrupt Control -// eic_arch_nmi_ctrl -#ifndef CONF_EIC_ENABLE_NMI_CTRL -#define CONF_EIC_ENABLE_NMI_CTRL 0 -#endif - -// Non-Maskable Interrupt Filter Enable -// Indicates whether the mon-maskable interrupt filter is enabled or not -// eic_arch_nmifilten -#ifndef CONF_EIC_NMIFILTEN -#define CONF_EIC_NMIFILTEN 0 -#endif - -// Non-Maskable Interrupt Sense -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines non-maskable interrupt sense -// eic_arch_nmisense -#ifndef CONF_EIC_NMISENSE -#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// Asynchronous Edge Detection Mode -// Indicates the interrupt detection mode operated synchronously or asynchronousl -// eic_arch_nmiasynch -#ifndef CONF_EIC_NMIASYNCH -#define CONF_EIC_NMIASYNCH 0 -#endif -// - -// Interrupt 0 Settings -// eic_arch_enable_irq_setting0 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING0 -#define CONF_EIC_ENABLE_IRQ_SETTING0 0 -#endif - -// External Interrupt 0 Filter Enable -// Indicates whether the external interrupt 0 filter is enabled or not -// eic_arch_filten0 -#ifndef CONF_EIC_FILTEN0 -#define CONF_EIC_FILTEN0 0 -#endif - -// External Interrupt 0 Debounce Enable -// Indicates whether the external interrupt 0 debounce is enabled or not -// eic_arch_debounce_enable0 -#ifndef CONF_EIC_DEBOUNCE_ENABLE0 -#define CONF_EIC_DEBOUNCE_ENABLE0 0 -#endif - -// External Interrupt 0 Event Output Enable -// Indicates whether the external interrupt 0 event output is enabled or not -// eic_arch_extinteo0 -#ifndef CONF_EIC_EXTINTEO0 -#define CONF_EIC_EXTINTEO0 0 -#endif - -// Input 0 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense0 -#ifndef CONF_EIC_SENSE0 -#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 0 Asynchronous Edge Detection Mode -// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl -// eic_arch_asynch0 -#ifndef CONF_EIC_ASYNCH0 -#define CONF_EIC_ASYNCH0 0 -#endif - -// - -// Interrupt 1 Settings -// eic_arch_enable_irq_setting1 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING1 -#define CONF_EIC_ENABLE_IRQ_SETTING1 0 -#endif - -// External Interrupt 1 Filter Enable -// Indicates whether the external interrupt 1 filter is enabled or not -// eic_arch_filten1 -#ifndef CONF_EIC_FILTEN1 -#define CONF_EIC_FILTEN1 0 -#endif - -// External Interrupt 1 Debounce Enable -// Indicates whether the external interrupt 1 debounce is enabled or not -// eic_arch_debounce_enable1 -#ifndef CONF_EIC_DEBOUNCE_ENABLE1 -#define CONF_EIC_DEBOUNCE_ENABLE1 0 -#endif - -// External Interrupt 1 Event Output Enable -// Indicates whether the external interrupt 1 event output is enabled or not -// eic_arch_extinteo1 -#ifndef CONF_EIC_EXTINTEO1 -#define CONF_EIC_EXTINTEO1 0 -#endif - -// Input 1 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense1 -#ifndef CONF_EIC_SENSE1 -#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 1 Asynchronous Edge Detection Mode -// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl -// eic_arch_asynch1 -#ifndef CONF_EIC_ASYNCH1 -#define CONF_EIC_ASYNCH1 0 -#endif - -// - -// Interrupt 2 Settings -// eic_arch_enable_irq_setting2 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING2 -#define CONF_EIC_ENABLE_IRQ_SETTING2 0 -#endif - -// External Interrupt 2 Filter Enable -// Indicates whether the external interrupt 2 filter is enabled or not -// eic_arch_filten2 -#ifndef CONF_EIC_FILTEN2 -#define CONF_EIC_FILTEN2 0 -#endif - -// External Interrupt 2 Debounce Enable -// Indicates whether the external interrupt 2 debounce is enabled or not -// eic_arch_debounce_enable2 -#ifndef CONF_EIC_DEBOUNCE_ENABLE2 -#define CONF_EIC_DEBOUNCE_ENABLE2 0 -#endif - -// External Interrupt 2 Event Output Enable -// Indicates whether the external interrupt 2 event output is enabled or not -// eic_arch_extinteo2 -#ifndef CONF_EIC_EXTINTEO2 -#define CONF_EIC_EXTINTEO2 0 -#endif - -// Input 2 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense2 -#ifndef CONF_EIC_SENSE2 -#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 2 Asynchronous Edge Detection Mode -// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl -// eic_arch_asynch2 -#ifndef CONF_EIC_ASYNCH2 -#define CONF_EIC_ASYNCH2 0 -#endif - -// - -// Interrupt 3 Settings -// eic_arch_enable_irq_setting3 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING3 -#define CONF_EIC_ENABLE_IRQ_SETTING3 0 -#endif - -// External Interrupt 3 Filter Enable -// Indicates whether the external interrupt 3 filter is enabled or not -// eic_arch_filten3 -#ifndef CONF_EIC_FILTEN3 -#define CONF_EIC_FILTEN3 0 -#endif - -// External Interrupt 3 Debounce Enable -// Indicates whether the external interrupt 3 debounce is enabled or not -// eic_arch_debounce_enable3 -#ifndef CONF_EIC_DEBOUNCE_ENABLE3 -#define CONF_EIC_DEBOUNCE_ENABLE3 0 -#endif - -// External Interrupt 3 Event Output Enable -// Indicates whether the external interrupt 3 event output is enabled or not -// eic_arch_extinteo3 -#ifndef CONF_EIC_EXTINTEO3 -#define CONF_EIC_EXTINTEO3 0 -#endif - -// Input 3 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense3 -#ifndef CONF_EIC_SENSE3 -#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 3 Asynchronous Edge Detection Mode -// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl -// eic_arch_asynch3 -#ifndef CONF_EIC_ASYNCH3 -#define CONF_EIC_ASYNCH3 0 -#endif - -// - -// Interrupt 4 Settings -// eic_arch_enable_irq_setting4 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING4 -#define CONF_EIC_ENABLE_IRQ_SETTING4 0 -#endif - -// External Interrupt 4 Filter Enable -// Indicates whether the external interrupt 4 filter is enabled or not -// eic_arch_filten4 -#ifndef CONF_EIC_FILTEN4 -#define CONF_EIC_FILTEN4 0 -#endif - -// External Interrupt 4 Debounce Enable -// Indicates whether the external interrupt 4 debounce is enabled or not -// eic_arch_debounce_enable4 -#ifndef CONF_EIC_DEBOUNCE_ENABLE4 -#define CONF_EIC_DEBOUNCE_ENABLE4 0 -#endif - -// External Interrupt 4 Event Output Enable -// Indicates whether the external interrupt 4 event output is enabled or not -// eic_arch_extinteo4 -#ifndef CONF_EIC_EXTINTEO4 -#define CONF_EIC_EXTINTEO4 0 -#endif - -// Input 4 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense4 -#ifndef CONF_EIC_SENSE4 -#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 4 Asynchronous Edge Detection Mode -// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl -// eic_arch_asynch4 -#ifndef CONF_EIC_ASYNCH4 -#define CONF_EIC_ASYNCH4 0 -#endif - -// - -// Interrupt 5 Settings -// eic_arch_enable_irq_setting5 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING5 -#define CONF_EIC_ENABLE_IRQ_SETTING5 0 -#endif - -// External Interrupt 5 Filter Enable -// Indicates whether the external interrupt 5 filter is enabled or not -// eic_arch_filten5 -#ifndef CONF_EIC_FILTEN5 -#define CONF_EIC_FILTEN5 0 -#endif - -// External Interrupt 5 Debounce Enable -// Indicates whether the external interrupt 5 debounce is enabled or not -// eic_arch_debounce_enable5 -#ifndef CONF_EIC_DEBOUNCE_ENABLE5 -#define CONF_EIC_DEBOUNCE_ENABLE5 0 -#endif - -// External Interrupt 5 Event Output Enable -// Indicates whether the external interrupt 5 event output is enabled or not -// eic_arch_extinteo5 -#ifndef CONF_EIC_EXTINTEO5 -#define CONF_EIC_EXTINTEO5 0 -#endif - -// Input 5 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense5 -#ifndef CONF_EIC_SENSE5 -#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 5 Asynchronous Edge Detection Mode -// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl -// eic_arch_asynch5 -#ifndef CONF_EIC_ASYNCH5 -#define CONF_EIC_ASYNCH5 0 -#endif - -// - -// Interrupt 6 Settings -// eic_arch_enable_irq_setting6 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING6 -#define CONF_EIC_ENABLE_IRQ_SETTING6 0 -#endif - -// External Interrupt 6 Filter Enable -// Indicates whether the external interrupt 6 filter is enabled or not -// eic_arch_filten6 -#ifndef CONF_EIC_FILTEN6 -#define CONF_EIC_FILTEN6 0 -#endif - -// External Interrupt 6 Debounce Enable -// Indicates whether the external interrupt 6 debounce is enabled or not -// eic_arch_debounce_enable6 -#ifndef CONF_EIC_DEBOUNCE_ENABLE6 -#define CONF_EIC_DEBOUNCE_ENABLE6 0 -#endif - -// External Interrupt 6 Event Output Enable -// Indicates whether the external interrupt 6 event output is enabled or not -// eic_arch_extinteo6 -#ifndef CONF_EIC_EXTINTEO6 -#define CONF_EIC_EXTINTEO6 0 -#endif - -// Input 6 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense6 -#ifndef CONF_EIC_SENSE6 -#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 6 Asynchronous Edge Detection Mode -// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl -// eic_arch_asynch6 -#ifndef CONF_EIC_ASYNCH6 -#define CONF_EIC_ASYNCH6 0 -#endif - -// - -// Interrupt 7 Settings -// eic_arch_enable_irq_setting7 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING7 -#define CONF_EIC_ENABLE_IRQ_SETTING7 0 -#endif - -// External Interrupt 7 Filter Enable -// Indicates whether the external interrupt 7 filter is enabled or not -// eic_arch_filten7 -#ifndef CONF_EIC_FILTEN7 -#define CONF_EIC_FILTEN7 0 -#endif - -// External Interrupt 7 Debounce Enable -// Indicates whether the external interrupt 7 debounce is enabled or not -// eic_arch_debounce_enable7 -#ifndef CONF_EIC_DEBOUNCE_ENABLE7 -#define CONF_EIC_DEBOUNCE_ENABLE7 0 -#endif - -// External Interrupt 7 Event Output Enable -// Indicates whether the external interrupt 7 event output is enabled or not -// eic_arch_extinteo7 -#ifndef CONF_EIC_EXTINTEO7 -#define CONF_EIC_EXTINTEO7 0 -#endif - -// Input 7 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense7 -#ifndef CONF_EIC_SENSE7 -#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 7 Asynchronous Edge Detection Mode -// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl -// eic_arch_asynch7 -#ifndef CONF_EIC_ASYNCH7 -#define CONF_EIC_ASYNCH7 0 -#endif - -// - -// Interrupt 8 Settings -// eic_arch_enable_irq_setting8 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING8 -#define CONF_EIC_ENABLE_IRQ_SETTING8 0 -#endif - -// External Interrupt 8 Filter Enable -// Indicates whether the external interrupt 8 filter is enabled or not -// eic_arch_filten8 -#ifndef CONF_EIC_FILTEN8 -#define CONF_EIC_FILTEN8 0 -#endif - -// External Interrupt 8 Debounce Enable -// Indicates whether the external interrupt 8 debounce is enabled or not -// eic_arch_debounce_enable8 -#ifndef CONF_EIC_DEBOUNCE_ENABLE8 -#define CONF_EIC_DEBOUNCE_ENABLE8 0 -#endif - -// External Interrupt 8 Event Output Enable -// Indicates whether the external interrupt 8 event output is enabled or not -// eic_arch_extinteo8 -#ifndef CONF_EIC_EXTINTEO8 -#define CONF_EIC_EXTINTEO8 0 -#endif - -// Input 8 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense8 -#ifndef CONF_EIC_SENSE8 -#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 8 Asynchronous Edge Detection Mode -// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl -// eic_arch_asynch8 -#ifndef CONF_EIC_ASYNCH8 -#define CONF_EIC_ASYNCH8 0 -#endif - -// - -// Interrupt 9 Settings -// eic_arch_enable_irq_setting9 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING9 -#define CONF_EIC_ENABLE_IRQ_SETTING9 0 -#endif - -// External Interrupt 9 Filter Enable -// Indicates whether the external interrupt 9 filter is enabled or not -// eic_arch_filten9 -#ifndef CONF_EIC_FILTEN9 -#define CONF_EIC_FILTEN9 0 -#endif - -// External Interrupt 9 Debounce Enable -// Indicates whether the external interrupt 9 debounce is enabled or not -// eic_arch_debounce_enable9 -#ifndef CONF_EIC_DEBOUNCE_ENABLE9 -#define CONF_EIC_DEBOUNCE_ENABLE9 0 -#endif - -// External Interrupt 9 Event Output Enable -// Indicates whether the external interrupt 9 event output is enabled or not -// eic_arch_extinteo9 -#ifndef CONF_EIC_EXTINTEO9 -#define CONF_EIC_EXTINTEO9 0 -#endif - -// Input 9 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense9 -#ifndef CONF_EIC_SENSE9 -#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 9 Asynchronous Edge Detection Mode -// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl -// eic_arch_asynch9 -#ifndef CONF_EIC_ASYNCH9 -#define CONF_EIC_ASYNCH9 0 -#endif - -// - -// Interrupt 10 Settings -// eic_arch_enable_irq_setting10 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING10 -#define CONF_EIC_ENABLE_IRQ_SETTING10 0 -#endif - -// External Interrupt 10 Filter Enable -// Indicates whether the external interrupt 10 filter is enabled or not -// eic_arch_filten10 -#ifndef CONF_EIC_FILTEN10 -#define CONF_EIC_FILTEN10 0 -#endif - -// External Interrupt 10 Debounce Enable -// Indicates whether the external interrupt 10 debounce is enabled or not -// eic_arch_debounce_enable10 -#ifndef CONF_EIC_DEBOUNCE_ENABLE10 -#define CONF_EIC_DEBOUNCE_ENABLE10 0 -#endif - -// External Interrupt 10 Event Output Enable -// Indicates whether the external interrupt 10 event output is enabled or not -// eic_arch_extinteo10 -#ifndef CONF_EIC_EXTINTEO10 -#define CONF_EIC_EXTINTEO10 0 -#endif - -// Input 10 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense10 -#ifndef CONF_EIC_SENSE10 -#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 10 Asynchronous Edge Detection Mode -// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl -// eic_arch_asynch10 -#ifndef CONF_EIC_ASYNCH10 -#define CONF_EIC_ASYNCH10 0 -#endif - -// - -// Interrupt 11 Settings -// eic_arch_enable_irq_setting11 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING11 -#define CONF_EIC_ENABLE_IRQ_SETTING11 0 -#endif - -// External Interrupt 11 Filter Enable -// Indicates whether the external interrupt 11 filter is enabled or not -// eic_arch_filten11 -#ifndef CONF_EIC_FILTEN11 -#define CONF_EIC_FILTEN11 0 -#endif - -// External Interrupt 11 Debounce Enable -// Indicates whether the external interrupt 11 debounce is enabled or not -// eic_arch_debounce_enable11 -#ifndef CONF_EIC_DEBOUNCE_ENABLE11 -#define CONF_EIC_DEBOUNCE_ENABLE11 0 -#endif - -// External Interrupt 11 Event Output Enable -// Indicates whether the external interrupt 11 event output is enabled or not -// eic_arch_extinteo11 -#ifndef CONF_EIC_EXTINTEO11 -#define CONF_EIC_EXTINTEO11 0 -#endif - -// Input 11 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense11 -#ifndef CONF_EIC_SENSE11 -#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 11 Asynchronous Edge Detection Mode -// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl -// eic_arch_asynch11 -#ifndef CONF_EIC_ASYNCH11 -#define CONF_EIC_ASYNCH11 0 -#endif - -// - -// Interrupt 12 Settings -// eic_arch_enable_irq_setting12 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING12 -#define CONF_EIC_ENABLE_IRQ_SETTING12 0 -#endif - -// External Interrupt 12 Filter Enable -// Indicates whether the external interrupt 12 filter is enabled or not -// eic_arch_filten12 -#ifndef CONF_EIC_FILTEN12 -#define CONF_EIC_FILTEN12 0 -#endif - -// External Interrupt 12 Debounce Enable -// Indicates whether the external interrupt 12 debounce is enabled or not -// eic_arch_debounce_enable12 -#ifndef CONF_EIC_DEBOUNCE_ENABLE12 -#define CONF_EIC_DEBOUNCE_ENABLE12 0 -#endif - -// External Interrupt 12 Event Output Enable -// Indicates whether the external interrupt 12 event output is enabled or not -// eic_arch_extinteo12 -#ifndef CONF_EIC_EXTINTEO12 -#define CONF_EIC_EXTINTEO12 0 -#endif - -// Input 12 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense12 -#ifndef CONF_EIC_SENSE12 -#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 12 Asynchronous Edge Detection Mode -// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl -// eic_arch_asynch12 -#ifndef CONF_EIC_ASYNCH12 -#define CONF_EIC_ASYNCH12 0 -#endif - -// - -// Interrupt 13 Settings -// eic_arch_enable_irq_setting13 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING13 -#define CONF_EIC_ENABLE_IRQ_SETTING13 0 -#endif - -// External Interrupt 13 Filter Enable -// Indicates whether the external interrupt 13 filter is enabled or not -// eic_arch_filten13 -#ifndef CONF_EIC_FILTEN13 -#define CONF_EIC_FILTEN13 0 -#endif - -// External Interrupt 13 Debounce Enable -// Indicates whether the external interrupt 13 debounce is enabled or not -// eic_arch_debounce_enable13 -#ifndef CONF_EIC_DEBOUNCE_ENABLE13 -#define CONF_EIC_DEBOUNCE_ENABLE13 0 -#endif - -// External Interrupt 13 Event Output Enable -// Indicates whether the external interrupt 13 event output is enabled or not -// eic_arch_extinteo13 -#ifndef CONF_EIC_EXTINTEO13 -#define CONF_EIC_EXTINTEO13 0 -#endif - -// Input 13 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense13 -#ifndef CONF_EIC_SENSE13 -#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 13 Asynchronous Edge Detection Mode -// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl -// eic_arch_asynch13 -#ifndef CONF_EIC_ASYNCH13 -#define CONF_EIC_ASYNCH13 0 -#endif - -// - -// Interrupt 14 Settings -// eic_arch_enable_irq_setting14 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING14 -#define CONF_EIC_ENABLE_IRQ_SETTING14 0 -#endif - -// External Interrupt 14 Filter Enable -// Indicates whether the external interrupt 14 filter is enabled or not -// eic_arch_filten14 -#ifndef CONF_EIC_FILTEN14 -#define CONF_EIC_FILTEN14 0 -#endif - -// External Interrupt 14 Debounce Enable -// Indicates whether the external interrupt 14 debounce is enabled or not -// eic_arch_debounce_enable14 -#ifndef CONF_EIC_DEBOUNCE_ENABLE14 -#define CONF_EIC_DEBOUNCE_ENABLE14 0 -#endif - -// External Interrupt 14 Event Output Enable -// Indicates whether the external interrupt 14 event output is enabled or not -// eic_arch_extinteo14 -#ifndef CONF_EIC_EXTINTEO14 -#define CONF_EIC_EXTINTEO14 0 -#endif - -// Input 14 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense14 -#ifndef CONF_EIC_SENSE14 -#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 14 Asynchronous Edge Detection Mode -// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl -// eic_arch_asynch14 -#ifndef CONF_EIC_ASYNCH14 -#define CONF_EIC_ASYNCH14 0 -#endif - -// - -// Interrupt 15 Settings -// eic_arch_enable_irq_setting15 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING15 -#define CONF_EIC_ENABLE_IRQ_SETTING15 0 -#endif - -// External Interrupt 15 Filter Enable -// Indicates whether the external interrupt 15 filter is enabled or not -// eic_arch_filten15 -#ifndef CONF_EIC_FILTEN15 -#define CONF_EIC_FILTEN15 0 -#endif - -// External Interrupt 15 Debounce Enable -// Indicates whether the external interrupt 15 debounce is enabled or not -// eic_arch_debounce_enable15 -#ifndef CONF_EIC_DEBOUNCE_ENABLE15 -#define CONF_EIC_DEBOUNCE_ENABLE15 0 -#endif - -// External Interrupt 15 Event Output Enable -// Indicates whether the external interrupt 15 event output is enabled or not -// eic_arch_extinteo15 -#ifndef CONF_EIC_EXTINTEO15 -#define CONF_EIC_EXTINTEO15 0 -#endif - -// Input 15 Sense Configuration -// No detection -// Rising-edge detection -// Falling-edge detection -// Both-edges detection -// High-level detection -// Low-level detection -// This defines input sense trigger -// eic_arch_sense15 -#ifndef CONF_EIC_SENSE15 -#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// External Interrupt 15 Asynchronous Edge Detection Mode -// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl -// eic_arch_asynch15 -#ifndef CONF_EIC_ASYNCH15 -#define CONF_EIC_ASYNCH15 0 -#endif - -// - -// Debouncer 0 Settings -// Debouncer Frequency Selection -// <0x0=>Divided by 2 -// <0x1=>Divided by 4 -// <0x2=>Divided by 8 -// <0x3=>Divided by 16 -// <0x4=>Divided by 32 -// <0x5=>Divided by 64 -// <0x6=>Divided by 128 -// <0x7=>Divided by 256 -// Select the debouncer low frequency clock for pins - -// EXTINT[7:0]. - -// eic_arch_prescaler0 -#ifndef CONF_EIC_DPRESCALER0 -#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0) -#endif - -// Low frequency samples -// <0x0=>3 -// <0x1=>7 -// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from -// current pin state to next pin state in synchronous debouncing mode. -// eic_arch_states0 -#ifndef CONF_EIC_STATES0 -#define CONF_EIC_STATES0 0x0 -#endif - -// - -// Debouncer 1 Settings -// Debouncer Frequency Selection -// <0x0=>Divided by 2 -// <0x1=>Divided by 4 -// <0x2=>Divided by 8 -// <0x3=>Divided by 16 -// <0x4=>Divided by 32 -// <0x5=>Divided by 64 -// <0x6=>Divided by 128 -// <0x7=>Divided by 256 -// Select the debouncer low frequency clock for pins - -// EXTINT[15:8]. - -// eic_arch_prescaler1 -#ifndef CONF_EIC_DPRESCALER1 -#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0) -#endif - -// Low frequency samples -// <0x0=>3 -// <0x1=>7 -// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from -// current pin state to next pin state in synchronous debouncing mode. -// eic_arch_states1 -#ifndef CONF_EIC_STATES1 -#define CONF_EIC_STATES1 0x0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_EIC_CONFIG_H +/* Auto-generated config file hpl_eic_config.h */ +#ifndef HPL_EIC_CONFIG_H +#define HPL_EIC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings +// Clock Selection +// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or +// either by CLK_ULP32K when power consumption is the priority. +// <0x0=> Clocked by GCLK +// <0x1=> Clocked by ULPOSC32K +// eic_arch_cksel +#ifndef CONF_EIC_CKSEL +#define CONF_EIC_CKSEL 0 +#endif + +// Pin Sampler frequency selection +// Indicates the sampling rate of the EXTINT pin. +// <0x0=> The sampling rate is EIC clock +// <0x1=> The sampling rate is the prescaled clock +// eic_arch_tickon +#ifndef CONF_EIC_TICKON +#define CONF_EIC_TICKON 0 +#endif + +// + +// Non-Maskable Interrupt Control +// eic_arch_nmi_ctrl +#ifndef CONF_EIC_ENABLE_NMI_CTRL +#define CONF_EIC_ENABLE_NMI_CTRL 0 +#endif + +// Non-Maskable Interrupt Filter Enable +// Indicates whether the mon-maskable interrupt filter is enabled or not +// eic_arch_nmifilten +#ifndef CONF_EIC_NMIFILTEN +#define CONF_EIC_NMIFILTEN 0 +#endif + +// Non-Maskable Interrupt Sense +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines non-maskable interrupt sense +// eic_arch_nmisense +#ifndef CONF_EIC_NMISENSE +#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// Asynchronous Edge Detection Mode +// Indicates the interrupt detection mode operated synchronously or asynchronousl +// eic_arch_nmiasynch +#ifndef CONF_EIC_NMIASYNCH +#define CONF_EIC_NMIASYNCH 0 +#endif +// + +// Interrupt 0 Settings +// eic_arch_enable_irq_setting0 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING0 +#define CONF_EIC_ENABLE_IRQ_SETTING0 0 +#endif + +// External Interrupt 0 Filter Enable +// Indicates whether the external interrupt 0 filter is enabled or not +// eic_arch_filten0 +#ifndef CONF_EIC_FILTEN0 +#define CONF_EIC_FILTEN0 0 +#endif + +// External Interrupt 0 Debounce Enable +// Indicates whether the external interrupt 0 debounce is enabled or not +// eic_arch_debounce_enable0 +#ifndef CONF_EIC_DEBOUNCE_ENABLE0 +#define CONF_EIC_DEBOUNCE_ENABLE0 0 +#endif + +// External Interrupt 0 Event Output Enable +// Indicates whether the external interrupt 0 event output is enabled or not +// eic_arch_extinteo0 +#ifndef CONF_EIC_EXTINTEO0 +#define CONF_EIC_EXTINTEO0 0 +#endif + +// Input 0 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense0 +#ifndef CONF_EIC_SENSE0 +#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 0 Asynchronous Edge Detection Mode +// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl +// eic_arch_asynch0 +#ifndef CONF_EIC_ASYNCH0 +#define CONF_EIC_ASYNCH0 0 +#endif + +// + +// Interrupt 1 Settings +// eic_arch_enable_irq_setting1 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING1 +#define CONF_EIC_ENABLE_IRQ_SETTING1 0 +#endif + +// External Interrupt 1 Filter Enable +// Indicates whether the external interrupt 1 filter is enabled or not +// eic_arch_filten1 +#ifndef CONF_EIC_FILTEN1 +#define CONF_EIC_FILTEN1 0 +#endif + +// External Interrupt 1 Debounce Enable +// Indicates whether the external interrupt 1 debounce is enabled or not +// eic_arch_debounce_enable1 +#ifndef CONF_EIC_DEBOUNCE_ENABLE1 +#define CONF_EIC_DEBOUNCE_ENABLE1 0 +#endif + +// External Interrupt 1 Event Output Enable +// Indicates whether the external interrupt 1 event output is enabled or not +// eic_arch_extinteo1 +#ifndef CONF_EIC_EXTINTEO1 +#define CONF_EIC_EXTINTEO1 0 +#endif + +// Input 1 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense1 +#ifndef CONF_EIC_SENSE1 +#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 1 Asynchronous Edge Detection Mode +// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl +// eic_arch_asynch1 +#ifndef CONF_EIC_ASYNCH1 +#define CONF_EIC_ASYNCH1 0 +#endif + +// + +// Interrupt 2 Settings +// eic_arch_enable_irq_setting2 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING2 +#define CONF_EIC_ENABLE_IRQ_SETTING2 0 +#endif + +// External Interrupt 2 Filter Enable +// Indicates whether the external interrupt 2 filter is enabled or not +// eic_arch_filten2 +#ifndef CONF_EIC_FILTEN2 +#define CONF_EIC_FILTEN2 0 +#endif + +// External Interrupt 2 Debounce Enable +// Indicates whether the external interrupt 2 debounce is enabled or not +// eic_arch_debounce_enable2 +#ifndef CONF_EIC_DEBOUNCE_ENABLE2 +#define CONF_EIC_DEBOUNCE_ENABLE2 0 +#endif + +// External Interrupt 2 Event Output Enable +// Indicates whether the external interrupt 2 event output is enabled or not +// eic_arch_extinteo2 +#ifndef CONF_EIC_EXTINTEO2 +#define CONF_EIC_EXTINTEO2 0 +#endif + +// Input 2 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense2 +#ifndef CONF_EIC_SENSE2 +#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 2 Asynchronous Edge Detection Mode +// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl +// eic_arch_asynch2 +#ifndef CONF_EIC_ASYNCH2 +#define CONF_EIC_ASYNCH2 0 +#endif + +// + +// Interrupt 3 Settings +// eic_arch_enable_irq_setting3 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING3 +#define CONF_EIC_ENABLE_IRQ_SETTING3 0 +#endif + +// External Interrupt 3 Filter Enable +// Indicates whether the external interrupt 3 filter is enabled or not +// eic_arch_filten3 +#ifndef CONF_EIC_FILTEN3 +#define CONF_EIC_FILTEN3 0 +#endif + +// External Interrupt 3 Debounce Enable +// Indicates whether the external interrupt 3 debounce is enabled or not +// eic_arch_debounce_enable3 +#ifndef CONF_EIC_DEBOUNCE_ENABLE3 +#define CONF_EIC_DEBOUNCE_ENABLE3 0 +#endif + +// External Interrupt 3 Event Output Enable +// Indicates whether the external interrupt 3 event output is enabled or not +// eic_arch_extinteo3 +#ifndef CONF_EIC_EXTINTEO3 +#define CONF_EIC_EXTINTEO3 0 +#endif + +// Input 3 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense3 +#ifndef CONF_EIC_SENSE3 +#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 3 Asynchronous Edge Detection Mode +// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl +// eic_arch_asynch3 +#ifndef CONF_EIC_ASYNCH3 +#define CONF_EIC_ASYNCH3 0 +#endif + +// + +// Interrupt 4 Settings +// eic_arch_enable_irq_setting4 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING4 +#define CONF_EIC_ENABLE_IRQ_SETTING4 0 +#endif + +// External Interrupt 4 Filter Enable +// Indicates whether the external interrupt 4 filter is enabled or not +// eic_arch_filten4 +#ifndef CONF_EIC_FILTEN4 +#define CONF_EIC_FILTEN4 0 +#endif + +// External Interrupt 4 Debounce Enable +// Indicates whether the external interrupt 4 debounce is enabled or not +// eic_arch_debounce_enable4 +#ifndef CONF_EIC_DEBOUNCE_ENABLE4 +#define CONF_EIC_DEBOUNCE_ENABLE4 0 +#endif + +// External Interrupt 4 Event Output Enable +// Indicates whether the external interrupt 4 event output is enabled or not +// eic_arch_extinteo4 +#ifndef CONF_EIC_EXTINTEO4 +#define CONF_EIC_EXTINTEO4 0 +#endif + +// Input 4 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense4 +#ifndef CONF_EIC_SENSE4 +#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 4 Asynchronous Edge Detection Mode +// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl +// eic_arch_asynch4 +#ifndef CONF_EIC_ASYNCH4 +#define CONF_EIC_ASYNCH4 0 +#endif + +// + +// Interrupt 5 Settings +// eic_arch_enable_irq_setting5 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING5 +#define CONF_EIC_ENABLE_IRQ_SETTING5 0 +#endif + +// External Interrupt 5 Filter Enable +// Indicates whether the external interrupt 5 filter is enabled or not +// eic_arch_filten5 +#ifndef CONF_EIC_FILTEN5 +#define CONF_EIC_FILTEN5 0 +#endif + +// External Interrupt 5 Debounce Enable +// Indicates whether the external interrupt 5 debounce is enabled or not +// eic_arch_debounce_enable5 +#ifndef CONF_EIC_DEBOUNCE_ENABLE5 +#define CONF_EIC_DEBOUNCE_ENABLE5 0 +#endif + +// External Interrupt 5 Event Output Enable +// Indicates whether the external interrupt 5 event output is enabled or not +// eic_arch_extinteo5 +#ifndef CONF_EIC_EXTINTEO5 +#define CONF_EIC_EXTINTEO5 0 +#endif + +// Input 5 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense5 +#ifndef CONF_EIC_SENSE5 +#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 5 Asynchronous Edge Detection Mode +// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl +// eic_arch_asynch5 +#ifndef CONF_EIC_ASYNCH5 +#define CONF_EIC_ASYNCH5 0 +#endif + +// + +// Interrupt 6 Settings +// eic_arch_enable_irq_setting6 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING6 +#define CONF_EIC_ENABLE_IRQ_SETTING6 0 +#endif + +// External Interrupt 6 Filter Enable +// Indicates whether the external interrupt 6 filter is enabled or not +// eic_arch_filten6 +#ifndef CONF_EIC_FILTEN6 +#define CONF_EIC_FILTEN6 0 +#endif + +// External Interrupt 6 Debounce Enable +// Indicates whether the external interrupt 6 debounce is enabled or not +// eic_arch_debounce_enable6 +#ifndef CONF_EIC_DEBOUNCE_ENABLE6 +#define CONF_EIC_DEBOUNCE_ENABLE6 0 +#endif + +// External Interrupt 6 Event Output Enable +// Indicates whether the external interrupt 6 event output is enabled or not +// eic_arch_extinteo6 +#ifndef CONF_EIC_EXTINTEO6 +#define CONF_EIC_EXTINTEO6 0 +#endif + +// Input 6 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense6 +#ifndef CONF_EIC_SENSE6 +#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 6 Asynchronous Edge Detection Mode +// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl +// eic_arch_asynch6 +#ifndef CONF_EIC_ASYNCH6 +#define CONF_EIC_ASYNCH6 0 +#endif + +// + +// Interrupt 7 Settings +// eic_arch_enable_irq_setting7 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING7 +#define CONF_EIC_ENABLE_IRQ_SETTING7 0 +#endif + +// External Interrupt 7 Filter Enable +// Indicates whether the external interrupt 7 filter is enabled or not +// eic_arch_filten7 +#ifndef CONF_EIC_FILTEN7 +#define CONF_EIC_FILTEN7 0 +#endif + +// External Interrupt 7 Debounce Enable +// Indicates whether the external interrupt 7 debounce is enabled or not +// eic_arch_debounce_enable7 +#ifndef CONF_EIC_DEBOUNCE_ENABLE7 +#define CONF_EIC_DEBOUNCE_ENABLE7 0 +#endif + +// External Interrupt 7 Event Output Enable +// Indicates whether the external interrupt 7 event output is enabled or not +// eic_arch_extinteo7 +#ifndef CONF_EIC_EXTINTEO7 +#define CONF_EIC_EXTINTEO7 0 +#endif + +// Input 7 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense7 +#ifndef CONF_EIC_SENSE7 +#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 7 Asynchronous Edge Detection Mode +// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl +// eic_arch_asynch7 +#ifndef CONF_EIC_ASYNCH7 +#define CONF_EIC_ASYNCH7 0 +#endif + +// + +// Interrupt 8 Settings +// eic_arch_enable_irq_setting8 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING8 +#define CONF_EIC_ENABLE_IRQ_SETTING8 0 +#endif + +// External Interrupt 8 Filter Enable +// Indicates whether the external interrupt 8 filter is enabled or not +// eic_arch_filten8 +#ifndef CONF_EIC_FILTEN8 +#define CONF_EIC_FILTEN8 0 +#endif + +// External Interrupt 8 Debounce Enable +// Indicates whether the external interrupt 8 debounce is enabled or not +// eic_arch_debounce_enable8 +#ifndef CONF_EIC_DEBOUNCE_ENABLE8 +#define CONF_EIC_DEBOUNCE_ENABLE8 0 +#endif + +// External Interrupt 8 Event Output Enable +// Indicates whether the external interrupt 8 event output is enabled or not +// eic_arch_extinteo8 +#ifndef CONF_EIC_EXTINTEO8 +#define CONF_EIC_EXTINTEO8 0 +#endif + +// Input 8 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense8 +#ifndef CONF_EIC_SENSE8 +#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 8 Asynchronous Edge Detection Mode +// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl +// eic_arch_asynch8 +#ifndef CONF_EIC_ASYNCH8 +#define CONF_EIC_ASYNCH8 0 +#endif + +// + +// Interrupt 9 Settings +// eic_arch_enable_irq_setting9 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING9 +#define CONF_EIC_ENABLE_IRQ_SETTING9 0 +#endif + +// External Interrupt 9 Filter Enable +// Indicates whether the external interrupt 9 filter is enabled or not +// eic_arch_filten9 +#ifndef CONF_EIC_FILTEN9 +#define CONF_EIC_FILTEN9 0 +#endif + +// External Interrupt 9 Debounce Enable +// Indicates whether the external interrupt 9 debounce is enabled or not +// eic_arch_debounce_enable9 +#ifndef CONF_EIC_DEBOUNCE_ENABLE9 +#define CONF_EIC_DEBOUNCE_ENABLE9 0 +#endif + +// External Interrupt 9 Event Output Enable +// Indicates whether the external interrupt 9 event output is enabled or not +// eic_arch_extinteo9 +#ifndef CONF_EIC_EXTINTEO9 +#define CONF_EIC_EXTINTEO9 0 +#endif + +// Input 9 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense9 +#ifndef CONF_EIC_SENSE9 +#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 9 Asynchronous Edge Detection Mode +// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl +// eic_arch_asynch9 +#ifndef CONF_EIC_ASYNCH9 +#define CONF_EIC_ASYNCH9 0 +#endif + +// + +// Interrupt 10 Settings +// eic_arch_enable_irq_setting10 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING10 +#define CONF_EIC_ENABLE_IRQ_SETTING10 0 +#endif + +// External Interrupt 10 Filter Enable +// Indicates whether the external interrupt 10 filter is enabled or not +// eic_arch_filten10 +#ifndef CONF_EIC_FILTEN10 +#define CONF_EIC_FILTEN10 0 +#endif + +// External Interrupt 10 Debounce Enable +// Indicates whether the external interrupt 10 debounce is enabled or not +// eic_arch_debounce_enable10 +#ifndef CONF_EIC_DEBOUNCE_ENABLE10 +#define CONF_EIC_DEBOUNCE_ENABLE10 0 +#endif + +// External Interrupt 10 Event Output Enable +// Indicates whether the external interrupt 10 event output is enabled or not +// eic_arch_extinteo10 +#ifndef CONF_EIC_EXTINTEO10 +#define CONF_EIC_EXTINTEO10 0 +#endif + +// Input 10 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense10 +#ifndef CONF_EIC_SENSE10 +#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 10 Asynchronous Edge Detection Mode +// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl +// eic_arch_asynch10 +#ifndef CONF_EIC_ASYNCH10 +#define CONF_EIC_ASYNCH10 0 +#endif + +// + +// Interrupt 11 Settings +// eic_arch_enable_irq_setting11 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING11 +#define CONF_EIC_ENABLE_IRQ_SETTING11 0 +#endif + +// External Interrupt 11 Filter Enable +// Indicates whether the external interrupt 11 filter is enabled or not +// eic_arch_filten11 +#ifndef CONF_EIC_FILTEN11 +#define CONF_EIC_FILTEN11 0 +#endif + +// External Interrupt 11 Debounce Enable +// Indicates whether the external interrupt 11 debounce is enabled or not +// eic_arch_debounce_enable11 +#ifndef CONF_EIC_DEBOUNCE_ENABLE11 +#define CONF_EIC_DEBOUNCE_ENABLE11 0 +#endif + +// External Interrupt 11 Event Output Enable +// Indicates whether the external interrupt 11 event output is enabled or not +// eic_arch_extinteo11 +#ifndef CONF_EIC_EXTINTEO11 +#define CONF_EIC_EXTINTEO11 0 +#endif + +// Input 11 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense11 +#ifndef CONF_EIC_SENSE11 +#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 11 Asynchronous Edge Detection Mode +// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl +// eic_arch_asynch11 +#ifndef CONF_EIC_ASYNCH11 +#define CONF_EIC_ASYNCH11 0 +#endif + +// + +// Interrupt 12 Settings +// eic_arch_enable_irq_setting12 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING12 +#define CONF_EIC_ENABLE_IRQ_SETTING12 0 +#endif + +// External Interrupt 12 Filter Enable +// Indicates whether the external interrupt 12 filter is enabled or not +// eic_arch_filten12 +#ifndef CONF_EIC_FILTEN12 +#define CONF_EIC_FILTEN12 0 +#endif + +// External Interrupt 12 Debounce Enable +// Indicates whether the external interrupt 12 debounce is enabled or not +// eic_arch_debounce_enable12 +#ifndef CONF_EIC_DEBOUNCE_ENABLE12 +#define CONF_EIC_DEBOUNCE_ENABLE12 0 +#endif + +// External Interrupt 12 Event Output Enable +// Indicates whether the external interrupt 12 event output is enabled or not +// eic_arch_extinteo12 +#ifndef CONF_EIC_EXTINTEO12 +#define CONF_EIC_EXTINTEO12 0 +#endif + +// Input 12 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense12 +#ifndef CONF_EIC_SENSE12 +#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 12 Asynchronous Edge Detection Mode +// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl +// eic_arch_asynch12 +#ifndef CONF_EIC_ASYNCH12 +#define CONF_EIC_ASYNCH12 0 +#endif + +// + +// Interrupt 13 Settings +// eic_arch_enable_irq_setting13 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING13 +#define CONF_EIC_ENABLE_IRQ_SETTING13 0 +#endif + +// External Interrupt 13 Filter Enable +// Indicates whether the external interrupt 13 filter is enabled or not +// eic_arch_filten13 +#ifndef CONF_EIC_FILTEN13 +#define CONF_EIC_FILTEN13 0 +#endif + +// External Interrupt 13 Debounce Enable +// Indicates whether the external interrupt 13 debounce is enabled or not +// eic_arch_debounce_enable13 +#ifndef CONF_EIC_DEBOUNCE_ENABLE13 +#define CONF_EIC_DEBOUNCE_ENABLE13 0 +#endif + +// External Interrupt 13 Event Output Enable +// Indicates whether the external interrupt 13 event output is enabled or not +// eic_arch_extinteo13 +#ifndef CONF_EIC_EXTINTEO13 +#define CONF_EIC_EXTINTEO13 0 +#endif + +// Input 13 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense13 +#ifndef CONF_EIC_SENSE13 +#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 13 Asynchronous Edge Detection Mode +// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl +// eic_arch_asynch13 +#ifndef CONF_EIC_ASYNCH13 +#define CONF_EIC_ASYNCH13 0 +#endif + +// + +// Interrupt 14 Settings +// eic_arch_enable_irq_setting14 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING14 +#define CONF_EIC_ENABLE_IRQ_SETTING14 0 +#endif + +// External Interrupt 14 Filter Enable +// Indicates whether the external interrupt 14 filter is enabled or not +// eic_arch_filten14 +#ifndef CONF_EIC_FILTEN14 +#define CONF_EIC_FILTEN14 0 +#endif + +// External Interrupt 14 Debounce Enable +// Indicates whether the external interrupt 14 debounce is enabled or not +// eic_arch_debounce_enable14 +#ifndef CONF_EIC_DEBOUNCE_ENABLE14 +#define CONF_EIC_DEBOUNCE_ENABLE14 0 +#endif + +// External Interrupt 14 Event Output Enable +// Indicates whether the external interrupt 14 event output is enabled or not +// eic_arch_extinteo14 +#ifndef CONF_EIC_EXTINTEO14 +#define CONF_EIC_EXTINTEO14 0 +#endif + +// Input 14 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense14 +#ifndef CONF_EIC_SENSE14 +#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 14 Asynchronous Edge Detection Mode +// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl +// eic_arch_asynch14 +#ifndef CONF_EIC_ASYNCH14 +#define CONF_EIC_ASYNCH14 0 +#endif + +// + +// Interrupt 15 Settings +// eic_arch_enable_irq_setting15 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING15 +#define CONF_EIC_ENABLE_IRQ_SETTING15 0 +#endif + +// External Interrupt 15 Filter Enable +// Indicates whether the external interrupt 15 filter is enabled or not +// eic_arch_filten15 +#ifndef CONF_EIC_FILTEN15 +#define CONF_EIC_FILTEN15 0 +#endif + +// External Interrupt 15 Debounce Enable +// Indicates whether the external interrupt 15 debounce is enabled or not +// eic_arch_debounce_enable15 +#ifndef CONF_EIC_DEBOUNCE_ENABLE15 +#define CONF_EIC_DEBOUNCE_ENABLE15 0 +#endif + +// External Interrupt 15 Event Output Enable +// Indicates whether the external interrupt 15 event output is enabled or not +// eic_arch_extinteo15 +#ifndef CONF_EIC_EXTINTEO15 +#define CONF_EIC_EXTINTEO15 0 +#endif + +// Input 15 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense15 +#ifndef CONF_EIC_SENSE15 +#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 15 Asynchronous Edge Detection Mode +// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl +// eic_arch_asynch15 +#ifndef CONF_EIC_ASYNCH15 +#define CONF_EIC_ASYNCH15 0 +#endif + +// + +// Debouncer 0 Settings +// Debouncer Frequency Selection +// <0x0=>Divided by 2 +// <0x1=>Divided by 4 +// <0x2=>Divided by 8 +// <0x3=>Divided by 16 +// <0x4=>Divided by 32 +// <0x5=>Divided by 64 +// <0x6=>Divided by 128 +// <0x7=>Divided by 256 +// Select the debouncer low frequency clock for pins + +// EXTINT[7:0]. + +// eic_arch_prescaler0 +#ifndef CONF_EIC_DPRESCALER0 +#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0) +#endif + +// Low frequency samples +// <0x0=>3 +// <0x1=>7 +// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from +// current pin state to next pin state in synchronous debouncing mode. +// eic_arch_states0 +#ifndef CONF_EIC_STATES0 +#define CONF_EIC_STATES0 0x0 +#endif + +// + +// Debouncer 1 Settings +// Debouncer Frequency Selection +// <0x0=>Divided by 2 +// <0x1=>Divided by 4 +// <0x2=>Divided by 8 +// <0x3=>Divided by 16 +// <0x4=>Divided by 32 +// <0x5=>Divided by 64 +// <0x6=>Divided by 128 +// <0x7=>Divided by 256 +// Select the debouncer low frequency clock for pins + +// EXTINT[15:8]. + +// eic_arch_prescaler1 +#ifndef CONF_EIC_DPRESCALER1 +#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0) +#endif + +// Low frequency samples +// <0x0=>3 +// <0x1=>7 +// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from +// current pin state to next pin state in synchronous debouncing mode. +// eic_arch_states1 +#ifndef CONF_EIC_STATES1 +#define CONF_EIC_STATES1 0x0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_EIC_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_gclk_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_gclk_config.h index fbce118..0a119df 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_gclk_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_gclk_config.h @@ -1,920 +1,920 @@ -/* Auto-generated config file hpl_gclk_config.h */ -#ifndef HPL_GCLK_CONFIG_H -#define HPL_GCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Generic clock generator 0 configuration -// Indicates whether generic clock 0 configuration is enabled or not -// enable_gclk_gen_0 -#ifndef CONF_GCLK_GENERATOR_0_CONFIG -#define CONF_GCLK_GENERATOR_0_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Generic clock generator 0 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 0 -// gclk_gen_0_oscillator -#ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_0_runstdby -#ifndef CONF_GCLK_GEN_0_RUNSTDBY -#define CONF_GCLK_GEN_0_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel -#ifndef CONF_GCLK_GEN_0_DIVSEL -#define CONF_GCLK_GEN_0_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_0_oe -#ifndef CONF_GCLK_GEN_0_OE -#define CONF_GCLK_GEN_0_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_0_oov -#ifndef CONF_GCLK_GEN_0_OOV -#define CONF_GCLK_GEN_0_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_0_idc -#ifndef CONF_GCLK_GEN_0_IDC -#define CONF_GCLK_GEN_0_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_0_enable -#ifndef CONF_GCLK_GEN_0_GENEN -#define CONF_GCLK_GEN_0_GENEN 1 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> -// gclk_gen_0_div -#ifndef CONF_GCLK_GEN_0_DIV -#define CONF_GCLK_GEN_0_DIV 1 -#endif -// -// - -// Generic clock generator 1 configuration -// Indicates whether generic clock 1 configuration is enabled or not -// enable_gclk_gen_1 -#ifndef CONF_GCLK_GENERATOR_1_CONFIG -#define CONF_GCLK_GENERATOR_1_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 1 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 1 -// gclk_gen_1_oscillator -#ifndef CONF_GCLK_GEN_1_SOURCE -#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_1_runstdby -#ifndef CONF_GCLK_GEN_1_RUNSTDBY -#define CONF_GCLK_GEN_1_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel -#ifndef CONF_GCLK_GEN_1_DIVSEL -#define CONF_GCLK_GEN_1_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_1_oe -#ifndef CONF_GCLK_GEN_1_OE -#define CONF_GCLK_GEN_1_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_1_oov -#ifndef CONF_GCLK_GEN_1_OOV -#define CONF_GCLK_GEN_1_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_1_idc -#ifndef CONF_GCLK_GEN_1_IDC -#define CONF_GCLK_GEN_1_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_1_enable -#ifndef CONF_GCLK_GEN_1_GENEN -#define CONF_GCLK_GEN_1_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> -// gclk_gen_1_div -#ifndef CONF_GCLK_GEN_1_DIV -#define CONF_GCLK_GEN_1_DIV 1 -#endif -// -// - -// Generic clock generator 2 configuration -// Indicates whether generic clock 2 configuration is enabled or not -// enable_gclk_gen_2 -#ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 2 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 2 -// gclk_gen_2_oscillator -#ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_2_runstdby -#ifndef CONF_GCLK_GEN_2_RUNSTDBY -#define CONF_GCLK_GEN_2_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel -#ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 1 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_2_oe -#ifndef CONF_GCLK_GEN_2_OE -#define CONF_GCLK_GEN_2_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_2_oov -#ifndef CONF_GCLK_GEN_2_OOV -#define CONF_GCLK_GEN_2_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_2_idc -#ifndef CONF_GCLK_GEN_2_IDC -#define CONF_GCLK_GEN_2_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_2_enable -#ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> -// gclk_gen_2_div -#ifndef CONF_GCLK_GEN_2_DIV -#define CONF_GCLK_GEN_2_DIV 1 -#endif -// -// - -// Generic clock generator 3 configuration -// Indicates whether generic clock 3 configuration is enabled or not -// enable_gclk_gen_3 -#ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 3 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 3 -// gclk_gen_3_oscillator -#ifndef CONF_GCLK_GEN_3_SOURCE -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_3_runstdby -#ifndef CONF_GCLK_GEN_3_RUNSTDBY -#define CONF_GCLK_GEN_3_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel -#ifndef CONF_GCLK_GEN_3_DIVSEL -#define CONF_GCLK_GEN_3_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_3_oe -#ifndef CONF_GCLK_GEN_3_OE -#define CONF_GCLK_GEN_3_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_3_oov -#ifndef CONF_GCLK_GEN_3_OOV -#define CONF_GCLK_GEN_3_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_3_idc -#ifndef CONF_GCLK_GEN_3_IDC -#define CONF_GCLK_GEN_3_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_3_enable -#ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> -// gclk_gen_3_div -#ifndef CONF_GCLK_GEN_3_DIV -#define CONF_GCLK_GEN_3_DIV 1 -#endif -// -// - -// Generic clock generator 4 configuration -// Indicates whether generic clock 4 configuration is enabled or not -// enable_gclk_gen_4 -#ifndef CONF_GCLK_GENERATOR_4_CONFIG -#define CONF_GCLK_GENERATOR_4_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 4 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 4 -// gclk_gen_4_oscillator -#ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_4_runstdby -#ifndef CONF_GCLK_GEN_4_RUNSTDBY -#define CONF_GCLK_GEN_4_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel -#ifndef CONF_GCLK_GEN_4_DIVSEL -#define CONF_GCLK_GEN_4_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_4_oe -#ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_4_oov -#ifndef CONF_GCLK_GEN_4_OOV -#define CONF_GCLK_GEN_4_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_4_idc -#ifndef CONF_GCLK_GEN_4_IDC -#define CONF_GCLK_GEN_4_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_4_enable -#ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> -// gclk_gen_4_div -#ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 -#endif -// -// - -// Generic clock generator 5 configuration -// Indicates whether generic clock 5 configuration is enabled or not -// enable_gclk_gen_5 -#ifndef CONF_GCLK_GENERATOR_5_CONFIG -#define CONF_GCLK_GENERATOR_5_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 5 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 5 -// gclk_gen_5_oscillator -#ifndef CONF_GCLK_GEN_5_SOURCE -#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_5_runstdby -#ifndef CONF_GCLK_GEN_5_RUNSTDBY -#define CONF_GCLK_GEN_5_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel -#ifndef CONF_GCLK_GEN_5_DIVSEL -#define CONF_GCLK_GEN_5_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_5_oe -#ifndef CONF_GCLK_GEN_5_OE -#define CONF_GCLK_GEN_5_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_5_oov -#ifndef CONF_GCLK_GEN_5_OOV -#define CONF_GCLK_GEN_5_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_5_idc -#ifndef CONF_GCLK_GEN_5_IDC -#define CONF_GCLK_GEN_5_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_5_enable -#ifndef CONF_GCLK_GEN_5_GENEN -#define CONF_GCLK_GEN_5_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> -// gclk_gen_5_div -#ifndef CONF_GCLK_GEN_5_DIV -#define CONF_GCLK_GEN_5_DIV 1 -#endif -// -// - -// Generic clock generator 6 configuration -// Indicates whether generic clock 6 configuration is enabled or not -// enable_gclk_gen_6 -#ifndef CONF_GCLK_GENERATOR_6_CONFIG -#define CONF_GCLK_GENERATOR_6_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 6 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 6 -// gclk_gen_6_oscillator -#ifndef CONF_GCLK_GEN_6_SOURCE -#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_6_runstdby -#ifndef CONF_GCLK_GEN_6_RUNSTDBY -#define CONF_GCLK_GEN_6_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel -#ifndef CONF_GCLK_GEN_6_DIVSEL -#define CONF_GCLK_GEN_6_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_6_oe -#ifndef CONF_GCLK_GEN_6_OE -#define CONF_GCLK_GEN_6_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_6_oov -#ifndef CONF_GCLK_GEN_6_OOV -#define CONF_GCLK_GEN_6_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_6_idc -#ifndef CONF_GCLK_GEN_6_IDC -#define CONF_GCLK_GEN_6_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_6_enable -#ifndef CONF_GCLK_GEN_6_GENEN -#define CONF_GCLK_GEN_6_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> -// gclk_gen_6_div -#ifndef CONF_GCLK_GEN_6_DIV -#define CONF_GCLK_GEN_6_DIV 1 -#endif -// -// - -// Generic clock generator 7 configuration -// Indicates whether generic clock 7 configuration is enabled or not -// enable_gclk_gen_7 -#ifndef CONF_GCLK_GENERATOR_7_CONFIG -#define CONF_GCLK_GENERATOR_7_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 7 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 7 -// gclk_gen_7_oscillator -#ifndef CONF_GCLK_GEN_7_SOURCE -#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_7_runstdby -#ifndef CONF_GCLK_GEN_7_RUNSTDBY -#define CONF_GCLK_GEN_7_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel -#ifndef CONF_GCLK_GEN_7_DIVSEL -#define CONF_GCLK_GEN_7_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_7_oe -#ifndef CONF_GCLK_GEN_7_OE -#define CONF_GCLK_GEN_7_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_7_oov -#ifndef CONF_GCLK_GEN_7_OOV -#define CONF_GCLK_GEN_7_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_7_idc -#ifndef CONF_GCLK_GEN_7_IDC -#define CONF_GCLK_GEN_7_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_7_enable -#ifndef CONF_GCLK_GEN_7_GENEN -#define CONF_GCLK_GEN_7_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> -// gclk_gen_7_div -#ifndef CONF_GCLK_GEN_7_DIV -#define CONF_GCLK_GEN_7_DIV 1 -#endif -// -// - -// Generic clock generator 8 configuration -// Indicates whether generic clock 8 configuration is enabled or not -// enable_gclk_gen_8 -#ifndef CONF_GCLK_GENERATOR_8_CONFIG -#define CONF_GCLK_GENERATOR_8_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 8 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 8 -// gclk_gen_8_oscillator -#ifndef CONF_GCLK_GEN_8_SOURCE -#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_8_runstdby -#ifndef CONF_GCLK_GEN_8_RUNSTDBY -#define CONF_GCLK_GEN_8_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_8_div_sel -#ifndef CONF_GCLK_GEN_8_DIVSEL -#define CONF_GCLK_GEN_8_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_8_oe -#ifndef CONF_GCLK_GEN_8_OE -#define CONF_GCLK_GEN_8_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_8_oov -#ifndef CONF_GCLK_GEN_8_OOV -#define CONF_GCLK_GEN_8_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_8_idc -#ifndef CONF_GCLK_GEN_8_IDC -#define CONF_GCLK_GEN_8_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_8_enable -#ifndef CONF_GCLK_GEN_8_GENEN -#define CONF_GCLK_GEN_8_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 8 division <0x0000-0xFFFF> -// gclk_gen_8_div -#ifndef CONF_GCLK_GEN_8_DIV -#define CONF_GCLK_GEN_8_DIV 1 -#endif -// -// - -// Generic clock generator 9 configuration -// Indicates whether generic clock 9 configuration is enabled or not -// enable_gclk_gen_9 -#ifndef CONF_GCLK_GENERATOR_9_CONFIG -#define CONF_GCLK_GENERATOR_9_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 9 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 9 -// gclk_gen_9_oscillator -#ifndef CONF_GCLK_GEN_9_SOURCE -#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_9_runstdby -#ifndef CONF_GCLK_GEN_9_RUNSTDBY -#define CONF_GCLK_GEN_9_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_9_div_sel -#ifndef CONF_GCLK_GEN_9_DIVSEL -#define CONF_GCLK_GEN_9_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_9_oe -#ifndef CONF_GCLK_GEN_9_OE -#define CONF_GCLK_GEN_9_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_9_oov -#ifndef CONF_GCLK_GEN_9_OOV -#define CONF_GCLK_GEN_9_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_9_idc -#ifndef CONF_GCLK_GEN_9_IDC -#define CONF_GCLK_GEN_9_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_9_enable -#ifndef CONF_GCLK_GEN_9_GENEN -#define CONF_GCLK_GEN_9_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 9 division <0x0000-0xFFFF> -// gclk_gen_9_div -#ifndef CONF_GCLK_GEN_9_DIV -#define CONF_GCLK_GEN_9_DIV 1 -#endif -// -// - -// Generic clock generator 10 configuration -// Indicates whether generic clock 10 configuration is enabled or not -// enable_gclk_gen_10 -#ifndef CONF_GCLK_GENERATOR_10_CONFIG -#define CONF_GCLK_GENERATOR_10_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 10 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 10 -// gclk_gen_10_oscillator -#ifndef CONF_GCLK_GEN_10_SOURCE -#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_10_runstdby -#ifndef CONF_GCLK_GEN_10_RUNSTDBY -#define CONF_GCLK_GEN_10_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_10_div_sel -#ifndef CONF_GCLK_GEN_10_DIVSEL -#define CONF_GCLK_GEN_10_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_10_oe -#ifndef CONF_GCLK_GEN_10_OE -#define CONF_GCLK_GEN_10_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_10_oov -#ifndef CONF_GCLK_GEN_10_OOV -#define CONF_GCLK_GEN_10_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_10_idc -#ifndef CONF_GCLK_GEN_10_IDC -#define CONF_GCLK_GEN_10_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_10_enable -#ifndef CONF_GCLK_GEN_10_GENEN -#define CONF_GCLK_GEN_10_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 10 division <0x0000-0xFFFF> -// gclk_gen_10_div -#ifndef CONF_GCLK_GEN_10_DIV -#define CONF_GCLK_GEN_10_DIV 1 -#endif -// -// - -// Generic clock generator 11 configuration -// Indicates whether generic clock 11 configuration is enabled or not -// enable_gclk_gen_11 -#ifndef CONF_GCLK_GENERATOR_11_CONFIG -#define CONF_GCLK_GENERATOR_11_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 11 source -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 11 -// gclk_gen_11_oscillator -#ifndef CONF_GCLK_GEN_11_SOURCE -#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_11_runstdby -#ifndef CONF_GCLK_GEN_11_RUNSTDBY -#define CONF_GCLK_GEN_11_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_11_div_sel -#ifndef CONF_GCLK_GEN_11_DIVSEL -#define CONF_GCLK_GEN_11_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_11_oe -#ifndef CONF_GCLK_GEN_11_OE -#define CONF_GCLK_GEN_11_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_11_oov -#ifndef CONF_GCLK_GEN_11_OOV -#define CONF_GCLK_GEN_11_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_11_idc -#ifndef CONF_GCLK_GEN_11_IDC -#define CONF_GCLK_GEN_11_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_11_enable -#ifndef CONF_GCLK_GEN_11_GENEN -#define CONF_GCLK_GEN_11_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 11 division <0x0000-0xFFFF> -// gclk_gen_11_div -#ifndef CONF_GCLK_GEN_11_DIV -#define CONF_GCLK_GEN_11_DIV 1 -#endif -// -// - -// <<< end of configuration section >>> - -#endif // HPL_GCLK_CONFIG_H +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h index 4089d83..03fbccb 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_mclk_config.h @@ -1,104 +1,104 @@ -/* Auto-generated config file hpl_mclk_config.h */ -#ifndef HPL_MCLK_CONFIG_H -#define HPL_MCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// System Configuration -// Indicates whether configuration for system is enabled or not -// enable_cpu_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// Basic settings -// CPU Clock source -// Generic clock generator 0 -// This defines the clock source for the CPU -// cpu_clock_source -#ifndef CONF_CPU_SRC -#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// CPU Clock Division Factor -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// Prescalar for CPU clock -// cpu_div -#ifndef CONF_MCLK_CPUDIV -#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val -#endif -// Low Power Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_lpdiv -#ifndef CONF_MCLK_LPDIV -#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val -#endif - -// Backup Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_bupdiv -#ifndef CONF_MCLK_BUPDIV -#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val -#endif -// High-Speed Clock Division -// Divide by 1 -// mclk_arch_hsdiv -#ifndef CONF_MCLK_HSDIV -#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val -#endif -// - -// NVM Settings -// NVM Wait States -// These bits select the number of wait states for a read operation. -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// nvm_wait_states -#ifndef CONF_NVM_WAIT_STATE -#define CONF_NVM_WAIT_STATE 5 -#endif - -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_MCLK_CONFIG_H +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 5 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h index 1126a13..d82f9a8 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_osc32kctrl_config.h @@ -1,165 +1,165 @@ -/* Auto-generated config file hpl_osc32kctrl_config.h */ -#ifndef HPL_OSC32KCTRL_CONFIG_H -#define HPL_OSC32KCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// RTC Source configuration -// enable_rtc_source -#ifndef CONF_RTCCTRL_CONFIG -#define CONF_RTCCTRL_CONFIG 0 -#endif - -// RTC source control -// RTC Clock Source Selection -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// This defines the clock source for RTC -// rtc_source_oscillator -#ifndef CONF_RTCCTRL_SRC -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K -#endif - -// Use 1 kHz output -// rtc_1khz_selection -#ifndef CONF_RTCCTRL_1KHZ - -#define CONF_RTCCTRL_1KHZ 0 - -#endif - -#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) -#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) -#else -#error unexpected CONF_RTCCTRL_SRC -#endif - -// -// - -// 32kHz External Crystal Oscillator Configuration -// Indicates whether configuration for External 32K Osc is enabled or not -// enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 1 -#endif - -// 32kHz External Crystal Oscillator Control -// Oscillator enable -// Indicates whether 32kHz External Crystal Oscillator is enabled or not -// xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 1 -#endif - -// Start-Up Time -// <0x0=>62592us -// <0x1=>125092us -// <0x2=>500092us -// <0x3=>1000092us -// <0x4=>2000092us -// <0x5=>4000092us -// <0x6=>8000092us -// xosc32k_arch_startup -#ifndef CONF_XOSC32K_STARTUP -#define CONF_XOSC32K_STARTUP 0x3 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc32k_arch_ondemand -#ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc32k_arch_runstdby -#ifndef CONF_XOSC32K_RUNSTDBY -#define CONF_XOSC32K_RUNSTDBY 0 -#endif - -// 1kHz Output Enable -// Indicates whether 1kHz Output is enabled or not -// xosc32k_arch_en1k -#ifndef CONF_XOSC32K_EN1K -#define CONF_XOSC32K_EN1K 0 -#endif - -// 32kHz Output Enable -// Indicates whether 32kHz Output is enabled or not -// xosc32k_arch_en32k -#ifndef CONF_XOSC32K_EN32K -#define CONF_XOSC32K_EN32K 1 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc32k_arch_swben -#ifndef CONF_XOSC32K_SWBEN -#define CONF_XOSC32K_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc32k_arch_cfden -#ifndef CONF_XOSC32K_CFDEN -#define CONF_XOSC32K_CFDEN 0 -#endif - -// Clock Failure Detector Event Out -// Indicates whether Clock Failure Detector Event Out is enabled or not -// xosc32k_arch_cfdeo -#ifndef CONF_XOSC32K_CFDEO -#define CONF_XOSC32K_CFDEO 0 -#endif - -// Crystal connected to XIN32/XOUT32 Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc32k_arch_xtalen -#ifndef CONF_XOSC32K_XTALEN -#define CONF_XOSC32K_XTALEN 1 -#endif - -// Control Gain Mode -// <0x0=>Low Power mode -// <0x1=>Standard mode -// <0x2=>High Speed mode -// xosc32k_arch_cgm -#ifndef CONF_XOSC32K_CGM -#define CONF_XOSC32K_CGM 0x1 -#endif - -// -// - -// 32kHz Ultra Low Power Internal Oscillator Configuration -// Indicates whether configuration for OSCULP32K is enabled or not -// enable_osculp32k -#ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 -#endif - -// 32kHz Ultra Low Power Internal Oscillator Control - -// Oscillator Calibration Control -// Indicates whether Oscillator Calibration is enabled or not -// osculp32k_calib_enable -#ifndef CONF_OSCULP32K_CALIB_ENABLE -#define CONF_OSCULP32K_CALIB_ENABLE 0 -#endif - -// Oscillator Calibration <0x0-0x3F> -// osculp32k_calib -#ifndef CONF_OSCULP32K_CALIB -#define CONF_OSCULP32K_CALIB 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSC32KCTRL_CONFIG_H +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x3 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 1 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_oscctrl_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_oscctrl_config.h index 2404d96..58665aa 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_oscctrl_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_oscctrl_config.h @@ -1,640 +1,640 @@ -/* Auto-generated config file hpl_oscctrl_config.h */ -#ifndef HPL_OSCCTRL_CONFIG_H -#define HPL_OSCCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC0 is enabled or not -// enable_xosc0 -#ifndef CONF_XOSC0_CONFIG -#define CONF_XOSC0_CONFIG 0 -#endif - -// Frequency <8000000-48000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc0_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC0_FREQUENCY 12000000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc0_arch_enable -#ifndef CONF_XOSC0_ENABLE -#define CONF_XOSC0_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc0_arch_startup -#ifndef CONF_XOSC0_STARTUP -#define CONF_XOSC0_STARTUP 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc0_arch_swben -#ifndef CONF_XOSC0_SWBEN -#define CONF_XOSC0_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc0_arch_cfden -#ifndef CONF_XOSC0_CFDEN -#define CONF_XOSC0_CFDEN 0 -#endif - -// Automatic Loop Control Enable -// Indicates whether Automatic Loop Control is enabled or not -// xosc0_arch_enalc -#ifndef CONF_XOSC0_ENALC -#define CONF_XOSC0_ENALC 0 -#endif - -// Low Buffer Gain Enable -// Indicates whether Low Buffer Gain is enabled or not -// xosc0_arch_lowbufgain -#ifndef CONF_XOSC0_LOWBUFGAIN -#define CONF_XOSC0_LOWBUFGAIN 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc0_arch_ondemand -#ifndef CONF_XOSC0_ONDEMAND -#define CONF_XOSC0_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc0_arch_runstdby -#ifndef CONF_XOSC0_RUNSTDBY -#define CONF_XOSC0_RUNSTDBY 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc0_arch_xtalen -#ifndef CONF_XOSC0_XTALEN -#define CONF_XOSC0_XTALEN 0 -#endif -// -// - -#if CONF_XOSC0_FREQUENCY >= 32000000 -#define CONF_XOSC0_CFDPRESC 0x0 -#define CONF_XOSC0_IMULT 0x7 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 24000000 -#define CONF_XOSC0_CFDPRESC 0x1 -#define CONF_XOSC0_IMULT 0x6 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 16000000 -#define CONF_XOSC0_CFDPRESC 0x2 -#define CONF_XOSC0_IMULT 0x5 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 8000000 -#define CONF_XOSC0_CFDPRESC 0x3 -#define CONF_XOSC0_IMULT 0x4 -#define CONF_XOSC0_IPTAT 0x3 -#endif - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC1 is enabled or not -// enable_xosc1 -#ifndef CONF_XOSC1_CONFIG -#define CONF_XOSC1_CONFIG 0 -#endif - -// Frequency <8000000-48000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc1_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC1_FREQUENCY 12000000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc1_arch_enable -#ifndef CONF_XOSC1_ENABLE -#define CONF_XOSC1_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc1_arch_startup -#ifndef CONF_XOSC1_STARTUP -#define CONF_XOSC1_STARTUP 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc1_arch_swben -#ifndef CONF_XOSC1_SWBEN -#define CONF_XOSC1_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc1_arch_cfden -#ifndef CONF_XOSC1_CFDEN -#define CONF_XOSC1_CFDEN 0 -#endif - -// Automatic Loop Control Enable -// Indicates whether Automatic Loop Control is enabled or not -// xosc1_arch_enalc -#ifndef CONF_XOSC1_ENALC -#define CONF_XOSC1_ENALC 0 -#endif - -// Low Buffer Gain Enable -// Indicates whether Low Buffer Gain is enabled or not -// xosc1_arch_lowbufgain -#ifndef CONF_XOSC1_LOWBUFGAIN -#define CONF_XOSC1_LOWBUFGAIN 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc1_arch_ondemand -#ifndef CONF_XOSC1_ONDEMAND -#define CONF_XOSC1_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc1_arch_runstdby -#ifndef CONF_XOSC1_RUNSTDBY -#define CONF_XOSC1_RUNSTDBY 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc1_arch_xtalen -#ifndef CONF_XOSC1_XTALEN -#define CONF_XOSC1_XTALEN 1 -#endif -// -// - -#if CONF_XOSC1_FREQUENCY >= 32000000 -#define CONF_XOSC1_CFDPRESC 0x0 -#define CONF_XOSC1_IMULT 0x7 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 24000000 -#define CONF_XOSC1_CFDPRESC 0x1 -#define CONF_XOSC1_IMULT 0x6 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 16000000 -#define CONF_XOSC1_CFDPRESC 0x2 -#define CONF_XOSC1_IMULT 0x5 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 8000000 -#define CONF_XOSC1_CFDPRESC 0x3 -#define CONF_XOSC1_IMULT 0x4 -#define CONF_XOSC1_IPTAT 0x3 -#endif - -// DFLL Configuration -// Indicates whether configuration for DFLL is enabled or not -// enable_dfll -#ifndef CONF_DFLL_CONFIG -#define CONF_DFLL_CONFIG 0 -#endif - -// Reference Clock Source -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source -// dfll_ref_clock -#ifndef CONF_DFLL_GCLK -#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -// Digital Frequency Locked Loop Control -// DFLL Enable -// Indicates whether DFLL is enabled or not -// dfll_arch_enable -#ifndef CONF_DFLL_ENABLE -#define CONF_DFLL_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// dfll_arch_ondemand -#ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// dfll_arch_runstdby -#ifndef CONF_DFLL_RUNSTDBY -#define CONF_DFLL_RUNSTDBY 0 -#endif - -// USB Clock Recovery Mode -// Indicates whether USB Clock Recovery Mode is enabled or not -// dfll_arch_usbcrm -#ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 0 -#endif - -// Wait Lock -// Indicates whether Wait Lock is enabled or not -// dfll_arch_waitlock -#ifndef CONF_DFLL_WAITLOCK -#define CONF_DFLL_WAITLOCK 1 -#endif - -// Bypass Coarse Lock -// Indicates whether Bypass Coarse Lock is enabled or not -// dfll_arch_bplckc -#ifndef CONF_DFLL_BPLCKC -#define CONF_DFLL_BPLCKC 0 -#endif - -// Quick Lock Disable -// Indicates whether Quick Lock Disable is enabled or not -// dfll_arch_qldis -#ifndef CONF_DFLL_QLDIS -#define CONF_DFLL_QLDIS 0 -#endif - -// Chill Cycle Disable -// Indicates whether Chill Cycle Disable is enabled or not -// dfll_arch_ccdis -#ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 -#endif - -// Lose Lock After Wake -// Indicates whether Lose Lock After Wake is enabled or not -// dfll_arch_llaw -#ifndef CONF_DFLL_LLAW -#define CONF_DFLL_LLAW 0 -#endif - -// Stable DFLL Frequency -// Indicates whether Stable DFLL Frequency is enabled or not -// dfll_arch_stable -#ifndef CONF_DFLL_STABLE -#define CONF_DFLL_STABLE 0 -#endif - -// Operating Mode Selection -// <0=>Open Loop Mode -// <1=>Closed Loop Mode -// dfll_mode -#ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 0x0 -#endif - -// Coarse Maximum Step <0x0-0x1F> -// dfll_arch_cstep -#ifndef CONF_DFLL_CSTEP -#define CONF_DFLL_CSTEP 0x1 -#endif - -// Fine Maximum Step <0x0-0xFF> -// dfll_arch_fstep -#ifndef CONF_DFLL_FSTEP -#define CONF_DFLL_FSTEP 0x1 -#endif - -// DFLL Multiply Factor <0x0-0xFFFF> -// dfll_mul -#ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0x0 -#endif - -// DFLL Calibration Overwrite -// Indicates whether Overwrite Calibration value of DFLL -// dfll_arch_calibration -#ifndef CONF_DFLL_OVERWRITE_CALIBRATION -#define CONF_DFLL_OVERWRITE_CALIBRATION 0 -#endif - -// Coarse Value <0x0-0x3F> -// dfll_arch_coarse -#ifndef CONF_DFLL_COARSE -#define CONF_DFLL_COARSE (0x1f / 4) -#endif - -// Fine Value <0x0-0xFF> -// dfll_arch_fine -#ifndef CONF_DFLL_FINE -#define CONF_DFLL_FINE (0x80) -#endif - -// - -// - -// - -// FDPLL0 Configuration -// Indicates whether configuration for FDPLL0 is enabled or not -// enable_fdpll0 -#ifndef CONF_FDPLL0_CONFIG -#define CONF_FDPLL0_CONFIG 1 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source. -// fdpll0_ref_clock -#ifndef CONF_FDPLL0_GCLK -#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll0_arch_enable -#ifndef CONF_FDPLL0_ENABLE -#define CONF_FDPLL0_ENABLE 1 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll0_arch_ondemand -#ifndef CONF_FDPLL0_ONDEMAND -#define CONF_FDPLL0_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll0_arch_runstdby -#ifndef CONF_FDPLL0_RUNSTDBY -#define CONF_FDPLL0_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0x1F> -// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll0_ldrfrac -#ifndef CONF_FDPLL0_LDRFRAC -#define CONF_FDPLL0_LDRFRAC 0x1 -#endif - -// Loop Divider Ratio Integer Part <0x0-0x1FFF> -// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll0_ldr -#ifndef CONF_FDPLL0_LDR -#define CONF_FDPLL0_LDR 0xe4d -#endif - -// Clock Divider <0x0-0x7FF> -// This Clock divider is only for XOSC clock input to DPLL -// fdpll0_clock_div -#ifndef CONF_FDPLL0_DIV -#define CONF_FDPLL0_DIV 0x0 -#endif - -// DCO Filter Enable -// Indicates whether DCO Filter Enable is enabled or not -// fdpll0_arch_dcoen -#ifndef CONF_FDPLL0_DCOEN -#define CONF_FDPLL0_DCOEN 0 -#endif - -// Sigma-Delta DCO Filter Selection <0x0-0x7> -// fdpll0_clock_dcofilter -#ifndef CONF_FDPLL0_DCOFILTER -#define CONF_FDPLL0_DCOFILTER 0x0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll0_arch_lbypass -#ifndef CONF_FDPLL0_LBYPASS -#define CONF_FDPLL0_LBYPASS 1 -#endif - -// Lock Time -// <0x0=>No time-out, automatic lock -// <0x4=>The Time-out if no lock within 800 us -// <0x5=>The Time-out if no lock within 900 us -// <0x6=>The Time-out if no lock within 1 ms -// <0x7=>The Time-out if no lock within 11 ms -// fdpll0_arch_ltime -#ifndef CONF_FDPLL0_LTIME -#define CONF_FDPLL0_LTIME 0x0 -#endif - -// Reference Clock Selection -// <0x0=>GCLK clock reference -// <0x1=>XOSC32K clock reference -// <0x2=>XOSC0 clock reference -// <0x3=>XOSC1 clock reference -// fdpll0_arch_refclk -#ifndef CONF_FDPLL0_REFCLK -#define CONF_FDPLL0_REFCLK 0x1 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll0_arch_wuf -#ifndef CONF_FDPLL0_WUF -#define CONF_FDPLL0_WUF 0 -#endif - -// Proportional Integral Filter Selection <0x0-0xF> -// fdpll0_arch_filter -#ifndef CONF_FDPLL0_FILTER -#define CONF_FDPLL0_FILTER 0x0 -#endif - -// -// -// FDPLL1 Configuration -// Indicates whether configuration for FDPLL1 is enabled or not -// enable_fdpll1 -#ifndef CONF_FDPLL1_CONFIG -#define CONF_FDPLL1_CONFIG 0 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source. -// fdpll1_ref_clock -#ifndef CONF_FDPLL1_GCLK -#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll1_arch_enable -#ifndef CONF_FDPLL1_ENABLE -#define CONF_FDPLL1_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll1_arch_ondemand -#ifndef CONF_FDPLL1_ONDEMAND -#define CONF_FDPLL1_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll1_arch_runstdby -#ifndef CONF_FDPLL1_RUNSTDBY -#define CONF_FDPLL1_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0x1F> -// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll1_ldrfrac -#ifndef CONF_FDPLL1_LDRFRAC -#define CONF_FDPLL1_LDRFRAC 0xd -#endif - -// Loop Divider Ratio Integer Part <0x0-0x1FFF> -// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register -// fdpll1_ldr -#ifndef CONF_FDPLL1_LDR -#define CONF_FDPLL1_LDR 0x5b7 -#endif - -// Clock Divider <0x0-0x7FF> -// This Clock divider is only for XOSC clock input to DPLL -// fdpll1_clock_div -#ifndef CONF_FDPLL1_DIV -#define CONF_FDPLL1_DIV 0x0 -#endif - -// DCO Filter Enable -// Indicates whether DCO Filter Enable is enabled or not -// fdpll1_arch_dcoen -#ifndef CONF_FDPLL1_DCOEN -#define CONF_FDPLL1_DCOEN 0 -#endif - -// Sigma-Delta DCO Filter Selection <0x0-0x7> -// fdpll1_clock_dcofilter -#ifndef CONF_FDPLL1_DCOFILTER -#define CONF_FDPLL1_DCOFILTER 0x0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll1_arch_lbypass -#ifndef CONF_FDPLL1_LBYPASS -#define CONF_FDPLL1_LBYPASS 0 -#endif - -// Lock Time -// <0x0=>No time-out, automatic lock -// <0x4=>The Time-out if no lock within 800 us -// <0x5=>The Time-out if no lock within 900 us -// <0x6=>The Time-out if no lock within 1 ms -// <0x7=>The Time-out if no lock within 11 ms -// fdpll1_arch_ltime -#ifndef CONF_FDPLL1_LTIME -#define CONF_FDPLL1_LTIME 0x0 -#endif - -// Reference Clock Selection -// <0x0=>GCLK clock reference -// <0x1=>XOSC32K clock reference -// <0x2=>XOSC0 clock reference -// <0x3=>XOSC1 clock reference -// fdpll1_arch_refclk -#ifndef CONF_FDPLL1_REFCLK -#define CONF_FDPLL1_REFCLK 0x1 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll1_arch_wuf -#ifndef CONF_FDPLL1_WUF -#define CONF_FDPLL1_WUF 0 -#endif - -// Proportional Integral Filter Selection <0x0-0xF> -// fdpll1_arch_filter -#ifndef CONF_FDPLL1_FILTER -#define CONF_FDPLL1_FILTER 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSCCTRL_CONFIG_H +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 1 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 1 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0x1 +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 0xe4d +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 1 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_port_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_port_config.h index b5315f0..68c0cca 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_port_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_port_config.h @@ -1,522 +1,522 @@ -/* Auto-generated config file hpl_port_config.h */ -#ifndef HPL_PORT_CONFIG_H -#define HPL_PORT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// PORT Input Event 0 configuration -// enable_port_input_event_0 -#ifndef CONF_PORT_EVCTRL_PORT_0 -#define CONF_PORT_EVCTRL_PORT_0 0 -#endif - -// PORT Input Event 0 configuration on PORT A - -// PORTA Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled -// porta_input_event_enable_0 -#ifndef CONF_PORTA_EVCTRL_PORTEI_0 -#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTA Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_0 -#ifndef CONF_PORTA_EVCTRL_PID_0 -#define CONF_PORTA_EVCTRL_PID_0 0x0 -#endif - -// PORTA Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 0 -// porta_event_action_0 -#ifndef CONF_PORTA_EVCTRL_EVACT_0 -#define CONF_PORTA_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT B - -// PORTB Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled -// portb_input_event_enable_0 -#ifndef CONF_PORTB_EVCTRL_PORTEI_0 -#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTB Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_0 -#ifndef CONF_PORTB_EVCTRL_PID_0 -#define CONF_PORTB_EVCTRL_PID_0 0x0 -#endif - -// PORTB Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 0 -// portb_event_action_0 -#ifndef CONF_PORTB_EVCTRL_EVACT_0 -#define CONF_PORTB_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT C - -// PORTC Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled -// portc_input_event_enable_0 -#ifndef CONF_PORTC_EVCTRL_PORTEI_0 -#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTC Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_0 -#ifndef CONF_PORTC_EVCTRL_PID_0 -#define CONF_PORTC_EVCTRL_PID_0 0x0 -#endif - -// PORTC Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 0 -// portc_event_action_0 -#ifndef CONF_PORTC_EVCTRL_EVACT_0 -#define CONF_PORTC_EVCTRL_EVACT_0 0 -#endif - -// -// PORT Input Event 0 configuration on PORT D - -// PORTD Input Event 0 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled -// portd_input_event_enable_0 -#ifndef CONF_PORTD_EVCTRL_PORTEI_0 -#define CONF_PORTD_EVCTRL_PORTEI_0 0x0 -#endif - -// PORTD Event 0 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_0 -#ifndef CONF_PORTD_EVCTRL_PID_0 -#define CONF_PORTD_EVCTRL_PID_0 0x0 -#endif - -// PORTD Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 0 -// portd_event_action_0 -#ifndef CONF_PORTD_EVCTRL_EVACT_0 -#define CONF_PORTD_EVCTRL_EVACT_0 0 -#endif - -// - -// - -// PORT Input Event 1 configuration -// enable_port_input_event_1 -#ifndef CONF_PORT_EVCTRL_PORT_1 -#define CONF_PORT_EVCTRL_PORT_1 0 -#endif - -// PORT Input Event 1 configuration on PORT A - -// PORTA Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled -// porta_input_event_enable_1 -#ifndef CONF_PORTA_EVCTRL_PORTEI_1 -#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTA Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_1 -#ifndef CONF_PORTA_EVCTRL_PID_1 -#define CONF_PORTA_EVCTRL_PID_1 0x0 -#endif - -// PORTA Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 1 -// porta_event_action_1 -#ifndef CONF_PORTA_EVCTRL_EVACT_1 -#define CONF_PORTA_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT B - -// PORTB Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled -// portb_input_event_enable_1 -#ifndef CONF_PORTB_EVCTRL_PORTEI_1 -#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTB Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_1 -#ifndef CONF_PORTB_EVCTRL_PID_1 -#define CONF_PORTB_EVCTRL_PID_1 0x0 -#endif - -// PORTB Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 1 -// portb_event_action_1 -#ifndef CONF_PORTB_EVCTRL_EVACT_1 -#define CONF_PORTB_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT C - -// PORTC Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled -// portc_input_event_enable_1 -#ifndef CONF_PORTC_EVCTRL_PORTEI_1 -#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTC Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_1 -#ifndef CONF_PORTC_EVCTRL_PID_1 -#define CONF_PORTC_EVCTRL_PID_1 0x0 -#endif - -// PORTC Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 1 -// portc_event_action_1 -#ifndef CONF_PORTC_EVCTRL_EVACT_1 -#define CONF_PORTC_EVCTRL_EVACT_1 0 -#endif - -// -// PORT Input Event 1 configuration on PORT D - -// PORTD Input Event 1 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled -// portd_input_event_enable_1 -#ifndef CONF_PORTD_EVCTRL_PORTEI_1 -#define CONF_PORTD_EVCTRL_PORTEI_1 0x0 -#endif - -// PORTD Event 1 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_1 -#ifndef CONF_PORTD_EVCTRL_PID_1 -#define CONF_PORTD_EVCTRL_PID_1 0x0 -#endif - -// PORTD Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 1 -// portd_event_action_1 -#ifndef CONF_PORTD_EVCTRL_EVACT_1 -#define CONF_PORTD_EVCTRL_EVACT_1 0 -#endif - -// - -// - -// PORT Input Event 2 configuration -// enable_port_input_event_2 -#ifndef CONF_PORT_EVCTRL_PORT_2 -#define CONF_PORT_EVCTRL_PORT_2 0 -#endif - -// PORT Input Event 2 configuration on PORT A - -// PORTA Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled -// porta_input_event_enable_2 -#ifndef CONF_PORTA_EVCTRL_PORTEI_2 -#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTA Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_2 -#ifndef CONF_PORTA_EVCTRL_PID_2 -#define CONF_PORTA_EVCTRL_PID_2 0x0 -#endif - -// PORTA Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 2 -// porta_event_action_2 -#ifndef CONF_PORTA_EVCTRL_EVACT_2 -#define CONF_PORTA_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT B - -// PORTB Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled -// portb_input_event_enable_2 -#ifndef CONF_PORTB_EVCTRL_PORTEI_2 -#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTB Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_2 -#ifndef CONF_PORTB_EVCTRL_PID_2 -#define CONF_PORTB_EVCTRL_PID_2 0x0 -#endif - -// PORTB Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 2 -// portb_event_action_2 -#ifndef CONF_PORTB_EVCTRL_EVACT_2 -#define CONF_PORTB_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT C - -// PORTC Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled -// portc_input_event_enable_2 -#ifndef CONF_PORTC_EVCTRL_PORTEI_2 -#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTC Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_2 -#ifndef CONF_PORTC_EVCTRL_PID_2 -#define CONF_PORTC_EVCTRL_PID_2 0x0 -#endif - -// PORTC Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 2 -// portc_event_action_2 -#ifndef CONF_PORTC_EVCTRL_EVACT_2 -#define CONF_PORTC_EVCTRL_EVACT_2 0 -#endif - -// -// PORT Input Event 2 configuration on PORT D - -// PORTD Input Event 2 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled -// portd_input_event_enable_2 -#ifndef CONF_PORTD_EVCTRL_PORTEI_2 -#define CONF_PORTD_EVCTRL_PORTEI_2 0x0 -#endif - -// PORTD Event 2 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_2 -#ifndef CONF_PORTD_EVCTRL_PID_2 -#define CONF_PORTD_EVCTRL_PID_2 0x0 -#endif - -// PORTD Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 2 -// portd_event_action_2 -#ifndef CONF_PORTD_EVCTRL_EVACT_2 -#define CONF_PORTD_EVCTRL_EVACT_2 0 -#endif - -// - -// - -// PORT Input Event 3 configuration -// enable_port_input_event_3 -#ifndef CONF_PORT_EVCTRL_PORT_3 -#define CONF_PORT_EVCTRL_PORT_3 0 -#endif - -// PORT Input Event 3 configuration on PORT A - -// PORTA Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled -// porta_input_event_enable_3 -#ifndef CONF_PORTA_EVCTRL_PORTEI_3 -#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTA Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port A on which the event action will be performed -// porta_event_pin_identifier_3 -#ifndef CONF_PORTA_EVCTRL_PID_3 -#define CONF_PORTA_EVCTRL_PID_3 0x0 -#endif - -// PORTA Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT A will perform on event input 3 -// porta_event_action_3 -#ifndef CONF_PORTA_EVCTRL_EVACT_3 -#define CONF_PORTA_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT B - -// PORTB Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled -// portb_input_event_enable_3 -#ifndef CONF_PORTB_EVCTRL_PORTEI_3 -#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTB Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port B on which the event action will be performed -// portb_event_pin_identifier_3 -#ifndef CONF_PORTB_EVCTRL_PID_3 -#define CONF_PORTB_EVCTRL_PID_3 0x0 -#endif - -// PORTB Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT B will perform on event input 3 -// portb_event_action_3 -#ifndef CONF_PORTB_EVCTRL_EVACT_3 -#define CONF_PORTB_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT C - -// PORTC Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled -// portc_input_event_enable_3 -#ifndef CONF_PORTC_EVCTRL_PORTEI_3 -#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTC Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port C on which the event action will be performed -// portc_event_pin_identifier_3 -#ifndef CONF_PORTC_EVCTRL_PID_3 -#define CONF_PORTC_EVCTRL_PID_3 0x0 -#endif - -// PORTC Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT C will perform on event input 3 -// portc_event_action_3 -#ifndef CONF_PORTC_EVCTRL_EVACT_3 -#define CONF_PORTC_EVCTRL_EVACT_3 0 -#endif - -// -// PORT Input Event 3 configuration on PORT D - -// PORTD Input Event 3 Enable -// The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled -// portd_input_event_enable_3 -#ifndef CONF_PORTD_EVCTRL_PORTEI_3 -#define CONF_PORTD_EVCTRL_PORTEI_3 0x0 -#endif - -// PORTD Event 3 Pin Identifier <0x00-0x1F> -// These bits define the I/O pin from port D on which the event action will be performed -// portd_event_pin_identifier_3 -#ifndef CONF_PORTD_EVCTRL_PID_3 -#define CONF_PORTD_EVCTRL_PID_3 0x0 -#endif - -// PORTD Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// These bits define the event action the PORT D will perform on event input 3 -// portd_event_action_3 -#ifndef CONF_PORTD_EVCTRL_EVACT_3 -#define CONF_PORTD_EVCTRL_EVACT_3 0 -#endif - -// - -// - -#define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) -#define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) -#define CONF_PORTC_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ - | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ - | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) -#define CONF_PORTD_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \ - | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \ - | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3)) - -// <<< end of configuration section >>> - -#endif // HPL_PORT_CONFIG_H +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT C + +// PORTC Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled +// portc_input_event_enable_0 +#ifndef CONF_PORTC_EVCTRL_PORTEI_0 +#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTC Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_0 +#ifndef CONF_PORTC_EVCTRL_PID_0 +#define CONF_PORTC_EVCTRL_PID_0 0x0 +#endif + +// PORTC Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 0 +// portc_event_action_0 +#ifndef CONF_PORTC_EVCTRL_EVACT_0 +#define CONF_PORTC_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT D + +// PORTD Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled +// portd_input_event_enable_0 +#ifndef CONF_PORTD_EVCTRL_PORTEI_0 +#define CONF_PORTD_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTD Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_0 +#ifndef CONF_PORTD_EVCTRL_PID_0 +#define CONF_PORTD_EVCTRL_PID_0 0x0 +#endif + +// PORTD Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 0 +// portd_event_action_0 +#ifndef CONF_PORTD_EVCTRL_EVACT_0 +#define CONF_PORTD_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT C + +// PORTC Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled +// portc_input_event_enable_1 +#ifndef CONF_PORTC_EVCTRL_PORTEI_1 +#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTC Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_1 +#ifndef CONF_PORTC_EVCTRL_PID_1 +#define CONF_PORTC_EVCTRL_PID_1 0x0 +#endif + +// PORTC Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 1 +// portc_event_action_1 +#ifndef CONF_PORTC_EVCTRL_EVACT_1 +#define CONF_PORTC_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT D + +// PORTD Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled +// portd_input_event_enable_1 +#ifndef CONF_PORTD_EVCTRL_PORTEI_1 +#define CONF_PORTD_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTD Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_1 +#ifndef CONF_PORTD_EVCTRL_PID_1 +#define CONF_PORTD_EVCTRL_PID_1 0x0 +#endif + +// PORTD Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 1 +// portd_event_action_1 +#ifndef CONF_PORTD_EVCTRL_EVACT_1 +#define CONF_PORTD_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT C + +// PORTC Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled +// portc_input_event_enable_2 +#ifndef CONF_PORTC_EVCTRL_PORTEI_2 +#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTC Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_2 +#ifndef CONF_PORTC_EVCTRL_PID_2 +#define CONF_PORTC_EVCTRL_PID_2 0x0 +#endif + +// PORTC Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 2 +// portc_event_action_2 +#ifndef CONF_PORTC_EVCTRL_EVACT_2 +#define CONF_PORTC_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT D + +// PORTD Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled +// portd_input_event_enable_2 +#ifndef CONF_PORTD_EVCTRL_PORTEI_2 +#define CONF_PORTD_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTD Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_2 +#ifndef CONF_PORTD_EVCTRL_PID_2 +#define CONF_PORTD_EVCTRL_PID_2 0x0 +#endif + +// PORTD Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 2 +// portd_event_action_2 +#ifndef CONF_PORTD_EVCTRL_EVACT_2 +#define CONF_PORTD_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT C + +// PORTC Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled +// portc_input_event_enable_3 +#ifndef CONF_PORTC_EVCTRL_PORTEI_3 +#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTC Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_3 +#ifndef CONF_PORTC_EVCTRL_PID_3 +#define CONF_PORTC_EVCTRL_PID_3 0x0 +#endif + +// PORTC Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 3 +// portc_event_action_3 +#ifndef CONF_PORTC_EVCTRL_EVACT_3 +#define CONF_PORTC_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT D + +// PORTD Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled +// portd_input_event_enable_3 +#ifndef CONF_PORTD_EVCTRL_PORTEI_3 +#define CONF_PORTD_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTD Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port D on which the event action will be performed +// portd_event_pin_identifier_3 +#ifndef CONF_PORTD_EVCTRL_PID_3 +#define CONF_PORTD_EVCTRL_PID_3 0x0 +#endif + +// PORTD Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT D will perform on event input 3 +// portd_event_action_3 +#ifndef CONF_PORTD_EVCTRL_EVACT_3 +#define CONF_PORTD_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) +#define CONF_PORTC_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ + | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ + | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) +#define CONF_PORTD_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \ + | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \ + | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h index 68ce64c..af90e32 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_sercom_config.h @@ -1,413 +1,413 @@ -/* Auto-generated config file hpl_sercom_config.h */ -#ifndef HPL_SERCOM_CONFIG_H -#define HPL_SERCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 1 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable input buffer in SERCOM module -// usart_rx_enable -#ifndef CONF_SERCOM_2_USART_RXEN -#define CONF_SERCOM_2_USART_RXEN 1 -#endif - -// Transmitt buffer enable -// Enable output buffer in SERCOM module -// usart_tx_enable -#ifndef CONF_SERCOM_2_USART_TXEN -#define CONF_SERCOM_2_USART_TXEN 1 -#endif - -// Frame parity -// <0x0=>No parity -// <0x1=>Even parity -// <0x2=>Odd parity -// Parity bit mode for USART frame -// usart_parity -#ifndef CONF_SERCOM_2_USART_PARITY -#define CONF_SERCOM_2_USART_PARITY 0x0 -#endif - -// Character Size -// <0x0=>8 bits -// <0x1=>9 bits -// <0x5=>5 bits -// <0x6=>6 bits -// <0x7=>7 bits -// Data character size in USART frame -// usart_character_size -#ifndef CONF_SERCOM_2_USART_CHSIZE -#define CONF_SERCOM_2_USART_CHSIZE 0x0 -#endif - -// Stop Bit -// <0=>One stop bit -// <1=>Two stop bits -// Number of stop bits in USART frame -// usart_stop_bit -#ifndef CONF_SERCOM_2_USART_SBMODE -#define CONF_SERCOM_2_USART_SBMODE 0 -#endif - -// Baud rate <1-6250000> -// USART baud rate setting -// usart_baud_rate -#ifndef CONF_SERCOM_2_USART_BAUD -#define CONF_SERCOM_2_USART_BAUD 115200 -#endif - -// - -// Advanced configuration -// usart_advanced -#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG -#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 -#endif - -// Run in stand-by -// Keep the module running in standby sleep mode -// usart_arch_runstdby -#ifndef CONF_SERCOM_2_USART_RUNSTDBY -#define CONF_SERCOM_2_USART_RUNSTDBY 0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when the BUFOVF status bit is asserted -// usart_arch_ibon -#ifndef CONF_SERCOM_2_USART_IBON -#define CONF_SERCOM_2_USART_IBON 0 -#endif - -// Start of Frame Detection Enable -// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) -// usart_arch_sfde -#ifndef CONF_SERCOM_2_USART_SFDE -#define CONF_SERCOM_2_USART_SFDE 0 -#endif - -// Collision Detection Enable -// Collision detection enable -// usart_arch_cloden -#ifndef CONF_SERCOM_2_USART_CLODEN -#define CONF_SERCOM_2_USART_CLODEN 0 -#endif - -// Operating Mode -// <0x0=>USART with external clock -// <0x1=>USART with internal clock -// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. -// usart_arch_clock_mode -#ifndef CONF_SERCOM_2_USART_MODE -#define CONF_SERCOM_2_USART_MODE 0x1 -#endif - -// Sample Rate -// <0x0=>16x arithmetic -// <0x1=>16x fractional -// <0x2=>8x arithmetic -// <0x3=>8x fractional -// <0x4=>3x arithmetic -// How many over-sampling bits used when sampling data state -// usart_arch_sampr -#ifndef CONF_SERCOM_2_USART_SAMPR -#define CONF_SERCOM_2_USART_SAMPR 0x0 -#endif - -// Sample Adjustment -// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) -// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) -// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) -// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) -// Adjust which samples to use for data sampling in asynchronous mode -// usart_arch_sampa -#ifndef CONF_SERCOM_2_USART_SAMPA -#define CONF_SERCOM_2_USART_SAMPA 0x0 -#endif - -// Fractional Part <0-7> -// Fractional part of the baud rate if baud rate generator is in fractional mode -// usart_arch_fractional -#ifndef CONF_SERCOM_2_USART_FRACTIONAL -#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 -#endif - -// Data Order -// <0=>MSB is transmitted first -// <1=>LSB is transmitted first -// Data order of the data bits in the frame -// usart_arch_dord -#ifndef CONF_SERCOM_2_USART_DORD -#define CONF_SERCOM_2_USART_DORD 1 -#endif - -// Does not do anything in UART mode -#define CONF_SERCOM_2_USART_CPOL 0 - -// Encoding Format -// <0=>No encoding -// <1=>IrDA encoded -// usart_arch_enc -#ifndef CONF_SERCOM_2_USART_ENC -#define CONF_SERCOM_2_USART_ENC 0 -#endif - -// LIN Slave Enable -// Break Character Detection and Auto-Baud/LIN Slave Enable. -// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). -// <0=>Disable -// <1=>Enable -// usart_arch_lin_slave_enable -#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE -#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// usart_arch_dbgstop -#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE -#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_2_USART_INACK -#define CONF_SERCOM_2_USART_INACK 0x0 -#endif - -#ifndef CONF_SERCOM_2_USART_DSNACK -#define CONF_SERCOM_2_USART_DSNACK 0x0 -#endif - -#ifndef CONF_SERCOM_2_USART_MAXITER -#define CONF_SERCOM_2_USART_MAXITER 0x7 -#endif - -#ifndef CONF_SERCOM_2_USART_GTIME -#define CONF_SERCOM_2_USART_GTIME 0x2 -#endif - -#define CONF_SERCOM_2_USART_RXINV 0x0 -#define CONF_SERCOM_2_USART_TXINV 0x0 - -#ifndef CONF_SERCOM_2_USART_CMODE -#define CONF_SERCOM_2_USART_CMODE 0 -#endif - -#ifndef CONF_SERCOM_2_USART_RXPO -#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ -#endif - -#ifndef CONF_SERCOM_2_USART_TXPO -#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ -#endif - -/* Set correct parity settings in register interface based on PARITY setting */ -#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 -#if CONF_SERCOM_2_USART_PARITY == 0 -#define CONF_SERCOM_2_USART_PMODE 0 -#define CONF_SERCOM_2_USART_FORM 4 -#else -#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 -#define CONF_SERCOM_2_USART_FORM 5 -#endif -#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ -#if CONF_SERCOM_2_USART_PARITY == 0 -#define CONF_SERCOM_2_USART_PMODE 0 -#define CONF_SERCOM_2_USART_FORM 0 -#else -#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 -#define CONF_SERCOM_2_USART_FORM 1 -#endif -#endif - -// Calculate BAUD register value in UART mode -#if CONF_SERCOM_2_USART_SAMPR == 0 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 1 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 2 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 3 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 4 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#endif - -#include - -#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) -#endif - -#ifndef CONF_SERCOM_3_I2CM_ENABLE -#define CONF_SERCOM_3_I2CM_ENABLE 1 -#endif - -// Basic - -// I2C Bus clock speed (Hz) <1-400000> -// I2C Bus clock (SCL) speed measured in Hz -// i2c_master_baud_rate -#ifndef CONF_SERCOM_3_I2CM_BAUD -#define CONF_SERCOM_3_I2CM_BAUD 100000 -#endif - -// - -// Advanced -// i2c_master_advanced -#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0 -#endif - -// TRise (ns) <0-300> -// Determined by the bus impedance, check electric characteristics in the datasheet -// Standard Fast Mode: typical 215ns, max 300ns -// Fast Mode +: typical 60ns, max 100ns -// High Speed Mode: typical 20ns, max 40ns -// i2c_master_arch_trise - -#ifndef CONF_SERCOM_3_I2CM_TRISE -#define CONF_SERCOM_3_I2CM_TRISE 215 -#endif - -// Master SCL Low Extended Time-Out (MEXTTOEN) -// This enables the master SCL low extend time-out -// i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN -#define CONF_SERCOM_3_I2CM_MEXTTOEN 0 -#endif - -// Slave SCL Low Extend Time-Out (SEXTTOEN) -// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine -// i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN -#define CONF_SERCOM_3_I2CM_SEXTTOEN 0 -#endif - -// SCL Low Time-Out (LOWTOUT) -// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold -// i2c_master_arch_lowtout -#ifndef CONF_SERCOM_3_I2CM_LOWTOUT -#define CONF_SERCOM_3_I2CM_LOWTOUT 0 -#endif - -// Inactive Time-Out (INACTOUT) -// <0x0=>Disabled -// <0x1=>5-6 SCL cycle time-out(50-60us) -// <0x2=>10-11 SCL cycle time-out(100-110us) -// <0x3=>20-21 SCL cycle time-out(200-210us) -// Defines if inactivity time-out should be enabled, and how long the time-out should be -// i2c_master_arch_inactout -#ifndef CONF_SERCOM_3_I2CM_INACTOUT -#define CONF_SERCOM_3_I2CM_INACTOUT 0x0 -#endif - -// SDA Hold Time (SDAHOLD) -// <0=>Disabled -// <1=>50-100ns hold time -// <2=>300-600ns hold time -// <3=>400-800ns hold time -// Defines the SDA hold time with respect to the negative edge of SCL -// i2c_master_arch_sdahold -#ifndef CONF_SERCOM_3_I2CM_SDAHOLD -#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2 -#endif - -// Run in stand-by -// Determine if the module shall run in standby sleep mode -// i2c_master_arch_runstdby -#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY -#define CONF_SERCOM_3_I2CM_RUNSTDBY 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_3_I2CM_SPEED -#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode -#endif -#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300 -#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_3_I2CM_TRISE -#define CONF_SERCOM_3_I2CM_TRISE 215U -#endif - -// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) -// BAUD + BAUDLOW = -------------------------------------------------------------------- -// i2c_scl_freq -// BAUD: register value low [7:0] -// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \ - / 1000U)) \ - * 10U \ - + 5U) \ - / (CONF_SERCOM_3_I2CM_BAUD * 10U)) -#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE -#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2) -#warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1 -#warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_3_I2CM_BAUD_RATE 1 -#else -#define CONF_SERCOM_3_I2CM_BAUD_RATE \ - ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2)) -#endif -#endif - -// <<< end of configuration section >>> - -#endif // HPL_SERCOM_CONFIG_H +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// Baud rate <1-6250000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 115200 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_USART_INACK +#define CONF_SERCOM_2_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_DSNACK +#define CONF_SERCOM_2_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_2_USART_MAXITER +#define CONF_SERCOM_2_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_2_USART_GTIME +#define CONF_SERCOM_2_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_2_USART_RXINV 0x0 +#define CONF_SERCOM_2_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 4 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_3_I2CM_BAUD +#define CONF_SERCOM_3_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_3_I2CM_TRISE +#define CONF_SERCOM_3_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN +#define CONF_SERCOM_3_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN +#define CONF_SERCOM_3_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_3_I2CM_LOWTOUT +#define CONF_SERCOM_3_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_3_I2CM_INACTOUT +#define CONF_SERCOM_3_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_3_I2CM_SDAHOLD +#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY +#define CONF_SERCOM_3_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_3_I2CM_SPEED +#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_3_I2CM_TRISE +#define CONF_SERCOM_3_I2CM_TRISE 215U +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_3_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE +#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_3_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_3_I2CM_BAUD_RATE \ + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h index ae5921c..4becca5 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/hpl_tc_config.h @@ -1,180 +1,180 @@ -/* Auto-generated config file hpl_tc_config.h */ -#ifndef HPL_TC_CONFIG_H -#define HPL_TC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef CONF_TC0_ENABLE -#define CONF_TC0_ENABLE 1 -#endif - -#include "peripheral_clk_config.h" - -// Basic configuration - -// Prescaler -// <0x0=> No division -// <0x1=> Divide by 2 -// <0x2=> Divide by 4 -// <0x3=> Divide by 8 -// <0x4=> Divide by 16 -// <0x5=> Divide by 64 -// <0x6=> Divide by 256 -// <0x7=> Divide by 1024 -// This defines the prescaler value -// timer_prescaler -#ifndef CONF_TC0_PRESCALER -#define CONF_TC0_PRESCALER 0x3 -#endif - -// Length of one timer tick in uS <0-4294967295> -// timer_tick -#ifndef CONF_TC0_TIMER_TICK -#define CONF_TC0_TIMER_TICK 1000 -#endif -// - -// Advanced configuration -// timer_advanced_configuration -#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE -#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0 -#endif - -// Prescaler and Counter Synchronization Selection -// Reload or reset counter on next GCLK -// Reload or reset counter on next prescaler clock -// Reload or reset counter on next GCLK and reset prescaler counter -// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. -// tc_arch_presync -#ifndef CONF_TC0_PRESCSYNC -#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val -#endif - -// Run in standby -// Indicates whether the module will continue to run in standby sleep mode -// tc_arch_runstdby -#ifndef CONF_TC0_RUNSTDBY -#define CONF_TC0_RUNSTDBY 0 -#endif - -// Run in debug mode -// Indicates whether the module will run in debug mode -// tc_arch_dbgrun -#ifndef CONF_TC0_DBGRUN -#define CONF_TC0_DBGRUN 0 -#endif - -// Run on demand -// Run if requested by some other peripheral in the device -// tc_arch_ondemand -#ifndef CONF_TC0_ONDEMAND -#define CONF_TC0_ONDEMAND 0 -#endif - -// - -// Event control -// timer_event_control -#ifndef CONF_TC0_EVENT_CONTROL_ENABLE -#define CONF_TC0_EVENT_CONTROL_ENABLE 0 -#endif - -// Output Event On Match or Capture on Channel 0 -// Enable output of event on timer tick -// tc_arch_mceo0 -#ifndef CONF_TC0_MCEO0 -#define CONF_TC0_MCEO0 0 -#endif - -// Output Event On Match or Capture on Channel 1 -// Enable output of event on timer tick -// tc_arch_mceo1 -#ifndef CONF_TC0_MCEO1 -#define CONF_TC0_MCEO1 0 -#endif - -// Output Event On Timer Tick -// Enable output of event on timer tick -// tc_arch_ovfeo -#ifndef CONF_TC0_OVFEO -#define CONF_TC0_OVFEO 0 -#endif - -// Event Input -// Enable asynchronous input events -// tc_arch_tcei -#ifndef CONF_TC0_TCEI -#define CONF_TC0_TCEI 0 -#endif - -// Inverted Event Input -// Invert the asynchronous input events -// tc_arch_tcinv -#ifndef CONF_TC0_TCINV -#define CONF_TC0_TCINV 0 -#endif - -// Event action -// <0=> Event action disabled -// <1=> Start, restart or re-trigger TC on event -// <2=> Count on event -// <3=> Start on event -// <4=> Time stamp capture -// <5=> Period captured in CC0, pulse width in CC1 -// <6=> Period captured in CC1, pulse width in CC0 -// <7=> Pulse width capture -// Event which will be performed on an event -// tc_arch_evact -#ifndef CONF_TC0_EVACT -#define CONF_TC0_EVACT 0 -#endif -// - -// Default values which the driver needs in order to work correctly - -// Mode set to 32-bit -#ifndef CONF_TC0_MODE -#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val -#endif - -// CC 1 register set to 0 -#ifndef CONF_TC0_CC1 -#define CONF_TC0_CC1 0 -#endif - -#ifndef CONF_TC0_ALOCK -#define CONF_TC0_ALOCK 0 -#endif - -// Not used in 32-bit mode -#define CONF_TC0_PER 0 - -// Calculating correct top value based on requested tick interval. -#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER) - -// Prescaler set to 64 -#if CONF_TC0_PRESCALER > 0x4 -#undef CONF_TC0_PRESCALE -#define CONF_TC0_PRESCALE 64 -#endif - -// Prescaler set to 256 -#if CONF_TC0_PRESCALER > 0x5 -#undef CONF_TC0_PRESCALE -#define CONF_TC0_PRESCALE 256 -#endif - -// Prescaler set to 1024 -#if CONF_TC0_PRESCALER > 0x6 -#undef CONF_TC0_PRESCALE -#define CONF_TC0_PRESCALE 1024 -#endif - -#ifndef CONF_TC0_CC0 -#define CONF_TC0_CC0 \ - (uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE))) -#endif - -// <<< end of configuration section >>> - -#endif // HPL_TC_CONFIG_H +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +#include "peripheral_clk_config.h" + +// Basic configuration + +// Prescaler +// <0x0=> No division +// <0x1=> Divide by 2 +// <0x2=> Divide by 4 +// <0x3=> Divide by 8 +// <0x4=> Divide by 16 +// <0x5=> Divide by 64 +// <0x6=> Divide by 256 +// <0x7=> Divide by 1024 +// This defines the prescaler value +// timer_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0x3 +#endif + +// Length of one timer tick in uS <0-4294967295> +// timer_tick +#ifndef CONF_TC0_TIMER_TICK +#define CONF_TC0_TIMER_TICK 1000 +#endif +// + +// Advanced configuration +// timer_advanced_configuration +#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE +#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the module will continue to run in standby sleep mode +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// Run in debug mode +// Indicates whether the module will run in debug mode +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Run on demand +// Run if requested by some other peripheral in the device +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +// Default values which the driver needs in order to work correctly + +// Mode set to 32-bit +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val +#endif + +// CC 1 register set to 0 +#ifndef CONF_TC0_CC1 +#define CONF_TC0_CC1 0 +#endif + +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +// Not used in 32-bit mode +#define CONF_TC0_PER 0 + +// Calculating correct top value based on requested tick interval. +#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER) + +// Prescaler set to 64 +#if CONF_TC0_PRESCALER > 0x4 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 64 +#endif + +// Prescaler set to 256 +#if CONF_TC0_PRESCALER > 0x5 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 256 +#endif + +// Prescaler set to 1024 +#if CONF_TC0_PRESCALER > 0x6 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 1024 +#endif + +#ifndef CONF_TC0_CC0 +#define CONF_TC0_CC0 \ + (uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE))) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h index 74141bb..edd9735 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/Config/peripheral_clk_config.h @@ -1,257 +1,257 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// EIC Clock Source -// eic_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for EIC. -#ifndef CONF_GCLK_EIC_SRC -#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EIC_FREQUENCY - * \brief EIC's Clock frequency - */ -#ifndef CONF_GCLK_EIC_FREQUENCY -#define CONF_GCLK_EIC_FREQUENCY 119997440 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 119997440 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM2_CORE_SRC -#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM2_SLOW_SRC -#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY - * \brief SERCOM2's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY -#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440 -#endif - -/** - * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY - * \brief SERCOM2's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM3_CORE_SRC -#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM3_SLOW_SRC -#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY - * \brief SERCOM3's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY -#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440 -#endif - -/** - * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY - * \brief SERCOM3's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 -#endif - -// TC Clock Source -// tc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for TC. -#ifndef CONF_GCLK_TC0_SRC -#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_TC0_FREQUENCY - * \brief TC0's Clock frequency - */ -#ifndef CONF_GCLK_TC0_FREQUENCY -#define CONF_GCLK_TC0_FREQUENCY 119997440 -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EIC Clock Source +// eic_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for EIC. +#ifndef CONF_GCLK_EIC_SRC +#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EIC_FREQUENCY + * \brief EIC's Clock frequency + */ +#ifndef CONF_GCLK_EIC_FREQUENCY +#define CONF_GCLK_EIC_FREQUENCY 119997440 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 119997440 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 119997440 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 119997440 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c index 79f252a..9d0900d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.c @@ -1,9 +1,9 @@ -#include - -/** - * Initializes MCU, drivers and middleware in the project - **/ -void atmel_start_init(void) -{ - system_init(); -} +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h index 0de62f5..a035c6c 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start.h @@ -1,18 +1,18 @@ -#ifndef ATMEL_START_H_INCLUDED -#define ATMEL_START_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include "driver_init.h" - -/** - * Initializes MCU, drivers and middleware in the project - **/ -void atmel_start_init(void); - -#ifdef __cplusplus -} -#endif -#endif +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h index 48712d5..1344f6c 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/atmel_start_pins.h @@ -1,12 +1,12 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef ATMEL_START_PINS_H_INCLUDED -#define ATMEL_START_PINS_H_INCLUDED - - -#endif // ATMEL_START_PINS_H_INCLUDED +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c index 9bda34f..2ee900b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.c @@ -1,134 +1,134 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_init.h" -#include -#include -#include - -/*! The buffer size for USART */ -#define USART_0_BUFFER_SIZE 16 - -struct usart_async_descriptor USART_0; -struct timer_descriptor TIMER_0; - -static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE]; - -struct i2c_m_sync_desc I2C_0; - -void EXTERNAL_IRQ_0_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_mclk_set_APBAMASK_EIC_bit(MCLK); - - ext_irq_init(); -} - -/** - * \brief USART Clock initialization function - * - * Enables register interface and peripheral clock - */ -void USART_0_CLOCK_init() -{ - - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); -} - -/** - * \brief USART pinmux initialization function - * - * Set each required pin to USART functionality - */ -void USART_0_PORT_init() -{ - - gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); - - gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); -} - -/** - * \brief USART initialization function - * - * Enables USART peripheral, clocks and initializes USART driver - */ -void USART_0_init(void) -{ - USART_0_CLOCK_init(); - usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); - USART_0_PORT_init(); -} - -void I2C_0_PORT_init(void) -{ - - gpio_set_pin_pull_mode(PA22, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0); - - gpio_set_pin_pull_mode(PA23, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); -} - -void I2C_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); -} - -void I2C_0_init(void) -{ - I2C_0_CLOCK_init(); - i2c_m_sync_init(&I2C_0, SERCOM3); - I2C_0_PORT_init(); -} - -/** - * \brief Timer initialization function - * - * Enables Timer peripheral, clocks and initializes Timer driver - */ -static void TIMER_0_init(void) -{ - hri_mclk_set_APBAMASK_TC0_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - timer_init(&TIMER_0, TC0, _tc_get_timer()); -} - -void system_init(void) -{ - init_mcu(); - - EXTERNAL_IRQ_0_init(); - - USART_0_init(); - - I2C_0_init(); - - TIMER_0_init(); -} +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +/*! The buffer size for USART */ +#define USART_0_BUFFER_SIZE 16 + +struct usart_async_descriptor USART_0; +struct timer_descriptor TIMER_0; + +static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE]; + +struct i2c_m_sync_desc I2C_0; + +void EXTERNAL_IRQ_0_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBAMASK_EIC_bit(MCLK); + + ext_irq_init(); +} + +/** + * \brief USART Clock initialization function + * + * Enables register interface and peripheral clock + */ +void USART_0_CLOCK_init() +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); +} + +/** + * \brief USART pinmux initialization function + * + * Set each required pin to USART functionality + */ +void USART_0_PORT_init() +{ + + gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); + + gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); +} + +/** + * \brief USART initialization function + * + * Enables USART peripheral, clocks and initializes USART driver + */ +void USART_0_init(void) +{ + USART_0_CLOCK_init(); + usart_async_init(&USART_0, SERCOM2, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); + USART_0_PORT_init(); +} + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA22, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0); + + gpio_set_pin_pull_mode(PA23, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM3); + I2C_0_PORT_init(); +} + +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) +{ + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&TIMER_0, TC0, _tc_get_timer()); +} + +void system_init(void) +{ + init_mcu(); + + EXTERNAL_IRQ_0_init(); + + USART_0_init(); + + I2C_0_init(); + + TIMER_0_init(); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h index 16d4f9f..b82abbb 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/driver_init.h @@ -1,54 +1,54 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_INIT_INCLUDED -#define DRIVER_INIT_INCLUDED - -#include "atmel_start_pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include -#include - -extern struct usart_async_descriptor USART_0; - -extern struct i2c_m_sync_desc I2C_0; -extern struct timer_descriptor TIMER_0; - -void USART_0_PORT_init(void); -void USART_0_CLOCK_init(void); -void USART_0_init(void); - -void I2C_0_CLOCK_init(void); -void I2C_0_init(void); -void I2C_0_PORT_init(void); - -/** - * \brief Perform system initialization, initialize pins and clocks for - * peripherals - */ -void system_init(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_INIT_INCLUDED +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +extern struct usart_async_descriptor USART_0; + +extern struct i2c_m_sync_desc I2C_0; +extern struct timer_descriptor TIMER_0; + +void USART_0_PORT_init(void); +void USART_0_CLOCK_init(void); +void USART_0_init(void); + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c index 7cf9ca8..4218cbe 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.c @@ -1,84 +1,84 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_examples.h" -#include "driver_init.h" -#include "utils.h" - -/** - * Example of using EXTERNAL_IRQ_0 - */ -void EXTERNAL_IRQ_0_example(void) -{ -} - -/** - * Example of using USART_0 to write "Hello World" using the IO abstraction. - * - * Since the driver is asynchronous we need to use statically allocated memory for string - * because driver initiates transfer and then returns before the transmission is completed. - * - * Once transfer has been completed the tx_cb function will be called. - */ - -static uint8_t example_USART_0[12] = "Hello World!"; - -static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr) -{ - /* Transfer completed */ -} - -void USART_0_example(void) -{ - struct io_descriptor *io; - - usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0); - /*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb); - usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/ - usart_async_get_io_descriptor(&USART_0, &io); - usart_async_enable(&USART_0); - - io_write(io, example_USART_0, 12); -} - -void I2C_0_example(void) -{ - struct io_descriptor *I2C_0_io; - - i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); - i2c_m_sync_enable(&I2C_0); - i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); - io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); -} - -static struct timer_task TIMER_0_task1, TIMER_0_task2; - -/** - * Example of using TIMER_0. - */ -static void TIMER_0_task1_cb(const struct timer_task *const timer_task) -{ -} - -static void TIMER_0_task2_cb(const struct timer_task *const timer_task) -{ -} - -void TIMER_0_example(void) -{ - TIMER_0_task1.interval = 100; - TIMER_0_task1.cb = TIMER_0_task1_cb; - TIMER_0_task1.mode = TIMER_TASK_REPEAT; - TIMER_0_task2.interval = 200; - TIMER_0_task2.cb = TIMER_0_task2_cb; - TIMER_0_task2.mode = TIMER_TASK_REPEAT; - - timer_add_task(&TIMER_0, &TIMER_0_task1); - timer_add_task(&TIMER_0, &TIMER_0_task2); - timer_start(&TIMER_0); -} +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using EXTERNAL_IRQ_0 + */ +void EXTERNAL_IRQ_0_example(void) +{ +} + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + * + * Since the driver is asynchronous we need to use statically allocated memory for string + * because driver initiates transfer and then returns before the transmission is completed. + * + * Once transfer has been completed the tx_cb function will be called. + */ + +static uint8_t example_USART_0[12] = "Hello World!"; + +static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr) +{ + /* Transfer completed */ +} + +void USART_0_example(void) +{ + struct io_descriptor *io; + + usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0); + /*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb); + usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/ + usart_async_get_io_descriptor(&USART_0, &io); + usart_async_enable(&USART_0); + + io_write(io, example_USART_0, 12); +} + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +static struct timer_task TIMER_0_task1, TIMER_0_task2; + +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h index 8e0cea1..bebd724 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/examples/driver_examples.h @@ -1,26 +1,26 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_EXAMPLES_H_INCLUDED -#define DRIVER_EXAMPLES_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -void EXTERNAL_IRQ_0_example(void); - -void USART_0_example(void); - -void I2C_0_example(void); - -void TIMER_0_example(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_EXAMPLES_H_INCLUDED +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void EXTERNAL_IRQ_0_example(void); + +void USART_0_example(void); + +void I2C_0_example(void); + +void TIMER_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/ext_irq.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/ext_irq.rst index 7dcdc7c..cd3a3e9 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/ext_irq.rst +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/ext_irq.rst @@ -1,39 +1,39 @@ -============== -EXT IRQ driver -============== - -The External Interrupt driver allows external pins to be -configured as interrupt lines. Each interrupt line can be -individually masked and can generate an interrupt on rising, -falling or both edges, or on high or low levels. Some of -external pin can also be configured to wake up the device -from sleep modes where all clocks have been disabled. -External pins can also generate an event. - -Features --------- -* Initialization and de-initialization -* Enabling and disabling -* Detect external pins interrupt - -Applications ------------- -* Generate an interrupt on rising, falling or both edges, - or on high or low levels. - -Dependencies ------------- -* GPIO hardware - -Concurrency ------------ -N/A - -Limitations ------------ -N/A - -Knows issues and workarounds ----------------------------- -N/A - +============== +EXT IRQ driver +============== + +The External Interrupt driver allows external pins to be +configured as interrupt lines. Each interrupt line can be +individually masked and can generate an interrupt on rising, +falling or both edges, or on high or low levels. Some of +external pin can also be configured to wake up the device +from sleep modes where all clocks have been disabled. +External pins can also generate an event. + +Features +-------- +* Initialization and de-initialization +* Enabling and disabling +* Detect external pins interrupt + +Applications +------------ +* Generate an interrupt on rising, falling or both edges, + or on high or low levels. + +Dependencies +------------ +* GPIO hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/i2c_master_sync.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/i2c_master_sync.rst index 77b4f6e..806606f 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/i2c_master_sync.rst +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/i2c_master_sync.rst @@ -1,87 +1,87 @@ -============================= -I2C Master synchronous driver -============================= - -I2C (Inter-Integrated Circuit) is a two wire serial interface usually used -for on-board low-speed bi-directional communication between controllers and -peripherals. The master device is responsible for initiating and controlling -all transfers on the I2C bus. Only one master device can be active on the I2C -bus at the time, but the master role can be transferred between devices on the -same I2C bus. I2C uses only two bidirectional open-drain lines, usually -designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up -resistors. - -The stop condition is automatically controlled by the driver if the I/O write and -read functions are used, but can be manually controlled by using the -i2c_m_sync_transfer function. - -Often a master accesses different information in the slave by accessing -different registers in the slave. This is done by first sending a message to -the target slave containing the register address, followed by a repeated start -condition (no stop condition between) ending with transferring register data. -This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read -function, but limited to 8-bit register addresses. - -I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in -Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to -stick within the SCL clock frequency range supported by the selected mode. -The requested SCL clock frequency is not validated by the -i2c_m_sync_set_baudrate function against the selected I2C mode. - -Features --------- - - * I2C Master support - * Initialization and de-initialization - * Enabling and disabling - * Run-time bus speed configuration - * Write and read I2C messages - * Slave register access functions (limited to 8-bit address) - * Manual or automatic stop condition generation - * 10- and 7- bit addressing - * I2C Modes supported - +----------------------+-------------------+ - |* Standard/Fast mode | (SCL: 1 - 400kHz) | - +----------------------+-------------------+ - |* Fastmode+ | (SCL: 1 - 1000kHz)| - +----------------------+-------------------+ - |* Highspeed mode | (SCL: 1 - 3400kHz)| - +----------------------+-------------------+ - -Applications ------------- - -* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals -* Data communication between micro controllers -* Controlling displays - -Dependencies ------------- - -* I2C Master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -General -^^^^^^^ - - * System Managmenet Bus (SMBus) not supported. - * Power Management Bus (PMBus) not supported. - -Clock considerations -^^^^^^^^^^^^^^^^^^^^ - -The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. - -Known issues and workarounds ----------------------------- - -N/A - - +============================= +I2C Master synchronous driver +============================= + +I2C (Inter-Integrated Circuit) is a two wire serial interface usually used +for on-board low-speed bi-directional communication between controllers and +peripherals. The master device is responsible for initiating and controlling +all transfers on the I2C bus. Only one master device can be active on the I2C +bus at the time, but the master role can be transferred between devices on the +same I2C bus. I2C uses only two bidirectional open-drain lines, usually +designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up +resistors. + +The stop condition is automatically controlled by the driver if the I/O write and +read functions are used, but can be manually controlled by using the +i2c_m_sync_transfer function. + +Often a master accesses different information in the slave by accessing +different registers in the slave. This is done by first sending a message to +the target slave containing the register address, followed by a repeated start +condition (no stop condition between) ending with transferring register data. +This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read +function, but limited to 8-bit register addresses. + +I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in +Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to +stick within the SCL clock frequency range supported by the selected mode. +The requested SCL clock frequency is not validated by the +i2c_m_sync_set_baudrate function against the selected I2C mode. + +Features +-------- + + * I2C Master support + * Initialization and de-initialization + * Enabling and disabling + * Run-time bus speed configuration + * Write and read I2C messages + * Slave register access functions (limited to 8-bit address) + * Manual or automatic stop condition generation + * 10- and 7- bit addressing + * I2C Modes supported + +----------------------+-------------------+ + |* Standard/Fast mode | (SCL: 1 - 400kHz) | + +----------------------+-------------------+ + |* Fastmode+ | (SCL: 1 - 1000kHz)| + +----------------------+-------------------+ + |* Highspeed mode | (SCL: 1 - 3400kHz)| + +----------------------+-------------------+ + +Applications +------------ + +* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals +* Data communication between micro controllers +* Controlling displays + +Dependencies +------------ + +* I2C Master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +General +^^^^^^^ + + * System Managmenet Bus (SMBus) not supported. + * Power Management Bus (PMBus) not supported. + +Clock considerations +^^^^^^^^^^^^^^^^^^^^ + +The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. + +Known issues and workarounds +---------------------------- + +N/A + + diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/timer.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/timer.rst index c5ca63d..2b3b63a 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/timer.rst +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/timer.rst @@ -1,52 +1,52 @@ -============================ -The Timer driver (bare-bone) -============================ - -The Timer driver provides means for delayed and periodical function invocation. - -A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has -been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a -configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically -changes execution delays and periods for all tasks in the timers task queue. - -A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue -and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on -the period set in the task configuration. -In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to -reuse the memory of expired task in the callback. - -Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. - -Features --------- -* Initialization and de-initialization -* Starting and stopping -* Timer tasks - periodical invocation of functions -* Changing and obtaining of the period of a timer - -Applications ------------- -* Delayed and periodical function execution for middle-ware stacks and applications. - -Dependencies ------------- -* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. - -Concurrency ------------ -The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during -the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed -until the task adding or removing is complete. - -The task queue is not protected from the access by interrupts not used by the driver. Due to this -it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes -the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. - -Limitations ------------ -* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. -* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. - -Knows issues and workarounds ----------------------------- -Not applicable +============================ +The Timer driver (bare-bone) +============================ + +The Timer driver provides means for delayed and periodical function invocation. + +A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has +been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a +configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically +changes execution delays and periods for all tasks in the timers task queue. + +A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue +and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on +the period set in the task configuration. +In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to +reuse the memory of expired task in the callback. + +Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. + +Features +-------- +* Initialization and de-initialization +* Starting and stopping +* Timer tasks - periodical invocation of functions +* Changing and obtaining of the period of a timer + +Applications +------------ +* Delayed and periodical function execution for middle-ware stacks and applications. + +Dependencies +------------ +* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. + +Concurrency +----------- +The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during +the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed +until the task adding or removing is complete. + +The task queue is not protected from the access by interrupts not used by the driver. Due to this +it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes +the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. + +Limitations +----------- +* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. +* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. + +Knows issues and workarounds +---------------------------- +Not applicable diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst index 6bf4a23..aeba074 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/documentation/usart_async.rst @@ -1,72 +1,72 @@ -The USART Asynchronous Driver -============================= - -The universal synchronous and asynchronous receiver and transmitter -(USART) is usually used to transfer data from one device to the other. - -The USART driver use a ring buffer to store received data. When the USART -raise the data received interrupt, this data will be stored in the ring buffer -at the next free location. When the ring buffer is full, the next reception -will overwrite the oldest data stored in the ring buffer. There is one -USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro -is called SERCOM0_USART_BUFFER_SIZE. - -On the other hand, when sending data over USART, the data is not copied to an -internal buffer, but the data buffer supplied by the user is used. The callback -will only be generated at the end of the buffer and not for each byte. - -User can set action for flow control pins by function usart_set_flow_control, -if the flow control is enabled. All the available states are defined in union -usart_flow_control_state. - -Note that user can set state of flow control pins only if automatic support of -the flow control is not supported by the hardware. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * UART or USRT communication mode - * Character size - * Data order - * Flow control -* Data transfer: transmission, reception -* Notifications about transfer done or error case via callbacks -* Status information with busy state and transfer count - -Applications ------------- - -They are commonly used in a terminal application or low-speed communication -between devices. - -Dependencies ------------- - -USART capable hardware, with interrupt on each character is sent or -received. - -Concurrency ------------ - -Write buffer should not be changed while data is being sent. - - -Limitations ------------ - -* The driver does not support 9-bit character size. -* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. - And the SCK pin can't be set directly. Application can use a GCLK output PIN - to generate SCK. For example to communicate with a SMARTCARD with ISO7816 - (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be - config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. - -Known issues and workarounds ----------------------------- - -N/A +The USART Asynchronous Driver +============================= + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +The USART driver use a ring buffer to store received data. When the USART +raise the data received interrupt, this data will be stored in the ring buffer +at the next free location. When the ring buffer is full, the next reception +will overwrite the oldest data stored in the ring buffer. There is one +USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro +is called SERCOM0_USART_BUFFER_SIZE. + +On the other hand, when sending data over USART, the data is not copied to an +internal buffer, but the data buffer supplied by the user is used. The callback +will only be generated at the end of the buffer and not for each byte. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception +* Notifications about transfer done or error case via callbacks +* Status information with busy state and transfer count + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware, with interrupt on each character is sent or +received. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_atomic.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_atomic.h index 82151fc..cba7d65 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_atomic.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_atomic.h @@ -1,120 +1,120 @@ -/** - * \file - * - * \brief Critical sections related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ATOMIC_H_INCLUDED -#define _HAL_ATOMIC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_atomic - * - *@{ - */ - -/** - * \brief Type for the register holding global interrupt enable flag - */ -typedef uint32_t hal_atomic_t; - -/** - * \brief Helper macro for entering critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_enterCritical() function to enter critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_ENTER() \ - { \ - volatile hal_atomic_t __atomic; \ - atomic_enter_critical(&__atomic); - -/** - * \brief Helper macro for leaving critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_leaveCritical() function to leave critical - * sections. No semicolon is required after the macro. - */ -#define CRITICAL_SECTION_LEAVE() \ - atomic_leave_critical(&__atomic); \ - } - -/** - * \brief Disable interrupts, enter critical section - * - * Disables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[out] atomic The pointer to a variable to store the value of global - * interrupt enable flag - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Exit atomic section - * - * Enables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[in] atomic The pointer to a variable, which stores the latest stored - * value of the global interrupt enable flag - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t atomic_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_ATOMIC_H_INCLUDED */ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h index 071486b..68aa3f8 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_cache.h @@ -1,96 +1,96 @@ -/** - * \file - * - * \brief HAL cache functionality implementation. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#ifndef HAL_CACHE_H_ -#define HAL_CACHE_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Enable cache module - * - * \param[in] pointer pointing to the starting address of cache module - * - * \return status of operation - */ -int32_t cache_enable(const void *hw); - -/** - * \brief Disable cache module - * - * \param[in] pointer pointing to the starting address of cache module - * - * \return status of operation - */ -int32_t cache_disable(const void *hw); - -/** - * \brief Initialize cache module - * - * This function initialize cache module configuration. - * - * \return status of operation - */ -int32_t cache_init(void); - -/** - * \brief Configure cache module - * - * \param[in] pointer pointing to the starting address of cache module - * \param[in] cache configuration structure pointer - * - * \return status of operation - */ -int32_t cache_configure(const void *hw, struct _cache_cfg *cache); - -/** - * \brief Invalidate entire cache entries - * - * \param[in] pointer pointing to the starting address of cache module - * - * \return status of operation - */ -int32_t cache_invalidate_all(const void *hw); - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_CACHE_H_ */ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HAL_CACHE_H_ +#define HAL_CACHE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_enable(const void *hw); + +/** + * \brief Disable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_disable(const void *hw); + +/** + * \brief Initialize cache module + * + * This function initialize cache module configuration. + * + * \return status of operation + */ +int32_t cache_init(void); + +/** + * \brief Configure cache module + * + * \param[in] pointer pointing to the starting address of cache module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache); + +/** + * \brief Invalidate entire cache entries + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_invalidate_all(const void *hw); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CACHE_H_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h index 9d4aa5c..9504de0 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_delay.h @@ -1,89 +1,89 @@ -/** - * \file - * - * \brief HAL delay related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#ifndef _HAL_DELAY_H_INCLUDED -#define _HAL_DELAY_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_delay Delay Driver - * - *@{ - */ - -/** - * \brief Initialize Delay driver - * - * \param[in] hw The pointer to hardware instance - */ -void delay_init(void *const hw); - -/** - * \brief Perform delay in us - * - * This function performs delay for the given amount of microseconds. - * - * \param[in] us The amount delay in us - */ -void delay_us(const uint16_t us); - -/** - * \brief Perform delay in ms - * - * This function performs delay for the given amount of milliseconds. - * - * \param[in] ms The amount delay in ms - */ -void delay_ms(const uint16_t ms); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t delay_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_DELAY_H_INCLUDED */ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_ext_irq.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_ext_irq.h index a7c2600..c1c3419 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_ext_irq.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_ext_irq.h @@ -1,118 +1,118 @@ -/** - * \file - * - * \brief External interrupt functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_EXT_IRQ_H_INCLUDED -#define _HAL_EXT_IRQ_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_ext_irq - * - * @{ - */ - -/** - * \brief External IRQ callback type - */ -typedef void (*ext_irq_cb_t)(void); - -/** - * \brief Initialize external IRQ component, if any - * - * \return Initialization status. - * \retval -1 External IRQ module is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t ext_irq_init(void); - -/** - * \brief Deinitialize external IRQ, if any - * - * \return De-initialization status. - * \retval -1 External IRQ module is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t ext_irq_deinit(void); - -/** - * \brief Register callback for the given external interrupt - * - * \param[in] pin Pin to enable external IRQ on - * \param[in] cb Callback function - * - * \return Registration status. - * \retval -1 Passed parameters were invalid - * \retval 0 The callback registration is completed successfully - */ -int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb); - -/** - * \brief Enable external IRQ - * - * \param[in] pin Pin to enable external IRQ on - * - * \return Enabling status. - * \retval -1 Passed parameters were invalid - * \retval 0 The enabling is completed successfully - */ -int32_t ext_irq_enable(const uint32_t pin); - -/** - * \brief Disable external IRQ - * - * \param[in] pin Pin to enable external IRQ on - * - * \return Disabling status. - * \retval -1 Passed parameters were invalid - * \retval 0 The disabling is completed successfully - */ -int32_t ext_irq_disable(const uint32_t pin); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t ext_irq_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_EXT_IRQ_H_INCLUDED */ +/** + * \file + * + * \brief External interrupt functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_EXT_IRQ_H_INCLUDED +#define _HAL_EXT_IRQ_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_ext_irq + * + * @{ + */ + +/** + * \brief External IRQ callback type + */ +typedef void (*ext_irq_cb_t)(void); + +/** + * \brief Initialize external IRQ component, if any + * + * \return Initialization status. + * \retval -1 External IRQ module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t ext_irq_init(void); + +/** + * \brief Deinitialize external IRQ, if any + * + * \return De-initialization status. + * \retval -1 External IRQ module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t ext_irq_deinit(void); + +/** + * \brief Register callback for the given external interrupt + * + * \param[in] pin Pin to enable external IRQ on + * \param[in] cb Callback function + * + * \return Registration status. + * \retval -1 Passed parameters were invalid + * \retval 0 The callback registration is completed successfully + */ +int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb); + +/** + * \brief Enable external IRQ + * + * \param[in] pin Pin to enable external IRQ on + * + * \return Enabling status. + * \retval -1 Passed parameters were invalid + * \retval 0 The enabling is completed successfully + */ +int32_t ext_irq_enable(const uint32_t pin); + +/** + * \brief Disable external IRQ + * + * \param[in] pin Pin to enable external IRQ on + * + * \return Disabling status. + * \retval -1 Passed parameters were invalid + * \retval 0 The disabling is completed successfully + */ +int32_t ext_irq_disable(const uint32_t pin); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t ext_irq_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_EXT_IRQ_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h index fbfa2d4..ee9fa79 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_gpio.h @@ -1,201 +1,201 @@ -/** - * \file - * - * \brief Port - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ -#ifndef _HAL_GPIO_INCLUDED_ -#define _HAL_GPIO_INCLUDED_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Set gpio pull mode - * - * Set pin pull mode, non existing pull modes throws an fatal assert - * - * \param[in] pin The pin number for device - * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor - * GPIO_PULL_UP = Pull pin high with internal resistor - * GPIO_PULL_OFF = Disable pin pull mode - */ -static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) -{ - _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); -} - -/** - * \brief Set pin function - * - * Select which function a pin will be used for - * - * \param[in] pin The pin number for device - * \param[in] function The pin function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) -{ - _gpio_set_pin_function(pin, function); -} - -/** - * \brief Set port data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - _gpio_set_direction(port, mask, direction); -} - -/** - * \brief Set gpio data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] pin The pin number for device - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) -{ - _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); -} - -/** - * \brief Set port level - * - * Sets output level on the pins defined by the bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply port level to the corresponding - * pin - * \param[in] level true = Pin levels set to "high" state - * false = Pin levels set to "low" state - */ -static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - _gpio_set_level(port, mask, level); -} - -/** - * \brief Set gpio level - * - * Sets output level on a pin - * - * \param[in] pin The pin number for device - * \param[in] level true = Pin level set to "high" state - * false = Pin level set to "low" state - */ -static inline void gpio_set_pin_level(const uint8_t pin, const bool level) -{ - _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); -} - -/** - * \brief Toggle out level on pins - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding - * pin - */ -static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) -{ - _gpio_toggle_level(port, mask); -} - -/** - * \brief Toggle output level on pin - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] pin The pin number for device - */ -static inline void gpio_toggle_pin_level(const uint8_t pin) -{ - _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); -} - -/** - * \brief Get input level on pins - * - * Read the input level on pins connected to a port - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t gpio_get_port_level(const enum gpio_port port) -{ - return _gpio_get_level(port); -} - -/** - * \brief Get level on pin - * - * Reads the level on pins connected to a port - * - * \param[in] pin The pin number for device - */ -static inline bool gpio_get_pin_level(const uint8_t pin) -{ - return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); -} -/** - * \brief Get current driver version - */ -uint32_t gpio_get_version(void); - -#ifdef __cplusplus -} -#endif - -#endif +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h index 24afd63..24acd92 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_i2c_m_sync.h @@ -1,244 +1,244 @@ -/** - * \file - * - * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_I2C_M_SYNC_H_INCLUDED -#define _HAL_I2C_M_SYNC_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_i2c_master_sync - * - * @{ - */ - -#define I2C_M_MAX_RETRY 1 - -/** - * \brief I2C descriptor structure, embed i2c_device & i2c_interface - */ -struct i2c_m_sync_desc { - struct _i2c_m_sync_device device; - struct io_descriptor io; - uint16_t slave_addr; -}; - -/** - * \brief Initialize synchronous I2C interface - * - * This function initializes the given I/O descriptor to be used as a - * synchronous I2C interface descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - * \retval -1 The passed parameters were invalid or the interface is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); - -/** - * \brief Deinitialize I2C interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Uninitialization status. - * \retval -1 The passed parameters were invalid or the interface is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); - -/** - * \brief Set the slave device address - * - * This function sets the next transfer target slave I2C device address. - * It takes no effect to any already started access. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] addr The slave address to access - * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN - * - * \return Masked slave address. The mask is a maximum 10-bit address, and 10th - * bit is set if a 10-bit address is used - */ -int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); - -/** - * \brief Set baudrate - * - * This function sets the I2C device to the specified baudrate. - * It only takes effect when the hardware is disabled. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] clkrate Unused parameter. Should always be 0 - * \param[in] baudrate The baudrate value set to master - * - * \return Whether successfully set the baudrate - * \retval -1 The passed parameters were invalid or the device is already enabled - * \retval 0 The baudrate set is completed successfully - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Sync version of enable hardware - * - * This function enables the I2C device, and then waits for this enabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully enable the device - * \retval -1 The passed parameters were invalid or the device enable failed - * \retval 0 The hardware enabling is completed successfully - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of disable hardware - * - * This function disables the I2C device and then waits for this disabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully disable the device - * \retval -1 The passed parameters were invalid or the device disable failed - * \retval 0 The hardware disabling is completed successfully - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of write command to I2C slave - * - * This function will write the value to a specified register in the I2C slave device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C slave device - * \param[in] buffer The buffer holding data to write to the I2C slave device - * \param[in] length The length (in bytes) to write to the I2C slave device - * - * \return Whether successfully write to the device - * \retval <0 The passed parameters were invalid or write fail - * \retval 0 Writing to register is completed successfully - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of read register value from I2C slave - * - * This function will read a byte value from a specified register in the I2C slave device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C slave device - * \param[in] buffer The buffer to hold the read data from the I2C slave device - * \param[in] length The length (in bytes) to read from the I2C slave device - * - * \return Whether successfully read from the device - * \retval <0 The passed parameters were invalid or read fail - * \retval 0 Reading from register is completed successfully - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of transfer message to/from the I2C slave - * - * This function will transfer a message between the I2C slave and the master. This function will wait for the operation - * to be done. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] msg An i2c_m_msg struct - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); - -/** - * \brief Sync version of send stop condition on the i2c bus - * - * This function will create a stop condition on the i2c bus to release the bus - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); - -/** - * \brief Return I/O descriptor for this I2C instance - * - * This function will return a I/O instance for this I2C driver instance - * - * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C - * \param[in] io_descriptor A pointer to an I/O descriptor pointer type - * - * \return Error code - * \retval 0 No error detected - * \retval <0 Error code - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t i2c_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_master_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t slave_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the slave device address + * + * This function sets the next transfer target slave I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The slave address to access + * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked slave address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to master + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C slave + * + * This function will write the value to a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer holding data to write to the I2C slave device + * \param[in] length The length (in bytes) to write to the I2C slave device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C slave + * + * This function will read a byte value from a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer to hold the read data from the I2C slave device + * \param[in] length The length (in bytes) to read from the I2C slave device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C slave + * + * This function will transfer a message between the I2C slave and the master. This function will wait for the operation + * to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_init.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_init.h index d7bc6fe..ce4be78 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_init.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_init.h @@ -1,72 +1,72 @@ -/** - * \file - * - * \brief HAL initialization related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_INIT_H_INCLUDED -#define _HAL_INIT_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_init Init Driver - * - *@{ - */ - -/** - * \brief Initialize the hardware abstraction layer - * - * This function calls the various initialization functions. - * Currently the following initialization functions are supported: - * - System clock initialization - */ -static inline void init_mcu(void) -{ - _init_chip(); -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t init_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_INIT_H_INCLUDED */ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_io.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_io.h index f50401d..1ae9449 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_io.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_io.h @@ -1,110 +1,110 @@ -/** - * \file - * - * \brief I/O related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_IO_INCLUDED -#define _HAL_IO_INCLUDED - -/** - * \addtogroup doc_driver_hal_helper_io I/O Driver - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I/O descriptor - * - * The I/O descriptor forward declaration. - */ -struct io_descriptor; - -/** - * \brief I/O write function pointer type - */ -typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read function pointer type - */ -typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O descriptor - */ -struct io_descriptor { - io_write_t write; /*! The write function pointer. */ - io_read_t read; /*! The read function pointer. */ -}; - -/** - * \brief I/O write interface - * - * This function writes up to \p length of bytes to a given I/O descriptor. - * It returns the number of bytes actually write. - * - * \param[in] descr An I/O descriptor to write - * \param[in] buf The buffer pointer to story the write data - * \param[in] length The number of bytes to write - * - * \return The number of bytes written - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read interface - * - * This function reads up to \p length bytes from a given I/O descriptor, and - * stores it in the buffer pointed to by \p buf. It returns the number of bytes - * actually read. - * - * \param[in] descr An I/O descriptor to read - * \param[in] buf The buffer pointer to story the read data - * \param[in] length The number of bytes to read - * - * \return The number of bytes actually read. This number can be less than the - * requested length. E.g., in a driver that uses ring buffer for - * reception, it may depend on the availability of data in the - * ring buffer. - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_IO_INCLUDED */ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_sleep.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_sleep.h index b90ef6a..e577886 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_sleep.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_sleep.h @@ -1,74 +1,74 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SLEEP_H_INCLUDED -#define _HAL_SLEEP_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_sleep - * - *@{ - */ - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t sleep_get_version(void); -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_SLEEP_H_INCLUDED */ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_timer.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_timer.h index 43a1ff4..c17f979 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_timer.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_timer.h @@ -1,206 +1,206 @@ -/** - * \file - * - * \brief Timer task functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_TIMER_H_INCLUDED -#define _HAL_TIMER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_timer - * - * @{ - */ - -/** - * \brief Timer mode type - */ -enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; - -/** - * \brief Timer task descriptor - * - * The timer task descriptor forward declaration. - */ -struct timer_task; - -/** - * \brief Timer task callback function type - */ -typedef void (*timer_cb_t)(const struct timer_task *const timer_task); - -/** - * \brief Timer task structure - */ -struct timer_task { - struct list_element elem; /*! List element. */ - uint32_t time_label; /*! Absolute timer start time. */ - - uint32_t interval; /*! Number of timer ticks before calling the task. */ - timer_cb_t cb; /*! Function pointer to the task. */ - enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ -}; - -/** - * \brief Timer structure - */ -struct timer_descriptor { - struct _timer_device device; - uint32_t time; - struct list_descriptor tasks; /*! Timer tasks list. */ - volatile uint8_t flags; -}; - -/** - * \brief Initialize timer - * - * This function initializes the given timer. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr A timer descriptor to initialize - * \param[in] hw The pointer to the hardware instance - * \param[in] func The pointer to a set of function pointers - * - * \return Initialization status. - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); - -/** - * \brief Deinitialize timer - * - * This function deinitializes the given timer. - * It checks if the given hardware is initialized and if the given hardware is - * permitted to be deinitialized. - * - * \param[in] descr A timer descriptor to deinitialize - * - * \return De-initialization status. - */ -int32_t timer_deinit(struct timer_descriptor *const descr); - -/** - * \brief Start timer - * - * This function starts the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to start - * - * \return Timer starting status. - */ -int32_t timer_start(struct timer_descriptor *const descr); - -/** - * \brief Stop timer - * - * This function stops the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * - * \return Timer stopping status. - */ -int32_t timer_stop(struct timer_descriptor *const descr); - -/** - * \brief Set amount of clock cycles per timer tick - * - * This function sets the amount of clock cycles per timer tick for the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * \param[in] clock_cycles The amount of clock cycles per tick to set - * - * \return Setting clock cycles amount status. - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); - -/** - * \brief Retrieve the amount of clock cycles in a tick - * - * This function retrieves how many clock cycles there are in a single timer tick. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to convert ticks to - * clock cycles - * \param[out] cycles The amount of clock cycles - * - * \return The status of clock cycles retrieving. - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); - -/** - * \brief Add timer task - * - * This function adds the given timer task to the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to add task to - * \param[in] task A task to add - * - * \return Timer's task adding status. - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); - -/** - * \brief Remove timer task - * - * This function removes the given timer task from the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to remove task from - * \param[in] task A task to remove - * - * \return Timer's task removing status. - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t timer_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_TIMER_H_INCLUDED */ +/** + * \file + * + * \brief Timer task functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_TIMER_H_INCLUDED +#define _HAL_TIMER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_timer + * + * @{ + */ + +/** + * \brief Timer mode type + */ +enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; + +/** + * \brief Timer task descriptor + * + * The timer task descriptor forward declaration. + */ +struct timer_task; + +/** + * \brief Timer task callback function type + */ +typedef void (*timer_cb_t)(const struct timer_task *const timer_task); + +/** + * \brief Timer task structure + */ +struct timer_task { + struct list_element elem; /*! List element. */ + uint32_t time_label; /*! Absolute timer start time. */ + + uint32_t interval; /*! Number of timer ticks before calling the task. */ + timer_cb_t cb; /*! Function pointer to the task. */ + enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ +}; + +/** + * \brief Timer structure + */ +struct timer_descriptor { + struct _timer_device device; + uint32_t time; + struct list_descriptor tasks; /*! Timer tasks list. */ + volatile uint8_t flags; +}; + +/** + * \brief Initialize timer + * + * This function initializes the given timer. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A timer descriptor to initialize + * \param[in] hw The pointer to the hardware instance + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); + +/** + * \brief Deinitialize timer + * + * This function deinitializes the given timer. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr A timer descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t timer_deinit(struct timer_descriptor *const descr); + +/** + * \brief Start timer + * + * This function starts the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to start + * + * \return Timer starting status. + */ +int32_t timer_start(struct timer_descriptor *const descr); + +/** + * \brief Stop timer + * + * This function stops the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * + * \return Timer stopping status. + */ +int32_t timer_stop(struct timer_descriptor *const descr); + +/** + * \brief Set amount of clock cycles per timer tick + * + * This function sets the amount of clock cycles per timer tick for the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * \param[in] clock_cycles The amount of clock cycles per tick to set + * + * \return Setting clock cycles amount status. + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); + +/** + * \brief Retrieve the amount of clock cycles in a tick + * + * This function retrieves how many clock cycles there are in a single timer tick. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to convert ticks to + * clock cycles + * \param[out] cycles The amount of clock cycles + * + * \return The status of clock cycles retrieving. + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); + +/** + * \brief Add timer task + * + * This function adds the given timer task to the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to add task to + * \param[in] task A task to add + * + * \return Timer's task adding status. + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); + +/** + * \brief Remove timer task + * + * This function removes the given timer task from the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to remove task from + * \param[in] task A task to remove + * + * \return Timer's task removing status. + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t timer_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h index 3a6de39..d3e0740 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hal_usart_async.h @@ -1,339 +1,339 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_USART_ASYNC_H_INCLUDED -#define _HAL_USART_ASYNC_H_INCLUDED - -#include "hal_io.h" -#include -#include - -/** - * \addtogroup doc_driver_hal_usart_async - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART descriptor - * - * The USART descriptor forward declaration. - */ -struct usart_async_descriptor; - -/** - * \brief USART callback type - */ -typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr); - -/** - * \brief USART callback types - */ -enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB }; - -/** - * \brief USART callbacks - */ -struct usart_async_callbacks { - usart_cb_t tx_done; - usart_cb_t rx_done; - usart_cb_t error; -}; - -/** \brief USART status - * Status descriptor holds the current status of transfer. - */ -struct usart_async_status { - /** Status flags */ - uint32_t flags; - /** Number of characters transmitted */ - uint16_t txcnt; - /** Number of characters receviced */ - uint16_t rxcnt; -}; - -/** - * \brief Asynchronous USART descriptor structure - */ -struct usart_async_descriptor { - struct io_descriptor io; - struct _usart_async_device device; - struct usart_async_callbacks usart_cb; - uint32_t stat; - - struct ringbuffer rx; - uint16_t tx_por; - uint8_t * tx_buffer; - uint16_t tx_buffer_length; -}; - -/** USART write busy */ -#define USART_ASYNC_STATUS_BUSY 0x0001 - -/** - * \brief Initialize USART interface - * - * This function initializes the given I/O descriptor to be used as USART - * interface descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr A USART descriptor which is used to communicate via the USART - * \param[in] hw The pointer to the hardware instance - * \param[in] rx_buffer An RX buffer - * \param[in] rx_buffer_length The length of the buffer above - * \param[in] func The pointer to a set of function pointers - * - * \return Initialization status. - * \retval -1 Passed parameters were invalid or the interface is already - * initialized - * \retval 0 The initialization is completed successfully - */ -int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer, - const uint16_t rx_buffer_length, void *const func); - -/** - * \brief Deinitialize USART interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and if the given hardware - * is permitted to be deinitialized. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return De-initialization status. - */ -int32_t usart_async_deinit(struct usart_async_descriptor *const descr); - -/** - * \brief Enable USART interface - * - * Enables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Enabling status. - */ -int32_t usart_async_enable(struct usart_async_descriptor *const descr); - -/** - * \brief Disable USART interface - * - * Disables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Disabling status. - */ -int32_t usart_async_disable(struct usart_async_descriptor *const descr); - -/** - * \brief Retrieve I/O descriptor - * - * This function retrieves the I/O descriptor of the given USART descriptor. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] io An I/O descriptor to retrieve - * - * \return The status of I/O descriptor retrieving. - */ -int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io); - -/** - * \brief Register USART callback - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] type Callback type - * \param[in] cb A callback function - * - * \return The status of callback assignment. - * \retval -1 Passed parameters were invalid or the interface is not initialized - * \retval 0 A callback is registered successfully - */ -int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, - const enum usart_async_callback_type type, usart_cb_t cb); - -/** - * \brief Specify action for flow control pins - * - * This function sets action (or state) for flow control pins if - * the flow control is enabled. - * It sets state of flow control pins only if automatic support of - * the flow control is not supported by the hardware. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] state A state to set the flow control pins - * - * \return The status of flow control action setup. - */ -int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, - const union usart_flow_control_state state); - -/** - * \brief Set USART baud rate - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] baud_rate A baud rate to set - * - * \return The status of baud rate setting. - */ -int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate); - -/** - * \brief Set USART data order - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] data_order A data order to set - * - * \return The status of data order setting. - */ -int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order); - -/** - * \brief Set USART mode - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] mode A mode to set - * - * \return The status of mode setting. - */ -int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode); - -/** - * \brief Set USART parity - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] parity A parity to set - * - * \return The status of parity setting. - */ -int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity); - -/** - * \brief Set USART stop bits - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] stop_bits Stop bits to set - * - * \return The status of stop bits setting. - */ -int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits); - -/** - * \brief Set USART character size - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] size A character size to set - * - * \return The status of character size setting. - */ -int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, - const enum usart_character_size size); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the flow control pins - * if the flow control is enabled. - * - * The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case - * if the flow control is done by the hardware - * and the pins state cannot be read out. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] state The state of flow control pins - * - * \return The status of flow control state reading. - */ -int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, - union usart_flow_control_state *const state); - -/** - * \brief Check if the USART transmitter is empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART TX empty checking. - * \retval 0 The USART transmitter is not empty - * \retval 1 The USART transmitter is empty - */ -int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr); - -/** - * \brief Check if the USART receiver is not empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of the USART RX empty checking. - * \retval 1 The USART receiver is not empty - * \retval 0 The USART receiver is empty - */ -int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr); - -/** - * \brief Retrieve the current interface status - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] status The state of USART - * - * \return The status of USART status retrieving. - */ -int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status); - -/** - * \brief flush USART ringbuf - * - * This function flush USART RX ringbuf. - * - * \param[in] descr The pointer to USART descriptor - * - * \return ERR_NONE - */ -int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usart_async_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_USART_ASYNC_H_INCLUDED */ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_USART_ASYNC_H_INCLUDED +#define _HAL_USART_ASYNC_H_INCLUDED + +#include "hal_io.h" +#include +#include + +/** + * \addtogroup doc_driver_hal_usart_async + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor + * + * The USART descriptor forward declaration. + */ +struct usart_async_descriptor; + +/** + * \brief USART callback type + */ +typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr); + +/** + * \brief USART callback types + */ +enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB }; + +/** + * \brief USART callbacks + */ +struct usart_async_callbacks { + usart_cb_t tx_done; + usart_cb_t rx_done; + usart_cb_t error; +}; + +/** \brief USART status + * Status descriptor holds the current status of transfer. + */ +struct usart_async_status { + /** Status flags */ + uint32_t flags; + /** Number of characters transmitted */ + uint16_t txcnt; + /** Number of characters receviced */ + uint16_t rxcnt; +}; + +/** + * \brief Asynchronous USART descriptor structure + */ +struct usart_async_descriptor { + struct io_descriptor io; + struct _usart_async_device device; + struct usart_async_callbacks usart_cb; + uint32_t stat; + + struct ringbuffer rx; + uint16_t tx_por; + uint8_t * tx_buffer; + uint16_t tx_buffer_length; +}; + +/** USART write busy */ +#define USART_ASYNC_STATUS_BUSY 0x0001 + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used as USART + * interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via the USART + * \param[in] hw The pointer to the hardware instance + * \param[in] rx_buffer An RX buffer + * \param[in] rx_buffer_length The length of the buffer above + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + * \retval -1 Passed parameters were invalid or the interface is already + * initialized + * \retval 0 The initialization is completed successfully + */ +int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer, + const uint16_t rx_buffer_length, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware + * is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_async_deinit(struct usart_async_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_async_enable(struct usart_async_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_async_disable(struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of I/O descriptor retrieving. + */ +int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Register USART callback + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] type Callback type + * \param[in] cb A callback function + * + * \return The status of callback assignment. + * \retval -1 Passed parameters were invalid or the interface is not initialized + * \retval 0 A callback is registered successfully + */ +int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, + const enum usart_async_callback_type type, usart_cb_t cb); + +/** + * \brief Specify action for flow control pins + * + * This function sets action (or state) for flow control pins if + * the flow control is enabled. + * It sets state of flow control pins only if automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, + const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the flow control pins + * if the flow control is enabled. + * + * The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of the USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve the current interface status + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] status The state of USART + * + * \return The status of USART status retrieving. + */ +int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status); + +/** + * \brief flush USART ringbuf + * + * This function flush USART RX ringbuf. + * + * \param[in] descr The pointer to USART descriptor + * + * \return ERR_NONE + */ +int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_async_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_USART_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h index cb26091..b8fdcd5 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_cmcc.h @@ -1,277 +1,277 @@ -/** - * \file - * - * \brief Generic CMCC(Cortex M Cache Controller) related functionality. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#ifndef HPL_CMCC_H_ -#define HPL_CMCC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * \Cache driver MACROS - */ -#define CMCC_DISABLE 0U -#define CMCC_ENABLE 1U -#define IS_CMCC_DISABLED 0U -#define IS_CMCC_ENABLED 1U -#define CMCC_WAY_NOS 4U -#define CMCC_LINE_NOS 64U -#define CMCC_MONITOR_DISABLE 0U - -/** - * \brief Cache size configurations - */ -enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; - -/** - * \brief Way Numbers - */ -enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; - -/** - * \brief Cache monitor configurations - */ -enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; - -/** - * \brief Cache configuration structure - */ -struct _cache_cfg { - enum conf_cache_size cache_size; - bool data_cache_disable; - bool inst_cache_disable; - bool gclk_gate_disable; -}; - -/** - * \brief Cache enable status - */ -static inline bool _is_cache_enabled(const void *hw) -{ - return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); -} - -/** - * \brief Cache disable status - */ -static inline bool _is_cache_disabled(const void *hw) -{ - return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); -} - -/** - * \brief Cache enable - */ -static inline int32_t _cmcc_enable(const void *hw) -{ - int32_t return_value; - - if (_is_cache_disabled(hw)) { - hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); - return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; - } else { - return_value = ERR_NO_CHANGE; - } - - return return_value; -} - -/** - * \brief Cache disable - */ -static inline int32_t _cmcc_disable(const void *hw) -{ - hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); - while (!(_is_cache_disabled(hw))) - ; - - return ERR_NONE; -} - -/** - * \brief Initialize Cache Module - * - * This function initialize low level cmcc module configuration. - * - * \return initialize status - */ -int32_t _cmcc_init(void); - -/** - * \brief Configure CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] cache configuration structure pointer - * - * \return status of operation - */ -int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); - -/** - * \brief Enable data cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache - * - * \return status of operation - */ -int32_t _cmcc_enable_data_cache(const void *hw, bool value); - -/** - * \brief Enable instruction cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache - * - * \return status of operation - */ -int32_t _cmcc_enable_inst_cache(const void *hw, bool value); - -/** - * \brief Enable clock gating in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate - * - * \return status of operation - */ -int32_t _cmcc_enable_clock_gating(const void *hw, bool value); - -/** - * \brief Configure the cache size in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache size configuration enumerator - * 0->1K, 1->2K, 2->4K(default) - * - * \return status of operation - */ -int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); - -/** - * \brief Lock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_lock_way(const void *hw, enum way_num_index); - -/** - * \brief Unlock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); - -/** - * \brief Invalidate the mentioned cache line in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num" enumerator (valid arg is 0-3) - * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) - * - * \return status of operation - */ -int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); - -/** - * \brief Invalidate entire cache entries in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_invalidate_all(const void *hw); - -/** - * \brief Configure cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache monitor configurations enumerator - * - * \return status of operation - */ -int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); - -/** - * \brief Enable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_enable_monitor(const void *hw); - -/** - * \brief Disable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_disable_monitor(const void *hw); - -/** - * \brief Reset cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_reset_monitor(const void *hw); - -/** - * \brief Get cache monitor event counter value from CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return event counter value - */ -uint32_t _cmcc_get_monitor_event_count(const void *hw); - -#ifdef __cplusplus -} -#endif -#endif /* HPL_CMCC_H_ */ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HPL_CMCC_H_ +#define HPL_CMCC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \Cache driver MACROS + */ +#define CMCC_DISABLE 0U +#define CMCC_ENABLE 1U +#define IS_CMCC_DISABLED 0U +#define IS_CMCC_ENABLED 1U +#define CMCC_WAY_NOS 4U +#define CMCC_LINE_NOS 64U +#define CMCC_MONITOR_DISABLE 0U + +/** + * \brief Cache size configurations + */ +enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; + +/** + * \brief Way Numbers + */ +enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; + +/** + * \brief Cache monitor configurations + */ +enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; + +/** + * \brief Cache configuration structure + */ +struct _cache_cfg { + enum conf_cache_size cache_size; + bool data_cache_disable; + bool inst_cache_disable; + bool gclk_gate_disable; +}; + +/** + * \brief Cache enable status + */ +static inline bool _is_cache_enabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); +} + +/** + * \brief Cache disable status + */ +static inline bool _is_cache_disabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); +} + +/** + * \brief Cache enable + */ +static inline int32_t _cmcc_enable(const void *hw) +{ + int32_t return_value; + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); + return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NO_CHANGE; + } + + return return_value; +} + +/** + * \brief Cache disable + */ +static inline int32_t _cmcc_disable(const void *hw) +{ + hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); + while (!(_is_cache_disabled(hw))) + ; + + return ERR_NONE; +} + +/** + * \brief Initialize Cache Module + * + * This function initialize low level cmcc module configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void); + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value); + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value); + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value); + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index); + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw); + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw); + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw); + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw); + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw); + +#ifdef __cplusplus +} +#endif +#endif /* HPL_CMCC_H_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_core.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_core.h index 9324c43..679f7ab 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_core.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_core.h @@ -1,56 +1,56 @@ -/** - * \file - * - * \brief CPU core related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_H_INCLUDED -#define _HPL_CORE_H_INCLUDED - -/** - * \addtogroup HPL Core - * - * \section hpl_core_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_core_port.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_CORE_H_INCLUDED */ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h index a0f1ac8..2e9ab95 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_delay.h @@ -1,97 +1,97 @@ -/** - * \file - * - * \brief Delay related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DELAY_H_INCLUDED -#define _HPL_DELAY_H_INCLUDED - -/** - * \addtogroup HPL Delay - * - * \section hpl_delay_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Initialize delay functionality - * - * \param[in] hw The pointer to hardware instance - */ -void _delay_init(void *const hw); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - * - * \param[in] us The amount of us to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_us(const uint16_t us); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - * - * \param[in] ms The amount of ms to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_ms(const uint16_t ms); - -/** - * \brief Delay loop to delay n number of cycles - * - * \param[in] hw The pointer to hardware instance - * \param[in] cycles The amount of cycles to delay for - */ -void _delay_cycles(void *const hw, uint32_t cycles); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_DELAY_H_INCLUDED */ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h index 1e08434..d6d08f6 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_dma.h @@ -1,176 +1,176 @@ -/** - * \file - * - * \brief DMA related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DMA_H_INCLUDED -#define _HPL_DMA_H_INCLUDED - -/** - * \addtogroup HPL DMA - * - * \section hpl_dma_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct _dma_resource; - -/** - * \brief DMA callback types - */ -enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; - -/** - * \brief DMA interrupt callbacks - */ -struct _dma_callbacks { - void (*transfer_done)(struct _dma_resource *resource); - void (*error)(struct _dma_resource *resource); -}; - -/** - * \brief DMA resource structure - */ -struct _dma_resource { - struct _dma_callbacks dma_cb; - void * back; -}; - -/** - * \brief Initialize DMA - * - * This function does low level DMA configuration. - * - * \return initialize status - */ -int32_t _dma_init(void); - -/** - * \brief Set destination address - * - * \param[in] channel DMA channel to set destination address for - * \param[in] dst Destination address - * - * \return setting status - */ -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); - -/** - * \brief Set source address - * - * \param[in] channel DMA channel to set source address for - * \param[in] src Source address - * - * \return setting status - */ -int32_t _dma_set_source_address(const uint8_t channel, const void *const src); - -/** - * \brief Set next descriptor address - * - * \param[in] current_channel Current DMA channel to set next descriptor address - * \param[in] next_channel Next DMA channel used as next descriptor - * - * \return setting status - */ -int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); - -/** - * \brief Enable/disable source address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set source address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); - -/** - * \brief Enable/disable Destination address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set destination address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); -/** - * \brief Set the amount of data to be transfered per transaction - * - * \param[in] channel DMA channel to set data amount for - * \param[in] amount Data amount - * - * \return status of operation - */ -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); - -/** - * \brief Trigger DMA transaction on the given channel - * - * \param[in] channel DMA channel to trigger transaction on - * - * \return status of operation - */ -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); - -/** - * \brief Retrieves DMA resource structure - * - * \param[out] resource The resource to be retrieved - * \param[in] channel DMA channel to retrieve structure for - * - * \return status of operation - */ -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); - -/** - * \brief Enable/disable DMA interrupt - * - * \param[in] channel DMA channel to enable/disable interrupt for - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -#endif /* HPL_DMA_H_INCLUDED */ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h index 3a169b6..e70baa3 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ext_irq.h @@ -1,95 +1,95 @@ -/** - * \file - * - * \brief External IRQ related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_EXT_IRQ_H_INCLUDED -#define _HPL_EXT_IRQ_H_INCLUDED - -/** - * \addtogroup HPL EXT IRQ - * - * \section hpl_ext_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize external interrupt module - * - * This function does low level external interrupt configuration. - * - * \param[in] cb The pointer to callback function from external interrupt - * - * \return Initialization status. - * \retval -1 External irq module is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t _ext_irq_init(void (*cb)(const uint32_t pin)); - -/** - * \brief Deinitialize external interrupt module - * - * \return Initialization status. - * \retval -1 External irq module is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t _ext_irq_deinit(void); - -/** - * \brief Enable / disable external irq - * - * \param[in] pin Pin to enable external irq on - * \param[in] enable True to enable, false to disable - * - * \return Status of external irq enabling / disabling - * \retval -1 External irq module can't be enabled / disabled - * \retval 0 External irq module is enabled / disabled successfully - */ -int32_t _ext_irq_enable(const uint32_t pin, const bool enable); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_EXT_IRQ_H_INCLUDED */ +/** + * \file + * + * \brief External IRQ related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_EXT_IRQ_H_INCLUDED +#define _HPL_EXT_IRQ_H_INCLUDED + +/** + * \addtogroup HPL EXT IRQ + * + * \section hpl_ext_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize external interrupt module + * + * This function does low level external interrupt configuration. + * + * \param[in] cb The pointer to callback function from external interrupt + * + * \return Initialization status. + * \retval -1 External irq module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)); + +/** + * \brief Deinitialize external interrupt module + * + * \return Initialization status. + * \retval -1 External irq module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t _ext_irq_deinit(void); + +/** + * \brief Enable / disable external irq + * + * \param[in] pin Pin to enable external irq on + * \param[in] enable True to enable, false to disable + * + * \return Status of external irq enabling / disabling + * \retval -1 External irq module can't be enabled / disabled + * \retval 0 External irq module is enabled / disabled successfully + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_EXT_IRQ_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h index 5cdd387..4441524 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_gpio.h @@ -1,185 +1,185 @@ -/** - * \file - * - * \brief Port related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GPIO_H_INCLUDED -#define _HPL_GPIO_H_INCLUDED - -/** - * \addtogroup HPL Port - * - * \section hpl_port_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/** - * \brief Macros for the pin and port group, lower 5 - * bits stands for pin number in the group, higher 3 - * bits stands for port group - */ -#define GPIO_PIN(n) (((n)&0x1Fu) << 0) -#define GPIO_PORT(n) ((n) >> 5) -#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) -#define GPIO_PIN_FUNCTION_OFF 0xffffffff - -/** - * \brief PORT pull mode settings - */ -enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; - -/** - * \brief PORT direction settins - */ -enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; - -/** - * \brief PORT group abstraction - */ - -enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Port initialization function - * - * Port initialization function should setup the port module based - * on a static configuration file, this function should normally - * not be called directly, but is a part of hal_init() - */ -void _gpio_init(void); - -/** - * \brief Set direction on port with mask - * - * Set data direction for each pin, or disable the pin - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input - * and disable input buffer to disable the pin - * GPIO_DIRECTION_IN = set pin direction to input - * and enable input buffer to enable the pin - * GPIO_DIRECTION_OUT = set pin direction to output - * and disable input buffer - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction); - -/** - * \brief Set output level on port with mask - * - * Sets output state on pin to high or low with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - * \param[in] level true = pin level is set to 1 - * false = pin level is set to 0 - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); - -/** - * \brief Change output level to the opposite with mask - * - * Change pin output level to the opposite with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); - -/** - * \brief Get input levels on all port pins - * - * Get input level on all port pins, will read IN register if configured to - * input and OUT register if configured as output - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port); - -/** - * \brief Set pin pull mode - * - * Set pull mode on a single pin - * - * \notice This function will automatically change pin direction to input - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] pin The pin in the group that pull mode should be selected - * for - * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled - * GPIO_PULL_DOWN = pull resistor on pin will pull pin - * level to ground level - * GPIO_PULL_UP = pull resistor on pin will pull pin - * level to VCC - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode); - -/** - * \brief Set gpio function - * - * Select which function a gpio is used for - * - * \param[in] gpio The gpio to set function for - * \param[in] function The gpio function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); - -#include -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_GPIO_H_INCLUDED */ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_async.h index 8a9491d..bb2fbf0 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_async.h @@ -1,205 +1,205 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED -#define _HPL_I2C_M_ASYNC_H_INCLUDED - -#include "hpl_i2c_m_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c master callback names - */ -enum _i2c_m_async_callback_type { - I2C_M_ASYNC_DEVICE_ERROR, - I2C_M_ASYNC_DEVICE_TX_COMPLETE, - I2C_M_ASYNC_DEVICE_RX_COMPLETE -}; - -struct _i2c_m_async_device; - -typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); -typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); - -/** - * \brief i2c callback pointers structure - */ -struct _i2c_m_async_callback { - _i2c_error_cb_t error; - _i2c_complete_cb_t tx_complete; - _i2c_complete_cb_t rx_complete; -}; - -/** - * \brief i2c device structure - */ -struct _i2c_m_async_device { - struct _i2c_m_service service; - void * hw; - struct _i2c_m_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C in interrupt mode - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c interrupt device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C in interrupt mode - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Register callback to I2C - * - * This function does low level I2C callback register. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] cb_type The callback type request - * \param[in] func The callback function pointer - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, - FUNC_PTR func); - -/** - * \brief Generate stop condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Operation status - * \retval 0 Operation executed successfully - * \retval <0 Operation failed - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Returns the number of bytes left or not used in the I2C message buffer - * - * This function will return the number of bytes left (not written to the bus) or still free - * (not received from the bus) in the message buffer, depending on direction of transmission. - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Number of bytes or error code - * \retval >0 Positive number indicating bytes left - * \retval 0 Buffer is full/empty depending on direction - * \retval <0 Error code - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable/disable I2C master interrupt - * - * param[in] device The pointer to I2C master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -#endif +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_sync.h index ce173ae..c1fc870 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_m_sync.h @@ -1,185 +1,185 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_SYNC_H_INCLUDED -#define _HPL_I2C_M_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c flags - */ -#define I2C_M_RD 0x0001 /* read data, from slave to master */ -#define I2C_M_BUSY 0x0100 -#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ -#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ -#define I2C_M_FAIL 0x1000 -#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ - -/** - * \brief i2c Return codes - */ -#define I2C_OK 0 /* Operation successful */ -#define I2C_ACK -1 /* Received ACK from device on I2C bus */ -#define I2C_NACK -2 /* Received NACK from device on I2C bus */ -#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ -#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ -#define I2C_ERR_BUS -5 /* Bus error */ -#define I2C_ERR_BUSY -6 /* Device busy */ -#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ - -/** - * \brief i2c I2C Modes - */ -#define I2C_STANDARD_MODE 0x00 -#define I2C_FASTMODE 0x01 -#define I2C_HIGHSPEED_MODE 0x02 - -/** - * \brief i2c master message structure - */ -struct _i2c_m_msg { - uint16_t addr; - volatile uint16_t flags; - int32_t len; - uint8_t * buffer; -}; - -/** - * \brief i2c master service - */ -struct _i2c_m_service { - struct _i2c_m_msg msg; - uint16_t mode; - uint16_t trise; -}; - -/** - * \brief i2c sync master device structure - */ -struct _i2c_m_sync_device { - struct _i2c_m_service service; - void * hw; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Send send condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_dev The pointer to i2c device struct - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); - -#ifdef __cplusplus -} -#endif - -#endif +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_async.h index 92a5765..9993593 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_async.h @@ -1,184 +1,184 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED -#define _HPL_I2C_S_ASYNC_H_INCLUDED - -#include "hpl_i2c_s_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c callback types - */ -enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; - -/** - * \brief Forward declaration of I2C Slave device - */ -struct _i2c_s_async_device; - -/** - * \brief i2c slave callback function type - */ -typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); - -/** - * \brief i2c slave callback pointers structure - */ -struct _i2c_s_async_callback { - void (*error)(struct _i2c_s_async_device *const device); - void (*tx)(struct _i2c_s_async_device *const device); - void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); -}; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_async_device { - void * hw; - struct _i2c_s_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize asynchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c interrupt device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); - -/** - * \brief Deinitialize asynchronous I2C in interrupt mode - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); - -/** - * \brief Abort data transmission - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); - -/** - * \brief Enable/disable I2C slave interrupt - * - * param[in] device The pointer to I2C slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool disable); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_sync.h index 93b5934..02c31f5 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_i2c_s_sync.h @@ -1,184 +1,184 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_SYNC_H_INCLUDED -#define _HPL_I2C_S_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I2C Slave status type - */ -typedef uint32_t i2c_s_status_t; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_sync_device { - void *hw; -}; - -#include - -/** - * \name HPL functions - */ - -/** - * \brief Initialize synchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize synchronous I2C slave - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); - -/** - * \brief Clear the Data Ready interrupt flag - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); - -/** - * \brief Read a byte from the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Data received via I2C interface. - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if I2C is ready to send next byte - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the ready check. - * \retval true if the I2C is ready to send next byte - * \retval false if the I2C is not ready to send next byte - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if there is data received by I2C - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the data received check. - * \retval true if the I2C has received a byte - * \retval false if the I2C has not received a byte - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_init.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_init.h index 71bf49c..0e18e0e 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_init.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_init.h @@ -1,124 +1,124 @@ -/** - * \file - * - * \brief Init related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_INIT_H_INCLUDED -#define _HPL_INIT_H_INCLUDED - -/** - * \addtogroup HPL Init - * - * \section hpl_init_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initializes clock sources - */ -void _sysctrl_init_sources(void); - -/** - * \brief Initializes Power Manager - */ -void _pm_init(void); - -/** - * \brief Initialize generators - */ -void _gclk_init_generators(void); - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void); - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _sysctrl_init_referenced_generators(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _oscctrl_init_referenced_generators(void); - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void); - -/** - * \brief Initialize clock generator - */ -void _lpmcu_misc_regs_init(void); - -/** - * \brief Initialize clock generator - */ -void _pmc_init(void); - -/** - * \brief Set performance level - * - * \param[in] level The performance level to set - */ -void _set_performance_level(const uint8_t level); - -/** - * \brief Initialize the chip - */ -void _init_chip(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_INIT_H_INCLUDED */ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h index 2894944..17561d4 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_irq.h @@ -1,116 +1,116 @@ -/** - * \file - * - * \brief IRQ related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_IRQ_H_INCLUDED -#define _HPL_IRQ_H_INCLUDED - -/** - * \addtogroup HPL IRQ - * - * \section hpl_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief IRQ descriptor - */ -struct _irq_descriptor { - void (*handler)(void *parameter); - void *parameter; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve current IRQ number - * - * \return The current IRQ number - */ -uint8_t _irq_get_current(void); - -/** - * \brief Disable the given IRQ - * - * \param[in] n The number of IRQ to disable - */ -void _irq_disable(uint8_t n); - -/** - * \brief Set the given IRQ - * - * \param[in] n The number of IRQ to set - */ -void _irq_set(uint8_t n); - -/** - * \brief Clear the given IRQ - * - * \param[in] n The number of IRQ to clear - */ -void _irq_clear(uint8_t n); - -/** - * \brief Enable the given IRQ - * - * \param[in] n The number of IRQ to enable - */ -void _irq_enable(uint8_t n); - -/** - * \brief Register IRQ handler - * - * \param[in] number The number registered IRQ - * \param[in] irq The pointer to irq handler to register - * - * \return The status of IRQ handler registering - * \retval -1 Passed parameters were invalid - * \retval 0 The registering is completed successfully - */ -void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_IRQ_H_INCLUDED */ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h index 7071db2..cc13311 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_missing_features.h @@ -1,37 +1,37 @@ -/** - * \file - * - * \brief Family-dependent missing features expected by HAL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_MISSING_FEATURES -#define _HPL_MISSING_FEATURES - -#endif /* _HPL_MISSING_FEATURES */ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h index ff87052..aca05f1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_pwm.h @@ -1,193 +1,193 @@ -/** - * \file - * - * \brief PWM related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_PWM_H_INCLUDED -#define _HPL_PWM_H_INCLUDED - -/** - * \addtogroup HPL PWM - * - * \section hpl_pwm_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief PWM callback types - */ -enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; - -/** - * \brief PWM pulse-width period - */ -typedef uint32_t pwm_period_t; - -/** - * \brief PWM device structure - * - * The PWM device structure forward declaration. - */ -struct _pwm_device; - -/** - * \brief PWM interrupt callbacks - */ -struct _pwm_callback { - void (*pwm_period_cb)(struct _pwm_device *device); - void (*pwm_error_cb)(struct _pwm_device *device); -}; - -/** - * \brief PWM descriptor device structure - */ -struct _pwm_device { - struct _pwm_callback callback; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief PWM functions, pointers to low-level functions - */ -struct _pwm_hpl_interface { - int32_t (*init)(struct _pwm_device *const device, void *const hw); - void (*deinit)(struct _pwm_device *const device); - void (*start_pwm)(struct _pwm_device *const device); - void (*stop_pwm)(struct _pwm_device *const device); - void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - bool (*is_pwm_enabled)(const struct _pwm_device *const device); - pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); - uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); - void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); -}; -/** - * \brief Initialize TC - * - * This function does low level TC configuration. - * - * \param[in] device The pointer to PWM device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _pwm_init(struct _pwm_device *const device, void *const hw); - -/** - * \brief Deinitialize TC - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_deinit(struct _pwm_device *const device); - -/** - * \brief Retrieve offset of the given tc hardware instance - * - * \param[in] device The pointer to PWM device instance - * - * \return The offset of the given tc hardware instance - */ -uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); - -/** - * \brief Start hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_enable(struct _pwm_device *const device); - -/** - * \brief Stop hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_disable(struct _pwm_device *const device); - -/** - * \brief Set pwm parameter - * - * \param[in] device The pointer to PWM device instance - * \param[in] period Total period of one PWM cycle. - * \param[in] duty_cycle Period of PWM first half during one cycle. - */ -void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - -/** - * \brief Check if pwm is working - * - * \param[in] device The pointer to PWM device instance - * - * \return Check status. - * \retval true The given pwm is working - * \retval false The given pwm is not working - */ -bool _pwm_is_enabled(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform period value - * - * \param[in] device The pointer to PWM device instance - * - * \return Period value. - */ -pwm_period_t _pwm_get_period(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform duty cycle value - * - * \param[in] device The pointer to PWM device instance - * - * \return Duty cycle value - */ -uint32_t _pwm_get_duty(const struct _pwm_device *const device); - -/** - * \brief Enable/disable PWM interrupt - * - * param[in] device The pointer to PWM device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_PWM_H_INCLUDED */ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ramecc.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ramecc.h index d79d514..dc7babe 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ramecc.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_ramecc.h @@ -1,100 +1,100 @@ -/** - * \file - * - * \brief RAMECC related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RAMECC_H_INCLUDED -#define _HPL_RAMECC_H_INCLUDED - -/** - * \addtogroup HPL RAMECC - * - * \section hpl_ramecc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief RAMECC callback type - */ -typedef void (*ramecc_cb_t)(const uint32_t data); - -/** - * \brief RAMECC callback types - */ -enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; - -/** - * \brief RAMECC interrupt callbacks - */ -struct _ramecc_callbacks { - ramecc_cb_t dual_bit_err; - ramecc_cb_t single_bit_err; -}; - -/** - * \brief RAMECC device structure - */ -struct _ramecc_device { - struct _ramecc_callbacks ramecc_cb; - struct _irq_descriptor irq; -}; - -/** - * \brief Initialize RAMECC - * - * This function does low level RAMECC configuration. - * - * \return initialize status - */ -int32_t _ramecc_init(void); - -/** - * \brief Register RAMECC callback - * - * \param[in] type The type of callback - * \param[in] cb A callback function - */ -void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RAMECC_H_INCLUDED */ +/** + * \file + * + * \brief RAMECC related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAMECC_H_INCLUDED +#define _HPL_RAMECC_H_INCLUDED + +/** + * \addtogroup HPL RAMECC + * + * \section hpl_ramecc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief RAMECC callback type + */ +typedef void (*ramecc_cb_t)(const uint32_t data); + +/** + * \brief RAMECC callback types + */ +enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; + +/** + * \brief RAMECC interrupt callbacks + */ +struct _ramecc_callbacks { + ramecc_cb_t dual_bit_err; + ramecc_cb_t single_bit_err; +}; + +/** + * \brief RAMECC device structure + */ +struct _ramecc_device { + struct _ramecc_callbacks ramecc_cb; + struct _irq_descriptor irq; +}; + +/** + * \brief Initialize RAMECC + * + * This function does low level RAMECC configuration. + * + * \return initialize status + */ +int32_t _ramecc_init(void); + +/** + * \brief Register RAMECC callback + * + * \param[in] type The type of callback + * \param[in] cb A callback function + */ +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_reset.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_reset.h index d627ea6..40ee6c5 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_reset.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_reset.h @@ -1,93 +1,93 @@ -/** - * \file - * - * \brief Reset related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RESET_H_INCLUDED -#define _HPL_RESET_H_INCLUDED - -/** - * \addtogroup HPL Reset - * - * \section hpl_reset_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Reset reason enumeration - * - * The list of possible reset reasons. - */ -enum reset_reason { - RESET_REASON_POR = 1, - RESET_REASON_BOD12 = 2, - RESET_REASON_BOD33 = 4, - RESET_REASON_NVM = 8, - RESET_REASON_EXT = 16, - RESET_REASON_WDT = 32, - RESET_REASON_SYST = 64, - RESET_REASON_BACKUP = 128 -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve the reset reason - * - * Retrieves the reset reason of the last MCU reset. - * - *\return An enum value indicating the reason of the last reset. - */ -enum reset_reason _get_reset_reason(void); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RESET_H_INCLUDED */ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_NVM = 8, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h index 6731ec3..245e71d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_sleep.h @@ -1,88 +1,88 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SLEEP_H_INCLUDED -#define _HPL_SLEEP_H_INCLUDED - -/** - * \addtogroup HPL Sleep - * - * \section hpl_sleep_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Set the sleep mode for the device - * - * This function sets the sleep mode for the device. - * For an overview of which systems are disabled in sleep for the different - * sleep modes see datasheet. - * - * \param[in] mode Sleep mode to use - * - * \return the status of a sleep request - * \retval -1 The requested sleep mode was invalid - * \retval 0 The operation completed successfully, sleep mode is set - */ -int32_t _set_sleep_mode(const uint8_t mode); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SLEEP_H_INCLUDED */ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi.h index a5652e5..f4b1be1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi.h @@ -1,163 +1,163 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_H_INCLUDED -#define _HPL_SPI_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SPI Dummy char is used when reading data from the SPI slave - */ -#define SPI_DUMMY_CHAR 0x1ff - -/** - * \brief SPI message to let driver to process - */ -//@{ -struct spi_msg { - /** Pointer to the output data buffer */ - uint8_t *txbuf; - /** Pointer to the input data buffer */ - uint8_t *rxbuf; - /** Size of the message data in SPI characters */ - uint32_t size; -}; -//@} - -/** - * \brief SPI transfer modes - * SPI transfer mode controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - */ -enum spi_transfer_mode { - /** Leading edge is rising edge, data sample on leading edge. */ - SPI_MODE_0, - /** Leading edge is rising edge, data sample on trailing edge. */ - SPI_MODE_1, - /** Leading edge is falling edge, data sample on leading edge. */ - SPI_MODE_2, - /** Leading edge is falling edge, data sample on trailing edge. */ - SPI_MODE_3 -}; - -/** - * \brief SPI character sizes - * The character size influence the way the data is sent/received. - * For char size <= 8 data is stored byte by byte. - * For char size between 9 ~ 16 data is stored in 2-byte length. - * Note that the default and recommended char size is 8 bit since it's - * supported by all system. - */ -enum spi_char_size { - /** Character size is 8 bit. */ - SPI_CHAR_SIZE_8 = 0, - /** Character size is 9 bit. */ - SPI_CHAR_SIZE_9 = 1, - /** Character size is 10 bit. */ - SPI_CHAR_SIZE_10 = 2, - /** Character size is 11 bit. */ - SPI_CHAR_SIZE_11 = 3, - /** Character size is 12 bit. */ - SPI_CHAR_SIZE_12 = 4, - /** Character size is 13 bit. */ - SPI_CHAR_SIZE_13 = 5, - /** Character size is 14 bit. */ - SPI_CHAR_SIZE_14 = 6, - /** Character size is 15 bit. */ - SPI_CHAR_SIZE_15 = 7, - /** Character size is 16 bit. */ - SPI_CHAR_SIZE_16 = 8 -}; - -/** - * \brief SPI data order - */ -enum spi_data_order { - /** MSB goes first. */ - SPI_DATA_ORDER_MSB_1ST = 0, - /** LSB goes first. */ - SPI_DATA_ORDER_LSB_1ST = 1 -}; - -/** \brief Transfer descriptor for SPI - * Transfer descriptor holds TX and RX buffers - */ -struct spi_xfer { - /** Pointer to data buffer to TX */ - uint8_t *txbuf; - /** Pointer to data buffer to RX */ - uint8_t *rxbuf; - /** Size of data characters to TX & RX */ - uint32_t size; -}; - -/** SPI generic driver. */ -struct spi_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Reference start of sync/async variables */ - uint32_t sync_async_misc[1]; -}; - -/** - * \brief Calculate the baudrate value for hardware to use to set baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] clk Clock frequency (Hz) for baudrate generation. - * \param[in] baud Target baudrate (bps). - * \return Error or baudrate value. - * \retval >0 Baudrate value. - * \retval ERR_INVALID_ARG Calculation fail. - */ -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_H_INCLUDED */ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h index 8e5a848..724fbc9 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_async.h @@ -1,131 +1,131 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_ASYNC_H_INCLUDED -#define _HPL_SPI_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Callbacks the SPI driver must offer in async mode - */ -//@{ -/** The callback types */ -enum _spi_async_dev_cb_type { - /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_TX, - /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_RX, - /** Callback type for \ref _spi_async_dev_cb_complete_t. */ - SPI_DEV_CB_COMPLETE, - /** Callback type for error */ - SPI_DEV_CB_ERROR, - /** Number of callbacks. */ - SPI_DEV_CB_N -}; - -struct _spi_async_dev; - -/** \brief The prototype for callback on SPI transfer error. - * If status code is zero, it indicates the normal completion, that is, - * SS deactivation. - * If status code belows zero, it indicates complete. - */ -typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); - -/** \brief The prototype for callback on SPI transmit/receive event - * For TX, the callback is invoked when transmit is done or ready to start - * transmit. - * For RX, the callback is invoked when receive is done or ready to read data, - * see \ref _spi_async_dev_read_one_t on data reading. - * Without DMA enabled, the callback is invoked on each character event. - * With DMA enabled, the callback is invoked on DMA buffer done. - */ -typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_async_dev_callbacks { - /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t tx; - /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t rx; - /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ - _spi_async_dev_cb_xfer_t complete; - /** Error callback, see \ref */ - _spi_async_dev_cb_error_t err; -}; -//@} - -/** - * \brief SPI async driver - */ -//@{ - -/** SPI driver to support async HAL */ -struct _spi_async_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; - - /** \brief Pointer to callback functions, ignored for polling mode - * Pointer to the callback functions so that initialize the driver to - * handle interrupts. - */ - struct _spi_async_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; -}; -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_async.h index 8d3555e..eddcd61 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_async.h @@ -1,243 +1,243 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED -#define _HPL_SPI_M_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_async_dev _spi_async_dev - -#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on after data transmission complate - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h index 2b48300..561609f 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_dma.h @@ -1,182 +1,182 @@ -/** - * \file - * - * \brief SPI Master DMA related functionality declaration. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_DMA_H_INCLUDED -#define _HPL_SPI_M_DMA_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI dma device driver. */ -#define _spi_m_dma_dev _spi_dma_dev - -#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); - -/** - * \brief Register the SPI device callback - * \param[in] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); - -/** \brief Do SPI data transfer (TX & RX) with DMA - * Log the TX & RX buffers and transfer them in background. It never blocks. - * - * \param[in] dev Pointer to the SPI device instance. - * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). - * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). - * \param[in] length spi transfer data length. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy. - */ -int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, - const uint16_t length); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h index 38df15b..98d41e8 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_m_sync.h @@ -1,166 +1,166 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_SYNC_H_INCLUDED -#define _HPL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI sync device driver. */ -#define _spi_m_sync_dev _spi_sync_dev - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); - -/** - * \brief Deinitialize SPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI char size - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Transfer the whole message without interrupt - * Transfer the message, it will keep waiting until the message finish or - * error. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] msg Pointer to the message instance to process. - * \return Error or number of characters transferred. - * \retval ERR_BUSY SPI hardware is not ready to start transfer (not - * enabled, busy applying settings, ...). - * \retval SPI_ERR_OVERFLOW Overflow error. - * \retval >=0 Number of characters transferred. - */ -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_async.h index 5647243..7bd7cc0 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_async.h @@ -1,232 +1,232 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED -#define _HPL_SPI_S_ASYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_async_dev _spi_async_dev - -#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI slave interrupt - * - * param[in] device The pointer to SPI slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_sync.h index ff4c811..a18807b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_s_sync.h @@ -1,232 +1,232 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_SYNC_H_INCLUDED -#define _HPL_SPI_S_SYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI sync device driver. */ -#define _spi_s_sync_dev _spi_sync_dev - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retval 0 OK Status - */ -int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); - -/** - * \brief Check if TX ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return TX ready state - * \retval true TX ready - * \retval false TX not ready - */ -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if RX character ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return RX character ready state - * \retval true RX character ready - * \retval false RX character not ready - */ -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if SS deactiviation detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return SS deactiviation state - * \retval true SS deactiviation detected - * \retval false SS deactiviation not detected - */ -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if error is detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return Error detection state - * \retval true Error detected - * \retval false Error not detected - */ -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h index dc88648..03aad78 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_spi_sync.h @@ -1,70 +1,70 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_SYNC_H_INCLUDED -#define _HPL_SPI_SYNC_H_INCLUDED - -#include -#include - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * \section hpl_spi_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI driver to support sync HAL */ -struct _spi_sync_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; -}; - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h index 9bdfbb7..f77a71d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_timer.h @@ -1,160 +1,160 @@ -/** - * \file - * - * \brief Timer related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIMER_H_INCLUDED -#define _HPL_TIMER_H_INCLUDED - -/** - * \addtogroup HPL Timer - * - * \section hpl_timer_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Timer device structure - * - * The Timer device structure forward declaration. - */ -struct _timer_device; - -/** - * \brief Timer interrupt callbacks - */ -struct _timer_callbacks { - void (*period_expired)(struct _timer_device *device); -}; - -/** - * \brief Timer device structure - */ -struct _timer_device { - struct _timer_callbacks timer_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief Timer functions, pointers to low-level functions - */ -struct _timer_hpl_interface { - int32_t (*init)(struct _timer_device *const device, void *const hw); - void (*deinit)(struct _timer_device *const device); - void (*start_timer)(struct _timer_device *const device); - void (*stop_timer)(struct _timer_device *const device); - void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); - uint32_t (*get_period)(const struct _timer_device *const device); - bool (*is_timer_started)(const struct _timer_device *const device); - void (*set_timer_irq)(struct _timer_device *const device); -}; -/** - * \brief Initialize TCC - * - * This function does low level TCC configuration. - * - * \param[in] device The pointer to timer device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _timer_init(struct _timer_device *const device, void *const hw); - -/** - * \brief Deinitialize TCC - * - * \param[in] device The pointer to timer device instance - */ -void _timer_deinit(struct _timer_device *const device); - -/** - * \brief Start hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_start(struct _timer_device *const device); - -/** - * \brief Stop hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_stop(struct _timer_device *const device); - -/** - * \brief Set timer period - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); - -/** - * \brief Retrieve timer period - * - * \param[in] device The pointer to timer device instance - * - * \return Timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const device); - -/** - * \brief Check if timer is running - * - * \param[in] device The pointer to timer device instance - * - * \return Check status. - * \retval true The given timer is running - * \retval false The given timer is not running - */ -bool _timer_is_started(const struct _timer_device *const device); - -/** - * \brief Set timer IRQ - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_irq(struct _timer_device *const device); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIMER_H_INCLUDED */ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart.h index 0e09501..b8ccd89 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart.h @@ -1,113 +1,113 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_H_INCLUDED -#define _HPL_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART flow control state - */ -union usart_flow_control_state { - struct { - uint8_t cts : 1; - uint8_t rts : 1; - uint8_t unavailable : 1; - uint8_t reserved : 5; - } bit; - uint8_t value; -}; - -/** - * \brief USART baud rate mode - */ -enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; - -/** - * \brief USART data order - */ -enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; - -/** - * \brief USART mode - */ -enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; - -/** - * \brief USART parity - */ -enum usart_parity { - USART_PARITY_EVEN = 0, - USART_PARITY_ODD = 1, - USART_PARITY_NONE = 2, - USART_PARITY_SPACE = 3, - USART_PARITY_MARK = 4 -}; - -/** - * \brief USART stop bits mode - */ -enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; - -/** - * \brief USART character size - */ -enum usart_character_size { - USART_CHARACTER_SIZE_8BITS = 0, - USART_CHARACTER_SIZE_9BITS = 1, - USART_CHARACTER_SIZE_5BITS = 5, - USART_CHARACTER_SIZE_6BITS = 6, - USART_CHARACTER_SIZE_7BITS = 7 -}; - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_H_INCLUDED */ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_async.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_async.h index 3f833d1..c227b62 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_async.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_async.h @@ -1,270 +1,270 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_ASYNC_H_INCLUDED -#define _HPL_USART_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL USART - * - * \section hpl_usart_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_usart.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART callback types - */ -enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; - -/** - * \brief USART device structure - * - * The USART device structure forward declaration. - */ -struct _usart_async_device; - -/** - * \brief USART interrupt callbacks - */ -struct _usart_async_callbacks { - void (*tx_byte_sent)(struct _usart_async_device *device); - void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); - void (*tx_done_cb)(struct _usart_async_device *device); - void (*error_cb)(struct _usart_async_device *device); -}; - -/** - * \brief USART descriptor device structure - */ -struct _usart_async_device { - struct _usart_async_callbacks usart_cb; - struct _irq_descriptor irq; - void * hw; -}; -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize asynchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_deinit(struct _usart_async_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable(struct _usart_async_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_disable(struct _usart_async_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); - -/** - * \brief Enable data register empty interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); - -/** - * \brief Enable transmission complete interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); - -/** - * \brief Enable/disable USART interrupt - * - * param[in] device The pointer to USART device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_ASYNC_H_INCLUDED */ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h index abc7264..228f64d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/include/hpl_usart_sync.h @@ -1,254 +1,254 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SYNC_USART_H_INCLUDED -#define _HPL_SYNC_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART descriptor device structure - */ -struct _usart_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_deinit(struct _usart_sync_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_enable(struct _usart_sync_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_disable(struct _usart_sync_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); - -/** - * \brief Read a byte from the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - * - * \return Data received via USART interface. - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART transmitter has sent the byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART transmitter has sent the byte - * \retval false if the USART transmitter has not send the byte - */ -bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); - -/** - * \brief Check if there is data received by USART - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the data received check. - * \retval true if the USART has received a byte - * \retval false if the USART has not received a byte - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SYNC_USART_H_INCLUDED */ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_atomic.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_atomic.c index f56418e..a4517e7 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_atomic.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_atomic.c @@ -1,66 +1,66 @@ -/** - * \file - * - * \brief Critical sections related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_atomic.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Disable interrupts, enter critical section - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic) -{ - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); -} - -/** - * \brief Exit atomic section - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic) -{ - __DMB(); - __set_PRIMASK(*atomic); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t atomic_get_version(void) -{ - return DRIVER_VERSION; -} +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c index b2e75aa..8968c77 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_cache.c @@ -1,78 +1,78 @@ -/** - * \file - * - * \brief HAL cache functionality implementation. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#include -#include - -/** - * \brief Initialize cache module - */ -int32_t cache_init(void) -{ - return _cmcc_init(); -} - -/** - * \brief Enable cache module - */ -int32_t cache_enable(const void *hw) -{ - return _cmcc_enable(hw); -} - -/** - * \brief Disable cache module - */ -int32_t cache_disable(const void *hw) -{ - return _cmcc_disable(hw); -} - -/** - * \brief Configure cache module - */ -int32_t cache_configure(const void *hw, struct _cache_cfg *cache) -{ - return _cmcc_configure(hw, cache); -} - -/** - * \brief Invalidate entire cache entries - */ -int32_t cache_invalidate_all(const void *hw) -{ - return _cmcc_invalidate_all(hw); -} +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include + +/** + * \brief Initialize cache module + */ +int32_t cache_init(void) +{ + return _cmcc_init(); +} + +/** + * \brief Enable cache module + */ +int32_t cache_enable(const void *hw) +{ + return _cmcc_enable(hw); +} + +/** + * \brief Disable cache module + */ +int32_t cache_disable(const void *hw) +{ + return _cmcc_disable(hw); +} + +/** + * \brief Configure cache module + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache) +{ + return _cmcc_configure(hw, cache); +} + +/** + * \brief Invalidate entire cache entries + */ +int32_t cache_invalidate_all(const void *hw) +{ + return _cmcc_invalidate_all(hw); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_delay.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_delay.c index 6f77cc7..9150314 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_delay.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_delay.c @@ -1,80 +1,80 @@ -/** - * \file - * - * \brief HAL delay related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include "hal_delay.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief The pointer to a hardware instance used by the driver. - */ -static void *hardware; - -/** - * \brief Initialize Delay driver - */ -void delay_init(void *const hw) -{ - _delay_init(hardware = hw); -} - -/** - * \brief Perform delay in us - */ -void delay_us(const uint16_t us) -{ - _delay_cycles(hardware, _get_cycles_for_us(us)); -} - -/** - * \brief Perform delay in ms - */ -void delay_ms(const uint16_t ms) -{ - _delay_cycles(hardware, _get_cycles_for_ms(ms)); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t delay_get_version(void) -{ - return DRIVER_VERSION; -} +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c index 2c1608c..3e6a1cf 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_ext_irq.c @@ -1,188 +1,188 @@ -/** - * \file - * - * \brief External interrupt functionality imkplementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_ext_irq.h" - -#define EXT_IRQ_AMOUNT 0 - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief External IRQ struct - */ -struct ext_irq { - ext_irq_cb_t cb; - uint32_t pin; -}; - -/* Remove KEIL compiling error in case no IRQ line selected */ -#if EXT_IRQ_AMOUNT == 0 -#undef EXT_IRQ_AMOUNT -#define EXT_IRQ_AMOUNT 1 -#endif - -/** - * \brief Array of external IRQs callbacks - */ -static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT]; - -static void process_ext_irq(const uint32_t pin); - -/** - * \brief Initialize external irq component if any - */ -int32_t ext_irq_init(void) -{ - uint16_t i; - - for (i = 0; i < EXT_IRQ_AMOUNT; i++) { - ext_irqs[i].pin = 0xFFFFFFFF; - ext_irqs[i].cb = NULL; - } - - return _ext_irq_init(process_ext_irq); -} - -/** - * \brief Deinitialize external irq if any - */ -int32_t ext_irq_deinit(void) -{ - return _ext_irq_deinit(); -} - -/** - * \brief Register callback for the given external interrupt - */ -int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb) -{ - uint8_t i = 0, j = 0; - bool found = false; - - for (; i < EXT_IRQ_AMOUNT; i++) { - if (ext_irqs[i].pin == pin) { - ext_irqs[i].cb = cb; - found = true; - break; - } - } - - if (NULL == cb) { - if (!found) { - return ERR_INVALID_ARG; - } - return _ext_irq_enable(pin, false); - } - - if (!found) { - for (i = 0; i < EXT_IRQ_AMOUNT; i++) { - if (NULL == ext_irqs[i].cb) { - ext_irqs[i].cb = cb; - ext_irqs[i].pin = pin; - found = true; - break; - } - } - for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) { - if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) { - struct ext_irq tmp = ext_irqs[j]; - - ext_irqs[j] = ext_irqs[i]; - ext_irqs[i] = tmp; - } - } - } - - if (!found) { - return ERR_INVALID_ARG; - } - - return _ext_irq_enable(pin, true); -} - -/** - * \brief Enable external irq - */ -int32_t ext_irq_enable(const uint32_t pin) -{ - return _ext_irq_enable(pin, true); -} - -/** - * \brief Disable external irq - */ -int32_t ext_irq_disable(const uint32_t pin) -{ - return _ext_irq_enable(pin, false); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t ext_irq_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \brief Interrupt processing routine - * - * \param[in] pin The pin which triggered the interrupt - */ -static void process_ext_irq(const uint32_t pin) -{ - uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; - - while (upper >= lower) { - middle = (upper + lower) >> 1; - if (middle >= EXT_IRQ_AMOUNT) { - return; - } - - if (ext_irqs[middle].pin == pin) { - if (ext_irqs[middle].cb) { - ext_irqs[middle].cb(); - } - return; - } - - if (ext_irqs[middle].pin < pin) { - lower = middle + 1; - } else { - upper = middle - 1; - } - } -} +/** + * \file + * + * \brief External interrupt functionality imkplementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_ext_irq.h" + +#define EXT_IRQ_AMOUNT 0 + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief External IRQ struct + */ +struct ext_irq { + ext_irq_cb_t cb; + uint32_t pin; +}; + +/* Remove KEIL compiling error in case no IRQ line selected */ +#if EXT_IRQ_AMOUNT == 0 +#undef EXT_IRQ_AMOUNT +#define EXT_IRQ_AMOUNT 1 +#endif + +/** + * \brief Array of external IRQs callbacks + */ +static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT]; + +static void process_ext_irq(const uint32_t pin); + +/** + * \brief Initialize external irq component if any + */ +int32_t ext_irq_init(void) +{ + uint16_t i; + + for (i = 0; i < EXT_IRQ_AMOUNT; i++) { + ext_irqs[i].pin = 0xFFFFFFFF; + ext_irqs[i].cb = NULL; + } + + return _ext_irq_init(process_ext_irq); +} + +/** + * \brief Deinitialize external irq if any + */ +int32_t ext_irq_deinit(void) +{ + return _ext_irq_deinit(); +} + +/** + * \brief Register callback for the given external interrupt + */ +int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb) +{ + uint8_t i = 0, j = 0; + bool found = false; + + for (; i < EXT_IRQ_AMOUNT; i++) { + if (ext_irqs[i].pin == pin) { + ext_irqs[i].cb = cb; + found = true; + break; + } + } + + if (NULL == cb) { + if (!found) { + return ERR_INVALID_ARG; + } + return _ext_irq_enable(pin, false); + } + + if (!found) { + for (i = 0; i < EXT_IRQ_AMOUNT; i++) { + if (NULL == ext_irqs[i].cb) { + ext_irqs[i].cb = cb; + ext_irqs[i].pin = pin; + found = true; + break; + } + } + for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) { + if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) { + struct ext_irq tmp = ext_irqs[j]; + + ext_irqs[j] = ext_irqs[i]; + ext_irqs[i] = tmp; + } + } + } + + if (!found) { + return ERR_INVALID_ARG; + } + + return _ext_irq_enable(pin, true); +} + +/** + * \brief Enable external irq + */ +int32_t ext_irq_enable(const uint32_t pin) +{ + return _ext_irq_enable(pin, true); +} + +/** + * \brief Disable external irq + */ +int32_t ext_irq_disable(const uint32_t pin) +{ + return _ext_irq_enable(pin, false); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t ext_irq_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief Interrupt processing routine + * + * \param[in] pin The pin which triggered the interrupt + */ +static void process_ext_irq(const uint32_t pin) +{ + uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; + + while (upper >= lower) { + middle = (upper + lower) >> 1; + if (middle >= EXT_IRQ_AMOUNT) { + return; + } + + if (ext_irqs[middle].pin == pin) { + if (ext_irqs[middle].cb) { + ext_irqs[middle].cb(); + } + return; + } + + if (ext_irqs[middle].pin < pin) { + lower = middle + 1; + } else { + upper = middle - 1; + } + } +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c index 00dfea6..27bed95 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_gpio.c @@ -1,44 +1,44 @@ -/** - * \file - * - * \brief Port - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_gpio.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t gpio_get_version(void) -{ - return DRIVER_VERSION; -} +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_i2c_m_sync.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_i2c_m_sync.c index 30821a2..7e87d37 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_i2c_m_sync.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_i2c_m_sync.c @@ -1,258 +1,258 @@ -/** - * \file - * - * \brief I/O I2C related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Sync version of I2C I/O read - */ -static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = n; - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of I2C I/O write - */ -static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = n; - msg.flags = I2C_M_STOP; - msg.buffer = (uint8_t *)buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of i2c initialize - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) -{ - int32_t init_status; - ASSERT(i2c); - - init_status = _i2c_m_sync_init(&i2c->device, hw); - if (init_status) { - return init_status; - } - - /* Init I/O */ - i2c->io.read = i2c_m_sync_read; - i2c->io.write = i2c_m_sync_write; - - return ERR_NONE; -} - -/** - * \brief deinitialize - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) -{ - int32_t status; - ASSERT(i2c); - - status = _i2c_m_sync_deinit(&i2c->device); - if (status) { - return status; - } - - i2c->io.read = NULL; - i2c->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c enable - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_enable(&i2c->device); -} - -/** - * \brief Sync version of i2c disable - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_disable(&i2c->device); -} - -/** - * \brief Sync version of i2c set slave address - */ -int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) -{ - return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); -} - -/** - * \brief Sync version of i2c set baudrate - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) -{ - return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); -} - -/** - * \brief Sync version of i2c write command - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c read command - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c transfer command - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) -{ - return _i2c_m_sync_transfer(&i2c->device, msg); -} - -/** - * \brief Sync version of i2c send stop condition command - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) -{ - return _i2c_m_sync_send_stop(&i2c->device); -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) -{ - *io = &i2c->io; - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t i2c_m_sync_get_version(void) -{ - return DRIVER_VERSION; -} +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set slave address + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_init.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_init.c index fb65341..cc4ccdb 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_init.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_init.c @@ -1,47 +1,47 @@ -/** - * \file - * - * \brief HAL initialization related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_init.h" - -/** - * \brief Driver version - */ -#define HAL_INIT_VERSION 0x00000001u - -/** - * \brief Retrieve the current driver version - */ -uint32_t init_get_version(void) -{ - return HAL_INIT_VERSION; -} +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_io.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_io.c index 7e8feb0..79c7562 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_io.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_io.c @@ -1,63 +1,63 @@ -/** - * \file - * - * \brief I/O functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t io_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \brief I/O write interface - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->write(io_descr, buf, length); -} - -/** - * \brief I/O read interface - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->read(io_descr, buf, length); -} +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_sleep.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_sleep.c index 89472f1..8e0283c 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_sleep.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_sleep.c @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Sleep related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_sleep.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode) -{ - if (ERR_NONE != _set_sleep_mode(mode)) - return ERR_INVALID_ARG; - - _go_to_sleep(); - - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version - */ -uint32_t sleep_get_version(void) -{ - return DRIVER_VERSION; -} +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_timer.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_timer.c index 565c6db..b08670f 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_timer.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_timer.c @@ -1,250 +1,250 @@ -/** - * \file - * - * \brief Timer functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_timer.h" -#include -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Timer flags - */ -#define TIMER_FLAG_QUEUE_IS_TAKEN 1 -#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 - -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); -static void timer_process_counted(struct _timer_device *device); - -/** - * \brief Initialize timer - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) -{ - ASSERT(descr && hw); - _timer_init(&descr->device, hw); - descr->time = 0; - descr->device.timer_cb.period_expired = timer_process_counted; - - return ERR_NONE; -} - -/** - * \brief Deinitialize timer - */ -int32_t timer_deinit(struct timer_descriptor *const descr) -{ - ASSERT(descr); - _timer_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Start timer - */ -int32_t timer_start(struct timer_descriptor *const descr) -{ - ASSERT(descr); - if (_timer_is_started(&descr->device)) { - return ERR_DENIED; - } - _timer_start(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Stop timer - */ -int32_t timer_stop(struct timer_descriptor *const descr) -{ - ASSERT(descr); - if (!_timer_is_started(&descr->device)) { - return ERR_DENIED; - } - _timer_stop(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Set amount of clock cycler per timer tick - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) -{ - ASSERT(descr); - _timer_set_period(&descr->device, clock_cycles); - - return ERR_NONE; -} - -/** - * \brief Add timer task - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) -{ - ASSERT(descr && task); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_ALREADY_INITIALIZED; - } - task->time_label = descr->time; - timer_add_timer_task(&descr->tasks, task, descr->time); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - _timer_set_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Remove timer task - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) -{ - ASSERT(descr && task); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (!is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_NOT_FOUND; - } - list_delete_element(&descr->tasks, task); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - _timer_set_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Retrieve the amount of clock cycles in a tick - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) -{ - ASSERT(descr && cycles); - *cycles = _timer_get_period(&descr->device); - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t timer_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal Insert a timer task into sorted timer's list - * - * \param[in] head The pointer to the head of timer task list - * \param[in] task The pointer to task to add - * \param[in] time Current timer time - */ -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) -{ - struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); - - if (!head) { - list_insert_as_head(list, new_task); - return; - } - - for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { - uint32_t time_left; - - if (it->time_label <= time) { - time_left = it->interval - (time - it->time_label); - } else { - time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; - } - if (time_left >= new_task->interval) - break; - prev = it; - } - - if (it == head) { - list_insert_as_head(list, new_task); - } else { - list_insert_after(prev, new_task); - } -} - -/** - * \internal Process interrupts - */ -static void timer_process_counted(struct _timer_device *device) -{ - struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); - struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); - uint32_t time = ++timer->time; - - if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { - timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; - return; - } - - while (it && ((time - it->time_label) >= it->interval)) { - struct timer_task *tmp = it; - - list_remove_head(&timer->tasks); - if (TIMER_TASK_REPEAT == tmp->mode) { - tmp->time_label = time; - timer_add_timer_task(&timer->tasks, tmp, time); - } - it = (struct timer_task *)list_get_head(&timer->tasks); - - tmp->cb(tmp); - } -} +/** + * \file + * + * \brief Timer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_timer.h" +#include +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Timer flags + */ +#define TIMER_FLAG_QUEUE_IS_TAKEN 1 +#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 + +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); +static void timer_process_counted(struct _timer_device *device); + +/** + * \brief Initialize timer + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) +{ + ASSERT(descr && hw); + _timer_init(&descr->device, hw); + descr->time = 0; + descr->device.timer_cb.period_expired = timer_process_counted; + + return ERR_NONE; +} + +/** + * \brief Deinitialize timer + */ +int32_t timer_deinit(struct timer_descriptor *const descr) +{ + ASSERT(descr); + _timer_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start timer + */ +int32_t timer_start(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_start(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop timer + */ +int32_t timer_stop(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (!_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_stop(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Set amount of clock cycler per timer tick + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) +{ + ASSERT(descr); + _timer_set_period(&descr->device, clock_cycles); + + return ERR_NONE; +} + +/** + * \brief Add timer task + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_ALREADY_INITIALIZED; + } + task->time_label = descr->time; + timer_add_timer_task(&descr->tasks, task, descr->time); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Remove timer task + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Retrieve the amount of clock cycles in a tick + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) +{ + ASSERT(descr && cycles); + *cycles = _timer_get_period(&descr->device); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t timer_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Insert a timer task into sorted timer's list + * + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + list_insert_as_head(list, new_task); + return; + } + + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + uint32_t time_left; + + if (it->time_label <= time) { + time_left = it->interval - (time - it->time_label); + } else { + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + } + if (time_left >= new_task->interval) + break; + prev = it; + } + + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + return; + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + } +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c index f07b266..506d31a 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/src/hal_usart_async.c @@ -1,420 +1,420 @@ -/** - * \file - * - * \brief I/O USART related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include "hal_usart_async.h" -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); -static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); -static void usart_process_byte_sent(struct _usart_async_device *device); -static void usart_transmission_complete(struct _usart_async_device *device); -static void usart_error(struct _usart_async_device *device); -static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data); - -/** - * \brief Initialize usart interface - */ -int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *rx_buffer, - uint16_t rx_buffer_length, void *const func) -{ - int32_t init_status; - ASSERT(descr && hw && rx_buffer && rx_buffer_length); - - if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { - return ERR_INVALID_ARG; - } - init_status = _usart_async_init(&descr->device, hw); - if (init_status) { - return init_status; - } - - descr->io.read = usart_async_read; - descr->io.write = usart_async_write; - - descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; - descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; - descr->device.usart_cb.tx_done_cb = usart_transmission_complete; - descr->device.usart_cb.error_cb = usart_error; - - return ERR_NONE; -} - -/** - * \brief Deinitialize usart interface - */ -int32_t usart_async_deinit(struct usart_async_descriptor *const descr) -{ - ASSERT(descr); - _usart_async_deinit(&descr->device); - descr->io.read = NULL; - descr->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable usart interface - */ -int32_t usart_async_enable(struct usart_async_descriptor *const descr) -{ - ASSERT(descr); - _usart_async_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Disable usart interface - */ -int32_t usart_async_disable(struct usart_async_descriptor *const descr) -{ - ASSERT(descr); - _usart_async_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io) -{ - ASSERT(descr && io); - - *io = &descr->io; - return ERR_NONE; -} - -/** - * \brief Register usart callback - */ -int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, - const enum usart_async_callback_type type, usart_cb_t cb) -{ - ASSERT(descr); - - switch (type) { - case USART_ASYNC_RXC_CB: - descr->usart_cb.rx_done = cb; - _usart_async_set_irq_state(&descr->device, USART_ASYNC_RX_DONE, NULL != cb); - break; - case USART_ASYNC_TXC_CB: - descr->usart_cb.tx_done = cb; - _usart_async_set_irq_state(&descr->device, USART_ASYNC_TX_DONE, NULL != cb); - break; - case USART_ASYNC_ERROR_CB: - descr->usart_cb.error = cb; - _usart_async_set_irq_state(&descr->device, USART_ASYNC_ERROR, NULL != cb); - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Specify action for flow control pins - */ -int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, - const union usart_flow_control_state state) -{ - ASSERT(descr); - _usart_async_set_flow_control_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Set usart baud rate - */ -int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate) -{ - ASSERT(descr); - _usart_async_set_baud_rate(&descr->device, baud_rate); - - return ERR_NONE; -} - -/** - * \brief Set usart data order - */ -int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order) -{ - ASSERT(descr); - _usart_async_set_data_order(&descr->device, data_order); - - return ERR_NONE; -} - -/** - * \brief Set usart mode - */ -int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode) -{ - ASSERT(descr); - _usart_async_set_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set usart parity - */ -int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity) -{ - ASSERT(descr); - _usart_async_set_parity(&descr->device, parity); - - return ERR_NONE; -} - -/** - * \brief Set usart stop bits - */ -int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits) -{ - ASSERT(descr); - _usart_async_set_stop_bits(&descr->device, stop_bits); - - return ERR_NONE; -} - -/** - * \brief Set usart character size - */ -int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, const enum usart_character_size size) -{ - ASSERT(descr); - _usart_async_set_character_size(&descr->device, size); - - return ERR_NONE; -} - -/** - * \brief Retrieve the state of flow control pins - */ -int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, - union usart_flow_control_state *const state) -{ - ASSERT(descr && state); - *state = _usart_async_get_flow_control_state(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Check if the usart transmitter is empty - */ -int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr) -{ - ASSERT(descr); - return _usart_async_is_byte_sent(&descr->device); -} - -/** - * \brief Check if the usart receiver is not empty - */ -int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr) -{ - ASSERT(descr); - - return ringbuffer_num(&descr->rx) > 0; -} - -/** - * \brief Retrieve the current interface status - */ -int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status) -{ - ASSERT(descr); - - volatile uint32_t *tmp_stat = &(descr->stat); - volatile uint16_t *tmp_txcnt = &(descr->tx_por); - - if (status) { - status->flags = *tmp_stat; - status->txcnt = *tmp_txcnt; - status->rxcnt = ringbuffer_num(&descr->rx); - } - if (*tmp_stat & USART_ASYNC_STATUS_BUSY) { - return ERR_BUSY; - } - - return ERR_NONE; -} - -/** - * \brief flush usart rx ringbuf - */ -int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr) -{ - ASSERT(descr); - - return ringbuffer_flush(&descr->rx); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t usart_async_get_version(void) -{ - return DRIVER_VERSION; -} - -/* - * \internal Write the given data to usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf Data to write to usart - * \param[in] length The number of bytes to write - * - * \return The number of bytes written. - */ -static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); - - ASSERT(descr && buf && length); - - if (descr->tx_por != descr->tx_buffer_length) { - return ERR_NO_RESOURCE; - } - descr->tx_buffer = (uint8_t *)buf; - descr->tx_buffer_length = length; - descr->tx_por = 0; - descr->stat = USART_ASYNC_STATUS_BUSY; - _usart_async_enable_byte_sent_irq(&descr->device); - - return (int32_t)length; -} - -/* - * \internal Read data from usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - uint16_t was_read = 0; - uint32_t num; - struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); - - ASSERT(descr && buf && length); - - CRITICAL_SECTION_ENTER() - num = ringbuffer_num(&descr->rx); - CRITICAL_SECTION_LEAVE() - - while ((was_read < num) && (was_read < length)) { - ringbuffer_get(&descr->rx, &buf[was_read++]); - } - - return (int32_t)was_read; -} - -/** - * \brief Process "byte is sent" interrupt - * - * \param[in] device The pointer to device structure - */ -static void usart_process_byte_sent(struct _usart_async_device *device) -{ - struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); - if (descr->tx_por != descr->tx_buffer_length) { - _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); - _usart_async_enable_byte_sent_irq(&descr->device); - } else { - _usart_async_enable_tx_done_irq(&descr->device); - } -} - -/** - * \brief Process completion of data sending - * - * \param[in] device The pointer to device structure - */ -static void usart_transmission_complete(struct _usart_async_device *device) -{ - struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); - - descr->stat = 0; - if (descr->usart_cb.tx_done) { - descr->usart_cb.tx_done(descr); - } -} - -/** - * \brief Process byte reception - * - * \param[in] device The pointer to device structure - * \param[in] data Data read - */ -static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data) -{ - struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); - - ringbuffer_put(&descr->rx, data); - - if (descr->usart_cb.rx_done) { - descr->usart_cb.rx_done(descr); - } -} - -/** - * \brief Process error interrupt - * - * \param[in] device The pointer to device structure - */ -static void usart_error(struct _usart_async_device *device) -{ - struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); - - descr->stat = 0; - if (descr->usart_cb.error) { - descr->usart_cb.error(descr); - } -} - -//@} +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_async.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); +static void usart_process_byte_sent(struct _usart_async_device *device); +static void usart_transmission_complete(struct _usart_async_device *device); +static void usart_error(struct _usart_async_device *device); +static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data); + +/** + * \brief Initialize usart interface + */ +int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *rx_buffer, + uint16_t rx_buffer_length, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw && rx_buffer && rx_buffer_length); + + if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { + return ERR_INVALID_ARG; + } + init_status = _usart_async_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_async_read; + descr->io.write = usart_async_write; + + descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; + descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; + descr->device.usart_cb.tx_done_cb = usart_transmission_complete; + descr->device.usart_cb.error_cb = usart_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize usart interface + */ +int32_t usart_async_deinit(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_deinit(&descr->device); + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_async_enable(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_async_disable(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Register usart callback + */ +int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, + const enum usart_async_callback_type type, usart_cb_t cb) +{ + ASSERT(descr); + + switch (type) { + case USART_ASYNC_RXC_CB: + descr->usart_cb.rx_done = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_RX_DONE, NULL != cb); + break; + case USART_ASYNC_TXC_CB: + descr->usart_cb.tx_done = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_TX_DONE, NULL != cb); + break; + case USART_ASYNC_ERROR_CB: + descr->usart_cb.error = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_ERROR, NULL != cb); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_async_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_async_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_async_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_async_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_async_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_async_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_async_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_async_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + return _usart_async_is_byte_sent(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + + return ringbuffer_num(&descr->rx) > 0; +} + +/** + * \brief Retrieve the current interface status + */ +int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status) +{ + ASSERT(descr); + + volatile uint32_t *tmp_stat = &(descr->stat); + volatile uint16_t *tmp_txcnt = &(descr->tx_por); + + if (status) { + status->flags = *tmp_stat; + status->txcnt = *tmp_txcnt; + status->rxcnt = ringbuffer_num(&descr->rx); + } + if (*tmp_stat & USART_ASYNC_STATUS_BUSY) { + return ERR_BUSY; + } + + return ERR_NONE; +} + +/** + * \brief flush usart rx ringbuf + */ +int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + + return ringbuffer_flush(&descr->rx); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_async_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); + + ASSERT(descr && buf && length); + + if (descr->tx_por != descr->tx_buffer_length) { + return ERR_NO_RESOURCE; + } + descr->tx_buffer = (uint8_t *)buf; + descr->tx_buffer_length = length; + descr->tx_por = 0; + descr->stat = USART_ASYNC_STATUS_BUSY; + _usart_async_enable_byte_sent_irq(&descr->device); + + return (int32_t)length; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint16_t was_read = 0; + uint32_t num; + struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); + + ASSERT(descr && buf && length); + + CRITICAL_SECTION_ENTER() + num = ringbuffer_num(&descr->rx); + CRITICAL_SECTION_LEAVE() + + while ((was_read < num) && (was_read < length)) { + ringbuffer_get(&descr->rx, &buf[was_read++]); + } + + return (int32_t)was_read; +} + +/** + * \brief Process "byte is sent" interrupt + * + * \param[in] device The pointer to device structure + */ +static void usart_process_byte_sent(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + if (descr->tx_por != descr->tx_buffer_length) { + _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); + _usart_async_enable_byte_sent_irq(&descr->device); + } else { + _usart_async_enable_tx_done_irq(&descr->device); + } +} + +/** + * \brief Process completion of data sending + * + * \param[in] device The pointer to device structure + */ +static void usart_transmission_complete(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + if (descr->usart_cb.tx_done) { + descr->usart_cb.tx_done(descr); + } +} + +/** + * \brief Process byte reception + * + * \param[in] device The pointer to device structure + * \param[in] data Data read + */ +static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + ringbuffer_put(&descr->rx, data); + + if (descr->usart_cb.rx_done) { + descr->usart_cb.rx_done(descr); + } +} + +/** + * \brief Process error interrupt + * + * \param[in] device The pointer to device structure + */ +static void usart_error(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + if (descr->usart_cb.error) { + descr->usart_cb.error(descr); + } +} + +//@} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/compiler.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/compiler.h index f35db3d..15e9d28 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/compiler.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/compiler.h @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Header - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -/****************************************************************************** - * compiler.h - * - * Created: 05.05.2014 - * Author: N. Fomin - ******************************************************************************/ - -#ifndef _COMPILER_H -#define _COMPILER_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef _UNIT_TEST_ -#include "parts.h" -#endif -#include "err_codes.h" - -#ifdef __cplusplus -} -#endif - -#endif /* _COMPILER_H */ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/err_codes.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/err_codes.h index a7aff01..97d5a79 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/err_codes.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/err_codes.h @@ -1,73 +1,73 @@ -/** - * \file - * - * \brief Error code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef ERROR_CODES_H_INCLUDED -#define ERROR_CODES_H_INCLUDED - -#define ERR_NONE 0 -#define ERR_INVALID_DATA -1 -#define ERR_NO_CHANGE -2 -#define ERR_ABORTED -3 -#define ERR_BUSY -4 -#define ERR_SUSPEND -5 -#define ERR_IO -6 -#define ERR_REQ_FLUSHED -7 -#define ERR_TIMEOUT -8 -#define ERR_BAD_DATA -9 -#define ERR_NOT_FOUND -10 -#define ERR_UNSUPPORTED_DEV -11 -#define ERR_NO_MEMORY -12 -#define ERR_INVALID_ARG -13 -#define ERR_BAD_ADDRESS -14 -#define ERR_BAD_FORMAT -15 -#define ERR_BAD_FRQ -16 -#define ERR_DENIED -17 -#define ERR_ALREADY_INITIALIZED -18 -#define ERR_OVERFLOW -19 -#define ERR_NOT_INITIALIZED -20 -#define ERR_SAMPLERATE_UNAVAILABLE -21 -#define ERR_RESOLUTION_UNAVAILABLE -22 -#define ERR_BAUDRATE_UNAVAILABLE -23 -#define ERR_PACKET_COLLISION -24 -#define ERR_PROTOCOL -25 -#define ERR_PIN_MUX_INVALID -26 -#define ERR_UNSUPPORTED_OP -27 -#define ERR_NO_RESOURCE -28 -#define ERR_NOT_READY -29 -#define ERR_FAILURE -30 -#define ERR_WRONG_LENGTH -31 - -#endif +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/events.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/events.h index 3ee891a..23aeb2b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/events.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/events.h @@ -1,54 +1,54 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _EVENTS_H_INCLUDED -#define _EVENTS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \brief List of events. Must start with 0, be unique and follow numerical order. - */ -#define EVENT_IS_READY_TO_SLEEP_ID 0 -#define EVENT_PREPARE_TO_SLEEP_ID 1 -#define EVENT_WOKEN_UP_ID 2 - -#ifdef __cplusplus -} -#endif - -#endif /* _EVENTS_H_INCLUDED */ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/parts.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/parts.h index 98bb969..4a1d7e6 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/parts.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/parts.h @@ -1,41 +1,41 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -#include "same54.h" - -#include "hri_e54.h" - -#endif /* ATMEL_PARTS_H */ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "same54.h" + +#include "hri_e54.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils.h index 1cf2699..68108bf 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils.h @@ -1,368 +1,368 @@ -/** - * \file - * - * \brief Different macros. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_H_INCLUDED -#define UTILS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_macro - * - * @{ - */ - -/** - * \brief Retrieve pointer to parent structure - */ -#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) - -/** - * \brief Retrieve array size - */ -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - -/** - * \brief Set aligned boundary. - */ -#if defined __GNUC__ -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif defined __ICCARM__ -#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#elif defined __CC_ARM -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#endif - -/** - * \brief Flash located data macros - */ -#if defined __GNUC__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __ICCARM__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __CC_ARM -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#endif - -/** - * \brief Optimization - */ -#if defined __GNUC__ -#define OPTIMIZE_HIGH __attribute__((optimize(s))) -#elif defined __CC_ARM -#define OPTIMIZE_HIGH _Pragma("O3") -#elif defined __ICCARM__ -#define OPTIMIZE_HIGH _Pragma("optimize=high") -#endif - -/** - * \brief RAM located function attribute - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define RAMFUNC __ramfunc -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#endif - -/** - * \brief No-init section. - * Place a data object or a function in a no-init section. - */ -#if defined(__CC_ARM) -#define NO_INIT(a) __attribute__((zero_init)) -#elif defined(__ICCARM__) -#define NO_INIT(a) __no_init -#elif defined(__GNUC__) -#define NO_INIT(a) __attribute__((section(".no_init"))) -#endif - -/** - * \brief Set user-defined section. - * Place a data object or a function in a user-defined section. - */ -#if defined(__CC_ARM) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#elif defined(__ICCARM__) -#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) -#elif defined(__GNUC__) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#endif - -/** - * \brief Define WEAK attribute. - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define WEAK __attribute__((weak)) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define WEAK __weak -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define WEAK __attribute__((weak)) -#endif - -/** - * \brief Pointer to function - */ -typedef void (*FUNC_PTR)(void); - -#define LE_BYTE0(a) ((uint8_t)(a)) -#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) -#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) -#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) - -#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) -#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define clz(u) __builtin_clz(u) -#else -#define clz(u) \ - ( \ - ((u) == 0) \ - ? 32 \ - : ((u) & (1ul << 31)) \ - ? 0 \ - : ((u) & (1ul << 30)) \ - ? 1 \ - : ((u) & (1ul << 29)) \ - ? 2 \ - : ((u) & (1ul << 28)) \ - ? 3 \ - : ((u) & (1ul << 27)) \ - ? 4 \ - : ((u) & (1ul << 26)) \ - ? 5 \ - : ((u) & (1ul << 25)) \ - ? 6 \ - : ((u) & (1ul << 24)) \ - ? 7 \ - : ((u) & (1ul << 23)) \ - ? 8 \ - : ((u) & (1ul << 22)) \ - ? 9 \ - : ((u) & (1ul << 21)) \ - ? 10 \ - : ((u) & (1ul << 20)) \ - ? 11 \ - : ((u) & (1ul << 19)) \ - ? 12 \ - : ((u) & (1ul << 18)) \ - ? 13 \ - : ((u) & (1ul << 17)) ? 14 \ - : ((u) & (1ul << 16)) ? 15 \ - : ((u) & (1ul << 15)) ? 16 \ - : ((u) & (1ul << 14)) ? 17 \ - : ((u) & (1ul << 13)) ? 18 \ - : ((u) & (1ul << 12)) ? 19 \ - : ((u) \ - & (1ul \ - << 11)) \ - ? 20 \ - : ((u) \ - & (1ul \ - << 10)) \ - ? 21 \ - : ((u) \ - & (1ul \ - << 9)) \ - ? 22 \ - : ((u) \ - & (1ul \ - << 8)) \ - ? 23 \ - : ((u) & (1ul << 7)) ? 24 \ - : ((u) & (1ul << 6)) ? 25 \ - : ((u) \ - & (1ul \ - << 5)) \ - ? 26 \ - : ((u) & (1ul << 4)) ? 27 \ - : ((u) & (1ul << 3)) ? 28 \ - : ((u) & (1ul << 2)) ? 29 \ - : ( \ - (u) & (1ul << 1)) \ - ? 30 \ - : 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define ctz(u) __builtin_ctz(u) -#else -#define ctz(u) \ - ( \ - (u) & (1ul << 0) \ - ? 0 \ - : (u) & (1ul << 1) \ - ? 1 \ - : (u) & (1ul << 2) \ - ? 2 \ - : (u) & (1ul << 3) \ - ? 3 \ - : (u) & (1ul << 4) \ - ? 4 \ - : (u) & (1ul << 5) \ - ? 5 \ - : (u) & (1ul << 6) \ - ? 6 \ - : (u) & (1ul << 7) \ - ? 7 \ - : (u) & (1ul << 8) \ - ? 8 \ - : (u) & (1ul << 9) \ - ? 9 \ - : (u) & (1ul << 10) \ - ? 10 \ - : (u) & (1ul << 11) \ - ? 11 \ - : (u) & (1ul << 12) \ - ? 12 \ - : (u) & (1ul << 13) \ - ? 13 \ - : (u) & (1ul << 14) \ - ? 14 \ - : (u) & (1ul << 15) \ - ? 15 \ - : (u) & (1ul << 16) \ - ? 16 \ - : (u) & (1ul << 17) \ - ? 17 \ - : (u) & (1ul << 18) \ - ? 18 \ - : (u) & (1ul << 19) ? 19 \ - : (u) & (1ul << 20) ? 20 \ - : (u) & (1ul << 21) ? 21 \ - : (u) & (1ul << 22) ? 22 \ - : (u) & (1ul << 23) ? 23 \ - : (u) & (1ul << 24) ? 24 \ - : (u) & (1ul << 25) ? 25 \ - : (u) & (1ul << 26) ? 26 \ - : (u) & (1ul << 27) ? 27 \ - : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) -#endif -/** @} */ - -/** - * \brief Counts the number of bits in a mask (no more than 32 bits) - * \param[in] mask Mask of which to count the bits. - */ -#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) - -/** - * \brief Retrieve the start position of bits mask (no more than 32 bits) - * \param[in] mask Mask of which to retrieve the start position. - */ -#define pos_of_mask(mask) ctz(mask) - -/** - * \brief Return division result of a/b and round up the result to the closest - * number divisible by "b" - */ -#define round_up(a, b) (((a)-1) / (b) + 1) - -/** - * \brief Get the minimum of x and y - */ -#define min(x, y) ((x) > (y) ? (y) : (x)) - -/** - * \brief Get the maximum of x and y - */ -#define max(x, y) ((x) > (y) ? (x) : (y)) - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* UTILS_H_INCLUDED */ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_assert.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_assert.h index c2328d6..b357145 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_assert.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_assert.h @@ -1,93 +1,93 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _ASSERT_H_INCLUDED -#define _ASSERT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifndef USE_SIMPLE_ASSERT -//# define USE_SIMPLE_ASSERT -#endif - -/** - * \brief Assert macro - * - * This macro is used to throw asserts. It can be mapped to different function - * based on debug level. - * - * \param[in] condition A condition to be checked; - * assert is thrown if the given condition is false - */ -#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) - -#ifdef DEBUG - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) \ - if (!(condition)) \ - __asm("BKPT #0"); -#else -#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) -#endif - -#else /* DEBUG */ - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) ((void)0) -#else -#define ASSERT_IMPL(condition, file, line) ((void)0) -#endif - -#endif /* DEBUG */ - -/** - * \brief Assert function - * - * This function is used to throw asserts. - * - * \param[in] condition A condition to be checked; assert is thrown if the given - * condition is false - * \param[in] file File name - * \param[in] line Line number - */ -void assert(const bool condition, const char *const file, const int line); - -#ifdef __cplusplus -} -#endif -#endif /* _ASSERT_H_INCLUDED */ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_event.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_event.h index 13067c4..68ef36b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_event.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_event.h @@ -1,115 +1,115 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_EVENT_H_INCLUDED -#define _UTILS_EVENT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \brief The maximum amount of events - */ -#define EVENT_MAX_AMOUNT 8 - -/** - * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the - * closest number divisible by 8. - */ -#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) - -/** - * \brief The type of event ID. IDs should start with 0 and be in numerical order. - */ -typedef uint8_t event_id_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef uintptr_t event_data_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef void (*event_cb_t)(event_id_t id, event_data_t data); - -/** - * \brief Event structure - */ -struct event { - struct list_element elem; /*! The pointer to next event */ - uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ - event_cb_t cb; /*! Callback to be called when an event occurs */ -}; - -/** - * \brief Subscribe to event - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to subscribe to - * \param[in] cb The callback function to call when the given event occurs - * - * \return The status of subscription - */ -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); - -/** - * \brief Remove event from subscription - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to remove subscription from - * - * \return The status of subscription removing - */ -int32_t event_unsubscribe(struct event *const event, const event_id_t id); - -/** - * \brief Post event - * - * \param[in] id The event ID to post - * \param[in] data The event data to be passed to event subscribers - */ -void event_post(const event_id_t id, const event_data_t data); - -#ifdef __cplusplus -} -#endif - -#endif /* _UTILS_EVENT_H_INCLUDED */ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_increment_macro.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_increment_macro.h index 464c6cb..4fe734a 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_increment_macro.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_increment_macro.h @@ -1,308 +1,308 @@ -/** - * \file - * - * \brief Increment macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_INCREMENT_MACRO_H -#define _UTILS_INCREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time increment, result value is entire integer literal - * - * \param[in] val - value to be incremented (254 max) - */ -#define INC_VALUE(val) SP_INC_##val - -// Preprocessor increment implementation -#define SP_INC_0 1 -#define SP_INC_1 2 -#define SP_INC_2 3 -#define SP_INC_3 4 -#define SP_INC_4 5 -#define SP_INC_5 6 -#define SP_INC_6 7 -#define SP_INC_7 8 -#define SP_INC_8 9 -#define SP_INC_9 10 -#define SP_INC_10 11 -#define SP_INC_11 12 -#define SP_INC_12 13 -#define SP_INC_13 14 -#define SP_INC_14 15 -#define SP_INC_15 16 -#define SP_INC_16 17 -#define SP_INC_17 18 -#define SP_INC_18 19 -#define SP_INC_19 20 -#define SP_INC_20 21 -#define SP_INC_21 22 -#define SP_INC_22 23 -#define SP_INC_23 24 -#define SP_INC_24 25 -#define SP_INC_25 26 -#define SP_INC_26 27 -#define SP_INC_27 28 -#define SP_INC_28 29 -#define SP_INC_29 30 -#define SP_INC_30 31 -#define SP_INC_31 32 -#define SP_INC_32 33 -#define SP_INC_33 34 -#define SP_INC_34 35 -#define SP_INC_35 36 -#define SP_INC_36 37 -#define SP_INC_37 38 -#define SP_INC_38 39 -#define SP_INC_39 40 -#define SP_INC_40 41 -#define SP_INC_41 42 -#define SP_INC_42 43 -#define SP_INC_43 44 -#define SP_INC_44 45 -#define SP_INC_45 46 -#define SP_INC_46 47 -#define SP_INC_47 48 -#define SP_INC_48 49 -#define SP_INC_49 50 -#define SP_INC_50 51 -#define SP_INC_51 52 -#define SP_INC_52 53 -#define SP_INC_53 54 -#define SP_INC_54 55 -#define SP_INC_55 56 -#define SP_INC_56 57 -#define SP_INC_57 58 -#define SP_INC_58 59 -#define SP_INC_59 60 -#define SP_INC_60 61 -#define SP_INC_61 62 -#define SP_INC_62 63 -#define SP_INC_63 64 -#define SP_INC_64 65 -#define SP_INC_65 66 -#define SP_INC_66 67 -#define SP_INC_67 68 -#define SP_INC_68 69 -#define SP_INC_69 70 -#define SP_INC_70 71 -#define SP_INC_71 72 -#define SP_INC_72 73 -#define SP_INC_73 74 -#define SP_INC_74 75 -#define SP_INC_75 76 -#define SP_INC_76 77 -#define SP_INC_77 78 -#define SP_INC_78 79 -#define SP_INC_79 80 -#define SP_INC_80 81 -#define SP_INC_81 82 -#define SP_INC_82 83 -#define SP_INC_83 84 -#define SP_INC_84 85 -#define SP_INC_85 86 -#define SP_INC_86 87 -#define SP_INC_87 88 -#define SP_INC_88 89 -#define SP_INC_89 90 -#define SP_INC_90 91 -#define SP_INC_91 92 -#define SP_INC_92 93 -#define SP_INC_93 94 -#define SP_INC_94 95 -#define SP_INC_95 96 -#define SP_INC_96 97 -#define SP_INC_97 98 -#define SP_INC_98 99 -#define SP_INC_99 100 -#define SP_INC_100 101 -#define SP_INC_101 102 -#define SP_INC_102 103 -#define SP_INC_103 104 -#define SP_INC_104 105 -#define SP_INC_105 106 -#define SP_INC_106 107 -#define SP_INC_107 108 -#define SP_INC_108 109 -#define SP_INC_109 110 -#define SP_INC_110 111 -#define SP_INC_111 112 -#define SP_INC_112 113 -#define SP_INC_113 114 -#define SP_INC_114 115 -#define SP_INC_115 116 -#define SP_INC_116 117 -#define SP_INC_117 118 -#define SP_INC_118 119 -#define SP_INC_119 120 -#define SP_INC_120 121 -#define SP_INC_121 122 -#define SP_INC_122 123 -#define SP_INC_123 124 -#define SP_INC_124 125 -#define SP_INC_125 126 -#define SP_INC_126 127 -#define SP_INC_127 128 -#define SP_INC_128 129 -#define SP_INC_129 130 -#define SP_INC_130 131 -#define SP_INC_131 132 -#define SP_INC_132 133 -#define SP_INC_133 134 -#define SP_INC_134 135 -#define SP_INC_135 136 -#define SP_INC_136 137 -#define SP_INC_137 138 -#define SP_INC_138 139 -#define SP_INC_139 140 -#define SP_INC_140 141 -#define SP_INC_141 142 -#define SP_INC_142 143 -#define SP_INC_143 144 -#define SP_INC_144 145 -#define SP_INC_145 146 -#define SP_INC_146 147 -#define SP_INC_147 148 -#define SP_INC_148 149 -#define SP_INC_149 150 -#define SP_INC_150 151 -#define SP_INC_151 152 -#define SP_INC_152 153 -#define SP_INC_153 154 -#define SP_INC_154 155 -#define SP_INC_155 156 -#define SP_INC_156 157 -#define SP_INC_157 158 -#define SP_INC_158 159 -#define SP_INC_159 160 -#define SP_INC_160 161 -#define SP_INC_161 162 -#define SP_INC_162 163 -#define SP_INC_163 164 -#define SP_INC_164 165 -#define SP_INC_165 166 -#define SP_INC_166 167 -#define SP_INC_167 168 -#define SP_INC_168 169 -#define SP_INC_169 170 -#define SP_INC_170 171 -#define SP_INC_171 172 -#define SP_INC_172 173 -#define SP_INC_173 174 -#define SP_INC_174 175 -#define SP_INC_175 176 -#define SP_INC_176 177 -#define SP_INC_177 178 -#define SP_INC_178 179 -#define SP_INC_179 180 -#define SP_INC_180 181 -#define SP_INC_181 182 -#define SP_INC_182 183 -#define SP_INC_183 184 -#define SP_INC_184 185 -#define SP_INC_185 186 -#define SP_INC_186 187 -#define SP_INC_187 188 -#define SP_INC_188 189 -#define SP_INC_189 190 -#define SP_INC_190 191 -#define SP_INC_191 192 -#define SP_INC_192 193 -#define SP_INC_193 194 -#define SP_INC_194 195 -#define SP_INC_195 196 -#define SP_INC_196 197 -#define SP_INC_197 198 -#define SP_INC_198 199 -#define SP_INC_199 200 -#define SP_INC_200 201 -#define SP_INC_201 202 -#define SP_INC_202 203 -#define SP_INC_203 204 -#define SP_INC_204 205 -#define SP_INC_205 206 -#define SP_INC_206 207 -#define SP_INC_207 208 -#define SP_INC_208 209 -#define SP_INC_209 210 -#define SP_INC_210 211 -#define SP_INC_211 212 -#define SP_INC_212 213 -#define SP_INC_213 214 -#define SP_INC_214 215 -#define SP_INC_215 216 -#define SP_INC_216 217 -#define SP_INC_217 218 -#define SP_INC_218 219 -#define SP_INC_219 220 -#define SP_INC_220 221 -#define SP_INC_221 222 -#define SP_INC_222 223 -#define SP_INC_223 224 -#define SP_INC_224 225 -#define SP_INC_225 226 -#define SP_INC_226 227 -#define SP_INC_227 228 -#define SP_INC_228 229 -#define SP_INC_229 230 -#define SP_INC_230 231 -#define SP_INC_231 232 -#define SP_INC_232 233 -#define SP_INC_233 234 -#define SP_INC_234 235 -#define SP_INC_235 236 -#define SP_INC_236 237 -#define SP_INC_237 238 -#define SP_INC_238 239 -#define SP_INC_239 240 -#define SP_INC_240 241 -#define SP_INC_241 242 -#define SP_INC_242 243 -#define SP_INC_243 244 -#define SP_INC_244 245 -#define SP_INC_245 246 -#define SP_INC_246 247 -#define SP_INC_247 248 -#define SP_INC_248 249 -#define SP_INC_249 250 -#define SP_INC_250 251 -#define SP_INC_251 252 -#define SP_INC_252 253 -#define SP_INC_253 254 -#define SP_INC_254 255 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_INCREMENT_MACRO_H */ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_list.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_list.h index 977e8cc..24c132b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_list.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_list.h @@ -1,164 +1,164 @@ -/** - * \file - * - * \brief List declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_LIST_H_INCLUDED -#define _UTILS_LIST_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_list - * - * @{ - */ - -#include - -/** - * \brief List element type - */ -struct list_element { - struct list_element *next; -}; - -/** - * \brief List head type - */ -struct list_descriptor { - struct list_element *head; -}; - -/** - * \brief Reset list - * - * \param[in] list The pointer to a list descriptor - */ -static inline void list_reset(struct list_descriptor *const list) -{ - list->head = NULL; -} - -/** - * \brief Retrieve list head - * - * \param[in] list The pointer to a list descriptor - * - * \return A pointer to the head of the given list or NULL if the list is - * empty - */ -static inline void *list_get_head(const struct list_descriptor *const list) -{ - return (void *)list->head; -} - -/** - * \brief Retrieve next list head - * - * \param[in] list The pointer to a list element - * - * \return A pointer to the next list element or NULL if there is not next - * element - */ -static inline void *list_get_next_element(const void *const element) -{ - return element ? ((struct list_element *)element)->next : NULL; -} - -/** - * \brief Insert an element as list head - * - * \param[in] list The pointer to a list element - * \param[in] element An element to insert to the given list - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element); - -/** - * \brief Insert an element after the given list element - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_after(void *const after, void *const element); - -/** - * \brief Insert an element at list end - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element); - -/** - * \brief Check whether an element belongs to a list - * - * \param[in] list The pointer to a list - * \param[in] element An element to check - * - * \return The result of checking - * \retval true If the given element is an element of the given list - * \retval false Otherwise - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element); - -/** - * \brief Removes list head - * - * This function removes the list head and sets the next element after the list - * head as a new list head. - * - * \param[in] list The pointer to a list - * - * \return The pointer to the new list head of NULL if the list head is NULL - */ -void *list_remove_head(struct list_descriptor *const list); - -/** - * \brief Removes the list element - * - * \param[in] list The pointer to a list - * \param[in] element An element to remove - * - * \return The result of element removing - * \retval true The given element is removed from the given list - * \retval false The given element is not an element of the given list - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_LIST_H_INCLUDED */ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_repeat_macro.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_repeat_macro.h index 89e6f52..433293e 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_repeat_macro.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_repeat_macro.h @@ -1,322 +1,322 @@ -/** - * \file - * - * \brief Repeat macro. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_REPEAT_MACRO_H -#define _UTILS_REPEAT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Sequently repeates specified macro for n times (255 max). - * - * Specified macro shall have two arguments: macro(arg, i) - * arg - user defined argument, which have the same value for all iterations. - * i - iteration number; numbering begins from zero and increments on each - * iteration. - * - * \param[in] macro - macro to be repeated - * \param[in] arg - user defined argument for repeated macro - * \param[in] n - total number of iterations (255 max) - */ -#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) - -#define REPEAT1(macro, arg, n) macro(arg, n) -#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) -#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) -#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) -#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) -#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) -#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) -#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) -#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) -#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) -#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) -#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) -#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) -#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) -#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) -#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) -#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) -#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) -#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) -#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) -#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) -#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) -#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) -#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) -#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) -#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) -#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) -#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) -#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) -#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) -#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) -#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) -#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) -#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) -#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) -#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) -#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) -#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) -#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) -#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) -#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) -#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) -#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) -#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) -#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) -#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) -#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) -#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) -#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) -#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) -#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) -#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) -#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) -#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) -#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) -#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) -#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) -#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) -#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) -#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) -#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) -#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) -#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) -#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) -#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) -#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) -#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) -#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) -#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) -#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) -#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) -#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) -#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) -#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) -#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) -#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) -#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) -#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) -#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) -#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) -#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) -#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) -#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) -#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) -#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) -#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) -#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) -#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) -#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) -#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) -#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) -#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) -#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) -#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) -#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) -#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) -#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) -#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) -#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) -#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) -#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) -#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) -#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) -#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) -#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) -#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) -#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) -#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) -#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) -#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) -#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) -#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) -#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) -#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) -#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) -#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) -#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) -#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) -#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) -#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) -#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) -#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) -#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) -#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) -#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) -#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) -#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) -#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) -#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) -#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) -#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) -#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) -#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) -#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) -#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) -#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) -#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) -#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) -#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) -#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) -#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) -#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) -#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) -#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) -#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) -#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) -#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) -#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) -#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) -#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) -#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) -#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) -#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) -#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) -#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) -#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) -#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) -#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) -#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) -#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) -#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) -#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) -#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) -#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) -#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) -#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) -#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) -#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) -#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) -#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) -#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) -#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) -#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) -#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) -#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) -#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) -#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) -#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) -#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) -#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) -#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) -#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) -#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) -#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) -#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) -#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) -#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) -#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) -#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) -#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) -#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) -#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) -#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) -#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) -#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) -#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) -#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) -#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) -#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) -#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) -#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) -#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) -#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) -#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) -#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) -#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) -#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) -#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) -#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) -#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) -#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) -#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) -#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) -#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) -#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) -#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) -#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) -#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) -#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) -#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) -#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) -#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) -#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) -#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) -#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) -#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) -#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) -#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) -#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) -#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) -#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) -#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) -#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) -#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) -#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) -#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) -#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) -#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) -#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) -#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) -#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) -#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) -#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) -#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) -#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) -#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) -#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) -#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) -#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) -#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) -#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) -#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) -#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) -#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) -#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_REPEAT_MACRO_H */ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h index 401d557..023ffc4 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/include/utils_ringbuffer.h @@ -1,116 +1,116 @@ -/** - * \file - * - * \brief Ringbuffer declaration. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#ifndef _UTILS_RINGBUFFER_H_INCLUDED -#define _UTILS_RINGBUFFER_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_ringbuffer - * - * @{ - */ - -#include "compiler.h" -#include "utils_assert.h" - -/** - * \brief Ring buffer element type - */ -struct ringbuffer { - uint8_t *buf; /** Buffer base address */ - uint32_t size; /** Buffer size */ - uint32_t read_index; /** Buffer read index */ - uint32_t write_index; /** Buffer write index */ -}; - -/** - * \brief Ring buffer init - * - * \param[in] rb The pointer to a ring buffer structure instance - * \param[in] buf Space to store the data - * \param[in] size The buffer length, must be aligned with power of 2 - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size); - -/** - * \brief Get one byte from ring buffer, the user needs to handle the concurrent - * access on buffer via put/get/flush - * - * \param[in] rb The pointer to a ring buffer structure instance - * \param[in] data One byte space to store the read data - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data); - -/** - * \brief Put one byte to ring buffer, the user needs to handle the concurrent access - * on buffer via put/get/flush - * - * \param[in] rb The pointer to a ring buffer structure instance - * \param[in] data One byte data to be put into ring buffer - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data); - -/** - * \brief Return the element number of ring buffer - * - * \param[in] rb The pointer to a ring buffer structure instance - * - * \return The number of elements in ring buffer [0, rb->size] - */ -uint32_t ringbuffer_num(const struct ringbuffer *const rb); - -/** - * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer - * via put/get/flush - * - * \param[in] rb The pointer to a ring buffer structure instance - * - * \return ERR_NONE on success, or an error code on failure. - */ -uint32_t ringbuffer_flush(struct ringbuffer *const rb); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_RINGBUFFER_H_INCLUDED */ +/** + * \file + * + * \brief Ringbuffer declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _UTILS_RINGBUFFER_H_INCLUDED +#define _UTILS_RINGBUFFER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_ringbuffer + * + * @{ + */ + +#include "compiler.h" +#include "utils_assert.h" + +/** + * \brief Ring buffer element type + */ +struct ringbuffer { + uint8_t *buf; /** Buffer base address */ + uint32_t size; /** Buffer size */ + uint32_t read_index; /** Buffer read index */ + uint32_t write_index; /** Buffer write index */ +}; + +/** + * \brief Ring buffer init + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] buf Space to store the data + * \param[in] size The buffer length, must be aligned with power of 2 + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size); + +/** + * \brief Get one byte from ring buffer, the user needs to handle the concurrent + * access on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte space to store the read data + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data); + +/** + * \brief Put one byte to ring buffer, the user needs to handle the concurrent access + * on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte data to be put into ring buffer + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data); + +/** + * \brief Return the element number of ring buffer + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return The number of elements in ring buffer [0, rb->size] + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb); + +/** + * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer + * via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return ERR_NONE on success, or an error code on failure. + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_RINGBUFFER_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_assert.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_assert.c index b376c97..504fe41 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_assert.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_assert.c @@ -1,46 +1,46 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include - -/** - * \brief Assert function - */ -void assert(const bool condition, const char *const file, const int line) -{ - if (!(condition)) { - __asm("BKPT #0"); - } - (void)file; - (void)line; -} +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_event.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_event.c index d1af9d0..f8fb477 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_event.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_event.c @@ -1,125 +1,125 @@ -/** - * \file - * - * \brief Events implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) - -static struct list_descriptor events; -static uint8_t subscribed[EVENT_MASK_SIZE]; - -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - - ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); - - if (event->mask[position] & mask) { - return ERR_NO_CHANGE; /* Already subscribed */ - } - - if (!is_list_element(&events, event)) { - memset(event->mask, 0, EVENT_MASK_SIZE); - list_insert_as_head(&events, event); - } - event->cb = cb; - event->mask[position] |= mask; - - subscribed[position] |= mask; - - return ERR_NONE; -} - -int32_t event_unsubscribe(struct event *const event, const event_id_t id) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - uint8_t i; - - ASSERT(event && (id < EVENT_MAX_AMOUNT)); - - if (!(event->mask[position] & mask)) { - return ERR_NO_CHANGE; /* Already unsubscribed */ - } - - event->mask[position] &= ~mask; - - /* Check if there are more subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - break; - } - } - if (!current) { - subscribed[position] &= ~mask; - } - - /* Remove event from the list. Can be unsave, document it! */ - for (i = 0; i < ARRAY_SIZE(event->mask); i++) { - if (event->mask[i]) { - return ERR_NONE; - } - } - list_delete_element(&events, event); - - return ERR_NONE; -} - -void event_post(const event_id_t id, const event_data_t data) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - - ASSERT((id < EVENT_MAX_AMOUNT)); - - if (!(subscribed[position] & mask)) { - return; /* No subscribers */ - } - - /* Find all subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - current->cb(id, data); - } - } -} +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_list.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_list.c index 4006a01..49d4db6 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_list.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_list.c @@ -1,136 +1,136 @@ -/** - * \file - * - * \brief List functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Check whether element belongs to list - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element) -{ - struct list_element *it; - for (it = list->head; it; it = it->next) { - if (it == element) { - return true; - } - } - - return false; -} - -/** - * \brief Insert an element as list head - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element) -{ - ASSERT(!is_list_element(list, element)); - - ((struct list_element *)element)->next = list->head; - list->head = (struct list_element *)element; -} - -/** - * \brief Insert an element after the given list element - */ -void list_insert_after(void *const after, void *const element) -{ - ((struct list_element *)element)->next = ((struct list_element *)after)->next; - ((struct list_element *)after)->next = (struct list_element *)element; -} - -/** - * \brief Insert an element at list end - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element) -{ - struct list_element *it = list->head; - - ASSERT(!is_list_element(list, element)); - - if (!list->head) { - list->head = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; - return; - } - - while (it->next) { - it = it->next; - } - it->next = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; -} - -/** - * \brief Removes list head - */ -void *list_remove_head(struct list_descriptor *const list) -{ - if (list->head) { - struct list_element *tmp = list->head; - - list->head = list->head->next; - return (void *)tmp; - } - - return NULL; -} - -/** - * \brief Removes list element - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element) -{ - if (!element) { - return false; - } - - if (list->head == element) { - list->head = list->head->next; - return true; - } else { - struct list_element *it = list->head; - - while (it && it->next != element) { - it = it->next; - } - if (it) { - it->next = ((struct list_element *)element)->next; - return true; - } - } - - return false; -} - -//@} +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c index 45cac83..e02de08 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_ringbuffer.c @@ -1,118 +1,118 @@ -/** - * \file - * - * \brief Ringbuffer functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include "utils_ringbuffer.h" - -/** - * \brief Ringbuffer init - */ -int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) -{ - ASSERT(rb && buf && size); - - /* - * buf size must be aligned to power of 2 - */ - if ((size & (size - 1)) != 0) { - return ERR_INVALID_ARG; - } - - /* size - 1 is faster in calculation */ - rb->size = size - 1; - rb->read_index = 0; - rb->write_index = rb->read_index; - rb->buf = (uint8_t *)buf; - - return ERR_NONE; -} - -/** - * \brief Get one byte from ringbuffer - * - */ -int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) -{ - ASSERT(rb && data); - - if (rb->write_index != rb->read_index) { - *data = rb->buf[rb->read_index & rb->size]; - rb->read_index++; - return ERR_NONE; - } - - return ERR_NOT_FOUND; -} - -/** - * \brief Put one byte to ringbuffer - * - */ -int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) -{ - ASSERT(rb); - - rb->buf[rb->write_index & rb->size] = data; - - /* - * buffer full strategy: new data will overwrite the oldest data in - * the buffer - */ - if ((rb->write_index - rb->read_index) > rb->size) { - rb->read_index = rb->write_index - rb->size; - } - - rb->write_index++; - - return ERR_NONE; -} - -/** - * \brief Return the element number of ringbuffer - */ -uint32_t ringbuffer_num(const struct ringbuffer *const rb) -{ - ASSERT(rb); - - return rb->write_index - rb->read_index; -} - -/** - * \brief Flush ringbuffer - */ -uint32_t ringbuffer_flush(struct ringbuffer *const rb) -{ - ASSERT(rb); - - rb->read_index = rb->write_index; - - return ERR_NONE; -} +/** + * \file + * + * \brief Ringbuffer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "utils_ringbuffer.h" + +/** + * \brief Ringbuffer init + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) +{ + ASSERT(rb && buf && size); + + /* + * buf size must be aligned to power of 2 + */ + if ((size & (size - 1)) != 0) { + return ERR_INVALID_ARG; + } + + /* size - 1 is faster in calculation */ + rb->size = size - 1; + rb->read_index = 0; + rb->write_index = rb->read_index; + rb->buf = (uint8_t *)buf; + + return ERR_NONE; +} + +/** + * \brief Get one byte from ringbuffer + * + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) +{ + ASSERT(rb && data); + + if (rb->write_index != rb->read_index) { + *data = rb->buf[rb->read_index & rb->size]; + rb->read_index++; + return ERR_NONE; + } + + return ERR_NOT_FOUND; +} + +/** + * \brief Put one byte to ringbuffer + * + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) +{ + ASSERT(rb); + + rb->buf[rb->write_index & rb->size] = data; + + /* + * buffer full strategy: new data will overwrite the oldest data in + * the buffer + */ + if ((rb->write_index - rb->read_index) > rb->size) { + rb->read_index = rb->write_index - rb->size; + } + + rb->write_index++; + + return ERR_NONE; +} + +/** + * \brief Return the element number of ringbuffer + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb) +{ + ASSERT(rb); + + return rb->write_index - rb->read_index; +} + +/** + * \brief Flush ringbuffer + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb) +{ + ASSERT(rb); + + rb->read_index = rb->write_index; + + return ERR_NONE; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_syscalls.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_syscalls.c index 79e2f1f..a51a097 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_syscalls.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hal/utils/src/utils_syscalls.c @@ -1,152 +1,152 @@ -/** - * \file - * - * \brief Syscalls for SAM0 (GCC). - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *_new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -/** - * \brief Replacement of C library of _sbrk - */ -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char * prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t)prev_heap; -} - -/** - * \brief Replacement of C library of link - */ -extern int link(char *old, char *_new) -{ - (void)old, (void)_new; - return -1; -} - -/** - * \brief Replacement of C library of _close - */ -extern int _close(int file) -{ - (void)file; - return -1; -} - -/** - * \brief Replacement of C library of _fstat - */ -extern int _fstat(int file, struct stat *st) -{ - (void)file; - st->st_mode = S_IFCHR; - - return 0; -} - -/** - * \brief Replacement of C library of _isatty - */ -extern int _isatty(int file) -{ - (void)file; - return 1; -} - -/** - * \brief Replacement of C library of _lseek - */ -extern int _lseek(int file, int ptr, int dir) -{ - (void)file, (void)ptr, (void)dir; - return 0; -} - -/** - * \brief Replacement of C library of _exit - */ -extern void _exit(int status) -{ - printf("Exiting with status %d.\n", status); - - for (;;) - ; -} - -/** - * \brief Replacement of C library of _kill - */ -extern void _kill(int pid, int sig) -{ - (void)pid, (void)sig; - return; -} - -/** - * \brief Replacement of C library of _getpid - */ -extern int _getpid(void) -{ - return -1; -} - -#ifdef __cplusplus -} -#endif +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/cmcc/hpl_cmcc.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/cmcc/hpl_cmcc.c index bddf0e1..475a305 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/cmcc/hpl_cmcc.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/cmcc/hpl_cmcc.c @@ -1,354 +1,354 @@ -/** - * \file - * - * \brief Generic CMCC(Cortex M Cache Controller) related functionality. - * - * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Microchip Support - */ - -#include -#include -#include - -/** - * \brief Initialize Cache Module - * - * This function does low level cache configuration. - * - * \return initialize status - */ -int32_t _cmcc_init(void) -{ - int32_t return_value; - - _cmcc_disable(CMCC); - - if (_is_cache_disabled(CMCC)) { - hri_cmcc_write_CFG_reg( - CMCC, - (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos) - | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE))); - - _cmcc_enable(CMCC); - return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE; - } else { - return_value = ERR_NOT_INITIALIZED; - } - - return return_value; -} - -/** - * \brief Configure CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] cache configuration structure pointer - * - * \return status of operation - */ -int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl) -{ - int32_t return_value; - - _cmcc_disable(hw); - - if (_is_cache_disabled(hw)) { - hri_cmcc_write_CFG_reg( - hw, - (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos) - | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable))); - - return_value = ERR_NONE; - } else { - return_value = ERR_NOT_INITIALIZED; - } - - return return_value; -} - -/** - * \brief Enable data cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache - * - * \return status of operation - */ -int32_t _cmcc_enable_data_cache(const void *hw, bool value) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp &= ~CMCC_CFG_DCDIS; - tmp |= ((!value) << CMCC_CFG_DCDIS_Pos); - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Enable instruction cache in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache - * - * \return status of operation - */ -int32_t _cmcc_enable_inst_cache(const void *hw, bool value) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp &= ~CMCC_CFG_ICDIS; - tmp |= ((!value) << CMCC_CFG_ICDIS_Pos); - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Enable clock gating in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate - * - * \return status of operation - */ -int32_t _cmcc_enable_clock_gating(const void *hw, bool value) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp |= value; - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Configure the cache size in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache size configuration enumerator - * 0->1K, 1->2K, 2->4K(default) - * - * \return status of operation - */ -int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_CFG_reg(hw); - tmp &= (~CMCC_CFG_CSIZESW_Msk); - tmp |= (size << CMCC_CFG_CSIZESW_Pos); - - ret = _cmcc_disable(hw); - hri_cmcc_write_CFG_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Lock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_lock_way(const void *hw, enum way_num_index num) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_LCKWAY_reg(hw); - tmp |= CMCC_LCKWAY_LCKWAY(num); - - ret = _cmcc_disable(hw); - hri_cmcc_write_LCKWAY_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Unlock the mentioned WAY in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num_index" enumerator - * - * \return status of operation - */ -int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num) -{ - uint32_t tmp; - int32_t ret; - - tmp = hri_cmcc_read_LCKWAY_reg(hw); - tmp &= (~CMCC_LCKWAY_LCKWAY(num)); - - ret = _cmcc_disable(hw); - hri_cmcc_write_LCKWAY_reg(hw, tmp); - ret = _cmcc_enable(hw); - - return ret; -} - -/** - * \brief Invalidate the mentioned cache line in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from "way_num" enumerator (valid arg is 0-3) - * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) - * - * \return status of operation - */ -int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num) -{ - int32_t return_value; - - if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) { - _cmcc_disable(hw); - while (!(_is_cache_disabled(hw))) - ; - hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num))); - return_value = ERR_NONE; - } else { - return_value = ERR_INVALID_ARG; - } - - return return_value; -} - -/** - * \brief Invalidate entire cache entries in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_invalidate_all(const void *hw) -{ - int32_t return_value; - - _cmcc_disable(hw); - if (_is_cache_disabled(hw)) { - hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL); - return_value = ERR_NONE; - } else { - return_value = ERR_FAILURE; - } - - return return_value; -} - -/** - * \brief Configure cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * \param[in] element from cache monitor configurations enumerator - * - * \return status of operation - */ -int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg) -{ - hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg)); - - return ERR_NONE; -} - -/** - * \brief Enable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_enable_monitor(const void *hw) -{ - hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE); - - return ERR_NONE; -} - -/** - * \brief Disable cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_disable_monitor(const void *hw) -{ - hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos)); - - return ERR_NONE; -} - -/** - * \brief Reset cache monitor in CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return status of operation - */ -int32_t _cmcc_reset_monitor(const void *hw) -{ - hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST); - - return ERR_NONE; -} - -/** - * \brief Get cache monitor event counter value from CMCC module - * - * \param[in] pointer pointing to the starting address of CMCC module - * - * \return event counter value - */ -uint32_t _cmcc_get_monitor_event_count(const void *hw) -{ - return hri_cmcc_read_MSR_reg(hw); -} +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include +#include + +/** + * \brief Initialize Cache Module + * + * This function does low level cache configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void) +{ + int32_t return_value; + + _cmcc_disable(CMCC); + + if (_is_cache_disabled(CMCC)) { + hri_cmcc_write_CFG_reg( + CMCC, + (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos) + | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE))); + + _cmcc_enable(CMCC); + return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl) +{ + int32_t return_value; + + _cmcc_disable(hw); + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CFG_reg( + hw, + (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos) + | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable))); + + return_value = ERR_NONE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_DCDIS; + tmp |= ((!value) << CMCC_CFG_DCDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_ICDIS; + tmp |= ((!value) << CMCC_CFG_ICDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp |= value; + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= (~CMCC_CFG_CSIZESW_Msk); + tmp |= (size << CMCC_CFG_CSIZESW_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp |= CMCC_LCKWAY_LCKWAY(num); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp &= (~CMCC_LCKWAY_LCKWAY(num)); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num) +{ + int32_t return_value; + + if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) { + _cmcc_disable(hw); + while (!(_is_cache_disabled(hw))) + ; + hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num))); + return_value = ERR_NONE; + } else { + return_value = ERR_INVALID_ARG; + } + + return return_value; +} + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw) +{ + int32_t return_value; + + _cmcc_disable(hw); + if (_is_cache_disabled(hw)) { + hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL); + return_value = ERR_NONE; + } else { + return_value = ERR_FAILURE; + } + + return return_value; +} + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg) +{ + hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg)); + + return ERR_NONE; +} + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE); + + return ERR_NONE; +} + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos)); + + return ERR_NONE; +} + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw) +{ + hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST); + + return ERR_NONE; +} + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw) +{ + return hri_cmcc_read_MSR_reg(hw); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_m4.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_m4.c index 4680ec3..3d5d9a7 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_m4.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_m4.c @@ -1,241 +1,241 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#ifndef _UNIT_TEST_ -#include -#endif -#include -#include - -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 1000000 -#endif - -#if CONF_CPU_FREQUENCY < 1000 -#define CPU_FREQ_POWER 3 -#elif CONF_CPU_FREQUENCY < 10000 -#define CPU_FREQ_POWER 4 -#elif CONF_CPU_FREQUENCY < 100000 -#define CPU_FREQ_POWER 5 -#elif CONF_CPU_FREQUENCY < 1000000 -#define CPU_FREQ_POWER 6 -#elif CONF_CPU_FREQUENCY < 10000000 -#define CPU_FREQ_POWER 7 -#elif CONF_CPU_FREQUENCY < 100000000 -#define CPU_FREQ_POWER 8 -#elif CONF_CPU_FREQUENCY < 1000000000 -#define CPU_FREQ_POWER 9 -#endif - -/** - * \brief The array of interrupt handlers - */ -struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; - -/** - * \brief Reset MCU - */ -void _reset_mcu(void) -{ - NVIC_SystemReset(); -} - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * \brief Retrieve current IRQ number - */ -uint8_t _irq_get_current(void) -{ - return (uint8_t)__get_IPSR() - 16; -} - -/** - * \brief Disable the given IRQ - */ -void _irq_disable(uint8_t n) -{ - NVIC_DisableIRQ((IRQn_Type)n); -} - -/** - * \brief Set the given IRQ - */ -void _irq_set(uint8_t n) -{ - NVIC_SetPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Clear the given IRQ - */ -void _irq_clear(uint8_t n) -{ - NVIC_ClearPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Enable the given IRQ - */ -void _irq_enable(uint8_t n) -{ - NVIC_EnableIRQ((IRQn_Type)n); -} - -/** - * \brief Register IRQ handler - */ -void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) -{ - ASSERT(n < PERIPH_COUNT_IRQn); - - _irq_table[n] = irq; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Default_Handler(void) -{ - while (1) { - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 9: - return (us * (freq / 1000000) + 2) / 3; - case 8: - return (us * (freq / 100000) + 29) / 30; - case 7: - return (us * (freq / 10000) + 299) / 300; - case 6: - return (us * (freq / 1000) + 2999) / 3000; - case 5: - return (us * (freq / 100) + 29999) / 30000; - case 4: - return (us * (freq / 10) + 299999) / 300000; - default: - return (us * freq + 2999999) / 3000000; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -uint32_t _get_cycles_for_us(const uint16_t us) -{ - return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 9: - return (ms * (freq / 1000000) + 2) / 3 * 1000; - case 8: - return (ms * (freq / 100000) + 2) / 3 * 100; - case 7: - return (ms * (freq / 10000) + 2) / 3 * 10; - case 6: - return (ms * (freq / 1000) + 2) / 3; - case 5: - return (ms * (freq / 100) + 29) / 30; - case 4: - return (ms * (freq / 10) + 299) / 300; - default: - return (ms * (freq / 1) + 2999) / 3000; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -uint32_t _get_cycles_for_ms(const uint16_t ms) -{ - return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} -/** - * \brief Initialize delay functionality - */ -void _delay_init(void *const hw) -{ - (void)hw; -} -/** - * \brief Delay loop to delay n number of cycles - */ -void _delay_cycles(void *const hw, uint32_t cycles) -{ -#ifndef _UNIT_TEST_ - (void)hw; - (void)cycles; -#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */ - __asm(".align 3 \n" - "__delay:\n" - "subs r1, r1, #1\n" - "bhi __delay\n"); -#elif defined __GNUC__ - __asm(".syntax unified\n" - ".align 3 \n" - "__delay:\n" - "subs r1, r1, #1\n" - "bhi __delay\n" - ".syntax divided"); -#elif defined __CC_ARM - __asm("__delay:\n" - "subs cycles, cycles, #1\n" - "bhi __delay\n"); -#elif defined __ICCARM__ - __asm("__delay:\n" - "subs r1, r1, #1\n" - "bhi.n __delay\n"); -#endif -#endif -} +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#elif CONF_CPU_FREQUENCY < 1000000000 +#define CPU_FREQ_POWER 9 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) + 2) / 3; + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000) + 2) / 3 * 1000; + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */ + __asm(".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#elif defined __GNUC__ + __asm(".syntax unified\n" + ".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi.n __delay\n"); +#endif +#endif +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_port.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_port.h index 3f3e8f2..ab9b9f1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_port.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_core_port.h @@ -1,61 +1,61 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_PORT_H_INCLUDED -#define _HPL_CORE_PORT_H_INCLUDED - -#include - -/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR - * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), - * there will be assembling errors. - * So the following things are not included for assembling. - */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) - -#ifndef _UNIT_TEST_ -#include -#endif - -/** - * \brief Check if it's in ISR handling - * \return \c true if it's in ISR - */ -static inline bool _is_in_isr(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); -} - -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _HPL_CORE_PORT_H_INCLUDED */ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_init.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_init.c index be0db93..753e58f 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_init.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/core/hpl_init.c @@ -1,78 +1,78 @@ -/** - * \file - * - * \brief HPL initialization related functionality implementation. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#include -#include -#include -#include - -/* Referenced GCLKs (out of 0~11), should be initialized firstly - */ -#define _GCLK_INIT_1ST 0x00000000 -/* Not referenced GCLKs, initialized last */ -#define _GCLK_INIT_LAST 0x00000FFF - -/** - * \brief Initialize the hardware abstraction layer - */ -void _init_chip(void) -{ - hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); - - _osc32kctrl_init_sources(); - _oscctrl_init_sources(); - _mclk_init(); -#if _GCLK_INIT_1ST - _gclk_init_generators_by_fref(_GCLK_INIT_1ST); -#endif - _oscctrl_init_referenced_generators(); - _gclk_init_generators_by_fref(_GCLK_INIT_LAST); - -#if CONF_DMAC_ENABLE - hri_mclk_set_AHBMASK_DMAC_bit(MCLK); - _dma_init(); -#endif - -#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) - _port_event_init(); -#endif - -#if CONF_CMCC_ENABLE - cache_init(); -#endif -} +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Referenced GCLKs (out of 0~11), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x00000FFF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif + +#if CONF_CMCC_ENABLE + cache_init(); +#endif +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/dmac/hpl_dmac.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/dmac/hpl_dmac.c index b1b3f5c..e2126be 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/dmac/hpl_dmac.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/dmac/hpl_dmac.c @@ -1,263 +1,263 @@ - -/** - * \file - * - * \brief Generic DMAC related functionality. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include - -#if CONF_DMAC_ENABLE -/* Section containing first descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -DmacDescriptor _descriptor_section[DMAC_CH_NUM]; - -/* Section containing current descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -DmacDescriptor _write_back_section[DMAC_CH_NUM]; - -/* Array containing callbacks for DMAC channels */ -static struct _dma_resource _resources[DMAC_CH_NUM]; - -/* DMAC interrupt handler */ -static void _dmac_handler(void); - -/* This macro DMAC configuration */ -#define DMAC_CHANNEL_CFG(i, n) \ - {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ - | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ - DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ - (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ - | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ - DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ - | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ - | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ - | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, - -/* DMAC channel configuration */ -struct dmac_channel_cfg { - uint32_t ctrla; - uint8_t prilvl; - uint8_t evctrl; - uint16_t btctrl; -}; - -/* DMAC channel configurations */ -const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; - -/** - * \brief Initialize DMAC - */ -int32_t _dma_init(void) -{ - uint8_t i; - - hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); - hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); - hri_dmac_set_CTRL_SWRST_bit(DMAC); - while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) - ; - - hri_dmac_write_CTRL_reg(DMAC, - (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) - | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) - | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); - hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); - - hri_dmac_write_PRICTRL0_reg( - DMAC, - DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) - | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) - | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) - | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); - hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); - hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); - - for (i = 0; i < DMAC_CH_NUM; i++) { - hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); - hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); - hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); - hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); - hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); - } - - for (i = 0; i < 5; i++) { - NVIC_DisableIRQ(DMAC_0_IRQn + i); - NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); - NVIC_EnableIRQ(DMAC_0_IRQn + i); - } - - hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); - - return ERR_NONE; -} - -/** - * \brief Enable/disable DMA interrupt - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) -{ - if (DMA_TRANSFER_COMPLETE_CB == type) { - hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); - } else if (DMA_TRANSFER_ERROR_CB == type) { - hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); - } -} - -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) -{ - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); - - return ERR_NONE; -} - -int32_t _dma_set_source_address(const uint8_t channel, const void *const src) -{ - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); - - return ERR_NONE; -} - -int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) -{ - hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], - (uint32_t)&_descriptor_section[next_channel]); - - return ERR_NONE; -} - -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} - -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) -{ - uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); - uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); - - return ERR_NONE; -} - -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) -{ - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); - hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); - - if (software_trigger) { - hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); - } - - return ERR_NONE; -} - -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) -{ - *resource = &_resources[channel]; - - return ERR_NONE; -} - -int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} -/** - * \internal DMAC interrupt handler - */ -static void _dmac_handler(void) -{ - uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); - struct _dma_resource *tmp_resource = &_resources[channel]; - - if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { - hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); - tmp_resource->dma_cb.error(tmp_resource); - } else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) { - hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel); - tmp_resource->dma_cb.transfer_done(tmp_resource); - } -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_0_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_1_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_2_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_3_Handler(void) -{ - _dmac_handler(); -} -/** - * \brief DMAC interrupt handler - */ -void DMAC_4_Handler(void) -{ - _dmac_handler(); -} - -#endif /* CONF_DMAC_ENABLE */ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM]; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM]; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* DMAC interrupt handler */ +static void _dmac_handler(void); + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ + | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ + DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ + (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ + | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint32_t ctrla; + uint8_t prilvl; + uint8_t evctrl; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); + hri_dmac_set_CTRL_SWRST_bit(DMAC); + while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) + ; + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); + hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); + hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + for (i = 0; i < 5; i++) { + NVIC_DisableIRQ(DMAC_0_IRQn + i); + NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); + NVIC_EnableIRQ(DMAC_0_IRQn + i); + } + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); + + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} +/** + * \internal DMAC interrupt handler + */ +static void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); + struct _dma_resource *tmp_resource = &_resources[channel]; + + if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); + tmp_resource->dma_cb.error(tmp_resource); + } else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) { + hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_0_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_1_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_2_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_3_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_4_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/eic/hpl_eic.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/eic/hpl_eic.c index b691409..95c3f44 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/eic/hpl_eic.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/eic/hpl_eic.c @@ -1,258 +1,258 @@ - -/** - * \file - * - * \brief EIC related functionality implementation. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include - -#ifdef __MINGW32__ -#define ffs __builtin_ffs -#endif -#if defined(__CC_ARM) || defined(__ICCARM__) -/* Find the first bit set */ -static int ffs(int v) -{ - int i, bit = 1; - for (i = 0; i < sizeof(int) * 8; i++) { - if (v & bit) { - return i + 1; - } - bit <<= 1; - } - return 0; -} -#endif - -/** - * \brief Invalid external interrupt and pin numbers - */ -#define INVALID_EXTINT_NUMBER 0xFF -#define INVALID_PIN_NUMBER 0xFFFFFFFF - -#ifndef CONFIG_EIC_EXTINT_MAP -/** Dummy mapping to pass compiling. */ -#define CONFIG_EIC_EXTINT_MAP \ - { \ - INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \ - } -#endif - -#define EXT_IRQ_AMOUNT 0 - -/** - * \brief EXTINTx and pin number map - */ -struct _eic_map { - uint8_t extint; - uint32_t pin; -}; - -/** - * \brief PIN and EXTINT map for enabled external interrupts - */ -static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP}; - -/** - * \brief The callback to upper layer's interrupt processing routine - */ -static void (*callback)(const uint32_t pin); - -static void _ext_irq_handler(void); - -/** - * \brief Initialize external interrupt module - */ -int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) -{ - if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { - if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { - hri_eic_clear_CTRLA_ENABLE_bit(EIC); - hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); - } - hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); - } - hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); - - hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL); - - hri_eic_write_NMICTRL_reg(EIC, - (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos) - | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH) - | 0); - - hri_eic_write_EVCTRL_reg(EIC, - (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2) - | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5) - | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8) - | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11) - | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13) - | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0); - hri_eic_write_ASYNCH_reg(EIC, - (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2) - | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5) - | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8) - | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11) - | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14) - | (CONF_EIC_ASYNCH15 << 15) | 0); - hri_eic_write_DEBOUNCEN_reg( - EIC, - (CONF_EIC_DEBOUNCE_ENABLE0 << 0) | (CONF_EIC_DEBOUNCE_ENABLE1 << 1) | (CONF_EIC_DEBOUNCE_ENABLE2 << 2) - | (CONF_EIC_DEBOUNCE_ENABLE3 << 3) | (CONF_EIC_DEBOUNCE_ENABLE4 << 4) | (CONF_EIC_DEBOUNCE_ENABLE5 << 5) - | (CONF_EIC_DEBOUNCE_ENABLE6 << 6) | (CONF_EIC_DEBOUNCE_ENABLE7 << 7) | (CONF_EIC_DEBOUNCE_ENABLE8 << 8) - | (CONF_EIC_DEBOUNCE_ENABLE9 << 9) | (CONF_EIC_DEBOUNCE_ENABLE10 << 10) | (CONF_EIC_DEBOUNCE_ENABLE11 << 11) - | (CONF_EIC_DEBOUNCE_ENABLE12 << 12) | (CONF_EIC_DEBOUNCE_ENABLE13 << 13) - | (CONF_EIC_DEBOUNCE_ENABLE14 << 14) | (CONF_EIC_DEBOUNCE_ENABLE15 << 15) | 0); - - hri_eic_write_DPRESCALER_reg( - EIC, - (EIC_DPRESCALER_PRESCALER0(CONF_EIC_DPRESCALER0)) | (CONF_EIC_STATES0 << EIC_DPRESCALER_STATES0_Pos) - | (EIC_DPRESCALER_PRESCALER1(CONF_EIC_DPRESCALER1)) | (CONF_EIC_STATES1 << EIC_DPRESCALER_STATES1_Pos) - | CONF_EIC_TICKON << EIC_DPRESCALER_TICKON_Pos | 0); - - hri_eic_write_CONFIG_reg(EIC, - 0, - (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0) - | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1) - | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2) - | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3) - | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4) - | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5) - | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6) - | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7) - | 0); - - hri_eic_write_CONFIG_reg(EIC, - 1, - (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8) - | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9) - | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10) - | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11) - | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12) - | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13) - | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14) - | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15) - | 0); - - hri_eic_set_CTRLA_ENABLE_bit(EIC); - - callback = cb; - - return ERR_NONE; -} - -/** - * \brief De-initialize external interrupt module - */ -int32_t _ext_irq_deinit(void) -{ - - callback = NULL; - - hri_eic_clear_CTRLA_ENABLE_bit(EIC); - hri_eic_set_CTRLA_SWRST_bit(EIC); - - return ERR_NONE; -} - -/** - * \brief Enable / disable external irq - */ -int32_t _ext_irq_enable(const uint32_t pin, const bool enable) -{ - uint8_t extint = INVALID_EXTINT_NUMBER; - uint8_t i = 0; - - for (; i < ARRAY_SIZE(_map); i++) { - if (_map[i].pin == pin) { - extint = _map[i].extint; - break; - } - } - if (INVALID_EXTINT_NUMBER == extint) { - return -1; - } - - if (enable) { - hri_eic_set_INTEN_reg(EIC, 1ul << extint); - } else { - hri_eic_clear_INTEN_reg(EIC, 1ul << extint); - hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint); - } - - return ERR_NONE; -} - -/** - * \brief Inter EIC interrupt handler - */ -static void _ext_irq_handler(void) -{ - volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC); - int8_t pos; - uint32_t pin = INVALID_PIN_NUMBER; - - hri_eic_clear_INTFLAG_reg(EIC, flags); - - ASSERT(callback); - - while (flags) { - pos = ffs(flags) - 1; - while (-1 != pos) { - uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; - - while (upper >= lower) { - middle = (upper + lower) >> 1; - if (_map[middle].extint == pos) { - pin = _map[middle].pin; - break; - } - if (_map[middle].extint < pos) { - lower = middle + 1; - } else { - upper = middle - 1; - } - } - - if (INVALID_PIN_NUMBER != pin) { - callback(pin); - } - flags &= ~(1ul << pos); - pos = ffs(flags) - 1; - } - flags = hri_eic_read_INTFLAG_reg(EIC); - hri_eic_clear_INTFLAG_reg(EIC, flags); - } -} + +/** + * \file + * + * \brief EIC related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#ifdef __MINGW32__ +#define ffs __builtin_ffs +#endif +#if defined(__CC_ARM) || defined(__ICCARM__) +/* Find the first bit set */ +static int ffs(int v) +{ + int i, bit = 1; + for (i = 0; i < sizeof(int) * 8; i++) { + if (v & bit) { + return i + 1; + } + bit <<= 1; + } + return 0; +} +#endif + +/** + * \brief Invalid external interrupt and pin numbers + */ +#define INVALID_EXTINT_NUMBER 0xFF +#define INVALID_PIN_NUMBER 0xFFFFFFFF + +#ifndef CONFIG_EIC_EXTINT_MAP +/** Dummy mapping to pass compiling. */ +#define CONFIG_EIC_EXTINT_MAP \ + { \ + INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \ + } +#endif + +#define EXT_IRQ_AMOUNT 0 + +/** + * \brief EXTINTx and pin number map + */ +struct _eic_map { + uint8_t extint; + uint32_t pin; +}; + +/** + * \brief PIN and EXTINT map for enabled external interrupts + */ +static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP}; + +/** + * \brief The callback to upper layer's interrupt processing routine + */ +static void (*callback)(const uint32_t pin); + +static void _ext_irq_handler(void); + +/** + * \brief Initialize external interrupt module + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) +{ + if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { + if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); + } + hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); + } + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); + + hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL); + + hri_eic_write_NMICTRL_reg(EIC, + (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos) + | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH) + | 0); + + hri_eic_write_EVCTRL_reg(EIC, + (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2) + | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5) + | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8) + | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11) + | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13) + | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0); + hri_eic_write_ASYNCH_reg(EIC, + (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2) + | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5) + | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8) + | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11) + | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14) + | (CONF_EIC_ASYNCH15 << 15) | 0); + hri_eic_write_DEBOUNCEN_reg( + EIC, + (CONF_EIC_DEBOUNCE_ENABLE0 << 0) | (CONF_EIC_DEBOUNCE_ENABLE1 << 1) | (CONF_EIC_DEBOUNCE_ENABLE2 << 2) + | (CONF_EIC_DEBOUNCE_ENABLE3 << 3) | (CONF_EIC_DEBOUNCE_ENABLE4 << 4) | (CONF_EIC_DEBOUNCE_ENABLE5 << 5) + | (CONF_EIC_DEBOUNCE_ENABLE6 << 6) | (CONF_EIC_DEBOUNCE_ENABLE7 << 7) | (CONF_EIC_DEBOUNCE_ENABLE8 << 8) + | (CONF_EIC_DEBOUNCE_ENABLE9 << 9) | (CONF_EIC_DEBOUNCE_ENABLE10 << 10) | (CONF_EIC_DEBOUNCE_ENABLE11 << 11) + | (CONF_EIC_DEBOUNCE_ENABLE12 << 12) | (CONF_EIC_DEBOUNCE_ENABLE13 << 13) + | (CONF_EIC_DEBOUNCE_ENABLE14 << 14) | (CONF_EIC_DEBOUNCE_ENABLE15 << 15) | 0); + + hri_eic_write_DPRESCALER_reg( + EIC, + (EIC_DPRESCALER_PRESCALER0(CONF_EIC_DPRESCALER0)) | (CONF_EIC_STATES0 << EIC_DPRESCALER_STATES0_Pos) + | (EIC_DPRESCALER_PRESCALER1(CONF_EIC_DPRESCALER1)) | (CONF_EIC_STATES1 << EIC_DPRESCALER_STATES1_Pos) + | CONF_EIC_TICKON << EIC_DPRESCALER_TICKON_Pos | 0); + + hri_eic_write_CONFIG_reg(EIC, + 0, + (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0) + | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1) + | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2) + | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3) + | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4) + | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5) + | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6) + | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7) + | 0); + + hri_eic_write_CONFIG_reg(EIC, + 1, + (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8) + | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9) + | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10) + | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11) + | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12) + | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13) + | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14) + | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15) + | 0); + + hri_eic_set_CTRLA_ENABLE_bit(EIC); + + callback = cb; + + return ERR_NONE; +} + +/** + * \brief De-initialize external interrupt module + */ +int32_t _ext_irq_deinit(void) +{ + + callback = NULL; + + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + hri_eic_set_CTRLA_SWRST_bit(EIC); + + return ERR_NONE; +} + +/** + * \brief Enable / disable external irq + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable) +{ + uint8_t extint = INVALID_EXTINT_NUMBER; + uint8_t i = 0; + + for (; i < ARRAY_SIZE(_map); i++) { + if (_map[i].pin == pin) { + extint = _map[i].extint; + break; + } + } + if (INVALID_EXTINT_NUMBER == extint) { + return -1; + } + + if (enable) { + hri_eic_set_INTEN_reg(EIC, 1ul << extint); + } else { + hri_eic_clear_INTEN_reg(EIC, 1ul << extint); + hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint); + } + + return ERR_NONE; +} + +/** + * \brief Inter EIC interrupt handler + */ +static void _ext_irq_handler(void) +{ + volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC); + int8_t pos; + uint32_t pin = INVALID_PIN_NUMBER; + + hri_eic_clear_INTFLAG_reg(EIC, flags); + + ASSERT(callback); + + while (flags) { + pos = ffs(flags) - 1; + while (-1 != pos) { + uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; + + while (upper >= lower) { + middle = (upper + lower) >> 1; + if (_map[middle].extint == pos) { + pin = _map[middle].pin; + break; + } + if (_map[middle].extint < pos) { + lower = middle + 1; + } else { + upper = middle - 1; + } + } + + if (INVALID_PIN_NUMBER != pin) { + callback(pin); + } + flags &= ~(1ul << pos); + pos = ffs(flags) - 1; + } + flags = hri_eic_read_INTFLAG_reg(EIC); + hri_eic_clear_INTFLAG_reg(EIC, flags); + } +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk.c index 211ccc3..acd15ef 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk.c @@ -1,312 +1,312 @@ - -/** - * \file - * - * \brief Generic Clock Controller related functionality. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initializes generators - */ -void _gclk_init_generators(void) -{ - -#if CONF_GCLK_GENERATOR_0_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_1_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_2_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_3_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_4_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_5_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 5, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_6_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 6, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_7_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 7, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_8_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 8, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_9_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 9, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_10_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 10, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); -#endif - -#if CONF_GCLK_GENERATOR_11_CONFIG == 1 - hri_gclk_write_GENCTRL_reg( - GCLK, - 11, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); -#endif -} - -void _gclk_init_generators_by_fref(uint32_t bm) -{ - -#if CONF_GCLK_GENERATOR_0_CONFIG == 1 - if (bm & (1ul << 0)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_1_CONFIG == 1 - if (bm & (1ul << 1)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_2_CONFIG == 1 - if (bm & (1ul << 2)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_3_CONFIG == 1 - if (bm & (1ul << 3)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_4_CONFIG == 1 - if (bm & (1ul << 4)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_5_CONFIG == 1 - if (bm & (1ul << 5)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 5, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_6_CONFIG == 1 - if (bm & (1ul << 6)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 6, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_7_CONFIG == 1 - if (bm & (1ul << 7)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 7, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_8_CONFIG == 1 - if (bm & (1ul << 8)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 8, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_9_CONFIG == 1 - if (bm & (1ul << 9)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 9, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_10_CONFIG == 1 - if (bm & (1ul << 10)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 10, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); - } -#endif - -#if CONF_GCLK_GENERATOR_11_CONFIG == 1 - if (bm & (1ul << 11)) { - hri_gclk_write_GENCTRL_reg( - GCLK, - 11, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); - } -#endif -} + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + if (bm & (1ul << 9)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + if (bm & (1ul << 10)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + if (bm & (1ul << 11)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); + } +#endif +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk_base.h index 3e7d282..7dfdd13 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk_base.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/gclk/hpl_gclk_base.h @@ -1,87 +1,87 @@ -/** - * \file - * - * \brief Generic Clock Controller. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GCLK_H_INCLUDED -#define _HPL_GCLK_H_INCLUDED - -#include -#ifdef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup gclk_group GCLK Hardware Proxy Layer - * - * \section gclk_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Enable clock on the given channel with the given clock source - * - * This function maps the given clock source to the given clock channel - * and enables channel. - * - * \param[in] channel The channel to enable clock for - * \param[in] source The clock source for the given channel - */ -static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) -{ - - hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); -} - -/** - * \brief Initialize GCLK generators by function references - * \param[in] bm Bit mapping for referenced generators, - * a bit 1 in position triggers generator initialization. - */ -void _gclk_init_generators_by_fref(uint32_t bm); - -//@} -/**@}*/ -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_GCLK_H_INCLUDED */ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/mclk/hpl_mclk.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/mclk/hpl_mclk.c index 6684320..d4958af 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/mclk/hpl_mclk.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/mclk/hpl_mclk.c @@ -1,44 +1,44 @@ -/** - * \file - * - * \brief SAM Main Clock. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void) -{ - void *hw = (void *)MCLK; - hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); -} +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/osc32kctrl/hpl_osc32kctrl.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/osc32kctrl/hpl_osc32kctrl.c index 8859b42..a4399f4 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/osc32kctrl/hpl_osc32kctrl.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -1,82 +1,82 @@ - -/** - * \file - * - * \brief SAM 32k Oscillators Controller. - * - * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void) -{ - void * hw = (void *)OSC32KCTRL; - uint16_t calib = 0; - -#if CONF_XOSC32K_CONFIG == 1 - hri_osc32kctrl_write_XOSC32K_reg( - hw, - OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) - | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) - | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) - | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) | -#ifdef CONF_XOSC32K_CGM - OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | -#endif - (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); - - hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); - - hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); -#endif - -#if CONF_OSCULP32K_CONFIG == 1 - calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); - hri_osc32kctrl_write_OSCULP32K_reg(hw, -#if CONF_OSCULP32K_CALIB_ENABLE == 1 - OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) -#else - OSC32KCTRL_OSCULP32K_CALIB(calib) -#endif - ); -#endif - -#if CONF_XOSC32K_CONFIG -#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 - while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) - ; -#endif -#endif - - hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); - (void)calib; -} + +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) | +#ifdef CONF_XOSC32K_CGM + OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | +#endif + (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSCULP32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/oscctrl/hpl_oscctrl.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/oscctrl/hpl_oscctrl.c index 9f55076..4dfd13c 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/oscctrl/hpl_oscctrl.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/oscctrl/hpl_oscctrl.c @@ -1,230 +1,230 @@ - -/** - * \file - * - * \brief SAM Oscillators Controller. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_XOSC0_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg( - hw, - 0, - OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) - | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) - | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) - | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); -#endif - -#if CONF_XOSC0_CONFIG == 1 -#if CONF_XOSC0_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) - ; -#endif -#if CONF_XOSC0_ENALC == 1 - hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0); -#endif -#if CONF_XOSC0_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); -#endif -#endif - -#if CONF_XOSC1_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg( - hw, - 1, - OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) - | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) - | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) - | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) - | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); -#endif - -#if CONF_XOSC1_CONFIG == 1 -#if CONF_XOSC1_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) - ; -#endif -#if CONF_XOSC1_ENALC == 1 - hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1); -#endif -#if CONF_XOSC1_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); -#endif -#endif - - (void)hw; -} - -void _oscctrl_init_referenced_generators(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_DFLL_CONFIG == 1 - hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); - while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) - ; - uint8_t tmp; - hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); -#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); -#endif - - hri_oscctrl_write_DFLLMUL_reg(hw, - OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) - | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); - while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) - ; - - hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); - while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) - ; - - tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; - hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); - while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) - ; - -#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 - hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); -#endif - hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); - while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) - ; - - tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) - | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) - | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) - | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; - hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); - while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) - ; -#endif - -#if CONF_FDPLL0_CONFIG == 1 -#if CONF_FDPLL0_REFCLK == 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg( - hw, - 0, - OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) - | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) - | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) - | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - 0, - (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_FDPLL1_CONFIG == 1 -#if CONF_FDPLL1_REFCLK == 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg( - hw, - 1, - OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) - | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) - | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) - | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - 1, - (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_DFLL_CONFIG == 1 - if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { - hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; - - while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) - ; - } else { - while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) - ; - } -#if CONF_DFLL_ONDEMAND == 1 - hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_FDPLL0_CONFIG == 1 -#if CONF_FDPLL0_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) - ; -#endif -#if CONF_FDPLL0_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); -#endif -#endif - -#if CONF_FDPLL1_CONFIG == 1 -#if CONF_FDPLL1_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) - ; -#endif -#if CONF_FDPLL1_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); -#endif -#endif - -#if CONF_DFLL_CONFIG == 1 - while (hri_gclk_read_SYNCBUSY_reg(GCLK)) - ; - hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); - while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) - ; -#endif - (void)hw; -} + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC0_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 0, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) + | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC0_CONFIG == 1 +#if CONF_XOSC0_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) + ; +#endif +#if CONF_XOSC0_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0); +#endif +#if CONF_XOSC0_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_XOSC1_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 1, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) + | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC1_CONFIG == 1 +#if CONF_XOSC1_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) + ; +#endif +#if CONF_XOSC1_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1); +#endif +#if CONF_XOSC1_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); +#endif +#endif + + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DFLL_CONFIG == 1 + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; + uint8_t tmp; + hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) + ; + + hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; + + tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; + hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); + while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) + ; + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) + | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) + | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; + hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 0, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) + | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 0, + (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 1, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) + | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 1, + (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) + ; +#endif +#if CONF_FDPLL0_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) + ; +#endif +#if CONF_FDPLL1_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; +#endif + (void)hw; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm.c index 55dc4db..5882b33 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm.c @@ -1,68 +1,68 @@ - -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Set the sleep mode for the device - */ -int32_t _set_sleep_mode(const uint8_t mode) -{ - uint8_t delay = 10; - - switch (mode) { - case 2: - case 4: - case 5: - case 6: - case 7: - hri_pm_write_SLEEPCFG_reg(PM, mode); - /* A small latency happens between the store instruction and actual - * writing of the SLEEPCFG register due to bridges. Software has to make - * sure the SLEEPCFG register reads the wanted value before issuing WFI - * instruction. - */ - do { - if (hri_pm_read_SLEEPCFG_reg(PM) == mode) { - break; - } - } while (--delay); - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + uint8_t delay = 10; + + switch (mode) { + case 2: + case 4: + case 5: + case 6: + case 7: + hri_pm_write_SLEEPCFG_reg(PM, mode); + /* A small latency happens between the store instruction and actual + * writing of the SLEEPCFG register due to bridges. Software has to make + * sure the SLEEPCFG register reads the wanted value before issuing WFI + * instruction. + */ + do { + if (hri_pm_read_SLEEPCFG_reg(PM) == mode) { + break; + } + } while (--delay); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm_base.h index 5a50a91..b4f6e02 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm_base.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/pm/hpl_pm_base.h @@ -1,45 +1,45 @@ -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HPL_PM_BASE_H_INCLUDED -#define _HPL_PM_BASE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_PM_BASE_H_INCLUDED */ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/port/hpl_gpio_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/port/hpl_gpio_base.h index f32c40f..52c899c 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/port/hpl_gpio_base.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/port/hpl_gpio_base.h @@ -1,172 +1,172 @@ - -/** - * \file - * - * \brief SAM PORT. - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include - -/** - * \brief Set direction on port with mask - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - switch (direction) { - case GPIO_DIRECTION_OFF: - hri_port_clear_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_IN: - hri_port_clear_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg(PORT, - port, - PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN - | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_OUT: - hri_port_set_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - default: - ASSERT(false); - } -} - -/** - * \brief Set output level on port with mask - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - if (level) { - hri_port_set_OUT_reg(PORT, port, mask); - } else { - hri_port_clear_OUT_reg(PORT, port, mask); - } -} - -/** - * \brief Change output level to the opposite with mask - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) -{ - hri_port_toggle_OUT_reg(PORT, port, mask); -} - -/** - * \brief Get input levels on all port pins - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port) -{ - uint32_t tmp; - - CRITICAL_SECTION_ENTER(); - - uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); - - tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; - tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; - - CRITICAL_SECTION_LEAVE(); - - return tmp; -} - -/** - * \brief Set pin pull mode - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode) -{ - switch (pull_mode) { - case GPIO_PULL_OFF: - hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); - break; - - case GPIO_PULL_UP: - hri_port_clear_DIR_reg(PORT, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_set_OUT_reg(PORT, port, 1U << pin); - break; - - case GPIO_PULL_DOWN: - hri_port_clear_DIR_reg(PORT, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_clear_OUT_reg(PORT, port, 1U << pin); - break; - - default: - ASSERT(false); - break; - } -} - -/** - * \brief Set gpio pin function - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) -{ - uint8_t port = GPIO_PORT(gpio); - uint8_t pin = GPIO_PIN(gpio); - - if (function == GPIO_PIN_FUNCTION_OFF) { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); - - } else { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); - - if (pin & 1) { - // Odd numbered pin - hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); - } else { - // Even numbered pin - hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); - } - } -} - -static inline void _port_event_init() -{ - hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL); -} + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT, port, mask); + } else { + hri_port_clear_OUT_reg(PORT, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/ramecc/hpl_ramecc.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/ramecc/hpl_ramecc.c index 4c158b2..92a342f 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/ramecc/hpl_ramecc.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/ramecc/hpl_ramecc.c @@ -1,83 +1,83 @@ -/** - * \file - * - * \brief Generic RAMECC related functionality. - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/* RAMECC device descriptor */ -struct _ramecc_device device; - -/** - * \brief Initialize RAMECC - */ -int32_t _ramecc_init(void) -{ - if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { - return ERR_ABORTED; - } - - NVIC_DisableIRQ(RAMECC_IRQn); - NVIC_ClearPendingIRQ(RAMECC_IRQn); - NVIC_EnableIRQ(RAMECC_IRQn); - - return ERR_NONE; -} - -void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) -{ - if (RAMECC_DUAL_ERROR_CB == type) { - device.ramecc_cb.dual_bit_err = cb; - hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); - } else if (RAMECC_SINGLE_ERROR_CB == type) { - device.ramecc_cb.single_bit_err = cb; - hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); - } -} - -/** - * \internal RAMECC interrupt handler - */ -void RAMECC_Handler(void) -{ - struct _ramecc_device *dev = (struct _ramecc_device *)&device; - volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); - - if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { - dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); - } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { - dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); - } else { - return; - } -} +/** + * \file + * + * \brief Generic RAMECC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/* RAMECC device descriptor */ +struct _ramecc_device device; + +/** + * \brief Initialize RAMECC + */ +int32_t _ramecc_init(void) +{ + if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { + return ERR_ABORTED; + } + + NVIC_DisableIRQ(RAMECC_IRQn); + NVIC_ClearPendingIRQ(RAMECC_IRQn); + NVIC_EnableIRQ(RAMECC_IRQn); + + return ERR_NONE; +} + +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) +{ + if (RAMECC_DUAL_ERROR_CB == type) { + device.ramecc_cb.dual_bit_err = cb; + hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); + } else if (RAMECC_SINGLE_ERROR_CB == type) { + device.ramecc_cb.single_bit_err = cb; + hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); + } +} + +/** + * \internal RAMECC interrupt handler + */ +void RAMECC_Handler(void) +{ + struct _ramecc_device *dev = (struct _ramecc_device *)&device; + volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); + + if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { + dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else { + return; + } +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c index 306c99b..ee9797d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/sercom/hpl_sercom.c @@ -1,3025 +1,3025 @@ - -/** - * \file - * - * \brief SAM Serial Communication Interface - * - * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_USART_ENABLE -#define CONF_SERCOM_1_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_USART_ENABLE -#define CONF_SERCOM_3_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_USART_ENABLE -#define CONF_SERCOM_4_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_USART_ENABLE -#define CONF_SERCOM_5_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_USART_ENABLE -#define CONF_SERCOM_6_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_USART_ENABLE -#define CONF_SERCOM_7_USART_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as USART. */ -#define SERCOM_USART_AMOUNT \ - (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ - + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ - + CONF_SERCOM_7_USART_ENABLE) - -/** - * \brief Macro is used to fill usart configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define SERCOM_CONFIGURATION(n) \ - { \ - n, \ - SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ - | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ - | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ - | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ - | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ - | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ - | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ - | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ - | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ - SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ - | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ - | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ - | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ - | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ - | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ - SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ - | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ - | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ - | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ - (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ - CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ - } - -/** - * \brief SERCOM USART configuration type - */ -struct usart_configuration { - uint8_t number; - hri_sercomusart_ctrla_reg_t ctrl_a; - hri_sercomusart_ctrlb_reg_t ctrl_b; - hri_sercomusart_ctrlc_reg_t ctrl_c; - hri_sercomusart_baud_reg_t baud; - uint8_t fractional; - hri_sercomusart_rxpl_reg_t rxpl; - hri_sercomusart_dbgctrl_reg_t debug_ctrl; -}; - -#if SERCOM_USART_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct usart_configuration _usarts[1] = {{0}}; -#else -/** - * \brief Array of SERCOM USART configurations - */ -static struct usart_configuration _usarts[] = { -#if CONF_SERCOM_0_USART_ENABLE == 1 - SERCOM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_USART_ENABLE == 1 - SERCOM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_USART_ENABLE == 1 - SERCOM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_USART_ENABLE == 1 - SERCOM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_USART_ENABLE == 1 - SERCOM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_USART_ENABLE == 1 - SERCOM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_USART_ENABLE == 1 - SERCOM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_USART_ENABLE == 1 - SERCOM_CONFIGURATION(7), -#endif -}; -#endif - -static struct _usart_async_device *_sercom2_dev = NULL; - -static uint8_t _get_sercom_index(const void *const hw); -static uint8_t _sercom_get_irq_num(const void *const hw); -static void _sercom_init_irq_param(const void *const hw, void *dev); -static uint8_t _sercom_get_hardware_index(const void *const hw); - -static int32_t _usart_init(void *const hw); -static inline void _usart_deinit(void *const hw); -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); -static void _usart_set_data_order(void *const hw, const enum usart_data_order order); -static void _usart_set_mode(void *const hw, const enum usart_mode mode); -static void _usart_set_parity(void *const hw, const enum usart_parity parity); -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); -static void _usart_set_character_size(void *const hw, const enum usart_character_size size); - -/** - * \brief Initialize synchronous SERCOM USART - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _usart_init(hw); -} - -/** - * \brief Initialize asynchronous SERCOM USART - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _usart_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - return ERR_NONE; -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_sync_deinit(struct _usart_sync_device *const device) -{ - _usart_deinit(device->hw); -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_async_deinit(struct _usart_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _usart_deinit(device->hw); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_sync_enable(struct _usart_sync_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_async_enable(struct _usart_async_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_sync_disable(struct _usart_sync_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_async_disable(struct _usart_async_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Set baud rate - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set baud rate - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set data order - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set data order - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set mode - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set mode - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set parity - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set parity - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set stop bits mode - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set stop bits mode - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set character size - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Set character size - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given SERCOM USART instance - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_DATA_reg(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if USART transmission complete - */ -bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_TXC_bit(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if there is data received by USART - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_RXC_bit(device->hw); -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Enable data register empty interrupt - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_DRE_bit(device->hw); -} - -/** - * \brief Enable transmission complete interrupt - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_TXC_bit(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given sercom hardware instance - */ -static uint8_t _sercom_get_hardware_index(const void *const hw) -{ - Sercom *const sercom_modules[] = SERCOM_INSTS; - /* Find index for SERCOM instance. */ - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { - return i; - } - } - return 0; -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Enable/disable USART interrupt - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { - hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); - hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); - } else if (USART_ASYNC_RX_DONE == type) { - hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); - } else if (USART_ASYNC_ERROR == type) { - hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal Sercom interrupt handler - * - * \param[in] p The pointer to interrupt parameter - */ -static void _sercom_usart_interrupt_handler(struct _usart_async_device *device) -{ - void *hw = device->hw; - - if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { - hri_sercomusart_clear_INTEN_DRE_bit(hw); - device->usart_cb.tx_byte_sent(device); - } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { - hri_sercomusart_clear_INTEN_TXC_bit(hw); - device->usart_cb.tx_done_cb(device); - } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { - if (hri_sercomusart_read_STATUS_reg(hw) - & (SERCOM_USART_STATUS_PERR | SERCOM_USART_STATUS_FERR | SERCOM_USART_STATUS_BUFOVF - | SERCOM_USART_STATUS_ISF | SERCOM_USART_STATUS_COLL)) { - hri_sercomusart_clear_STATUS_reg(hw, SERCOM_USART_STATUS_MASK); - return; - } - - device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); - } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { - uint32_t status; - - hri_sercomusart_clear_interrupt_ERROR_bit(hw); - device->usart_cb.error_cb(device); - status = hri_sercomusart_read_STATUS_reg(hw); - hri_sercomusart_clear_STATUS_reg(hw, status); - } -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static uint8_t _get_sercom_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_usarts); i++) { - if (_usarts[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Init irq param with the given sercom hardware instance - */ -static void _sercom_init_irq_param(const void *const hw, void *dev) -{ - - if (hw == SERCOM2) { - _sercom2_dev = (struct _usart_async_device *)dev; - } -} - -/** - * \internal Initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - * - * \return The status of initialization - */ -static int32_t _usart_init(void *const hw) -{ - uint8_t i = _get_sercom_index(hw); - - if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { - uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; - if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - } - hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); - } - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - - hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); - hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); - hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); - if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { - ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; - ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; - } else { - hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); - } - - hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); - hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); - - return ERR_NONE; -} - -/** - * \internal De-initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _usart_deinit(void *const hw) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate SERCOM clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { - return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; - } - - if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { - return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); - } - - if (USART_BAUDRATE_SYNCH == mode) { - return clock_rate / baud / 2 - 1; - } - - return 0; -} - -/** - * \internal Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_BAUD_reg(hw, baud_rate); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -static void _usart_set_data_order(void *const hw, const enum usart_data_order order) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_DORD_bit(hw, order); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -static void _usart_set_mode(void *const hw, const enum usart_mode mode) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -static void _usart_set_parity(void *const hw, const enum usart_parity parity) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - - if (USART_PARITY_NONE != parity) { - hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); - } else { - hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); - } - - hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -static void _usart_set_character_size(void *const hw, const enum usart_character_size size) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomusart_set_CTRLA_ENABLE_bit(hw); - } -} - - /* Sercom I2C implementation */ - -#ifndef CONF_SERCOM_0_I2CM_ENABLE -#define CONF_SERCOM_0_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CM_ENABLE -#define CONF_SERCOM_2_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CM_ENABLE -#define CONF_SERCOM_3_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CM_ENABLE -#define CONF_SERCOM_4_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CM_ENABLE -#define CONF_SERCOM_5_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CM_ENABLE -#define CONF_SERCOM_6_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CM_ENABLE -#define CONF_SERCOM_7_I2CM_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Master. */ -#define SERCOM_I2CM_AMOUNT \ - (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ - + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) - -/** - * \brief Macro is used to fill i2cm configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CM_CONFIGURATION(n) \ - { \ - (n), \ - (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ - | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ - SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ - CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ - } - -#define ERROR_FLAG (1 << 7) -#define SB_FLAG (1 << 1) -#define MB_FLAG (1 << 0) - -#define CMD_STOP 0x3 -#define I2C_IDLE 0x1 -#define I2C_SM 0x0 -#define I2C_FM 0x1 -#define I2C_HS 0x2 -#define TEN_ADDR_FRAME 0x78 -#define TEN_ADDR_MASK 0x3ff -#define SEVEN_ADDR_MASK 0x7f - -/** - * \brief SERCOM I2CM configuration type - */ -struct i2cm_configuration { - uint8_t number; - hri_sercomi2cm_ctrla_reg_t ctrl_a; - hri_sercomi2cm_ctrlb_reg_t ctrl_b; - hri_sercomi2cm_baud_reg_t baud; - hri_sercomi2cm_dbgctrl_reg_t dbgctrl; - uint16_t trise; - uint32_t clk; /* SERCOM peripheral clock frequency */ -}; - -static inline int32_t _i2c_m_enable_implementation(void *hw); -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); - -#if SERCOM_I2CM_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct i2cm_configuration _i2cms[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2CM configurations - */ -static struct i2cm_configuration _i2cms[] = { -#if CONF_SERCOM_0_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2cm_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { - if (_i2cms[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -static inline void _sercom_i2c_send_stop(void *const hw) -{ - hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); -} - -/** - * \brief SERCOM I2CM analyze hardware status and transfer next byte - */ -static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) -{ - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); - - if (flags & MB_FLAG) { - /* tx error */ - if (status & SERCOM_I2CM_STATUS_ARBLOST) { - hri_sercomi2cm_clear_interrupt_MB_bit(hw); - msg->flags |= I2C_M_FAIL; - msg->flags &= ~I2C_M_BUSY; - - if (status & SERCOM_I2CM_STATUS_BUSERR) { - return I2C_ERR_BUS; - } - - return I2C_ERR_BAD_ADDRESS; - } else { - if (status & SERCOM_I2CM_STATUS_RXNACK) { - - /* Slave rejects to receive more data */ - if (msg->len > 0) { - msg->flags |= I2C_M_FAIL; - } - - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - - return I2C_NACK; - } - - if (msg->flags & I2C_M_TEN) { - hri_sercomi2cm_write_ADDR_reg(hw, - ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - msg->flags &= ~I2C_M_TEN; - - return I2C_OK; - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } else { - hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); - msg->buffer++; - msg->len--; - } - - return I2C_OK; - } - } else if (flags & SB_FLAG) { - if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { - msg->len--; - - /* last byte, send nack */ - if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } - - /* Accessing DATA.DATA auto-triggers I2C bus operations. - * The operation performed depends on the state of - * CTRLB.ACKACT, CTRLB.SMEN - **/ - *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); - } else { - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - return I2C_NACK; - } - - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - } - - return I2C_OK; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - return _i2c_m_enable_implementation(i2c_dev->hw); -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _sercom_get_irq_num(const void *const hw) -{ - return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); -} - -/** - * \brief Initialize sercom i2c module to use in async mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) -{ - int32_t init_status; - - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); - if (init_status) { - return init_status; - } - - _sercom_init_irq_param(hw, (void *)i2c_dev); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - return ERR_NONE; -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Transfer the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - return ERR_NONE; -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail, return the error code - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) -{ - int ret; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (msg->len == 0) { - return ERR_NONE; - } - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); - - ret = _sercom_i2c_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Set callback to be called in interrupt handler - * - * \param[in] i2c_dev The pointer to master i2c device - * \param[in] type The callback type - * \param[in] func The callback function pointer - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, - FUNC_PTR func) -{ - switch (type) { - case I2C_M_ASYNC_DEVICE_ERROR: - i2c_dev->cb.error = (_i2c_error_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_TX_COMPLETE: - i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_RX_COMPLETE: - i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; - break; - default: - /* error */ - break; - } - - return ERR_NONE; -} - -/** - * \brief Set stop condition on I2C - * - * \param i2c_dev Pointer to master i2c device - * - * \return Operation status - * \retval I2C_OK Operation was successfull - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -/** - * \brief Get number of bytes left in transfer buffer - * - * \param i2c_dev Pointer to i2c master device - * - * \return Bytes left in buffer - * \retval =>0 Bytes left in buffer - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) -{ - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return i2c_dev->service.msg.len; - } - - return 0; -} - -/** - * \brief Initialize sercom i2c module to use in sync mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) -{ - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - return _i2c_m_sync_init_impl(&i2c_dev->service, hw); -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - return _i2c_m_enable_implementation(i2c_dev->hw); -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C master interrupt - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state) -{ - if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); - hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); - } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { - hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \brief Wait for bus response - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] flags Store the hardware response - * - * \return Bus response status. - * \retval 0 Bus response status OK - * \retval <0 Bus response fail - */ -inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) -{ - uint32_t timeout = 65535; - void * hw = i2c_dev->hw; - - do { - *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); - - if (timeout-- == 0) { - return I2C_ERR_BUS; - } - } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); - - return I2C_OK; -} - -/** - * \brief Send the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint32_t flags; - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - return _sercom_i2c_sync_analyse_flags(hw, flags, msg); -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail or partial fail, return the error code - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) -{ - uint32_t flags; - int ret; - void * hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return I2C_ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); - - ret = _sercom_i2c_sync_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - while (i2c_dev->service.msg.flags & I2C_M_BUSY) { - ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - - if (ret) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); - } - - return ret; -} - -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -static inline int32_t _i2c_m_enable_implementation(void *const hw) -{ - int timeout = 65535; - int timeout_attempt = 4; - - ASSERT(hw); - - /* Enable interrupts */ - hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); - - while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { - timeout--; - - if (timeout <= 0) { - if (--timeout_attempt) - timeout = 65535; - else - return I2C_ERR_BUSY; - hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); - } - } - return ERR_NONE; -} - -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) -{ - uint8_t i = _get_i2cm_index(hw); - - if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { - uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; - if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); - } - hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); - } - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - - hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); - hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); - hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); - - service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); - - service->trise = _i2cms[i].trise; - - return ERR_NONE; -} - - /* SERCOM I2C slave */ - -#ifndef CONF_SERCOM_0_I2CS_ENABLE -#define CONF_SERCOM_0_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CS_ENABLE -#define CONF_SERCOM_1_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CS_ENABLE -#define CONF_SERCOM_2_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CS_ENABLE -#define CONF_SERCOM_3_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CS_ENABLE -#define CONF_SERCOM_4_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CS_ENABLE -#define CONF_SERCOM_5_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CS_ENABLE -#define CONF_SERCOM_6_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CS_ENABLE -#define CONF_SERCOM_7_I2CS_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Slave. */ -#define SERCOM_I2CS_AMOUNT \ - (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ - + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) - -/** - * \brief Macro is used to fill I2C slave configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CS_CONFIGURATION(n) \ - { \ - n, \ - SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ - | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ - | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ - SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ - (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ - | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ - } - -/** - * \brief Macro to check 10-bit addressing - */ -#define I2CS_7BIT_ADDRESSING_MASK 0x7F - -static int32_t _i2c_s_init(void *const hw); -static int8_t _get_i2c_s_index(const void *const hw); -static inline void _i2c_s_deinit(void *const hw); -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); - -/** - * \brief SERCOM I2C slave configuration type - */ -struct i2cs_configuration { - uint8_t number; - hri_sercomi2cs_ctrla_reg_t ctrl_a; - hri_sercomi2cs_ctrlb_reg_t ctrl_b; - hri_sercomi2cs_addr_reg_t address; -}; - -#if SERCOM_I2CS_AMOUNT < 1 -/** Dummy array for compiling. */ -static struct i2cs_configuration _i2css[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2C slave configurations - */ -static struct i2cs_configuration _i2css[] = { -#if CONF_SERCOM_0_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \brief Initialize synchronous I2C slave - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) -{ - int32_t status; - - ASSERT(device); - - status = _i2c_s_init(hw); - if (status) { - return status; - } - device->hw = hw; - - return ERR_NONE; -} - -/** - * \brief Initialize asynchronous I2C slave - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _i2c_s_init(hw); - if (init_status) { - return init_status; - } - - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -/** - * \brief Deinitialize synchronous I2C - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) -{ - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Deinitialize asynchronous I2C - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given I2C instance - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_DATA_reg(device->hw); -} - -/** - * \brief Check if I2C is ready to send next byt - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Check if there is data received by I2C - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Clear the Data Ready interrupt flag - */ -int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Abort data transmission - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C slave interrupt - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); - } else if (I2C_S_DEVICE_ERROR == type) { - hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); - } - - return ERR_NONE; -} - -/** - * \internal Initalize i2c slave hardware - * - * \param[in] p The pointer to hardware instance - * - *\ return status of initialization - */ -static int32_t _i2c_s_init(void *const hw) -{ - int8_t i = _get_i2c_s_index(hw); - if (i == -1) { - return ERR_INVALID_ARG; - } - - if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { - uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; - if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); - } - hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); - } - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - - hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); - hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); - hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); - - return ERR_NONE; -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - * - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2c_s_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2css); i++) { - if (_i2css[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _i2c_s_deinit(void *const hw) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - * \param[in] address Address to set - */ -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) -{ - bool enabled; - - enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); - } - - return ERR_NONE; -} - - /* Sercom SPI implementation */ - -#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) -#endif - -#define SPI_DEV_IRQ_MODE 0x8000 - -#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) -#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) - -COMPILER_PACK_SET(1) -/** Initialization configuration of registers. */ -struct sercomspi_regs_cfg { - uint32_t ctrla; - uint32_t ctrlb; - uint32_t addr; - uint8_t baud; - uint8_t dbgctrl; - uint16_t dummy_byte; - uint8_t n; -}; -COMPILER_PACK_RESET() - -/** Build configuration from header macros. */ -#define SERCOMSPI_REGS(n) \ - { \ - (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ - | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ - | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ - | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ - ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ - | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ - | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ - | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ - (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ - | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ - ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ - (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ - CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ - n /* sercom number */ \ - } - -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_SPI_ENABLE -#define CONF_SERCOM_1_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_SPI_ENABLE -#define CONF_SERCOM_2_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_SPI_ENABLE -#define CONF_SERCOM_4_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_SPI_ENABLE -#define CONF_SERCOM_5_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_SPI_ENABLE -#define CONF_SERCOM_6_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_SPI_ENABLE -#define CONF_SERCOM_7_SPI_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as SPI */ -#define SERCOM_SPI_AMOUNT \ - (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ - + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) - -#if SERCOM_SPI_AMOUNT < 1 -/** Dummy array for compiling. */ -static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; -#else -/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ -static const struct sercomspi_regs_cfg sercomspi_regs[] = { -#if CONF_SERCOM_0_SPI_ENABLE - SERCOMSPI_REGS(0), -#endif -#if CONF_SERCOM_1_SPI_ENABLE - SERCOMSPI_REGS(1), -#endif -#if CONF_SERCOM_2_SPI_ENABLE - SERCOMSPI_REGS(2), -#endif -#if CONF_SERCOM_3_SPI_ENABLE - SERCOMSPI_REGS(3), -#endif -#if CONF_SERCOM_4_SPI_ENABLE - SERCOMSPI_REGS(4), -#endif -#if CONF_SERCOM_5_SPI_ENABLE - SERCOMSPI_REGS(5), -#endif -#if CONF_SERCOM_6_SPI_ENABLE - SERCOMSPI_REGS(6), -#endif -#if CONF_SERCOM_7_SPI_ENABLE - SERCOMSPI_REGS(7), -#endif -}; -#endif - -/** \internal De-initialize SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return De-initialization status - */ -static int32_t _spi_deinit(void *const hw) -{ - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_sync_enable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_set_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_async_enable(void *const hw) -{ - _spi_sync_enable(hw); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_EnableIRQ((IRQn_Type)irq++); - } - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_sync_disable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_async_disable(void *const hw) -{ - _spi_sync_disable(hw); - hri_sercomspi_clear_INTEN_reg( - hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq++); - } - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI mode - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] mode The mode to set - * - * \return Setting mode status - */ -static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); - ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI baudrate - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting baudrate status - */ -static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_write_BAUD_reg(hw, baud_val); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI char size - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * \param[out] size Stored char size - * - * \return Setting char size status - */ -static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) -{ - /* Only 8-bit or 9-bit accepted */ - if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { - return ERR_INVALID_ARG; - } - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { - return ERR_BUSY; - } - - hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); - *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI data order - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting data order status - */ -static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - - if (dord == SPI_DATA_ORDER_LSB_1ST) { - ctrla |= SERCOM_SPI_CTRLA_DORD; - } else { - ctrla &= ~SERCOM_SPI_CTRLA_DORD; - } - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \brief Load SERCOM registers to init for SPI master mode - * The settings will be applied with default master mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg( - hw, - (regs->ctrlb - & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) - | (SERCOM_SPI_CTRLB_RXEN)); - hri_sercomspi_write_BAUD_reg(hw, regs->baud); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); -} - -/** \brief Load SERCOM registers to init for SPI slave mode - * The settings will be applied with default slave mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg(hw, - (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) - | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); - hri_sercomspi_write_ADDR_reg(hw, regs->addr); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); - while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) - ; -} - -/** \brief Return the pointer to register settings of specific SERCOM - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific SERCOM. - */ -static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { - if (sercomspi_regs[i].n == n) { - return &sercomspi_regs[i]; - } - } - - return NULL; -} - -/** - * \internal Sercom interrupt handler - */ -void SERCOM2_0_Handler(void) -{ - _sercom_usart_interrupt_handler(_sercom2_dev); -} -/** - * \internal Sercom interrupt handler - */ -void SERCOM2_1_Handler(void) -{ - _sercom_usart_interrupt_handler(_sercom2_dev); -} -/** - * \internal Sercom interrupt handler - */ -void SERCOM2_2_Handler(void) -{ - _sercom_usart_interrupt_handler(_sercom2_dev); -} -/** - * \internal Sercom interrupt handler - */ -void SERCOM2_3_Handler(void) -{ - _sercom_usart_interrupt_handler(_sercom2_dev); -} - -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) -{ - const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); - - ASSERT(dev && hw); - - if (regs == NULL) { - return ERR_INVALID_ARG; - } - - if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; - if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); - } - hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); - } - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - - dev->prvt = hw; - - if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { - _spi_load_regs_slave(hw, regs); - } else { - _spi_load_regs_master(hw, regs); - } - - /* Load character size from default hardware configuration */ - dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; - - dev->dummy_byte = regs->dummy_byte; - - return ERR_NONE; -} - -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) -{ - return _spi_m_sync_init(dev, hw); -} - -int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) -{ - struct _spi_async_dev *spid = dev; - /* Do hardware initialize. */ - int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); - - if (rc < 0) { - return rc; - } - - _sercom_init_irq_param(hw, (void *)dev); - /* Initialize callbacks: must use them */ - spid->callbacks.complete = NULL; - spid->callbacks.rx = NULL; - spid->callbacks.tx = NULL; - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) -{ - return _spi_m_async_init(dev, hw); -} - -int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_m_async_enable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_m_async_disable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) -{ - int32_t rc; - ASSERT(dev); - - /* Not accept 0es */ - if (clk == 0 || baud == 0) { - return ERR_INVALID_ARG; - } - - /* Check baudrate range of current assigned clock */ - if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { - return ERR_INVALID_ARG; - } - - rc = ((clk >> 1) / baud) - 1; - return rc; -} - -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -/** Wait until SPI bus idle. */ -static inline void _spi_wait_bus_idle(void *const hw) -{ - while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { - ; - } - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); -} - -/** Holds run time information for message sync transaction. */ -struct _spi_trans_ctrl { - /** Pointer to transmitting data buffer. */ - uint8_t *txbuf; - /** Pointer to receiving data buffer. */ - uint8_t *rxbuf; - /** Count number of data transmitted. */ - uint32_t txcnt; - /** Count number of data received. */ - uint32_t rxcnt; - /** Data character size. */ - uint8_t char_size; -}; - -/** Check interrupt flag of RXC and update transaction runtime information. */ -static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) -{ - uint32_t data; - - if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { - return false; - } - - data = hri_sercomspi_read_DATA_reg(hw); - - if (ctrl->rxbuf) { - *ctrl->rxbuf++ = (uint8_t)data; - - if (ctrl->char_size > 1) { - *ctrl->rxbuf++ = (uint8_t)(data >> 8); - } - } - - ctrl->rxcnt++; - - return true; -} - -/** Check interrupt flag of DRE and update transaction runtime information. */ -static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, - uint16_t dummy) -{ - uint32_t data; - - if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { - return; - } - - if (ctrl->txbuf) { - data = *ctrl->txbuf++; - - if (ctrl->char_size > 1) { - data |= (*ctrl->txbuf) << 8; - ctrl->txbuf++; - } - } else { - data = dummy; - } - - ctrl->txcnt++; - hri_sercomspi_write_DATA_reg(hw, data); -} - -/** Check interrupt flag of ERROR and update transaction runtime information. */ -static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) -{ - if (SERCOM_SPI_INTFLAG_ERROR & iflag) { - hri_sercomspi_clear_STATUS_reg(hw, ~0); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return ERR_OVERFLOW; - } - - return ERR_NONE; -} - -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) -{ - void * hw = dev->prvt; - int32_t rc = 0; - struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; - - ASSERT(dev && hw); - - /* If settings are not applied (pending), we can not go on */ - if (hri_sercomspi_is_syncing( - hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { - return ERR_BUSY; - } - - /* SPI must be enabled to start synchronous transfer */ - if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_NOT_INITIALIZED; - } - - for (;;) { - uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); - - if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { - /* In master mode, do not start next byte before previous byte received - * to make better output waveform */ - if (ctrl.rxcnt >= ctrl.txcnt) { - _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); - } - } - - rc = _spi_err_check(iflag, hw); - - if (rc < 0) { - break; - } - if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { - rc = ctrl.txcnt; - break; - } - } - /* Wait until SPI bus idle */ - _spi_wait_bus_idle(hw); - - return rc; -} - -int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (state) { - hri_sercomspi_set_INTEN_DRE_bit(hw); - } else { - hri_sercomspi_clear_INTEN_DRE_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx(dev, state); -} - -int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev); - ASSERT(hw); - - if (state) { - hri_sercomspi_set_INTEN_RXC_bit(hw); - } else { - hri_sercomspi_clear_INTEN_RXC_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_rx(dev, state); -} - -int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) -{ - ASSERT(dev && dev->prvt); - - if (state) { - hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); - } else { - hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx_complete(dev, state); -} - -int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - typedef void (*func_t)(void); - struct _spi_async_dev *spid = dev; - - ASSERT(dev && (cb_type < SPI_DEV_CB_N)); - - func_t *p_ls = (func_t *)&spid->callbacks; - p_ls[cb_type] = (func_t)func; - - return ERR_NONE; -} - -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - return _spi_m_async_register_callback(dev, cb_type, func); -} - -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); -} - -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); -} - -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); - return true; - } - return false; -} - -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { - hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return true; - } - return false; -} - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - ASSERT(device); - - if (SPI_DEV_CB_ERROR == type) { - hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); - } -} - -/** - * \brief Enable/disable SPI slave interrupt - * - * param[in] device The pointer to SPI slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - _spi_m_async_set_irq_state(device, type, state); -} + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ + | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ + | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ + | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ + | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_ctrlc_reg_t ctrl_c; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static struct _usart_async_device *_sercom2_dev = NULL; + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ + Sercom *const sercom_modules[] = SERCOM_INSTS; + /* Find index for SERCOM instance. */ + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { + return i; + } + } + return 0; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Sercom interrupt handler + * + * \param[in] p The pointer to interrupt parameter + */ +static void _sercom_usart_interrupt_handler(struct _usart_async_device *device) +{ + void *hw = device->hw; + + if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { + hri_sercomusart_clear_INTEN_DRE_bit(hw); + device->usart_cb.tx_byte_sent(device); + } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { + hri_sercomusart_clear_INTEN_TXC_bit(hw); + device->usart_cb.tx_done_cb(device); + } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { + if (hri_sercomusart_read_STATUS_reg(hw) + & (SERCOM_USART_STATUS_PERR | SERCOM_USART_STATUS_FERR | SERCOM_USART_STATUS_BUFOVF + | SERCOM_USART_STATUS_ISF | SERCOM_USART_STATUS_COLL)) { + hri_sercomusart_clear_STATUS_reg(hw, SERCOM_USART_STATUS_MASK); + return; + } + + device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); + } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { + uint32_t status; + + hri_sercomusart_clear_interrupt_ERROR_bit(hw); + device->usart_cb.error_cb(device); + status = hri_sercomusart_read_STATUS_reg(hw); + hri_sercomusart_clear_STATUS_reg(hw, status); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ + + if (hw == SERCOM2) { + _sercom2_dev = (struct _usart_async_device *)dev; + } +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_EnableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_0_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_1_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_2_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM2_3_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom2_dev); +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc.c index c50f65d..766be1d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc.c @@ -1,347 +1,347 @@ - -/** - * \file - * - * \brief SAM TC - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CONF_TC0_ENABLE -#define CONF_TC0_ENABLE 0 -#endif -#ifndef CONF_TC1_ENABLE -#define CONF_TC1_ENABLE 0 -#endif -#ifndef CONF_TC2_ENABLE -#define CONF_TC2_ENABLE 0 -#endif -#ifndef CONF_TC3_ENABLE -#define CONF_TC3_ENABLE 0 -#endif -#ifndef CONF_TC4_ENABLE -#define CONF_TC4_ENABLE 0 -#endif -#ifndef CONF_TC5_ENABLE -#define CONF_TC5_ENABLE 0 -#endif -#ifndef CONF_TC6_ENABLE -#define CONF_TC6_ENABLE 0 -#endif -#ifndef CONF_TC7_ENABLE -#define CONF_TC7_ENABLE 0 -#endif - -/** - * \brief Macro is used to fill usart configuration structure based on its - * number - * - * \param[in] n The number of structures - */ -#define TC_CONFIGURATION(n) \ - { \ - n, TC##n##_IRQn, \ - TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ - | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ - | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ - (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ - | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ - | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ - (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ - } -/** - * \brief TC configuration type - */ -struct tc_configuration { - uint8_t number; - IRQn_Type irq; - hri_tc_ctrla_reg_t ctrl_a; - hri_tc_evctrl_reg_t event_ctrl; - hri_tc_dbgctrl_reg_t dbg_ctrl; - hri_tccount8_per_reg_t per; - hri_tccount32_cc_reg_t cc0; - hri_tccount32_cc_reg_t cc1; -}; - -/** - * \brief Array of TC configurations - */ -static struct tc_configuration _tcs[] = { -#if CONF_TC0_ENABLE == 1 - TC_CONFIGURATION(0), -#endif -#if CONF_TC1_ENABLE == 1 - TC_CONFIGURATION(1), -#endif -#if CONF_TC2_ENABLE == 1 - TC_CONFIGURATION(2), -#endif -#if CONF_TC3_ENABLE == 1 - TC_CONFIGURATION(3), -#endif -#if CONF_TC4_ENABLE == 1 - TC_CONFIGURATION(4), -#endif -#if CONF_TC5_ENABLE == 1 - TC_CONFIGURATION(5), -#endif -#if CONF_TC6_ENABLE == 1 - TC_CONFIGURATION(6), -#endif -#if CONF_TC7_ENABLE == 1 - TC_CONFIGURATION(7), -#endif -}; - -static struct _timer_device *_tc0_dev = NULL; - -static int8_t get_tc_index(const void *const hw); -static void _tc_init_irq_param(const void *const hw, void *dev); -static inline uint8_t _get_hardware_offset(const void *const hw); -/** - * \brief Initialize TC - */ -int32_t _timer_init(struct _timer_device *const device, void *const hw) -{ - int8_t i = get_tc_index(hw); - - device->hw = hw; - ASSERT(ARRAY_SIZE(_tcs)); - - if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { - if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { - hri_tc_clear_CTRLA_ENABLE_bit(hw); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); - } - hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST); - } - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - - hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); - hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); - hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); - hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ); - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); - - } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { - hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); - hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1); - - } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { - hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); - hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1); - hri_tccount8_write_PER_reg(hw, _tcs[i].per); - } - hri_tc_set_INTEN_OVF_bit(hw); - - _tc_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ(_tcs[i].irq); - NVIC_ClearPendingIRQ(_tcs[i].irq); - NVIC_EnableIRQ(_tcs[i].irq); - - return ERR_NONE; -} -/** - * \brief De-initialize TC - */ -void _timer_deinit(struct _timer_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - ASSERT(ARRAY_SIZE(_tcs)); - - NVIC_DisableIRQ(_tcs[i].irq); - - hri_tc_clear_CTRLA_ENABLE_bit(hw); - hri_tc_set_CTRLA_SWRST_bit(hw); -} -/** - * \brief Start hardware timer - */ -void _timer_start(struct _timer_device *const device) -{ - hri_tc_set_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Stop hardware timer - */ -void _timer_stop(struct _timer_device *const device) -{ - hri_tc_clear_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Set timer period - */ -void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles) -{ - void *const hw = device->hw; - - if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - hri_tccount32_write_CC_reg(hw, 0, clock_cycles); - } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles); - } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - hri_tccount8_write_PER_reg(hw, clock_cycles); - } -} -/** - * \brief Retrieve timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const device) -{ - void *const hw = device->hw; - - if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - return hri_tccount32_read_CC_reg(hw, 0); - } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - return hri_tccount16_read_CC_reg(hw, 0); - } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { - return hri_tccount8_read_PER_reg(hw); - } - - return 0; -} -/** - * \brief Check if timer is running - */ -bool _timer_is_started(const struct _timer_device *const device) -{ - return hri_tc_get_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void) -{ - return NULL; -} - -/** - * \brief Retrieve pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void) -{ - return NULL; -} -/** - * \brief Set timer IRQ - * - * \param[in] hw The pointer to hardware instance - */ -void _timer_set_irq(struct _timer_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - ASSERT(ARRAY_SIZE(_tcs)); - - _irq_set(_tcs[i].irq); -} -/** - * \internal TC interrupt handler for Timer - * - * \param[in] instance TC instance number - */ -static void tc_interrupt_handler(struct _timer_device *device) -{ - void *const hw = device->hw; - - if (hri_tc_get_interrupt_OVF_bit(hw)) { - hri_tc_clear_interrupt_OVF_bit(hw); - device->timer_cb.period_expired(device); - } -} - -/** - * \brief TC interrupt handler - */ -void TC0_Handler(void) -{ - tc_interrupt_handler(_tc0_dev); -} - -/** - * \internal Retrieve TC index - * - * \param[in] hw The pointer to hardware instance - * - * \return The index of TC configuration - */ -static int8_t get_tc_index(const void *const hw) -{ - uint8_t index = _get_hardware_offset(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_tcs); i++) { - if (_tcs[i].number == index) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \brief Init irq param with the given tc hardware instance - */ -static void _tc_init_irq_param(const void *const hw, void *dev) -{ - if (hw == TC0) { - _tc0_dev = (struct _timer_device *)dev; - } -} - -/** - * \internal Retrieve TC hardware index - * - * \param[in] hw The pointer to hardware instance - */ -static inline uint8_t _get_hardware_offset(const void *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if ((uint32_t)hw == (uint32_t)tc_modules[i]) { - return i; - } - } - return 0; -} + +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 0 +#endif +#ifndef CONF_TC1_ENABLE +#define CONF_TC1_ENABLE 0 +#endif +#ifndef CONF_TC2_ENABLE +#define CONF_TC2_ENABLE 0 +#endif +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 0 +#endif +#ifndef CONF_TC4_ENABLE +#define CONF_TC4_ENABLE 0 +#endif +#ifndef CONF_TC5_ENABLE +#define CONF_TC5_ENABLE 0 +#endif +#ifndef CONF_TC6_ENABLE +#define CONF_TC6_ENABLE 0 +#endif +#ifndef CONF_TC7_ENABLE +#define CONF_TC7_ENABLE 0 +#endif + +/** + * \brief Macro is used to fill usart configuration structure based on its + * number + * + * \param[in] n The number of structures + */ +#define TC_CONFIGURATION(n) \ + { \ + n, TC##n##_IRQn, \ + TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ + | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ + | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ + (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ + | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ + | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ + (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ + } +/** + * \brief TC configuration type + */ +struct tc_configuration { + uint8_t number; + IRQn_Type irq; + hri_tc_ctrla_reg_t ctrl_a; + hri_tc_evctrl_reg_t event_ctrl; + hri_tc_dbgctrl_reg_t dbg_ctrl; + hri_tccount8_per_reg_t per; + hri_tccount32_cc_reg_t cc0; + hri_tccount32_cc_reg_t cc1; +}; + +/** + * \brief Array of TC configurations + */ +static struct tc_configuration _tcs[] = { +#if CONF_TC0_ENABLE == 1 + TC_CONFIGURATION(0), +#endif +#if CONF_TC1_ENABLE == 1 + TC_CONFIGURATION(1), +#endif +#if CONF_TC2_ENABLE == 1 + TC_CONFIGURATION(2), +#endif +#if CONF_TC3_ENABLE == 1 + TC_CONFIGURATION(3), +#endif +#if CONF_TC4_ENABLE == 1 + TC_CONFIGURATION(4), +#endif +#if CONF_TC5_ENABLE == 1 + TC_CONFIGURATION(5), +#endif +#if CONF_TC6_ENABLE == 1 + TC_CONFIGURATION(6), +#endif +#if CONF_TC7_ENABLE == 1 + TC_CONFIGURATION(7), +#endif +}; + +static struct _timer_device *_tc0_dev = NULL; + +static int8_t get_tc_index(const void *const hw); +static void _tc_init_irq_param(const void *const hw, void *dev); +static inline uint8_t _get_hardware_offset(const void *const hw); +/** + * \brief Initialize TC + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw) +{ + int8_t i = get_tc_index(hw); + + device->hw = hw; + ASSERT(ARRAY_SIZE(_tcs)); + + if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { + if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); + } + hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST); + } + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { + hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); + hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1); + hri_tccount8_write_PER_reg(hw, _tcs[i].per); + } + hri_tc_set_INTEN_OVF_bit(hw); + + _tc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ(_tcs[i].irq); + NVIC_ClearPendingIRQ(_tcs[i].irq); + NVIC_EnableIRQ(_tcs[i].irq); + + return ERR_NONE; +} +/** + * \brief De-initialize TC + */ +void _timer_deinit(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + NVIC_DisableIRQ(_tcs[i].irq); + + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_set_CTRLA_SWRST_bit(hw); +} +/** + * \brief Start hardware timer + */ +void _timer_start(struct _timer_device *const device) +{ + hri_tc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop hardware timer + */ +void _timer_stop(struct _timer_device *const device) +{ + hri_tc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set timer period + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount32_write_CC_reg(hw, 0, clock_cycles); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount8_write_PER_reg(hw, clock_cycles); + } +} +/** + * \brief Retrieve timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount32_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount16_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount8_read_PER_reg(hw); + } + + return 0; +} +/** + * \brief Check if timer is running + */ +bool _timer_is_started(const struct _timer_device *const device) +{ + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void) +{ + return NULL; +} +/** + * \brief Set timer IRQ + * + * \param[in] hw The pointer to hardware instance + */ +void _timer_set_irq(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + _irq_set(_tcs[i].irq); +} +/** + * \internal TC interrupt handler for Timer + * + * \param[in] instance TC instance number + */ +static void tc_interrupt_handler(struct _timer_device *device) +{ + void *const hw = device->hw; + + if (hri_tc_get_interrupt_OVF_bit(hw)) { + hri_tc_clear_interrupt_OVF_bit(hw); + device->timer_cb.period_expired(device); + } +} + +/** + * \brief TC interrupt handler + */ +void TC0_Handler(void) +{ + tc_interrupt_handler(_tc0_dev); +} + +/** + * \internal Retrieve TC index + * + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + uint8_t index = _get_hardware_offset(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_tcs); i++) { + if (_tcs[i].number == index) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \brief Init irq param with the given tc hardware instance + */ +static void _tc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TC0) { + _tc0_dev = (struct _timer_device *)dev; + } +} + +/** + * \internal Retrieve TC hardware index + * + * \param[in] hw The pointer to hardware instance + */ +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)tc_modules[i]) { + return i; + } + } + return 0; +} diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc_base.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc_base.h index ae77c90..cb59197 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc_base.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hpl/tc/hpl_tc_base.h @@ -1,77 +1,77 @@ -/** - * \file - * - * \brief SAM Timer/Counter - * - * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HPL_TC_BASE_H_INCLUDED -#define _HPL_TC_BASE_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup tc_group TC Hardware Proxy Layer - * - * \section tc_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void); - -/** - * \brief Retrieve pwm helper functions - * - * \return A pointer to set of pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void); - -//@} -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_TC_BASE_H_INCLUDED */ +/** + * \file + * + * \brief SAM Timer/Counter + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TC_BASE_H_INCLUDED +#define _HPL_TC_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tc_group TC Hardware Proxy Layer + * + * \section tc_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ac_e54.h index 588499e..47da91b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ac_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ac_e54.h @@ -1,1836 +1,1836 @@ -/** - * \file - * - * \brief SAM AC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_AC_COMPONENT_ -#ifndef _HRI_AC_E54_H_INCLUDED_ -#define _HRI_AC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AC_CRITICAL_SECTIONS) -#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AC_CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_ac_calib_reg_t; -typedef uint16_t hri_ac_evctrl_reg_t; -typedef uint32_t hri_ac_compctrl_reg_t; -typedef uint32_t hri_ac_syncbusy_reg_t; -typedef uint8_t hri_ac_ctrla_reg_t; -typedef uint8_t hri_ac_ctrlb_reg_t; -typedef uint8_t hri_ac_dbgctrl_reg_t; -typedef uint8_t hri_ac_intenset_reg_t; -typedef uint8_t hri_ac_intflag_reg_t; -typedef uint8_t hri_ac_scaler_reg_t; -typedef uint8_t hri_ac_statusa_reg_t; -typedef uint8_t hri_ac_statusb_reg_t; -typedef uint8_t hri_ac_winctrl_reg_t; - -static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - while (((Ac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - return ((Ac *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) -{ - return ((Ac *)hw)->INTFLAG.reg; -} - -static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - ((Ac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; -} - -static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; -} - -static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; - } -} - -static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; -} - -static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; -} - -static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; -} - -static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; - } -} - -static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; -} - -static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; -} - -static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; -} - -static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; - } -} - -static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; -} - -static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENSET.reg = mask; -} - -static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) -{ - return ((Ac *)hw)->INTENSET.reg; -} - -static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) -{ - ((Ac *)hw)->INTENSET.reg = data; - ((Ac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; -} - -static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSA.reg; -} - -static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; -} - -static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; -} - -static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSB.reg; -} - -static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Ac *)hw)->SYNCBUSY.reg; -} - -static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_ENABLE; - tmp |= value << AC_CTRLA_ENABLE_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - return ((Ac *)hw)->CTRLA.reg; -} - -static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO0; - tmp |= value << AC_EVCTRL_COMPEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO1; - tmp |= value << AC_EVCTRL_COMPEO1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_WINEO0; - tmp |= value << AC_EVCTRL_WINEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI0; - tmp |= value << AC_EVCTRL_COMPEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI1; - tmp |= value << AC_EVCTRL_COMPEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI0; - tmp |= value << AC_EVCTRL_INVEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI1; - tmp |= value << AC_EVCTRL_INVEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->EVCTRL.reg; -} - -static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= ~AC_DBGCTRL_DBGRUN; - tmp |= value << AC_DBGCTRL_DBGRUN_Pos; - ((Ac *)hw)->DBGCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->DBGCTRL.reg; -} - -static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WEN0; - tmp |= value << AC_WINCTRL_WEN0_Pos; - ((Ac *)hw)->WINCTRL.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WINTSEL0_Msk; - tmp |= AC_WINCTRL_WINTSEL0(data); - ((Ac *)hw)->WINCTRL.reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - return ((Ac *)hw)->WINCTRL.reg; -} - -static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, - hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= ~AC_SCALER_VALUE_Msk; - tmp |= AC_SCALER_VALUE(data); - ((Ac *)hw)->SCALER[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->SCALER[index].reg; -} - -static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_ENABLE; - tmp |= value << AC_COMPCTRL_ENABLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SINGLE; - tmp |= value << AC_COMPCTRL_SINGLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_RUNSTDBY; - tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SWAP; - tmp |= value << AC_COMPCTRL_SWAP_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYSTEN; - tmp |= value << AC_COMPCTRL_HYSTEN_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_INTSEL_Msk; - tmp |= AC_COMPCTRL_INTSEL(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXNEG_Msk; - tmp |= AC_COMPCTRL_MUXNEG(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXPOS_Msk; - tmp |= AC_COMPCTRL_MUXPOS(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SPEED_Msk; - tmp |= AC_COMPCTRL_SPEED(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYST_Msk; - tmp |= AC_COMPCTRL_HYST(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_FLEN_Msk; - tmp |= AC_COMPCTRL_FLEN(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_OUT_Msk; - tmp |= AC_COMPCTRL_OUT(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg = data; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= mask; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) -{ - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - return ((Ac *)hw)->COMPCTRL[index].reg; -} - -static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; - return tmp; -} - -static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->CALIB.reg; - tmp &= ~AC_CALIB_BIAS0_Msk; - tmp |= AC_CALIB_BIAS0(data); - ((Ac *)hw)->CALIB.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; - return tmp; -} - -static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) -{ - return ((Ac *)hw)->CALIB.reg; -} - -static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AC_E54_H_INCLUDED */ -#endif /* _SAME54_AC_COMPONENT_ */ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AC_COMPONENT_ +#ifndef _HRI_AC_E54_H_INCLUDED_ +#define _HRI_AC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_calib_reg_t; +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= ~AC_CALIB_BIAS0_Msk; + tmp |= AC_CALIB_BIAS0(data); + ((Ac *)hw)->CALIB.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) +{ + return ((Ac *)hw)->CALIB.reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_E54_H_INCLUDED */ +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_adc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_adc_e54.h index 7bb7e6f..60fbe63 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_adc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_adc_e54.h @@ -1,3663 +1,3663 @@ -/** - * \file - * - * \brief SAM ADC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_ADC_COMPONENT_ -#ifndef _HRI_ADC_E54_H_INCLUDED_ -#define _HRI_ADC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ADC_CRITICAL_SECTIONS) -#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ADC_CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_adc_calib_reg_t; -typedef uint16_t hri_adc_ctrla_reg_t; -typedef uint16_t hri_adc_ctrlb_reg_t; -typedef uint16_t hri_adc_gaincorr_reg_t; -typedef uint16_t hri_adc_inputctrl_reg_t; -typedef uint16_t hri_adc_offsetcorr_reg_t; -typedef uint16_t hri_adc_ress_reg_t; -typedef uint16_t hri_adc_result_reg_t; -typedef uint16_t hri_adc_winlt_reg_t; -typedef uint16_t hri_adc_winut_reg_t; -typedef uint32_t hri_adc_dseqctrl_reg_t; -typedef uint32_t hri_adc_dseqdata_reg_t; -typedef uint32_t hri_adc_dseqstat_reg_t; -typedef uint32_t hri_adc_syncbusy_reg_t; -typedef uint8_t hri_adc_avgctrl_reg_t; -typedef uint8_t hri_adc_dbgctrl_reg_t; -typedef uint8_t hri_adc_evctrl_reg_t; -typedef uint8_t hri_adc_intenset_reg_t; -typedef uint8_t hri_adc_intflag_reg_t; -typedef uint8_t hri_adc_refctrl_reg_t; -typedef uint8_t hri_adc_sampctrl_reg_t; -typedef uint8_t hri_adc_status_reg_t; -typedef uint8_t hri_adc_swtrig_reg_t; - -static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - while (((Adc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - return ((Adc *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) -{ - return ((Adc *)hw)->INTFLAG.reg; -} - -static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - ((Adc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; -} - -static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; -} - -static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; - } -} - -static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; -} - -static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; -} - -static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; -} - -static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; - } -} - -static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; -} - -static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; -} - -static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; -} - -static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; - } -} - -static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; -} - -static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENSET.reg = mask; -} - -static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) -{ - return ((Adc *)hw)->INTENSET.reg; -} - -static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) -{ - ((Adc *)hw)->INTENSET.reg = data; - ((Adc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) -{ - return ((Adc *)hw)->STATUS.reg; -} - -static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Adc *)hw)->SYNCBUSY.reg; -} - -static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; -} - -static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQSTAT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->DSEQSTAT.reg; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESULT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) -{ - return ((Adc *)hw)->RESULT.reg; -} - -static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) -{ - return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; -} - -static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) -{ - return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; -} - -static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) -{ - return ((Adc *)hw)->RESS.reg; -} - -static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ENABLE; - tmp |= value << ADC_CTRLA_ENABLE_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_SLAVEEN; - tmp |= value << ADC_CTRLA_SLAVEEN_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_RUNSTDBY; - tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ONDEMAND; - tmp |= value << ADC_CTRLA_ONDEMAND_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_R2R; - tmp |= value << ADC_CTRLA_R2R_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_DUALSEL_Msk; - tmp |= ADC_CTRLA_DUALSEL(data); - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_PRESCALER_Msk; - tmp |= ADC_CTRLA_PRESCALER(data); - ((Adc *)hw)->CTRLA.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - return ((Adc *)hw)->CTRLA.reg; -} - -static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHEI; - tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTEI; - tmp |= value << ADC_EVCTRL_STARTEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHINV; - tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTINV; - tmp |= value << ADC_EVCTRL_STARTINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_RESRDYEO; - tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_WINMONEO; - tmp |= value << ADC_EVCTRL_WINMONEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->EVCTRL.reg; -} - -static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= ~ADC_DBGCTRL_DBGRUN; - tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; - ((Adc *)hw)->DBGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->DBGCTRL.reg; -} - -static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_DIFFMODE; - tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_DSEQSTOP; - tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; - tmp |= ADC_INPUTCTRL_MUXPOS(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; - tmp |= ADC_INPUTCTRL_MUXNEG(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->INPUTCTRL.reg; -} - -static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_LEFTADJ; - tmp |= value << ADC_CTRLB_LEFTADJ_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_FREERUN; - tmp |= value << ADC_CTRLB_FREERUN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_CORREN; - tmp |= value << ADC_CTRLB_CORREN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_WINSS; - tmp |= value << ADC_CTRLB_WINSS_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_RESSEL_Msk; - tmp |= ADC_CTRLB_RESSEL(data); - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_WINMODE_Msk; - tmp |= ADC_CTRLB_WINMODE(data); - ((Adc *)hw)->CTRLB.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->CTRLB.reg; -} - -static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFCOMP; - tmp |= value << ADC_REFCTRL_REFCOMP_Pos; - ((Adc *)hw)->REFCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFSEL_Msk; - tmp |= ADC_REFCTRL_REFSEL(data); - ((Adc *)hw)->REFCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->REFCTRL.reg; -} - -static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; - tmp |= ADC_AVGCTRL_SAMPLENUM(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_ADJRES_Msk; - tmp |= ADC_AVGCTRL_ADJRES(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->AVGCTRL.reg; -} - -static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_OFFCOMP; - tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; - ((Adc *)hw)->SAMPCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; - tmp |= ADC_SAMPCTRL_SAMPLEN(data); - ((Adc *)hw)->SAMPCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->SAMPCTRL.reg; -} - -static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= ~ADC_WINLT_WINLT_Msk; - tmp |= ADC_WINLT_WINLT(data); - ((Adc *)hw)->WINLT.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - return ((Adc *)hw)->WINLT.reg; -} - -static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= ~ADC_WINUT_WINUT_Msk; - tmp |= ADC_WINUT_WINUT(data); - ((Adc *)hw)->WINUT.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - return ((Adc *)hw)->WINUT.reg; -} - -static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= ~ADC_GAINCORR_GAINCORR_Msk; - tmp |= ADC_GAINCORR_GAINCORR(data); - ((Adc *)hw)->GAINCORR.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - return ((Adc *)hw)->GAINCORR.reg; -} - -static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, - hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; - tmp |= ADC_OFFSETCORR_OFFSETCORR(data); - ((Adc *)hw)->OFFSETCORR.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->OFFSETCORR.reg; -} - -static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_FLUSH; - tmp |= value << ADC_SWTRIG_FLUSH_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_START; - tmp |= value << ADC_SWTRIG_START_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg = data; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= mask; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - return ((Adc *)hw)->SWTRIG.reg; -} - -static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_INPUTCTRL; - tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_CTRLB; - tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_REFCTRL; - tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_AVGCTRL; - tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_SAMPCTRL; - tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_WINLT; - tmp |= value << ADC_DSEQCTRL_WINLT_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_WINUT; - tmp |= value << ADC_DSEQCTRL_WINUT_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_GAINCORR; - tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_OFFSETCORR; - tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_AUTOSTART; - tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= mask; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg = data; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~mask; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= mask; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return ((Adc *)hw)->DSEQCTRL.reg; -} - -static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASCOMP_Msk; - tmp |= ADC_CALIB_BIASCOMP(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASR2R_Msk; - tmp |= ADC_CALIB_BIASR2R(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASREFBUF_Msk; - tmp |= ADC_CALIB_BIASREFBUF(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) -{ - return ((Adc *)hw)->CALIB.reg; -} - -static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQDATA.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ADC_E54_H_INCLUDED */ -#endif /* _SAME54_ADC_COMPONENT_ */ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ADC_COMPONENT_ +#ifndef _HRI_ADC_E54_H_INCLUDED_ +#define _HRI_ADC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrla_reg_t; +typedef uint16_t hri_adc_ctrlb_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_ress_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_dseqctrl_reg_t; +typedef uint32_t hri_adc_dseqdata_reg_t; +typedef uint32_t hri_adc_dseqstat_reg_t; +typedef uint32_t hri_adc_syncbusy_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_status_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->STATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQSTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQSTAT.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) +{ + return ((Adc *)hw)->RESS.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_R2R; + tmp |= value << ADC_CTRLA_R2R_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_DUALSEL_Msk; + tmp |= ADC_CTRLA_DUALSEL(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_PRESCALER_Msk; + tmp |= ADC_CTRLA_PRESCALER(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DIFFMODE; + tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DSEQSTOP; + tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_LEFTADJ; + tmp |= value << ADC_CTRLB_LEFTADJ_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_FREERUN; + tmp |= value << ADC_CTRLB_FREERUN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_CORREN; + tmp |= value << ADC_CTRLB_CORREN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINSS; + tmp |= value << ADC_CTRLB_WINSS_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_RESSEL_Msk; + tmp |= ADC_CTRLB_RESSEL(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINMODE_Msk; + tmp |= ADC_CTRLB_WINMODE(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_INPUTCTRL; + tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_CTRLB; + tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_REFCTRL; + tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AVGCTRL; + tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_SAMPCTRL; + tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINLT; + tmp |= value << ADC_DSEQCTRL_WINLT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINUT; + tmp |= value << ADC_DSEQCTRL_WINUT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_GAINCORR; + tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_OFFSETCORR; + tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AUTOSTART; + tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg = data; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASR2R_Msk; + tmp |= ADC_CALIB_BIASR2R(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQDATA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_E54_H_INCLUDED */ +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_aes_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_aes_e54.h index c1070e2..015cbba 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_aes_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_aes_e54.h @@ -1,1287 +1,1287 @@ -/** - * \file - * - * \brief SAM AES - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_AES_COMPONENT_ -#ifndef _HRI_AES_E54_H_INCLUDED_ -#define _HRI_AES_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AES_CRITICAL_SECTIONS) -#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AES_CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_aes_ciplen_reg_t; -typedef uint32_t hri_aes_ctrla_reg_t; -typedef uint32_t hri_aes_ghash_reg_t; -typedef uint32_t hri_aes_hashkey_reg_t; -typedef uint32_t hri_aes_indata_reg_t; -typedef uint32_t hri_aes_intvectv_reg_t; -typedef uint32_t hri_aes_keyword_reg_t; -typedef uint32_t hri_aes_randseed_reg_t; -typedef uint8_t hri_aes_ctrlb_reg_t; -typedef uint8_t hri_aes_databufptr_reg_t; -typedef uint8_t hri_aes_dbgctrl_reg_t; -typedef uint8_t hri_aes_intenset_reg_t; -typedef uint8_t hri_aes_intflag_reg_t; - -static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) -{ - return ((Aes *)hw)->INTFLAG.reg; -} - -static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - ((Aes *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; -} - -static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; -} - -static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; - } -} - -static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; -} - -static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; -} - -static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; -} - -static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; - } -} - -static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; -} - -static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENSET.reg = mask; -} - -static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) -{ - return ((Aes *)hw)->INTENSET.reg; -} - -static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) -{ - ((Aes *)hw)->INTENSET.reg = data; - ((Aes *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_ENABLE; - tmp |= value << AES_CTRLA_ENABLE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CIPHER; - tmp |= value << AES_CTRLA_CIPHER_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_STARTMODE; - tmp |= value << AES_CTRLA_STARTMODE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_LOD; - tmp |= value << AES_CTRLA_LOD_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYGEN; - tmp |= value << AES_CTRLA_KEYGEN_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_XORKEY; - tmp |= value << AES_CTRLA_XORKEY_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_AESMODE_Msk; - tmp |= AES_CTRLA_AESMODE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CFBS_Msk; - tmp |= AES_CTRLA_CFBS(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYSIZE_Msk; - tmp |= AES_CTRLA_KEYSIZE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CTYPE_Msk; - tmp |= AES_CTRLA_CTYPE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLA.reg; -} - -static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_START; - tmp |= value << AES_CTRLB_START_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_NEWMSG; - tmp |= value << AES_CTRLB_NEWMSG_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_EOM; - tmp |= value << AES_CTRLB_EOM_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_GFMUL; - tmp |= value << AES_CTRLB_GFMUL_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLB.reg; -} - -static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, - hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; - tmp |= AES_DATABUFPTR_INDATAPTR(data); - ((Aes *)hw)->DATABUFPTR.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) -{ - return ((Aes *)hw)->DATABUFPTR.reg; -} - -static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp &= ~AES_DBGCTRL_DBGRUN; - tmp |= value << AES_DBGCTRL_DBGRUN_Pos; - ((Aes *)hw)->DBGCTRL.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) -{ - return ((Aes *)hw)->DBGCTRL.reg; -} - -static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->INDATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) -{ - return ((Aes *)hw)->INDATA.reg; -} - -static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, - hri_aes_hashkey_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->HASHKEY[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->HASHKEY[index].reg; -} - -static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->GHASH[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->GHASH[index].reg; -} - -static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CIPLEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) -{ - return ((Aes *)hw)->CIPLEN.reg; -} - -static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->RANDSEED.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) -{ - return ((Aes *)hw)->RANDSEED.reg; -} - -static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->KEYWORD[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INTVECTV[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AES_E54_H_INCLUDED */ -#endif /* _SAME54_AES_COMPONENT_ */ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AES_COMPONENT_ +#ifndef _HRI_AES_E54_H_INCLUDED_ +#define _HRI_AES_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= ~AES_DBGCTRL_DBGRUN; + tmp |= value << AES_DBGCTRL_DBGRUN_Pos; + ((Aes *)hw)->DBGCTRL.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) +{ + return ((Aes *)hw)->DBGCTRL.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_E54_H_INCLUDED */ +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_can_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_can_e54.h index 2c02884..bff59b1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_can_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_can_e54.h @@ -1,16997 +1,16997 @@ -/** - * \file - * - * \brief SAM CAN - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_CAN_COMPONENT_ -#ifndef _HRI_CAN_E54_H_INCLUDED_ -#define _HRI_CAN_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CAN_CRITICAL_SECTIONS) -#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CAN_CRITICAL_SECTION_ENTER() -#define CAN_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_can_cccr_reg_t; -typedef uint32_t hri_can_crel_reg_t; -typedef uint32_t hri_can_dbtp_reg_t; -typedef uint32_t hri_can_ecr_reg_t; -typedef uint32_t hri_can_endn_reg_t; -typedef uint32_t hri_can_gfc_reg_t; -typedef uint32_t hri_can_hpms_reg_t; -typedef uint32_t hri_can_ie_reg_t; -typedef uint32_t hri_can_ile_reg_t; -typedef uint32_t hri_can_ils_reg_t; -typedef uint32_t hri_can_ir_reg_t; -typedef uint32_t hri_can_mrcfg_reg_t; -typedef uint32_t hri_can_nbtp_reg_t; -typedef uint32_t hri_can_ndat1_reg_t; -typedef uint32_t hri_can_ndat2_reg_t; -typedef uint32_t hri_can_psr_reg_t; -typedef uint32_t hri_can_rwd_reg_t; -typedef uint32_t hri_can_rxbc_reg_t; -typedef uint32_t hri_can_rxesc_reg_t; -typedef uint32_t hri_can_rxf0a_reg_t; -typedef uint32_t hri_can_rxf0c_reg_t; -typedef uint32_t hri_can_rxf0s_reg_t; -typedef uint32_t hri_can_rxf1a_reg_t; -typedef uint32_t hri_can_rxf1c_reg_t; -typedef uint32_t hri_can_rxf1s_reg_t; -typedef uint32_t hri_can_sidfc_reg_t; -typedef uint32_t hri_can_tdcr_reg_t; -typedef uint32_t hri_can_test_reg_t; -typedef uint32_t hri_can_tocc_reg_t; -typedef uint32_t hri_can_tocv_reg_t; -typedef uint32_t hri_can_tscc_reg_t; -typedef uint32_t hri_can_tscv_reg_t; -typedef uint32_t hri_can_txbar_reg_t; -typedef uint32_t hri_can_txbc_reg_t; -typedef uint32_t hri_can_txbcf_reg_t; -typedef uint32_t hri_can_txbcie_reg_t; -typedef uint32_t hri_can_txbcr_reg_t; -typedef uint32_t hri_can_txbrp_reg_t; -typedef uint32_t hri_can_txbtie_reg_t; -typedef uint32_t hri_can_txbto_reg_t; -typedef uint32_t hri_can_txefa_reg_t; -typedef uint32_t hri_can_txefc_reg_t; -typedef uint32_t hri_can_txefs_reg_t; -typedef uint32_t hri_can_txesc_reg_t; -typedef uint32_t hri_can_txfqs_reg_t; -typedef uint32_t hri_can_xidam_reg_t; -typedef uint32_t hri_can_xidfc_reg_t; - -static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; -} - -static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) -{ - return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; -} - -static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CREL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) -{ - return ((Can *)hw)->CREL.reg; -} - -static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) -{ - return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; -} - -static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) -{ - return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; -} - -static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ENDN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) -{ - return ((Can *)hw)->ENDN.reg; -} - -static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) -{ - return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; -} - -static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) -{ - return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; -} - -static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCV.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) -{ - return ((Can *)hw)->TSCV.reg; -} - -static inline bool hri_can_get_ECR_RP_bit(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) -{ - return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; -} - -static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ECR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) -{ - return ((Can *)hw)->ECR.reg; -} - -static inline bool hri_can_get_PSR_EP_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; -} - -static inline bool hri_can_get_PSR_EW_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; -} - -static inline bool hri_can_get_PSR_BO_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; -} - -static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; -} - -static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; -} - -static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; -} - -static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) -{ - return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; -} - -static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->PSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) -{ - return ((Can *)hw)->PSR.reg; -} - -static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) -{ - return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; -} - -static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->HPMS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) -{ - return ((Can *)hw)->HPMS.reg; -} - -static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; -} - -static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; -} - -static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0S.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) -{ - return ((Can *)hw)->RXF0S.reg; -} - -static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; -} - -static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) -{ - return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; -} - -static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1S.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) -{ - return ((Can *)hw)->RXF1S.reg; -} - -static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) -{ - return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; -} - -static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXFQS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) -{ - return ((Can *)hw)->TXFQS.reg; -} - -static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; -} - -static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) -{ - return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; -} - -static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBRP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) -{ - return ((Can *)hw)->TXBRP.reg; -} - -static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; -} - -static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; -} - -static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; -} - -static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; -} - -static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; -} - -static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; -} - -static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; -} - -static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; -} - -static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; -} - -static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; -} - -static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; -} - -static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; -} - -static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; -} - -static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; -} - -static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; -} - -static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; -} - -static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; -} - -static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; -} - -static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; -} - -static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; -} - -static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; -} - -static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; -} - -static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; -} - -static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; -} - -static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; -} - -static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; -} - -static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; -} - -static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; -} - -static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; -} - -static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; -} - -static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; -} - -static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) -{ - return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; -} - -static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTO.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) -{ - return ((Can *)hw)->TXBTO.reg; -} - -static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; -} - -static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; -} - -static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; -} - -static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; -} - -static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; -} - -static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; -} - -static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; -} - -static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; -} - -static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; -} - -static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; -} - -static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; -} - -static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; -} - -static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; -} - -static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; -} - -static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; -} - -static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; -} - -static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; -} - -static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; -} - -static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; -} - -static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; -} - -static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; -} - -static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; -} - -static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; -} - -static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; -} - -static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; -} - -static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; -} - -static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; -} - -static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; -} - -static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; -} - -static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; -} - -static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; -} - -static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) -{ - return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; -} - -static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) -{ - return ((Can *)hw)->TXBCF.reg; -} - -static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; -} - -static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) -{ - return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; -} - -static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) -{ - return ((Can *)hw)->TXEFS.reg; -} - -static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->MRCFG.reg; - tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; - return tmp; -} - -static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->MRCFG.reg; - tmp &= ~CAN_MRCFG_QOS_Msk; - tmp |= CAN_MRCFG_QOS(data); - ((Can *)hw)->MRCFG.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->MRCFG.reg; - tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; - return tmp; -} - -static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->MRCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->MRCFG.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) -{ - return ((Can *)hw)->MRCFG.reg; -} - -static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_TDC; - tmp |= value << CAN_DBTP_TDC_Pos; - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DSJW_Msk; - tmp |= CAN_DBTP_DSJW(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DTSEG2_Msk; - tmp |= CAN_DBTP_DTSEG2(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DTSEG1_Msk; - tmp |= CAN_DBTP_DTSEG1(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; - return tmp; -} - -static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->DBTP.reg; - tmp &= ~CAN_DBTP_DBRP_Msk; - tmp |= CAN_DBTP_DBRP(data); - ((Can *)hw)->DBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; - return tmp; -} - -static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->DBTP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->DBTP.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) -{ - return ((Can *)hw)->DBTP.reg; -} - -static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TEST.reg; - tmp &= ~CAN_TEST_LBCK; - tmp |= value << CAN_TEST_LBCK_Pos; - ((Can *)hw)->TEST.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TEST_RX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= CAN_TEST_RX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TEST_RX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TEST.reg; - tmp &= ~CAN_TEST_RX; - tmp |= value << CAN_TEST_RX_Pos; - ((Can *)hw)->TEST.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_RX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; - return tmp; -} - -static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TEST.reg; - tmp &= ~CAN_TEST_TX_Msk; - tmp |= CAN_TEST_TX(data); - ((Can *)hw)->TEST.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; - return tmp; -} - -static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TEST.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TEST.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) -{ - return ((Can *)hw)->TEST.reg; -} - -static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; - return tmp; -} - -static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RWD.reg; - tmp &= ~CAN_RWD_WDC_Msk; - tmp |= CAN_RWD_WDC(data); - ((Can *)hw)->RWD.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; - return tmp; -} - -static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; - return tmp; -} - -static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RWD.reg; - tmp &= ~CAN_RWD_WDV_Msk; - tmp |= CAN_RWD_WDV(data); - ((Can *)hw)->RWD.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; - return tmp; -} - -static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RWD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RWD.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) -{ - return ((Can *)hw)->RWD.reg; -} - -static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_INIT; - tmp |= value << CAN_CCCR_INIT_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_CCE; - tmp |= value << CAN_CCCR_CCE_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_ASM; - tmp |= value << CAN_CCCR_ASM_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_CSA; - tmp |= value << CAN_CCCR_CSA_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_CSR; - tmp |= value << CAN_CCCR_CSR_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_MON_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_MON; - tmp |= value << CAN_CCCR_MON_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_DAR; - tmp |= value << CAN_CCCR_DAR_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_TEST; - tmp |= value << CAN_CCCR_TEST_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_FDOE; - tmp |= value << CAN_CCCR_FDOE_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_BRSE; - tmp |= value << CAN_CCCR_BRSE_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_PXHD; - tmp |= value << CAN_CCCR_PXHD_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_EFBI; - tmp |= value << CAN_CCCR_EFBI_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_TXP; - tmp |= value << CAN_CCCR_TXP_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->CCCR.reg; - tmp &= ~CAN_CCCR_NISO; - tmp |= value << CAN_CCCR_NISO_Pos; - ((Can *)hw)->CCCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->CCCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->CCCR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) -{ - return ((Can *)hw)->CCCR.reg; -} - -static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NTSEG2_Msk; - tmp |= CAN_NBTP_NTSEG2(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NTSEG1_Msk; - tmp |= CAN_NBTP_NTSEG1(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NBRP_Msk; - tmp |= CAN_NBTP_NBRP(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; - return tmp; -} - -static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NBTP.reg; - tmp &= ~CAN_NBTP_NSJW_Msk; - tmp |= CAN_NBTP_NSJW(data); - ((Can *)hw)->NBTP.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; - return tmp; -} - -static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NBTP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NBTP.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) -{ - return ((Can *)hw)->NBTP.reg; -} - -static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; - return tmp; -} - -static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TSCC.reg; - tmp &= ~CAN_TSCC_TSS_Msk; - tmp |= CAN_TSCC_TSS(data); - ((Can *)hw)->TSCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; - return tmp; -} - -static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; - return tmp; -} - -static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TSCC.reg; - tmp &= ~CAN_TSCC_TCP_Msk; - tmp |= CAN_TSCC_TCP(data); - ((Can *)hw)->TSCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; - return tmp; -} - -static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TSCC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TSCC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) -{ - return ((Can *)hw)->TSCC.reg; -} - -static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCC.reg; - tmp &= ~CAN_TOCC_ETOC; - tmp |= value << CAN_TOCC_ETOC_Pos; - ((Can *)hw)->TOCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; - return tmp; -} - -static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCC.reg; - tmp &= ~CAN_TOCC_TOS_Msk; - tmp |= CAN_TOCC_TOS(data); - ((Can *)hw)->TOCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; - return tmp; -} - -static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; - return tmp; -} - -static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCC.reg; - tmp &= ~CAN_TOCC_TOP_Msk; - tmp |= CAN_TOCC_TOP(data); - ((Can *)hw)->TOCC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; - return tmp; -} - -static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) -{ - return ((Can *)hw)->TOCC.reg; -} - -static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCV.reg; - tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; - return tmp; -} - -static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TOCV.reg; - tmp &= ~CAN_TOCV_TOC_Msk; - tmp |= CAN_TOCV_TOC(data); - ((Can *)hw)->TOCV.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCV.reg; - tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; - return tmp; -} - -static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TOCV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TOCV.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) -{ - return ((Can *)hw)->TOCV.reg; -} - -static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; - return tmp; -} - -static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TDCR.reg; - tmp &= ~CAN_TDCR_TDCF_Msk; - tmp |= CAN_TDCR_TDCF(data); - ((Can *)hw)->TDCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; - return tmp; -} - -static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; - return tmp; -} - -static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TDCR.reg; - tmp &= ~CAN_TDCR_TDCO_Msk; - tmp |= CAN_TDCR_TDCO(data); - ((Can *)hw)->TDCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; - return tmp; -} - -static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TDCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TDCR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) -{ - return ((Can *)hw)->TDCR.reg; -} - -static inline void hri_can_set_IR_RF0N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0N; - tmp |= value << CAN_IR_RF0N_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF0W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0W; - tmp |= value << CAN_IR_RF0W_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF0F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0F; - tmp |= value << CAN_IR_RF0F_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF0L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF0L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF0L; - tmp |= value << CAN_IR_RF0L_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1N; - tmp |= value << CAN_IR_RF1N_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1W; - tmp |= value << CAN_IR_RF1W_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1F; - tmp |= value << CAN_IR_RF1F_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_RF1L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_RF1L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_RF1L; - tmp |= value << CAN_IR_RF1L_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_HPM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_HPM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_HPM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_HPM; - tmp |= value << CAN_IR_HPM_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_HPM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_HPM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TC; - tmp |= value << CAN_IR_TC_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TCF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TCF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TCF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TCF; - tmp |= value << CAN_IR_TCF_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TCF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TCF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TFE; - tmp |= value << CAN_IR_TFE_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFN_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFN; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFN; - tmp |= value << CAN_IR_TEFN_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFW; - tmp |= value << CAN_IR_TEFW_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFF; - tmp |= value << CAN_IR_TEFF_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TEFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TEFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TEFL; - tmp |= value << CAN_IR_TEFL_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TSW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TSW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TSW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TSW; - tmp |= value << CAN_IR_TSW_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TSW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TSW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_MRAF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_MRAF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_MRAF; - tmp |= value << CAN_IR_MRAF_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_TOO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_TOO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_TOO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_TOO; - tmp |= value << CAN_IR_TOO_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_TOO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_TOO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_DRX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_DRX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_DRX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_DRX; - tmp |= value << CAN_IR_DRX_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_DRX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_DRX; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_BEC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_BEC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_BEC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_BEC; - tmp |= value << CAN_IR_BEC_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_BEC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_BEC; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_BEU_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_BEU; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_BEU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_BEU; - tmp |= value << CAN_IR_BEU_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_BEU_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_BEU; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_ELO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_ELO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_ELO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_ELO; - tmp |= value << CAN_IR_ELO_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_ELO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_ELO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_EP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_EP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_EP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_EP; - tmp |= value << CAN_IR_EP_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_EP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_EP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_EP_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_EP; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_EW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_EW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_EW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_EW; - tmp |= value << CAN_IR_EW_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_EW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_EW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_EW_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_EW; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_BO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_BO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_BO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_BO; - tmp |= value << CAN_IR_BO_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_BO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_BO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_BO_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_BO; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_WDI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_WDI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_WDI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_WDI; - tmp |= value << CAN_IR_WDI_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_WDI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_WDI; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_PEA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_PEA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_PEA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_PEA; - tmp |= value << CAN_IR_PEA_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_PEA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_PEA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_PED_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_PED; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_PED_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_PED; - tmp |= value << CAN_IR_PED_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_PED_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_PED; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_PED_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_PED; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_ARA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= CAN_IR_ARA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IR_ARA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IR.reg; - tmp &= ~CAN_IR_ARA; - tmp |= value << CAN_IR_ARA_Pos; - ((Can *)hw)->IR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_ARA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= CAN_IR_ARA; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) -{ - return ((Can *)hw)->IR.reg; -} - -static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0NE; - tmp |= value << CAN_IE_RF0NE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0WE; - tmp |= value << CAN_IE_RF0WE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0FE; - tmp |= value << CAN_IE_RF0FE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF0LE; - tmp |= value << CAN_IE_RF0LE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1NE; - tmp |= value << CAN_IE_RF1NE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1WE; - tmp |= value << CAN_IE_RF1WE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1FE; - tmp |= value << CAN_IE_RF1FE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_RF1LE; - tmp |= value << CAN_IE_RF1LE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_HPME_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_HPME; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_HPME_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_HPME; - tmp |= value << CAN_IE_HPME_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_HPME_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_HPME; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TCE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TCE; - tmp |= value << CAN_IE_TCE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TCE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TCFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TCFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TCFE; - tmp |= value << CAN_IE_TCFE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TFEE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TFEE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TFEE; - tmp |= value << CAN_IE_TFEE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFNE; - tmp |= value << CAN_IE_TEFNE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFWE; - tmp |= value << CAN_IE_TEFWE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFFE; - tmp |= value << CAN_IE_TEFFE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TEFLE; - tmp |= value << CAN_IE_TEFLE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TSWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TSWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TSWE; - tmp |= value << CAN_IE_TSWE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_MRAFE; - tmp |= value << CAN_IE_MRAFE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_TOOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_TOOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_TOOE; - tmp |= value << CAN_IE_TOOE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_DRXE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_DRXE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_DRXE; - tmp |= value << CAN_IE_DRXE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_BECE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_BECE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_BECE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_BECE; - tmp |= value << CAN_IE_BECE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_BECE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_BECE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_BEUE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_BEUE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_BEUE; - tmp |= value << CAN_IE_BEUE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_ELOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_ELOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_ELOE; - tmp |= value << CAN_IE_ELOE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_EPE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_EPE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_EPE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_EPE; - tmp |= value << CAN_IE_EPE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_EPE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_EPE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_EWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_EWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_EWE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_EWE; - tmp |= value << CAN_IE_EWE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_EWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_EWE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_BOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_BOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_BOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_BOE; - tmp |= value << CAN_IE_BOE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_BOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_BOE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_WDIE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_WDIE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_WDIE; - tmp |= value << CAN_IE_WDIE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_PEAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_PEAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_PEAE; - tmp |= value << CAN_IE_PEAE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_PEDE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_PEDE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_PEDE; - tmp |= value << CAN_IE_PEDE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_ARAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= CAN_IE_ARAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->IE.reg; - tmp &= ~CAN_IE_ARAE; - tmp |= value << CAN_IE_ARAE_Pos; - ((Can *)hw)->IE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->IE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->IE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) -{ - return ((Can *)hw)->IE.reg; -} - -static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0NL; - tmp |= value << CAN_ILS_RF0NL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0WL; - tmp |= value << CAN_ILS_RF0WL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0FL; - tmp |= value << CAN_ILS_RF0FL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF0LL; - tmp |= value << CAN_ILS_RF0LL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1NL; - tmp |= value << CAN_ILS_RF1NL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1WL; - tmp |= value << CAN_ILS_RF1WL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1FL; - tmp |= value << CAN_ILS_RF1FL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_RF1LL; - tmp |= value << CAN_ILS_RF1LL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_HPML_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_HPML; - tmp |= value << CAN_ILS_HPML_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TCL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TCL; - tmp |= value << CAN_ILS_TCL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TCFL; - tmp |= value << CAN_ILS_TCFL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TFEL; - tmp |= value << CAN_ILS_TFEL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFNL; - tmp |= value << CAN_ILS_TEFNL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFWL; - tmp |= value << CAN_ILS_TEFWL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFFL; - tmp |= value << CAN_ILS_TEFFL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TEFLL; - tmp |= value << CAN_ILS_TEFLL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TSWL; - tmp |= value << CAN_ILS_TSWL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_MRAFL; - tmp |= value << CAN_ILS_MRAFL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_TOOL; - tmp |= value << CAN_ILS_TOOL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_DRXL; - tmp |= value << CAN_ILS_DRXL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_BECL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_BECL; - tmp |= value << CAN_ILS_BECL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_BEUL; - tmp |= value << CAN_ILS_BEUL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_ELOL; - tmp |= value << CAN_ILS_ELOL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_EPL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_EPL; - tmp |= value << CAN_ILS_EPL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_EWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_EWL; - tmp |= value << CAN_ILS_EWL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_BOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_BOL; - tmp |= value << CAN_ILS_BOL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_WDIL; - tmp |= value << CAN_ILS_WDIL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_PEAL; - tmp |= value << CAN_ILS_PEAL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_PEDL; - tmp |= value << CAN_ILS_PEDL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILS.reg; - tmp &= ~CAN_ILS_ARAL; - tmp |= value << CAN_ILS_ARAL_Pos; - ((Can *)hw)->ILS.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILS.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) -{ - return ((Can *)hw)->ILS.reg; -} - -static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILE.reg; - tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILE.reg; - tmp &= ~CAN_ILE_EINT0; - tmp |= value << CAN_ILE_EINT0_Pos; - ((Can *)hw)->ILE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILE.reg; - tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->ILE.reg; - tmp &= ~CAN_ILE_EINT1; - tmp |= value << CAN_ILE_EINT1_Pos; - ((Can *)hw)->ILE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->ILE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->ILE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) -{ - return ((Can *)hw)->ILE.reg; -} - -static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_RRFE; - tmp |= value << CAN_GFC_RRFE_Pos; - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_RRFS; - tmp |= value << CAN_GFC_RRFS_Pos; - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; - return tmp; -} - -static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_ANFE_Msk; - tmp |= CAN_GFC_ANFE(data); - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; - return tmp; -} - -static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; - return tmp; -} - -static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->GFC.reg; - tmp &= ~CAN_GFC_ANFS_Msk; - tmp |= CAN_GFC_ANFS(data); - ((Can *)hw)->GFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; - return tmp; -} - -static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->GFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->GFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) -{ - return ((Can *)hw)->GFC.reg; -} - -static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; - return tmp; -} - -static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->SIDFC.reg; - tmp &= ~CAN_SIDFC_FLSSA_Msk; - tmp |= CAN_SIDFC_FLSSA(data); - ((Can *)hw)->SIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; - return tmp; -} - -static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; - return tmp; -} - -static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->SIDFC.reg; - tmp &= ~CAN_SIDFC_LSS_Msk; - tmp |= CAN_SIDFC_LSS(data); - ((Can *)hw)->SIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; - return tmp; -} - -static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->SIDFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->SIDFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) -{ - return ((Can *)hw)->SIDFC.reg; -} - -static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; - return tmp; -} - -static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->XIDFC.reg; - tmp &= ~CAN_XIDFC_FLESA_Msk; - tmp |= CAN_XIDFC_FLESA(data); - ((Can *)hw)->XIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; - return tmp; -} - -static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; - return tmp; -} - -static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->XIDFC.reg; - tmp &= ~CAN_XIDFC_LSE_Msk; - tmp |= CAN_XIDFC_LSE(data); - ((Can *)hw)->XIDFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; - return tmp; -} - -static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) -{ - return ((Can *)hw)->XIDFC.reg; -} - -static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDAM.reg; - tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; - return tmp; -} - -static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->XIDAM.reg; - tmp &= ~CAN_XIDAM_EIDM_Msk; - tmp |= CAN_XIDAM_EIDM(data); - ((Can *)hw)->XIDAM.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDAM.reg; - tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; - return tmp; -} - -static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->XIDAM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->XIDAM.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) -{ - return ((Can *)hw)->XIDAM.reg; -} - -static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND0; - tmp |= value << CAN_NDAT1_ND0_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND1; - tmp |= value << CAN_NDAT1_ND1_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND2; - tmp |= value << CAN_NDAT1_ND2_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND3; - tmp |= value << CAN_NDAT1_ND3_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND4; - tmp |= value << CAN_NDAT1_ND4_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND5; - tmp |= value << CAN_NDAT1_ND5_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND6; - tmp |= value << CAN_NDAT1_ND6_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND7; - tmp |= value << CAN_NDAT1_ND7_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND8; - tmp |= value << CAN_NDAT1_ND8_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND9; - tmp |= value << CAN_NDAT1_ND9_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND10; - tmp |= value << CAN_NDAT1_ND10_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND11; - tmp |= value << CAN_NDAT1_ND11_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND12; - tmp |= value << CAN_NDAT1_ND12_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND13; - tmp |= value << CAN_NDAT1_ND13_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND14; - tmp |= value << CAN_NDAT1_ND14_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND15; - tmp |= value << CAN_NDAT1_ND15_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND16; - tmp |= value << CAN_NDAT1_ND16_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND17; - tmp |= value << CAN_NDAT1_ND17_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND18; - tmp |= value << CAN_NDAT1_ND18_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND19; - tmp |= value << CAN_NDAT1_ND19_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND20; - tmp |= value << CAN_NDAT1_ND20_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND21; - tmp |= value << CAN_NDAT1_ND21_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND22; - tmp |= value << CAN_NDAT1_ND22_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND23; - tmp |= value << CAN_NDAT1_ND23_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND24; - tmp |= value << CAN_NDAT1_ND24_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND25; - tmp |= value << CAN_NDAT1_ND25_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND26; - tmp |= value << CAN_NDAT1_ND26_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND27; - tmp |= value << CAN_NDAT1_ND27_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND28; - tmp |= value << CAN_NDAT1_ND28_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND29; - tmp |= value << CAN_NDAT1_ND29_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND30; - tmp |= value << CAN_NDAT1_ND30_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= ~CAN_NDAT1_ND31; - tmp |= value << CAN_NDAT1_ND31_Pos; - ((Can *)hw)->NDAT1.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT1.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) -{ - return ((Can *)hw)->NDAT1.reg; -} - -static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND32; - tmp |= value << CAN_NDAT2_ND32_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND33; - tmp |= value << CAN_NDAT2_ND33_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND34; - tmp |= value << CAN_NDAT2_ND34_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND35; - tmp |= value << CAN_NDAT2_ND35_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND36; - tmp |= value << CAN_NDAT2_ND36_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND37; - tmp |= value << CAN_NDAT2_ND37_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND38; - tmp |= value << CAN_NDAT2_ND38_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND39; - tmp |= value << CAN_NDAT2_ND39_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND40; - tmp |= value << CAN_NDAT2_ND40_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND41; - tmp |= value << CAN_NDAT2_ND41_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND42; - tmp |= value << CAN_NDAT2_ND42_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND43; - tmp |= value << CAN_NDAT2_ND43_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND44; - tmp |= value << CAN_NDAT2_ND44_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND45; - tmp |= value << CAN_NDAT2_ND45_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND46; - tmp |= value << CAN_NDAT2_ND46_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND47; - tmp |= value << CAN_NDAT2_ND47_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND48; - tmp |= value << CAN_NDAT2_ND48_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND49; - tmp |= value << CAN_NDAT2_ND49_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND50; - tmp |= value << CAN_NDAT2_ND50_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND51; - tmp |= value << CAN_NDAT2_ND51_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND52; - tmp |= value << CAN_NDAT2_ND52_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND53; - tmp |= value << CAN_NDAT2_ND53_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND54; - tmp |= value << CAN_NDAT2_ND54_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND55; - tmp |= value << CAN_NDAT2_ND55_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND56; - tmp |= value << CAN_NDAT2_ND56_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND57; - tmp |= value << CAN_NDAT2_ND57_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND58; - tmp |= value << CAN_NDAT2_ND58_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND59; - tmp |= value << CAN_NDAT2_ND59_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND60; - tmp |= value << CAN_NDAT2_ND60_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND61; - tmp |= value << CAN_NDAT2_ND61_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND62; - tmp |= value << CAN_NDAT2_ND62_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= ~CAN_NDAT2_ND63; - tmp |= value << CAN_NDAT2_ND63_Pos; - ((Can *)hw)->NDAT2.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->NDAT2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->NDAT2.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) -{ - return ((Can *)hw)->NDAT2.reg; -} - -static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0OM; - tmp |= value << CAN_RXF0C_F0OM_Pos; - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0SA_Msk; - tmp |= CAN_RXF0C_F0SA(data); - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0S_Msk; - tmp |= CAN_RXF0C_F0S(data); - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= ~CAN_RXF0C_F0WM_Msk; - tmp |= CAN_RXF0C_F0WM(data); - ((Can *)hw)->RXF0C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0C.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0C.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) -{ - return ((Can *)hw)->RXF0C.reg; -} - -static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0A.reg; - tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; - return tmp; -} - -static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF0A.reg; - tmp &= ~CAN_RXF0A_F0AI_Msk; - tmp |= CAN_RXF0A_F0AI(data); - ((Can *)hw)->RXF0A.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0A.reg; - tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; - return tmp; -} - -static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF0A.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF0A.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) -{ - return ((Can *)hw)->RXF0A.reg; -} - -static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXBC.reg; - tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; - return tmp; -} - -static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXBC.reg; - tmp &= ~CAN_RXBC_RBSA_Msk; - tmp |= CAN_RXBC_RBSA(data); - ((Can *)hw)->RXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXBC.reg; - tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; - return tmp; -} - -static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXBC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXBC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) -{ - return ((Can *)hw)->RXBC.reg; -} - -static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1OM; - tmp |= value << CAN_RXF1C_F1OM_Pos; - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1SA_Msk; - tmp |= CAN_RXF1C_F1SA(data); - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1S_Msk; - tmp |= CAN_RXF1C_F1S(data); - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= ~CAN_RXF1C_F1WM_Msk; - tmp |= CAN_RXF1C_F1WM(data); - ((Can *)hw)->RXF1C.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1C.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1C.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) -{ - return ((Can *)hw)->RXF1C.reg; -} - -static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1A.reg; - tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; - return tmp; -} - -static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXF1A.reg; - tmp &= ~CAN_RXF1A_F1AI_Msk; - tmp |= CAN_RXF1A_F1AI(data); - ((Can *)hw)->RXF1A.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1A.reg; - tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; - return tmp; -} - -static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXF1A.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXF1A.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) -{ - return ((Can *)hw)->RXF1A.reg; -} - -static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; - return tmp; -} - -static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXESC.reg; - tmp &= ~CAN_RXESC_F0DS_Msk; - tmp |= CAN_RXESC_F0DS(data); - ((Can *)hw)->RXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; - return tmp; -} - -static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; - return tmp; -} - -static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXESC.reg; - tmp &= ~CAN_RXESC_F1DS_Msk; - tmp |= CAN_RXESC_F1DS(data); - ((Can *)hw)->RXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; - return tmp; -} - -static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; - return tmp; -} - -static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->RXESC.reg; - tmp &= ~CAN_RXESC_RBDS_Msk; - tmp |= CAN_RXESC_RBDS(data); - ((Can *)hw)->RXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; - return tmp; -} - -static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->RXESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->RXESC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) -{ - return ((Can *)hw)->RXESC.reg; -} - -static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_TFQM; - tmp |= value << CAN_TXBC_TFQM_Pos; - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; - return tmp; -} - -static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_TBSA_Msk; - tmp |= CAN_TXBC_TBSA(data); - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; - return tmp; -} - -static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; - return tmp; -} - -static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_NDTB_Msk; - tmp |= CAN_TXBC_NDTB(data); - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; - return tmp; -} - -static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; - return tmp; -} - -static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBC.reg; - tmp &= ~CAN_TXBC_TFQS_Msk; - tmp |= CAN_TXBC_TFQS(data); - ((Can *)hw)->TXBC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; - return tmp; -} - -static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) -{ - return ((Can *)hw)->TXBC.reg; -} - -static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXESC.reg; - tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; - return tmp; -} - -static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXESC.reg; - tmp &= ~CAN_TXESC_TBDS_Msk; - tmp |= CAN_TXESC_TBDS(data); - ((Can *)hw)->TXESC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXESC.reg; - tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; - return tmp; -} - -static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXESC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) -{ - return ((Can *)hw)->TXESC.reg; -} - -static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR0; - tmp |= value << CAN_TXBAR_AR0_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR1; - tmp |= value << CAN_TXBAR_AR1_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR2; - tmp |= value << CAN_TXBAR_AR2_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR3; - tmp |= value << CAN_TXBAR_AR3_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR4; - tmp |= value << CAN_TXBAR_AR4_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR5; - tmp |= value << CAN_TXBAR_AR5_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR6; - tmp |= value << CAN_TXBAR_AR6_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR7; - tmp |= value << CAN_TXBAR_AR7_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR8; - tmp |= value << CAN_TXBAR_AR8_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR9; - tmp |= value << CAN_TXBAR_AR9_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR10; - tmp |= value << CAN_TXBAR_AR10_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR11; - tmp |= value << CAN_TXBAR_AR11_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR12; - tmp |= value << CAN_TXBAR_AR12_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR13; - tmp |= value << CAN_TXBAR_AR13_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR14; - tmp |= value << CAN_TXBAR_AR14_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR15; - tmp |= value << CAN_TXBAR_AR15_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR16; - tmp |= value << CAN_TXBAR_AR16_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR17; - tmp |= value << CAN_TXBAR_AR17_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR18; - tmp |= value << CAN_TXBAR_AR18_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR19; - tmp |= value << CAN_TXBAR_AR19_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR20; - tmp |= value << CAN_TXBAR_AR20_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR21; - tmp |= value << CAN_TXBAR_AR21_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR22; - tmp |= value << CAN_TXBAR_AR22_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR23; - tmp |= value << CAN_TXBAR_AR23_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR24; - tmp |= value << CAN_TXBAR_AR24_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR25; - tmp |= value << CAN_TXBAR_AR25_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR26; - tmp |= value << CAN_TXBAR_AR26_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR27; - tmp |= value << CAN_TXBAR_AR27_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR28; - tmp |= value << CAN_TXBAR_AR28_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR29; - tmp |= value << CAN_TXBAR_AR29_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR30; - tmp |= value << CAN_TXBAR_AR30_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= ~CAN_TXBAR_AR31; - tmp |= value << CAN_TXBAR_AR31_Pos; - ((Can *)hw)->TXBAR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBAR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBAR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) -{ - return ((Can *)hw)->TXBAR.reg; -} - -static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR0; - tmp |= value << CAN_TXBCR_CR0_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR1; - tmp |= value << CAN_TXBCR_CR1_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR2; - tmp |= value << CAN_TXBCR_CR2_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR3; - tmp |= value << CAN_TXBCR_CR3_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR4; - tmp |= value << CAN_TXBCR_CR4_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR5; - tmp |= value << CAN_TXBCR_CR5_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR6; - tmp |= value << CAN_TXBCR_CR6_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR7; - tmp |= value << CAN_TXBCR_CR7_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR8; - tmp |= value << CAN_TXBCR_CR8_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR9; - tmp |= value << CAN_TXBCR_CR9_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR10; - tmp |= value << CAN_TXBCR_CR10_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR11; - tmp |= value << CAN_TXBCR_CR11_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR12; - tmp |= value << CAN_TXBCR_CR12_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR13; - tmp |= value << CAN_TXBCR_CR13_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR14; - tmp |= value << CAN_TXBCR_CR14_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR15; - tmp |= value << CAN_TXBCR_CR15_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR16; - tmp |= value << CAN_TXBCR_CR16_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR17; - tmp |= value << CAN_TXBCR_CR17_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR18; - tmp |= value << CAN_TXBCR_CR18_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR19; - tmp |= value << CAN_TXBCR_CR19_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR20; - tmp |= value << CAN_TXBCR_CR20_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR21; - tmp |= value << CAN_TXBCR_CR21_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR22; - tmp |= value << CAN_TXBCR_CR22_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR23; - tmp |= value << CAN_TXBCR_CR23_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR24; - tmp |= value << CAN_TXBCR_CR24_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR25; - tmp |= value << CAN_TXBCR_CR25_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR26; - tmp |= value << CAN_TXBCR_CR26_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR27; - tmp |= value << CAN_TXBCR_CR27_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR28; - tmp |= value << CAN_TXBCR_CR28_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR29; - tmp |= value << CAN_TXBCR_CR29_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR30; - tmp |= value << CAN_TXBCR_CR30_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= ~CAN_TXBCR_CR31; - tmp |= value << CAN_TXBCR_CR31_Pos; - ((Can *)hw)->TXBCR.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCR.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) -{ - return ((Can *)hw)->TXBCR.reg; -} - -static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE0; - tmp |= value << CAN_TXBTIE_TIE0_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE1; - tmp |= value << CAN_TXBTIE_TIE1_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE2; - tmp |= value << CAN_TXBTIE_TIE2_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE3; - tmp |= value << CAN_TXBTIE_TIE3_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE4; - tmp |= value << CAN_TXBTIE_TIE4_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE5; - tmp |= value << CAN_TXBTIE_TIE5_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE6; - tmp |= value << CAN_TXBTIE_TIE6_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE7; - tmp |= value << CAN_TXBTIE_TIE7_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE8; - tmp |= value << CAN_TXBTIE_TIE8_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE9; - tmp |= value << CAN_TXBTIE_TIE9_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE10; - tmp |= value << CAN_TXBTIE_TIE10_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE11; - tmp |= value << CAN_TXBTIE_TIE11_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE12; - tmp |= value << CAN_TXBTIE_TIE12_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE13; - tmp |= value << CAN_TXBTIE_TIE13_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE14; - tmp |= value << CAN_TXBTIE_TIE14_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE15; - tmp |= value << CAN_TXBTIE_TIE15_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE16; - tmp |= value << CAN_TXBTIE_TIE16_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE17; - tmp |= value << CAN_TXBTIE_TIE17_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE18; - tmp |= value << CAN_TXBTIE_TIE18_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE19; - tmp |= value << CAN_TXBTIE_TIE19_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE20; - tmp |= value << CAN_TXBTIE_TIE20_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE21; - tmp |= value << CAN_TXBTIE_TIE21_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE22; - tmp |= value << CAN_TXBTIE_TIE22_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE23; - tmp |= value << CAN_TXBTIE_TIE23_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE24; - tmp |= value << CAN_TXBTIE_TIE24_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE25; - tmp |= value << CAN_TXBTIE_TIE25_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE26; - tmp |= value << CAN_TXBTIE_TIE26_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE27; - tmp |= value << CAN_TXBTIE_TIE27_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE28; - tmp |= value << CAN_TXBTIE_TIE28_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE29; - tmp |= value << CAN_TXBTIE_TIE29_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE30; - tmp |= value << CAN_TXBTIE_TIE30_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= ~CAN_TXBTIE_TIE31; - tmp |= value << CAN_TXBTIE_TIE31_Pos; - ((Can *)hw)->TXBTIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBTIE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBTIE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) -{ - return ((Can *)hw)->TXBTIE.reg; -} - -static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE0; - tmp |= value << CAN_TXBCIE_CFIE0_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE1; - tmp |= value << CAN_TXBCIE_CFIE1_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE2; - tmp |= value << CAN_TXBCIE_CFIE2_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE3; - tmp |= value << CAN_TXBCIE_CFIE3_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE4; - tmp |= value << CAN_TXBCIE_CFIE4_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE5; - tmp |= value << CAN_TXBCIE_CFIE5_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE6; - tmp |= value << CAN_TXBCIE_CFIE6_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE7; - tmp |= value << CAN_TXBCIE_CFIE7_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE8; - tmp |= value << CAN_TXBCIE_CFIE8_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE9; - tmp |= value << CAN_TXBCIE_CFIE9_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE10; - tmp |= value << CAN_TXBCIE_CFIE10_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE11; - tmp |= value << CAN_TXBCIE_CFIE11_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE12; - tmp |= value << CAN_TXBCIE_CFIE12_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE13; - tmp |= value << CAN_TXBCIE_CFIE13_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE14; - tmp |= value << CAN_TXBCIE_CFIE14_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE15; - tmp |= value << CAN_TXBCIE_CFIE15_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE16; - tmp |= value << CAN_TXBCIE_CFIE16_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE17; - tmp |= value << CAN_TXBCIE_CFIE17_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE18; - tmp |= value << CAN_TXBCIE_CFIE18_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE19; - tmp |= value << CAN_TXBCIE_CFIE19_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE20; - tmp |= value << CAN_TXBCIE_CFIE20_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE21; - tmp |= value << CAN_TXBCIE_CFIE21_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE22; - tmp |= value << CAN_TXBCIE_CFIE22_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE23; - tmp |= value << CAN_TXBCIE_CFIE23_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE24; - tmp |= value << CAN_TXBCIE_CFIE24_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE25; - tmp |= value << CAN_TXBCIE_CFIE25_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE26; - tmp |= value << CAN_TXBCIE_CFIE26_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE27; - tmp |= value << CAN_TXBCIE_CFIE27_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE28; - tmp |= value << CAN_TXBCIE_CFIE28_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE29; - tmp |= value << CAN_TXBCIE_CFIE29_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE30; - tmp |= value << CAN_TXBCIE_CFIE30_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; - return (bool)tmp; -} - -static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= ~CAN_TXBCIE_CFIE31; - tmp |= value << CAN_TXBCIE_CFIE31_Pos; - ((Can *)hw)->TXBCIE.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXBCIE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXBCIE.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) -{ - return ((Can *)hw)->TXBCIE.reg; -} - -static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= ~CAN_TXEFC_EFSA_Msk; - tmp |= CAN_TXEFC_EFSA(data); - ((Can *)hw)->TXEFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= ~CAN_TXEFC_EFS_Msk; - tmp |= CAN_TXEFC_EFS(data); - ((Can *)hw)->TXEFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= ~CAN_TXEFC_EFWM_Msk; - tmp |= CAN_TXEFC_EFWM(data); - ((Can *)hw)->TXEFC.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFC.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) -{ - return ((Can *)hw)->TXEFC.reg; -} - -static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFA.reg; - tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; - return tmp; -} - -static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) -{ - uint32_t tmp; - CAN_CRITICAL_SECTION_ENTER(); - tmp = ((Can *)hw)->TXEFA.reg; - tmp &= ~CAN_TXEFA_EFAI_Msk; - tmp |= CAN_TXEFA_EFAI(data); - ((Can *)hw)->TXEFA.reg = tmp; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFA.reg; - tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; - return tmp; -} - -static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg |= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Can *)hw)->TXEFA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg = data; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg &= ~mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) -{ - CAN_CRITICAL_SECTION_ENTER(); - ((Can *)hw)->TXEFA.reg ^= mask; - CAN_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) -{ - return ((Can *)hw)->TXEFA.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CAN_E54_H_INCLUDED */ -#endif /* _SAME54_CAN_COMPONENT_ */ +/** + * \file + * + * \brief SAM CAN + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CAN_COMPONENT_ +#ifndef _HRI_CAN_E54_H_INCLUDED_ +#define _HRI_CAN_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CAN_CRITICAL_SECTIONS) +#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CAN_CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_can_cccr_reg_t; +typedef uint32_t hri_can_crel_reg_t; +typedef uint32_t hri_can_dbtp_reg_t; +typedef uint32_t hri_can_ecr_reg_t; +typedef uint32_t hri_can_endn_reg_t; +typedef uint32_t hri_can_gfc_reg_t; +typedef uint32_t hri_can_hpms_reg_t; +typedef uint32_t hri_can_ie_reg_t; +typedef uint32_t hri_can_ile_reg_t; +typedef uint32_t hri_can_ils_reg_t; +typedef uint32_t hri_can_ir_reg_t; +typedef uint32_t hri_can_mrcfg_reg_t; +typedef uint32_t hri_can_nbtp_reg_t; +typedef uint32_t hri_can_ndat1_reg_t; +typedef uint32_t hri_can_ndat2_reg_t; +typedef uint32_t hri_can_psr_reg_t; +typedef uint32_t hri_can_rwd_reg_t; +typedef uint32_t hri_can_rxbc_reg_t; +typedef uint32_t hri_can_rxesc_reg_t; +typedef uint32_t hri_can_rxf0a_reg_t; +typedef uint32_t hri_can_rxf0c_reg_t; +typedef uint32_t hri_can_rxf0s_reg_t; +typedef uint32_t hri_can_rxf1a_reg_t; +typedef uint32_t hri_can_rxf1c_reg_t; +typedef uint32_t hri_can_rxf1s_reg_t; +typedef uint32_t hri_can_sidfc_reg_t; +typedef uint32_t hri_can_tdcr_reg_t; +typedef uint32_t hri_can_test_reg_t; +typedef uint32_t hri_can_tocc_reg_t; +typedef uint32_t hri_can_tocv_reg_t; +typedef uint32_t hri_can_tscc_reg_t; +typedef uint32_t hri_can_tscv_reg_t; +typedef uint32_t hri_can_txbar_reg_t; +typedef uint32_t hri_can_txbc_reg_t; +typedef uint32_t hri_can_txbcf_reg_t; +typedef uint32_t hri_can_txbcie_reg_t; +typedef uint32_t hri_can_txbcr_reg_t; +typedef uint32_t hri_can_txbrp_reg_t; +typedef uint32_t hri_can_txbtie_reg_t; +typedef uint32_t hri_can_txbto_reg_t; +typedef uint32_t hri_can_txefa_reg_t; +typedef uint32_t hri_can_txefc_reg_t; +typedef uint32_t hri_can_txefs_reg_t; +typedef uint32_t hri_can_txesc_reg_t; +typedef uint32_t hri_can_txfqs_reg_t; +typedef uint32_t hri_can_xidam_reg_t; +typedef uint32_t hri_can_xidfc_reg_t; + +static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CREL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) +{ + return ((Can *)hw)->CREL.reg; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ENDN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) +{ + return ((Can *)hw)->ENDN.reg; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) +{ + return ((Can *)hw)->TSCV.reg; +} + +static inline bool hri_can_get_ECR_RP_bit(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ECR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) +{ + return ((Can *)hw)->ECR.reg; +} + +static inline bool hri_can_get_PSR_EP_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; +} + +static inline bool hri_can_get_PSR_EW_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; +} + +static inline bool hri_can_get_PSR_BO_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; +} + +static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; +} + +static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; +} + +static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; +} + +static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) +{ + return ((Can *)hw)->PSR.reg; +} + +static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->HPMS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) +{ + return ((Can *)hw)->HPMS.reg; +} + +static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; +} + +static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0S.reg; +} + +static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; +} + +static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1S.reg; +} + +static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXFQS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) +{ + return ((Can *)hw)->TXFQS.reg; +} + +static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; +} + +static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBRP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) +{ + return ((Can *)hw)->TXBRP.reg; +} + +static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; +} + +static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; +} + +static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; +} + +static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; +} + +static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; +} + +static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; +} + +static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; +} + +static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; +} + +static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; +} + +static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; +} + +static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; +} + +static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; +} + +static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; +} + +static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; +} + +static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; +} + +static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; +} + +static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; +} + +static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; +} + +static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; +} + +static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; +} + +static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; +} + +static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; +} + +static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; +} + +static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; +} + +static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; +} + +static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; +} + +static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; +} + +static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; +} + +static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; +} + +static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; +} + +static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; +} + +static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; +} + +static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTO.reg; +} + +static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; +} + +static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; +} + +static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; +} + +static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; +} + +static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; +} + +static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; +} + +static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; +} + +static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; +} + +static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; +} + +static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; +} + +static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; +} + +static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; +} + +static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; +} + +static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; +} + +static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; +} + +static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; +} + +static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; +} + +static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; +} + +static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; +} + +static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; +} + +static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; +} + +static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; +} + +static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; +} + +static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; +} + +static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; +} + +static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; +} + +static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; +} + +static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; +} + +static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; +} + +static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; +} + +static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; +} + +static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; +} + +static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCF.reg; +} + +static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; +} + +static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFS.reg; +} + +static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= ~CAN_MRCFG_QOS_Msk; + tmp |= CAN_MRCFG_QOS(data); + ((Can *)hw)->MRCFG.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) +{ + return ((Can *)hw)->MRCFG.reg; +} + +static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_TDC; + tmp |= value << CAN_DBTP_TDC_Pos; + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DSJW_Msk; + tmp |= CAN_DBTP_DSJW(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG2_Msk; + tmp |= CAN_DBTP_DTSEG2(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG1_Msk; + tmp |= CAN_DBTP_DTSEG1(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DBRP_Msk; + tmp |= CAN_DBTP_DBRP(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) +{ + return ((Can *)hw)->DBTP.reg; +} + +static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_LBCK; + tmp |= value << CAN_TEST_LBCK_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_RX; + tmp |= value << CAN_TEST_RX_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_TX_Msk; + tmp |= CAN_TEST_TX(data); + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) +{ + return ((Can *)hw)->TEST.reg; +} + +static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDC_Msk; + tmp |= CAN_RWD_WDC(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDV_Msk; + tmp |= CAN_RWD_WDV(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) +{ + return ((Can *)hw)->RWD.reg; +} + +static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_INIT; + tmp |= value << CAN_CCCR_INIT_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CCE; + tmp |= value << CAN_CCCR_CCE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_ASM; + tmp |= value << CAN_CCCR_ASM_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSA; + tmp |= value << CAN_CCCR_CSA_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSR; + tmp |= value << CAN_CCCR_CSR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_MON; + tmp |= value << CAN_CCCR_MON_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_DAR; + tmp |= value << CAN_CCCR_DAR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TEST; + tmp |= value << CAN_CCCR_TEST_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_FDOE; + tmp |= value << CAN_CCCR_FDOE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_BRSE; + tmp |= value << CAN_CCCR_BRSE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_PXHD; + tmp |= value << CAN_CCCR_PXHD_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_EFBI; + tmp |= value << CAN_CCCR_EFBI_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TXP; + tmp |= value << CAN_CCCR_TXP_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_NISO; + tmp |= value << CAN_CCCR_NISO_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) +{ + return ((Can *)hw)->CCCR.reg; +} + +static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG2_Msk; + tmp |= CAN_NBTP_NTSEG2(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG1_Msk; + tmp |= CAN_NBTP_NTSEG1(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NBRP_Msk; + tmp |= CAN_NBTP_NBRP(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NSJW_Msk; + tmp |= CAN_NBTP_NSJW(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) +{ + return ((Can *)hw)->NBTP.reg; +} + +static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TSS_Msk; + tmp |= CAN_TSCC_TSS(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TCP_Msk; + tmp |= CAN_TSCC_TCP(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) +{ + return ((Can *)hw)->TSCC.reg; +} + +static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_ETOC; + tmp |= value << CAN_TOCC_ETOC_Pos; + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOS_Msk; + tmp |= CAN_TOCC_TOS(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOP_Msk; + tmp |= CAN_TOCC_TOP(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) +{ + return ((Can *)hw)->TOCC.reg; +} + +static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCV.reg; + tmp &= ~CAN_TOCV_TOC_Msk; + tmp |= CAN_TOCV_TOC(data); + ((Can *)hw)->TOCV.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) +{ + return ((Can *)hw)->TOCV.reg; +} + +static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCF_Msk; + tmp |= CAN_TDCR_TDCF(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCO_Msk; + tmp |= CAN_TDCR_TDCO(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) +{ + return ((Can *)hw)->TDCR.reg; +} + +static inline void hri_can_set_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0N; + tmp |= value << CAN_IR_RF0N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0W; + tmp |= value << CAN_IR_RF0W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0F; + tmp |= value << CAN_IR_RF0F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0L; + tmp |= value << CAN_IR_RF0L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1N; + tmp |= value << CAN_IR_RF1N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1W; + tmp |= value << CAN_IR_RF1W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1F; + tmp |= value << CAN_IR_RF1F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1L; + tmp |= value << CAN_IR_RF1L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_HPM; + tmp |= value << CAN_IR_HPM_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TC; + tmp |= value << CAN_IR_TC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TCF; + tmp |= value << CAN_IR_TCF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TFE; + tmp |= value << CAN_IR_TFE_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFN; + tmp |= value << CAN_IR_TEFN_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFW; + tmp |= value << CAN_IR_TEFW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFF; + tmp |= value << CAN_IR_TEFF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFL; + tmp |= value << CAN_IR_TEFL_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TSW; + tmp |= value << CAN_IR_TSW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_MRAF; + tmp |= value << CAN_IR_MRAF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TOO; + tmp |= value << CAN_IR_TOO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_DRX; + tmp |= value << CAN_IR_DRX_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEC; + tmp |= value << CAN_IR_BEC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEU; + tmp |= value << CAN_IR_BEU_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ELO; + tmp |= value << CAN_IR_ELO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EP; + tmp |= value << CAN_IR_EP_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EW; + tmp |= value << CAN_IR_EW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BO; + tmp |= value << CAN_IR_BO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_WDI; + tmp |= value << CAN_IR_WDI_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PEA; + tmp |= value << CAN_IR_PEA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PED; + tmp |= value << CAN_IR_PED_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ARA; + tmp |= value << CAN_IR_ARA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) +{ + return ((Can *)hw)->IR.reg; +} + +static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0NE; + tmp |= value << CAN_IE_RF0NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0WE; + tmp |= value << CAN_IE_RF0WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0FE; + tmp |= value << CAN_IE_RF0FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0LE; + tmp |= value << CAN_IE_RF0LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1NE; + tmp |= value << CAN_IE_RF1NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1WE; + tmp |= value << CAN_IE_RF1WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1FE; + tmp |= value << CAN_IE_RF1FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1LE; + tmp |= value << CAN_IE_RF1LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_HPME; + tmp |= value << CAN_IE_HPME_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCE; + tmp |= value << CAN_IE_TCE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCFE; + tmp |= value << CAN_IE_TCFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TFEE; + tmp |= value << CAN_IE_TFEE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFNE; + tmp |= value << CAN_IE_TEFNE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFWE; + tmp |= value << CAN_IE_TEFWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFFE; + tmp |= value << CAN_IE_TEFFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFLE; + tmp |= value << CAN_IE_TEFLE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TSWE; + tmp |= value << CAN_IE_TSWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_MRAFE; + tmp |= value << CAN_IE_MRAFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TOOE; + tmp |= value << CAN_IE_TOOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_DRXE; + tmp |= value << CAN_IE_DRXE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BECE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BECE; + tmp |= value << CAN_IE_BECE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BEUE; + tmp |= value << CAN_IE_BEUE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ELOE; + tmp |= value << CAN_IE_ELOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EPE; + tmp |= value << CAN_IE_EPE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EWE; + tmp |= value << CAN_IE_EWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BOE; + tmp |= value << CAN_IE_BOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_WDIE; + tmp |= value << CAN_IE_WDIE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEAE; + tmp |= value << CAN_IE_PEAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEDE; + tmp |= value << CAN_IE_PEDE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ARAE; + tmp |= value << CAN_IE_ARAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) +{ + return ((Can *)hw)->IE.reg; +} + +static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0NL; + tmp |= value << CAN_ILS_RF0NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0WL; + tmp |= value << CAN_ILS_RF0WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0FL; + tmp |= value << CAN_ILS_RF0FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0LL; + tmp |= value << CAN_ILS_RF0LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1NL; + tmp |= value << CAN_ILS_RF1NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1WL; + tmp |= value << CAN_ILS_RF1WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1FL; + tmp |= value << CAN_ILS_RF1FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1LL; + tmp |= value << CAN_ILS_RF1LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_HPML; + tmp |= value << CAN_ILS_HPML_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCL; + tmp |= value << CAN_ILS_TCL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCFL; + tmp |= value << CAN_ILS_TCFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TFEL; + tmp |= value << CAN_ILS_TFEL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFNL; + tmp |= value << CAN_ILS_TEFNL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFWL; + tmp |= value << CAN_ILS_TEFWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFFL; + tmp |= value << CAN_ILS_TEFFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFLL; + tmp |= value << CAN_ILS_TEFLL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TSWL; + tmp |= value << CAN_ILS_TSWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_MRAFL; + tmp |= value << CAN_ILS_MRAFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TOOL; + tmp |= value << CAN_ILS_TOOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_DRXL; + tmp |= value << CAN_ILS_DRXL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BECL; + tmp |= value << CAN_ILS_BECL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BEUL; + tmp |= value << CAN_ILS_BEUL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ELOL; + tmp |= value << CAN_ILS_ELOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EPL; + tmp |= value << CAN_ILS_EPL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EWL; + tmp |= value << CAN_ILS_EWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BOL; + tmp |= value << CAN_ILS_BOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_WDIL; + tmp |= value << CAN_ILS_WDIL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEAL; + tmp |= value << CAN_ILS_PEAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEDL; + tmp |= value << CAN_ILS_PEDL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ARAL; + tmp |= value << CAN_ILS_ARAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) +{ + return ((Can *)hw)->ILS.reg; +} + +static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT0; + tmp |= value << CAN_ILE_EINT0_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT1; + tmp |= value << CAN_ILE_EINT1_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) +{ + return ((Can *)hw)->ILE.reg; +} + +static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFE; + tmp |= value << CAN_GFC_RRFE_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFS; + tmp |= value << CAN_GFC_RRFS_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFE_Msk; + tmp |= CAN_GFC_ANFE(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFS_Msk; + tmp |= CAN_GFC_ANFS(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) +{ + return ((Can *)hw)->GFC.reg; +} + +static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_FLSSA_Msk; + tmp |= CAN_SIDFC_FLSSA(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_LSS_Msk; + tmp |= CAN_SIDFC_LSS(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->SIDFC.reg; +} + +static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_FLESA_Msk; + tmp |= CAN_XIDFC_FLESA(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_LSE_Msk; + tmp |= CAN_XIDFC_LSE(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->XIDFC.reg; +} + +static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= ~CAN_XIDAM_EIDM_Msk; + tmp |= CAN_XIDAM_EIDM(data); + ((Can *)hw)->XIDAM.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) +{ + return ((Can *)hw)->XIDAM.reg; +} + +static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND0; + tmp |= value << CAN_NDAT1_ND0_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND1; + tmp |= value << CAN_NDAT1_ND1_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND2; + tmp |= value << CAN_NDAT1_ND2_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND3; + tmp |= value << CAN_NDAT1_ND3_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND4; + tmp |= value << CAN_NDAT1_ND4_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND5; + tmp |= value << CAN_NDAT1_ND5_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND6; + tmp |= value << CAN_NDAT1_ND6_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND7; + tmp |= value << CAN_NDAT1_ND7_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND8; + tmp |= value << CAN_NDAT1_ND8_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND9; + tmp |= value << CAN_NDAT1_ND9_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND10; + tmp |= value << CAN_NDAT1_ND10_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND11; + tmp |= value << CAN_NDAT1_ND11_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND12; + tmp |= value << CAN_NDAT1_ND12_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND13; + tmp |= value << CAN_NDAT1_ND13_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND14; + tmp |= value << CAN_NDAT1_ND14_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND15; + tmp |= value << CAN_NDAT1_ND15_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND16; + tmp |= value << CAN_NDAT1_ND16_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND17; + tmp |= value << CAN_NDAT1_ND17_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND18; + tmp |= value << CAN_NDAT1_ND18_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND19; + tmp |= value << CAN_NDAT1_ND19_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND20; + tmp |= value << CAN_NDAT1_ND20_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND21; + tmp |= value << CAN_NDAT1_ND21_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND22; + tmp |= value << CAN_NDAT1_ND22_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND23; + tmp |= value << CAN_NDAT1_ND23_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND24; + tmp |= value << CAN_NDAT1_ND24_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND25; + tmp |= value << CAN_NDAT1_ND25_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND26; + tmp |= value << CAN_NDAT1_ND26_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND27; + tmp |= value << CAN_NDAT1_ND27_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND28; + tmp |= value << CAN_NDAT1_ND28_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND29; + tmp |= value << CAN_NDAT1_ND29_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND30; + tmp |= value << CAN_NDAT1_ND30_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND31; + tmp |= value << CAN_NDAT1_ND31_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT1.reg; +} + +static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND32; + tmp |= value << CAN_NDAT2_ND32_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND33; + tmp |= value << CAN_NDAT2_ND33_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND34; + tmp |= value << CAN_NDAT2_ND34_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND35; + tmp |= value << CAN_NDAT2_ND35_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND36; + tmp |= value << CAN_NDAT2_ND36_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND37; + tmp |= value << CAN_NDAT2_ND37_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND38; + tmp |= value << CAN_NDAT2_ND38_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND39; + tmp |= value << CAN_NDAT2_ND39_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND40; + tmp |= value << CAN_NDAT2_ND40_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND41; + tmp |= value << CAN_NDAT2_ND41_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND42; + tmp |= value << CAN_NDAT2_ND42_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND43; + tmp |= value << CAN_NDAT2_ND43_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND44; + tmp |= value << CAN_NDAT2_ND44_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND45; + tmp |= value << CAN_NDAT2_ND45_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND46; + tmp |= value << CAN_NDAT2_ND46_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND47; + tmp |= value << CAN_NDAT2_ND47_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND48; + tmp |= value << CAN_NDAT2_ND48_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND49; + tmp |= value << CAN_NDAT2_ND49_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND50; + tmp |= value << CAN_NDAT2_ND50_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND51; + tmp |= value << CAN_NDAT2_ND51_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND52; + tmp |= value << CAN_NDAT2_ND52_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND53; + tmp |= value << CAN_NDAT2_ND53_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND54; + tmp |= value << CAN_NDAT2_ND54_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND55; + tmp |= value << CAN_NDAT2_ND55_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND56; + tmp |= value << CAN_NDAT2_ND56_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND57; + tmp |= value << CAN_NDAT2_ND57_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND58; + tmp |= value << CAN_NDAT2_ND58_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND59; + tmp |= value << CAN_NDAT2_ND59_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND60; + tmp |= value << CAN_NDAT2_ND60_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND61; + tmp |= value << CAN_NDAT2_ND61_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND62; + tmp |= value << CAN_NDAT2_ND62_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND63; + tmp |= value << CAN_NDAT2_ND63_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT2.reg; +} + +static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0OM; + tmp |= value << CAN_RXF0C_F0OM_Pos; + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0SA_Msk; + tmp |= CAN_RXF0C_F0SA(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0S_Msk; + tmp |= CAN_RXF0C_F0S(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0WM_Msk; + tmp |= CAN_RXF0C_F0WM(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0C.reg; +} + +static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= ~CAN_RXF0A_F0AI_Msk; + tmp |= CAN_RXF0A_F0AI(data); + ((Can *)hw)->RXF0A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0A.reg; +} + +static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXBC.reg; + tmp &= ~CAN_RXBC_RBSA_Msk; + tmp |= CAN_RXBC_RBSA(data); + ((Can *)hw)->RXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) +{ + return ((Can *)hw)->RXBC.reg; +} + +static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1OM; + tmp |= value << CAN_RXF1C_F1OM_Pos; + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1SA_Msk; + tmp |= CAN_RXF1C_F1SA(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1S_Msk; + tmp |= CAN_RXF1C_F1S(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1WM_Msk; + tmp |= CAN_RXF1C_F1WM(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1C.reg; +} + +static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= ~CAN_RXF1A_F1AI_Msk; + tmp |= CAN_RXF1A_F1AI(data); + ((Can *)hw)->RXF1A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1A.reg; +} + +static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F0DS_Msk; + tmp |= CAN_RXESC_F0DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F1DS_Msk; + tmp |= CAN_RXESC_F1DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_RBDS_Msk; + tmp |= CAN_RXESC_RBDS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) +{ + return ((Can *)hw)->RXESC.reg; +} + +static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQM; + tmp |= value << CAN_TXBC_TFQM_Pos; + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TBSA_Msk; + tmp |= CAN_TXBC_TBSA(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_NDTB_Msk; + tmp |= CAN_TXBC_NDTB(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQS_Msk; + tmp |= CAN_TXBC_TFQS(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) +{ + return ((Can *)hw)->TXBC.reg; +} + +static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXESC.reg; + tmp &= ~CAN_TXESC_TBDS_Msk; + tmp |= CAN_TXESC_TBDS(data); + ((Can *)hw)->TXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) +{ + return ((Can *)hw)->TXESC.reg; +} + +static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR0; + tmp |= value << CAN_TXBAR_AR0_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR1; + tmp |= value << CAN_TXBAR_AR1_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR2; + tmp |= value << CAN_TXBAR_AR2_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR3; + tmp |= value << CAN_TXBAR_AR3_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR4; + tmp |= value << CAN_TXBAR_AR4_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR5; + tmp |= value << CAN_TXBAR_AR5_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR6; + tmp |= value << CAN_TXBAR_AR6_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR7; + tmp |= value << CAN_TXBAR_AR7_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR8; + tmp |= value << CAN_TXBAR_AR8_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR9; + tmp |= value << CAN_TXBAR_AR9_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR10; + tmp |= value << CAN_TXBAR_AR10_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR11; + tmp |= value << CAN_TXBAR_AR11_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR12; + tmp |= value << CAN_TXBAR_AR12_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR13; + tmp |= value << CAN_TXBAR_AR13_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR14; + tmp |= value << CAN_TXBAR_AR14_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR15; + tmp |= value << CAN_TXBAR_AR15_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR16; + tmp |= value << CAN_TXBAR_AR16_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR17; + tmp |= value << CAN_TXBAR_AR17_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR18; + tmp |= value << CAN_TXBAR_AR18_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR19; + tmp |= value << CAN_TXBAR_AR19_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR20; + tmp |= value << CAN_TXBAR_AR20_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR21; + tmp |= value << CAN_TXBAR_AR21_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR22; + tmp |= value << CAN_TXBAR_AR22_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR23; + tmp |= value << CAN_TXBAR_AR23_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR24; + tmp |= value << CAN_TXBAR_AR24_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR25; + tmp |= value << CAN_TXBAR_AR25_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR26; + tmp |= value << CAN_TXBAR_AR26_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR27; + tmp |= value << CAN_TXBAR_AR27_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR28; + tmp |= value << CAN_TXBAR_AR28_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR29; + tmp |= value << CAN_TXBAR_AR29_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR30; + tmp |= value << CAN_TXBAR_AR30_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR31; + tmp |= value << CAN_TXBAR_AR31_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBAR.reg; +} + +static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR0; + tmp |= value << CAN_TXBCR_CR0_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR1; + tmp |= value << CAN_TXBCR_CR1_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR2; + tmp |= value << CAN_TXBCR_CR2_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR3; + tmp |= value << CAN_TXBCR_CR3_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR4; + tmp |= value << CAN_TXBCR_CR4_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR5; + tmp |= value << CAN_TXBCR_CR5_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR6; + tmp |= value << CAN_TXBCR_CR6_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR7; + tmp |= value << CAN_TXBCR_CR7_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR8; + tmp |= value << CAN_TXBCR_CR8_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR9; + tmp |= value << CAN_TXBCR_CR9_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR10; + tmp |= value << CAN_TXBCR_CR10_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR11; + tmp |= value << CAN_TXBCR_CR11_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR12; + tmp |= value << CAN_TXBCR_CR12_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR13; + tmp |= value << CAN_TXBCR_CR13_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR14; + tmp |= value << CAN_TXBCR_CR14_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR15; + tmp |= value << CAN_TXBCR_CR15_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR16; + tmp |= value << CAN_TXBCR_CR16_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR17; + tmp |= value << CAN_TXBCR_CR17_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR18; + tmp |= value << CAN_TXBCR_CR18_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR19; + tmp |= value << CAN_TXBCR_CR19_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR20; + tmp |= value << CAN_TXBCR_CR20_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR21; + tmp |= value << CAN_TXBCR_CR21_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR22; + tmp |= value << CAN_TXBCR_CR22_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR23; + tmp |= value << CAN_TXBCR_CR23_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR24; + tmp |= value << CAN_TXBCR_CR24_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR25; + tmp |= value << CAN_TXBCR_CR25_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR26; + tmp |= value << CAN_TXBCR_CR26_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR27; + tmp |= value << CAN_TXBCR_CR27_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR28; + tmp |= value << CAN_TXBCR_CR28_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR29; + tmp |= value << CAN_TXBCR_CR29_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR30; + tmp |= value << CAN_TXBCR_CR30_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR31; + tmp |= value << CAN_TXBCR_CR31_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCR.reg; +} + +static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE0; + tmp |= value << CAN_TXBTIE_TIE0_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE1; + tmp |= value << CAN_TXBTIE_TIE1_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE2; + tmp |= value << CAN_TXBTIE_TIE2_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE3; + tmp |= value << CAN_TXBTIE_TIE3_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE4; + tmp |= value << CAN_TXBTIE_TIE4_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE5; + tmp |= value << CAN_TXBTIE_TIE5_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE6; + tmp |= value << CAN_TXBTIE_TIE6_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE7; + tmp |= value << CAN_TXBTIE_TIE7_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE8; + tmp |= value << CAN_TXBTIE_TIE8_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE9; + tmp |= value << CAN_TXBTIE_TIE9_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE10; + tmp |= value << CAN_TXBTIE_TIE10_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE11; + tmp |= value << CAN_TXBTIE_TIE11_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE12; + tmp |= value << CAN_TXBTIE_TIE12_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE13; + tmp |= value << CAN_TXBTIE_TIE13_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE14; + tmp |= value << CAN_TXBTIE_TIE14_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE15; + tmp |= value << CAN_TXBTIE_TIE15_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE16; + tmp |= value << CAN_TXBTIE_TIE16_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE17; + tmp |= value << CAN_TXBTIE_TIE17_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE18; + tmp |= value << CAN_TXBTIE_TIE18_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE19; + tmp |= value << CAN_TXBTIE_TIE19_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE20; + tmp |= value << CAN_TXBTIE_TIE20_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE21; + tmp |= value << CAN_TXBTIE_TIE21_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE22; + tmp |= value << CAN_TXBTIE_TIE22_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE23; + tmp |= value << CAN_TXBTIE_TIE23_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE24; + tmp |= value << CAN_TXBTIE_TIE24_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE25; + tmp |= value << CAN_TXBTIE_TIE25_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE26; + tmp |= value << CAN_TXBTIE_TIE26_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE27; + tmp |= value << CAN_TXBTIE_TIE27_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE28; + tmp |= value << CAN_TXBTIE_TIE28_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE29; + tmp |= value << CAN_TXBTIE_TIE29_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE30; + tmp |= value << CAN_TXBTIE_TIE30_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE31; + tmp |= value << CAN_TXBTIE_TIE31_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTIE.reg; +} + +static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE0; + tmp |= value << CAN_TXBCIE_CFIE0_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE1; + tmp |= value << CAN_TXBCIE_CFIE1_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE2; + tmp |= value << CAN_TXBCIE_CFIE2_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE3; + tmp |= value << CAN_TXBCIE_CFIE3_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE4; + tmp |= value << CAN_TXBCIE_CFIE4_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE5; + tmp |= value << CAN_TXBCIE_CFIE5_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE6; + tmp |= value << CAN_TXBCIE_CFIE6_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE7; + tmp |= value << CAN_TXBCIE_CFIE7_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE8; + tmp |= value << CAN_TXBCIE_CFIE8_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE9; + tmp |= value << CAN_TXBCIE_CFIE9_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE10; + tmp |= value << CAN_TXBCIE_CFIE10_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE11; + tmp |= value << CAN_TXBCIE_CFIE11_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE12; + tmp |= value << CAN_TXBCIE_CFIE12_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE13; + tmp |= value << CAN_TXBCIE_CFIE13_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE14; + tmp |= value << CAN_TXBCIE_CFIE14_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE15; + tmp |= value << CAN_TXBCIE_CFIE15_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE16; + tmp |= value << CAN_TXBCIE_CFIE16_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE17; + tmp |= value << CAN_TXBCIE_CFIE17_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE18; + tmp |= value << CAN_TXBCIE_CFIE18_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE19; + tmp |= value << CAN_TXBCIE_CFIE19_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE20; + tmp |= value << CAN_TXBCIE_CFIE20_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE21; + tmp |= value << CAN_TXBCIE_CFIE21_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE22; + tmp |= value << CAN_TXBCIE_CFIE22_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE23; + tmp |= value << CAN_TXBCIE_CFIE23_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE24; + tmp |= value << CAN_TXBCIE_CFIE24_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE25; + tmp |= value << CAN_TXBCIE_CFIE25_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE26; + tmp |= value << CAN_TXBCIE_CFIE26_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE27; + tmp |= value << CAN_TXBCIE_CFIE27_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE28; + tmp |= value << CAN_TXBCIE_CFIE28_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE29; + tmp |= value << CAN_TXBCIE_CFIE29_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE30; + tmp |= value << CAN_TXBCIE_CFIE30_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE31; + tmp |= value << CAN_TXBCIE_CFIE31_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCIE.reg; +} + +static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFSA_Msk; + tmp |= CAN_TXEFC_EFSA(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFS_Msk; + tmp |= CAN_TXEFC_EFS(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFWM_Msk; + tmp |= CAN_TXEFC_EFWM(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFC.reg; +} + +static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= ~CAN_TXEFA_EFAI_Msk; + tmp |= CAN_TXEFA_EFAI(data); + ((Can *)hw)->TXEFA.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CAN_E54_H_INCLUDED */ +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ccl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ccl_e54.h index c5c4867..6d798fb 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ccl_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ccl_e54.h @@ -1,776 +1,776 @@ -/** - * \file - * - * \brief SAM CCL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_CCL_COMPONENT_ -#ifndef _HRI_CCL_E54_H_INCLUDED_ -#define _HRI_CCL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CCL_CRITICAL_SECTIONS) -#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CCL_CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ccl_lutctrl_reg_t; -typedef uint8_t hri_ccl_ctrl_reg_t; -typedef uint8_t hri_ccl_seqctrl_reg_t; - -static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_ENABLE; - tmp |= value << CCL_CTRL_ENABLE_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_RUNSTDBY; - tmp |= value << CCL_CTRL_RUNSTDBY_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) -{ - return ((Ccl *)hw)->CTRL.reg; -} - -static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; - tmp |= CCL_SEQCTRL_SEQSEL(data); - ((Ccl *)hw)->SEQCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->SEQCTRL[index].reg; -} - -static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_ENABLE; - tmp |= value << CCL_LUTCTRL_ENABLE_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_EDGESEL; - tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INVEI; - tmp |= value << CCL_LUTCTRL_INVEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEI; - tmp |= value << CCL_LUTCTRL_LUTEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEO; - tmp |= value << CCL_LUTCTRL_LUTEO_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; - tmp |= CCL_LUTCTRL_FILTSEL(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL0_Msk; - tmp |= CCL_LUTCTRL_INSEL0(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL1_Msk; - tmp |= CCL_LUTCTRL_INSEL1(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL2_Msk; - tmp |= CCL_LUTCTRL_INSEL2(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_TRUTH_Msk; - tmp |= CCL_LUTCTRL_TRUTH(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->LUTCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CCL_E54_H_INCLUDED */ -#endif /* _SAME54_CCL_COMPONENT_ */ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CCL_COMPONENT_ +#ifndef _HRI_CCL_E54_H_INCLUDED_ +#define _HRI_CCL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_E54_H_INCLUDED */ +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_cmcc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_cmcc_e54.h index c973d35..ec9d693 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_cmcc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_cmcc_e54.h @@ -1,361 +1,361 @@ -/** - * \file - * - * \brief SAM CMCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_CMCC_COMPONENT_ -#ifndef _HRI_CMCC_E54_H_INCLUDED_ -#define _HRI_CMCC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) -#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CMCC_CRITICAL_SECTION_ENTER() -#define CMCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_cmcc_cfg_reg_t; -typedef uint32_t hri_cmcc_ctrl_reg_t; -typedef uint32_t hri_cmcc_lckway_reg_t; -typedef uint32_t hri_cmcc_maint0_reg_t; -typedef uint32_t hri_cmcc_maint1_reg_t; -typedef uint32_t hri_cmcc_mcfg_reg_t; -typedef uint32_t hri_cmcc_mctrl_reg_t; -typedef uint32_t hri_cmcc_men_reg_t; -typedef uint32_t hri_cmcc_msr_reg_t; -typedef uint32_t hri_cmcc_sr_reg_t; -typedef uint32_t hri_cmcc_type_reg_t; - -static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; -} - -static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; -} - -static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->TYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) -{ - return ((Cmcc *)hw)->TYPE.reg; -} - -static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) -{ - return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; -} - -static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->SR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) -{ - return ((Cmcc *)hw)->SR.reg; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) -{ - return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) -{ - return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MSR.reg; -} - -static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) -{ - return ((Cmcc *)hw)->CFG.reg; -} - -static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->LCKWAY.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) -{ - return ((Cmcc *)hw)->LCKWAY.reg; -} - -static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MCFG.reg; -} - -static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MEN.reg; -} - -static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CTRL.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MAINT0.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MAINT1.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCTRL.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CMCC_E54_H_INCLUDED */ -#endif /* _SAME54_CMCC_COMPONENT_ */ +/** + * \file + * + * \brief SAM CMCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CMCC_COMPONENT_ +#ifndef _HRI_CMCC_E54_H_INCLUDED_ +#define _HRI_CMCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) +#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CMCC_CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_cmcc_cfg_reg_t; +typedef uint32_t hri_cmcc_ctrl_reg_t; +typedef uint32_t hri_cmcc_lckway_reg_t; +typedef uint32_t hri_cmcc_maint0_reg_t; +typedef uint32_t hri_cmcc_maint1_reg_t; +typedef uint32_t hri_cmcc_mcfg_reg_t; +typedef uint32_t hri_cmcc_mctrl_reg_t; +typedef uint32_t hri_cmcc_men_reg_t; +typedef uint32_t hri_cmcc_msr_reg_t; +typedef uint32_t hri_cmcc_sr_reg_t; +typedef uint32_t hri_cmcc_type_reg_t; + +static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; +} + +static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; +} + +static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) +{ + return ((Cmcc *)hw)->TYPE.reg; +} + +static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) +{ + return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->SR.reg; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MSR.reg; +} + +static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->CFG.reg; +} + +static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->LCKWAY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) +{ + return ((Cmcc *)hw)->LCKWAY.reg; +} + +static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MCFG.reg; +} + +static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MEN.reg; +} + +static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT0.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT1.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CMCC_E54_H_INCLUDED */ +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dac_e54.h index 911dd52..e23b4a8 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dac_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dac_e54.h @@ -1,1706 +1,1706 @@ -/** - * \file - * - * \brief SAM DAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_DAC_COMPONENT_ -#ifndef _HRI_DAC_E54_H_INCLUDED_ -#define _HRI_DAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DAC_CRITICAL_SECTIONS) -#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DAC_CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dac_dacctrl_reg_t; -typedef uint16_t hri_dac_data_reg_t; -typedef uint16_t hri_dac_databuf_reg_t; -typedef uint16_t hri_dac_result_reg_t; -typedef uint32_t hri_dac_syncbusy_reg_t; -typedef uint8_t hri_dac_ctrla_reg_t; -typedef uint8_t hri_dac_ctrlb_reg_t; -typedef uint8_t hri_dac_dbgctrl_reg_t; -typedef uint8_t hri_dac_evctrl_reg_t; -typedef uint8_t hri_dac_intenset_reg_t; -typedef uint8_t hri_dac_intflag_reg_t; -typedef uint8_t hri_dac_status_reg_t; - -static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) -{ - while (((Dac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) -{ - return ((Dac *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; -} - -static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; -} - -static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; -} - -static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; -} - -static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; -} - -static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; -} - -static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; -} - -static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; -} - -static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; -} - -static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; -} - -static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; -} - -static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; -} - -static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; -} - -static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; -} - -static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; -} - -static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) -{ - return ((Dac *)hw)->INTFLAG.reg; -} - -static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - ((Dac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; -} - -static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; -} - -static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; -} - -static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; -} - -static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; -} - -static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; -} - -static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; -} - -static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; -} - -static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; - } -} - -static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; -} - -static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; -} - -static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; -} - -static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; - } -} - -static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; -} - -static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; -} - -static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; -} - -static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; - } -} - -static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; -} - -static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; -} - -static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; -} - -static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; - } -} - -static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; -} - -static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENSET.reg = mask; -} - -static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) -{ - return ((Dac *)hw)->INTENSET.reg; -} - -static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) -{ - ((Dac *)hw)->INTENSET.reg = data; - ((Dac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; -} - -static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; -} - -static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; -} - -static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; -} - -static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) -{ - return ((Dac *)hw)->STATUS.reg; -} - -static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; -} - -static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Dac *)hw)->SYNCBUSY.reg; -} - -static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, - hri_dac_result_reg_t mask) -{ - return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; -} - -static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) -{ - return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; -} - -static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, - hri_dac_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->RESULT[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) -{ - return ((Dac *)hw)->RESULT[index].reg; -} - -static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= ~DAC_CTRLA_ENABLE; - tmp |= value << DAC_CTRLA_ENABLE_Pos; - ((Dac *)hw)->CTRLA.reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg &= ~mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg ^= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) -{ - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - return ((Dac *)hw)->CTRLA.reg; -} - -static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_DIFF; - tmp |= value << DAC_CTRLB_DIFF_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_REFSEL_Msk; - tmp |= DAC_CTRLB_REFSEL(data); - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) -{ - return ((Dac *)hw)->CTRLB.reg; -} - -static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI0; - tmp |= value << DAC_EVCTRL_STARTEI0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI1; - tmp |= value << DAC_EVCTRL_STARTEI1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO0; - tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO1; - tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_INVEI0; - tmp |= value << DAC_EVCTRL_INVEI0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_INVEI1; - tmp |= value << DAC_EVCTRL_INVEI1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_RESRDYEO0; - tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_RESRDYEO1; - tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->EVCTRL.reg; -} - -static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_LEFTADJ; - tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_ENABLE; - tmp |= value << DAC_DACCTRL_ENABLE_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_FEXT; - tmp |= value << DAC_DACCTRL_FEXT_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_RUNSTDBY; - tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_DITHER; - tmp |= value << DAC_DACCTRL_DITHER_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_CCTRL_Msk; - tmp |= DAC_DACCTRL_CCTRL(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_REFRESH_Msk; - tmp |= DAC_DACCTRL_REFRESH(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_OSR_Msk; - tmp |= DAC_DACCTRL_OSR(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= mask; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) -{ - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - return ((Dac *)hw)->DACCTRL[index].reg; -} - -static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp &= ~DAC_DBGCTRL_DBGRUN; - tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; - ((Dac *)hw)->DBGCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA[index].reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF[index].reg = data; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); - DAC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DAC_E54_H_INCLUDED */ -#endif /* _SAME54_DAC_COMPONENT_ */ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DAC_COMPONENT_ +#ifndef _HRI_DAC_E54_H_INCLUDED_ +#define _HRI_DAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint16_t hri_dac_result_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; +} + +static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; +} + +static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; +} + +static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; +} + +static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; +} + +static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; +} + +static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; +} + +static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->RESULT[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) +{ + return ((Dac *)hw)->RESULT[index].reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO0; + tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO1; + tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_FEXT; + tmp |= value << DAC_DACCTRL_FEXT_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_OSR_Msk; + tmp |= DAC_DACCTRL_OSR(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_E54_H_INCLUDED */ +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dmac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dmac_e54.h index b4a6ba1..25a8094 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dmac_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dmac_e54.h @@ -1,6800 +1,6800 @@ -/** - * \file - * - * \brief SAM DMAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_DMAC_COMPONENT_ -#ifndef _HRI_DMAC_E54_H_INCLUDED_ -#define _HRI_DMAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) -#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DMAC_CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dmac_crcctrl_reg_t; -typedef uint16_t hri_dmac_ctrl_reg_t; -typedef uint16_t hri_dmac_intpend_reg_t; -typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; -typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; -typedef uint32_t hri_dmac_active_reg_t; -typedef uint32_t hri_dmac_baseaddr_reg_t; -typedef uint32_t hri_dmac_busych_reg_t; -typedef uint32_t hri_dmac_chctrla_reg_t; -typedef uint32_t hri_dmac_crcchksum_reg_t; -typedef uint32_t hri_dmac_crcdatain_reg_t; -typedef uint32_t hri_dmac_intstatus_reg_t; -typedef uint32_t hri_dmac_pendch_reg_t; -typedef uint32_t hri_dmac_prictrl0_reg_t; -typedef uint32_t hri_dmac_swtrigctrl_reg_t; -typedef uint32_t hri_dmac_wrbaddr_reg_t; -typedef uint32_t hri_dmacchannel_chctrla_reg_t; -typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; -typedef uint8_t hri_dmac_chctrlb_reg_t; -typedef uint8_t hri_dmac_chevctrl_reg_t; -typedef uint8_t hri_dmac_chintenset_reg_t; -typedef uint8_t hri_dmac_chintflag_reg_t; -typedef uint8_t hri_dmac_chprilvl_reg_t; -typedef uint8_t hri_dmac_chstatus_reg_t; -typedef uint8_t hri_dmac_crcstatus_reg_t; -typedef uint8_t hri_dmac_dbgctrl_reg_t; -typedef uint8_t hri_dmacchannel_chctrlb_reg_t; -typedef uint8_t hri_dmacchannel_chevctrl_reg_t; -typedef uint8_t hri_dmacchannel_chintenset_reg_t; -typedef uint8_t hri_dmacchannel_chintflag_reg_t; -typedef uint8_t hri_dmacchannel_chprilvl_reg_t; -typedef uint8_t hri_dmacchannel_chstatus_reg_t; - -static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTSTATUS.reg; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; -} - -static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->BUSYCH.reg; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PENDCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->PENDCH.reg; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->ACTIVE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) -{ - return ((Dmac *)hw)->ACTIVE.reg; -} - -static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_DMAENABLE; - tmp |= value << DMAC_CTRL_DMAENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN0; - tmp |= value << DMAC_CTRL_LVLEN0_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN1; - tmp |= value << DMAC_CTRL_LVLEN1_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN2; - tmp |= value << DMAC_CTRL_LVLEN2_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN3; - tmp |= value << DMAC_CTRL_LVLEN3_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CTRL.reg; -} - -static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, - hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; - tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; - tmp |= DMAC_CRCCTRL_CRCPOLY(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; - tmp |= DMAC_CRCCTRL_CRCSRC(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; - tmp |= DMAC_CRCCTRL_CRCMODE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCTRL.reg; -} - -static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, - hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; - tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); - ((Dmac *)hw)->CRCDATAIN.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCDATAIN.reg; -} - -static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, - hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; - tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); - ((Dmac *)hw)->CRCCHKSUM.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCHKSUM.reg; -} - -static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= ~DMAC_DBGCTRL_DBGRUN; - tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; - ((Dmac *)hw)->DBGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, - hri_dmac_swtrigctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->SWTRIGCTRL.reg; -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN0; - tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN1; - tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN2; - tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN3; - tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS0_Msk; - tmp |= DMAC_PRICTRL0_QOS0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS1_Msk; - tmp |= DMAC_PRICTRL0_QOS1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS2_Msk; - tmp |= DMAC_PRICTRL0_QOS2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS3_Msk; - tmp |= DMAC_PRICTRL0_QOS3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) -{ - return ((Dmac *)hw)->PRICTRL0.reg; -} - -static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TERR; - tmp |= value << DMAC_INTPEND_TERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TCMPL; - tmp |= value << DMAC_INTPEND_TCMPL_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_SUSP; - tmp |= value << DMAC_INTPEND_SUSP_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_CRCERR; - tmp |= value << DMAC_INTPEND_CRCERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_FERR; - tmp |= value << DMAC_INTPEND_FERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_BUSY; - tmp |= value << DMAC_INTPEND_BUSY_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_PEND; - tmp |= value << DMAC_INTPEND_PEND_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_ID_Msk; - tmp |= DMAC_INTPEND_ID(data); - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTPEND.reg; -} - -static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, - hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; - tmp |= DMAC_BASEADDR_BASEADDR(data); - ((Dmac *)hw)->BASEADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->BASEADDR.reg; -} - -static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; - tmp |= DMAC_WRBADDR_WRBADDR(data); - ((Dmac *)hw)->WRBADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->WRBADDR.reg; -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CRCSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCSTATUS.reg; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_VALID; - tmp |= value << DMAC_BTCTRL_VALID_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_SRCINC; - tmp |= value << DMAC_BTCTRL_SRCINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_DSTINC; - tmp |= value << DMAC_BTCTRL_DSTINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSEL; - tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; - tmp |= DMAC_BTCTRL_EVOSEL(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; - tmp |= DMAC_BTCTRL_BLOCKACT(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; - tmp |= DMAC_BTCTRL_BEATSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; - tmp |= DMAC_BTCTRL_STEPSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCTRL.reg; -} - -static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= ~DMAC_BTCNT_BTCNT_Msk; - tmp |= DMAC_BTCNT_BTCNT(data); - ((DmacDescriptor *)hw)->BTCNT.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCNT.reg; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t -hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; - tmp |= DMAC_SRCADDR_SRCADDR(data); - ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->SRCADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; - tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; - tmp |= DMAC_DSTADDR_DSTADDR(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DSTADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; - tmp |= DMAC_DESCADDR_DESCADDR(data); - ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DESCADDR.reg; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, - hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHINTFLAG.reg; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, - hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHINTENSET.reg; -} - -static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = data; - ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = mask; -} - -static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLA_TRIGSRC(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; - tmp |= DMAC_CHCTRLA_TRIGACT(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; - tmp |= DMAC_CHCTRLA_BURSTLEN(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; - tmp |= DMAC_CHCTRLA_THRESHOLD(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHCTRLA.reg; -} - -static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((DmacChannel *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHCTRLB.reg; -} - -static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; - tmp |= DMAC_CHPRILVL_PRILVL(data); - ((DmacChannel *)hw)->CHPRILVL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHPRILVL.reg; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVIE; - tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOE; - tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; - tmp |= DMAC_CHEVCTRL_EVACT(data); - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; - tmp |= DMAC_CHEVCTRL_EVOMODE(data); - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHEVCTRL.reg; -} - -static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, - hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHSTATUS.reg; -} - -static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; -} - -static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintflag_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; -} - -static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; -} - -static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t data) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; -} - -static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; -} - -static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLA_TRIGSRC(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; - tmp |= DMAC_CHCTRLA_TRIGACT(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; - tmp |= DMAC_CHCTRLA_BURSTLEN(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; - tmp |= DMAC_CHCTRLA_THRESHOLD(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; -} - -static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; -} - -static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; - tmp |= DMAC_CHPRILVL_PRILVL(data); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; -} - -static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVIE; - tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOE; - tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; - tmp |= DMAC_CHEVCTRL_EVACT(data); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; - tmp |= DMAC_CHEVCTRL_EVOMODE(data); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; -} - -static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) -#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DMAC_E54_H_INCLUDED */ -#endif /* _SAME54_DMAC_COMPONENT_ */ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_E54_H_INCLUDED_ +#define _HRI_DMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrla_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacchannel_chctrla_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrlb_reg_t; +typedef uint8_t hri_dmac_chevctrl_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chprilvl_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmacchannel_chctrlb_reg_t; +typedef uint8_t hri_dmacchannel_chevctrl_reg_t; +typedef uint8_t hri_dmacchannel_chintenset_reg_t; +typedef uint8_t hri_dmacchannel_chintflag_reg_t; +typedef uint8_t hri_dmacchannel_chprilvl_reg_t; +typedef uint8_t hri_dmacchannel_chstatus_reg_t; + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; + tmp |= DMAC_CRCCTRL_CRCMODE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS0_Msk; + tmp |= DMAC_PRICTRL0_QOS0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS1_Msk; + tmp |= DMAC_PRICTRL0_QOS1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS2_Msk; + tmp |= DMAC_PRICTRL0_QOS2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS3_Msk; + tmp |= DMAC_PRICTRL0_QOS3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_CRCERR; + tmp |= value << DMAC_INTPEND_CRCERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; + tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = data; + ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((DmacChannel *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLB.reg; +} + +static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((DmacChannel *)hw)->CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHPRILVL.reg; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHEVCTRL.reg; +} + +static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHSTATUS.reg; +} + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; +} + +static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; +} + +static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_E54_H_INCLUDED */ +#endif /* _SAME54_DMAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dsu_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dsu_e54.h index b192276..24bccee 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dsu_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_dsu_e54.h @@ -1,1256 +1,1256 @@ -/** - * \file - * - * \brief SAM DSU - * - * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_DSU_COMPONENT_ -#ifndef _HRI_DSU_E54_H_INCLUDED_ -#define _HRI_DSU_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DSU_CRITICAL_SECTIONS) -#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DSU_CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_dsu_addr_reg_t; -typedef uint32_t hri_dsu_cfg_reg_t; -typedef uint32_t hri_dsu_cid0_reg_t; -typedef uint32_t hri_dsu_cid1_reg_t; -typedef uint32_t hri_dsu_cid2_reg_t; -typedef uint32_t hri_dsu_cid3_reg_t; -typedef uint32_t hri_dsu_data_reg_t; -typedef uint32_t hri_dsu_dcc_reg_t; -typedef uint32_t hri_dsu_did_reg_t; -typedef uint32_t hri_dsu_end_reg_t; -typedef uint32_t hri_dsu_entry0_reg_t; -typedef uint32_t hri_dsu_entry1_reg_t; -typedef uint32_t hri_dsu_length_reg_t; -typedef uint32_t hri_dsu_memtype_reg_t; -typedef uint32_t hri_dsu_pid0_reg_t; -typedef uint32_t hri_dsu_pid1_reg_t; -typedef uint32_t hri_dsu_pid2_reg_t; -typedef uint32_t hri_dsu_pid3_reg_t; -typedef uint32_t hri_dsu_pid4_reg_t; -typedef uint32_t hri_dsu_pid5_reg_t; -typedef uint32_t hri_dsu_pid6_reg_t; -typedef uint32_t hri_dsu_pid7_reg_t; -typedef uint8_t hri_dsu_ctrl_reg_t; -typedef uint8_t hri_dsu_statusa_reg_t; -typedef uint8_t hri_dsu_statusb_reg_t; - -static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; -} - -static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; -} - -static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSB.reg; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) -{ - return ((Dsu *)hw)->DID.reg; -} - -static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; -} - -static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY0.reg; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY1.reg; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->END.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) -{ - return ((Dsu *)hw)->END.reg; -} - -static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) -{ - return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MEMTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) -{ - return ((Dsu *)hw)->MEMTYPE.reg; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID4.reg; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID5.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID5.reg; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID6.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID6.reg; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID7.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID7.reg; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID0.reg; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID1.reg; -} - -static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID2.reg; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID3.reg; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID0.reg; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID1.reg; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID2.reg; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID3.reg; -} - -static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_AMOD_Msk; - tmp |= DSU_ADDR_AMOD(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_ADDR_Msk; - tmp |= DSU_ADDR_ADDR(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) -{ - return ((Dsu *)hw)->ADDR.reg; -} - -static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= ~DSU_LENGTH_LENGTH_Msk; - tmp |= DSU_LENGTH_LENGTH(data); - ((Dsu *)hw)->LENGTH.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) -{ - return ((Dsu *)hw)->LENGTH.reg; -} - -static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= ~DSU_DATA_DATA_Msk; - tmp |= DSU_DATA_DATA(data); - ((Dsu *)hw)->DATA.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) -{ - return ((Dsu *)hw)->DATA.reg; -} - -static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= ~DSU_DCC_DATA_Msk; - tmp |= DSU_DCC_DATA(data); - ((Dsu *)hw)->DCC[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCC[index].reg; -} - -static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_ETBRAMEN; - tmp |= value << DSU_CFG_ETBRAMEN_Pos; - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; - return tmp; -} - -static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_LQOS_Msk; - tmp |= DSU_CFG_LQOS(data); - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; - return tmp; -} - -static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; - return tmp; -} - -static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; - tmp |= DSU_CFG_DCCDMALEVEL(data); - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; - return tmp; -} - -static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) -{ - return ((Dsu *)hw)->CFG.reg; -} - -static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; -} - -static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; -} - -static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; -} - -static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSA.reg; -} - -static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CTRL.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DSU_E54_H_INCLUDED */ -#endif /* _SAME54_DSU_COMPONENT_ */ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DSU_COMPONENT_ +#ifndef _HRI_DSU_E54_H_INCLUDED_ +#define _HRI_DSU_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cfg_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_ETBRAMEN; + tmp |= value << DSU_CFG_ETBRAMEN_Pos; + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_LQOS_Msk; + tmp |= DSU_CFG_LQOS(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; + tmp |= DSU_CFG_DCCDMALEVEL(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) +{ + return ((Dsu *)hw)->CFG.reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_E54_H_INCLUDED */ +#endif /* _SAME54_DSU_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_e54.h index 46e77ca..d1a5b0e 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_e54.h @@ -1,76 +1,76 @@ -/** - * \file - * - * \brief SAM E54 HRI top-level header file - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - */ - -#ifndef _HRI_E54_H_INCLUDED_ -#define _HRI_E54_H_INCLUDED_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _HRI_E54_H_INCLUDED_ */ +/** + * \file + * + * \brief SAM E54 HRI top-level header file + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HRI_E54_H_INCLUDED_ +#define _HRI_E54_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_E54_H_INCLUDED_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_eic_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_eic_e54.h index f86e452..9fffdf7 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_eic_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_eic_e54.h @@ -1,1838 +1,1838 @@ -/** - * \file - * - * \brief SAM EIC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_EIC_COMPONENT_ -#ifndef _HRI_EIC_E54_H_INCLUDED_ -#define _HRI_EIC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EIC_CRITICAL_SECTIONS) -#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EIC_CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_eic_nmiflag_reg_t; -typedef uint32_t hri_eic_asynch_reg_t; -typedef uint32_t hri_eic_config_reg_t; -typedef uint32_t hri_eic_debouncen_reg_t; -typedef uint32_t hri_eic_dprescaler_reg_t; -typedef uint32_t hri_eic_evctrl_reg_t; -typedef uint32_t hri_eic_intenset_reg_t; -typedef uint32_t hri_eic_intflag_reg_t; -typedef uint32_t hri_eic_pinstate_reg_t; -typedef uint32_t hri_eic_syncbusy_reg_t; -typedef uint8_t hri_eic_ctrla_reg_t; -typedef uint8_t hri_eic_nmictrl_reg_t; - -static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - while (((Eic *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - return ((Eic *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) -{ - return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; -} - -static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) -{ - ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Eic *)hw)->NMIFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->NMIFLAG.reg; -} - -static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - ((Eic *)hw)->NMIFLAG.reg = mask; -} - -static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->INTFLAG.reg; -} - -static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - ((Eic *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); - ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); -} - -static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = mask; -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) -{ - return ((Eic *)hw)->INTENSET.reg; -} - -static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = data; - ((Eic *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Eic *)hw)->SYNCBUSY.reg; -} - -static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) -{ - return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; -} - -static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) -{ - return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; -} - -static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->PINSTATE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) -{ - return ((Eic *)hw)->PINSTATE.reg; -} - -static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_ENABLE; - tmp |= value << EIC_CTRLA_ENABLE_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_CKSEL; - tmp |= value << EIC_CTRLA_CKSEL_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg = data; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= mask; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) -{ - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - return ((Eic *)hw)->CTRLA.reg; -} - -static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIFILTEN; - tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIASYNCH; - tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMISENSE_Msk; - tmp |= EIC_NMICTRL_NMISENSE(data); - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->NMICTRL.reg; -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; - tmp |= EIC_EVCTRL_EXTINTEO(data); - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->EVCTRL.reg; -} - -static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= ~EIC_ASYNCH_ASYNCH_Msk; - tmp |= EIC_ASYNCH_ASYNCH(data); - ((Eic *)hw)->ASYNCH.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) -{ - return ((Eic *)hw)->ASYNCH.reg; -} - -static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN0; - tmp |= value << EIC_CONFIG_FILTEN0_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN1; - tmp |= value << EIC_CONFIG_FILTEN1_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN2; - tmp |= value << EIC_CONFIG_FILTEN2_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN3; - tmp |= value << EIC_CONFIG_FILTEN3_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN4; - tmp |= value << EIC_CONFIG_FILTEN4_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN5; - tmp |= value << EIC_CONFIG_FILTEN5_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN6; - tmp |= value << EIC_CONFIG_FILTEN6_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN7; - tmp |= value << EIC_CONFIG_FILTEN7_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE0_Msk; - tmp |= EIC_CONFIG_SENSE0(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE1_Msk; - tmp |= EIC_CONFIG_SENSE1(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE2_Msk; - tmp |= EIC_CONFIG_SENSE2(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE3_Msk; - tmp |= EIC_CONFIG_SENSE3(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE4_Msk; - tmp |= EIC_CONFIG_SENSE4(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE5_Msk; - tmp |= EIC_CONFIG_SENSE5(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE6_Msk; - tmp |= EIC_CONFIG_SENSE6(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE7_Msk; - tmp |= EIC_CONFIG_SENSE7(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) -{ - return ((Eic *)hw)->CONFIG[index].reg; -} - -static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, - hri_eic_debouncen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; - return tmp; -} - -static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; - tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); - ((Eic *)hw)->DEBOUNCEN.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; - return tmp; -} - -static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) -{ - return ((Eic *)hw)->DEBOUNCEN.reg; -} - -static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_STATES0; - tmp |= value << EIC_DPRESCALER_STATES0_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_STATES1; - tmp |= value << EIC_DPRESCALER_STATES1_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_TICKON; - tmp |= value << EIC_DPRESCALER_TICKON_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, - hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; - tmp |= EIC_DPRESCALER_PRESCALER0(data); - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; - return tmp; -} - -static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, - hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; - tmp |= EIC_DPRESCALER_PRESCALER1(data); - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; - return tmp; -} - -static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) -{ - return ((Eic *)hw)->DPRESCALER.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EIC_E54_H_INCLUDED */ -#endif /* _SAME54_EIC_COMPONENT_ */ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EIC_COMPONENT_ +#ifndef _HRI_EIC_E54_H_INCLUDED_ +#define _HRI_EIC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_debouncen_reg_t; +typedef uint32_t hri_eic_dprescaler_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_pinstate_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->PINSTATE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) +{ + return ((Eic *)hw)->PINSTATE.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, + hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; + tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); + ((Eic *)hw)->DEBOUNCEN.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) +{ + return ((Eic *)hw)->DEBOUNCEN.reg; +} + +static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES0; + tmp |= value << EIC_DPRESCALER_STATES0_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES1; + tmp |= value << EIC_DPRESCALER_STATES1_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_TICKON; + tmp |= value << EIC_DPRESCALER_TICKON_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; + tmp |= EIC_DPRESCALER_PRESCALER0(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; + tmp |= EIC_DPRESCALER_PRESCALER1(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) +{ + return ((Eic *)hw)->DPRESCALER.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_E54_H_INCLUDED */ +#endif /* _SAME54_EIC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_evsys_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_evsys_e54.h index cd4a98a..ed76048 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_evsys_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_evsys_e54.h @@ -1,1707 +1,1707 @@ -/** - * \file - * - * \brief SAM EVSYS - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_EVSYS_COMPONENT_ -#ifndef _HRI_EVSYS_E54_H_INCLUDED_ -#define _HRI_EVSYS_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) -#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EVSYS_CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_evsys_intpend_reg_t; -typedef uint32_t hri_evsys_busych_reg_t; -typedef uint32_t hri_evsys_channel_reg_t; -typedef uint32_t hri_evsys_intstatus_reg_t; -typedef uint32_t hri_evsys_readyusr_reg_t; -typedef uint32_t hri_evsys_swevt_reg_t; -typedef uint32_t hri_evsys_user_reg_t; -typedef uint32_t hri_evsyschannel_channel_reg_t; -typedef uint8_t hri_evsys_chintenset_reg_t; -typedef uint8_t hri_evsys_chintflag_reg_t; -typedef uint8_t hri_evsys_chstatus_reg_t; -typedef uint8_t hri_evsys_ctrla_reg_t; -typedef uint8_t hri_evsys_prictrl_reg_t; -typedef uint8_t hri_evsyschannel_chintenset_reg_t; -typedef uint8_t hri_evsyschannel_chintflag_reg_t; -typedef uint8_t hri_evsyschannel_chstatus_reg_t; - -static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; -} - -static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, - hri_evsys_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTSTATUS.reg; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; -} - -static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) -{ - return ((Evsys *)hw)->BUSYCH.reg; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; -} - -static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->READYUSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) -{ - return ((Evsys *)hw)->READYUSR.reg; -} - -static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) -{ - return ((Evsys *)hw)->CTRLA.reg; -} - -static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= ~EVSYS_PRICTRL_RREN; - tmp |= value << EVSYS_PRICTRL_RREN_Pos; - ((Evsys *)hw)->PRICTRL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; - return tmp; -} - -static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) -{ - uint8_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= ~EVSYS_PRICTRL_PRI_Msk; - tmp |= EVSYS_PRICTRL_PRI(data); - ((Evsys *)hw)->PRICTRL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; - return tmp; -} - -static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) -{ - return ((Evsys *)hw)->PRICTRL.reg; -} - -static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_OVR; - tmp |= value << EVSYS_INTPEND_OVR_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_EVD; - tmp |= value << EVSYS_INTPEND_EVD_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_READY; - tmp |= value << EVSYS_INTPEND_READY_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_BUSY; - tmp |= value << EVSYS_INTPEND_BUSY_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_ID_Msk; - tmp |= EVSYS_INTPEND_ID(data); - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTPEND.reg; -} - -static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= ~EVSYS_USER_CHANNEL_Msk; - tmp |= EVSYS_USER_CHANNEL(data); - ((Evsys *)hw)->USER[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) -{ - return ((Evsys *)hw)->USER[index].reg; -} - -static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->SWEVT.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, - hri_evsys_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHINTFLAG.reg; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; -} - -static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; -} - -static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; - } else { - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; - } -} - -static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; -} - -static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; -} - -static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; -} - -static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; - } else { - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; - } -} - -static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; -} - -static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, - hri_evsys_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHINTENSET.reg; -} - -static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = data; - ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; -} - -static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; -} - -static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, - hri_evsys_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHSTATUS.reg; -} - -static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHANNEL.reg; -} - -static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; -} - -static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintflag_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; -} - -static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; -} - -static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; -} - -static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; - } else { - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; - } -} - -static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; -} - -static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; -} - -static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; -} - -static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; - } else { - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; - } -} - -static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; -} - -static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; -} - -static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; -} - -static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t data) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; -} - -static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; -} - -static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; -} - -static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EVSYS_E54_H_INCLUDED */ -#endif /* _SAME54_EVSYS_COMPONENT_ */ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_E54_H_INCLUDED_ +#define _HRI_EVSYS_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_evsys_intpend_reg_t; +typedef uint32_t hri_evsys_busych_reg_t; +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_intstatus_reg_t; +typedef uint32_t hri_evsys_readyusr_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint32_t hri_evsyschannel_channel_reg_t; +typedef uint8_t hri_evsys_chintenset_reg_t; +typedef uint8_t hri_evsys_chintflag_reg_t; +typedef uint8_t hri_evsys_chstatus_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; +typedef uint8_t hri_evsys_prictrl_reg_t; +typedef uint8_t hri_evsyschannel_chintenset_reg_t; +typedef uint8_t hri_evsyschannel_chintflag_reg_t; +typedef uint8_t hri_evsyschannel_chstatus_reg_t; + +static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, + hri_evsys_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTSTATUS.reg; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) +{ + return ((Evsys *)hw)->BUSYCH.reg; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->READYUSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) +{ + return ((Evsys *)hw)->READYUSR.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_RREN; + tmp |= value << EVSYS_PRICTRL_RREN_Pos; + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_PRI_Msk; + tmp |= EVSYS_PRICTRL_PRI(data); + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) +{ + return ((Evsys *)hw)->PRICTRL.reg; +} + +static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_OVR; + tmp |= value << EVSYS_INTPEND_OVR_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_EVD; + tmp |= value << EVSYS_INTPEND_EVD_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_READY; + tmp |= value << EVSYS_INTPEND_READY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_BUSY; + tmp |= value << EVSYS_INTPEND_BUSY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_ID_Msk; + tmp |= EVSYS_INTPEND_ID(data); + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTPEND.reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = data; + ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHANNEL.reg; +} + +static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t data) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_E54_H_INCLUDED */ +#endif /* _SAME54_EVSYS_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_freqm_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_freqm_e54.h index 8cbc484..495f954 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_freqm_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_freqm_e54.h @@ -1,464 +1,464 @@ -/** - * \file - * - * \brief SAM FREQM - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_FREQM_COMPONENT_ -#ifndef _HRI_FREQM_E54_H_INCLUDED_ -#define _HRI_FREQM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) -#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define FREQM_CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_freqm_cfga_reg_t; -typedef uint32_t hri_freqm_syncbusy_reg_t; -typedef uint32_t hri_freqm_value_reg_t; -typedef uint8_t hri_freqm_ctrla_reg_t; -typedef uint8_t hri_freqm_ctrlb_reg_t; -typedef uint8_t hri_freqm_intenset_reg_t; -typedef uint8_t hri_freqm_intflag_reg_t; -typedef uint8_t hri_freqm_status_reg_t; - -static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - while (((Freqm *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - return ((Freqm *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTFLAG.reg; -} - -static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - ((Freqm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; -} - -static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; -} - -static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; - } else { - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; - } -} - -static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; -} - -static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENSET.reg = mask; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTENSET.reg; -} - -static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) -{ - ((Freqm *)hw)->INTENSET.reg = data; - ((Freqm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Freqm *)hw)->SYNCBUSY.reg; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->VALUE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) -{ - return ((Freqm *)hw)->VALUE.reg; -} - -static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= ~FREQM_CTRLA_ENABLE; - tmp |= value << FREQM_CTRLA_ENABLE_Pos; - ((Freqm *)hw)->CTRLA.reg = tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg = data; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= mask; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) -{ - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); - return ((Freqm *)hw)->CTRLA.reg; -} - -static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) -{ - uint16_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= ~FREQM_CFGA_REFNUM_Msk; - tmp |= FREQM_CFGA_REFNUM(data); - ((Freqm *)hw)->CFGA.reg = tmp; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) -{ - return ((Freqm *)hw)->CFGA.reg; -} - -static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; -} - -static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; -} - -static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) -{ - return ((Freqm *)hw)->STATUS.reg; -} - -static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLB.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_FREQM_E54_H_INCLUDED */ -#endif /* _SAME54_FREQM_COMPONENT_ */ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_E54_H_INCLUDED_ +#define _HRI_FREQM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_E54_H_INCLUDED */ +#endif /* _SAME54_FREQM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gclk_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gclk_e54.h index f83af2a..f4de576 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gclk_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gclk_e54.h @@ -1,805 +1,805 @@ -/** - * \file - * - * \brief SAM GCLK - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_GCLK_COMPONENT_ -#ifndef _HRI_GCLK_E54_H_INCLUDED_ -#define _HRI_GCLK_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) -#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GCLK_CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_gclk_genctrl_reg_t; -typedef uint32_t hri_gclk_pchctrl_reg_t; -typedef uint32_t hri_gclk_syncbusy_reg_t; -typedef uint8_t hri_gclk_ctrla_reg_t; - -static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - while (((Gclk *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - return ((Gclk *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Gclk *)hw)->SYNCBUSY.reg; -} - -static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg = data; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg &= ~mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg ^= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) -{ - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - return ((Gclk *)hw)->CTRLA.reg; -} - -static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_GENEN; - tmp |= value << GCLK_GENCTRL_GENEN_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_IDC; - tmp |= value << GCLK_GENCTRL_IDC_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OOV; - tmp |= value << GCLK_GENCTRL_OOV_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OE; - tmp |= value << GCLK_GENCTRL_OE_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIVSEL; - tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_RUNSTDBY; - tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_SRC_Msk; - tmp |= GCLK_GENCTRL_SRC(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIV_Msk; - tmp |= GCLK_GENCTRL_DIV(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg = data; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= mask; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) -{ - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); - return ((Gclk *)hw)->GENCTRL[index].reg; -} - -static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_CHEN; - tmp |= value << GCLK_PCHCTRL_CHEN_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_WRTLOCK; - tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_GEN_Msk; - tmp |= GCLK_PCHCTRL_GEN(data); - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Gclk *)hw)->PCHCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GCLK_E54_H_INCLUDED */ -#endif /* _SAME54_GCLK_COMPONENT_ */ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_E54_H_INCLUDED_ +#define _HRI_GCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_E54_H_INCLUDED */ +#endif /* _SAME54_GCLK_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gmac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gmac_e54.h index 2875061..a78e404 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gmac_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_gmac_e54.h @@ -1,3766 +1,3766 @@ -/** - * \file - * - * \brief SAM GMAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_GMAC_COMPONENT_ -#ifndef _HRI_GMAC_E54_H_INCLUDED_ -#define _HRI_GMAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) -#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GMAC_CRITICAL_SECTION_ENTER() -#define GMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_gmac_ae_reg_t; -typedef uint32_t hri_gmac_bcfr_reg_t; -typedef uint32_t hri_gmac_bcft_reg_t; -typedef uint32_t hri_gmac_bfr64_reg_t; -typedef uint32_t hri_gmac_bft64_reg_t; -typedef uint32_t hri_gmac_cse_reg_t; -typedef uint32_t hri_gmac_dcfgr_reg_t; -typedef uint32_t hri_gmac_dtf_reg_t; -typedef uint32_t hri_gmac_ec_reg_t; -typedef uint32_t hri_gmac_efrn_reg_t; -typedef uint32_t hri_gmac_efrsh_reg_t; -typedef uint32_t hri_gmac_efrsl_reg_t; -typedef uint32_t hri_gmac_eftn_reg_t; -typedef uint32_t hri_gmac_eftsh_reg_t; -typedef uint32_t hri_gmac_eftsl_reg_t; -typedef uint32_t hri_gmac_fcse_reg_t; -typedef uint32_t hri_gmac_fr_reg_t; -typedef uint32_t hri_gmac_ft_reg_t; -typedef uint32_t hri_gmac_gtbft1518_reg_t; -typedef uint32_t hri_gmac_hrb_reg_t; -typedef uint32_t hri_gmac_hrt_reg_t; -typedef uint32_t hri_gmac_ihce_reg_t; -typedef uint32_t hri_gmac_imr_reg_t; -typedef uint32_t hri_gmac_ipgs_reg_t; -typedef uint32_t hri_gmac_isr_reg_t; -typedef uint32_t hri_gmac_jr_reg_t; -typedef uint32_t hri_gmac_lc_reg_t; -typedef uint32_t hri_gmac_lffe_reg_t; -typedef uint32_t hri_gmac_man_reg_t; -typedef uint32_t hri_gmac_mcf_reg_t; -typedef uint32_t hri_gmac_mfr_reg_t; -typedef uint32_t hri_gmac_mft_reg_t; -typedef uint32_t hri_gmac_ncfgr_reg_t; -typedef uint32_t hri_gmac_ncr_reg_t; -typedef uint32_t hri_gmac_nsc_reg_t; -typedef uint32_t hri_gmac_nsr_reg_t; -typedef uint32_t hri_gmac_ofr_reg_t; -typedef uint32_t hri_gmac_orhi_reg_t; -typedef uint32_t hri_gmac_orlo_reg_t; -typedef uint32_t hri_gmac_othi_reg_t; -typedef uint32_t hri_gmac_otlo_reg_t; -typedef uint32_t hri_gmac_pefrn_reg_t; -typedef uint32_t hri_gmac_pefrsh_reg_t; -typedef uint32_t hri_gmac_pefrsl_reg_t; -typedef uint32_t hri_gmac_peftn_reg_t; -typedef uint32_t hri_gmac_peftsh_reg_t; -typedef uint32_t hri_gmac_peftsl_reg_t; -typedef uint32_t hri_gmac_pfr_reg_t; -typedef uint32_t hri_gmac_pft_reg_t; -typedef uint32_t hri_gmac_rbqb_reg_t; -typedef uint32_t hri_gmac_rjfml_reg_t; -typedef uint32_t hri_gmac_rlpiti_reg_t; -typedef uint32_t hri_gmac_rlpitr_reg_t; -typedef uint32_t hri_gmac_roe_reg_t; -typedef uint32_t hri_gmac_rpq_reg_t; -typedef uint32_t hri_gmac_rpsf_reg_t; -typedef uint32_t hri_gmac_rre_reg_t; -typedef uint32_t hri_gmac_rse_reg_t; -typedef uint32_t hri_gmac_rsr_reg_t; -typedef uint32_t hri_gmac_sab_reg_t; -typedef uint32_t hri_gmac_samb1_reg_t; -typedef uint32_t hri_gmac_samt1_reg_t; -typedef uint32_t hri_gmac_sat_reg_t; -typedef uint32_t hri_gmac_scf_reg_t; -typedef uint32_t hri_gmac_sch_reg_t; -typedef uint32_t hri_gmac_scl_reg_t; -typedef uint32_t hri_gmac_svlan_reg_t; -typedef uint32_t hri_gmac_ta_reg_t; -typedef uint32_t hri_gmac_tbfr1023_reg_t; -typedef uint32_t hri_gmac_tbfr127_reg_t; -typedef uint32_t hri_gmac_tbfr1518_reg_t; -typedef uint32_t hri_gmac_tbfr255_reg_t; -typedef uint32_t hri_gmac_tbfr511_reg_t; -typedef uint32_t hri_gmac_tbft1023_reg_t; -typedef uint32_t hri_gmac_tbft127_reg_t; -typedef uint32_t hri_gmac_tbft1518_reg_t; -typedef uint32_t hri_gmac_tbft255_reg_t; -typedef uint32_t hri_gmac_tbft511_reg_t; -typedef uint32_t hri_gmac_tbqb_reg_t; -typedef uint32_t hri_gmac_tce_reg_t; -typedef uint32_t hri_gmac_ti_reg_t; -typedef uint32_t hri_gmac_tidm_reg_t; -typedef uint32_t hri_gmac_tisubn_reg_t; -typedef uint32_t hri_gmac_tlpiti_reg_t; -typedef uint32_t hri_gmac_tlpitr_reg_t; -typedef uint32_t hri_gmac_tmxbfr_reg_t; -typedef uint32_t hri_gmac_tn_reg_t; -typedef uint32_t hri_gmac_tpfcp_reg_t; -typedef uint32_t hri_gmac_tpq_reg_t; -typedef uint32_t hri_gmac_tpsf_reg_t; -typedef uint32_t hri_gmac_tsh_reg_t; -typedef uint32_t hri_gmac_tsl_reg_t; -typedef uint32_t hri_gmac_tsr_reg_t; -typedef uint32_t hri_gmac_tssn_reg_t; -typedef uint32_t hri_gmac_tsssl_reg_t; -typedef uint32_t hri_gmac_tur_reg_t; -typedef uint32_t hri_gmac_uce_reg_t; -typedef uint32_t hri_gmac_ufr_reg_t; -typedef uint32_t hri_gmac_ur_reg_t; -typedef uint32_t hri_gmac_wol_reg_t; -typedef uint32_t hri_gmacsa_sab_reg_t; -typedef uint32_t hri_gmacsa_sat_reg_t; - -static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - uint32_t tmp; - tmp = ((GmacSa *)hw)->SAB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) -{ - return ((GmacSa *)hw)->SAB.reg; -} - -static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - uint32_t tmp; - tmp = ((GmacSa *)hw)->SAT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((GmacSa *)hw)->SAT.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) -{ - return ((GmacSa *)hw)->SAT.reg; -} - -static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, - hri_gmac_sab_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; -} - -static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, - hri_gmac_sat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; -} - -static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; -} - -static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; -} - -static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; - } -} - -static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; -} - -static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; -} - -static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; -} - -static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; - } -} - -static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; -} - -static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; -} - -static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; -} - -static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; - } -} - -static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; -} - -static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; -} - -static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; -} - -static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; - } -} - -static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; -} - -static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; -} - -static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; -} - -static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; - } -} - -static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; -} - -static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; -} - -static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; -} - -static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; - } -} - -static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; -} - -static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; -} - -static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; -} - -static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; - } -} - -static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; -} - -static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; -} - -static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; -} - -static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; - } -} - -static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; -} - -static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; -} - -static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; -} - -static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; - } -} - -static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; -} - -static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; -} - -static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; -} - -static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; - } -} - -static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; -} - -static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; -} - -static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; -} - -static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; - } -} - -static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; -} - -static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; -} - -static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; -} - -static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; - } -} - -static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; -} - -static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; -} - -static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; -} - -static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; - } -} - -static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; -} - -static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; -} - -static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; -} - -static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; - } -} - -static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; -} - -static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; -} - -static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; -} - -static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; - } -} - -static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; -} - -static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; -} - -static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; -} - -static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; - } -} - -static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; -} - -static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; -} - -static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; -} - -static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; - } -} - -static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; -} - -static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; -} - -static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; -} - -static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; - } -} - -static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; -} - -static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; -} - -static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; -} - -static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; - } -} - -static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; -} - -static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; -} - -static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; -} - -static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; - } -} - -static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; -} - -static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; -} - -static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; -} - -static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; - } -} - -static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; -} - -static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; -} - -static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; -} - -static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; - } -} - -static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; -} - -static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; -} - -static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; -} - -static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; - } -} - -static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; -} - -static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; -} - -static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; -} - -static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; - } -} - -static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; -} - -static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; -} - -static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) -{ - return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; -} - -static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; - } else { - ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; - } -} - -static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) -{ - ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; -} - -static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) -{ - ((Gmac *)hw)->IER.reg = mask; -} - -static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) -{ - return ((Gmac *)hw)->IMR.reg; -} - -static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) -{ - ((Gmac *)hw)->IER.reg = data; - ((Gmac *)hw)->IDR.reg = ~data; -} - -static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) -{ - ((Gmac *)hw)->IDR.reg = mask; -} - -static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) -{ - return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; -} - -static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) -{ - return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; -} - -static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) -{ - return ((Gmac *)hw)->NSR.reg; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) -{ - return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) -{ - return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RPQ.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) -{ - return ((Gmac *)hw)->RPQ.reg; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) -{ - return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFTSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFTSH.reg; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) -{ - return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFRSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFRSH.reg; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) -{ - return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFTSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFTSH.reg; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) -{ - return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFRSH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFRSH.reg; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) -{ - return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->OTLO.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) -{ - return ((Gmac *)hw)->OTLO.reg; -} - -static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) -{ - return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; -} - -static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; -} - -static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->OTHI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) -{ - return ((Gmac *)hw)->OTHI.reg; -} - -static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) -{ - return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; -} - -static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; -} - -static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->FT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) -{ - return ((Gmac *)hw)->FT.reg; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) -{ - return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BCFT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) -{ - return ((Gmac *)hw)->BCFT.reg; -} - -static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) -{ - return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; -} - -static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; -} - -static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MFT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) -{ - return ((Gmac *)hw)->MFT.reg; -} - -static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) -{ - return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; -} - -static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; -} - -static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PFT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) -{ - return ((Gmac *)hw)->PFT.reg; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) -{ - return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BFT64.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) -{ - return ((Gmac *)hw)->BFT64.reg; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) -{ - return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT127.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT127.reg; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) -{ - return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT255.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT255.reg; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) -{ - return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT511.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT511.reg; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) -{ - return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT1023.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT1023.reg; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) -{ - return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFT1518.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFT1518.reg; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, - hri_gmac_gtbft1518_reg_t mask) -{ - return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) -{ - return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->GTBFT1518.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) -{ - return ((Gmac *)hw)->GTBFT1518.reg; -} - -static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) -{ - return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; -} - -static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) -{ - return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; -} - -static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TUR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TUR.reg; -} - -static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) -{ - return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; -} - -static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; -} - -static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SCF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) -{ - return ((Gmac *)hw)->SCF.reg; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) -{ - return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MCF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) -{ - return ((Gmac *)hw)->MCF.reg; -} - -static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) -{ - return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; -} - -static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; -} - -static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) -{ - return ((Gmac *)hw)->EC.reg; -} - -static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) -{ - return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; -} - -static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) -{ - return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; -} - -static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->LC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) -{ - return ((Gmac *)hw)->LC.reg; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) -{ - return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) -{ - return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->DTF.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) -{ - return ((Gmac *)hw)->DTF.reg; -} - -static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) -{ - return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; -} - -static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) -{ - return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; -} - -static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->CSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) -{ - return ((Gmac *)hw)->CSE.reg; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) -{ - return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ORLO.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) -{ - return ((Gmac *)hw)->ORLO.reg; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) -{ - return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) -{ - return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ORHI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) -{ - return ((Gmac *)hw)->ORHI.reg; -} - -static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) -{ - return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; -} - -static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; -} - -static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->FR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) -{ - return ((Gmac *)hw)->FR.reg; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) -{ - return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BCFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->BCFR.reg; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) -{ - return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->MFR.reg; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) -{ - return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->PFR.reg; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) -{ - return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->BFR64.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) -{ - return ((Gmac *)hw)->BFR64.reg; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) -{ - return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR127.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR127.reg; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) -{ - return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR255.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR255.reg; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) -{ - return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR511.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR511.reg; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) -{ - return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR1023.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR1023.reg; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) -{ - return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBFR1518.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBFR1518.reg; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) -{ - return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TMXBFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TMXBFR.reg; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) -{ - return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->UFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->UFR.reg; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) -{ - return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->OFR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) -{ - return ((Gmac *)hw)->OFR.reg; -} - -static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) -{ - return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; -} - -static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) -{ - return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; -} - -static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->JR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) -{ - return ((Gmac *)hw)->JR.reg; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) -{ - return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) -{ - return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->FCSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) -{ - return ((Gmac *)hw)->FCSE.reg; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) -{ - return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) -{ - return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->LFFE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) -{ - return ((Gmac *)hw)->LFFE.reg; -} - -static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) -{ - return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; -} - -static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) -{ - return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; -} - -static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) -{ - return ((Gmac *)hw)->RSE.reg; -} - -static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) -{ - return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; -} - -static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) -{ - return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; -} - -static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->AE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) -{ - return ((Gmac *)hw)->AE.reg; -} - -static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) -{ - return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; -} - -static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) -{ - return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; -} - -static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RRE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) -{ - return ((Gmac *)hw)->RRE.reg; -} - -static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) -{ - return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; -} - -static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) -{ - return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; -} - -static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ROE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) -{ - return ((Gmac *)hw)->ROE.reg; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) -{ - return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) -{ - return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->IHCE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) -{ - return ((Gmac *)hw)->IHCE.reg; -} - -static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) -{ - return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; -} - -static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) -{ - return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; -} - -static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TCE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) -{ - return ((Gmac *)hw)->TCE.reg; -} - -static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) -{ - return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; -} - -static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) -{ - return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; -} - -static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->UCE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) -{ - return ((Gmac *)hw)->UCE.reg; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) -{ - return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFTSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFTSL.reg; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) -{ - return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFTN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFTN.reg; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) -{ - return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFRSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFRSL.reg; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) -{ - return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->EFRN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) -{ - return ((Gmac *)hw)->EFRN.reg; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) -{ - return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFTSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFTSL.reg; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) -{ - return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFTN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFTN.reg; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) -{ - return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFRSL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFRSL.reg; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) -{ - return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) -{ - return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->PEFRN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) -{ - return ((Gmac *)hw)->PEFRN.reg; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) -{ - return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) -{ - return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RLPITR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) -{ - return ((Gmac *)hw)->RLPITR.reg; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) -{ - return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) -{ - return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RLPITI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) -{ - return ((Gmac *)hw)->RLPITI.reg; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) -{ - return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) -{ - return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TLPITR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TLPITR.reg; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) -{ - return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) -{ - return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TLPITI.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) -{ - return ((Gmac *)hw)->TLPITI.reg; -} - -static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) -{ - return ((Gmac *)hw)->NCR.reg; -} - -static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NCFGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NCFGR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) -{ - return ((Gmac *)hw)->NCFGR.reg; -} - -static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->UR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->UR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) -{ - return ((Gmac *)hw)->UR.reg; -} - -static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->DCFGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->DCFGR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) -{ - return ((Gmac *)hw)->DCFGR.reg; -} - -static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSR.reg; -} - -static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RBQB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RBQB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) -{ - return ((Gmac *)hw)->RBQB.reg; -} - -static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TBQB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TBQB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) -{ - return ((Gmac *)hw)->TBQB.reg; -} - -static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RSR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) -{ - return ((Gmac *)hw)->RSR.reg; -} - -static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->ISR.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) -{ - return ((Gmac *)hw)->ISR.reg; -} - -static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->MAN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->MAN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) -{ - return ((Gmac *)hw)->MAN.reg; -} - -static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TPQ.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPQ.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) -{ - return ((Gmac *)hw)->TPQ.reg; -} - -static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TPSF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPSF.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) -{ - return ((Gmac *)hw)->TPSF.reg; -} - -static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RPSF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RPSF.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) -{ - return ((Gmac *)hw)->RPSF.reg; -} - -static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->RJFML.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->RJFML.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) -{ - return ((Gmac *)hw)->RJFML.reg; -} - -static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->HRB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRB.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) -{ - return ((Gmac *)hw)->HRB.reg; -} - -static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->HRT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->HRT.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) -{ - return ((Gmac *)hw)->HRT.reg; -} - -static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TIDM[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TIDM[index].reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) -{ - return ((Gmac *)hw)->TIDM[index].reg; -} - -static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->WOL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->WOL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) -{ - return ((Gmac *)hw)->WOL.reg; -} - -static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->IPGS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->IPGS.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) -{ - return ((Gmac *)hw)->IPGS.reg; -} - -static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SVLAN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SVLAN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) -{ - return ((Gmac *)hw)->SVLAN.reg; -} - -static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TPFCP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TPFCP.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) -{ - return ((Gmac *)hw)->TPFCP.reg; -} - -static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SAMB1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMB1.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) -{ - return ((Gmac *)hw)->SAMB1.reg; -} - -static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SAMT1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SAMT1.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) -{ - return ((Gmac *)hw)->SAMT1.reg; -} - -static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->NSC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->NSC.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) -{ - return ((Gmac *)hw)->NSC.reg; -} - -static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SCL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) -{ - return ((Gmac *)hw)->SCL.reg; -} - -static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->SCH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->SCH.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) -{ - return ((Gmac *)hw)->SCH.reg; -} - -static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TISUBN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TISUBN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) -{ - return ((Gmac *)hw)->TISUBN.reg; -} - -static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSH.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSH.reg; -} - -static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSSSL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSSL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSSSL.reg; -} - -static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSSN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSSN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSSN.reg; -} - -static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TSL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TSL.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) -{ - return ((Gmac *)hw)->TSL.reg; -} - -static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TN.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) -{ - return ((Gmac *)hw)->TN.reg; -} - -static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg |= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gmac *)hw)->TI.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg &= ~mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TI.reg ^= mask; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) -{ - return ((Gmac *)hw)->TI.reg; -} - -static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) -{ - GMAC_CRITICAL_SECTION_ENTER(); - ((Gmac *)hw)->TA.reg = data; - GMAC_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GMAC_E54_H_INCLUDED */ -#endif /* _SAME54_GMAC_COMPONENT_ */ +/** + * \file + * + * \brief SAM GMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GMAC_COMPONENT_ +#ifndef _HRI_GMAC_E54_H_INCLUDED_ +#define _HRI_GMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) +#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GMAC_CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gmac_ae_reg_t; +typedef uint32_t hri_gmac_bcfr_reg_t; +typedef uint32_t hri_gmac_bcft_reg_t; +typedef uint32_t hri_gmac_bfr64_reg_t; +typedef uint32_t hri_gmac_bft64_reg_t; +typedef uint32_t hri_gmac_cse_reg_t; +typedef uint32_t hri_gmac_dcfgr_reg_t; +typedef uint32_t hri_gmac_dtf_reg_t; +typedef uint32_t hri_gmac_ec_reg_t; +typedef uint32_t hri_gmac_efrn_reg_t; +typedef uint32_t hri_gmac_efrsh_reg_t; +typedef uint32_t hri_gmac_efrsl_reg_t; +typedef uint32_t hri_gmac_eftn_reg_t; +typedef uint32_t hri_gmac_eftsh_reg_t; +typedef uint32_t hri_gmac_eftsl_reg_t; +typedef uint32_t hri_gmac_fcse_reg_t; +typedef uint32_t hri_gmac_fr_reg_t; +typedef uint32_t hri_gmac_ft_reg_t; +typedef uint32_t hri_gmac_gtbft1518_reg_t; +typedef uint32_t hri_gmac_hrb_reg_t; +typedef uint32_t hri_gmac_hrt_reg_t; +typedef uint32_t hri_gmac_ihce_reg_t; +typedef uint32_t hri_gmac_imr_reg_t; +typedef uint32_t hri_gmac_ipgs_reg_t; +typedef uint32_t hri_gmac_isr_reg_t; +typedef uint32_t hri_gmac_jr_reg_t; +typedef uint32_t hri_gmac_lc_reg_t; +typedef uint32_t hri_gmac_lffe_reg_t; +typedef uint32_t hri_gmac_man_reg_t; +typedef uint32_t hri_gmac_mcf_reg_t; +typedef uint32_t hri_gmac_mfr_reg_t; +typedef uint32_t hri_gmac_mft_reg_t; +typedef uint32_t hri_gmac_ncfgr_reg_t; +typedef uint32_t hri_gmac_ncr_reg_t; +typedef uint32_t hri_gmac_nsc_reg_t; +typedef uint32_t hri_gmac_nsr_reg_t; +typedef uint32_t hri_gmac_ofr_reg_t; +typedef uint32_t hri_gmac_orhi_reg_t; +typedef uint32_t hri_gmac_orlo_reg_t; +typedef uint32_t hri_gmac_othi_reg_t; +typedef uint32_t hri_gmac_otlo_reg_t; +typedef uint32_t hri_gmac_pefrn_reg_t; +typedef uint32_t hri_gmac_pefrsh_reg_t; +typedef uint32_t hri_gmac_pefrsl_reg_t; +typedef uint32_t hri_gmac_peftn_reg_t; +typedef uint32_t hri_gmac_peftsh_reg_t; +typedef uint32_t hri_gmac_peftsl_reg_t; +typedef uint32_t hri_gmac_pfr_reg_t; +typedef uint32_t hri_gmac_pft_reg_t; +typedef uint32_t hri_gmac_rbqb_reg_t; +typedef uint32_t hri_gmac_rjfml_reg_t; +typedef uint32_t hri_gmac_rlpiti_reg_t; +typedef uint32_t hri_gmac_rlpitr_reg_t; +typedef uint32_t hri_gmac_roe_reg_t; +typedef uint32_t hri_gmac_rpq_reg_t; +typedef uint32_t hri_gmac_rpsf_reg_t; +typedef uint32_t hri_gmac_rre_reg_t; +typedef uint32_t hri_gmac_rse_reg_t; +typedef uint32_t hri_gmac_rsr_reg_t; +typedef uint32_t hri_gmac_sab_reg_t; +typedef uint32_t hri_gmac_samb1_reg_t; +typedef uint32_t hri_gmac_samt1_reg_t; +typedef uint32_t hri_gmac_sat_reg_t; +typedef uint32_t hri_gmac_scf_reg_t; +typedef uint32_t hri_gmac_sch_reg_t; +typedef uint32_t hri_gmac_scl_reg_t; +typedef uint32_t hri_gmac_svlan_reg_t; +typedef uint32_t hri_gmac_ta_reg_t; +typedef uint32_t hri_gmac_tbfr1023_reg_t; +typedef uint32_t hri_gmac_tbfr127_reg_t; +typedef uint32_t hri_gmac_tbfr1518_reg_t; +typedef uint32_t hri_gmac_tbfr255_reg_t; +typedef uint32_t hri_gmac_tbfr511_reg_t; +typedef uint32_t hri_gmac_tbft1023_reg_t; +typedef uint32_t hri_gmac_tbft127_reg_t; +typedef uint32_t hri_gmac_tbft1518_reg_t; +typedef uint32_t hri_gmac_tbft255_reg_t; +typedef uint32_t hri_gmac_tbft511_reg_t; +typedef uint32_t hri_gmac_tbqb_reg_t; +typedef uint32_t hri_gmac_tce_reg_t; +typedef uint32_t hri_gmac_ti_reg_t; +typedef uint32_t hri_gmac_tidm_reg_t; +typedef uint32_t hri_gmac_tisubn_reg_t; +typedef uint32_t hri_gmac_tlpiti_reg_t; +typedef uint32_t hri_gmac_tlpitr_reg_t; +typedef uint32_t hri_gmac_tmxbfr_reg_t; +typedef uint32_t hri_gmac_tn_reg_t; +typedef uint32_t hri_gmac_tpfcp_reg_t; +typedef uint32_t hri_gmac_tpq_reg_t; +typedef uint32_t hri_gmac_tpsf_reg_t; +typedef uint32_t hri_gmac_tsh_reg_t; +typedef uint32_t hri_gmac_tsl_reg_t; +typedef uint32_t hri_gmac_tsr_reg_t; +typedef uint32_t hri_gmac_tssn_reg_t; +typedef uint32_t hri_gmac_tsssl_reg_t; +typedef uint32_t hri_gmac_tur_reg_t; +typedef uint32_t hri_gmac_uce_reg_t; +typedef uint32_t hri_gmac_ufr_reg_t; +typedef uint32_t hri_gmac_ur_reg_t; +typedef uint32_t hri_gmac_wol_reg_t; +typedef uint32_t hri_gmacsa_sab_reg_t; +typedef uint32_t hri_gmacsa_sat_reg_t; + +static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAB.reg; +} + +static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAT.reg; +} + +static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; +} + +static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; +} + +static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; +} + +static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; +} + +static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; + } +} + +static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; +} + +static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; +} + +static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; + } +} + +static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; +} + +static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; +} + +static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; + } +} + +static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; +} + +static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; +} + +static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; + } +} + +static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; +} + +static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; +} + +static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; +} + +static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; + } +} + +static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; +} + +static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; +} + +static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; +} + +static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; + } +} + +static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; +} + +static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; +} + +static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; +} + +static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; + } +} + +static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; +} + +static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; +} + +static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; + } +} + +static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; +} + +static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; +} + +static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; +} + +static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; + } +} + +static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; +} + +static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; +} + +static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; +} + +static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; + } +} + +static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; +} + +static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; +} + +static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; +} + +static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; + } +} + +static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; +} + +static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; +} + +static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; +} + +static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; + } +} + +static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; +} + +static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; +} + +static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; +} + +static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; + } +} + +static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; +} + +static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; +} + +static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; +} + +static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; + } +} + +static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; +} + +static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; +} + +static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; + } +} + +static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; +} + +static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; +} + +static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; +} + +static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; + } +} + +static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; +} + +static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; +} + +static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; + } +} + +static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; +} + +static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; +} + +static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; +} + +static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; + } +} + +static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; +} + +static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; +} + +static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; +} + +static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; +} + +static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; +} + +static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; +} + +static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; +} + +static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; +} + +static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; +} + +static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; +} + +static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; +} + +static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; + } +} + +static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; +} + +static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; +} + +static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; +} + +static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; + } +} + +static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; +} + +static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; +} + +static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; +} + +static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; + } +} + +static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; +} + +static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IER.reg = mask; +} + +static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) +{ + return ((Gmac *)hw)->IMR.reg; +} + +static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) +{ + ((Gmac *)hw)->IER.reg = data; + ((Gmac *)hw)->IDR.reg = ~data; +} + +static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IDR.reg = mask; +} + +static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; +} + +static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSR.reg; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPQ.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPQ.reg; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSH.reg; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSH.reg; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSH.reg; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSH.reg; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTLO.reg; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTHI.reg; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) +{ + return ((Gmac *)hw)->FT.reg; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFT.reg; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFT.reg; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFT.reg; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFT64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFT64.reg; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT127.reg; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT255.reg; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT511.reg; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1023.reg; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1518.reg; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, + hri_gmac_gtbft1518_reg_t mask) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GTBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GTBFT1518.reg; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TUR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TUR.reg; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCF.reg; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->MCF.reg; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) +{ + return ((Gmac *)hw)->EC.reg; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) +{ + return ((Gmac *)hw)->LC.reg; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DTF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) +{ + return ((Gmac *)hw)->DTF.reg; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->CSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->CSE.reg; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORLO.reg; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORHI.reg; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) +{ + return ((Gmac *)hw)->FR.reg; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFR.reg; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFR.reg; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFR.reg; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFR64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFR64.reg; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR127.reg; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR255.reg; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR511.reg; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1023.reg; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1518.reg; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TMXBFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TMXBFR.reg; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UFR.reg; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->OFR.reg; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->JR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) +{ + return ((Gmac *)hw)->JR.reg; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FCSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->FCSE.reg; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LFFE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) +{ + return ((Gmac *)hw)->LFFE.reg; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSE.reg; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->AE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) +{ + return ((Gmac *)hw)->AE.reg; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RRE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RRE.reg; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ROE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) +{ + return ((Gmac *)hw)->ROE.reg; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IHCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->IHCE.reg; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->TCE.reg; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->UCE.reg; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSL.reg; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTN.reg; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSL.reg; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRN.reg; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSL.reg; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTN.reg; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSL.reg; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRN.reg; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITR.reg; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITI.reg; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITR.reg; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITI.reg; +} + +static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCR.reg; +} + +static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCFGR.reg; +} + +static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UR.reg; +} + +static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->DCFGR.reg; +} + +static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSR.reg; +} + +static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->RBQB.reg; +} + +static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBQB.reg; +} + +static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSR.reg; +} + +static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) +{ + return ((Gmac *)hw)->ISR.reg; +} + +static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->MAN.reg; +} + +static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPQ.reg; +} + +static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPSF.reg; +} + +static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPSF.reg; +} + +static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RJFML.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) +{ + return ((Gmac *)hw)->RJFML.reg; +} + +static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRB.reg; +} + +static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRT.reg; +} + +static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TIDM[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->TIDM[index].reg; +} + +static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->WOL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) +{ + return ((Gmac *)hw)->WOL.reg; +} + +static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IPGS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) +{ + return ((Gmac *)hw)->IPGS.reg; +} + +static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SVLAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->SVLAN.reg; +} + +static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPFCP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPFCP.reg; +} + +static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMB1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMB1.reg; +} + +static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMT1.reg; +} + +static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSC.reg; +} + +static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCL.reg; +} + +static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCH.reg; +} + +static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TISUBN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TISUBN.reg; +} + +static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSH.reg; +} + +static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSSL.reg; +} + +static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSN.reg; +} + +static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSL.reg; +} + +static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TN.reg; +} + +static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TI.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TI.reg; +} + +static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TA.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GMAC_E54_H_INCLUDED */ +#endif /* _SAME54_GMAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_hmatrixb_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_hmatrixb_e54.h index 2ef0684..153faab 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_hmatrixb_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_hmatrixb_e54.h @@ -1,237 +1,237 @@ -/** - * \file - * - * \brief SAM HMATRIXB - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_HMATRIXB_COMPONENT_ -#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_ -#define _HRI_HMATRIXB_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) -#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define HMATRIXB_CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_hmatrixb_pras_reg_t; -typedef uint32_t hri_hmatrixb_prbs_reg_t; -typedef uint32_t hri_hmatrixbprs_pras_reg_t; -typedef uint32_t hri_hmatrixbprs_prbs_reg_t; - -static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRAS.reg; -} - -static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRBS.reg; -} - -static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; -} - -static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */ -#endif /* _SAME54_HMATRIXB_COMPONENT_ */ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_ +#define _HRI_HMATRIXB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */ +#endif /* _SAME54_HMATRIXB_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_i2s_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_i2s_e54.h index 42b88dc..56daf0d 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_i2s_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_i2s_e54.h @@ -1,3032 +1,3032 @@ -/** - * \file - * - * \brief SAM I2S - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_I2S_COMPONENT_ -#ifndef _HRI_I2S_E54_H_INCLUDED_ -#define _HRI_I2S_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_I2S_CRITICAL_SECTIONS) -#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define I2S_CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_i2s_intenset_reg_t; -typedef uint16_t hri_i2s_intflag_reg_t; -typedef uint16_t hri_i2s_syncbusy_reg_t; -typedef uint32_t hri_i2s_clkctrl_reg_t; -typedef uint32_t hri_i2s_rxctrl_reg_t; -typedef uint32_t hri_i2s_rxdata_reg_t; -typedef uint32_t hri_i2s_txctrl_reg_t; -typedef uint32_t hri_i2s_txdata_reg_t; -typedef uint8_t hri_i2s_ctrla_reg_t; - -static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - while (((I2s *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - return ((I2s *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) -{ - return ((I2s *)hw)->INTFLAG.reg; -} - -static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - ((I2s *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; -} - -static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; -} - -static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; -} - -static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; -} - -static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; -} - -static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; -} - -static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; -} - -static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; -} - -static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; -} - -static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; -} - -static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; -} - -static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; -} - -static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; -} - -static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; -} - -static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; -} - -static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; -} - -static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENSET.reg = mask; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) -{ - return ((I2s *)hw)->INTENSET.reg; -} - -static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) -{ - ((I2s *)hw)->INTENSET.reg = data; - ((I2s *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) -{ - return ((I2s *)hw)->SYNCBUSY.reg; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) -{ - uint32_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->RXDATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return ((I2s *)hw)->RXDATA.reg; -} - -static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_ENABLE; - tmp |= value << I2S_CTRLA_ENABLE_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN0; - tmp |= value << I2S_CTRLA_CKEN0_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN1; - tmp |= value << I2S_CTRLA_CKEN1_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_TXEN; - tmp |= value << I2S_CTRLA_TXEN_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_RXEN; - tmp |= value << I2S_CTRLA_RXEN_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= mask; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg = data; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~mask; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= mask; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); - return ((I2s *)hw)->CTRLA.reg; -} - -static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_BITDELAY; - tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSSEL; - tmp |= value << I2S_CLKCTRL_FSSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSINV; - tmp |= value << I2S_CLKCTRL_FSINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSOUTINV; - tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKSEL; - tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKOUTINV; - tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKSEL; - tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKEN; - tmp |= value << I2S_CLKCTRL_MCKEN_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTINV; - tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; - tmp |= I2S_CLKCTRL_SLOTSIZE(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; - tmp |= I2S_CLKCTRL_NBSLOTS(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; - tmp |= I2S_CLKCTRL_FSWIDTH(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; - tmp |= I2S_CLKCTRL_MCKDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; - tmp |= I2S_CLKCTRL_MCKOUTDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) -{ - return ((I2s *)hw)->CLKCTRL[index].reg; -} - -static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_TXSAME; - tmp |= value << I2S_TXCTRL_TXSAME_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTADJ; - tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_WORDADJ; - tmp |= value << I2S_TXCTRL_WORDADJ_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_BITREV; - tmp |= value << I2S_TXCTRL_BITREV_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS0; - tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS1; - tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS2; - tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS3; - tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS4; - tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS5; - tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS6; - tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS7; - tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_MONO; - tmp |= value << I2S_TXCTRL_MONO_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_DMA; - tmp |= value << I2S_TXCTRL_DMA_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; - tmp |= I2S_TXCTRL_TXDEFAULT(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_DATASIZE_Msk; - tmp |= I2S_TXCTRL_DATASIZE(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_EXTEND_Msk; - tmp |= I2S_TXCTRL_EXTEND(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) -{ - return ((I2s *)hw)->TXCTRL.reg; -} - -static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_CLKSEL; - tmp |= value << I2S_RXCTRL_CLKSEL_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTADJ; - tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_WORDADJ; - tmp |= value << I2S_RXCTRL_WORDADJ_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_BITREV; - tmp |= value << I2S_RXCTRL_BITREV_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS0; - tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS1; - tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS2; - tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS3; - tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS4; - tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS5; - tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS6; - tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS7; - tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_MONO; - tmp |= value << I2S_RXCTRL_MONO_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_DMA; - tmp |= value << I2S_RXCTRL_DMA_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_RXLOOP; - tmp |= value << I2S_RXCTRL_RXLOOP_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SERMODE_Msk; - tmp |= I2S_RXCTRL_SERMODE(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_DATASIZE_Msk; - tmp |= I2S_RXCTRL_DATASIZE(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_EXTEND_Msk; - tmp |= I2S_RXCTRL_EXTEND(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) -{ - return ((I2s *)hw)->RXCTRL.reg; -} - -static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXDATA.reg = data; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - I2S_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_I2S_E54_H_INCLUDED */ -#endif /* _SAME54_I2S_COMPONENT_ */ +/** + * \file + * + * \brief SAM I2S + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_I2S_COMPONENT_ +#ifndef _HRI_I2S_E54_H_INCLUDED_ +#define _HRI_I2S_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2S_CRITICAL_SECTIONS) +#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2S_CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_i2s_intenset_reg_t; +typedef uint16_t hri_i2s_intflag_reg_t; +typedef uint16_t hri_i2s_syncbusy_reg_t; +typedef uint32_t hri_i2s_clkctrl_reg_t; +typedef uint32_t hri_i2s_rxctrl_reg_t; +typedef uint32_t hri_i2s_rxdata_reg_t; +typedef uint32_t hri_i2s_txctrl_reg_t; +typedef uint32_t hri_i2s_txdata_reg_t; +typedef uint8_t hri_i2s_ctrla_reg_t; + +static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + while (((I2s *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + return ((I2s *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) +{ + return ((I2s *)hw)->INTFLAG.reg; +} + +static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + ((I2s *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; +} + +static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; +} + +static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; +} + +static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; +} + +static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; +} + +static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; +} + +static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; +} + +static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; +} + +static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; +} + +static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; +} + +static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; +} + +static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; +} + +static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; +} + +static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; +} + +static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; +} + +static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; +} + +static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENSET.reg = mask; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) +{ + return ((I2s *)hw)->INTENSET.reg; +} + +static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) +{ + ((I2s *)hw)->INTENSET.reg = data; + ((I2s *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) +{ + return ((I2s *)hw)->SYNCBUSY.reg; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + uint32_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return ((I2s *)hw)->RXDATA.reg; +} + +static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_ENABLE; + tmp |= value << I2S_CTRLA_ENABLE_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN0; + tmp |= value << I2S_CTRLA_CKEN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN1; + tmp |= value << I2S_CTRLA_CKEN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_TXEN; + tmp |= value << I2S_CTRLA_TXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_RXEN; + tmp |= value << I2S_CTRLA_RXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + return ((I2s *)hw)->CTRLA.reg; +} + +static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_BITDELAY; + tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSSEL; + tmp |= value << I2S_CLKCTRL_FSSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSINV; + tmp |= value << I2S_CLKCTRL_FSINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSOUTINV; + tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKSEL; + tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKOUTINV; + tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKSEL; + tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKEN; + tmp |= value << I2S_CLKCTRL_MCKEN_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTINV; + tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; + tmp |= I2S_CLKCTRL_SLOTSIZE(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; + tmp |= I2S_CLKCTRL_NBSLOTS(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; + tmp |= I2S_CLKCTRL_FSWIDTH(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; + tmp |= I2S_CLKCTRL_MCKDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; + tmp |= I2S_CLKCTRL_MCKOUTDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->CLKCTRL[index].reg; +} + +static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXSAME; + tmp |= value << I2S_TXCTRL_TXSAME_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTADJ; + tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_WORDADJ; + tmp |= value << I2S_TXCTRL_WORDADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_BITREV; + tmp |= value << I2S_TXCTRL_BITREV_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS0; + tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS1; + tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS2; + tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS3; + tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS4; + tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS5; + tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS6; + tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS7; + tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_MONO; + tmp |= value << I2S_TXCTRL_MONO_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DMA; + tmp |= value << I2S_TXCTRL_DMA_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; + tmp |= I2S_TXCTRL_TXDEFAULT(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DATASIZE_Msk; + tmp |= I2S_TXCTRL_DATASIZE(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_EXTEND_Msk; + tmp |= I2S_TXCTRL_EXTEND(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->TXCTRL.reg; +} + +static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_CLKSEL; + tmp |= value << I2S_RXCTRL_CLKSEL_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTADJ; + tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_WORDADJ; + tmp |= value << I2S_RXCTRL_WORDADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_BITREV; + tmp |= value << I2S_RXCTRL_BITREV_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS0; + tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS1; + tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS2; + tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS3; + tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS4; + tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS5; + tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS6; + tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS7; + tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_MONO; + tmp |= value << I2S_RXCTRL_MONO_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DMA; + tmp |= value << I2S_RXCTRL_DMA_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_RXLOOP; + tmp |= value << I2S_RXCTRL_RXLOOP_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SERMODE_Msk; + tmp |= I2S_RXCTRL_SERMODE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DATASIZE_Msk; + tmp |= I2S_RXCTRL_DATASIZE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_EXTEND_Msk; + tmp |= I2S_RXCTRL_EXTEND(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->RXCTRL.reg; +} + +static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXDATA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2S_E54_H_INCLUDED */ +#endif /* _SAME54_I2S_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_icm_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_icm_e54.h index 374caa4..f8841a1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_icm_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_icm_e54.h @@ -1,761 +1,761 @@ -/** - * \file - * - * \brief SAM ICM - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_ICM_COMPONENT_ -#ifndef _HRI_ICM_E54_H_INCLUDED_ -#define _HRI_ICM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ICM_CRITICAL_SECTIONS) -#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ICM_CRITICAL_SECTION_ENTER() -#define ICM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_icm_cfg_reg_t; -typedef uint32_t hri_icm_ctrl_reg_t; -typedef uint32_t hri_icm_dscr_reg_t; -typedef uint32_t hri_icm_hash_reg_t; -typedef uint32_t hri_icm_imr_reg_t; -typedef uint32_t hri_icm_isr_reg_t; -typedef uint32_t hri_icm_sr_reg_t; -typedef uint32_t hri_icm_uasr_reg_t; -typedef uint32_t hri_icm_uihval_reg_t; -typedef uint32_t hri_icmdescriptor_raddr_reg_t; -typedef uint32_t hri_icmdescriptor_rcfg_reg_t; -typedef uint32_t hri_icmdescriptor_rctrl_reg_t; -typedef uint32_t hri_icmdescriptor_rnext_reg_t; - -static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, - hri_icmdescriptor_raddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RADDR.reg; -} - -static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, - hri_icmdescriptor_rcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RCFG.reg; -} - -static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, - hri_icmdescriptor_rctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RCTRL.reg; -} - -static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, - hri_icmdescriptor_rnext_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RNEXT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RNEXT.reg; -} - -static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_URAD; -} - -static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) -{ - return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; -} - -static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; - } else { - ((Icm *)hw)->IER.reg = ICM_IMR_URAD; - } -} - -static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; -} - -static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); -} - -static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); -} - -static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); -} - -static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); -} - -static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); -} - -static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); -} - -static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); -} - -static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); -} - -static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); -} - -static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); -} - -static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); -} - -static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); -} - -static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = mask; -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) -{ - return ((Icm *)hw)->IMR.reg; -} - -static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = data; - ((Icm *)hw)->IDR.reg = ~data; -} - -static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = mask; -} - -static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->SR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) -{ - return ((Icm *)hw)->SR.reg; -} - -static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) -{ - return ((Icm *)hw)->ISR.reg; -} - -static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) -{ - return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; -} - -static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) -{ - return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; -} - -static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->UASR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) -{ - return ((Icm *)hw)->UASR.reg; -} - -static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) -{ - return ((Icm *)hw)->CFG.reg; -} - -static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->DSCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) -{ - return ((Icm *)hw)->DSCR.reg; -} - -static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->HASH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) -{ - return ((Icm *)hw)->HASH.reg; -} - -static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CTRL.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->UIHVAL[index].reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ICM_E54_H_INCLUDED */ -#endif /* _SAME54_ICM_COMPONENT_ */ +/** + * \file + * + * \brief SAM ICM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ICM_COMPONENT_ +#ifndef _HRI_ICM_E54_H_INCLUDED_ +#define _HRI_ICM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ICM_CRITICAL_SECTIONS) +#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ICM_CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_icm_cfg_reg_t; +typedef uint32_t hri_icm_ctrl_reg_t; +typedef uint32_t hri_icm_dscr_reg_t; +typedef uint32_t hri_icm_hash_reg_t; +typedef uint32_t hri_icm_imr_reg_t; +typedef uint32_t hri_icm_isr_reg_t; +typedef uint32_t hri_icm_sr_reg_t; +typedef uint32_t hri_icm_uasr_reg_t; +typedef uint32_t hri_icm_uihval_reg_t; +typedef uint32_t hri_icmdescriptor_raddr_reg_t; +typedef uint32_t hri_icmdescriptor_rcfg_reg_t; +typedef uint32_t hri_icmdescriptor_rctrl_reg_t; +typedef uint32_t hri_icmdescriptor_rnext_reg_t; + +static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, + hri_icmdescriptor_raddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RADDR.reg; +} + +static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, + hri_icmdescriptor_rcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCFG.reg; +} + +static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, + hri_icmdescriptor_rctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCTRL.reg; +} + +static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, + hri_icmdescriptor_rnext_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RNEXT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RNEXT.reg; +} + +static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; +} + +static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; +} + +static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; + } else { + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; + } +} + +static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; +} + +static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); +} + +static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); +} + +static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); +} + +static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); +} + +static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); +} + +static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); +} + +static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); +} + +static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); +} + +static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); +} + +static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); +} + +static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); +} + +static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); +} + +static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = mask; +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) +{ + return ((Icm *)hw)->IMR.reg; +} + +static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = data; + ((Icm *)hw)->IDR.reg = ~data; +} + +static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = mask; +} + +static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) +{ + return ((Icm *)hw)->SR.reg; +} + +static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) +{ + return ((Icm *)hw)->ISR.reg; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->UASR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) +{ + return ((Icm *)hw)->UASR.reg; +} + +static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) +{ + return ((Icm *)hw)->CFG.reg; +} + +static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->DSCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) +{ + return ((Icm *)hw)->DSCR.reg; +} + +static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->HASH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) +{ + return ((Icm *)hw)->HASH.reg; +} + +static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->UIHVAL[index].reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ICM_E54_H_INCLUDED */ +#endif /* _SAME54_ICM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_mclk_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_mclk_e54.h index 7e3963b..c121789 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_mclk_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_mclk_e54.h @@ -1,3556 +1,3556 @@ -/** - * \file - * - * \brief SAM MCLK - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_MCLK_COMPONENT_ -#ifndef _HRI_MCLK_E54_H_INCLUDED_ -#define _HRI_MCLK_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) -#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define MCLK_CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_mclk_ahbmask_reg_t; -typedef uint32_t hri_mclk_apbamask_reg_t; -typedef uint32_t hri_mclk_apbbmask_reg_t; -typedef uint32_t hri_mclk_apbcmask_reg_t; -typedef uint32_t hri_mclk_apbdmask_reg_t; -typedef uint8_t hri_mclk_cpudiv_reg_t; -typedef uint8_t hri_mclk_hsdiv_reg_t; -typedef uint8_t hri_mclk_intenset_reg_t; -typedef uint8_t hri_mclk_intflag_reg_t; - -static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTFLAG.reg; -} - -static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - ((Mclk *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; -} - -static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; -} - -static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; - } else { - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; - } -} - -static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; -} - -static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENSET.reg = mask; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTENSET.reg; -} - -static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) -{ - ((Mclk *)hw)->INTENSET.reg = data; - ((Mclk *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENCLR.reg = mask; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) -{ - return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) -{ - return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->HSDIV.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->HSDIV.reg; -} - -static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - uint8_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= ~MCLK_CPUDIV_DIV_Msk; - tmp |= MCLK_CPUDIV_DIV(data); - ((Mclk *)hw)->CPUDIV.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; - return tmp; -} - -static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->CPUDIV.reg; -} - -static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB0; - tmp |= value << MCLK_AHBMASK_HPB0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB1; - tmp |= value << MCLK_AHBMASK_HPB1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB2; - tmp |= value << MCLK_AHBMASK_HPB2_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB3; - tmp |= value << MCLK_AHBMASK_HPB3_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DSU; - tmp |= value << MCLK_AHBMASK_DSU_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HMATRIX; - tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL; - tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HSRAM; - tmp |= value << MCLK_AHBMASK_HSRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CMCC; - tmp |= value << MCLK_AHBMASK_CMCC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DMAC; - tmp |= value << MCLK_AHBMASK_DMAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_USB; - tmp |= value << MCLK_AHBMASK_USB_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_BKUPRAM; - tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PAC; - tmp |= value << MCLK_AHBMASK_PAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_QSPI; - tmp |= value << MCLK_AHBMASK_QSPI_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_GMAC; - tmp |= value << MCLK_AHBMASK_GMAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_SDHC0; - tmp |= value << MCLK_AHBMASK_SDHC0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_SDHC1; - tmp |= value << MCLK_AHBMASK_SDHC1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CAN0; - tmp |= value << MCLK_AHBMASK_CAN0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CAN1; - tmp |= value << MCLK_AHBMASK_CAN1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_ICM; - tmp |= value << MCLK_AHBMASK_ICM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PUKCC; - tmp |= value << MCLK_AHBMASK_PUKCC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_QSPI_2X; - tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; - tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; - tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->AHBMASK.reg; -} - -static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PAC; - tmp |= value << MCLK_APBAMASK_PAC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PM; - tmp |= value << MCLK_APBAMASK_PM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_MCLK; - tmp |= value << MCLK_APBAMASK_MCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RSTC; - tmp |= value << MCLK_APBAMASK_RSTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSCCTRL; - tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSC32KCTRL; - tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SUPC; - tmp |= value << MCLK_APBAMASK_SUPC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_GCLK; - tmp |= value << MCLK_APBAMASK_GCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_WDT; - tmp |= value << MCLK_APBAMASK_WDT_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RTC; - tmp |= value << MCLK_APBAMASK_RTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_EIC; - tmp |= value << MCLK_APBAMASK_EIC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_FREQM; - tmp |= value << MCLK_APBAMASK_FREQM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SERCOM0; - tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SERCOM1; - tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_TC0; - tmp |= value << MCLK_APBAMASK_TC0_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_TC1; - tmp |= value << MCLK_APBAMASK_TC1_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBAMASK.reg; -} - -static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_USB; - tmp |= value << MCLK_APBBMASK_USB_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_DSU; - tmp |= value << MCLK_APBBMASK_DSU_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_NVMCTRL; - tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_PORT; - tmp |= value << MCLK_APBBMASK_PORT_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_HMATRIX; - tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_EVSYS; - tmp |= value << MCLK_APBBMASK_EVSYS_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_SERCOM2; - tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_SERCOM3; - tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TCC0; - tmp |= value << MCLK_APBBMASK_TCC0_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TCC1; - tmp |= value << MCLK_APBBMASK_TCC1_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TC2; - tmp |= value << MCLK_APBBMASK_TC2_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TC3; - tmp |= value << MCLK_APBBMASK_TC3_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_RAMECC; - tmp |= value << MCLK_APBBMASK_RAMECC_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBBMASK.reg; -} - -static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_GMAC; - tmp |= value << MCLK_APBCMASK_GMAC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC2; - tmp |= value << MCLK_APBCMASK_TCC2_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC3; - tmp |= value << MCLK_APBCMASK_TCC3_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC4; - tmp |= value << MCLK_APBCMASK_TC4_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC5; - tmp |= value << MCLK_APBCMASK_TC5_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_PDEC; - tmp |= value << MCLK_APBCMASK_PDEC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AC; - tmp |= value << MCLK_APBCMASK_AC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AES; - tmp |= value << MCLK_APBCMASK_AES_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TRNG; - tmp |= value << MCLK_APBCMASK_TRNG_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_ICM; - tmp |= value << MCLK_APBCMASK_ICM_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_QSPI; - tmp |= value << MCLK_APBCMASK_QSPI_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_CCL; - tmp |= value << MCLK_APBCMASK_CCL_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBCMASK.reg; -} - -static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM4; - tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM5; - tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM6; - tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM7; - tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TCC4; - tmp |= value << MCLK_APBDMASK_TCC4_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TC6; - tmp |= value << MCLK_APBDMASK_TC6_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TC7; - tmp |= value << MCLK_APBDMASK_TC7_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_ADC0; - tmp |= value << MCLK_APBDMASK_ADC0_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_ADC1; - tmp |= value << MCLK_APBDMASK_ADC1_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_DAC; - tmp |= value << MCLK_APBDMASK_DAC_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_I2S; - tmp |= value << MCLK_APBDMASK_I2S_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_PCC; - tmp |= value << MCLK_APBDMASK_PCC_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBDMASK.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_MCLK_E54_H_INCLUDED */ -#endif /* _SAME54_MCLK_COMPONENT_ */ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_E54_H_INCLUDED_ +#define _HRI_MCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_hsdiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->HSDIV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->HSDIV.reg; +} + +static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_DIV_Msk; + tmp |= MCLK_CPUDIV_DIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIX; + tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CMCC; + tmp |= value << MCLK_AHBMASK_CMCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_BKUPRAM; + tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI; + tmp |= value << MCLK_AHBMASK_QSPI_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_GMAC; + tmp |= value << MCLK_AHBMASK_GMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC0; + tmp |= value << MCLK_AHBMASK_SDHC0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC1; + tmp |= value << MCLK_AHBMASK_SDHC1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN0; + tmp |= value << MCLK_AHBMASK_CAN0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN1; + tmp |= value << MCLK_AHBMASK_CAN1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_ICM; + tmp |= value << MCLK_AHBMASK_ICM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PUKCC; + tmp |= value << MCLK_AHBMASK_PUKCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI_2X; + tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM0; + tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM1; + tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC0; + tmp |= value << MCLK_APBAMASK_TC0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC1; + tmp |= value << MCLK_APBAMASK_TC1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIX; + tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_EVSYS; + tmp |= value << MCLK_APBBMASK_EVSYS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM2; + tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM3; + tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC0; + tmp |= value << MCLK_APBBMASK_TCC0_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC1; + tmp |= value << MCLK_APBBMASK_TCC1_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC2; + tmp |= value << MCLK_APBBMASK_TC2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC3; + tmp |= value << MCLK_APBBMASK_TC3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_RAMECC; + tmp |= value << MCLK_APBBMASK_RAMECC_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_GMAC; + tmp |= value << MCLK_APBCMASK_GMAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC3; + tmp |= value << MCLK_APBCMASK_TCC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC5; + tmp |= value << MCLK_APBCMASK_TC5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PDEC; + tmp |= value << MCLK_APBCMASK_PDEC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ICM; + tmp |= value << MCLK_APBCMASK_ICM_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_QSPI; + tmp |= value << MCLK_APBCMASK_QSPI_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM4; + tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM6; + tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM7; + tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TCC4; + tmp |= value << MCLK_APBDMASK_TCC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC6; + tmp |= value << MCLK_APBDMASK_TC6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC7; + tmp |= value << MCLK_APBDMASK_TC7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC0; + tmp |= value << MCLK_APBDMASK_ADC0_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC1; + tmp |= value << MCLK_APBDMASK_ADC1_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_DAC; + tmp |= value << MCLK_APBDMASK_DAC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_I2S; + tmp |= value << MCLK_APBDMASK_I2S_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PCC; + tmp |= value << MCLK_APBDMASK_PCC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_E54_H_INCLUDED */ +#endif /* _SAME54_MCLK_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_nvmctrl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_nvmctrl_e54.h index 12d4022..a0f5963 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_nvmctrl_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_nvmctrl_e54.h @@ -1,1618 +1,1618 @@ -/** - * \file - * - * \brief SAM NVMCTRL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_NVMCTRL_COMPONENT_ -#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ -#define _HRI_NVMCTRL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) -#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVMCTRL_CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_nvmctrl_ctrla_reg_t; -typedef uint16_t hri_nvmctrl_ctrlb_reg_t; -typedef uint16_t hri_nvmctrl_intenset_reg_t; -typedef uint16_t hri_nvmctrl_intflag_reg_t; -typedef uint16_t hri_nvmctrl_status_reg_t; -typedef uint32_t hri_nvmctrl_addr_reg_t; -typedef uint32_t hri_nvmctrl_eccerr_reg_t; -typedef uint32_t hri_nvmctrl_param_reg_t; -typedef uint32_t hri_nvmctrl_pbldata_reg_t; -typedef uint32_t hri_nvmctrl_runlock_reg_t; -typedef uint32_t hri_nvmctrl_seestat_reg_t; -typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; -typedef uint8_t hri_nvmctrl_seecfg_reg_t; - -static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; -} - -static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; -} - -static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; -} - -static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; -} - -static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; -} - -static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; -} - -static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; -} - -static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; -} - -static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; -} - -static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; -} - -static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; -} - -static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, - hri_nvmctrl_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; -} - -static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; -} - -static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; -} - -static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; -} - -static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; -} - -static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; -} - -static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; -} - -static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; -} - -static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; -} - -static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; -} - -static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; -} - -static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; -} - -static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; -} - -static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; - } -} - -static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; -} - -static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; -} - -static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; -} - -static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; -} - -static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; -} - -static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; -} - -static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; -} - -static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; -} - -static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; -} - -static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, - hri_nvmctrl_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTENSET.reg; -} - -static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) -{ - ((Nvmctrl *)hw)->INTENSET.reg = data; - ((Nvmctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->PARAM.reg; -} - -static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, - hri_nvmctrl_status_reg_t mask) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->STATUS.reg; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, - hri_nvmctrl_runlock_reg_t mask) -{ - return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, - hri_nvmctrl_runlock_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->RUNLOCK.reg; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, - hri_nvmctrl_pbldata_reg_t mask) -{ - return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) -{ - return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, - hri_nvmctrl_pbldata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) -{ - return ((Nvmctrl *)hw)->PBLDATA[index].reg; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ECCERR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ECCERR.reg; -} - -static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->SEESTAT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->SEESTAT.reg; -} - -static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AUTOWS; - tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_SUSPEN; - tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AHBNS0; - tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AHBNS1; - tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; - tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; - tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; - tmp |= NVMCTRL_CTRLA_WMODE(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_PRM_Msk; - tmp |= NVMCTRL_CTRLA_PRM(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_RWS_Msk; - tmp |= NVMCTRL_CTRLA_RWS(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLA.reg; -} - -static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= ~NVMCTRL_ADDR_ADDR_Msk; - tmp |= NVMCTRL_ADDR_ADDR(data); - ((Nvmctrl *)hw)->ADDR.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ADDR.reg; -} - -static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; - tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; - ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; - tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; - ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, - hri_nvmctrl_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->DBGCTRL.reg; -} - -static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= ~NVMCTRL_SEECFG_WMODE; - tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; - ((Nvmctrl *)hw)->SEECFG.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= ~NVMCTRL_SEECFG_APRDIS; - tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; - ((Nvmctrl *)hw)->SEECFG.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->SEECFG.reg; -} - -static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ -#endif /* _SAME54_NVMCTRL_COMPONENT_ */ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ +#define _HRI_NVMCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_ctrlb_reg_t; +typedef uint16_t hri_nvmctrl_intenset_reg_t; +typedef uint16_t hri_nvmctrl_intflag_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_eccerr_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata_reg_t; +typedef uint32_t hri_nvmctrl_runlock_reg_t; +typedef uint32_t hri_nvmctrl_seestat_reg_t; +typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; +typedef uint8_t hri_nvmctrl_seecfg_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; +} + +static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; +} + +static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; +} + +static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; + } +} + +static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; +} + +static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, + hri_nvmctrl_status_reg_t mask) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->RUNLOCK.reg; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) +{ + return ((Nvmctrl *)hw)->PBLDATA[index].reg; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ECCERR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ECCERR.reg; +} + +static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->SEESTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEESTAT.reg; +} + +static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AUTOWS; + tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_SUSPEN; + tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS0; + tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS1; + tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; + tmp |= NVMCTRL_CTRLA_WMODE(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_PRM_Msk; + tmp |= NVMCTRL_CTRLA_PRM(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_RWS_Msk; + tmp |= NVMCTRL_CTRLA_RWS(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; + tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; + tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, + hri_nvmctrl_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->DBGCTRL.reg; +} + +static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_WMODE; + tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_APRDIS; + tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEECFG.reg; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_NVMCTRL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_osc32kctrl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_osc32kctrl_e54.h index 2eabbca..c33846b 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_osc32kctrl_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_osc32kctrl_e54.h @@ -1,1199 +1,1199 @@ -/** - * \file - * - * \brief SAM OSC32KCTRL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_OSC32KCTRL_COMPONENT_ -#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ -#define _HRI_OSC32KCTRL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; -typedef uint32_t hri_osc32kctrl_intenset_reg_t; -typedef uint32_t hri_osc32kctrl_intflag_reg_t; -typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; -typedef uint32_t hri_osc32kctrl_status_reg_t; -typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; -typedef uint8_t hri_osc32kctrl_evctrl_reg_t; -typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, - hri_osc32kctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; -} - -static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, - hri_osc32kctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTENSET.reg; -} - -static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = data; - ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, - hri_osc32kctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->STATUS.reg; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; - tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); - ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->RTCCTRL.reg; -} - -static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; - tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; - tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN32K; - tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN1K; - tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; - tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; - tmp |= OSC32KCTRL_XOSC32K_CGM(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->XOSC32K.reg; -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; - tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, - hri_osc32kctrl_cfdctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->CFDCTRL.reg; -} - -static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; - tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; - ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, - hri_osc32kctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; - tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->OSCULP32K.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ -#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ +#define _HRI_OSC32KCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; +typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; + tmp |= OSC32KCTRL_XOSC32K_CGM(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_oscctrl_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_oscctrl_e54.h index f331410..4b81e12 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_oscctrl_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_oscctrl_e54.h @@ -1,4441 +1,4441 @@ -/** - * \file - * - * \brief SAM OSCCTRL - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_OSCCTRL_COMPONENT_ -#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ -#define _HRI_OSCCTRL_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) -#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSCCTRL_CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_oscctrl_dfllmul_reg_t; -typedef uint32_t hri_oscctrl_dfllval_reg_t; -typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrl_dpllratio_reg_t; -typedef uint32_t hri_oscctrl_dpllstatus_reg_t; -typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; -typedef uint32_t hri_oscctrl_intenset_reg_t; -typedef uint32_t hri_oscctrl_intflag_reg_t; -typedef uint32_t hri_oscctrl_status_reg_t; -typedef uint32_t hri_oscctrl_xoscctrl_reg_t; -typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; -typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; -typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; -typedef uint8_t hri_oscctrl_dfllctrla_reg_t; -typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; -typedef uint8_t hri_oscctrl_dfllsync_reg_t; -typedef uint8_t hri_oscctrl_dpllctrla_reg_t; -typedef uint8_t hri_oscctrl_evctrl_reg_t; -typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; - -static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; -} - -static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllsyncbusy_reg_t reg) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; -} - -static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) - >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, - hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) -{ - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) -{ - hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); - return ((OscctrlDpll *)hw)->DPLLRATIO.reg; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; - tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) - >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) - >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t -hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) - >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) - >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t -hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t -hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) -{ - hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; - tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, - hri_oscctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) -{ - ((Oscctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; -} - -static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, - hri_oscctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTENSET.reg; -} - -static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) -{ - ((Oscctrl *)hw)->INTENSET.reg = data; - ((Oscctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->STATUS.reg; -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO0; - tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO1; - tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; - tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; - tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; - tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENALC; - tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; - tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; - tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; - tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; - tmp |= OSCCTRL_XOSCCTRL_IMULT(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; - tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; - tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Oscctrl *)hw)->XOSCCTRL[index].reg; -} - -static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, - hri_oscctrl_dfllctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_MODE; - tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; - tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; - tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; - tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; - tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; - tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; - tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; - tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, - hri_oscctrl_dfllctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLCTRLB.reg; -} - -static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; - tmp |= OSCCTRL_DFLLVAL_FINE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; - tmp |= OSCCTRL_DFLLVAL_COARSE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; - tmp |= OSCCTRL_DFLLVAL_DIFF(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLVAL.reg; -} - -static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; - tmp |= OSCCTRL_DFLLMUL_MUL(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_FSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_CSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLMUL.reg; -} - -static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; - tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, - hri_oscctrl_dfllsync_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLSYNC.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ -#endif /* _SAME54_OSCCTRL_COMPONENT_ */ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ +#define _HRI_OSCCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_dpllstatus_reg_t; +typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint32_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; +typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; +typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_dfllctrla_reg_t; +typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; + +static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((OscctrlDpll *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) + >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t +hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) + >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) + >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO0; + tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO1; + tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENALC; + tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IMULT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; + tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Oscctrl *)hw)->XOSCCTRL[index].reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, + hri_oscctrl_dfllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_MODE; + tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; + tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; + tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, + hri_oscctrl_dfllctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; + tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSCCTRL_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pac_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pac_e54.h index 8963135..5f331c9 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pac_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pac_e54.h @@ -1,1514 +1,1514 @@ -/** - * \file - * - * \brief SAM PAC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PAC_COMPONENT_ -#ifndef _HRI_PAC_E54_H_INCLUDED_ -#define _HRI_PAC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PAC_CRITICAL_SECTIONS) -#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PAC_CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pac_intflaga_reg_t; -typedef uint32_t hri_pac_intflagahb_reg_t; -typedef uint32_t hri_pac_intflagb_reg_t; -typedef uint32_t hri_pac_intflagc_reg_t; -typedef uint32_t hri_pac_intflagd_reg_t; -typedef uint32_t hri_pac_statusa_reg_t; -typedef uint32_t hri_pac_statusb_reg_t; -typedef uint32_t hri_pac_statusc_reg_t; -typedef uint32_t hri_pac_statusd_reg_t; -typedef uint32_t hri_pac_wrctrl_reg_t; -typedef uint8_t hri_pac_evctrl_reg_t; -typedef uint8_t hri_pac_intenset_reg_t; - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; -} - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; -} - -static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; -} - -static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; -} - -static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; -} - -static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; -} - -static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; -} - -static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGAHB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGAHB.reg; -} - -static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGAHB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; -} - -static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; -} - -static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; -} - -static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; -} - -static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; -} - -static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; -} - -static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; -} - -static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; -} - -static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; -} - -static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; -} - -static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; -} - -static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; -} - -static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; -} - -static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; -} - -static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGA.reg; -} - -static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - ((Pac *)hw)->INTFLAGA.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; -} - -static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; -} - -static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; -} - -static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; -} - -static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; -} - -static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; -} - -static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; -} - -static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; -} - -static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; -} - -static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; -} - -static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; -} - -static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; -} - -static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; -} - -static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; -} - -static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; -} - -static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGB.reg; -} - -static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; -} - -static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; -} - -static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; -} - -static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; -} - -static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; -} - -static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; -} - -static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; -} - -static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; -} - -static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; -} - -static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; -} - -static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; -} - -static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; -} - -static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; -} - -static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; -} - -static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; -} - -static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGC.reg; -} - -static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - ((Pac *)hw)->INTFLAGC.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; -} - -static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; -} - -static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; -} - -static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; -} - -static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; -} - -static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; -} - -static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; -} - -static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; -} - -static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; -} - -static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGD.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGD.reg; -} - -static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) -{ - ((Pac *)hw)->INTFLAGD.reg = mask; -} - -static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; -} - -static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; -} - -static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; - } else { - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; - } -} - -static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; -} - -static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENSET.reg = mask; -} - -static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) -{ - return ((Pac *)hw)->INTENSET.reg; -} - -static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) -{ - ((Pac *)hw)->INTENSET.reg = data; - ((Pac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; -} - -static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; -} - -static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; -} - -static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; -} - -static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; -} - -static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; -} - -static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; -} - -static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; -} - -static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; -} - -static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; -} - -static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSA.reg; -} - -static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; -} - -static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; -} - -static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; -} - -static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; -} - -static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; -} - -static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; -} - -static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; -} - -static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; -} - -static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; -} - -static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; -} - -static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; -} - -static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; -} - -static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; -} - -static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; -} - -static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSB.reg; -} - -static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; -} - -static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; -} - -static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; -} - -static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; -} - -static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; -} - -static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; -} - -static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; -} - -static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; -} - -static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; -} - -static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; -} - -static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; -} - -static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSC.reg; -} - -static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; -} - -static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; -} - -static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; -} - -static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; -} - -static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; -} - -static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; -} - -static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; -} - -static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; -} - -static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; -} - -static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSD.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSD.reg; -} - -static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_PERID_Msk; - tmp |= PAC_WRCTRL_PERID(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_KEY_Msk; - tmp |= PAC_WRCTRL_KEY(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->WRCTRL.reg; -} - -static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= ~PAC_EVCTRL_ERREO; - tmp |= value << PAC_EVCTRL_ERREO_Pos; - ((Pac *)hw)->EVCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->EVCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PAC_E54_H_INCLUDED */ -#endif /* _SAME54_PAC_COMPONENT_ */ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PAC_COMPONENT_ +#ifndef _HRI_PAC_E54_H_INCLUDED_ +#define _HRI_PAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; +} + +static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; +} + +static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; +} + +static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; +} + +static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; +} + +static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; +} + +static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; +} + +static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; +} + +static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; +} + +static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; +} + +static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; +} + +static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; +} + +static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; +} + +static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; +} + +static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; +} + +static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; +} + +static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; +} + +static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; +} + +static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; +} + +static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; +} + +static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; +} + +static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; +} + +static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; +} + +static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; +} + +static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; +} + +static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; +} + +static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; +} + +static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; +} + +static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_E54_H_INCLUDED */ +#endif /* _SAME54_PAC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pcc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pcc_e54.h index 42a5600..0bc8a24 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pcc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pcc_e54.h @@ -1,298 +1,298 @@ -/** - * \file - * - * \brief SAM PCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PCC_COMPONENT_ -#ifndef _HRI_PCC_E54_H_INCLUDED_ -#define _HRI_PCC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PCC_CRITICAL_SECTIONS) -#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PCC_CRITICAL_SECTION_ENTER() -#define PCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pcc_imr_reg_t; -typedef uint32_t hri_pcc_isr_reg_t; -typedef uint32_t hri_pcc_mr_reg_t; -typedef uint32_t hri_pcc_rhr_reg_t; -typedef uint32_t hri_pcc_wpmr_reg_t; -typedef uint32_t hri_pcc_wpsr_reg_t; - -static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) -{ - ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; -} - -static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) -{ - return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; -} - -static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; - } else { - ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; - } -} - -static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) -{ - ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; -} - -static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) -{ - ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; -} - -static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) -{ - return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; -} - -static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; - } else { - ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; - } -} - -static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) -{ - ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; -} - -static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - ((Pcc *)hw)->IER.reg = mask; -} - -static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) -{ - return ((Pcc *)hw)->IMR.reg; -} - -static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) -{ - ((Pcc *)hw)->IER.reg = data; - ((Pcc *)hw)->IDR.reg = ~data; -} - -static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - ((Pcc *)hw)->IDR.reg = mask; -} - -static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) -{ - return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; -} - -static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) -{ - return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; -} - -static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) -{ - return ((Pcc *)hw)->ISR.reg; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) -{ - return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) -{ - return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->RHR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) -{ - return ((Pcc *)hw)->RHR.reg; -} - -static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->WPSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) -{ - return ((Pcc *)hw)->WPSR.reg; -} - -static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg |= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->MR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg = data; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg &= ~mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg ^= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) -{ - return ((Pcc *)hw)->MR.reg; -} - -static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg |= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->WPMR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg = data; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg &= ~mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg ^= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) -{ - return ((Pcc *)hw)->WPMR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PCC_E54_H_INCLUDED */ -#endif /* _SAME54_PCC_COMPONENT_ */ +/** + * \file + * + * \brief SAM PCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PCC_COMPONENT_ +#ifndef _HRI_PCC_E54_H_INCLUDED_ +#define _HRI_PCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PCC_CRITICAL_SECTIONS) +#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PCC_CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pcc_imr_reg_t; +typedef uint32_t hri_pcc_isr_reg_t; +typedef uint32_t hri_pcc_mr_reg_t; +typedef uint32_t hri_pcc_rhr_reg_t; +typedef uint32_t hri_pcc_wpmr_reg_t; +typedef uint32_t hri_pcc_wpsr_reg_t; + +static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; +} + +static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; +} + +static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; + } +} + +static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; +} + +static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; +} + +static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; +} + +static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; + } +} + +static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; +} + +static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IER.reg = mask; +} + +static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->IMR.reg; +} + +static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) +{ + ((Pcc *)hw)->IER.reg = data; + ((Pcc *)hw)->IDR.reg = ~data; +} + +static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IDR.reg = mask; +} + +static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; +} + +static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; +} + +static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) +{ + return ((Pcc *)hw)->ISR.reg; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->RHR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) +{ + return ((Pcc *)hw)->RHR.reg; +} + +static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPSR.reg; +} + +static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->MR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) +{ + return ((Pcc *)hw)->MR.reg; +} + +static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPMR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PCC_E54_H_INCLUDED */ +#endif /* _SAME54_PCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pdec_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pdec_e54.h index ec7ce30..e31c8cb 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pdec_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pdec_e54.h @@ -1,2684 +1,2684 @@ -/** - * \file - * - * \brief SAM PDEC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PDEC_COMPONENT_ -#ifndef _HRI_PDEC_E54_H_INCLUDED_ -#define _HRI_PDEC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) -#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PDEC_CRITICAL_SECTION_ENTER() -#define PDEC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_pdec_evctrl_reg_t; -typedef uint16_t hri_pdec_status_reg_t; -typedef uint32_t hri_pdec_cc_reg_t; -typedef uint32_t hri_pdec_ccbuf_reg_t; -typedef uint32_t hri_pdec_count_reg_t; -typedef uint32_t hri_pdec_ctrla_reg_t; -typedef uint32_t hri_pdec_syncbusy_reg_t; -typedef uint8_t hri_pdec_ctrlbset_reg_t; -typedef uint8_t hri_pdec_dbgctrl_reg_t; -typedef uint8_t hri_pdec_filter_reg_t; -typedef uint8_t hri_pdec_filterbuf_reg_t; -typedef uint8_t hri_pdec_intenset_reg_t; -typedef uint8_t hri_pdec_intflag_reg_t; -typedef uint8_t hri_pdec_presc_reg_t; -typedef uint8_t hri_pdec_prescbuf_reg_t; - -static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) -{ - while (((Pdec *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) -{ - return ((Pdec *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; -} - -static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; -} - -static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; -} - -static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; -} - -static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; -} - -static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; -} - -static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; -} - -static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; -} - -static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; -} - -static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; -} - -static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; -} - -static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; -} - -static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; -} - -static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; -} - -static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; -} - -static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; -} - -static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; -} - -static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; -} - -static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) -{ - return ((Pdec *)hw)->INTFLAG.reg; -} - -static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) -{ - ((Pdec *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; -} - -static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; - } else { - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; - } -} - -static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; -} - -static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); - ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); -} - -static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); -} - -static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) -{ - return ((Pdec *)hw)->CTRLBSET.reg; -} - -static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) -{ - ((Pdec *)hw)->CTRLBSET.reg = data; - ((Pdec *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; -} - -static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; -} - -static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; - } -} - -static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; -} - -static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; -} - -static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; -} - -static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; - } -} - -static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; -} - -static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; -} - -static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; -} - -static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; - } -} - -static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; -} - -static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; -} - -static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; -} - -static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; - } -} - -static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; -} - -static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; -} - -static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; -} - -static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; - } -} - -static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; -} - -static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; -} - -static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; -} - -static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; - } -} - -static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; -} - -static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - ((Pdec *)hw)->INTENSET.reg = mask; -} - -static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) -{ - return ((Pdec *)hw)->INTENSET.reg; -} - -static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) -{ - ((Pdec *)hw)->INTENSET.reg = data; - ((Pdec *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - ((Pdec *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; -} - -static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Pdec *)hw)->SYNCBUSY.reg; -} - -static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ENABLE; - tmp |= value << PDEC_CTRLA_ENABLE_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_RUNSTDBY; - tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ALOCK; - tmp |= value << PDEC_CTRLA_ALOCK_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_SWAP; - tmp |= value << PDEC_CTRLA_SWAP_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PEREN; - tmp |= value << PDEC_CTRLA_PEREN_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN0; - tmp |= value << PDEC_CTRLA_PINEN0_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN1; - tmp |= value << PDEC_CTRLA_PINEN1_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN2; - tmp |= value << PDEC_CTRLA_PINEN2_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN0; - tmp |= value << PDEC_CTRLA_PINVEN0_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN1; - tmp |= value << PDEC_CTRLA_PINVEN1_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN2; - tmp |= value << PDEC_CTRLA_PINVEN2_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_MODE_Msk; - tmp |= PDEC_CTRLA_MODE(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_CONF_Msk; - tmp |= PDEC_CTRLA_CONF(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ANGULAR_Msk; - tmp |= PDEC_CTRLA_ANGULAR(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_MAXCMP_Msk; - tmp |= PDEC_CTRLA_MAXCMP(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - return ((Pdec *)hw)->CTRLA.reg; -} - -static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_OVFEO; - tmp |= value << PDEC_EVCTRL_OVFEO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_ERREO; - tmp |= value << PDEC_EVCTRL_ERREO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_DIREO; - tmp |= value << PDEC_EVCTRL_DIREO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_VLCEO; - tmp |= value << PDEC_EVCTRL_VLCEO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_MCEO0; - tmp |= value << PDEC_EVCTRL_MCEO0_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_MCEO1; - tmp |= value << PDEC_EVCTRL_MCEO1_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVACT_Msk; - tmp |= PDEC_EVCTRL_EVACT(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVINV_Msk; - tmp |= PDEC_EVCTRL_EVINV(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVEI_Msk; - tmp |= PDEC_EVCTRL_EVEI(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) -{ - return ((Pdec *)hw)->EVCTRL.reg; -} - -static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp &= ~PDEC_DBGCTRL_DBGRUN; - tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; - ((Pdec *)hw)->DBGCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) -{ - return ((Pdec *)hw)->DBGCTRL.reg; -} - -static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp &= ~PDEC_PRESC_PRESC_Msk; - tmp |= PDEC_PRESC_PRESC(data); - ((Pdec *)hw)->PRESC.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - return ((Pdec *)hw)->PRESC.reg; -} - -static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; - return tmp; -} - -static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp &= ~PDEC_FILTER_FILTER_Msk; - tmp |= PDEC_FILTER_FILTER(data); - ((Pdec *)hw)->FILTER.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; - return tmp; -} - -static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - return ((Pdec *)hw)->FILTER.reg; -} - -static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, - hri_pdec_prescbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; - tmp |= PDEC_PRESCBUF_PRESCBUF(data); - ((Pdec *)hw)->PRESCBUF.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->PRESCBUF.reg; -} - -static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, - hri_pdec_filterbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; - tmp |= PDEC_FILTERBUF_FILTERBUF(data); - ((Pdec *)hw)->FILTERBUF.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->FILTERBUF.reg; -} - -static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp &= ~PDEC_COUNT_COUNT_Msk; - tmp |= PDEC_COUNT_COUNT(data); - ((Pdec *)hw)->COUNT.reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - return ((Pdec *)hw)->COUNT.reg; -} - -static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; - return tmp; -} - -static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp &= ~PDEC_CC_CC_Msk; - tmp |= PDEC_CC_CC(data); - ((Pdec *)hw)->CC[index].reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; - return tmp; -} - -static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); - return ((Pdec *)hw)->CC[index].reg; -} - -static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_pdec_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp &= ~PDEC_CCBUF_CCBUF_Msk; - tmp |= PDEC_CCBUF_CCBUF(data); - ((Pdec *)hw)->CCBUF[index].reg = tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg |= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_pdec_ccbuf_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg = data; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg &= ~mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg ^= mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->CCBUF[index].reg; -} - -static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; -} - -static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; -} - -static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; -} - -static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; -} - -static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) -{ - uint16_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = mask; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return ((Pdec *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PDEC_E54_H_INCLUDED */ -#endif /* _SAME54_PDEC_COMPONENT_ */ +/** + * \file + * + * \brief SAM PDEC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PDEC_COMPONENT_ +#ifndef _HRI_PDEC_E54_H_INCLUDED_ +#define _HRI_PDEC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) +#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PDEC_CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pdec_evctrl_reg_t; +typedef uint16_t hri_pdec_status_reg_t; +typedef uint32_t hri_pdec_cc_reg_t; +typedef uint32_t hri_pdec_ccbuf_reg_t; +typedef uint32_t hri_pdec_count_reg_t; +typedef uint32_t hri_pdec_ctrla_reg_t; +typedef uint32_t hri_pdec_syncbusy_reg_t; +typedef uint8_t hri_pdec_ctrlbset_reg_t; +typedef uint8_t hri_pdec_dbgctrl_reg_t; +typedef uint8_t hri_pdec_filter_reg_t; +typedef uint8_t hri_pdec_filterbuf_reg_t; +typedef uint8_t hri_pdec_intenset_reg_t; +typedef uint8_t hri_pdec_intflag_reg_t; +typedef uint8_t hri_pdec_presc_reg_t; +typedef uint8_t hri_pdec_prescbuf_reg_t; + +static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + while (((Pdec *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + return ((Pdec *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTFLAG.reg; +} + +static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + ((Pdec *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; +} + +static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; + } else { + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; + } +} + +static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; +} + +static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); + ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); +} + +static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) +{ + return ((Pdec *)hw)->CTRLBSET.reg; +} + +static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = data; + ((Pdec *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; +} + +static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; +} + +static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; + } +} + +static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; +} + +static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; +} + +static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; +} + +static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; + } +} + +static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; +} + +static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; +} + +static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; +} + +static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; + } +} + +static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; +} + +static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; +} + +static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; +} + +static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; + } +} + +static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; +} + +static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; +} + +static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; +} + +static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; + } +} + +static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; +} + +static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; +} + +static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; +} + +static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; + } +} + +static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; +} + +static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENSET.reg = mask; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTENSET.reg; +} + +static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) +{ + ((Pdec *)hw)->INTENSET.reg = data; + ((Pdec *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Pdec *)hw)->SYNCBUSY.reg; +} + +static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ENABLE; + tmp |= value << PDEC_CTRLA_ENABLE_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_RUNSTDBY; + tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ALOCK; + tmp |= value << PDEC_CTRLA_ALOCK_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_SWAP; + tmp |= value << PDEC_CTRLA_SWAP_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PEREN; + tmp |= value << PDEC_CTRLA_PEREN_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN0; + tmp |= value << PDEC_CTRLA_PINEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN1; + tmp |= value << PDEC_CTRLA_PINEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN2; + tmp |= value << PDEC_CTRLA_PINEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN0; + tmp |= value << PDEC_CTRLA_PINVEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN1; + tmp |= value << PDEC_CTRLA_PINVEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN2; + tmp |= value << PDEC_CTRLA_PINVEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MODE_Msk; + tmp |= PDEC_CTRLA_MODE(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_CONF_Msk; + tmp |= PDEC_CTRLA_CONF(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ANGULAR_Msk; + tmp |= PDEC_CTRLA_ANGULAR(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MAXCMP_Msk; + tmp |= PDEC_CTRLA_MAXCMP(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + return ((Pdec *)hw)->CTRLA.reg; +} + +static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_OVFEO; + tmp |= value << PDEC_EVCTRL_OVFEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_ERREO; + tmp |= value << PDEC_EVCTRL_ERREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_DIREO; + tmp |= value << PDEC_EVCTRL_DIREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_VLCEO; + tmp |= value << PDEC_EVCTRL_VLCEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO0; + tmp |= value << PDEC_EVCTRL_MCEO0_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO1; + tmp |= value << PDEC_EVCTRL_MCEO1_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVACT_Msk; + tmp |= PDEC_EVCTRL_EVACT(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVINV_Msk; + tmp |= PDEC_EVCTRL_EVINV(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVEI_Msk; + tmp |= PDEC_EVCTRL_EVEI(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->EVCTRL.reg; +} + +static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= ~PDEC_DBGCTRL_DBGRUN; + tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; + ((Pdec *)hw)->DBGCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->DBGCTRL.reg; +} + +static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= ~PDEC_PRESC_PRESC_Msk; + tmp |= PDEC_PRESC_PRESC(data); + ((Pdec *)hw)->PRESC.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + return ((Pdec *)hw)->PRESC.reg; +} + +static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= ~PDEC_FILTER_FILTER_Msk; + tmp |= PDEC_FILTER_FILTER(data); + ((Pdec *)hw)->FILTER.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + return ((Pdec *)hw)->FILTER.reg; +} + +static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, + hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; + tmp |= PDEC_PRESCBUF_PRESCBUF(data); + ((Pdec *)hw)->PRESCBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->PRESCBUF.reg; +} + +static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, + hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; + tmp |= PDEC_FILTERBUF_FILTERBUF(data); + ((Pdec *)hw)->FILTERBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->FILTERBUF.reg; +} + +static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= ~PDEC_COUNT_COUNT_Msk; + tmp |= PDEC_COUNT_COUNT(data); + ((Pdec *)hw)->COUNT.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + return ((Pdec *)hw)->COUNT.reg; +} + +static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= ~PDEC_CC_CC_Msk; + tmp |= PDEC_CC_CC(data); + ((Pdec *)hw)->CC[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + return ((Pdec *)hw)->CC[index].reg; +} + +static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= ~PDEC_CCBUF_CCBUF_Msk; + tmp |= PDEC_CCBUF_CCBUF(data); + ((Pdec *)hw)->CCBUF[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->CCBUF[index].reg; +} + +static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; +} + +static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; +} + +static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + uint16_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PDEC_E54_H_INCLUDED */ +#endif /* _SAME54_PDEC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pm_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pm_e54.h index 0b91bee..a329673 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pm_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_pm_e54.h @@ -1,820 +1,820 @@ -/** - * \file - * - * \brief SAM PM - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PM_COMPONENT_ -#ifndef _HRI_PM_E54_H_INCLUDED_ -#define _HRI_PM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PM_CRITICAL_SECTIONS) -#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PM_CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_pm_bkupcfg_reg_t; -typedef uint8_t hri_pm_ctrla_reg_t; -typedef uint8_t hri_pm_hibcfg_reg_t; -typedef uint8_t hri_pm_intenset_reg_t; -typedef uint8_t hri_pm_intflag_reg_t; -typedef uint8_t hri_pm_pwsakdly_reg_t; -typedef uint8_t hri_pm_sleepcfg_reg_t; -typedef uint8_t hri_pm_stdbycfg_reg_t; - -static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; -} - -static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; -} - -static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; -} - -static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; -} - -static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) -{ - return ((Pm *)hw)->INTFLAG.reg; -} - -static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - ((Pm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; -} - -static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; -} - -static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; - } else { - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; - } -} - -static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; -} - -static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENSET.reg = mask; -} - -static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) -{ - return ((Pm *)hw)->INTENSET.reg; -} - -static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) -{ - ((Pm *)hw)->INTENSET.reg = data; - ((Pm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= ~PM_CTRLA_IORET; - tmp |= value << PM_CTRLA_IORET_Pos; - ((Pm *)hw)->CTRLA.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) -{ - return ((Pm *)hw)->CTRLA.reg; -} - -static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; - tmp |= PM_SLEEPCFG_SLEEPMODE(data); - ((Pm *)hw)->SLEEPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->SLEEPCFG.reg; -} - -static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_RAMCFG_Msk; - tmp |= PM_STDBYCFG_RAMCFG(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; - tmp |= PM_STDBYCFG_FASTWKUP(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->STDBYCFG.reg; -} - -static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= ~PM_HIBCFG_RAMCFG_Msk; - tmp |= PM_HIBCFG_RAMCFG(data); - ((Pm *)hw)->HIBCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= ~PM_HIBCFG_BRAMCFG_Msk; - tmp |= PM_HIBCFG_BRAMCFG(data); - ((Pm *)hw)->HIBCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->HIBCFG.reg; -} - -static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; - tmp |= PM_BKUPCFG_BRAMCFG(data); - ((Pm *)hw)->BKUPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->BKUPCFG.reg; -} - -static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= ~PM_PWSAKDLY_IGNACK; - tmp |= value << PM_PWSAKDLY_IGNACK_Pos; - ((Pm *)hw)->PWSAKDLY.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; - return tmp; -} - -static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; - tmp |= PM_PWSAKDLY_DLYVAL(data); - ((Pm *)hw)->PWSAKDLY.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; - return tmp; -} - -static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) -{ - return ((Pm *)hw)->PWSAKDLY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PM_E54_H_INCLUDED */ -#endif /* _SAME54_PM_COMPONENT_ */ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PM_COMPONENT_ +#ifndef _HRI_PM_E54_H_INCLUDED_ +#define _HRI_PM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_pm_bkupcfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_hibcfg_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; +typedef uint8_t hri_pm_stdbycfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; +} + +static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; +} + +static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; + } +} + +static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_RAMCFG_Msk; + tmp |= PM_STDBYCFG_RAMCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; + tmp |= PM_STDBYCFG_FASTWKUP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_RAMCFG_Msk; + tmp |= PM_HIBCFG_RAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_BRAMCFG_Msk; + tmp |= PM_HIBCFG_BRAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->HIBCFG.reg; +} + +static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; + tmp |= PM_BKUPCFG_BRAMCFG(data); + ((Pm *)hw)->BKUPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->BKUPCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_E54_H_INCLUDED */ +#endif /* _SAME54_PM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_port_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_port_e54.h index 261fcf5..5fef4e3 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_port_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_port_e54.h @@ -1,2528 +1,2528 @@ -/** - * \file - * - * \brief SAM PORT - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_PORT_COMPONENT_ -#ifndef _HRI_PORT_E54_H_INCLUDED_ -#define _HRI_PORT_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PORT_CRITICAL_SECTIONS) -#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PORT_CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_port_ctrl_reg_t; -typedef uint32_t hri_port_dir_reg_t; -typedef uint32_t hri_port_evctrl_reg_t; -typedef uint32_t hri_port_in_reg_t; -typedef uint32_t hri_port_out_reg_t; -typedef uint32_t hri_port_wrconfig_reg_t; -typedef uint32_t hri_portgroup_ctrl_reg_t; -typedef uint32_t hri_portgroup_dir_reg_t; -typedef uint32_t hri_portgroup_evctrl_reg_t; -typedef uint32_t hri_portgroup_in_reg_t; -typedef uint32_t hri_portgroup_out_reg_t; -typedef uint32_t hri_portgroup_wrconfig_reg_t; -typedef uint8_t hri_port_pincfg_reg_t; -typedef uint8_t hri_port_pmux_reg_t; -typedef uint8_t hri_portgroup_pincfg_reg_t; -typedef uint8_t hri_portgroup_pmux_reg_t; - -static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); - ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) -{ - return ((PortGroup *)hw)->DIR.reg; -} - -static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = data; - ((PortGroup *)hw)->DIRCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = mask; -} - -static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); - ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) -{ - return ((PortGroup *)hw)->OUT.reg; -} - -static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = data; - ((PortGroup *)hw)->OUTCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = mask; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) -{ - return ((PortGroup *)hw)->IN.reg; -} - -static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((PortGroup *)hw)->CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->CTRL.reg; -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->EVCTRL.reg; -} - -static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PMUX[index].reg; -} - -static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PINCFG[index].reg; -} - -static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].DIR.reg; -} - -static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; -} - -static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; -} - -static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; -} - -static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].OUT.reg; -} - -static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; -} - -static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; -} - -static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; -} - -static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].IN.reg; -} - -static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].CTRL.reg; -} - -static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; -} - -static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; -} - -static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; -} - -static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, - hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PORT_E54_H_INCLUDED */ -#endif /* _SAME54_PORT_COMPONENT_ */ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PORT_COMPONENT_ +#ifndef _HRI_PORT_E54_H_INCLUDED_ +#define _HRI_PORT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_E54_H_INCLUDED */ +#endif /* _SAME54_PORT_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_qspi_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_qspi_e54.h index 23742bc..4927a99 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_qspi_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_qspi_e54.h @@ -1,2058 +1,2058 @@ -/** - * \file - * - * \brief SAM QSPI - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_QSPI_COMPONENT_ -#ifndef _HRI_QSPI_E54_H_INCLUDED_ -#define _HRI_QSPI_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) -#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define QSPI_CRITICAL_SECTION_ENTER() -#define QSPI_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_qspi_baud_reg_t; -typedef uint32_t hri_qspi_ctrla_reg_t; -typedef uint32_t hri_qspi_ctrlb_reg_t; -typedef uint32_t hri_qspi_instraddr_reg_t; -typedef uint32_t hri_qspi_instrctrl_reg_t; -typedef uint32_t hri_qspi_instrframe_reg_t; -typedef uint32_t hri_qspi_intenset_reg_t; -typedef uint32_t hri_qspi_intflag_reg_t; -typedef uint32_t hri_qspi_rxdata_reg_t; -typedef uint32_t hri_qspi_scrambctrl_reg_t; -typedef uint32_t hri_qspi_scrambkey_reg_t; -typedef uint32_t hri_qspi_status_reg_t; -typedef uint32_t hri_qspi_txdata_reg_t; - -static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; -} - -static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; -} - -static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; -} - -static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; -} - -static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; -} - -static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; -} - -static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; -} - -static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; -} - -static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; -} - -static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; -} - -static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; -} - -static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; -} - -static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; -} - -static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; -} - -static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; -} - -static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; -} - -static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; -} - -static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Qspi *)hw)->INTFLAG.reg; -} - -static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) -{ - ((Qspi *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; -} - -static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; -} - -static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; - } -} - -static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; -} - -static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; -} - -static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; -} - -static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; - } -} - -static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; -} - -static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; -} - -static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; -} - -static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; - } -} - -static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; -} - -static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; -} - -static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; -} - -static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; - } -} - -static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; -} - -static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; -} - -static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; -} - -static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; - } -} - -static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; -} - -static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; -} - -static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; -} - -static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; - } -} - -static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; -} - -static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - ((Qspi *)hw)->INTENSET.reg = mask; -} - -static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) -{ - return ((Qspi *)hw)->INTENSET.reg; -} - -static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) -{ - ((Qspi *)hw)->INTENSET.reg = data; - ((Qspi *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - ((Qspi *)hw)->INTENCLR.reg = mask; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) -{ - return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) -{ - return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->RXDATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) -{ - return ((Qspi *)hw)->RXDATA.reg; -} - -static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) -{ - return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; -} - -static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) -{ - return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; -} - -static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) -{ - return ((Qspi *)hw)->STATUS.reg; -} - -static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= ~QSPI_CTRLA_ENABLE; - tmp |= value << QSPI_CTRLA_ENABLE_Pos; - ((Qspi *)hw)->CTRLA.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= ~QSPI_CTRLA_LASTXFER; - tmp |= value << QSPI_CTRLA_LASTXFER_Pos; - ((Qspi *)hw)->CTRLA.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) -{ - return ((Qspi *)hw)->CTRLA.reg; -} - -static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_MODE; - tmp |= value << QSPI_CTRLB_MODE_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_LOOPEN; - tmp |= value << QSPI_CTRLB_LOOPEN_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_WDRBT; - tmp |= value << QSPI_CTRLB_WDRBT_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_SMEMREG; - tmp |= value << QSPI_CTRLB_SMEMREG_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_CSMODE_Msk; - tmp |= QSPI_CTRLB_CSMODE(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DATALEN_Msk; - tmp |= QSPI_CTRLB_DATALEN(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DLYBCT_Msk; - tmp |= QSPI_CTRLB_DLYBCT(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DLYCS_Msk; - tmp |= QSPI_CTRLB_DLYCS(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) -{ - return ((Qspi *)hw)->CTRLB.reg; -} - -static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_CPOL; - tmp |= value << QSPI_BAUD_CPOL_Pos; - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_CPHA; - tmp |= value << QSPI_BAUD_CPHA_Pos; - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_BAUD_Msk; - tmp |= QSPI_BAUD_BAUD(data); - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; - return tmp; -} - -static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_DLYBS_Msk; - tmp |= QSPI_BAUD_DLYBS(data); - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; - return tmp; -} - -static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) -{ - return ((Qspi *)hw)->BAUD.reg; -} - -static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, - hri_qspi_instraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp &= ~QSPI_INSTRADDR_ADDR_Msk; - tmp |= QSPI_INSTRADDR_ADDR(data); - ((Qspi *)hw)->INSTRADDR.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRADDR.reg; -} - -static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, - hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; - tmp |= QSPI_INSTRCTRL_INSTR(data); - ((Qspi *)hw)->INSTRCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, - hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; - tmp |= QSPI_INSTRCTRL_OPTCODE(data); - ((Qspi *)hw)->INSTRCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRCTRL.reg; -} - -static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_INSTREN; - tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_ADDREN; - tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; - tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DATAEN; - tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_ADDRLEN; - tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_CRMODE; - tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DDREN; - tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; - tmp |= QSPI_INSTRFRAME_WIDTH(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; - tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; - tmp |= QSPI_INSTRFRAME_TFRTYPE(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; - tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRFRAME.reg; -} - -static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= ~QSPI_SCRAMBCTRL_ENABLE; - tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; - ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; - tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; - ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, - hri_qspi_scrambctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) -{ - return ((Qspi *)hw)->SCRAMBCTRL.reg; -} - -static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->TXDATA.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBKEY.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_QSPI_E54_H_INCLUDED */ -#endif /* _SAME54_QSPI_COMPONENT_ */ +/** + * \file + * + * \brief SAM QSPI + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_QSPI_COMPONENT_ +#ifndef _HRI_QSPI_E54_H_INCLUDED_ +#define _HRI_QSPI_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) +#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define QSPI_CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_qspi_baud_reg_t; +typedef uint32_t hri_qspi_ctrla_reg_t; +typedef uint32_t hri_qspi_ctrlb_reg_t; +typedef uint32_t hri_qspi_instraddr_reg_t; +typedef uint32_t hri_qspi_instrctrl_reg_t; +typedef uint32_t hri_qspi_instrframe_reg_t; +typedef uint32_t hri_qspi_intenset_reg_t; +typedef uint32_t hri_qspi_intflag_reg_t; +typedef uint32_t hri_qspi_rxdata_reg_t; +typedef uint32_t hri_qspi_scrambctrl_reg_t; +typedef uint32_t hri_qspi_scrambkey_reg_t; +typedef uint32_t hri_qspi_status_reg_t; +typedef uint32_t hri_qspi_txdata_reg_t; + +static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTFLAG.reg; +} + +static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + ((Qspi *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; +} + +static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; +} + +static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; + } +} + +static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; +} + +static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; +} + +static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; +} + +static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; + } +} + +static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; +} + +static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; +} + +static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; +} + +static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; + } +} + +static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; +} + +static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; +} + +static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; +} + +static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; + } +} + +static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; +} + +static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; +} + +static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; +} + +static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; + } +} + +static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; +} + +static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; +} + +static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; +} + +static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; + } +} + +static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; +} + +static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENSET.reg = mask; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTENSET.reg; +} + +static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) +{ + ((Qspi *)hw)->INTENSET.reg = data; + ((Qspi *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENCLR.reg = mask; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) +{ + return ((Qspi *)hw)->RXDATA.reg; +} + +static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; +} + +static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; +} + +static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) +{ + return ((Qspi *)hw)->STATUS.reg; +} + +static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_ENABLE; + tmp |= value << QSPI_CTRLA_ENABLE_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_LASTXFER; + tmp |= value << QSPI_CTRLA_LASTXFER_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLA.reg; +} + +static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_MODE; + tmp |= value << QSPI_CTRLB_MODE_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_LOOPEN; + tmp |= value << QSPI_CTRLB_LOOPEN_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_WDRBT; + tmp |= value << QSPI_CTRLB_WDRBT_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_SMEMREG; + tmp |= value << QSPI_CTRLB_SMEMREG_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_CSMODE_Msk; + tmp |= QSPI_CTRLB_CSMODE(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DATALEN_Msk; + tmp |= QSPI_CTRLB_DATALEN(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYBCT_Msk; + tmp |= QSPI_CTRLB_DLYBCT(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYCS_Msk; + tmp |= QSPI_CTRLB_DLYCS(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLB.reg; +} + +static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPOL; + tmp |= value << QSPI_BAUD_CPOL_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPHA; + tmp |= value << QSPI_BAUD_CPHA_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_BAUD_Msk; + tmp |= QSPI_BAUD_BAUD(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_DLYBS_Msk; + tmp |= QSPI_BAUD_DLYBS(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) +{ + return ((Qspi *)hw)->BAUD.reg; +} + +static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, + hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= ~QSPI_INSTRADDR_ADDR_Msk; + tmp |= QSPI_INSTRADDR_ADDR(data); + ((Qspi *)hw)->INSTRADDR.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRADDR.reg; +} + +static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; + tmp |= QSPI_INSTRCTRL_INSTR(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; + tmp |= QSPI_INSTRCTRL_OPTCODE(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRCTRL.reg; +} + +static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_INSTREN; + tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDREN; + tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; + tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DATAEN; + tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDRLEN; + tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_CRMODE; + tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DDREN; + tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; + tmp |= QSPI_INSTRFRAME_WIDTH(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; + tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; + tmp |= QSPI_INSTRFRAME_TFRTYPE(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; + tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRFRAME.reg; +} + +static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_ENABLE; + tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, + hri_qspi_scrambctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->SCRAMBCTRL.reg; +} + +static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->TXDATA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBKEY.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_QSPI_E54_H_INCLUDED */ +#endif /* _SAME54_QSPI_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ramecc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ramecc_e54.h index 6031cce..5a1215c 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ramecc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_ramecc_e54.h @@ -1,362 +1,362 @@ -/** - * \file - * - * \brief SAM RAMECC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_RAMECC_COMPONENT_ -#ifndef _HRI_RAMECC_E54_H_INCLUDED_ -#define _HRI_RAMECC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) -#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RAMECC_CRITICAL_SECTION_ENTER() -#define RAMECC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ramecc_erraddr_reg_t; -typedef uint8_t hri_ramecc_dbgctrl_reg_t; -typedef uint8_t hri_ramecc_intenset_reg_t; -typedef uint8_t hri_ramecc_intflag_reg_t; -typedef uint8_t hri_ramecc_status_reg_t; - -static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; -} - -static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; -} - -static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; -} - -static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; -} - -static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; -} - -static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; -} - -static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; -} - -static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; -} - -static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) -{ - return ((Ramecc *)hw)->INTFLAG.reg; -} - -static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) -{ - ((Ramecc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; -} - -static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; -} - -static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; - } else { - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; - } -} - -static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; -} - -static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; -} - -static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; -} - -static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; - } else { - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; - } -} - -static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; -} - -static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - ((Ramecc *)hw)->INTENSET.reg = mask; -} - -static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) -{ - return ((Ramecc *)hw)->INTENSET.reg; -} - -static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) -{ - ((Ramecc *)hw)->INTENSET.reg = data; - ((Ramecc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - ((Ramecc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) -{ - return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; -} - -static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) -{ - return ((Ramecc *)hw)->STATUS.reg; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, - hri_ramecc_erraddr_reg_t mask) -{ - return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) -{ - return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ramecc *)hw)->ERRADDR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) -{ - return ((Ramecc *)hw)->ERRADDR.reg; -} - -static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RAMECC_CRITICAL_SECTION_ENTER(); - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= ~RAMECC_DBGCTRL_ECCDIS; - tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; - ((Ramecc *)hw)->DBGCTRL.reg = tmp; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; - return (bool)tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RAMECC_CRITICAL_SECTION_ENTER(); - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= ~RAMECC_DBGCTRL_ECCELOG; - tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; - ((Ramecc *)hw)->DBGCTRL.reg = tmp; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg = data; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ramecc *)hw)->DBGCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RAMECC_E54_H_INCLUDED */ -#endif /* _SAME54_RAMECC_COMPONENT_ */ +/** + * \file + * + * \brief SAM RAMECC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RAMECC_COMPONENT_ +#ifndef _HRI_RAMECC_E54_H_INCLUDED_ +#define _HRI_RAMECC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) +#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RAMECC_CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ramecc_erraddr_reg_t; +typedef uint8_t hri_ramecc_dbgctrl_reg_t; +typedef uint8_t hri_ramecc_intenset_reg_t; +typedef uint8_t hri_ramecc_intflag_reg_t; +typedef uint8_t hri_ramecc_status_reg_t; + +static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTFLAG.reg; +} + +static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + ((Ramecc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; +} + +static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; + } +} + +static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; +} + +static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; +} + +static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; + } +} + +static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; +} + +static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENSET.reg = mask; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTENSET.reg; +} + +static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) +{ + ((Ramecc *)hw)->INTENSET.reg = data; + ((Ramecc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) +{ + return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) +{ + return ((Ramecc *)hw)->STATUS.reg; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, + hri_ramecc_erraddr_reg_t mask) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ramecc *)hw)->ERRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) +{ + return ((Ramecc *)hw)->ERRADDR.reg; +} + +static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCDIS; + tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCELOG; + tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg = data; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ramecc *)hw)->DBGCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RAMECC_E54_H_INCLUDED */ +#endif /* _SAME54_RAMECC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rstc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rstc_e54.h index bf5592a..f8f9fe0 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rstc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rstc_e54.h @@ -1,142 +1,142 @@ -/** - * \file - * - * \brief SAM RSTC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_RSTC_COMPONENT_ -#ifndef _HRI_RSTC_E54_H_INCLUDED_ -#define _HRI_RSTC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) -#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RSTC_CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_rstc_bkupexit_reg_t; -typedef uint8_t hri_rstc_rcause_reg_t; - -static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->RCAUSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) -{ - return ((Rstc *)hw)->RCAUSE.reg; -} - -static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->BKUPEXIT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) -{ - return ((Rstc *)hw)->BKUPEXIT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RSTC_E54_H_INCLUDED */ -#endif /* _SAME54_RSTC_COMPONENT_ */ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_E54_H_INCLUDED_ +#define _HRI_RSTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_E54_H_INCLUDED */ +#endif /* _SAME54_RSTC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rtc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rtc_e54.h index 2f2fa3b..4b892bf 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rtc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_rtc_e54.h @@ -1,10139 +1,10139 @@ -/** - * \file - * - * \brief SAM RTC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_RTC_COMPONENT_ -#ifndef _HRI_RTC_E54_H_INCLUDED_ -#define _HRI_RTC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RTC_CRITICAL_SECTIONS) -#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RTC_CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_rtcmode0_ctrla_reg_t; -typedef uint16_t hri_rtcmode0_ctrlb_reg_t; -typedef uint16_t hri_rtcmode0_intenset_reg_t; -typedef uint16_t hri_rtcmode0_intflag_reg_t; -typedef uint16_t hri_rtcmode1_comp_reg_t; -typedef uint16_t hri_rtcmode1_count_reg_t; -typedef uint16_t hri_rtcmode1_ctrla_reg_t; -typedef uint16_t hri_rtcmode1_ctrlb_reg_t; -typedef uint16_t hri_rtcmode1_intenset_reg_t; -typedef uint16_t hri_rtcmode1_intflag_reg_t; -typedef uint16_t hri_rtcmode1_per_reg_t; -typedef uint16_t hri_rtcmode2_ctrla_reg_t; -typedef uint16_t hri_rtcmode2_ctrlb_reg_t; -typedef uint16_t hri_rtcmode2_intenset_reg_t; -typedef uint16_t hri_rtcmode2_intflag_reg_t; -typedef uint32_t hri_rtc_bkup_reg_t; -typedef uint32_t hri_rtc_gp_reg_t; -typedef uint32_t hri_rtc_tampctrl_reg_t; -typedef uint32_t hri_rtc_tampid_reg_t; -typedef uint32_t hri_rtcalarm_alarm_reg_t; -typedef uint32_t hri_rtcmode0_comp_reg_t; -typedef uint32_t hri_rtcmode0_count_reg_t; -typedef uint32_t hri_rtcmode0_evctrl_reg_t; -typedef uint32_t hri_rtcmode0_syncbusy_reg_t; -typedef uint32_t hri_rtcmode0_timestamp_reg_t; -typedef uint32_t hri_rtcmode1_evctrl_reg_t; -typedef uint32_t hri_rtcmode1_syncbusy_reg_t; -typedef uint32_t hri_rtcmode1_timestamp_reg_t; -typedef uint32_t hri_rtcmode2_alarm_reg_t; -typedef uint32_t hri_rtcmode2_clock_reg_t; -typedef uint32_t hri_rtcmode2_evctrl_reg_t; -typedef uint32_t hri_rtcmode2_syncbusy_reg_t; -typedef uint32_t hri_rtcmode2_timestamp_reg_t; -typedef uint8_t hri_rtc_dbgctrl_reg_t; -typedef uint8_t hri_rtc_freqcorr_reg_t; -typedef uint8_t hri_rtcalarm_mask_reg_t; -typedef uint8_t hri_rtcmode2_mask_reg_t; - -static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, - hri_rtcmode0_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTFLAG.reg; -} - -static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; -} - -static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, - hri_rtcmode1_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTFLAG.reg; -} - -static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; -} - -static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, - hri_rtcmode2_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTFLAG.reg; -} - -static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; -} - -static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; - } -} - -static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = mask; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, - hri_rtcmode0_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTENSET.reg; -} - -static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = data; - ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; -} - -static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; -} - -static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; -} - -static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; - } -} - -static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = mask; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, - hri_rtcmode1_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTENSET.reg; -} - -static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = data; - ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; -} - -static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; -} - -static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; - } -} - -static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = mask; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, - hri_rtcmode2_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTENSET.reg; -} - -static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = data; - ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode0_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode1_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode2_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; -} - -static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_ENABLE; - tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_BKTRST; - tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_GPTRST; - tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; - tmp |= RTC_MODE0_CTRLA_MODE(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE0_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - return ((Rtc *)hw)->MODE0.CTRLA.reg; -} - -static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_ENABLE; - tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_BKTRST; - tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_GPTRST; - tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; - tmp |= RTC_MODE1_CTRLA_MODE(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE1_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - return ((Rtc *)hw)->MODE1.CTRLA.reg; -} - -static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_ENABLE; - tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLKREP; - tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_BKTRST; - tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_GPTRST; - tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; - tmp |= RTC_MODE2_CTRLA_MODE(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE2_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg = data; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - return ((Rtc *)hw)->MODE2.CTRLA.reg; -} - -static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP0EN; - tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP2EN; - tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_RTCOUT; - tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DMAEN; - tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; - tmp |= RTC_MODE0_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; - tmp |= RTC_MODE0_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.CTRLB.reg; -} - -static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP0EN; - tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP2EN; - tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_RTCOUT; - tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DMAEN; - tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; - tmp |= RTC_MODE1_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; - tmp |= RTC_MODE1_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.CTRLB.reg; -} - -static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP0EN; - tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP2EN; - tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_RTCOUT; - tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DMAEN; - tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; - tmp |= RTC_MODE2_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; - tmp |= RTC_MODE2_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CTRLB.reg; -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO0; - tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO1; - tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO2; - tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO3; - tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO4; - tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO5; - tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO6; - tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO7; - tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_OVFEO; - tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, - hri_rtcmode0_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.EVCTRL.reg; -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO0; - tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO1; - tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO2; - tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO3; - tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO4; - tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO5; - tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO6; - tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO7; - tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_OVFEO; - tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, - hri_rtcmode1_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.EVCTRL.reg; -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO0; - tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO1; - tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO2; - tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO3; - tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO4; - tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO5; - tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO6; - tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO7; - tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_OVFEO; - tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, - hri_rtcmode2_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.EVCTRL.reg; -} - -static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.DBGCTRL.reg; -} - -static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - uint8_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - return ((Rtc *)hw)->MODE0.FREQCORR.reg; -} - -static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; - tmp |= RTC_MODE0_COUNT_COUNT(data); - ((Rtc *)hw)->MODE0.COUNT.reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE0.COUNT.reg; -} - -static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; - tmp |= RTC_MODE1_COUNT_COUNT(data); - ((Rtc *)hw)->MODE1.COUNT.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return ((Rtc *)hw)->MODE1.COUNT.reg; -} - -static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; - tmp |= RTC_MODE2_CLOCK_SECOND(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; - tmp |= RTC_MODE2_CLOCK_MINUTE(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; - tmp |= RTC_MODE2_CLOCK_HOUR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; - tmp |= RTC_MODE2_CLOCK_DAY(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; - tmp |= RTC_MODE2_CLOCK_MONTH(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; - tmp |= RTC_MODE2_CLOCK_YEAR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg = data; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return ((Rtc *)hw)->MODE2.CLOCK.reg; -} - -static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= ~RTC_MODE1_PER_PER_Msk; - tmp |= RTC_MODE1_PER_PER(data); - ((Rtc *)hw)->MODE1.PER.reg = tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg = data; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= mask; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - return ((Rtc *)hw)->MODE1.PER.reg; -} - -static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= ~RTC_MODE0_COMP_COMP_Msk; - tmp |= RTC_MODE0_COMP_COMP(data); - ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg = data; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); - return ((Rtc *)hw)->MODE0.COMP[index].reg; -} - -static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= ~RTC_MODE1_COMP_COMP_Msk; - tmp |= RTC_MODE1_COMP_COMP(data); - ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg = data; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode1_wait_for_sync( - hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); - return ((Rtc *)hw)->MODE1.COMP[index].reg; -} - -static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= ~RTC_GP_GP_Msk; - tmp |= RTC_GP_GP(data); - ((Rtc *)hw)->MODE0.GP[index].reg = tmp; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= mask; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg = data; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) -{ - hri_rtcmode0_wait_for_sync( - hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); - return ((Rtc *)hw)->MODE0.GP[index].reg; -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL0; - tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL1; - tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL2; - tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL3; - tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL4; - tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC0; - tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC1; - tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC2; - tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC3; - tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC4; - tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; - tmp |= RTC_TAMPCTRL_IN0ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; - tmp |= RTC_TAMPCTRL_IN1ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; - tmp |= RTC_TAMPCTRL_IN2ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; - tmp |= RTC_TAMPCTRL_IN3ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; - tmp |= RTC_TAMPCTRL_IN4ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; -} - -static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID0; - tmp |= value << RTC_TAMPID_TAMPID0_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID1; - tmp |= value << RTC_TAMPID_TAMPID1_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID2; - tmp |= value << RTC_TAMPID_TAMPID2_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID3; - tmp |= value << RTC_TAMPID_TAMPID3_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID4; - tmp |= value << RTC_TAMPID_TAMPID4_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; - return (bool)tmp; -} - -static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPEVT; - tmp |= value << RTC_TAMPID_TAMPEVT_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPID.reg; -} - -static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= ~RTC_BKUP_BKUP_Msk; - tmp |= RTC_BKUP_BKUP(data); - ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.BKUP[index].reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) -#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) -#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) -#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) -#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) -#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) -#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) -#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) -#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) -#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) -#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) -#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) -#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) -#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) -#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) -#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) -#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) -#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) -#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) -#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) -#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) -#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) -#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) -#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) -#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) -#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) -#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) -#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) -#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) -#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) -#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) -#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) -#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) -#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) -#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) -#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) -#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) -#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) -#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) -#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) -#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) -#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) -#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) -#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) -#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) -#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) -#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) -#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) -#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) -#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) -#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) -#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) -#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) -#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) -#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) -#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) -#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) -#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) -#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) -#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) -#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) -#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) -#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) -#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) -#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) -#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) -#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) -#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) -#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) -#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) -#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) -#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) -#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) -#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) -#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) -#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) -#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) -#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) -#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) -#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) -#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) -#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) -#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) -#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) -#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) -#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) -#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) -#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) -#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) -#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) -#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) -#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) -#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) -#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) -#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) -#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) -#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) -#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) -#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) -#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) -#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) -#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) -#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) -#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) -#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) -#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) -#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) -#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) -#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) -#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) -#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) -#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) -#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) -#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) -#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) -#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) -#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) -#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) -#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) -#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) -#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) -#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) -#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) -#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) -#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) -#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) -#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) -#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) -#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) -#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) -#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) -#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) -#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) -#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) -#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) -#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) -#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) -#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) -#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RTC_E54_H_INCLUDED */ -#endif /* _SAME54_RTC_COMPONENT_ */ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RTC_COMPONENT_ +#ifndef _HRI_RTC_E54_H_INCLUDED_ +#define _HRI_RTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_ctrlb_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_ctrlb_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_ctrlb_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_bkup_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtc_tampctrl_reg_t; +typedef uint32_t hri_rtc_tampid_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode0_timestamp_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_timestamp_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_timestamp_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_BKTRST; + tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_GPTRST; + tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_BKTRST; + tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_GPTRST; + tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_BKTRST; + tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_GPTRST; + tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP0EN; + tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP2EN; + tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_RTCOUT; + tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DMAEN; + tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; + tmp |= RTC_MODE0_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; + tmp |= RTC_MODE0_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLB.reg; +} + +static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP0EN; + tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP2EN; + tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_RTCOUT; + tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DMAEN; + tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; + tmp |= RTC_MODE1_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; + tmp |= RTC_MODE1_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLB.reg; +} + +static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP0EN; + tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP2EN; + tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_RTCOUT; + tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DMAEN; + tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; + tmp |= RTC_MODE2_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; + tmp |= RTC_MODE2_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLB.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE0.GP[index].reg = tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; +} + +static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPID.reg; +} + +static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.BKUP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_E54_H_INCLUDED */ +#endif /* _SAME54_RTC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sdhc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sdhc_e54.h index 0b7f609..ff9f36a 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sdhc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sdhc_e54.h @@ -1,7477 +1,7477 @@ -/** - * \file - * - * \brief SAM SDHC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_SDHC_COMPONENT_ -#ifndef _HRI_SDHC_E54_H_INCLUDED_ -#define _HRI_SDHC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) -#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SDHC_CRITICAL_SECTION_ENTER() -#define SDHC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sdhc_acesr_reg_t; -typedef uint16_t hri_sdhc_bcr_reg_t; -typedef uint16_t hri_sdhc_bsr_reg_t; -typedef uint16_t hri_sdhc_ccr_reg_t; -typedef uint16_t hri_sdhc_cr_reg_t; -typedef uint16_t hri_sdhc_eisier_reg_t; -typedef uint16_t hri_sdhc_eister_reg_t; -typedef uint16_t hri_sdhc_eistr_reg_t; -typedef uint16_t hri_sdhc_feraces_reg_t; -typedef uint16_t hri_sdhc_fereis_reg_t; -typedef uint16_t hri_sdhc_hc2r_reg_t; -typedef uint16_t hri_sdhc_hcvr_reg_t; -typedef uint16_t hri_sdhc_nisier_reg_t; -typedef uint16_t hri_sdhc_nister_reg_t; -typedef uint16_t hri_sdhc_nistr_reg_t; -typedef uint16_t hri_sdhc_pvr_reg_t; -typedef uint16_t hri_sdhc_sisr_reg_t; -typedef uint16_t hri_sdhc_tmr_reg_t; -typedef uint32_t hri_sdhc_acr_reg_t; -typedef uint32_t hri_sdhc_arg1r_reg_t; -typedef uint32_t hri_sdhc_asar_reg_t; -typedef uint32_t hri_sdhc_bdpr_reg_t; -typedef uint32_t hri_sdhc_ca0r_reg_t; -typedef uint32_t hri_sdhc_ca1r_reg_t; -typedef uint32_t hri_sdhc_cacr_reg_t; -typedef uint32_t hri_sdhc_cc2r_reg_t; -typedef uint32_t hri_sdhc_mccar_reg_t; -typedef uint32_t hri_sdhc_psr_reg_t; -typedef uint32_t hri_sdhc_rr_reg_t; -typedef uint32_t hri_sdhc_ssar_reg_t; -typedef uint8_t hri_sdhc_aesr_reg_t; -typedef uint8_t hri_sdhc_bgcr_reg_t; -typedef uint8_t hri_sdhc_dbgr_reg_t; -typedef uint8_t hri_sdhc_hc1r_reg_t; -typedef uint8_t hri_sdhc_mc1r_reg_t; -typedef uint8_t hri_sdhc_mc2r_reg_t; -typedef uint8_t hri_sdhc_pcr_reg_t; -typedef uint8_t hri_sdhc_srr_reg_t; -typedef uint8_t hri_sdhc_tcr_reg_t; -typedef uint8_t hri_sdhc_wcr_reg_t; - -static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) -{ - return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) -{ - return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->RR[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->RR[index].reg; -} - -static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; -} - -static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; -} - -static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; -} - -static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; -} - -static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; -} - -static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; -} - -static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->PSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->PSR.reg; -} - -static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; -} - -static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; -} - -static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->ACESR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ACESR.reg; -} - -static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CA0R.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CA0R.reg; -} - -static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CA1R.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CA1R.reg; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->MCCAR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->MCCAR.reg; -} - -static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->AESR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->AESR.reg; -} - -static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; -} - -static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->SISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SISR.reg; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HCVR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HCVR.reg; -} - -static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= ~SDHC_SSAR_ADDR_Msk; - tmp |= SDHC_SSAR_ADDR(data); - ((Sdhc *)hw)->SSAR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; - return tmp; -} - -static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; - tmp |= SDHC_SSAR_CMD23_ARG2(data); - ((Sdhc *)hw)->SSAR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; - return tmp; -} - -static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SSAR.reg; -} - -static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; - tmp |= SDHC_BSR_BLOCKSIZE(data); - ((Sdhc *)hw)->BSR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= ~SDHC_BSR_BOUNDARY_Msk; - tmp |= SDHC_BSR_BOUNDARY(data); - ((Sdhc *)hw)->BSR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BSR.reg; -} - -static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BCR.reg; - tmp &= ~SDHC_BCR_BCNT_Msk; - tmp |= SDHC_BCR_BCNT(data); - ((Sdhc *)hw)->BCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BCR.reg; -} - -static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp &= ~SDHC_ARG1R_ARG_Msk; - tmp |= SDHC_ARG1R_ARG(data); - ((Sdhc *)hw)->ARG1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ARG1R.reg; -} - -static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_DMAEN; - tmp |= value << SDHC_TMR_DMAEN_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_BCEN; - tmp |= value << SDHC_TMR_BCEN_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_DTDSEL; - tmp |= value << SDHC_TMR_DTDSEL_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_MSBSEL; - tmp |= value << SDHC_TMR_MSBSEL_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; - return tmp; -} - -static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_ACMDEN_Msk; - tmp |= SDHC_TMR_ACMDEN(data); - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; - return tmp; -} - -static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->TMR.reg; -} - -static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDCCEN; - tmp |= value << SDHC_CR_CMDCCEN_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDICEN; - tmp |= value << SDHC_CR_CMDICEN_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_DPSEL; - tmp |= value << SDHC_CR_DPSEL_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_RESPTYP_Msk; - tmp |= SDHC_CR_RESPTYP(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDTYP_Msk; - tmp |= SDHC_CR_CMDTYP(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDIDX_Msk; - tmp |= SDHC_CR_CMDIDX(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CR.reg; -} - -static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp &= ~SDHC_BDPR_BUFDATA_Msk; - tmp |= SDHC_BDPR_BUFDATA(data); - ((Sdhc *)hw)->BDPR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BDPR.reg; -} - -static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_LEDCTRL; - tmp |= value << SDHC_HC1R_LEDCTRL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_DW; - tmp |= value << SDHC_HC1R_DW_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_HSEN; - tmp |= value << SDHC_HC1R_HSEN_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_CARDDTL; - tmp |= value << SDHC_HC1R_CARDDTL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_CARDDSEL; - tmp |= value << SDHC_HC1R_CARDDSEL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_DMASEL_Msk; - tmp |= SDHC_HC1R_DMASEL(data); - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC1R.reg; -} - -static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= ~SDHC_PCR_SDBPWR; - tmp |= value << SDHC_PCR_SDBPWR_Pos; - ((Sdhc *)hw)->PCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= ~SDHC_PCR_SDBVSEL_Msk; - tmp |= SDHC_PCR_SDBVSEL(data); - ((Sdhc *)hw)->PCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->PCR.reg; -} - -static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_STPBGR; - tmp |= value << SDHC_BGCR_STPBGR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_CONTR; - tmp |= value << SDHC_BGCR_CONTR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_RWCTRL; - tmp |= value << SDHC_BGCR_RWCTRL_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_INTBG; - tmp |= value << SDHC_BGCR_INTBG_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BGCR.reg; -} - -static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCINT; - tmp |= value << SDHC_WCR_WKENCINT_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCINS; - tmp |= value << SDHC_WCR_WKENCINS_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCREM; - tmp |= value << SDHC_WCR_WKENCREM_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->WCR.reg; -} - -static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_INTCLKEN; - tmp |= value << SDHC_CCR_INTCLKEN_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_INTCLKS; - tmp |= value << SDHC_CCR_INTCLKS_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_SDCLKEN; - tmp |= value << SDHC_CCR_SDCLKEN_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_CLKGSEL; - tmp |= value << SDHC_CCR_CLKGSEL_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; - tmp |= SDHC_CCR_USDCLKFSEL(data); - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; - tmp |= SDHC_CCR_SDCLKFSEL(data); - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CCR.reg; -} - -static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TCR.reg; - tmp &= ~SDHC_TCR_DTCVAL_Msk; - tmp |= SDHC_TCR_DTCVAL(data); - ((Sdhc *)hw)->TCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->TCR.reg; -} - -static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTALL; - tmp |= value << SDHC_SRR_SWRSTALL_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTCMD; - tmp |= value << SDHC_SRR_SWRSTCMD_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTDAT; - tmp |= value << SDHC_SRR_SWRSTDAT_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SRR.reg; -} - -static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CMDC; - tmp |= value << SDHC_NISTR_CMDC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_TRFC; - tmp |= value << SDHC_NISTR_TRFC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BLKGE; - tmp |= value << SDHC_NISTR_BLKGE_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_DMAINT; - tmp |= value << SDHC_NISTR_DMAINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BWRRDY; - tmp |= value << SDHC_NISTR_BWRRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BRDRDY; - tmp |= value << SDHC_NISTR_BRDRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CINS; - tmp |= value << SDHC_NISTR_CINS_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CREM; - tmp |= value << SDHC_NISTR_CREM_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CINT; - tmp |= value << SDHC_NISTR_CINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_BOOTAR; - tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_ERRINT; - tmp |= value << SDHC_NISTR_ERRINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTR.reg; -} - -static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDTEO; - tmp |= value << SDHC_EISTR_CMDTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDCRC; - tmp |= value << SDHC_EISTR_CMDCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDEND; - tmp |= value << SDHC_EISTR_CMDEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDIDX; - tmp |= value << SDHC_EISTR_CMDIDX_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATTEO; - tmp |= value << SDHC_EISTR_DATTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATCRC; - tmp |= value << SDHC_EISTR_DATCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATEND; - tmp |= value << SDHC_EISTR_DATEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CURLIM; - tmp |= value << SDHC_EISTR_CURLIM_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_ACMD; - tmp |= value << SDHC_EISTR_ACMD_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_ADMA; - tmp |= value << SDHC_EISTR_ADMA_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_BOOTAE; - tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTR.reg; -} - -static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CMDC; - tmp |= value << SDHC_NISTER_CMDC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_TRFC; - tmp |= value << SDHC_NISTER_TRFC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BLKGE; - tmp |= value << SDHC_NISTER_BLKGE_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_DMAINT; - tmp |= value << SDHC_NISTER_DMAINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BWRRDY; - tmp |= value << SDHC_NISTER_BWRRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BRDRDY; - tmp |= value << SDHC_NISTER_BRDRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CINS; - tmp |= value << SDHC_NISTER_CINS_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CREM; - tmp |= value << SDHC_NISTER_CREM_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CINT; - tmp |= value << SDHC_NISTER_CINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_BOOTAR; - tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTER.reg; -} - -static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDTEO; - tmp |= value << SDHC_EISTER_CMDTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDCRC; - tmp |= value << SDHC_EISTER_CMDCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDEND; - tmp |= value << SDHC_EISTER_CMDEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDIDX; - tmp |= value << SDHC_EISTER_CMDIDX_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATTEO; - tmp |= value << SDHC_EISTER_DATTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATCRC; - tmp |= value << SDHC_EISTER_DATCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATEND; - tmp |= value << SDHC_EISTER_DATEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CURLIM; - tmp |= value << SDHC_EISTER_CURLIM_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_ACMD; - tmp |= value << SDHC_EISTER_ACMD_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_ADMA; - tmp |= value << SDHC_EISTER_ADMA_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_BOOTAE; - tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTER.reg; -} - -static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CMDC; - tmp |= value << SDHC_NISIER_CMDC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_TRFC; - tmp |= value << SDHC_NISIER_TRFC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BLKGE; - tmp |= value << SDHC_NISIER_BLKGE_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_DMAINT; - tmp |= value << SDHC_NISIER_DMAINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BWRRDY; - tmp |= value << SDHC_NISIER_BWRRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BRDRDY; - tmp |= value << SDHC_NISIER_BRDRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CINS; - tmp |= value << SDHC_NISIER_CINS_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CREM; - tmp |= value << SDHC_NISIER_CREM_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CINT; - tmp |= value << SDHC_NISIER_CINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_BOOTAR; - tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISIER.reg; -} - -static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDTEO; - tmp |= value << SDHC_EISIER_CMDTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDCRC; - tmp |= value << SDHC_EISIER_CMDCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDEND; - tmp |= value << SDHC_EISIER_CMDEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDIDX; - tmp |= value << SDHC_EISIER_CMDIDX_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATTEO; - tmp |= value << SDHC_EISIER_DATTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATCRC; - tmp |= value << SDHC_EISIER_DATCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATEND; - tmp |= value << SDHC_EISIER_DATEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CURLIM; - tmp |= value << SDHC_EISIER_CURLIM_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_ACMD; - tmp |= value << SDHC_EISIER_ACMD_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_ADMA; - tmp |= value << SDHC_EISIER_ADMA_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_BOOTAE; - tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISIER.reg; -} - -static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_VS18EN; - tmp |= value << SDHC_HC2R_VS18EN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EXTUN; - tmp |= value << SDHC_HC2R_EXTUN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_SLCKSEL; - tmp |= value << SDHC_HC2R_SLCKSEL_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_ASINTEN; - tmp |= value << SDHC_HC2R_ASINTEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_PVALEN; - tmp |= value << SDHC_HC2R_PVALEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_UHSMS_Msk; - tmp |= SDHC_HC2R_UHSMS(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; - tmp |= SDHC_HC2R_EMMC_HS200EN(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_DRVSEL_Msk; - tmp |= SDHC_HC2R_DRVSEL(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC2R.reg; -} - -static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, - hri_sdhc_asar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp &= ~SDHC_ASAR_ADMASA_Msk; - tmp |= SDHC_ASAR_ADMASA(data); - ((Sdhc *)hw)->ASAR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->ASAR[index].reg; -} - -static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_CLKGSEL; - tmp |= value << SDHC_PVR_CLKGSEL_Pos; - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, - hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; - tmp |= SDHC_PVR_SDCLKFSEL(data); - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, - hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_DRVSEL_Msk; - tmp |= SDHC_PVR_DRVSEL(data); - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->PVR[index].reg; -} - -static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_DDR; - tmp |= value << SDHC_MC1R_DDR_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_OPD; - tmp |= value << SDHC_MC1R_OPD_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_BOOTA; - tmp |= value << SDHC_MC1R_BOOTA_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_RSTN; - tmp |= value << SDHC_MC1R_RSTN_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_FCD; - tmp |= value << SDHC_MC1R_FCD_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_CMDTYP_Msk; - tmp |= SDHC_MC1R_CMDTYP(data); - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->MC1R.reg; -} - -static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ACR.reg; - tmp &= ~SDHC_ACR_BMAX_Msk; - tmp |= SDHC_ACR_BMAX(data); - ((Sdhc *)hw)->ACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ACR.reg; -} - -static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp &= ~SDHC_CC2R_FSDCLKD; - tmp |= value << SDHC_CC2R_FSDCLKD_Pos; - ((Sdhc *)hw)->CC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CC2R.reg; -} - -static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= ~SDHC_CACR_CAPWREN; - tmp |= value << SDHC_CACR_CAPWREN_Pos; - ((Sdhc *)hw)->CACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= ~SDHC_CACR_KEY_Msk; - tmp |= SDHC_CACR_KEY(data); - ((Sdhc *)hw)->CACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CACR.reg; -} - -static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp &= ~SDHC_DBGR_NIDBG; - tmp |= value << SDHC_DBGR_NIDBG_Pos; - ((Sdhc *)hw)->DBGR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->DBGR.reg; -} - -static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->FERACES.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->FEREIS.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) -#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) -#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) -#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) -#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) -#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) -#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) -#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) -#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) -#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) -#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) -#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) -#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) -#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) -#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) -#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) -#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) -#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) -#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) -#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) -#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) -#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) -#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) -#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) -#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) -#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) -#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) -#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) -#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) -#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) -#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) -#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) -#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) -#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) -#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) -#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) -#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) -#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) -#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) -#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) -#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) -#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) -#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) -#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) -#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) -#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) -#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) -#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) -#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) -#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) -#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) -#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) -#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) -#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) -#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) -#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) -#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) -#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) -#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) -#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) -#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) -#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) -#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) -#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) -#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) -#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) -#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) -#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) -#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) -#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) -#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) -#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) -#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) -#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) -#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) -#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) -#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) -#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) -#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) -#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) -#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) -#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) -#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) -#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) -#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) -#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) -#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) -#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) -#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) -#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) -#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) -#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) -#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) -#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) -#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) -#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) -#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) -#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) -#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) -#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) -#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) -#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) -#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) -#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) -#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) -#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) -#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) -#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) -#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) -#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) -#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) -#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) -#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) -#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) -#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) -#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) -#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) -#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) -#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) -#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) -#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) -#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) -#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) -#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) -#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) -#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) -#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) -#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) -#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) -#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) -#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) -#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) -#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) -#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) -#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) -#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) -#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) -#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) -#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) -#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) -#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) -#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) -#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) -#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) -#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) -#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) -#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) -#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) -#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) -#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) -#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) -#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) -#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) -#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) -#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) -#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) -#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) -#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) -#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) -#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) -#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) -#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) -#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) -#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) -#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) -#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) -#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) -#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) -#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) -#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) -#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) -#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) -#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) -#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) -#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) -#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) -#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) -#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) -#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) -#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) -#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) -#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) -#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) -#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) -#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) -#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) -#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) -#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) -#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) -#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) -#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) -#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) -#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) -#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) -#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) -#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) -#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) -#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) -#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) -#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) -#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) -#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) -#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) -#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) -#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) -#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) -#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) -#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) -#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) -#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) -#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) -#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) -#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) -#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) -#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) -#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) -#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) -#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) -#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) -#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) -#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) -#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SDHC_E54_H_INCLUDED */ -#endif /* _SAME54_SDHC_COMPONENT_ */ +/** + * \file + * + * \brief SAM SDHC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SDHC_COMPONENT_ +#ifndef _HRI_SDHC_E54_H_INCLUDED_ +#define _HRI_SDHC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) +#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDHC_CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdhc_acesr_reg_t; +typedef uint16_t hri_sdhc_bcr_reg_t; +typedef uint16_t hri_sdhc_bsr_reg_t; +typedef uint16_t hri_sdhc_ccr_reg_t; +typedef uint16_t hri_sdhc_cr_reg_t; +typedef uint16_t hri_sdhc_eisier_reg_t; +typedef uint16_t hri_sdhc_eister_reg_t; +typedef uint16_t hri_sdhc_eistr_reg_t; +typedef uint16_t hri_sdhc_feraces_reg_t; +typedef uint16_t hri_sdhc_fereis_reg_t; +typedef uint16_t hri_sdhc_hc2r_reg_t; +typedef uint16_t hri_sdhc_hcvr_reg_t; +typedef uint16_t hri_sdhc_nisier_reg_t; +typedef uint16_t hri_sdhc_nister_reg_t; +typedef uint16_t hri_sdhc_nistr_reg_t; +typedef uint16_t hri_sdhc_pvr_reg_t; +typedef uint16_t hri_sdhc_sisr_reg_t; +typedef uint16_t hri_sdhc_tmr_reg_t; +typedef uint32_t hri_sdhc_acr_reg_t; +typedef uint32_t hri_sdhc_arg1r_reg_t; +typedef uint32_t hri_sdhc_asar_reg_t; +typedef uint32_t hri_sdhc_bdpr_reg_t; +typedef uint32_t hri_sdhc_ca0r_reg_t; +typedef uint32_t hri_sdhc_ca1r_reg_t; +typedef uint32_t hri_sdhc_cacr_reg_t; +typedef uint32_t hri_sdhc_cc2r_reg_t; +typedef uint32_t hri_sdhc_mccar_reg_t; +typedef uint32_t hri_sdhc_psr_reg_t; +typedef uint32_t hri_sdhc_rr_reg_t; +typedef uint32_t hri_sdhc_ssar_reg_t; +typedef uint8_t hri_sdhc_aesr_reg_t; +typedef uint8_t hri_sdhc_bgcr_reg_t; +typedef uint8_t hri_sdhc_dbgr_reg_t; +typedef uint8_t hri_sdhc_hc1r_reg_t; +typedef uint8_t hri_sdhc_mc1r_reg_t; +typedef uint8_t hri_sdhc_mc2r_reg_t; +typedef uint8_t hri_sdhc_pcr_reg_t; +typedef uint8_t hri_sdhc_srr_reg_t; +typedef uint8_t hri_sdhc_tcr_reg_t; +typedef uint8_t hri_sdhc_wcr_reg_t; + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->RR[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->RR[index].reg; +} + +static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; +} + +static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; +} + +static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PSR.reg; +} + +static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; +} + +static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->ACESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACESR.reg; +} + +static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA0R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA0R.reg; +} + +static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA1R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA1R.reg; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->MCCAR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MCCAR.reg; +} + +static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->AESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->AESR.reg; +} + +static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->SISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SISR.reg; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HCVR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HCVR.reg; +} + +static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_ADDR_Msk; + tmp |= SDHC_SSAR_ADDR(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; + tmp |= SDHC_SSAR_CMD23_ARG2(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SSAR.reg; +} + +static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; + tmp |= SDHC_BSR_BLOCKSIZE(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BOUNDARY_Msk; + tmp |= SDHC_BSR_BOUNDARY(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BSR.reg; +} + +static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= ~SDHC_BCR_BCNT_Msk; + tmp |= SDHC_BCR_BCNT(data); + ((Sdhc *)hw)->BCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BCR.reg; +} + +static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= ~SDHC_ARG1R_ARG_Msk; + tmp |= SDHC_ARG1R_ARG(data); + ((Sdhc *)hw)->ARG1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ARG1R.reg; +} + +static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DMAEN; + tmp |= value << SDHC_TMR_DMAEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_BCEN; + tmp |= value << SDHC_TMR_BCEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DTDSEL; + tmp |= value << SDHC_TMR_DTDSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_MSBSEL; + tmp |= value << SDHC_TMR_MSBSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_ACMDEN_Msk; + tmp |= SDHC_TMR_ACMDEN(data); + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TMR.reg; +} + +static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDCCEN; + tmp |= value << SDHC_CR_CMDCCEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDICEN; + tmp |= value << SDHC_CR_CMDICEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_DPSEL; + tmp |= value << SDHC_CR_DPSEL_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_RESPTYP_Msk; + tmp |= SDHC_CR_RESPTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDTYP_Msk; + tmp |= SDHC_CR_CMDTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDIDX_Msk; + tmp |= SDHC_CR_CMDIDX(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CR.reg; +} + +static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= ~SDHC_BDPR_BUFDATA_Msk; + tmp |= SDHC_BDPR_BUFDATA(data); + ((Sdhc *)hw)->BDPR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BDPR.reg; +} + +static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_LEDCTRL; + tmp |= value << SDHC_HC1R_LEDCTRL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DW; + tmp |= value << SDHC_HC1R_DW_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_HSEN; + tmp |= value << SDHC_HC1R_HSEN_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDTL; + tmp |= value << SDHC_HC1R_CARDDTL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDSEL; + tmp |= value << SDHC_HC1R_CARDDSEL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DMASEL_Msk; + tmp |= SDHC_HC1R_DMASEL(data); + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC1R.reg; +} + +static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBPWR; + tmp |= value << SDHC_PCR_SDBPWR_Pos; + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBVSEL_Msk; + tmp |= SDHC_PCR_SDBVSEL(data); + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PCR.reg; +} + +static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_STPBGR; + tmp |= value << SDHC_BGCR_STPBGR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_CONTR; + tmp |= value << SDHC_BGCR_CONTR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_RWCTRL; + tmp |= value << SDHC_BGCR_RWCTRL_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_INTBG; + tmp |= value << SDHC_BGCR_INTBG_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BGCR.reg; +} + +static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINT; + tmp |= value << SDHC_WCR_WKENCINT_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINS; + tmp |= value << SDHC_WCR_WKENCINS_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCREM; + tmp |= value << SDHC_WCR_WKENCREM_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->WCR.reg; +} + +static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKEN; + tmp |= value << SDHC_CCR_INTCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKS; + tmp |= value << SDHC_CCR_INTCLKS_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKEN; + tmp |= value << SDHC_CCR_SDCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_CLKGSEL; + tmp |= value << SDHC_CCR_CLKGSEL_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; + tmp |= SDHC_CCR_USDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; + tmp |= SDHC_CCR_SDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CCR.reg; +} + +static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= ~SDHC_TCR_DTCVAL_Msk; + tmp |= SDHC_TCR_DTCVAL(data); + ((Sdhc *)hw)->TCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TCR.reg; +} + +static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTALL; + tmp |= value << SDHC_SRR_SWRSTALL_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTCMD; + tmp |= value << SDHC_SRR_SWRSTCMD_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTDAT; + tmp |= value << SDHC_SRR_SWRSTDAT_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SRR.reg; +} + +static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CMDC; + tmp |= value << SDHC_NISTR_CMDC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_TRFC; + tmp |= value << SDHC_NISTR_TRFC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BLKGE; + tmp |= value << SDHC_NISTR_BLKGE_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_DMAINT; + tmp |= value << SDHC_NISTR_DMAINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BWRRDY; + tmp |= value << SDHC_NISTR_BWRRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BRDRDY; + tmp |= value << SDHC_NISTR_BRDRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINS; + tmp |= value << SDHC_NISTR_CINS_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CREM; + tmp |= value << SDHC_NISTR_CREM_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINT; + tmp |= value << SDHC_NISTR_CINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BOOTAR; + tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_ERRINT; + tmp |= value << SDHC_NISTR_ERRINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTR.reg; +} + +static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDTEO; + tmp |= value << SDHC_EISTR_CMDTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDCRC; + tmp |= value << SDHC_EISTR_CMDCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDEND; + tmp |= value << SDHC_EISTR_CMDEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDIDX; + tmp |= value << SDHC_EISTR_CMDIDX_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATTEO; + tmp |= value << SDHC_EISTR_DATTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATCRC; + tmp |= value << SDHC_EISTR_DATCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATEND; + tmp |= value << SDHC_EISTR_DATEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CURLIM; + tmp |= value << SDHC_EISTR_CURLIM_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ACMD; + tmp |= value << SDHC_EISTR_ACMD_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ADMA; + tmp |= value << SDHC_EISTR_ADMA_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_BOOTAE; + tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTR.reg; +} + +static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CMDC; + tmp |= value << SDHC_NISTER_CMDC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_TRFC; + tmp |= value << SDHC_NISTER_TRFC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BLKGE; + tmp |= value << SDHC_NISTER_BLKGE_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_DMAINT; + tmp |= value << SDHC_NISTER_DMAINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BWRRDY; + tmp |= value << SDHC_NISTER_BWRRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BRDRDY; + tmp |= value << SDHC_NISTER_BRDRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINS; + tmp |= value << SDHC_NISTER_CINS_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CREM; + tmp |= value << SDHC_NISTER_CREM_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINT; + tmp |= value << SDHC_NISTER_CINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BOOTAR; + tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTER.reg; +} + +static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDTEO; + tmp |= value << SDHC_EISTER_CMDTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDCRC; + tmp |= value << SDHC_EISTER_CMDCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDEND; + tmp |= value << SDHC_EISTER_CMDEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDIDX; + tmp |= value << SDHC_EISTER_CMDIDX_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATTEO; + tmp |= value << SDHC_EISTER_DATTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATCRC; + tmp |= value << SDHC_EISTER_DATCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATEND; + tmp |= value << SDHC_EISTER_DATEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CURLIM; + tmp |= value << SDHC_EISTER_CURLIM_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ACMD; + tmp |= value << SDHC_EISTER_ACMD_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ADMA; + tmp |= value << SDHC_EISTER_ADMA_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_BOOTAE; + tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTER.reg; +} + +static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CMDC; + tmp |= value << SDHC_NISIER_CMDC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_TRFC; + tmp |= value << SDHC_NISIER_TRFC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BLKGE; + tmp |= value << SDHC_NISIER_BLKGE_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_DMAINT; + tmp |= value << SDHC_NISIER_DMAINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BWRRDY; + tmp |= value << SDHC_NISIER_BWRRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BRDRDY; + tmp |= value << SDHC_NISIER_BRDRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINS; + tmp |= value << SDHC_NISIER_CINS_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CREM; + tmp |= value << SDHC_NISIER_CREM_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINT; + tmp |= value << SDHC_NISIER_CINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BOOTAR; + tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISIER.reg; +} + +static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDTEO; + tmp |= value << SDHC_EISIER_CMDTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDCRC; + tmp |= value << SDHC_EISIER_CMDCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDEND; + tmp |= value << SDHC_EISIER_CMDEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDIDX; + tmp |= value << SDHC_EISIER_CMDIDX_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATTEO; + tmp |= value << SDHC_EISIER_DATTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATCRC; + tmp |= value << SDHC_EISIER_DATCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATEND; + tmp |= value << SDHC_EISIER_DATEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CURLIM; + tmp |= value << SDHC_EISIER_CURLIM_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ACMD; + tmp |= value << SDHC_EISIER_ACMD_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ADMA; + tmp |= value << SDHC_EISIER_ADMA_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_BOOTAE; + tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISIER.reg; +} + +static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_VS18EN; + tmp |= value << SDHC_HC2R_VS18EN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EXTUN; + tmp |= value << SDHC_HC2R_EXTUN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_SLCKSEL; + tmp |= value << SDHC_HC2R_SLCKSEL_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_ASINTEN; + tmp |= value << SDHC_HC2R_ASINTEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_PVALEN; + tmp |= value << SDHC_HC2R_PVALEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_UHSMS_Msk; + tmp |= SDHC_HC2R_UHSMS(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; + tmp |= SDHC_HC2R_EMMC_HS200EN(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_DRVSEL_Msk; + tmp |= SDHC_HC2R_DRVSEL(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC2R.reg; +} + +static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, + hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= ~SDHC_ASAR_ADMASA_Msk; + tmp |= SDHC_ASAR_ADMASA(data); + ((Sdhc *)hw)->ASAR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->ASAR[index].reg; +} + +static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_CLKGSEL; + tmp |= value << SDHC_PVR_CLKGSEL_Pos; + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; + tmp |= SDHC_PVR_SDCLKFSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_DRVSEL_Msk; + tmp |= SDHC_PVR_DRVSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->PVR[index].reg; +} + +static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_DDR; + tmp |= value << SDHC_MC1R_DDR_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_OPD; + tmp |= value << SDHC_MC1R_OPD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_BOOTA; + tmp |= value << SDHC_MC1R_BOOTA_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_RSTN; + tmp |= value << SDHC_MC1R_RSTN_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_FCD; + tmp |= value << SDHC_MC1R_FCD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_CMDTYP_Msk; + tmp |= SDHC_MC1R_CMDTYP(data); + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MC1R.reg; +} + +static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= ~SDHC_ACR_BMAX_Msk; + tmp |= SDHC_ACR_BMAX(data); + ((Sdhc *)hw)->ACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACR.reg; +} + +static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= ~SDHC_CC2R_FSDCLKD; + tmp |= value << SDHC_CC2R_FSDCLKD_Pos; + ((Sdhc *)hw)->CC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CC2R.reg; +} + +static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_CAPWREN; + tmp |= value << SDHC_CACR_CAPWREN_Pos; + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_KEY_Msk; + tmp |= SDHC_CACR_KEY(data); + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CACR.reg; +} + +static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= ~SDHC_DBGR_NIDBG; + tmp |= value << SDHC_DBGR_NIDBG_Pos; + ((Sdhc *)hw)->DBGR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->DBGR.reg; +} + +static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FERACES.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FEREIS.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) +#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) +#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) +#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) +#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) +#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) +#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) +#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) +#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) +#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) +#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) +#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) +#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) +#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) +#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) +#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) +#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) +#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) +#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) +#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) +#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) +#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) +#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) +#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) +#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) +#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) +#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) +#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) +#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) +#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) +#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) +#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) +#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) +#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) +#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) +#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) +#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) +#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) +#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) +#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) +#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) +#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) +#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) +#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) +#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) +#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) +#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) +#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) +#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) +#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) +#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) +#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) +#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) +#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) +#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) +#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) +#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) +#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) +#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) +#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) +#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) +#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) +#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) +#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) +#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) +#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) +#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) +#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) +#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) +#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) +#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) +#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) +#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) +#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) +#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) +#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDHC_E54_H_INCLUDED */ +#endif /* _SAME54_SDHC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sercom_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sercom_e54.h index fed00ff..b3de9e1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sercom_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_sercom_e54.h @@ -1,8892 +1,8892 @@ -/** - * \file - * - * \brief SAM SERCOM - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_SERCOM_COMPONENT_ -#ifndef _HRI_SERCOM_E54_H_INCLUDED_ -#define _HRI_SERCOM_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) -#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SERCOM_CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sercomi2cm_status_reg_t; -typedef uint16_t hri_sercomi2cs_length_reg_t; -typedef uint16_t hri_sercomi2cs_status_reg_t; -typedef uint16_t hri_sercomspi_length_reg_t; -typedef uint16_t hri_sercomspi_status_reg_t; -typedef uint16_t hri_sercomusart_baud_reg_t; -typedef uint16_t hri_sercomusart_length_reg_t; -typedef uint16_t hri_sercomusart_status_reg_t; -typedef uint32_t hri_sercomi2cm_addr_reg_t; -typedef uint32_t hri_sercomi2cm_baud_reg_t; -typedef uint32_t hri_sercomi2cm_ctrla_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; -typedef uint32_t hri_sercomi2cm_data_reg_t; -typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; -typedef uint32_t hri_sercomi2cs_addr_reg_t; -typedef uint32_t hri_sercomi2cs_ctrla_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; -typedef uint32_t hri_sercomi2cs_data_reg_t; -typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; -typedef uint32_t hri_sercomspi_addr_reg_t; -typedef uint32_t hri_sercomspi_ctrla_reg_t; -typedef uint32_t hri_sercomspi_ctrlb_reg_t; -typedef uint32_t hri_sercomspi_ctrlc_reg_t; -typedef uint32_t hri_sercomspi_data_reg_t; -typedef uint32_t hri_sercomspi_syncbusy_reg_t; -typedef uint32_t hri_sercomusart_ctrla_reg_t; -typedef uint32_t hri_sercomusart_ctrlb_reg_t; -typedef uint32_t hri_sercomusart_ctrlc_reg_t; -typedef uint32_t hri_sercomusart_data_reg_t; -typedef uint32_t hri_sercomusart_syncbusy_reg_t; -typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; -typedef uint8_t hri_sercomi2cm_intenset_reg_t; -typedef uint8_t hri_sercomi2cm_intflag_reg_t; -typedef uint8_t hri_sercomi2cs_intenset_reg_t; -typedef uint8_t hri_sercomi2cs_intflag_reg_t; -typedef uint8_t hri_sercomspi_baud_reg_t; -typedef uint8_t hri_sercomspi_dbgctrl_reg_t; -typedef uint8_t hri_sercomspi_intenset_reg_t; -typedef uint8_t hri_sercomspi_intflag_reg_t; -typedef uint8_t hri_sercomusart_dbgctrl_reg_t; -typedef uint8_t hri_sercomusart_intenset_reg_t; -typedef uint8_t hri_sercomusart_intflag_reg_t; -typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; -typedef uint8_t hri_sercomusart_rxpl_reg_t; - -static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTFLAG.reg; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cs_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTFLAG.reg; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; -} - -static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, - hri_sercomspi_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTFLAG.reg; -} - -static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = mask; -} - -static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, - hri_sercomusart_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTFLAG.reg; -} - -static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = mask; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, - hri_sercomi2cm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTENSET.reg; -} - -static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = data; - ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; -} - -static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = mask; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, - hri_sercomi2cs_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTENSET.reg; -} - -static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = data; - ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; -} - -static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; -} - -static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; - } -} - -static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; -} - -static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; - } -} - -static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; - } -} - -static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = mask; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, - hri_sercomspi_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTENSET.reg; -} - -static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = data; - ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; -} - -static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = mask; -} - -static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; -} - -static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; - } -} - -static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; - } -} - -static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; - } -} - -static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENSET.reg = mask; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, - hri_sercomusart_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTENSET.reg; -} - -static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) -{ - ((Sercom *)hw)->USART.INTENSET.reg = data; - ((Sercom *)hw)->USART.INTENCLR.reg = ~data; -} - -static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cs_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, - hri_sercomspi_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, - hri_sercomusart_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, - hri_sercomusart_rxerrcnt_reg_t mask) -{ - uint8_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.RXERRCNT.reg; -} - -static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CM_CTRLA_MODE(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CM_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; - tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->I2CM.CTRLA.reg; -} - -static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CS_CTRLA_MODE(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CS_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg = data; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) -{ - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->I2CS.CTRLA.reg; -} - -static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_ENABLE; - tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_IBON; - tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPHA; - tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPOL; - tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DORD; - tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; - tmp |= SERCOM_SPI_CTRLA_MODE(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DOPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DIPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; - tmp |= SERCOM_SPI_CTRLA_FORM(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->SPI.CTRLA.reg; -} - -static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_ENABLE; - tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_IBON; - tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXINV; - tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXINV; - tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CMODE; - tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CPOL; - tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_DORD; - tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; - tmp |= SERCOM_USART_CTRLA_MODE(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPR(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; - tmp |= SERCOM_USART_CTRLA_TXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; - tmp |= SERCOM_USART_CTRLA_RXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPA(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; - tmp |= SERCOM_USART_CTRLA_FORM(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - return ((Sercom *)hw)->USART.CTRLA.reg; -} - -static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_SMEN; - tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_QCEN; - tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CM_CTRLB_CMD(data); - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.CTRLB.reg; -} - -static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_SMEN; - tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_GCMD; - tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; - tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; - tmp |= SERCOM_I2CS_CTRLB_AMODE(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CS_CTRLB_CMD(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLB.reg; -} - -static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; - tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_SSDE; - tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_MSSEN; - tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_RXEN; - tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; - tmp |= SERCOM_SPI_CTRLB_AMODE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - return ((Sercom *)hw)->SPI.CTRLB.reg; -} - -static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SBMODE; - tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_COLDEN; - tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SFDE; - tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_ENC; - tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_PMODE; - tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_TXEN; - tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_RXEN; - tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_USART_CTRLB_CHSIZE(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; - tmp |= SERCOM_USART_CTRLB_LINCMD(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.CTRLB.reg; -} - -static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; - tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, - hri_sercomi2cm_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLC.reg; -} - -static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; - tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, - hri_sercomi2cs_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; - tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); - ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, - hri_sercomi2cs_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLC.reg; -} - -static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= ~SERCOM_SPI_CTRLC_DATA32B; - tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->SPI.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, - hri_sercomspi_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; - tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); - ((Sercom *)hw)->SPI.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, - hri_sercomspi_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLC.reg; -} - -static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_INACK; - tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DSNACK; - tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; - tmp |= SERCOM_USART_CTRLC_GTIME(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; - tmp |= SERCOM_USART_CTRLC_BRKLEN(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; - tmp |= SERCOM_USART_CTRLC_HDRDLY(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; - tmp |= SERCOM_USART_CTRLC_MAXITER(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; - tmp |= SERCOM_USART_CTRLC_DATA32B(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLC.reg; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.BAUD.reg; -} - -static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; - tmp |= SERCOM_SPI_BAUD_BAUD(data); - ((Sercom *)hw)->SPI.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; - tmp |= SERCOM_USART_RXPL_RXPL(data); - ((Sercom *)hw)->USART.RXPL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXPL.reg; -} - -static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= ~SERCOM_I2CS_LENGTH_LENEN; - tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; - ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomi2cs_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; - tmp |= SERCOM_I2CS_LENGTH_LEN(data); - ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, - hri_sercomi2cs_length_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg = data; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) -{ - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - return ((Sercom *)hw)->I2CS.LENGTH.reg; -} - -static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= ~SERCOM_SPI_LENGTH_LENEN; - tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; - ((Sercom *)hw)->SPI.LENGTH.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomspi_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; - tmp |= SERCOM_SPI_LENGTH_LEN(data); - ((Sercom *)hw)->SPI.LENGTH.reg = tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, - hri_sercomspi_length_reg_t mask) -{ - uint16_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg = data; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) -{ - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - return ((Sercom *)hw)->SPI.LENGTH.reg; -} - -static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; - tmp |= SERCOM_USART_LENGTH_LEN(data); - ((Sercom *)hw)->USART.LENGTH.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; - tmp |= SERCOM_USART_LENGTH_LENEN(data); - ((Sercom *)hw)->USART.LENGTH.reg = tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg = data; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= mask; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) -{ - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - return ((Sercom *)hw)->USART.LENGTH.reg; -} - -static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LENEN; - tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_HS; - tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CM_ADDR_ADDR(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; - tmp |= SERCOM_I2CM_ADDR_LEN(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.ADDR.reg; -} - -static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_GENCEN; - tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDR(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.ADDR.reg; -} - -static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; - tmp |= SERCOM_SPI_ADDR_ADDR(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.ADDR.reg; -} - -static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, - hri_sercomi2cm_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; - tmp |= SERCOM_I2CM_DATA_DATA(data); - ((Sercom *)hw)->I2CM.DATA.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg |= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, - hri_sercomi2cm_data_reg_t mask) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg = data; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg ^= mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.DATA.reg; -} - -static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, - hri_sercomi2cs_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; - tmp |= SERCOM_I2CS_DATA_DATA(data); - ((Sercom *)hw)->I2CS.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, - hri_sercomi2cs_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.DATA.reg; -} - -static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, - hri_sercomspi_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp &= ~SERCOM_SPI_DATA_DATA_Msk; - tmp |= SERCOM_SPI_DATA_DATA(data); - ((Sercom *)hw)->SPI.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DATA.reg; -} - -static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, - hri_sercomusart_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= ~SERCOM_USART_DATA_DATA_Msk; - tmp |= SERCOM_USART_DATA_DATA(data); - ((Sercom *)hw)->USART.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, - hri_sercomusart_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DATA.reg; -} - -static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, - hri_sercomi2cm_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DBGCTRL.reg; -} - -static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, - hri_sercomspi_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DBGCTRL.reg; -} - -static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, - hri_sercomusart_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DBGCTRL.reg; -} - -static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, - hri_sercomi2cs_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.STATUS.reg; -} - -static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, - hri_sercomspi_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.STATUS.reg; -} - -static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, - hri_sercomusart_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.STATUS.reg; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSERR; - tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; - tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_RXNACK; - tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; - tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; - tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LENERR; - tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; - tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - ((Sercom *)hw)->I2CM.STATUS.reg |= mask; -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.STATUS.reg; -} - -static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - ((Sercom *)hw)->I2CM.STATUS.reg = data; -} - -static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; -} - -static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = mask; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) -#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) -#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) -#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) -#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) -#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) -#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) -#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) -#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) -#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) -#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) -#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) -#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) -#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) -#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) -#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) -#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) -#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SERCOM_E54_H_INCLUDED */ -#endif /* _SAME54_SERCOM_COMPONENT_ */ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_E54_H_INCLUDED_ +#define _HRI_SERCOM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_length_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_length_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_length_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cm_data_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cs_data_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_ctrlc_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_data_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, + hri_sercomusart_rxerrcnt_reg_t mask) +{ + uint8_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.RXERRCNT.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXINV; + tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXINV; + tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, + hri_sercomi2cm_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLC.reg; +} + +static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; + tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLC.reg; +} + +static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_DATA32B; + tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; + tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLC.reg; +} + +static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_INACK; + tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DSNACK; + tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; + tmp |= SERCOM_USART_CTRLC_MAXITER(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; + tmp |= SERCOM_USART_CTRLC_DATA32B(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LENEN; + tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; + tmp |= SERCOM_I2CS_LENGTH_LEN(data); + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.LENGTH.reg; +} + +static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LENEN; + tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; + tmp |= SERCOM_SPI_LENGTH_LEN(data); + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.LENGTH.reg; +} + +static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; + tmp |= SERCOM_USART_LENGTH_LEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; + tmp |= SERCOM_USART_LENGTH_LENEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.LENGTH.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_E54_H_INCLUDED */ +#endif /* _SAME54_SERCOM_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_supc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_supc_e54.h index 501c36f..45d4828 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_supc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_supc_e54.h @@ -1,1769 +1,1769 @@ -/** - * \file - * - * \brief SAM SUPC - * - * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_SUPC_COMPONENT_ -#ifndef _HRI_SUPC_E54_H_INCLUDED_ -#define _HRI_SUPC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) -#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SUPC_CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_supc_bbps_reg_t; -typedef uint32_t hri_supc_bkin_reg_t; -typedef uint32_t hri_supc_bkout_reg_t; -typedef uint32_t hri_supc_bod33_reg_t; -typedef uint32_t hri_supc_intenset_reg_t; -typedef uint32_t hri_supc_intflag_reg_t; -typedef uint32_t hri_supc_status_reg_t; -typedef uint32_t hri_supc_vref_reg_t; -typedef uint32_t hri_supc_vreg_reg_t; - -static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) -{ - return ((Supc *)hw)->INTFLAG.reg; -} - -static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - ((Supc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; -} - -static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; -} - -static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; -} - -static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; -} - -static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; -} - -static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; -} - -static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; - } -} - -static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; -} - -static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; -} - -static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; -} - -static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; - } -} - -static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; -} - -static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENSET.reg = mask; -} - -static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) -{ - return ((Supc *)hw)->INTENSET.reg; -} - -static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) -{ - ((Supc *)hw)->INTENSET.reg = data; - ((Supc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; -} - -static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) -{ - return ((Supc *)hw)->STATUS.reg; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKIN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) -{ - return ((Supc *)hw)->BKIN.reg; -} - -static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ENABLE; - tmp |= value << SUPC_BOD33_ENABLE_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_STDBYCFG; - tmp |= value << SUPC_BOD33_STDBYCFG_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNSTDBY; - tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNHIB; - tmp |= value << SUPC_BOD33_RUNHIB_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNBKUP; - tmp |= value << SUPC_BOD33_RUNBKUP_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ACTION_Msk; - tmp |= SUPC_BOD33_ACTION(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_HYST_Msk; - tmp |= SUPC_BOD33_HYST(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_PSEL_Msk; - tmp |= SUPC_BOD33_PSEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_LEVEL_Msk; - tmp |= SUPC_BOD33_LEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; - tmp |= SUPC_BOD33_VBATLEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD33.reg; -} - -static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_ENABLE; - tmp |= value << SUPC_VREG_ENABLE_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_SEL; - tmp |= value << SUPC_VREG_SEL_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_RUNBKUP; - tmp |= value << SUPC_VREG_RUNBKUP_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSEN; - tmp |= value << SUPC_VREG_VSEN_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSPER_Msk; - tmp |= SUPC_VREG_VSPER(data); - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) -{ - return ((Supc *)hw)->VREG.reg; -} - -static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSEN; - tmp |= value << SUPC_VREF_TSEN_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_VREFOE; - tmp |= value << SUPC_VREF_VREFOE_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSSEL; - tmp |= value << SUPC_VREF_TSSEL_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_RUNSTDBY; - tmp |= value << SUPC_VREF_RUNSTDBY_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_ONDEMAND; - tmp |= value << SUPC_VREF_ONDEMAND_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_SEL_Msk; - tmp |= SUPC_VREF_SEL(data); - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) -{ - return ((Supc *)hw)->VREF.reg; -} - -static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_CONF; - tmp |= value << SUPC_BBPS_CONF_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_WAKEEN; - tmp |= value << SUPC_BBPS_WAKEEN_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) -{ - return ((Supc *)hw)->BBPS.reg; -} - -static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_EN_Msk; - tmp |= SUPC_BKOUT_EN(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_CLR_Msk; - tmp |= SUPC_BKOUT_CLR(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_SET_Msk; - tmp |= SUPC_BKOUT_SET(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_RTCTGL_Msk; - tmp |= SUPC_BKOUT_RTCTGL(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) -{ - return ((Supc *)hw)->BKOUT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SUPC_E54_H_INCLUDED */ -#endif /* _SAME54_SUPC_COMPONENT_ */ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_E54_H_INCLUDED_ +#define _HRI_SUPC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNHIB; + tmp |= value << SUPC_BOD33_RUNHIB_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST_Msk; + tmp |= SUPC_BOD33_HYST(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; + tmp |= SUPC_BOD33_VBATLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL; + tmp |= value << SUPC_VREG_SEL_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNBKUP; + tmp |= value << SUPC_VREG_RUNBKUP_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSEN; + tmp |= value << SUPC_VREG_VSEN_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSSEL; + tmp |= value << SUPC_VREF_TSSEL_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF; + tmp |= value << SUPC_BBPS_CONF_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_E54_H_INCLUDED */ +#endif /* _SAME54_SUPC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tc_e54.h index a31cb2c..7db856a 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tc_e54.h @@ -1,3003 +1,3003 @@ -/** - * \file - * - * \brief SAM TC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_TC_COMPONENT_ -#ifndef _HRI_TC_E54_H_INCLUDED_ -#define _HRI_TC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TC_CRITICAL_SECTIONS) -#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TC_CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tc_evctrl_reg_t; -typedef uint16_t hri_tccount16_cc_reg_t; -typedef uint16_t hri_tccount16_ccbuf_reg_t; -typedef uint16_t hri_tccount16_count_reg_t; -typedef uint32_t hri_tc_ctrla_reg_t; -typedef uint32_t hri_tc_syncbusy_reg_t; -typedef uint32_t hri_tccount32_cc_reg_t; -typedef uint32_t hri_tccount32_ccbuf_reg_t; -typedef uint32_t hri_tccount32_count_reg_t; -typedef uint8_t hri_tc_ctrlbset_reg_t; -typedef uint8_t hri_tc_dbgctrl_reg_t; -typedef uint8_t hri_tc_drvctrl_reg_t; -typedef uint8_t hri_tc_intenset_reg_t; -typedef uint8_t hri_tc_intflag_reg_t; -typedef uint8_t hri_tc_status_reg_t; -typedef uint8_t hri_tc_wave_reg_t; -typedef uint8_t hri_tccount8_cc_reg_t; -typedef uint8_t hri_tccount8_ccbuf_reg_t; -typedef uint8_t hri_tccount8_count_reg_t; -typedef uint8_t hri_tccount8_per_reg_t; -typedef uint8_t hri_tccount8_perbuf_reg_t; - -static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; -} - -static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.INTFLAG.reg; -} - -static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; -} - -static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; -} - -static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; - } -} - -static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; -} - -static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; -} - -static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; - } -} - -static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; -} - -static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; - } else { - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; -} - -static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); -} - -static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); -} - -static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.CTRLBSET.reg; -} - -static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; -} - -static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; -} - -static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; -} - -static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; -} - -static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; - } -} - -static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; -} - -static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; -} - -static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; -} - -static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; - } -} - -static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; -} - -static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; -} - -static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; -} - -static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; - } -} - -static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; -} - -static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; -} - -static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; -} - -static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; - } else { - ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; - } -} - -static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; -} - -static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = mask; -} - -static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.INTENSET.reg; -} - -static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) -{ - ((Tc *)hw)->COUNT16.INTENSET.reg = data; - ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; -} - -static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; -} - -static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; -} - -static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ENABLE; - tmp |= value << TC_CTRLA_ENABLE_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_RUNSTDBY; - tmp |= value << TC_CTRLA_RUNSTDBY_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ONDEMAND; - tmp |= value << TC_CTRLA_ONDEMAND_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_ALOCK; - tmp |= value << TC_CTRLA_ALOCK_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN0; - tmp |= value << TC_CTRLA_CAPTEN0_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN1; - tmp |= value << TC_CTRLA_CAPTEN1_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN0; - tmp |= value << TC_CTRLA_COPEN0_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN1; - tmp |= value << TC_CTRLA_COPEN1_Pos; - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_MODE_Msk; - tmp |= TC_CTRLA_MODE(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCSYNC_Msk; - tmp |= TC_CTRLA_PRESCSYNC(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCALER_Msk; - tmp |= TC_CTRLA_PRESCALER(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTMODE0_Msk; - tmp |= TC_CTRLA_CAPTMODE0(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTMODE1_Msk; - tmp |= TC_CTRLA_CAPTMODE1(data); - ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - return ((Tc *)hw)->COUNT16.CTRLA.reg; -} - -static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCINV; - tmp |= value << TC_EVCTRL_TCINV_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCEI; - tmp |= value << TC_EVCTRL_TCEI_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_OVFEO; - tmp |= value << TC_EVCTRL_OVFEO_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO0; - tmp |= value << TC_EVCTRL_MCEO0_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO1; - tmp |= value << TC_EVCTRL_MCEO1_Pos; - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= ~TC_EVCTRL_EVACT_Msk; - tmp |= TC_EVCTRL_EVACT(data); - ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.EVCTRL.reg; -} - -static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp &= ~TC_WAVE_WAVEGEN_Msk; - tmp |= TC_WAVE_WAVEGEN(data); - ((Tc *)hw)->COUNT16.WAVE.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.WAVE.reg; -} - -static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN0; - tmp |= value << TC_DRVCTRL_INVEN0_Pos; - ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN1; - tmp |= value << TC_DRVCTRL_INVEN1_Pos; - ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.DRVCTRL.reg; -} - -static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp &= ~TC_DBGCTRL_DBGRUN; - tmp |= value << TC_DBGCTRL_DBGRUN_Pos; - ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.DBGCTRL.reg; -} - -static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount8_count_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; - tmp |= TC_COUNT8_COUNT_COUNT(data); - ((Tc *)hw)->COUNT8.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT8.COUNT.reg; -} - -static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount16_count_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; - tmp |= TC_COUNT16_COUNT_COUNT(data); - ((Tc *)hw)->COUNT16.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, - hri_tccount16_count_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT16.COUNT.reg; -} - -static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, - hri_tccount32_count_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; - tmp |= TC_COUNT32_COUNT_COUNT(data); - ((Tc *)hw)->COUNT32.COUNT.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, - hri_tccount32_count_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - return ((Tc *)hw)->COUNT32.COUNT.reg; -} - -static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= ~TC_COUNT8_PER_PER_Msk; - tmp |= TC_COUNT8_PER_PER(data); - ((Tc *)hw)->COUNT8.PER.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - return ((Tc *)hw)->COUNT8.PER.reg; -} - -static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount8_cc_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= ~TC_COUNT8_CC_CC_Msk; - tmp |= TC_COUNT8_CC_CC(data); - ((Tc *)hw)->COUNT8.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount8_cc_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT8.CC[index].reg; -} - -static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount16_cc_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= ~TC_COUNT16_CC_CC_Msk; - tmp |= TC_COUNT16_CC_CC(data); - ((Tc *)hw)->COUNT16.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount16_cc_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT16.CC[index].reg; -} - -static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, - hri_tccount32_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= ~TC_COUNT32_CC_CC_Msk; - tmp |= TC_COUNT32_CC_CC(data); - ((Tc *)hw)->COUNT32.CC[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, - hri_tccount32_cc_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); - return ((Tc *)hw)->COUNT32.CC[index].reg; -} - -static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, - hri_tccount8_perbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; - tmp |= TC_COUNT8_PERBUF_PERBUF(data); - ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, - hri_tccount8_perbuf_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT8.PERBUF.reg; -} - -static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT8_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount8_ccbuf_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT8.CCBUF[index].reg; -} - -static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT16_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount16_ccbuf_reg_t mask) -{ - uint16_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT16.CCBUF[index].reg; -} - -static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT32_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tccount32_ccbuf_reg_t mask) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT32.CCBUF[index].reg; -} - -static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; -} - -static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; -} - -static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT16.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.STATUS.reg = mask; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return ((Tc *)hw)->COUNT16.STATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) -#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) -#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) -#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) -#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) -#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) -#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) -#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) -#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) -#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) -#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) -#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) -#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) -#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) -#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) -#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) -#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) -#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) -#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) -#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) -#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) -#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) -#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) -#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TC_E54_H_INCLUDED */ -#endif /* _SAME54_TC_COMPONENT_ */ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TC_COMPONENT_ +#ifndef _HRI_TC_E54_H_INCLUDED_ +#define _HRI_TC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE0_Msk; + tmp |= TC_CTRLA_CAPTMODE0(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE1_Msk; + tmp |= TC_CTRLA_CAPTMODE1(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_E54_H_INCLUDED */ +#endif /* _SAME54_TC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tcc_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tcc_e54.h index 55f46bd..6ab48e2 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tcc_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_tcc_e54.h @@ -1,9992 +1,9992 @@ -/** - * \file - * - * \brief SAM TCC - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_TCC_COMPONENT_ -#ifndef _HRI_TCC_E54_H_INCLUDED_ -#define _HRI_TCC_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TCC_CRITICAL_SECTIONS) -#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TCC_CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tcc_patt_reg_t; -typedef uint16_t hri_tcc_pattbuf_reg_t; -typedef uint32_t hri_tcc_cc_reg_t; -typedef uint32_t hri_tcc_ccbuf_reg_t; -typedef uint32_t hri_tcc_count_reg_t; -typedef uint32_t hri_tcc_ctrla_reg_t; -typedef uint32_t hri_tcc_drvctrl_reg_t; -typedef uint32_t hri_tcc_evctrl_reg_t; -typedef uint32_t hri_tcc_fctrla_reg_t; -typedef uint32_t hri_tcc_fctrlb_reg_t; -typedef uint32_t hri_tcc_intenset_reg_t; -typedef uint32_t hri_tcc_intflag_reg_t; -typedef uint32_t hri_tcc_per_reg_t; -typedef uint32_t hri_tcc_perbuf_reg_t; -typedef uint32_t hri_tcc_status_reg_t; -typedef uint32_t hri_tcc_syncbusy_reg_t; -typedef uint32_t hri_tcc_wave_reg_t; -typedef uint32_t hri_tcc_wexctrl_reg_t; -typedef uint8_t hri_tcc_ctrlbset_reg_t; -typedef uint8_t hri_tcc_dbgctrl_reg_t; - -static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - while (((Tcc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - return ((Tcc *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; -} - -static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; -} - -static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; -} - -static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTFLAG.reg; -} - -static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - ((Tcc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; -} - -static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; -} - -static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; - } -} - -static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; -} - -static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); -} - -static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); -} - -static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLBSET.reg; -} - -static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = data; - ((Tcc *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; -} - -static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; -} - -static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; - } -} - -static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; -} - -static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; -} - -static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; -} - -static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; - } -} - -static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; -} - -static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; -} - -static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; -} - -static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; - } -} - -static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; -} - -static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; -} - -static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; -} - -static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; - } -} - -static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; -} - -static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; -} - -static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; -} - -static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; - } -} - -static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; -} - -static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; -} - -static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; -} - -static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; - } -} - -static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; -} - -static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; -} - -static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; -} - -static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; -} - -static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; -} - -static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; -} - -static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; -} - -static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; -} - -static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; -} - -static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; -} - -static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; -} - -static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; - } -} - -static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; -} - -static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; -} - -static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; -} - -static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; - } -} - -static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; -} - -static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; -} - -static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; -} - -static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; - } -} - -static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; -} - -static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; -} - -static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; -} - -static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; - } -} - -static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; -} - -static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; -} - -static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; -} - -static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; - } -} - -static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; -} - -static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; -} - -static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; -} - -static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; - } -} - -static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; -} - -static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENSET.reg = mask; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTENSET.reg; -} - -static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) -{ - ((Tcc *)hw)->INTENSET.reg = data; - ((Tcc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tcc *)hw)->SYNCBUSY.reg; -} - -static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ENABLE; - tmp |= value << TCC_CTRLA_ENABLE_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RUNSTDBY; - tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ALOCK; - tmp |= value << TCC_CTRLA_ALOCK_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_MSYNC; - tmp |= value << TCC_CTRLA_MSYNC_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_DMAOS; - tmp |= value << TCC_CTRLA_DMAOS_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN0; - tmp |= value << TCC_CTRLA_CPTEN0_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN1; - tmp |= value << TCC_CTRLA_CPTEN1_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN2; - tmp |= value << TCC_CTRLA_CPTEN2_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN3; - tmp |= value << TCC_CTRLA_CPTEN3_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN4; - tmp |= value << TCC_CTRLA_CPTEN4_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN5; - tmp |= value << TCC_CTRLA_CPTEN5_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RESOLUTION_Msk; - tmp |= TCC_CTRLA_RESOLUTION(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCALER_Msk; - tmp |= TCC_CTRLA_PRESCALER(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; - tmp |= TCC_CTRLA_PRESCSYNC(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - return ((Tcc *)hw)->CTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_KEEP; - tmp |= value << TCC_FCTRLA_KEEP_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_QUAL; - tmp |= value << TCC_FCTRLA_QUAL_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_RESTART; - tmp |= value << TCC_FCTRLA_RESTART_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKPRESC; - tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_SRC_Msk; - tmp |= TCC_FCTRLA_SRC(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANK_Msk; - tmp |= TCC_FCTRLA_BLANK(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_HALT_Msk; - tmp |= TCC_FCTRLA_HALT(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CHSEL_Msk; - tmp |= TCC_FCTRLA_CHSEL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CAPTURE_Msk; - tmp |= TCC_FCTRLA_CAPTURE(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; - tmp |= TCC_FCTRLA_BLANKVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; - tmp |= TCC_FCTRLA_FILTERVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_KEEP; - tmp |= value << TCC_FCTRLB_KEEP_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_QUAL; - tmp |= value << TCC_FCTRLB_QUAL_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_RESTART; - tmp |= value << TCC_FCTRLB_RESTART_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKPRESC; - tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_SRC_Msk; - tmp |= TCC_FCTRLB_SRC(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANK_Msk; - tmp |= TCC_FCTRLB_BLANK(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_HALT_Msk; - tmp |= TCC_FCTRLB_HALT(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CHSEL_Msk; - tmp |= TCC_FCTRLB_CHSEL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CAPTURE_Msk; - tmp |= TCC_FCTRLB_CAPTURE(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; - tmp |= TCC_FCTRLB_BLANKVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; - tmp |= TCC_FCTRLB_FILTERVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLB.reg; -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN0; - tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN1; - tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN2; - tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN3; - tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_OTMX_Msk; - tmp |= TCC_WEXCTRL_OTMX(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTLS_Msk; - tmp |= TCC_WEXCTRL_DTLS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTHS_Msk; - tmp |= TCC_WEXCTRL_DTHS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->WEXCTRL.reg; -} - -static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE0; - tmp |= value << TCC_DRVCTRL_NRE0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE1; - tmp |= value << TCC_DRVCTRL_NRE1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE2; - tmp |= value << TCC_DRVCTRL_NRE2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE3; - tmp |= value << TCC_DRVCTRL_NRE3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE4; - tmp |= value << TCC_DRVCTRL_NRE4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE5; - tmp |= value << TCC_DRVCTRL_NRE5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE6; - tmp |= value << TCC_DRVCTRL_NRE6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE7; - tmp |= value << TCC_DRVCTRL_NRE7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV0; - tmp |= value << TCC_DRVCTRL_NRV0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV1; - tmp |= value << TCC_DRVCTRL_NRV1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV2; - tmp |= value << TCC_DRVCTRL_NRV2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV3; - tmp |= value << TCC_DRVCTRL_NRV3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV4; - tmp |= value << TCC_DRVCTRL_NRV4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV5; - tmp |= value << TCC_DRVCTRL_NRV5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV6; - tmp |= value << TCC_DRVCTRL_NRV6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV7; - tmp |= value << TCC_DRVCTRL_NRV7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN0; - tmp |= value << TCC_DRVCTRL_INVEN0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN1; - tmp |= value << TCC_DRVCTRL_INVEN1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN2; - tmp |= value << TCC_DRVCTRL_INVEN2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN3; - tmp |= value << TCC_DRVCTRL_INVEN3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN4; - tmp |= value << TCC_DRVCTRL_INVEN4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN5; - tmp |= value << TCC_DRVCTRL_INVEN5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN6; - tmp |= value << TCC_DRVCTRL_INVEN6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN7; - tmp |= value << TCC_DRVCTRL_INVEN7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL0(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL1(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DRVCTRL.reg; -} - -static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_DBGRUN; - tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_FDDBD; - tmp |= value << TCC_DBGCTRL_FDDBD_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DBGCTRL.reg; -} - -static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_OVFEO; - tmp |= value << TCC_EVCTRL_OVFEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TRGEO; - tmp |= value << TCC_EVCTRL_TRGEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTEO; - tmp |= value << TCC_EVCTRL_CNTEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV0; - tmp |= value << TCC_EVCTRL_TCINV0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV1; - tmp |= value << TCC_EVCTRL_TCINV1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI0; - tmp |= value << TCC_EVCTRL_TCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI1; - tmp |= value << TCC_EVCTRL_TCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI0; - tmp |= value << TCC_EVCTRL_MCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI1; - tmp |= value << TCC_EVCTRL_MCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI2; - tmp |= value << TCC_EVCTRL_MCEI2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI3; - tmp |= value << TCC_EVCTRL_MCEI3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI4; - tmp |= value << TCC_EVCTRL_MCEI4_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI5; - tmp |= value << TCC_EVCTRL_MCEI5_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO0; - tmp |= value << TCC_EVCTRL_MCEO0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO1; - tmp |= value << TCC_EVCTRL_MCEO1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO2; - tmp |= value << TCC_EVCTRL_MCEO2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO3; - tmp |= value << TCC_EVCTRL_MCEO3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO4; - tmp |= value << TCC_EVCTRL_MCEO4_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO5; - tmp |= value << TCC_EVCTRL_MCEO5_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT0_Msk; - tmp |= TCC_EVCTRL_EVACT0(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT1_Msk; - tmp |= TCC_EVCTRL_EVACT1(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTSEL_Msk; - tmp |= TCC_EVCTRL_CNTSEL(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->EVCTRL.reg; -} - -static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE0; - tmp |= value << TCC_PATT_PGE0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE1; - tmp |= value << TCC_PATT_PGE1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE2; - tmp |= value << TCC_PATT_PGE2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE3; - tmp |= value << TCC_PATT_PGE3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE4; - tmp |= value << TCC_PATT_PGE4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE5; - tmp |= value << TCC_PATT_PGE5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE6; - tmp |= value << TCC_PATT_PGE6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE7; - tmp |= value << TCC_PATT_PGE7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV0; - tmp |= value << TCC_PATT_PGV0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV1; - tmp |= value << TCC_PATT_PGV1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV2; - tmp |= value << TCC_PATT_PGV2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV3; - tmp |= value << TCC_PATT_PGV3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV4; - tmp |= value << TCC_PATT_PGV4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV5; - tmp |= value << TCC_PATT_PGV5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV6; - tmp |= value << TCC_PATT_PGV6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV7; - tmp |= value << TCC_PATT_PGV7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - uint16_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->PATT.reg; -} - -static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CIPEREN; - tmp |= value << TCC_WAVE_CIPEREN_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN0; - tmp |= value << TCC_WAVE_CICCEN0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN1; - tmp |= value << TCC_WAVE_CICCEN1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN2; - tmp |= value << TCC_WAVE_CICCEN2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN3; - tmp |= value << TCC_WAVE_CICCEN3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL0; - tmp |= value << TCC_WAVE_POL0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL1; - tmp |= value << TCC_WAVE_POL1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL2; - tmp |= value << TCC_WAVE_POL2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL3; - tmp |= value << TCC_WAVE_POL3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL4; - tmp |= value << TCC_WAVE_POL4_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL5; - tmp |= value << TCC_WAVE_POL5_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP0; - tmp |= value << TCC_WAVE_SWAP0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP1; - tmp |= value << TCC_WAVE_SWAP1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP2; - tmp |= value << TCC_WAVE_SWAP2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP3; - tmp |= value << TCC_WAVE_SWAP3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_WAVEGEN_Msk; - tmp |= TCC_WAVE_WAVEGEN(data); - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_RAMP_Msk; - tmp |= TCC_WAVE_RAMP(data); - ((Tcc *)hw)->WAVE.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->WAVE.reg; -} - -static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_DITHER_Msk; - tmp |= TCC_PER_DITH4_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_DITHER_Msk; - tmp |= TCC_PER_DITH5_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_DITHER_Msk; - tmp |= TCC_PER_DITH6_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_DITHER_Msk; - tmp |= TCC_CC_DITH4_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_DITHER_Msk; - tmp |= TCC_CC_DITH5_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_DITHER_Msk; - tmp |= TCC_CC_DITH6_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) -{ - hri_tcc_wait_for_sync(hw, - TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 - | TCC_SYNCBUSY_CC5); - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB0; - tmp |= value << TCC_PATTBUF_PGEB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB1; - tmp |= value << TCC_PATTBUF_PGEB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB2; - tmp |= value << TCC_PATTBUF_PGEB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB3; - tmp |= value << TCC_PATTBUF_PGEB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB4; - tmp |= value << TCC_PATTBUF_PGEB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB5; - tmp |= value << TCC_PATTBUF_PGEB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB6; - tmp |= value << TCC_PATTBUF_PGEB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB7; - tmp |= value << TCC_PATTBUF_PGEB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB0; - tmp |= value << TCC_PATTBUF_PGVB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB1; - tmp |= value << TCC_PATTBUF_PGVB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB2; - tmp |= value << TCC_PATTBUF_PGVB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB3; - tmp |= value << TCC_PATTBUF_PGVB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB4; - tmp |= value << TCC_PATTBUF_PGVB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB5; - tmp |= value << TCC_PATTBUF_PGVB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB6; - tmp |= value << TCC_PATTBUF_PGVB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB7; - tmp |= value << TCC_PATTBUF_PGVB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATTBUF.reg; -} - -static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; -} - -static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; -} - -static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; -} - -static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = mask; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) -{ - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - return ((Tcc *)hw)->STATUS.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) -#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) -#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) -#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) -#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) -#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) -#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) -#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) -#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) -#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) -#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) -#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) -#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) -#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) -#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) -#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) -#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) -#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) -#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) -#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) -#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) -#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) -#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) -#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) -#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) -#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) -#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) -#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) -#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) -#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) -#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) -#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TCC_E54_H_INCLUDED */ -#endif /* _SAME54_TCC_COMPONENT_ */ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TCC_COMPONENT_ +#ifndef _HRI_TCC_E54_H_INCLUDED_ +#define _HRI_TCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; +} + +static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; +} + +static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; + } +} + +static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; +} + +static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; +} + +static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; +} + +static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; + } +} + +static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN4; + tmp |= value << TCC_CTRLA_CPTEN4_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN5; + tmp |= value << TCC_CTRLA_CPTEN5_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI4; + tmp |= value << TCC_EVCTRL_MCEI4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI5; + tmp |= value << TCC_EVCTRL_MCEI5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO4; + tmp |= value << TCC_EVCTRL_MCEO4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO5; + tmp |= value << TCC_EVCTRL_MCEO5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL4; + tmp |= value << TCC_WAVE_POL4_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL5; + tmp |= value << TCC_WAVE_POL5_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_E54_H_INCLUDED */ +#endif /* _SAME54_TCC_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_trng_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_trng_e54.h index e42caab..e57352a 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_trng_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_trng_e54.h @@ -1,380 +1,380 @@ -/** - * \file - * - * \brief SAM TRNG - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_TRNG_COMPONENT_ -#ifndef _HRI_TRNG_E54_H_INCLUDED_ -#define _HRI_TRNG_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) -#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TRNG_CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_trng_data_reg_t; -typedef uint8_t hri_trng_ctrla_reg_t; -typedef uint8_t hri_trng_evctrl_reg_t; -typedef uint8_t hri_trng_intenset_reg_t; -typedef uint8_t hri_trng_intflag_reg_t; - -static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) -{ - return ((Trng *)hw)->INTFLAG.reg; -} - -static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - ((Trng *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; -} - -static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; -} - -static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; - } else { - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; - } -} - -static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; -} - -static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENSET.reg = mask; -} - -static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) -{ - return ((Trng *)hw)->INTENSET.reg; -} - -static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) -{ - ((Trng *)hw)->INTENSET.reg = data; - ((Trng *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENCLR.reg = mask; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Trng *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) -{ - return ((Trng *)hw)->DATA.reg; -} - -static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_ENABLE; - tmp |= value << TRNG_CTRLA_ENABLE_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_RUNSTDBY; - tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) -{ - return ((Trng *)hw)->CTRLA.reg; -} - -static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= ~TRNG_EVCTRL_DATARDYEO; - tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; - ((Trng *)hw)->EVCTRL.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) -{ - return ((Trng *)hw)->EVCTRL.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TRNG_E54_H_INCLUDED */ -#endif /* _SAME54_TRNG_COMPONENT_ */ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_E54_H_INCLUDED_ +#define _HRI_TRNG_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_E54_H_INCLUDED */ +#endif /* _SAME54_TRNG_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_usb_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_usb_e54.h index 34b5e02..7a8bff1 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_usb_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_usb_e54.h @@ -1,9335 +1,9335 @@ -/** - * \file - * - * \brief SAM USB - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_USB_COMPONENT_ -#ifndef _HRI_USB_E54_H_INCLUDED_ -#define _HRI_USB_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_USB_CRITICAL_SECTIONS) -#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define USB_CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_usb_padcal_reg_t; -typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; -typedef uint16_t hri_usbdesc_bank_extreg_reg_t; -typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; -typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; -typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; -typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; -typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; -typedef uint16_t hri_usbdevice_ctrlb_reg_t; -typedef uint16_t hri_usbdevice_epintsmry_reg_t; -typedef uint16_t hri_usbdevice_fnum_reg_t; -typedef uint16_t hri_usbdevice_intenset_reg_t; -typedef uint16_t hri_usbdevice_intflag_reg_t; -typedef uint16_t hri_usbhost_ctrlb_reg_t; -typedef uint16_t hri_usbhost_fnum_reg_t; -typedef uint16_t hri_usbhost_intenset_reg_t; -typedef uint16_t hri_usbhost_intflag_reg_t; -typedef uint16_t hri_usbhost_pintsmry_reg_t; -typedef uint32_t hri_usb_descadd_reg_t; -typedef uint32_t hri_usbdesc_bank_addr_reg_t; -typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; -typedef uint32_t hri_usbdescriptordevice_addr_reg_t; -typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; -typedef uint32_t hri_usbdescriptorhost_addr_reg_t; -typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; -typedef uint8_t hri_usb_ctrla_reg_t; -typedef uint8_t hri_usb_fsmstatus_reg_t; -typedef uint8_t hri_usb_qosctrl_reg_t; -typedef uint8_t hri_usb_syncbusy_reg_t; -typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; -typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; -typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; -typedef uint8_t hri_usbdevice_dadd_reg_t; -typedef uint8_t hri_usbdevice_epcfg_reg_t; -typedef uint8_t hri_usbdevice_epintenset_reg_t; -typedef uint8_t hri_usbdevice_epintflag_reg_t; -typedef uint8_t hri_usbdevice_epstatus_reg_t; -typedef uint8_t hri_usbdevice_status_reg_t; -typedef uint8_t hri_usbendpoint_epcfg_reg_t; -typedef uint8_t hri_usbendpoint_epintenset_reg_t; -typedef uint8_t hri_usbendpoint_epintflag_reg_t; -typedef uint8_t hri_usbendpoint_epstatus_reg_t; -typedef uint8_t hri_usbhost_binterval_reg_t; -typedef uint8_t hri_usbhost_flenhigh_reg_t; -typedef uint8_t hri_usbhost_hsofc_reg_t; -typedef uint8_t hri_usbhost_pcfg_reg_t; -typedef uint8_t hri_usbhost_pintenset_reg_t; -typedef uint8_t hri_usbhost_pintflag_reg_t; -typedef uint8_t hri_usbhost_pstatus_reg_t; -typedef uint8_t hri_usbhost_status_reg_t; -typedef uint8_t hri_usbpipe_binterval_reg_t; -typedef uint8_t hri_usbpipe_pcfg_reg_t; -typedef uint8_t hri_usbpipe_pintenset_reg_t; -typedef uint8_t hri_usbpipe_pintflag_reg_t; -typedef uint8_t hri_usbpipe_pstatus_reg_t; - -static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->EXTREG.reg; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_BK.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; -} - -static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t -hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t -hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) - >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) - >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_bk_reg_t -hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) - >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) - >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) - >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptorhost_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptorhost_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbendpoint_epintflag_reg_t -hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintflag_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbendpoint_epstatus_reg_t -hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbendpoint_epintenset_reg_t -hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbdevice_epintflag_reg_t -hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbdevice_epintenset_reg_t -hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, - hri_usbdevice_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTFLAG.reg; -} - -static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; -} - -static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, - hri_usbhost_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTFLAG.reg; -} - -static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; - } -} - -static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; - } -} - -static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; - } -} - -static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = mask; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, - hri_usbdevice_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTENSET.reg; -} - -static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = data; - ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; -} - -static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; -} - -static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; -} - -static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; - } -} - -static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; -} - -static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; -} - -static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; -} - -static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; - } -} - -static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; -} - -static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; - } -} - -static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; - } -} - -static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; -} - -static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; -} - -static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; - } -} - -static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; -} - -static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; -} - -static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; -} - -static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; - } -} - -static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; -} - -static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENSET.reg = mask; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, - hri_usbhost_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTENSET.reg; -} - -static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) -{ - ((Usb *)hw)->HOST.INTENSET.reg = data; - ((Usb *)hw)->HOST.INTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = mask; -} - -static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.SYNCBUSY.reg; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.STATUS.reg; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usb_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FSMSTATUS.reg; -} - -static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FNUM.reg; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FLENHIGH.reg; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, - hri_usbdevice_epintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, - hri_usbhost_pintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PINTSMRY.reg; -} - -static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg = data; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= mask; - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) -{ - hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); - return ((Usb *)hw)->HOST.CTRLA.reg; -} - -static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.QOSCTRL.reg; -} - -static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_DETACH; - tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_UPRSM; - tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_NREPLY; - tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTJ; - tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTK; - tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; - tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_OPMODE2; - tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_GNAK; - tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; - tmp |= USB_DEVICE_CTRLB_SPDCONF(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; - tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLB.reg; -} - -static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_RESUME; - tmp |= value << USB_HOST_CTRLB_RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_AUTORESUME; - tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTJ; - tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTK; - tmp |= value << USB_HOST_CTRLB_TSTK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SOFE; - tmp |= value << USB_HOST_CTRLB_SOFE_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_BUSRESET; - tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_VBUSOK; - tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_L1RESUME; - tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; - tmp |= USB_HOST_CTRLB_SPDCONF(data); - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.CTRLB.reg; -} - -static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_ADDEN; - tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, - hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_DADD_Msk; - tmp |= USB_DEVICE_DADD_DADD(data); - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DADD.reg; -} - -static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENCE; - tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENC_Msk; - tmp |= USB_HOST_HSOFC_FLENC(data); - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.HSOFC.reg; -} - -static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_MFNUM_Msk; - tmp |= USB_HOST_FNUM_MFNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_FNUM_Msk; - tmp |= USB_HOST_FNUM_FNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FNUM.reg; -} - -static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->HOST.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.DESCADD.reg; -} - -static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PADCAL.reg; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.STATUS.reg; -} - -static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->EXTREG.reg; -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, - hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void -hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) - >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_status_bk_reg_t -hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdescriptordevice_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdescriptordevice_status_bk_reg_t -hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; -} - -/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ -#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) -#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) -#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) -#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) -#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) -#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) -#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) -#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) -#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) -#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) -#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) -#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) -#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) -#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) -#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) -#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) -#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) -#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) -#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) -#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) -#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) -#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) -#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) -#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) -#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) -#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) -#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) -#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) -#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) -#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) -#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) -#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) -#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) -#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) -#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) -#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) -#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) -#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) -#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) -#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) -#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) -#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) -#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) -#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) -#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) -#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) -#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) -#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) -#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) -#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) -#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) -#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) -#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) -#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) -#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) -#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) -#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) -#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) -#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) -#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) -#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) -#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) -#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) -#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) -#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) -#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) -#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) -#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) -#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) -#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) -#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) -#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) -#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) -#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) -#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) -#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) -#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) -#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) -#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) -#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) -#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) -#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) -#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) -#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) -#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) -#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) -#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) -#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) -#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) -#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) -#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) -#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) -#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) -#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) -#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) -#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) -#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) -#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) -#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) -#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) -#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) -#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) -#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) -#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) -#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) -#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) -#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) -#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) -#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) -#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) -#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) -#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) -#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) -#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) -#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_USB_E54_H_INCLUDED */ -#endif /* _SAME54_USB_COMPONENT_ */ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_USB_COMPONENT_ +#ifndef _HRI_USB_E54_H_INCLUDED_ +#define _HRI_USB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint32_t hri_usbdescriptorhost_addr_reg_t; +typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_E54_H_INCLUDED */ +#endif /* _SAME54_USB_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_wdt_e54.h b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_wdt_e54.h index 3549e2f..26f835e 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_wdt_e54.h +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/hri/hri_wdt_e54.h @@ -1,617 +1,617 @@ -/** - * \file - * - * \brief SAM WDT - * - * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. - * - * \asf_license_start - * - * \page License - * - * Subject to your compliance with these terms, you may use Microchip - * software and any derivatives exclusively with Microchip products. - * It is your responsibility to comply with third party license terms applicable - * to your use of third party software (including open source software) that - * may accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, - * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, - * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, - * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE - * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE - * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE - * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY - * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, - * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - * \asf_license_stop - * - */ - -#ifdef _SAME54_WDT_COMPONENT_ -#ifndef _HRI_WDT_E54_H_INCLUDED_ -#define _HRI_WDT_E54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_WDT_CRITICAL_SECTIONS) -#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define WDT_CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_wdt_syncbusy_reg_t; -typedef uint8_t hri_wdt_clear_reg_t; -typedef uint8_t hri_wdt_config_reg_t; -typedef uint8_t hri_wdt_ctrla_reg_t; -typedef uint8_t hri_wdt_ewctrl_reg_t; -typedef uint8_t hri_wdt_intenset_reg_t; -typedef uint8_t hri_wdt_intflag_reg_t; - -static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - while (((Wdt *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - return ((Wdt *)hw)->SYNCBUSY.reg & reg; -} - -static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTFLAG.reg; -} - -static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - ((Wdt *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; -} - -static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; -} - -static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; - } else { - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; - } -} - -static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; -} - -static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENSET.reg = mask; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTENSET.reg; -} - -static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) -{ - ((Wdt *)hw)->INTENSET.reg = data; - ((Wdt *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Wdt *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Wdt *)hw)->SYNCBUSY.reg; -} - -static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ENABLE; - tmp |= value << WDT_CTRLA_ENABLE_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_WEN; - tmp |= value << WDT_CTRLA_WEN_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ALWAYSON; - tmp |= value << WDT_CTRLA_ALWAYSON_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg = data; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= mask; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) -{ - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - return ((Wdt *)hw)->CTRLA.reg; -} - -static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_PER_Msk; - tmp |= WDT_CONFIG_PER(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_WINDOW_Msk; - tmp |= WDT_CONFIG_WINDOW(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) -{ - return ((Wdt *)hw)->CONFIG.reg; -} - -static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; - tmp |= WDT_EWCTRL_EWOFFSET(data); - ((Wdt *)hw)->EWCTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) -{ - return ((Wdt *)hw)->EWCTRL.reg; -} - -static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CLEAR.reg = data; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); - WDT_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_WDT_E54_H_INCLUDED */ -#endif /* _SAME54_WDT_COMPONENT_ */ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_WDT_COMPONENT_ +#ifndef _HRI_WDT_E54_H_INCLUDED_ +#define _HRI_WDT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_E54_H_INCLUDED */ +#endif /* _SAME54_WDT_COMPONENT_ */ diff --git a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/main.c b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/main.c index 4d12c56..4a4fba3 100644 --- a/software/firmware/project_oracle_test_prj/project_oracle_test_prj/main.c +++ b/software/firmware/project_oracle_test_prj/project_oracle_test_prj/main.c @@ -1,6 +1,6 @@ -#include - -int main(void) -{ - proj_init(); -} +#include + +int main(void) +{ + proj_init(); +}